iCEcube2 Tutorial
Contents
1. TAL Script Messages Figure 2 6 Synplify Pro Graphical User Interface Hit the Run Button to synthesis your design Once synthesis is complete you will see a Done message See Figure 2 7 iCecube2 Tutorial www SiliconBlueTech com 12 e Silicon ie Technologies Synplify Pro D 2009 125 Early Access 2 C SbtTools examples blinky quick start quick start syn prj ld DE Fle Edt View Project Pun Analysis HOL Analyst Options Window Tech Support Web Help mae CERES IE A 4 9 o R ERE amp EJ pjaa py quick start Jmpkant Son Bue KEES CEGSUM y CR204 Implementation Directory B MS quick start syn C SbtTocisjexamples blink qal start quick_start_syr C SbtTools examples blinky quick_start quick_start_impinnt B quick_start fse quick_start htm B quick start scf quick start srd quick start srl d quick start srm quick start srr 8 quick start srs quick start szr B quick start tg M quick start prepass srd isl Information U oo 9d m ow SBTiCE65 Mapper Completed with varnings Return Code 1 Completion Time 12 37 50 gt TQ Script Messages Figure 2 7 Status showing synthesis has been completed View Timing Constraints Double Click on the blinky_syn sdc file under the Constraint folder See Figure 2 8 It will open the timing constraints for the project shown in Figure 2 9 13 www SiliconBlueTech com iCecu2. Right Bank IO Voltage V 2 5 Power Consumption Static Power mW 0 013 Top Bank IO Voltage V 2 5 Dynamic Power rmWwW 3 30151 Bottom Bank IO VolEage V 25 Total Power mW 3 31451 Reset All Calculate Figure 2 23 Power Estimator Programming the Device In order to program a device you will need to generate a programming file In the project navigator double click on Bitmap You are now ready to program an iCE65 mobileFPGA deice with the generated bitmap Invoke the programmer from the Programming icon which is now enabled in the Project Navigator Alternately you may invoke it from the Tool gt Programmer menu item The iCEman65 Evaluation Kit Board includes an on board USB 2 0 programming solution to program the on board SPI serial Flash or the iCE65 device directly In a future iCEcube release the utility will also support direct programming of the iCE65 device although this is not currently supported Additional details on programming a device are provided in a separate section Programming the Device in Chapter 5 iCEcube Physical Implementation Tools iCecube2 Tutorial www SiliconBlueTech com 26 Silicon I Technologies S Programmer Programming Options Programming Hardware Eval Board Digilent USB Cable DCabUsb Digilent USB Cable CCabUsb Digilent USB Cable BCabLisb iCE Cable im25p80 a Image Image Type Single Image Image File
3. SB LUT4 amp Device Operating Condition E M Divider to 1Hz un SB CARRY 3 Device Info gg DIVIDE 32MHe un SB LUT4 DeviceFamily iCE65 lox S Device LO4 j Device Package CB284 p Power Grade L 4 Operating Condition Core Voltage V 1 14 Temperature C 70 C3 13 mm 1 ewam s E Ti PM m i TE FT TP LL ETa rro rra n a ABE n amp we iy es e FRE B EE je i d 4 ke Ed ka a lor lo ite wI po an rm xw i eno see e Figure 2 18 Floorplanner View the Package Viewer You can also see how pins were placed for your design by selecting the Package Viewer You can select the package viewer by going to the menu and selecting Tool Package Viewer or you can also select the Package Vierwer Icon See Figure 2 19 23 wwWw SiliconBlueTech com iCecube Tutorial Silicon Technologies ES SiliconBlue iCEcube2 gt File ns View Tool Window Help icetest Package View DE ES 1 Project l Name quick start 3 Design Flow E Specify Synthesis Input Files Design Files amp Constraint Files Y Synthesis g P amp R Input Files e Select Implementation qui quick_start edf quick_start scf Specify Additional Files e Import P amp R Input Files e Place gt Route gt Bitmap Output Files reports bitrnap simulation netlist Device Operating Con
4. CEcube2 Tutorial v1 0 May 2010 Q Siliconl uis Technologies Silicon Mit Technologies Copyright Information Copyright 2008 20010 SiliconBlue Technologies Corporation All rights reserved SiliconBlue iCEcube iCEcube2 iCE65 mobileFPGA are trademarks of SiliconBlue Technologies Corporation Magma and Blast FPGA are trademarks Magma Design Automation Inc Synopsys and Synplify Pro are trademarks of Synopsys Inc All other trademarks are the property of their prospective owners All specifications are subject to change without notice Notice of Disclaimer This software is provided to you as is without any express or implied watranty Contact Information SiliconBlue Technologies Corporation 3255 7 Scott Blvd Suite 101 Santa Clara CA 95054 Tel 408 727 6101 Fax 408 727 6085 support siliconbluetech com Revision History The following table lists the revision history of this document Version Revision Release iCEcube2 2010 03 iCecube2 Tutorial www SiliconBlueTech com 2 Siliconi illi Technologies www SiliconBlueTech com iCecube Tutorial Silicon Mit Technologies Preface About this Document The 1CEcube2 Tutorial takes the user through the iCEcube2 development tools step by step using a sample design After using the tutorial the user will be able to set up a project compile a design and run different analysis tools such as the static timing analyzer and
5. ShtTools examples blinky quick_start quick_start_syn prj n t File Edit View Project Run Analysis HDL Analyst Options Window Tech Support Web Help LEEN 0 BR P d V FRE S co Y Qm LZ 3 S oc A 145 Els Pm mimi eae Synplify Pro Run has Ready 5 Open Project quick start Implmnt Silicon Blue iCE65 iCEGSLU4 CB284 L Implementation Directory E B quick start syn C SbtTools examplesiblinky quick startiquick start syr Ci SbtToolslexamplesiblinkylquick startlquick start Implmnt E blinky vhd work B e Constraint ES blinkly_syn sdc da quick stark Implmnt Directory Directory Directory Directory Directory identify log 152 bytes log File quick_start edf 119 kB Edif Metlist quick_start Fse O bytes fse File guick_start htm 348 bytes htm File quick_start scf 2 kB scf File quick start srd 14 kB Netlist Feauni A M a quick start srl 6kB Netlist RTL a 14 quick_start srm 121 kB Netlist Gate e Auto Constrain quick start srr 47 kB str File I quick start srs 6 kB Netlist RTL 17 45 00000 FSM Compiler E quick start szr 17 kB sar File 17 45 Resource Sharing E quick_start tlg 869 bytes tlg File E uick start prepass srd 7 kB Netlist 17 45 Pipelining ri Retiming B quick_start_syn pri Information ES a e Se E d e License synplifypro sbt node locked Log Parameter quick stark Implmnt
6. change the Device to L04 and change the device package to the CB284 4 Operating Condition Fields This section allows you to specify the operating conditions of the device which will be used for timing and power analysis 5 Start From Synthesis This option allows you to specify the Synopsys Synplify synthesis tool or the Magma BlastFPGA synthesis tool for logic synthesis For this example select Synplify 6 Click Next to go to the Add Files dialog box shown in Figure 2 3 You will be prompted to create a new project directory Click Yes 7 In the Add Files dialog box navigate to lt iCEcube2 installation directory examples blinky Highlight the following files blinky vhd blinky syn sdc Select each file and click to add the selected file or click 29 to add all the files in the open directory files can be removed using and to your project Click Finish to create the project The SDC file is a Synopsys constraint file which contains timing constraint information E Add Files Files to add Look in C SbtToolsfexamples blinky Mi e Ia 2 i blinky sde blink vhd q blinky pcf igg B blinky sdc blinky vhd My Computer iL quick start E Desktop File name blinky vhd Details Files of Eype All Files v Finish Cancel Figure 0 3 New Project Wizard Add Files dialog box After successfully setting up your project you will return to the
7. and Pin constraints 3 Perform Placement and Routing using the iCEcube2 place and route tools iCEcube2 also supports physical implementation tools such as floor planning allowing users to manually place logic cells and IOs 4 Perform timing simulation of your design using an industry standard HDL simulation tool The files necessary for simulation are automatically generated by the iCEcube2 Physical Implementation tools after the routing phase 5 Perform Static Timing Analysis using the iCEcube2 static timing analyzer 6 Generate the device programming and configuration files from the iCEcube2 Physical Implementation tools 7 Program your device using the device programming hardware provided by Silicon Blue Technologies Tutorial This chapter provides a brief introduction to the iCEcube2 design flow The goal of this chapter is to familiarize the user with the fundamental steps needed to create a design project synthesize and implement the design generate the necessary device configuration files and program the target device Detailed information on tool features and usage is provided in subsequent chapters Creating a Project Starting the CEcube2 software for the first time you will see the following interface shown in Figure 2 1 iCecube2 Tutorial www SiliconBlueTech com 6 Silicon ii Technologies m SiliconBlue iCEcube2 y View Tool Window Help r2 Figure 0 1 Create a New Project The firs
8. has been completed you can view the placement of the design by opening the Floorplanner You can open the Floorplanner by going to the menu and selecting Tool gt Floorplanner or you can also select the Floorplanner Icon See Figure 2 18 iCecube2 Tutorial www SiliconBlueTech com 22 e Silicon lll Technologies SiliconBlue iCEcube2 icetest Floor Planner CB lt ro q e a Output dow Help ERR amp Specify Synthesis Input Files i Design Files Logic Instance Instance Type Constraint Files e IN MUX bfv 14 5 SB_CARRY_IN Y Synthesis d de IN MUX bfv 14 6 SB CARRY IN P amp R Input Files dj a IN MUX bfv 14 7 SB CARRY IN ha amp 4M IN_MUX_bfy_14_8 SB_CARRY_IN 2 A Select Implementation qul 5 mi Mux pe 14 1 SB_CARRY_IN quick_start edf d Ae IN MUX bfv_14 2 SB_CARRY_IN quick_start scf d 4 IN_MUX_bfv_14_3 SB CARRY IN Specify Additional Files de IN MUX bfv 14 4 SB CARRY IN e Import P amp R Input Files d amp 4 IN MUX bfv 15 1 SB CARRY IN Y Place amp 4M IN MUX bfv 15 2 SB CARRY IN D Route dde IN MUX b v 15 3 SB CARRY IN rw p re mm e ver m aw ara x m Era 73 D Bitmap 4 IN MUX bfv 15 4 SB CARRY IN 3 Output Files UY CONSTANT ONE L SB LUT4 amp reports E YD Order to 1Hz un SB LUT4 bitmap 4M Divider to 1Hz un SB CARRY simulation netlist i d Divider to 1H2 un
9. mtcl 5 quick start File name blinky_constraints mtcl Files of type FILES sdc scf clb pcf mtcl edf edif edn vqm Figure 2 26 Add mtcl file iCecube2 Tutorial www SiliconBlueTech com 28 e Silicon Technologies Import Place amp Route Input Files The next step is to import the files for Place and Route Double click on Import P amp R Input Files in the Project Navigator See Figure 2 27 Once completed you will see a green check next to Import P amp R Input Files See Figure 2 28 SiliconBlue iCEcube2 EFE 3 2 C Design Flow E Specify Synthesis Input Files amp Design Files amp Constraint Files e Synthesis E P amp R Input Files ef Select Implementation qui quick_start edf quick start scf Specify Additional Files Constraint Files blinky_constraints mtel o Route gt Bitmap Output Files i reports bitmap simulation netlist Device Operating Condition E Device Info DeviceFamily iCE6S Device L04 Device Package CB284 Power Grade L Operating Condition Core Voltage Temperature C Figure 2 27 Double click on Import P amp R Input files 29 wwWw SiliconBlueTech com iCecube 2 Tutorial e Silicon 46 Technologies SiliconBlue iCEcube2 Output E JB px W File View Tool Window Help MIFARE Project Name quick_start 5 B x E Design Flow Specify Synthesis Input Files Design Files CiSbtTools sbE backe
10. power estimator tools For information on the Synopsys Synplify Pro software please refer to the Synplify Pro documentation provided in the synpro doc directory in the iCEcube2 software installation lt icecube2_install_dir gt synpro doc and on the SiliconBlue website For detailed information of the iCEcube2 development tools please refer to the CEcube2 User Guide Software Version This tutorial documents the features of iCecube2 Software Version 2010 03 For more information about acquiring the iCecube2 software please visit the SiliconBlue website http www siliconbluetech com Platform Requirements The iCecube2 software can be installed on a platform satisfying the following minimum requirements A Pentium 4 computer 500 MHz with 512 MB of RAM running one of the following operating systems e Windows XP Professional e Windows Vista e Red Hat Enterprise Linux WS v4 0 Programming Hardware There are three ways to program iCE FPGA devices e A third party programmer using the programming files generated by the Cecube2 Physical Implementation Tools Consult the third party programmer user manual for instructions e The iCEman Evaluation Board which not only serves as a vehicle to evaluate CE FPGAs but also includes an integrated device programmer This programmer can be used to program devices on the iCEman board or it can be used to program devices in a target system Please contact SiliconBlue Technolog
11. Editor Icon i23 PMCO B1B RUSL Physical constraints save as Packing constraints file ick startlquick start Implimntisbticonstraintlicetest_clb_sbt clbl Physical constraints File ede wa ll Y mU We maa a k startiquick start Implmntisbticonstraintlicetest pef sbt pcf RR r Add these constraints files into the project check it will result im the current tools closed Figure 2 30 Pin Constraints Editor www SiliconBlueTech com 10 Standard g kg km OOOO ER pm E E 5 8 E 8 iCecube Tutorial
12. IF Parser succeeded S Import P amp R Input Files Top module is icetest Place gt Route gt Bitmap Output Files reports bitmap simulation netlist Device Operating Condition amp Device Info DeviceFamily iCE65 Device LO4 Device Package CB284 Power Grade L 5 Operating Condition Core Voltage v Temperature C Figure 2 16 Successful Import of P amp R Input Files Place the Design Double click on Run Placer Once placement is complete a green check will appear and the Output window will show information about the placement of the design See Figure 2 17 21 www SiliconBlueTech com iCecube Tutorial e Silicon Mit Technologies SiliconBlue iCEcube 2 icetest Output 3 Specify Synthesis Input Files Design Files Constraint Files Synthesis 3 P amp R Input Files r Quick start edf mber of clocks lt Quick start scf Specify Additional Files Y Import PAR Input Files End of Clock Summar b U U bU B b B Bi B d B B Ui FSR SK SSS Bi i B SSS SSSR SSSR Bi B B d LEALES te o SON COME e Success Place Comple Information regarding placement simulation netlist e g Clock Summary Device Operating Condition Device Info DeviceFamily iCE65 Device LO4 Device Package CB284 Power Grade L Operating Condition Core Voltage V Temperature C Figure 2 17 Place complete View Floorplanner At this point since placement
13. Settings Multiple Images 2 24 Programmer Graphical User Interface Addendum Importing Physical Constraints from iCEcube to iCEcube2 For users who have created physical constraints using iCEcube this section describes how to import and convert those constraints for use in iCEcube2 This section will demonstrate how to import a MTCL file from iCEcube and save it into PCF format used in iCEcube2 In the iCEcube2 project navigator Right click on Specify Additional Files See Figure 2 25 oF www SiliconBlueTech com iCecube Tutorial Siliconl Technologies SiliconBlue iCEcube amp Design Flow amp Specify Synthesis Input Files Design Files amp Constraint Files ef Synthesis E P amp R Input Files B e Select Implementation qui quick start edf quick start scf ES Specify Additional File Constraint Files D Import P amp R Input Files gt Place gt Route D Bitmap Output Files reports bitmap simulation netlist Device Operating Condition amp Device Info DeviceFamily iCE65 Device L04 Device Package CB284 Power Grade L 5 Operating Condition Core voltage 1 14 Temperature C 70 Add Files Remove Files Figure 2 25 Add additional constraint file Navigate to the lt iCEcube2 Installation Directory gt examples blinky and Add blinky mtcl file See Figure 2 26 Add Files blinky_constraints mtcl amp blinkly_syn sdc blinky_constraints
14. acer Perform Static Timing Analysis Now that you have routed the design you can perform timing analysis to check to see if the design is meets your timing requirements To launch the timing analyzer go to the menu and select Tool gt Timing Analysis You can also select the Timing Analysis Icon See Figure 2 22 iCecube2 Tutorial www SiliconBlueTech com 24 e Silicon ie Technologies SiliconBlue iCEcube Timing Analyzer File View Too Window Help J BARES Ce Timing Analysis Icon Project Name quick_start ax Output icetest_sbt rpt Timing Analyzer 2 Design Flow 3 Specify Synthesis Input Files Summary Analyze Paths Timing Corner Best Typical Worst z Design Files eas TT J bliscy vd Constant Files blinky sde Save Surrenar Y Synthesis P amp R Input Files Clock Name Worst Slack ps FMAX MHZ Target Frequency MHZ Failing Path t Y Select Implementation qul t CLk 32KHz 991479 117 36 1 00 Specify Additional Files Constraint Files 2 OK 32MHZ 18696 79 65 Y Import PSR Input Files clock divider 12 Y Place COUNTER inferred Y Route y Dock divider SeME D Bitmap COUNTER _inferred_ Output Files reports bitmap simulation netlist 5 Device Operating Condition 3 Device Info DeviceFamily ICE65 I Device LOA CAOS Device Package CB284 Paths Summary 1 1 Power Grade Save Summary Save Detail gt Operating Condition Start Port Star
15. ap simulation netlist Device Operating Condition Device Info DeviceFamily iCE65 Device LO4 Device Package CB284 Power Grade L Operating Condition Core Woltage y 1 14 Temperature C 70 Output C SbtTools synpro bin synplify_pro exe C SbtTools examplesiblinkyquick_start quick_start_syn prj C SbtTools synpro bin synplify_pro exe C SbtTools examples blinky quick_start quick_start_synprj Select Synthesis Implementation Synthesis Implementation Selection Please select the implementation as input to PER C SbtTools examples blinky quick_start quick_start_Implmnt Figure 2 12 Select Synthesis Implementation Importing Physical Constraints Physical constraints such as pin assignments are stored in a PCF file Physical Constraint File Add the PCF file to your project In the iCEcube2 Project Navigator Right Click on Specify Additional Files Select Add Files See Figure 2 13 Note For information on importing physical constraints from iCEcube to iCEcube2 please refer to the Importing Physical Constraints from iCEcube to iCEcube2 section at the end of this quick start guide iCecube2 Tutorial www SiliconBlueTech com 18 e Silicon ie Technologies SiliconBlue CEcube2 Fie View Tool Window Help amp Design Flow amp Specify Synthesis Input Files Design Files d Constraint Files ef Synthesis E P amp R Input Files B Y Select Implementatio
16. dition i Device Info DeviceFamily Device LO4 Device Package CB284 Power Grade L Operating Condition Core Voltaqe Temperature C iCE6S E LE 54 36 4 IR E Floor Planner Y Pin Constraints Editor PPPPPP E El E PMOD ES TAY 4 PMOD_BOR_313 1 4 PMOD_B3B_138 1 4 PMOD B1T J20 1 4 PMOD B1B 321 1 4 PMOD_BOL_312 1 4 2 BINS PMOD_B2L_331 1 4 iP sws ANM CLK_32MHZ BL CLK 32KHz gb sw r Ta TEN r PARAS Gooo 11 Li Lj E mU li LLCELT BOO 1 poema jom LL lt ees O30 ODOMDa2 a6000 22000 a o0costal C 3 8 OOOOOOOQO0 2 S sean oe iow e I 25 Cu war a purae S i H za a 0080 0089 ii en ow salen 8e E edi x as a TET Aor 70r0674 OO LLL ess ex ao SONO r 1 8 GOOOOGOQGOO Package View Package Pin Legend Pio E PIO GBIN 5 SPI_SI SPI_SO SPI_SCk SPI_S5_B HB cu ai vcc i vccrojvopro ser _ CDONE CRESET B DRESET B EI vPPJVDDP B vnEF B TCK TDI TDO TMS TRST_B i O q World View iCE65L04 CB284 Figure 2 19 Package Viewer Route the Design Double click on Route in the project navigation window Place and Route have been separated into different steps as to allow you to re route the design after making placement modifications in the floorplanner without having to re run the pl
17. er the locked column Uncheck and Recheck one of the pins under the locked column The save icon will now become an active icon Click on the Save physical constraints icon This will bring up a dialog box where you can save the CLB and PCF files Hit OK See Figure 2 30 The PCF file contain physical constraints in the design used for place and route iCecube2 Tutorial www SiliconBlueTech com 30 SiliconBlue iCEcube 2 gt icetest Pin Constraints Editor Constraint Files Y Synthese gt P amp R Input Files PMOO B3T J359 1 PMOD B3T 139 2 3 Y Select Implementation qui quick start edf quick start scf Specify Additional Files e import PER Input Files simulation netlist Device Operating Condition Device Info DeviceFamily ICE65 Device LO4 Device Package CB284 Power Grade L Operating Condition Core Voltage V 1 14 Temperature C 70 31 PMOO B2R J30 4 9 PMOO_BOR_J13 1 10 PMOO BOR 213 2 ii PMOO BOR 213 3 12 PMOO BOR Ji3 4 13 PMOO_B3B_J39 1 14 PMOO B3B 738 2 s PMOO 535 J58 3 16 PMOO B38 J3e 4 17 PMOO BT J20 1 18 PMOO B1T J20 7 19 PMOO BIT J20 3 20 PMOO BIT Jo0 4 21 PMOO BIB J21 1 122 PMOD 518 Jzi 2 Silicon iG Technologies Save Physical Constraints Pin Constraints Editor Package View Pin Location Bark M Left meo Left N7 Left w Uncheck and recheck Locked Box Y20 Bottom Y18 Bottom Y19 Bottom Pin Constraints
18. following CEcube2 Project Navigator screen shown in Figure 2 4 9 www SiliconBlueTech com iCecube Tutorial Silicon Mt Technologies SiliconBlue CEcube2 Output File View Tool Window Help De Bee Project Name quick_start E Specify Synthesis Input Files a Design Files blinky vind Constraint Files blinkly_syn sde p Synthesis BR Input Files Synthesis input files gt Select Implementation amp Specify Additional Files are now added Y hi FE AS I unt les i gt 3 Output Files reports bitmap Tikal Device Information Device Info and Operating Conditions DeviceFamily Device LO4 are now set Device Package C8284 Power Grade L 3 Operating Condibon Core Voltage V 1 14 Temperature C 70 Figure 0 4 CEcube2 Project Navigator View after Completing Project Set up Synthesizing the design After a successful project setup Double Click on the Synthesis Launch Synthesis Tool icon in the project navigator window See Figure 2 5 This will bring up the Synopsys Synplify Pro synthesis tool s graphical user interface See Figure 2 6 iCecube2 Tutorial www SiliconBlueTech com 10 Silicon Technologies Us SiliconBlue CEcube2 Output es D o JDLud ERE CN M d 4 Hale blinky vhd 3 Constraint Files Double click on Synthesis Figure 2 5 Launch Synthesis Tool 11 www SiliconBlueTech cam iCecuhe Tutorial e Siliconlitte Technologies Synplify Pra D 2009 125 Early Access 2 C
19. hat block See Figure 2 11 iCecube2 Tutorial www SiliconBlueTech com 16 e Silicon ie Technologies Synplify Pro D 2009 125 Early Access 2 Hj File Edit View Project Run Analysis HDL Analyst Options Window Tech Support Web Help Dia OFC 4 i J sw Gum Oo Ft ia a P aja py Sheet Tof 1 top level of module icetest MIL View Jquickostartimpimnt quick starters C sbttools examples blinky blinky EL f instances PMOD BOL Jl2 lt TOP EDGE 7 downto 4 PMOD BOR Jl3 lt TOP EDGE 3 downto 0 Ports 13 A E Nets 13 i PMOD BlT J20 lt RIGHT EDGE 7 downto 4 H Clock Tree PMOD B1B J21 lt RIGHT EDGE 3 downto 0 PMOD B2R J30 lt BOTTOM EDGE 7 downto 4 PMOD B2L J31 BOTTOM EDGE 3 downto 0 PM D B3B J38 lt LEFT EDGE 7 downto 4 PMOD B3T J39 lt LEFT EDGE 3 downto 0 Divide 32 kHz clock to 1 Hz 1 second EEES clock divider lHz port map CLK 3ZkHz gt CLK_32KHz CLK_1Hz gt CLK 1Hz LED CLK gt LED CLK 100 1 101 102 Top edge PMOD Drivers 103 PMOD_TOP rotate led 104 port map 105 CLK gt LED CLE 106 SU3 gt SUS 107 swz gt SWZ 108 BTN3 gt BTN3 PMOD LEFT FETU LED gt TOP EDGE Port put sel of entity work clock_divider_1 hz is unconnected Help Ln GL ana iB quick start syn prj El blinkly_syn sdc 3 quick start srs la blinky vhd Information EPA CUTTER umi TRATO TOD 55 Sacs Opening object
20. he Tutorial e Siliconlilli Technologies Synplify Pro D 2009 125 Early Access 2 C SbtTools examples blinky quick start quick start syn prj S File Edt view Projet Run Analysis HDL Analyst Options Window Tech Support Web Help ID El amp tct2 d 4 480908 mw 92272 3 lt lt gt Q 9i bs Em P mins c quick start Implmnt S con Blue ICE6S jCE65L04 CB284 SD qud_stsrt_syn C Sbt Tools examples Bg wo dl birky vhd work lB Constraint E sde Q quick start ret Aartiquck start sy mii Open the SDC file 8 quick start htm quick_start scf quick_start srd C2E2ESEPEXQ GG PHI Ht PER Figure 2 8 Open the SDC file to View Timing Constraints iCecube2 Tutorial www SiliconBlueTech com 14 Silicon Mite Technologies Synplify Pro D 2009 125 Early Access 2 C SbtTools examples blinky blinkly_syn sdc B T l Fle Edt View Project Run Analysis HOL Analyst Options Window Tech Support Web Help BF 3 A li 8 4 0 gt 4 amp f V m OFF amp Edo a la a mpm gt Clock Object Fall Ar ES Cycle Route Virtual n ns clock CLK_32KHz CLK _32KHz 1000 defaut clkgroup 0 CLK 32MHZ CLK 32MHZ 31 25 defauk clkgroup 3 Timing constraints Click on Project tab to return to Project GUI Clocks Clockto Clock ollecbons InputsjOutputs Registers Delay Paths Attributes ljO Standards Co
21. ies for additional information on the iCEman Evaluation Board e Digilent USB cables iCecube2 Tutorial www SiliconBlueTech com 4 Siliconl itte Technologies Overview iCEcube2 Tool Suite The figure below depicts the design flow using the iCEcube2 Tool Suite The components in blue signify functionality supported by SiliconBlue Technologies proprietary iCEcube2 software and the components in purple indicate the functionality supported by Synopsys Synplify Pro synthesis tools The iCEcube2 software and Synopsys software together constitute the iCEcube2 Tool Suite Verilog VHDL Design Files 9 Post Synthesized VHDL or Verilog Netlists EDIF Netlist Timing Constraints Post P amp R Verilog or VHDL Netlist SDF Figure 0 1 The iCEcube2 Design Flow 5 www SiliconBlueTech cam iCecuhe Tutorial Siliconlitte Technologies Design Flow The following steps provide an overview of the design flow using the iCEcube2 Tool Suite 1 Create a new project in the iCEcube2 Project Navigator and specify a target device and its operating conditions Add your HDL Verilog or VHDL design files and your Constraint files to the project 2 Synthesize your design using the Synplify Pro design software This software has been provided as part of the iCEcube2 Tool Suite and can be invoked from the iCEcube2 Project Navigator Within the Synopsys design environment assign your Logic Synthesis Timing
22. mplePonts Other art_syn prj E blnkly syn sdc Information Sx Watch oe cw eee Ro zav uw a ee L LIA au weve ye License synplitypro sbt node locked quick start Implmot Figure 2 9 View Timing Constraints Viewing Hierarchical View of Synthesis Results Under the HDL Analyst menu Select RTL gt Hierarchical View You will see a hierarchical RTL view of the design just synthesized See Figure 2 10 15 www SiliconBlueTech com iCecube Tutorial e Siliconlitte Technologies Synplify Pro D 2009 125 Early Access 2 Sheet 1 of 1 top level of module icetest RTL View quick_start_Implmnt quick_start srs EIE D File Edit View Project Run Analysis HDL Analyst Options Window Tech Support Web Help 5 xi psemnitxsJ tgeme55o6moo7is5 e 29s9 93 9334i w SHH Pea SAB 74 E 2 Instances 6 m E K Ports 13 mig S f Nets 13 H E E Clock Tree Deke r b 1H PMO D_LEFT IP quick start syri prj E blinly syn sdc 42 quick start htm a quick start srm quick start srs Y quick start srs Information Exi Watch Log Parameter SBTiCE65 Mapper Completed with warnings Return Code l Completion Time 13 37 50 E quick start Implmnt TCL Script Messages Log Watch f 0t EA gt Y Figure 2 10 Hierarchical RTL View in HDL Analyst If you double click on one of the blocks it will take you to the RTL for t
23. n qui quick_start edf quick_start scf ES Specify Additional File Constraint Files D Import P amp R Input Files D Place gt Route D Bitmap amp Output Files reports bitmap simulation netlist Device Operating Condition amp Device Info DeviceFamily iCE65 Device L04 Device Package CB284 Power Grade L 5 Operating Condition Core voltage 1 14 Temperature C 70 Add Files Remove Files Figure 2 13 Specify Additional Files for Place and Route Navigate to the lt iCEcube2 Installation Directory gt examples blinky and Add blinky pcf file See Figure 2 14 Add Files A a Fles to add blinky pcfF quick start blinky pcf blinky sde My Computer Filename blinky pcf Files of type Constraint sdc scF clb pcf mtcl Ca Figure 2 14 Add pcf file 19 www SiliconBlueTech com iCecuhe Tutorial e Silicon lie Technologies Import Place amp Route Input Files The next step is to import the files for Place and Route Double click on Import P amp R Input Files in the Project Navigator See Figure 2 15 Once completed you will see a green check next to Import P amp R Input Files See Figure 2 16 SiliconBlue iCEcube2 Fie View Tool Window Heb ID nae 3 C 2 8x Design Flow E Specify Synthesis Input Files Design Files Constraint Files e Synthesis E P amp R Input Files ef Select Implementation qui quick start edf Quick s
24. ndjbinjwin32 optedifparser exe C SbtTools sbt_backend devices ICES dey C Constraint Files S5btTools examplesblinkyquick_startfquick_start Implmnt quick start edf C SbtTools examples blinky quick_start quick_start_Implmnt sbt netlist 2 Synthesis pCB284 mC SbtTools examplesjblinky blinky constraints mtl SiliconBlue Tech Edif Parser P amp R Input Files Release 2010 03 11374 e Select Implementation qui Build Date Apr 14 2010 11 52 25 quick start edf quick start scf Specify Additional Files Constraint Files blinky_constraints mtel EDIF Parser succeeded e Import P amp R Input Files Place Route D Bitmap Output Files reports bitmap simulation netlist Device Operating Condition Device Info DeviceFamily iCE65 Device LO4 Device Package CB284 Power Grade L Operating Condition Core Voltage v Temperature C Parsing edif File C YSbtToolsexamplesiblinkyYquick stark quick stare Implmnt quiek starb edF Generating netlist Stored edif netlist at C SbEToolslexamples blinky quick skart quiek start Implmnt sbE netlistoadb icetest Figure 2 28 Successful Import of P amp R Input Files Saving Physical Constraints into pcf Format Open the Pin Constraints Editor by going to the menu and selecting Tool gt Pin Constraints Editor or you can also select the Pin Constraints Editor Icon See Figure 2 29 You will se a list of pin assignments that are Locked und
25. source file c sbttools examples blinky blinky vhd Opening object source file c sbttools examples blinky blinky vhd Opening object source file c sbttools examples blinky blinky vhd Opening object source file c sbttools examples blinky blinky vhd n Log Farameter quick start Implmnt TCL Script Messages Log Watch n SS I Ot EP Figure 2 11 Double clicking on a block will reveal its HDL code in HDL Analyst Select Implementation In order to ensure that the synthesized design can be successfully imported into iCEcube2 exit the Synplify Pro GUI Return to the iCEcube2 Navigator and Double click on Select Implementation See Figure 2 10 This will tell iCEcube2 which synthesis implementation to process for place and route If you have different synthesis implementations you will be able to select the synthesis implementation you wish to place and route Since we only have one implementation select OK when the Select Synthesis Implementation dialog box appears 17 www SiliconBlueTech com iCecube Tutorial e Silicon Mit Technologies V Siliconfilue iCEcube2 TIT TL De sas Project Name quick start _ Design Flow Specify Synthesis Input Files Design Files Constraint Files e Synthesis E PAR Input Files Select Implementation Specify Additional Files Constraint Files D Import P amp R Input Files D Place gt Route gt Bitmap Output Files reports bitm
26. t Edge End Point Core Voltage 12 Core Voltage v 1 Divider_to 1Hz C RISE Otvider to RISE Temperature C 3 Figure 2 22 Timing Analysis Summary You can see from the timing analysis that our 1MHz design is running at over 100 MHz and our 32 MHz clock is running at over 70 MHz worst case timing If we were not meeting timing the timing analyzer will allow you to see your failing paths and do a more in depth analysis For this tutorial we won t go into details on timing slack analysis Perform Power Analysis iCEcube2 also comes with power estimator tool To launch the power estimator to the menu and select Tool gt gt Power Estimator You can alternatively select the power estimator icon Figure 2 23 There are multiple tabs in the Power Estimator tool including Summary IO and Clock Domain On the Summary tab change the Core Vdd to 1 0V and make sure all IO voltages are at 2 5V Then hit calculate The estimator will update with power information for both static and dynamic power For more information on using the IO and Clock Domain tabs please refer to the detailed section on the Power Estimator tool 25 www SiliconBlueTech com iCecube Tutorial Silicon Mit Technologies C Power Estimator Summary IO Clock Domain Core Ydd w 1 00 w Power Grade L Dynamic Power Breakdown IO Voltage Core Power mW 1 30151 IO Power mW 2 Left Bank IO Voltage V 2 5
27. t step is to create a new design project and add the appropriate design files to your project You can create a new project by either selecting File gt New Project from the iCEcube2 menu or by clicking the Create a New Project icon as seen in Figure 2 1 The New Project Wizard GUI is displayed in Figure 2 2 Silicon Mit Technologies New Project Praject Project Name quick start Project Directory I C SbtTools examplesiblinky quick start Device Device Family iCE6S ww Device L04 v Device Package CB284 v Power Grade L wv Operating Condition Junction Temperature in degrees Celsius Range Best Typical Worst Commercial v lo 25 7 Core Voltage w voltage Tolerance Range Best Typical Worst 53 datasheet defaul i 1 2 v 1 14 al Perform timing analysis based on C Best Typical Worst G Start From Synthesis Synplify Magma C3 Start From BackEnd Figure 0 2 New Project Setup Form 1 Project Name Field Specify a project name quick_start in the Project Name field 2 Project Directory Field Specify any directory where you want to place the project directory in the Project Directory field iCecube2 Tutorial www SiliconBlueTech com 8 Silicon I Technologies 3 Device Fields This section allows you to specify the SiliconBlue device you are targeting For this example
28. tart scf amp Specify Additional Files Constraint Files blinky_constraints mtel oP Route gt Bitmap E Output Files reports bitmap i simulation netlist Device Operating Condition Device Info DeviceFamily iCE65 Device LD4 Device Package CB284 Power Grade L Operating Condition Core Voltaget Temperature C Figure 2 15 Import P amp R Input files iCecube2 Tutorial www SiliconBlueTech com 20 Silicon dite Technologies SiliconBlue iCEcube2 Output W File View Tool Window Help De Bas Project Name quick_start Output E Design Flow Specify Synthesis Input Files Design Files CiSbtTools sbt backendjbin win32 optedifparser exe C SbtTools sbt_backend devices ICES dey C amp Constraint Files SbtTools examples blinky quick_start quick_start_Implmnt quick_stat t edt C SbtTools examples blinky quick_start quick_start_Implmnt sbt netlist ef Synthesis pCB284 mCt Sbt Tools x amples blinky blinis constraints mtel y SiliconBlue Tech Edif Parser zi PAR Input Files Rel 2010 03 11374 i e Select Implementation qui Build Date Apr 14 2010 11 52 25 quick start edf x qu ick start scf cae ima 1 SbtToolsiexamplesiblinkyNquick starb quick start Implmnt quiek starb edF Generating netlist E I fea Files Stored adi netlist at C SbtToolsfexamples blinky quick_start quick_start_Implmnt sbt netlist oadb icetest iz Constraint Files blinky_constraints mtcl ED
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