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RCCIPC - Data Sheet

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1. 31 30 29 28 27 26 25 24 2322 21 20 19 18 17 16 15 14 1312 11 109 8 7 6 5 4 3 2 1 0 field ix err cnt rx err cnt reserved lc o 3 3 lo rccipc state cic 3 9 lx o H D o lo o lS lel lt lo oxbsoi o Q 2C s jS sdo host ro ro ro ro ro ro ro rwiro ro rst 0x0 0x0 0x0 000100 000000 5 e S E Bit Number Mnemonic Description 5 0 ccipc state RCCIPC NMT state value e 000001 gt Initialising e 000010 gt Reset Application e 000100 gt Reset Communication e 001000 gt Pre Operational e 010000 gt Operational e 100000 gt Stopped 6 active bus Currently CAN bus used 7 rx overflow This condition arises when incoming message arrives and the previous message has not been still processed This condition is handle as a CAN interface error and is associated to Error IRQ line User has to clear this bit during the IRQ handling 9 err passive CAN core Error Passive condition 10 bus off CAN core Bus Off condition 11 auto op This fag indicates if the Auto operational condition is activated or not If 1 RCCIPC automatically enters in Operational state after Initialization phase 23 16 rx err cnt CAN core Receiver error counter value 31 24 tx err cnt CAN core Transmitter error counter value gt IRQ status Index 2003h Sub Index 3h Address 0x1128 3
2. Index Entry Name Hardware implementation 1000h Device Type Not available 1001h Error register Not available 1005h COB ID synch Not available 1007h Synchronous Window length Not available 1016h Heartbeat consumer time Not available 1017h Producer Heartbeat time Not available 1018h Identity object Not available 1200h Server SDO Not available 1400h RPDO Communication Parameter Not available 1600h RPDO Mapping Parameter Not available 1800h TPDO Communication Parameter Not available 1A00h TPDO Mapping Parameter Not available 2000h Redundancy Management Available in Read only mode 2002h Node parameters Available in Read only mode 2003h RCCIPC status amp configuration Available 6000h RPDO Application Objects Available 6001h TPDO Application Objects Available 6002h SDO Application Objects Available The value of the parameters of these entries depends on NodelD assigned to RCCIPC The NodelD is sampled after Reset phase using a dedicated interface pins 6 1 1 Configurable Parameters Tab 6 1 RCCIPC OD structure A VHDL file RCCIPCconf vhd is used to define the RCCIPC configuration through a set of VHDL constant The relationship between OD entry and configurable mapping parameter is reported in Tab 6 2 Index Entry Name Configurable Constant 1016h Heartbeat consumer time CONS HB 1017h Producer H
3. Create a symbolic link to the main directory of CCIPC DataBase directory with CCIPC_DB name In s YourPath RCCIPC_DB RCCIPC_DB Create a symbolic link to the to the Makefile included in the SRC directory gt In s RCCIPC DB SRC Makefile gt In s RCCIPC DB SRC Makefile mem Set up the simulator path in the CDS ROOT environment variable gt setenv CDS ROOT YOUR SIMULATOR PATH Launch the set up command gt make setup Create the following simulation auxiliary file gt touch stimuli txt Now launch the make command to generate simulation file gt make After process elaboration to simulate the system launch the following command gt ncsim RCCIPC tb A gui amp File name CAS RCCIPC DTS 0001 Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use Doc CAS RCCIPC DTS 0001 Issue 6 SITAEL RCCIPC Data Sheet A Aenean Page 30 of 53 Other tools If another tool is utilised the VHDL_Comp and CHDL_Elab variables and the tool Set up section have to be modified inserting the specific tool commands before proceeding with the compilation process 8 1 RCCIPC Core Test Bench The RCCIPC co
4. Doc CAS RCCIPC DTS 0001 l 6 S TAEL RCCIPC Data Sheet iA EN Page 1 of 53 RCCIPC Data Sheet Prepared by P Tosi ffo he Date 08 05 2014 Verified by W Errico ihn pu 08 05 2014 Approved by F Bigongiari Project Manager 08 05 2014 fees File name CAS RCCIPC DTS 0001 Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use Doc CAS RCCIPC DTS 0001 l 6 S TAEL RCCIPC Data Sheet i mm Page 2 of 53 Change Document Record Document title RCCIPC Data Sheet Modified 3 10 06 2011 First issue of the document A 4 2 2 2 3 3 3 3 3 File name CAS RCCIPC DTS 0001 Issue6 docx RCCIPC Data Sheet Replaced all CCIPC references with RCCIPC in all 10 Modified Tab 4 2 FPGA family files o In TPDO AO table in 5 1 2 replaced RPDO AO description with TPDO AO In RCCIPC AO and RCCIPC AO Total Bytes o tables in 85 1 2 modified Sub Index upper limit to 254 In Block Size table in 85 2 3 modified Sub Index o upper limit to 254 In 6 modified periphery signal names in Fig 6 1and 21 09 2011 4 20 Added 86 1 3 Node ID Acquisition and Modification In Tab 7 1 modified BLKIDL BLKDL BIkIUL and o BIKUL definitions Modified ID f
5. ID Daca nis 2002h Eesti Da Im RUD UNE field reserved node_id sdo B i host ro ro rst 0x0 0x00 T0 node id teotg lt 0 field ESTEE sdo host ro ro rst 0x000000 0x6 7 0 st amp cfg Subindex 0 of RCCIPC Status and Configuration entry gt cer configuration Index 2003h Sub Index unl Address Ox10A0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514 09 8 7 6 5 4 3 2 1 0 field reserved RSJ PS2 PS1 BPR 2 E sdo s host ro rw rw rw rw rw rst 0x0 s t T n PS2 VAL PS1 VAL S S i i BPR Frequency scaler value 1 0 5 2 PS1 Phase Segment 1 value 9 6 PS2 Phase Segment 2 value File name CAS RCCIPC DTS 0001 Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use SITAEL Doc CAS RCCIPC DTS 0001 Issue 6 Date 08 05 2014 Page 41 of 53 RCCIPC Data Sheet Bit Number Mnemonic Description 12 10 RSJ Resynchronization Jump width 13 can_rst Active High CAN Core reset gt HurriCANe amp RCCIPC status Index 2003h Sub Index 2h Address 0x10A4
6. ACTEL AX TECH GEN ax ram512x8 vhd not furnished tech generic vhd RAM 512x8 bit RAM model RAM 512x8 bit Generic RAM model Tab 5 2 RCCIPC FPGA technology files Currently the RCCIPC supports only the Microsemi Axcelerator family Users have to generate the correspondent technology memory file The following characteristics have to be used to generate a supported memory device Name ax ram512x8 Type Single Port RAM Write Width 8 Read Width 8 Write Depth 512 Enable Pin Not available Write Enable High Read Enable High Pipeline No Reset No Clock Single Tab 5 8 RCCIPC RAM Model characteristics The generated file has to be included in the appropriate directory according to the target FPGA family File name CAS RCCIPC DTS 0001 Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use Doc CAS RCCIPC DTS 0001 Issue 6 SITAEL RCCIPC Data Sheet ron Page 16 of 53 5 2 1 TESTBENCH Directory The TESTBENCH subdirectory contains the files needed to set up the RCCIPC core simulation environment The files needed for simulation are reported in the following table Name Description RCCIPC tb vhd RCCIPC
7. Signals Dir Description Clk In System clock Rst_n In System reset Nodeld 6 0 In RCCIPC Node ID BusSel Out Can Bus selection CanTx Out Can tx line CanRx In Can rx line HOSI A 12 0 In Address Bus HOSI WR In Data write or read neg command HOSI REQ In Bus ownership request HOSI Q 31 0 In Out Data Read Bus HOSI OEn In Output Enable Q contains data read when OEn is low HOSI_GNT Out Bus ownership grant HOSI READY Out Operation done flag IRQ 1 0 Out Interrupt lines It includes IRQ error lines Synch_rx Out Strobe to signal synch message reception Bus_switch Out Strobe to signal CAN bus switch condition Tab 7 1 RCCIPC periphery File name CAS RCCIPC DTS 0001 Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use Doc CAS RCCIPC DTS 0001 6 SITAEL RCCIPC Data Sheet ia d PN Page 25 of 53 The following Fig 7 2 and Fig 7 3 figures show the timing of the RCCIPC arbiter interface signals during read and write operations The interface timing charts are here described to allow users to correctly interface with the RCCIPC periphery HOSI prefix has been omitted for readability On the RCCIPC interface all the operations are word oriented in order to assure the correct management of
8. D 20 D 21 D 23 D 26 D 30 EB 1 D 0 D 1 D 3 D 4 D 6 D 8 D 10 D 12 D 14 D 17 D 20 D 22 D 24 D 27 D 31 EB 2 D 0 D 2 D 3 D 5 D 6 D 9 D 11 D 12 D 15 D 18 D 21 D 22 D 25 D 28 EB 3 D 1 D 2 D 3 D 7 D 8 D 9 D 13 D 14 D 15 D 19 D 23 D 24 D 25 D 29 EB 4 D 4 D 5 D 6 D 7 D 8 D 9 D 16 D 17 D 18 D 19 D 26 D 27 D 28 D 29 EB 5 D 10 D 11 D 12 D 13 D 14 D 15 D 16 D 17 D 18 D 19 D 30 D 31 EB 6 D 20 D 21 D 22 D 23 D 24 D 25 D 26 D 27 D 28 D 29 D 30 D 31 A dedicated register Tab 14 2 is used to control EDAC functionality The EDAC Enable flag is used to enable or disable EDAC protection on Memory modules A write operation on the register forces both single and double error flag to reset value Bit Number Description Reset value 7 0 reserved 0 8 Single error flag 0 9 Double error flag 0 10 EDAC Enable 0 11 reserved 0 15 12 reserved 0 16 reserved 0 17 reserved 0 Tab 14 2 EDAC error register The behaviour of the EDAC protection is illustrated in Fig 14 1 The EDAC error is generated when EDAC enable bit is set and EDAC error flag is not masked File name CAS RCCIPC DTS 0001 Issue6 docx RCCIPC Da
9. BPR PS1 HurriCANe PS Configuration RSJ can rst ccipc state active bus rx overflow HurriCANe amp err passive ME sll sll Paci soll sl asl Pcl cll M all sl ee ll sl 23 25 25 25 5 25 5 25 5 5 M ll le ee oe le ll cl al RCCIPC status bus off Constant value auto_op rx_err_cnt tx_err_cnt pdo_rx pdo_tx end_sdo sdo_abort sdo_dw IRQ status sdo_ul init_sdo nmt_cos edac_err can_err IRQ Mask clear serr derr EDAC error Mem en queue_en serr_mask derr_mask SS S a lal 3a a333 3 MEINEM NR BRENNEN BRBNmBNREBBNrBNNNrNr lt lt MIDIS Kee eerie KK M Dane Dans ee eae Das m cll il ancl Dll cll soll cll cll cll cll ll Il TPDO Trig tpdo_trig Tab 10 2 Initialization event for Configuration and Status Area Registers 10 1 1 IRQ handling As already defined in 7 1 1 the RCCIPC handles two IRQ lines e Transfer IRQ TRX_IRQ e Error IRQ ERR_IRQ User has to clear the IRQ request Three simple pseudo code examples of RCCIPC IRQ manager are written below TRX IRQ irq status IRQ status reg ARPDO IRQ irq status 0 ATPDO IRQ irq status 1 SDO IRQ irq status 2 INITSDO IRQ irq status 11 NMT CS IRQ irq status 12 NMT change state File name CAS RCCIPC DTS 0001 Issue6 docx RCCIPC Data Sheet T
10. can err rx of read HurriCANe amp RCCIPC status reg gt gt 7 Overflow error if msgin_full HurriCANe amp RCCIPC status reg 0 Clear error IRQ MASK CLEAR reg 0x8000000 clear Can error File name CAS RCCIPC DTS 0001 Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use SITAEL RCCIPC Data Sheet Doc CAS RCCIPC DTS 0001 Issue 6 Date 08 05 2014 Page 46 of 53 10 2 AOs Addressing The RCCIPC uses a single memory block of up to 512 words of 32 bits to store the Applications Objects The memory area is composed of the following sections as illustrated in Fig 10 1 RCCIPC private area it contains internal RCCIPC functional registers RPDO area it stores data to be transferred by TPDO e e RPDO area it stores data received by RPDO e e SDO Buffer it stores data to be transferred by SDO File name CAS RCCIPC DTS 0001 Issue6 docx SDO Buffer RCCIPC private Unused area Fig 10 1 RCCIPC Memory mapping In order to preserve the RCCIPC correct functionality writing accesses on RCCIPC private area are automatically rejected by RCCIPC RCCIPC Data Sheet The copyright of this document is vested in SITAEL
11. 250 FPGA target device The basic instructions to build a fitting project are included in 9 5 6 CONFIG File Directory The directory contains the VHDL configuration file produced by the Configuration tool All the VHDL files needed to perform the test listed in Tab 5 6 are available in VRP_CF sub directory 5 7 CONFIG Tool Directory The directory contains the executable file of the RCCIPC Configuration tool a Perl Tk script whose description is reported in 11 File name CAS RCCIPC DTS 0001_Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use SITAEL RCCIPC Data Sheet Doc CAS RCCIPC DTS 0001 Issue 6 Date 08 05 2014 Page 19 of 53 6 RCCIPC CONFIGURATION The RCCIPC is a reduced version of the CCIPC core designed to furnish a limited set of CANopen services using a pre defined Object Dictionary configuration 6 1 RCCIPC Object Dictionary The OD configuration is reported in Tab 6 1 In the last column is reported the Hardware implementation of each entry e Not available means that no HW logic is used to allow user to read or write the value because it has a pre defined value e Available means that HW logic is used to allow user to read or write the value
12. Byte received RX MSG 1 00000025 2 Byte received RX MSG 2 00000026 3 Byte received RX MSG 3 00000027 4 Byte received RX MSG 4 00000028 5 Byte received RX MSG 5 00000029 6 Byte received RX MSG 6 0000002A 7 Byte received RX MSG 7 0000002B 8 Byte received RX STATUS 0000002C not used RX len Tab 8 2 CAN MST registers of Receiver interface The clear irq function allows clearing CAN message IRQ and it performs the following command File name CAS RCCIPC DTS 0001 Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use Doc CAS RCCIPC DTS 0001 l 6 SITAEL RCCIPC Data Sheet e e Page 33 of 53 WRITE CAN 00000003 AO write SETUP 3 register where SETUP 3 register is defined below Name Address Hex Function 7 0 SETUP 3 00000003 RxClear Rst IRQclear TxReq RSJ The can set irq function allows enabling CAN IRQ on message reception and it performs the following command WRITE CAN 00000000 42 write SETUP O register where SETUP 0 register is defined below Name Address Hex Function 7 0 SETUP O 00000000 BPR RX irq Tab 8 3 reports the meanings of the constants ut
13. Description Value 0 sub index supported 2 0x1400 1 COB ID 200h NODEID 2 Transmission type 255h File name CAS RCCIPC DTS 0001 Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use Doc CAS RCCIPC DTS 0001 l 6 SITAEL RCCIPC Data Sheet iA NM Page 22 of 53 Descriptio Value sub index supported 2 0x1600 1 1 Mapping parameter 6000h 01h 20h 2 2 Mapping parameter 6000h 02h 20h Incoming RPDO is accepted only if it addresses to 1 RPDO COB ID 200h NODEID and it has a length of 8 byte otherwise it is filtered out by CAN interface The RPDO mapping parameters are static and the elaboration of the RPDO changes the content of Application Objects mapped at Index 6000h 6 2 2 Transmit PDO Service The RCCIPC supports only a single asynchronous event driven TPDO service with a static structure to define the Communication and Mapping parameters 0 sub index supported 2 0x1600 1 COB ID 180h NODEID 2 Transmission type 255h 3 Inhibit Time Oh not supported 4 Reserved Oh 5 Event timer Oh not supported 0 sub index supported 2 0x1800 1 1 Mapping parameter 6001h 01h 20h 2 2 Mapping
14. ES 33 8 4 Test Procedures Simulation eiie essen ener nannten nnn n 34 8 4 1 RCCIPC default tests eee nh hh h hah haha p aa pap anapi idaraan arinin 34 8 4 2 User defined tests eiisseeeiissssseseeee eene nnne nennen nnns nn nn a nn nnns sana sa sese araen sr nn nnns nnn 35 9 SYNTHESIS AND FITTING SCRIPTS eeeree ernannt aan aa na auam a a a aaa EIE IE PARE EN a 4E MEER RE aaa uIE 36 9 1 Micr s mi RT JAX UL cU 36 cE M SWNINCS IS c A OE TO AE AT N A E A E O A OE AE 36 CE MEN Duns E A E A A A O AA T 37 10 RCCIPC MEMORY MAPPING eren ntn nun an tuna nana aa aa a IE IER RENE HERE ERR E R40 HEN E RARE RE nnna 38 10 1 Configuration amp Status Area iius rota rara po sea sas eae RIR E EFE IA E oco EE pda pH EHE rE E Ea Papia 38 10 1 1 IRQ Handling PE 44 10 2 ADS AO OVS SSI ena NE A E esses ee 46 11 CONFIGURATION TOOL snoa aaa aa aa a a aaa a SR a aaa aai 47 Tit VADL Configuration Flessen ere EEEE ER EOE E EERE s 47 11 2 RCCIPC Config ration 100 T itear ensia rare erae EE EEES 48 12 RCCIPC Resource OCCUPATION 2eccsseccsserecsececcnencussensnsnensnenceanansasannsuensssnaneasaaesasenessnaneusaaesaseensnenesanaesaae 49 13 HCCIPC Timing Characteristics s rino tnesavdenennnnsncnnctdscececonnennnrtutiarrnecersnnstasteceysereonssasossienst 50 14 HCGCIPC Pottabilily 22er etica tec enean caudam esL aaron ua ren ae ck aat cae am panes yan casi docu un
15. Error on CAN interface IRQ 16 pdo rx clear Clear RPDO successfully processed IRQ 17 pdo tx clear Clear TPDO successfully processed IRQ 18 end sdo clear Clear SDO successfully completed IRQ 19 sdo abort clear Clear SDO abort detected IRQ File name CAS RCCIPC DTS 0001_Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use sit A E L RCCIPC Data Sheet a Doc CAS RCCIPC DTS 0001 Issue 6 Date 08 05 2014 Page 43 of 53 27 init_sdo_clear Clear Initiate SDO request accepted IRQ 28 nmt_cos_clear Clear RCCIPC change of state IRQ 30 edac_err_clear Clear EDAC error flag IRQ 31 can_err_clear Clear Error on CAN interface IRQ gt EDAC error Index 2003h Sub Index 5h Address 0x1130 field o lala reserved SENE 84 reserved l 2 sdo H F host ro rw rc rc ro rst 000000000000000000000 0 O O 0x00 Serr Single error flag This bit is auto cleared every time this register is written 9 derr Double error flag This bit is auto cleared every time this register is written 10 edac en Enable EDAC capability on RCCIPC The EDAC capability is disabled at start up User has to enabl
16. Fig 5 1 RCCIPC DB C CAN CORE gt LIBRARIES TESTBENCH SIM SCRIPT SYN SCRIPT FIT SCRIPT CONFIG FILE CONFIG TOOL 99000 Fig 5 1 RCCIPC database tree It is composed of the following directories SRC It includes all the VHDL files that constitutes the RCCIPC architecture SIM SCRIPT It includes the scripts and file used to compile the RCCIPC core SYN SCRIPT It includes files needed to perform the RCCIPC synthesis process FIT SCRIPT It includes files needed to perform the RCCIPC fitting process CONFIG FILE it includes the configuration files needed by the RCCIPC configuration tool CONFIG TOOL it includes the executable RCCIPC configuration tool 5 1 Software Requirement The minimum software requirement for Linux kernel and GNU tools versions that has been tested is the following File name CAS RCCIPC DTS 0001 Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use Doc CAS RCCIPC DTS 0001 Issue 6 Date 08 05 2014 Page 14 of 53 RCCIPC Data Sheet SITAEL Linux Kernel 2 6 27 11 generic GNU make 3 81 gcc version 4 3 2 Perl V5 10 0 perl Tk V804 028 VVVVV All the RCCIPC SW features has been tested using Ubuntu 8 10 Linux Kernel 2 6 27 11 g
17. MYFILE in test and redirect the output to the stimuli txt file contained in the MYSIM directory RCCIPCTestWriter pl MYFILE in YourSIM stimuli txt Now launch the simulation ncsim RCCIPC tb A gui File name CAS RCCIPC DTS 0001 Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use Doc CAS RCCIPC DTS 0001 l 6 S TAEL RCCIPC Data Sheet ia EN Page 36 of 53 9 SYNTHESIS AND FITTING SCRIPTS Synthesis and fitting scripts are included in the SYN SCRIPT and FIT SCRIPT directories Follow the simple instructions included in next sub sections for each technology The constraint file RCCIPC sdc included in the SYN SCRIPT directory keeps the system clock and peripheral timing constraints for the RCCIPC design and it is used during synthesis process Before proceeding with Synthesis and Fitting processes assure that all files needed to instantiate memory module for the selected technology have been correctly generated and copied in the correspondent directory see 5 2 1 9 1 Microsemi RT AX FPGA 9 1 1 Synthesis Go to SYN SCRIPT directory and open the RCCIPC prj file using the Synplify Pro Microsemi Edition tool Synplify Pro E 2010 09A 1 Z RCCIPC DB S
18. S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use Doc CAS RCCIPC DTS 0001 l 6 S TAEL RCCIPC Data Sheet e en Page 47 of 53 11 CONFIGURATION TOOL This section explains how to configure the RCCIPC core A simple configuration tool allows automatically generating the VHDL configuration file that has to be copied in the SRC directory in place of the RCCIPCconf vhd file 11 1 VHDL Configuration File The VHDL package configuration collects the VHDL constants used to configure the main aspects of the RCCIPC Core like interface technology and the default values of its configuration area objects The following constants are defined in the configuration file e TARGET_DEV it defines the RCCIPC core target technology o AXCELERATOR constant value for Microsemi Axcelerator device o GENERIC TECH constant for technology independent memory model e NODEID RCCIPC node ID Tthis value is used only in simulation mode During real mode this value is triggerd using the dedicated external pins Index 2002h SubIndex 01h e MSTID CONSHB constant value of Heartbeat consumer time index 101 6h o MST NODEID it defines the Node ID of the Master o CONS HB it defines the value of the heartbeat time PROD HB constant value of Heartbeat producer time index 1017h B DEF constant value of Default bus p
19. Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use Doc CAS RCCIPC DTS 0001 l 6 SITAEL RCCIPC Data Sheet e e Page 51 of 53 14 RCCIPC PORTABILITY 14 1 CAN Bus Controller The RCCIPC has been designed and in conjunction with the ESA HurriCANe core version 5 2 4 To insert this CAN Bus controller in the RCCIPC database all its source files have to be copied in the CAN CORE directory contained in SRC directory The CAN Bus Controller specific interface details are managed in the RCCIPC interface Block This VHDL module has to be re written if a controller other than HurriCANe is used 14 2 FPGA Technology The RCCIPC DataBase is equipped to support the following FPGA families e Microsemi RT AX family e Microsemi ProAsic family e Xilinx Virtex IV family For each one of these FPGA families the specific memory model is already available in the RCCIPC Database SRC LIBRARIES directory To insert specific technology memory model follows these steps 1 In SRC LIBRARIES folder create a MY TECH directory 2 Copy my technology memory vhd file in MY TECH directory Note that the target memory model supported by RCCIPC is 512x8 bit 3 Modify RCCIPCconf vhd file inserting a new technology constant For example
20. can err Error on CAN interface ERR IRQ The following register allows masking and clearing different CCIPC IRQ The following notation is used to mask and unmask IRQ 0 not masked IRQ propagated 1 masked IRQ not propagated gt IRQ Mask clear Index 2003h Sub Index 4h Address 0x112C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 1211 10 9 8 7 6 5 4 3 2 1 0 s ile leis 2 9 1318 8 ala 3 S 29m PIS I7 o ejgjeses t I WE IE le 9l 8 8 B BIER el ble Se 2 els mn S I 3 3 g F 2 S reserved E 928 A 5 5 A reserved 3 8 A A m D x Q x sdo__ host rw rw rw rw rw ro rw rw rw rw rw rw ro rw rw ro rw rw rw rw rst 000 0 0 0000000 0 0 0 0 0 0 0 0 0 0000000 0 0 0 Bit Number Mnemonic Description 0 pdo rx mask Mask RPDO successfully processed IRQ 1 pdo tx mask Mask TPDO successfully processed IRQ 2 end sdo mask Mask SDO successfully completed IRQ 3 sdo abort mask Mask SDO abort detected IRQ 11 init sdo mask Mask Initiate SDO request accepted IRQ 12 nmt cos mask Mask RCCIPC change of state IRQ 14 edac err mask Mask EDAC error flag IRQ 15 can err mask Mask
21. constant my technlogy std logic vector 3 downto 0 1001 4 Add the memory model instantiation to tech mem vhd file considering that CCIPC target memory ram512x8 supports the following signals Signals Direction Function Data 7 0 Write bus Q 7 0 O Read Bus WaAddress 8 0 Write Address RAddress 8 0 Read Address WE Write Enable active high HE Read Enable active high Clock Clock Tab 14 1 RCCIPC 512x8 target memory peripheral 14 3 Rad Hard Technique The RCCIPC has been developed considering Microsemi RTAX FPGAs as target technology Microsemi RTAX technology uses SEU Hardened Registers avoiding the need of Triple Module Redundancy TMR RCCIPC uses FPGA on chip RAM and it includes an Error Detection And Correction EDAC module in order to e detect and correct single bit error File name CAS RCCIPC DTS 0001 Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use Doc CAS RCCIPC DTS 0001 l 6 S TAEL RCCIPC Data Sheet e ces Page 52 of 53 e detect double bit error The equation below shows the Hamming code used during generation of EDAC bits EB EB 0 D 0 D 1 D 2 D 4 D 5 D 7 D 10 D 11 D 13 D 16
22. nS EP uS SENE NS cuan nn canna Erin 51 14 1 CAN Bus Gontroller ote ste a bei iE 51 142 FPGA 210 9 918 68 Met 51 14 3 Rad Hard Technig ME RE 51 File name CAS RCCIPC DTS 0001 Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use Doc CAS RCCIPC DTS 0001 Issue 6 SITA E L RCCIPC Data Sheet Date 08 05 2014 TT Page 6 of 53 1 INTRODUCTION This document acts as Reduced Can Controller IP Core data sheet and toolset user manual The Core features and its development environment are here described A quick start approach to RCCIPC should pass through the following steps 1 Set up the RCCIPC database inserting HurriCANe core see 5 2 2 The IP Core Database is presented in 4 with a detailed description its directories structure and main files 2 Run standard configuration tests The simulation environment set up is presented in 8 4 with explicit information about the files involved in the simulation process 3 Simulate application specific core instance the explanation how to customise the simulation environment and the compiler tool are provided in 8 4 Synthetize and Fit application specific configuration Section 9 provide users with basic instructions for synthetizing and fittin
23. parameter 6001h 02h 20h Only 1 TPDO COB ID 180h NODEID is defined for RCCIPC device The transmission of TPDO starts using the external trigger interface The TPDO mapping parameters are static and the content of Application Objects mapped at Index 6001h is transferred during TPDO elaboration 6 2 3 SDO Service RCCIPC is a SDO server and it supports only Block SDO transfer Download and Upload to access a single OD entry mapped at Index 6002h When an SDO Initiate request is received the RCCIPC checks the multiplexor field SDO transfer starts if Index field is equal to 6002h and sub index is equal to 1h otherwise SDO abort reply is transmitted The SDO service continues until entire entry is completely transferred RCCIPC is in charge of decoding size error sequence error and block size error In the next table the expected block size for each Buffer configuration is reported in table below 32 5 10 19 64 10 19 37 File name CAS RCCIPC DTS 0001 Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use SITAEL RCCIPC Data Sheet Doc CAS RCCIPC DTS 0001 Issue 6 Date 08 05 2014 Page 23 of 53 128 19 37 74 254 37 73
24. the EDAC protection mechanism 1 EDAC byte every 4 data bytes The RCCIPC works in Little Endian mode the least significant address contains the least significant byte of a word and the most significant address contains the most significant byte of the word Fig 7 2 Single Read CLK LCI OJT LI LT Lo OEn XXX e RBE OQ READY Fig 7 3 Single write Memory operation starts when Host device set REQ signal high The WR signal is used to identify which operation has to be performed 1 for write access 0 for read access GNT signal high determines when the bus is granted Afterwards data passing takes place only when READY signal is high During read access it signals that data are stable on Q bus while during write operation it signals that D bus has correctly sampled 7 1 1 IRQ amp External Trigger The RCCIPC interface is able to handle three IRQ lines File name CAS RCCIPC DTS 0001 Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use Doc CAS RCCIPC DTS 0001 l 6 SITAEL RCCIPC Data Sheet i ce Page 26 of 53 e IRQ O Transfer IRQ TRX IRQ e IRQ 1 Error IRQ ERR IRQ The TRX IRQ is used to si
25. the synthesis process clicking on Run button in the left top side of the window The Synthesis process generates in the specified output directory the RCCIPC edn file 9 1 2 Fitting When the synthesis process is completed in the FIT_SCRIPT directory open the RCCIPC adb file using the Microsemi Designer tool 8 Designer RCCIPC File View Tools Options Help osal aala Eeo Design Flow A ORA 5 E Back Annotate BSa Programming File MultiView Navigator SmartTime EI T Netlist emis b 170 Attribute Constraints Timing Viewer PinEditor ChipPlanner Editor Editor Analyzer Actel Designer Software Version 8 5 1 13 Release v8 5 SP1 Info The design Z RCCIPC_DB FIT_SCRIPT CCIPC adb was last modified by software version 8 5 1 13 Opened an existing design 2 RCCIPC_DB FIT_SCRIPT CCIPC adb Warning Your ACTEL SUMMIT license will expire in 10 days Design saved to file Z RCCIPC_DB FIT_SCRIPT RCCIPC adh Jan Errors Warnings Info 7 FAM Axcelerator DIE RTAX2505 PKG 208 CQFP Fig 9 2 Microsemi fitting tool Utilize the Options gt Device Selection menu on the left edge to change the Device speed grade package etc selections if needed Click on the Programming File button to start the fitting process The fitting process completes with generation of the RCCIPC pdb FPGA programming file File name CAS RCCIPC DTS 0001 Issue6 docx RCCIPC Data Sheet The copyri
26. third parties that may result from its use Doc CAS RCCIPC DTS 0001 l 6 SITAEL RCCIPC Data Sheet B ces Page 12 of 53 4 7 1 2 RPDO The RCCIPC supports only the Asynchronous elaboration modes for RPDO service associated to a static Application Objects of 8 bytes 6000h 4 7 1 2 1 Asynchronous The CCIPC starts the elaboration of this type of RPDO immediately after its reception 4 7 2 Service Data Object SDO The SDO service allows a client to access the Object Dictionary of a server node to read SDO Upload or write SDO Download specific Object Dictionary entries The RCCIPC supports only SDO Block service without CRC feature associated to a static Application Objects 6002h that user can configure The SDO transfer has to address the subindex 1 of entry 6002h to start correctly RCCIPC supports the SDO Abort service It is in charge signalling errors if a SDO protocol error is detected and stopping SDO transfer when an SDO abort is received File name CAS RCCIPC DTS 0001 Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use Doc CAS RCCIPC DTS 0001 l 6 S TAEL RCCIPC Data Sheet B e Page 13 of 53 5 IP CORE DATABASE The RCCIPC database tree is described
27. 0001 l 6 S TAEL RCCIPC Data Sheet e e Page 31 of 53 8 2 Input Stimuli Format The input stimuli for the CANOpen testbench are built as sequence of CAN messages and memory accesses on its host interface Both of them are written in the in test files using the intuitive format described below in Tab 8 1 Function Description can read msg CAN master read message received can clear irq CAN master clear message received IRQ can set irq CAN master enable message received IRQ start node NodelD CAN Master send a Enter Operational state request to NodelD stop node NodelD CAN Master send a Stop Node request to NodelD rst comm NodelD CAN Master send a Reset Communication request to NodelD rst node NodelD CAN Master send a Reset Application request to NodelD enter preop NodelD CAN Master send a Enter Pre Operational state request to NodelD Heartbeat NodelD CAN master send an Heartbeat message NodelD Master Node ID synch CAN Master send synch object rpdo COBID DATA CAN Master send RPDO message COB ID RPDO COB ID DATA RPDO data max 8 byte sdo ID TYPE OPT CAN Master sends SDO request ID ID of SDO client TYPE SDO type e BIKkIDL Index subindex size o lndex Pointed index o sublndex pointed sub index o size Block download size e BIKDL cflag byte num o cflag status of completed bit o byte nu
28. 01_Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use SITAEL Doc CAS RCCIPC DTS 0001 Issue 6 Date 08 05 2014 Page 17 of 53 RCCIPC Data Sheet e VHDL constants configuration file see 11 1 for file content e Input stimuli in in format see 88 2 for file format e Expected results file The VRP TB sub directory includes all the test procedures files and the full list of the RCCIPC test procedure is contained in Tab 5 6 Test Name Description TP5113 boot RCCIPC boot up message test TP5123 nmt s1 TP5123 nmt s2 TP5123 nmt s3 TP5123 nmt s4 RCCIPC NMT state transition test TP5133 NMT filtering RCCIPC NMT state transition vs Communication Objects filtering TP5143 hbt Heartbeat transmission test TP5213 asyncRPDO Asynchronous RPDO test TP5223 syncrx Reception of synch message TP5323 asynchTPDO Asynchronous RPDO test TP5443 DW block SDO Upload segmented test TP5453 UL block SDO Upload segmented test TP5462 AbortRx Reception of SDO abort test TP5462 ccs TP5462 IndexError TP5462 SizeError TP5462 blksize err TP5462 seq err SDO Error Decoding and Transmission of Abort messag
29. 130 29 28 27 26 25 24 2322 21 20 19 1817 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Ins 88223222 amm pg FG e Je P e e reserved E 9 2 8 S S S reserved S zi ads File name CAS RCCIPC DTS 0001 Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use SITAEL RCCIPC Data Sheet Doc CAS RCCIPC DTS 0001 Issue 6 Date 08 05 2014 Page 42 of 53 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdo host ro ro ro ro ro ro jro ro ro ro ro ro rst 0x0000 O O O o 0 0 O 00000 0 0 0 0 Bit Mnemonic Description IRQ line Number 0 pdo_rx RPDO successfully processed TRX_IRQ 1 pdo_tx TPDO successfully processed TRX_IRQ 2 end_sdo SDO successfully completed TRX_IRQ 3 sdo_abort SDO abort detected ERR_IRQ 9 sdo_dw Download SDO type 10 sdo_up Upload SDO type 11 init sdo Initiate SDO request accepted TRX IRQ 12 nmt cos RCCIPC change of state TRX IRQ 14 edac err EDAC error flag ERR IRQ 15
30. 146 127 19 The Buffer has to be transferred in two steps because the segment number exceed the upper limit of 127 The RCCIPC is in charge of decoding the error reported in Tab 6 3 but it replies using the General Error Abort code 08000000h Client Server command specifier not valid or unknown Data type does not match length of service parameter does not match Subindex does not exist Invalid Block size Invalid Sequence number General Error File name CAS RCCIPC DTS 0001 Issue6 docx Tab 6 3 RCCIPC Error Decoding RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use Doc CAS RCCIPC DTS 0001 l 6 S TAEL RCCIPC Data Sheet ia NM Page 24 of 53 7 INTERFACE This section is assigned to contain the final detailed description of the RCCIPC interface RCCIPC _ HOSI REQ NodelD Cfg area itf HOSI WR CanTx RCCIPC CanRx core L HOSI GNT Bussel SHOSI READY HOSI A AOs area itf HOSI Q AOs Area HOSI OEn IRQ s Synch rx Bus switch Fig 7 1 CANOpen slave node A simple description of each signal is reported in Tab 7 1
31. BA Advanced Microcontroller Bus Architecture AO Application Object CAN Controller Area Network CAN MST CAN Master CCIPC CANOPEN Controller IP core CiA CAN In Automation COB ID Communication Object Identifier DCF Device Configuration File EDAC Error Detection And Correction EDS Electronic Data Sheet FPGA Field Programmable Gate Array FSM Finite State Machine GUI Graphical User Interface HB Heartbeat HW Hardware IRQ Interrupt Request NMT Network Management OD Object Dictionary PDO Process Data Object RAM Random Access Memory RCCIPC Reduced CANOPEN Controller IP core ROM Read Only Memory RPDO Receive PDO SDO Service Data Object SW Software SYNC Synchronization Object TPDO Transmit PDO U8 Unsigned 8 U16 Unsigned 16 U32 Unsigned 32 UUT Unit Under Test VHDL VHSIC Very High Speed Integrated Circuit HW Description Language File name CAS RCCIPC DTS 0001_Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use Doc CAS RCCIPC DTS 0001 l 6 S TAEL RCCIPC Data Sheet ie mm Page 9 of 53 4 CANOPEN OVERVIEW In this paragraph an overview of CANOpen services supported by the Reduced CANOpen Controller IP Core RCCIPC core is provided The CAN in Automation CiA Standard CANopen Application Layer and Commun
32. CCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use Doc CAS RCCIPC DTS 0001 l 6 SITAEL RCCIPC Data Sheet e cen Page 10 of 53 3h Ntoggle 4h Ctoggle 2001 Oh Filler entry Oh 2002h 1h ID base 2h ID mask Oh th HurriCANe configuration 2h HurriCANe amp CCIPC status 2003h 3h IRQ status 4h IRQ mask clear 5h EDAC error 6h TPDO Trig Read Write Area 6000h Oh th RPDO AO1 2h RPDO AO2 6001h Oh th TPDO AO1 2h TPDO AO2 Oh 254h SDO Guoan User Defined Application Objects Tab 4 1 RCCIPC Object Dictionary Layout 4 3 Data Type The RCCIPC supports the following types to define the data type of each Application Object e Unsigned 8 U8 e Unsigned 16 U16 e Unsigned 32 U32 4 4 Object Type The RCCIPC supports the following Object types to define the type of the Application Objects entry e Variable VAR single value e Record multiple data field object composed by a combination of simple variables e Array multiple data field object composed by a combination of simple variable of the same data type 4 5 Network Management Objects The RCCIPC works as slave node in Network Manager service Through this service a master i
33. E ide Combinational Sequential Total aida Utilization MHz Axcelerator RTAX250S 2730 976 3706 5 87 74 16 6 ProAsic A3PE3000 4801 975 5776 5 7 6 19 6 Xilinx XC4VLX25 2250 924 1385 5 12 27 7 Tab 12 1 RCCIPC Area Occupation File name CAS RCCIPC DTS 0001_Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use SITAEL RCCIPC Data Sheet Doc CAS RCCIPC DTS 0001 Issue 6 Date 08 05 2014 Page 50 of 53 13 RCCIPC TIMING CHARACTERISTICS The RCCIPC timings characterization is reported in next tables and it gives an estimation of elaboration time in terms of clock cycles of the main CANopen features All the timings are characterized without considering congestions on CAN network and performing one task at time avoiding any processing delays at RCCIPC system level All timing values are measured using a 16 MHz clock frequency Heartbeat time Parameters Elab time Note Heartbeat producer HBP 1ms RCCIPC guarantees the correct management of Heartbeat producer time with granularity of 1ms Heartbeat counter reset consumer HBC 1ms 1ms HBC 1ms timer The reception of Heartbeat resets the Heartbeat Consumer In the worst case the mis
34. IPC tig 27KB tlg File Resource Sharing B RECIPE sdc sdc 450 bytes sdcFie 1 57 58 27 mag 2011 Retiming BB identify log 158 bytes log File 10 52 48 27 mag 2011 E run options txt 248 bx File 10 52 48 27 mag 2011 E scratchoroject prs 318 prs File 10 18 28 20 mag 2011 B traplog tig 1k tlg File 10 55 19 27 mag 2011 gt I RccIPC_ONLY_10 prj m ix Information Return Code 1 Run Time 00 05 49 m project save Z CCIPC DB1 9 SYN SCRIPT CCIPC GEN AX prj m project close Z CCIPC DB1 9 SYN SCRIPT CCIPC GEN AX prj project load Z RCCIPC DB SYN SCRIPT RCCIPC ONLY 10 prj maxfan hard3 is unrecognized option for current device IPIE H g TCL Script Messages Fig 9 1 Microsemi synthesis tool File name CAS RCCIPC DTS 0001 Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use Doc CAS RCCIPC DTS 0001 l 6 S TAEL RCCIPC Data Sheet e es Page 37 of 53 If necessary use the Implementation Option menu on the left edge to synthesis option e Device selection choose target FPGA e Options change synthesis option e Constraint add constraint files e Implementation results change synthesis output file destination e VHDL set VHDL options After configuration phase start
35. N Bit Rate bit s SDO Butter Type U32 Bus Manager Parameters Ttoggle 0 Ntoggle 0 DefautBus o 4 Consumer amp Producer HB Consumer HB o Master ID fo Producer HB oem in RSJ fo Ps2 CN PS1 le BPR fo SDO Butter Len 254 Fig 11 1 RCCIPC Configuration tool The user is in charge of defining the RCCIPC parameters and save them in the correspondent VHDL configuration file File name CAS RCCIPC DTS 0001 Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use Doc CAS RCCIPC DTS 0001 l 6 S TAEL RCCIPC Data Sheet ia PNE Page 49 of 53 12 RCCIPC RESOURCE OCCUPATION The results are obtained with the following RCCIPC configuration and refer to Post Place and Route process e 1 Node ld supported e 1 RPDOs and 1 TPDOs e 3 Application Objects o Array of U32 with 2 sub indexes o Array of U32 with 2 sub indexes o Array of U32 with 254 sub indexes e Consumer Heartbeat Time 5 s e Producer Heartbeat Time 5 s e Ttoggle 15 e Ntoggle 15 For Xilinx device Combinational field refers to Number of 4 input LUTs Sequential field refers to Number of Slice Flip Flops and Total field refers to total number of occupied slices E Cells EE Fmax m
36. VE PDO SOrVICO uestrae iuit e aeda aeaiia ea anaa da aid aiiai 21 File name CAS RCCIPC DTS 0001_Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use Doc CAS RCCIPC DTS 0001 l 6 SITAEL RCCIPC Data Sheet mE Page 5 of 53 6 2 2 Transmit PDO Service cccccccccccccccecececececececececacecacanacacacacacacacacananacacanacacauanauanauananananananananeees 22 G28 SD O TI IUE 22 HEN rli EE AE 24 7 1 1 IRQ amp External Trigger sees eene enne enne siena nnne s sans 25 Z L2 CAN Bus SGICCUON siciesessinsosndsunsentasissoundsidusucsigiaievsddusucsbaestieloddusucsbieladeveddusucsbiessieleddusucsdidusuesends 26 7 1 8 Node ID Acquisition and Modification esses esses enne nennen nnns nnn 26 7 1 4 Reset Distribution iiiisssssseeeeesessesees enne nnne nnn nnn nnn n nsns nena nnns ness s nena sisi sn esas sana sean nnns nnn 26 8 SIMULATION ENVIRONMENT eere nnn nnnm uana nana aa au anna aaa aa 4a NIRE IR DR RAE 4E NIE EIER E224 MESE E224 28 8 1 RCGIPG Gore Test Bench o e t e oa easet akneli ae Da rege EFE ERE PES Rt 30 8 2 Inp t Stimuli Formal EET EO T D LO PO 31 8 3 d PISTE REIS FE RE ENTE MT IE
37. YN SCRIPT RCCIPC ONLY 10 prj B File Edit View Project Run Analysis HDL Analyst Options Window Tech Support Web Help 2 x HE ENNET IR PAR E E E L EE s HP FR Fa PN 93 Synplify Pro Run y Ready n Open Project Project Files Design Hierarchy Implementation Directory ED RECIPC_ONLY_10 RCCIPC_ONLY_10 Actel Axcelerator RTAX2505 COFP208 Std Z RCCIPC_DB SYN_SCRIPT RCCIPC_ONLY_10 BR Close Project S RCCIPC ONLY 10 Z RCCIPC DB SYN SCRIPTIRCCIPC ONLY 10 prj Bere E 2 Name sze Type Modified aa Be RCCIPC_ONLY_ 10 3 8 backup Directory 16 53 52 18 mag 2011 B Change File a coreip Directory mmm dm Directory e mum a synlog Directory 16 47 55 18 mag 2011 o a syntmp Directory 11 26 07 19 mag 2011 2 Implementation Options BB RccIPC areasr 32 8 areasrr File 10 58 00 27 mag 2011 I B RCCIPC edn 2MB edn File 10 57 59 27 mag 2011 RR Add PER Implementation D rccipc tse 5 fse File 10 57 45 27 mag 2011 NNC B RCCIPC htm 349 bytes htm File 10 58 00 27 mag 2011 View Log B RcCIPC map 28 bytes map File 10 58 00 27 mag 2011 eee B rccirc so 210bytes so File 10 57 59 27 mag 2011 Frequency MHz RcCIPC srd 313 kB Netlist 10 57 45 27 mag 2011 e 16 RCCIPC stl 4MB Netist RTL 10 55 12 27 mag 2011 Auto Constrain dk RCCIPC srm 18MB Netlist Gate j B Rcapc sr 80 kB str File FSM Compiler F7 RCCIPC srs 4MB Netlist RTL FSM Explorer B RcaPC szr 21kB sar File D RCC
38. arameter index 2000h Sub Index 01h T TOGGLE constant value of Ttoggle parameter index 2000h Sub Index 02h N TOGGLE constant value of Ntoggle parameter index 2000h Sub Index 03h HuCANe Cfg default value of the HurriCANe configuration Index 2003h Sub Index 01h o RSJ VAL RSJ default value o PS2 VAL PS2 default value o PS1 VAL PS1 default value o BPR VAL BPR default value e RCCIPC ST default value of the RCCIPC status register Index 2003h Sub Index 02h o AUTO OP defines the possibility of the RCCIPC to enter automatically in Operational state at the end of the initialization phase e SDO BUF TYPE defines the characteristics of the SDO buffer e SYS FREQ defined the system frequency File name CAS RCCIPC DTS 0001 Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use RCCIPC Data Sheet SITAEL Doc CAS RCCIPC DTS 0001 Issue 6 Date 08 05 2014 Page 48 of 53 11 2 RCCIPC Configuration Tool The RCCIPC Configuration tool allows user to simply define the configuration parameters specified in the previous paragraph 9 8 RCCIPC configuration N File RCCIPC Set Up RCCIPC Configuration Parameters BaseNodelD i Autoop Target Technology AXCELERATOR x System Clock MHz he CA
39. d in the Application Objects area are reset e Reset Communication the registers defined in the Communication Objects area are reset To act as asynchronous resets these three signals are combined with the power on reset and synchronized using a dedicated circuit whose structure is reported in Fig 7 5 Fig 7 5 Reset synchronizer Due to their critical functions the user has to verify that no timing violations on these reset signals has been arisen after the Place and Route process A static timing analysis has to be performed on the output signals of the second Flip Flip of the synchronizer circuit Here below the paths that has to be verified e Bus Switch SW_RST rst_n Q 0 e Reset Application AO RST rst n Q 0 e Reset Communication COM RST rst n Q 0 File name CAS RCCIPC DTS 0001 Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use Doc CAS RCCIPC DTS 0001 l 6 S TAEL RCCIPC Data Sheet ia NM Page 28 of 53 8 SIMULATION ENVIRONMENT This section gives the instructions to set up and run simulation of the RCCIPC core The simulation set up procedure is based on the make tool and all the tools specific commands are included in the Makefile script Compilation analysis and elabora
40. deceiver gentesereean divert nenetbivecmertenintaeaetinees 12 4 7 2 Service Data Object SDO sridi aniis aae eaaa iaa aa Eaa E AN Ee i Ei AiE ia 12 Jj dsel i gs up YlpplM T 13 5 1 Soltwar TO QUINTON ss qeu tr ae idea eR petite Ur Ru Mh pU EE 13 as SL Os 2 6 0 p ooncndusx uU tuc ttu IM dM aL EA NDS LIES 14 5 21 EIBRARIES Directory e ped Ua es ERE ee das scab REY Dee e eda iss Das Rea ads 15 521 TESTBENCHIDirectoty hti t EE Ee i en AR EFE uh das Lax D sh sass ted ened iss tances tals 16 5 22 CAN Bus Conttoller i btt b ti o nnda ava a veia be desea Sonne ede dn YER edad Desa cs 16 53 SIM Soript Directory Tp 16 5 4 SYN Soript ee 2110 g T E rcr 17 5 5 Ecco pE nie Tm 18 5 6 CONFIG Elle DIGCIOFV ei a ep L n URP UM AEDEM DUDEN E ERR 18 BF CONFIG Tool DIEGO EMT MITTM 18 RCCIPC CONFIGURATION ext ciie oput ruat y no nam ng kS DE Na IE XS tn kn ERE SERERE RS FA Ru RE RS FE Sea ER Kock SNR Paca eR Fe SEES E aac Nn u 19 6 1 RCCIPC Object ICN scade cactus turo nar deus tea pun pue ER Lope eheu aez PESE MR pin Ep ERd Mes 19 6 1 1 Configurable Parameters sss eiie sitne nnns th nne na niente enne 19 6 1 2 Application Objects ssisssissssssssssiisss einen nnne nnne nnne trennen sina ns sites eren n ases nnns en nnns nnn nnn 20 62 RCCIPC CANOpen Services essssissssiisssss eese s esent nnns hin a thes nnns ssh nna 21 6 2 4 RECEI
41. e it after RCCIPC initialization Since Double error detection represents a critical condition for the core because the management of wrong values can compromise the RCCIPC behaviour it is strictly recommended that user reset the RCCIPC core if this error occurs gt aoa eee 20038 ounces 6h Address 0x1134 field tpdo_trig sdo host wo rst 0x0 31 0 tpdo_trig A write operation on this register enables the transmission of the asynchronous TPDO The following table shows which events cause the inizialization of the registers eee brm sO Constant value Bdefault b def y y n n Ttoggle t toggle y y n n Ntoogle n toggle y y n n C toggle c toggle Constant value Node Parameters nodepar sO uz E Constant value ID Base node_id y n n n Value sampled at boot RCCIPC status amp st amp cfg sO Constant value File name CAS RCCIPC DTS 0001_Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use Doc CAS RCCIPC DTS 0001 l 6 S TAEL RCCIPC Data Sheet e e Page 44 of 53 Event Reset Reset Application Communication Regisien feld Power On Bus Switch Note Configuration
42. e test TP5513 hbc tce Heartbeat reception and Ttoggle expiration test TP5523 Ctoggle Ctoggle expiration and Bus switch test TP5613_parallel 1 TP5623_parallel 2 RCCIPC handling of different task simultaneously test Tab 5 6 RCCIPC test list The ADDON_TB sub directory includes a set of additional tests that are performed to cover more CANopen protocol aspects The instructions to run all test procedures are provided in 8 4 5 4 SYN Script Directory The SYN_SCRIPT houses the files needed to synthetize the RCCIPC for RTAX technology Two types of script files are included e The project prj files holds the reference to all the VHDL source files and includes the technology specific settings e The constraint sdc files keeps the system clock and peripheral timing constraints for the RCCIPC design The section 89 provides the user with a basic procedure for the core synthesis with Synplify Synthesizer Tool File name CAS RCCIPC DTS 0001 Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use Doc CAS RCCIPC DTS 0001 Issue 6 SITAEL RCCIPC Data Sheet aimee Page 18 of 53 5 5 FIT Script Directory FIT SCRIPT directory includes the project targeted to RTAX
43. eartbeat time PROD HB 2002h_ Node parameters NODEID used during simulation phase Redundancy Management T_TOGGLE 2000h N_TOGGLE B DEF File name CAS RCCIPC DTS 0001 Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use Doc CAS RCCIPC DTS 0001 l 6 SITAEL RCCIPC Data Sheet ia Page 20 of 53 RCCIPC status amp configuration RSJ VAL PS1 VAL PS2 VAL BPR VAL AUTO OPER EDAC REG VAL 2003h Tab 6 2 Configurable parameters vs OD entry The explanation on its parameter is here reported e NODEID This field allows defining the RCCIPC Node ID This value is used only for simulation scope During normal operation the NodelD is defined using dedicated input port pins e RSJ VAL PS1 VAL PS2 VAL and BPR VAL These constants have to be set to obtain the desired Bit Rate according to system frequency value RCCIPC supports a working frequency in the range from 10MHz to 16 MHz The supported Bit Rate are g 1 Mbps 500 Kbps 250 Kbps 125 Kbps e CONS_HB It allows specifying the expected Heartbeat cycle time expressed with millisecond granularity and the COB ID of Master node e PROD_HB It allows specifying the cycle time of the heartbeat object expressed with millisec
44. eneric and Ubuntu 9 10 Linux Kernel 2 6 31 22 generic 5 2 SRC Directory The SRC directory contains the source files that fully describe the RCCIPC core in behavioural synthesizable VHDL format and into separated subdirectories the additional files needed to map RCCIPC in specific technologies to compose its simulation environment and to house the low level CAN controller core The RCCIPC proper VHDL source files are listed in Tab 5 1 RCCIPCconf vhd RCCIPC configuration file CANopen_pkg vhd CANopen constant parameters mem_tech vhd Definition of memory blocks using specific technology EDAC_pack vhd Definition of EDAC package RCCIPC vhd RCCIPC top level arbiter vhd Memory arbiter RCCIPC_interface vhd RCCIPC CAN interface controller ccipc_can vhd RCCIPC can module It embodies both RCCIPC_interface and CAN controller entities NetworkManager vhd Network Manager event handler vhd Event handler OD handler vhd CANopen communication protocol handler RCCIPC FSM vhd FSM implementation of the CANopen protocol services edac calc vhd EDAC module adder vhd Adder module reset sync vhd Reset synchroniser module MemRF vhd Register handler module Makefile VHDL compilation file Makefile mem Technology Makefile Tab 5 1 RCCIPC SRC files The RCCIPC architecture composed of e CAN interface composed by
45. field it associates a mnemonic name to register field e sdo it indicates the access type supported via SDO e host it indicated how Host can access to the register e rst it indicates the reset value of the field The following notation is used o Binary single or double quotes indicate binary values o Hexadecimal Oxnn notation indicates an Hexadecimal number o RST VAL the reset value is indicated in the correspondent parameter available in the CCIPC configuration file CCIPCconf vha Three different access types are defined e ro Read Only e rw Read Write File name CAS RCCIPC DTS 0001 Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use SITAEL RCCIPC Data Sheet Doc CAS RCCIPC DTS 0001 Issue 6 Date 08 05 2014 Page 39 of 53 e rc Read and clean A write access only cleans the value of the register Redundancy Management nex ee ae Index Oh SERT AGGIE 15 14 13 12 11 10 field IU brm s0 sdo host ro ro rst 0x000000 0x4 7 0 brm sO Sublindex 0 of Bus Redundancy management entry Bdefault Index 2000h E index 1h RE 0x1044 31 30 2928 2726 2524 2322 sja E lo field c sdo zi ho
46. g of the RCCIPC core instance in the Microsemi RTAX250 technology RCCIPC area occupation and operating frequency for different FPGA technologies are reported in 12 In 13 an estimation of elaboration time of the main CANOpen features is reported A brief description of RCCIPC portability is illustrated 14 File name CAS RCCIPC DTS 0001_Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use sit A E L RCCIPC Data Sheet a Doc CAS RCCIPC DTS 0001 Issue 6 Date 08 05 2014 Page 7 of 53 2 DOCUMENTS 2 4 Reference Documents RD 1 CiA Draft Standard 301 Version 4 02 RD 2 CiA Draft Standard 306 Version 1 3 File name CAS RCCIPC DTS 0001 lIssue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use Doc CAS RCCIPC DTS 0001 l 6 SITAEL RCCIPC Data Sheet e mm Page 8 of 53 3 LIST OF ACRONYMS AND ABBREVIATIONS Abbreviation Meaning AHB Advanced High performance Bus AM
47. ght of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use Doc CAS RCCIPC DTS 0001 l 6 S TAEL RCCIPC Data Sheet i ce Page 38 of 53 10 RCCIPC MEMORY MAPPING The RCCIPC utilizes two different memory areas e Configuration amp Status area this is implemented in sparse registers assigned to control the main parameters inside the Core e Application Objects area this area includes the application objects shared between the RCCIPC and host device 10 1 Configuration amp Status Area The RCCIPC Configuration amp Status area is composed of the following OD entries Cfg Index Subindex Register Name Addrass Obj Type Oh Redundancy 0x1040 U8 Management th Bdefault 0x1044 U8 20008 oh Ttoggle 0x1048 U8 3h Ntoggle 0x104C U8 4h Ctoggle 0x1050 U8 Oh Node 0x1094 U8 2002h parameters th ID base 0x1098 U8 Oh RCCIPC status 0x109C U8 amp configuration th HurriCANe 0x10A0 U32 configuration 2h HurriCANe amp Ox10A4 U32 2003h RCCIPC status 3h IRQ status 0x1128 U32 4h IRQ mask clear 0x112C U32 bh EDAC error 0x1130 U32 6h TPDO Trig 0x1134 U32 Tab 10 1 Configuration Register mapping Each register is defined in next tables Each table is composed of the following fields e
48. gnal the following conditions e reception of Initiate SDO transfer e successful elaboration of an SDO transfer e successful elaboration of asynchronous T R PDO e NMT state transition The ERR IRQ line is used to inform the Host that an error has been detected These signals have to be cleared by user through dedicated registers described in 10 1 Two additional lines have been used to inform the Host on reception of the Synch message and when a bus switch event occurs These bits are active for a single clock cycle 7 1 2 CAN Bus Selection The RCCIPC manages the redundancy algorithm and bus multiplexing that is RCCIPC implements a single CAN controller capable to handle two physical busses The BusSel output signal select which of the two CAN busses is logically connected to the core according to the Redundancy algorithm Since the BusSel output signal is stable to 0 or to 1 according to the active bus selected by the redundancy manager it can be used as control signal for the multiplexer which selects the active CAN transceiver 7 1 3 Node ID Acquisition and Modification The RCCIPC acquires information on base Node ID using a dedicated external signals NodelD in Tab 7 1 in the first eight clock cycles after the reset phase In Fig 7 4 the behaviour of this interface is explained CLK a fh S Rst_n Node ID A Base Nolde ID Fig 7 4 Acquisition of Node ID
49. he copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use Doc CAS RCCIPC DTS 0001 l 6 S TAEL RCCIPC Data Sheet d e Page 35 of 53 gt cd YourSIM Create a symbolic link to the RCCIPC test shell script gt ln s RCCIPC DB SIM SCRIPT RCCIPC test sh gt In s RCCIPC DB SIM SCRIPT RCCIPCTestWriter pl To run tests included in VRP TB directory and reported in Tab 5 6 launch the RCCIPC test sh command specifying the test name RCCIPC test sh name TP5113 boot To run tests included in ADDON TB directory launch the RCCIPC_test sh command specifying the path pointing the test gt RCCIPC_test sh dir RCCIPC DB SIM SCRIPT ADDON TB TP5123 AutoOperational S1 The whole list of ADDON TB tests is reported in the README txt file available in the main RCCIPC DataBase directory At the end of simulation if the test is passed the following messages appears Simulation success files match Otherwise the test returns Simulation failure files differ 8 4 2 User defined tests To create a new test procedure generate the specific test file MYFILE in using the instructions defined in Tab 8 1 Using the RCCIPCTestWriter pl script compile the
50. he copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use Doc CAS RCCIPC DTS 0001 l 6 S TAEL RCCIPC Data Sheet e en Page 45 of 53 if ARPDO IRQ while elab_rpdo lt Elaborate Data gt IRQ MASK CLEAR reg 0x10000 clear RPDO part of PDO IRQ reg if ATPDO IRQ while elab_tpdo lt Elaborate Data gt IRQ MASK CLEAR reg 0x20000 clear TPDO part of PDO IRQ reg if SDO_IRQ lt Elaborate Data gt IRQ MASK CLEAR reg 0x40000 clear SDO IRQ if INITSDO_IRQ IRQ MASK CLEAR reg 0x8000000 clear SDO IRQ if NMT_CS nmt state HurriCANe amp RCCIPC status reg amp Ox1F gt read NMT state IRQ MASK CLEAR reg 0x10000000 clear SDO IRQ ERROR IRQ irq status read IRQ status reg Manage error IRQ MASK CLEAR reg ERROR CLEAR BIT clear specific error bit The receiver message overflow condition is associated to the HurriCANe error flag bit 15 of IRQ status register Before clean the IRQ status register user has to clear the rx overflow error by writing the correspondent bit of HurriCANe and RCCIPC status MsgIn Queue full error irq status read IRQ status reg can err irq status 15 if
51. ication Profile RD 1 is used as reference document for the CANopen standard 4 1 Communication Model The RCCIPC is designed to act as e SLAVE node in a CANopen network responding to a master request e SERVER node for SDO Download and Upload services e PRODUCER and CONSUMER node for PDO and Heartbeat services e CONSUMER of SYNC message 4 2 Object Dictionary The RCCIPC supports the Object Dictionary implementation A limited set of Object Dictionary entries are supported as shown in next table The RCCIPC Object Dictionary foresees a dedicated area entries starting from index 2000h that defines RCCIPC specific parameters and two macro areas Read Write and Read Only that allows user to define its specific Application Objects 1016h Oh Consumer Heartbeat timer th Master amp Consumer Heartbeat time 1017h Oh Producer Heartbeat time SDO Server Parameter Oh Server SDO Parameter 1200h 1h COB ID client server 2h COB ID server client RPDO Parameter Oh RPDO Communication 1400h th COB ID 2h Transmission Type Oh RPDO Mapping Teguh 1h 8h Mapping Parameter TPDO Parameter Oh RPDO Communication th COB ID 2h Transmission Type 1800h ran Inhibit Time 4h Reserved bh Inhibit Time Oh TPDO Mapping neon ih 8h Mapping Parameter RCCIPC Parameter Oh 2000h 1h Bdefault 2h Ttoggle File name CAS RCCIPC DTS 0001 Issue6 docx R
52. ield in Tab 7 2 558 Modified Address value in Tab 7 3 Modified Default values of Sub Index 0 and 1 of Index m Ww 2003 in Tab 9 1 31 Modified Default values in Tab 9 3 Ba x In Tab 9 5 IRQ status register added SDO Dw and UI flags 34 Modified TRX IRQ pseudo code box 34 Removed reference to SYNCH IRQ management Updated 11 RCCIPC Resource Occupation SUEUTe Updated 812 RCCIPC Timing Characteristics All In all document replaced Actel reference with Microsemi In 4 explained in more details the CANopen features supported by RCCIPC In 5 1 highlighted that SW requirement refers to the minimum that has been tested In 5 2 added Fig 5 2 adding more details of SRC 31 10 2012 a mes 16 Added 5 2 1 with a detailed description of Libraries directory A description of RAM model characteristics has been included Incorporate previous TESTBENCH directory section in 85 2 1 Renamed 5 2 2 Added also HurriCANe file list In 6 2 added basic information on FSM implementation I 10 14 14 16 18 0 4 6 0 1 2 4 4 13 14 15 16 16 21 The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use Doc CAS RCCIPC DTS 0001 Issue 6 SITAEL RCCIPC Data Sheet i Page 3 of 53 Docume
53. ilized in the test files Name Value Description R_ST_ADDR 10A4h Pointer to HurriCANe amp RCCIPC status register Index 2000 Sublndex 2 R_IRQ_ST_ADDR 1128h Pointer to IRQ status register Index 2000 SubIndex 4 R_IRQ_MK_CL_ADDR 112Ch Pointer to IRQ mask clear register Index 2000 SubIndex 5 Tab 8 3 Test Constant value 8 3 Output Test Log File The RCCIPC test bench furnishes a simulation output Log file report txt that reports all the traffic recorded on CAN bus and the memory accesses performed by Host interface The Log file helps user during the debug phase to understand what data are effectively exchanged between CAN Master HOST and RCCIPC The following information are reported in the Log File 1 Time stamp time reference expressed in ns 2 Access Type this field reports the type of operation to be executed a READ read operation b WRITE write operation 3 Peripheral this field defines which peripheral performs the operation a CAN CAN Master b EXT Host interface 4 Address Operation Address The address refers to CAN Master internal registers when Peripheral field is CAN while it refers to RCCIPC Configuration Area or RAM area when Peripheral field is set to EXT 5 Data Data read or write according to Access type An example of Log File without time stamp information is reported in next table with a simple description of the operations performed File
54. information FPGA samples Node ID between the 7 and 9 clock cycle after reset Then user can re assign corresponding pins to different custom functions without affecting the RCCIPC functionalities RCCIPC utilizes this information to perform filtering function of the incoming CANopen messages and to correctly set the COB ID of message to be sent In this way the Node ID can be modified without requiring a new FPGA programming but only a reset procedure in order to allow RCCIPC to re sample the new Node information 7 1 4 Reset Distribution The RCCIPC is provided of an active low asynchronous Power On Reset rst n This reset allows initialize all the sequential logic available in the RCCIPC in an asynchronous way File name CAS RCCIPC DTS 0001 Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use Doc CAS RCCIPC DTS 0001 Issue 6 SITAEL RCCIPC Data Sheet ip ME Page 27 of 53 Together with this global reset the RCCIPC has three additional signals that act as asynchronous reset to re establish the default values of RCCIPC internal registers These signals are associated to following conditions e Bus switch the whole RCCIPC core is reset including the CAN core e Reset Application the registers define
55. m number of bytes to download e BlkEndDW e BIKIUL Index subIndex Blksize o lndex Pointed index o sublndex pointed sub index o Blksize Block size e BIKUL ackseq Blksize o ackseq Sequence number of last segment rx o Blksize Next Block size e EndBIKUL e Abort Index subIndex abort code o lndex Pointed index o sublndex pointed sub index o abort code transmitted abort code Waitsegm num seg CAN master wait for num seq RCCIPC SDO messages during the SDO block upload service Fillbuf ADDRESS len Host device fills len consecutive SRAM locations with static data starting from Address Trig STPDO NUM Host Device requests the transmission of the TPDO NUM TPDO Waitirgq SIRQ TYPE Wait for a specific IRQ File name CAS RCCIPC DTS 0001 Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use Doc CAS RCCIPC DTS 0001 Issue 6 Date 08 05 2014 Page 32 of 53 RCCIPC Data Sheet SITAEL Function Description IRQ TYPE e Canmsg CAN master waits rx message IRQ Error Host device waits RCCIPC error IRQ Pdo Host device waits the end of PDO processing Sdo Host device waits the end of SDO processing Synch rx Host device waits sy
56. match between the expected Heartbeat expiration and the real Heartbeat expiration is 1ms at maximum Event Driven As nchronous TPDO Parameters Elaboration time Note TPDO elaboration Trepo 426 Time to Elaborate TPDO Parameters Asynchronous RPDO Elaboration time Note RPDO elaboration Treno 508 Time to Elaborate RPDO SDO Download Block Parameters Elaboration time Note Initiate request Tgown 410 Elaboration of Initiate Download request Download Segment Tap 958 Elaboration of Download request 7 byte request Download Segment Tgpwtseg 1160 Elaboration of Last message of a segment If response another segment has to be received TapwR 610 Elaboration of Last message of a segment If last segment has been received End Block Request Tapwena 572 Elaboration of End SDO Block Download request SDO Upload Block Parameters Elaboration time Note Initiate request Tepupin 476 Elaboration of Initiate Upload request Start request TBupstart 166 Elaboration of Upload Start request Upload segment Tau 814 Elaboration of 1 Upload segment 7 byte request Block segment Tui seg 320 If last segment has been sent response TaupinR 304 If another segment has to be sent End Block request TaupEnd 208 Elaboration of End SDO Upload Block request File name CAS RCCIPC DTS 0001 Issue6 docx RCCIPC Data
57. name CAS RCCIPC DTS 0001_Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use Doc CAS RCCIPC DTS 0001 l 6 SITAEL RCCIPC Data Sheet ia EN Page 34 of 53 Access Per Address Data Description Type z RITE CAN 00000000 00000042 Write CAN Master SETUP O register RITE CAN 00000003 000000A0 Write CAN Master SETUP 3 register EAD CAN 00000020 000000E0 EAD CAN 00000021 00000041 Read CAN Master Arbitration registers EAD CAN 00000022 00000000 RX ARB 0 RX ARB 3 EAD CAN 00000023 00000030 EAD CAN 00000024 00000000 EAD CAN 00000025 00000030 EAD CAN 00000026 0000008D EAD CAN 00000027 00000078 Read CAN Master Message registers EAD CAN 00000028 00000000 RX MSG 0 RX MSG 7 CAN 00000029 00000000 EAD CAN 0000002A 00000000 EAD CAN 0000002B 00000000 EAD CAN 0000002C 00000001 Read CAN Master RX STATUS register EAD EXT 000010A4 00000810 HOST reads RCCIPC HurriCANe amp RCCIPC Status register EAD EXT 00001128 00001000 HOST reads RCCIPC IRQ status register RITE EXT 0000112C 10000000 HOST wri
58. nch object reception flag e Bus switch Host device waits bus switch flag Host device reads len word starting from Address Host device write data word at specific Address Parser module waits for time us before reading next instruction Dev read Address len Dev write Address data Waitus time Tab 8 1 Stimuli instruction definition The read msg function returns ID Data and length of CAN message received and it is composed of the following command READ CAN 00000020 read RX ARB O register READ CAN 00000021 read RX ARB 1 register READ CAN 00000022 read RX ARB 2 register READ CAN 00000023 read RX ARB 3 register READ CAN 00000024 read RX MSG O register READ CAN 00000025 read RX MSG 1 register READ CAN 00000026 read RX MSG 2 register READ CAN 00000027 read RX MSG 3 register READ CAN 00000028 read RX MSG 4 register READ CAN 00000029 read RX MSG 5 register READ CAN 0000002A read RX MSG 6 register READ CAN 0000002B read RX_MSG_7 register READ CAN 0000002c read RX STATUS register The table below explains functions of the CAN MST receiver interface registers Name Address Hex Function 7 0 RX ARB 0 00000020 ID 10 iD g ipfe 107 Ife impp D4 D s RX ARB 1 00000021 ID 2 ID 1 ID 0 not used 00000 RX ARB 2 00000022 not used RX ARB 3 00000023 not used RX MSG 0 00000024 1
59. nt title RCCIPC Data Sheet EC NN 04 12 2012 52 CRIMEN File name CAS RCCIPC DTS 0001_Issue6 docx Modified tests 51 Added 7 1 4 with a simple description of Reset distribution inside RCCIPC In 8 modified instructions for CCIPC simulations and test execution Added 8 3 describing simulation Log file In Tab 8 1 modified BIKDL parameter and rst_comm function Split 8 4 in two paragraphs 8 4 1 RCCIPC default tests and 8 4 2 User defined 10 has been completely reviewed In 13 replace Segment with Block in Parameter filed of SDO Download Block and SDO Upload Block In 14 3 inserted additional information on EDAC feature implemented in RCCIPC n 4 1 added that RCCIPC is a SYNC consumer n 4 5 3 substituted Ctoggle with Ntoggle In 4 7 2 added that SDO has to address subindex 1 to correctly start n 6 2 removed warning on FSM implementation n 7 added information on RCCIPC endianness In Tab 8 1 added explanation of cflag parameter of BIKDL function n 89 1 1 removed warning on FSM implementation In 10 1 changed host access type of IRQ Mask clear register In 13 modified Note about Heartbeat consumer counter reset parameters name of SDO Download and Upload Block to match the standard CANopen nomenclature RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its u
60. ond granularity e T TOGGLE It defines the number of Heartbeat event that can occur before Bus switching e N TOGGLE It defines the maximum number of bus switching e B DEF It defines the Default Bus e AUTO OPER It defines if RCCIPC enters automatically 1 or not 0 in Operational State after initialization phase e EDAC REG VAL It defines the value of the EDAC error register 6 1 2 Application Objects RCCIPC OD layout foresees only 3 Application Objects which have the following structure 0 sub index supported 2 0x6000 1 RPDO AO 1 U32 2 RPDO AC2 U32 0 sub index supported 2 0x6001 1 TPDO AO1 U32 2 TPDO AO2 U32 0 sub index supported 255 OXG008 3 954 AO mn U8 U16 U32 File name CAS RCCIPC DTS 0001_Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use Doc CAS RCCIPC DTS 0001 Issue 6 Date 08 05 2014 Page 21 of 53 RCCIPC Data Sheet SITAEL The RPDO AO and TPDO AO entries are composed of 2 sub indexes of U32 and are used to store the data values elaborated during RPDO and TPDO transfers respectively The RCCIP AO entry represents a single buffer used during SDO transfers It supports only 32 64 128 and 254
61. re test bench that has been used to test the CANopen functionalities supported by the RCCIPC slave node is presented in Fig 8 1 RCCIPC_tb Parser Memory bus gt Memory req gnt RCCIPC S Core 9 i Fig 8 1 RCCIPC test bench The test bench module called RCCIPC tb consists of Parser module it traduces input stream from Stimuli file in specific requests on CAN MST or UUT Memory interface emulating the external device It controls CAN MST and emulates host device in the simulation test CAN MST it implements a CAN controller module based on micro controller interface that allows exchanging CAN data frame with the UUT This module works with an input frequency of 16MHz and with 1Mbps of CAN bit rate UUT itis the Unit under test and it implements the RCCIPC slave node The files used during the test procedure are Stimuli it contains the test instruction used to drive the CAN MST interface and also to perform access on AOs module emulating the behaviour of a generic external device interface Test Log this task logs any transition on UUT interface File name CAS RCCIPC DTS 0001 Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use Doc CAS RCCIPC DTS
62. s in charge of managing the status of each slave in the CAN net 4 5 4 Module Control Services The RCCIPC supports the following services File name CAS RCCIPC DTS 0001_Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use Doc CAS RCCIPC DTS 0001 l 6 S TAEL RCCIPC Data Sheet iA T Page 11 of 53 Start Remote Node RCCIPC enters in OPERATIONAL state Stop Remote node RCCIPC enters in STOP state Enter Pre Operational RCCIPC enters in PRE OPERATIONAL state Reset Node RCCIPC enters RESET APPLICATION state Reset Communication RCCIPC enters RESET COMMUNICATION state RCCIPC supports a special feature that allows RCCIPC to enter directly in OPERATIONAL state at the end of initialization phase when a dedicated flag is active 4 5 2 Bootup Service RCCIPC supports the Boot up service signaling to the Master that the initialization phase ended 4 5 3 Error Control Service and Bus Redundancy The RCCIPC supports the Heartbeat protocol to detect failures in a CAN network RCCIPC is in charge of receiving and transmitting Heartbeat messages When RCCIPC does not receive the Heartbeat message from the Master node it generates an Heartbeat event This event is used by RCCIPC to implement the Bus Red
63. se nor for any infringements of patents or other rights of third parties that may result from its use Doc CAS RCCIPC DTS 0001 l 6 S TAEL RCCIPC Data Sheet Re mm Page 4 of 53 Table of Contents gps 6 DOCUMENT ua ra Sie 7 2 1 Reference DOCUIMGNIG E ienie ia REE EEEE E RE EREE EE 7 LIST OF ACRONYMS AND ABBREVIATIONS 2 cccccceccsereseecsennsncnsnensnansnaeenasenanennenenseeeseseneeeneneess 8 CANOPEN OVERVIEW 9 4 1 CGo omm nication Model E EEEE EEEE EERE 9 42 Object Dictionary seeen R e er E E EE Eaa 9 43 Pata tvDE nud A UD NO EDU SUPER oer OPE a DUUM 10 4 4 deus E E TTC rcr TEC 10 4 5 Network Management CDIGGIS cd eae ese sea i Cette eta seai Ge beber Com aces CelbeSebtt tu eed Getae e ER NM ed fca 10 4 5 1 Module Control Services i eid ee Mes ehe nde ap du area erii ede 10 45 2 BOOP Service ise ee t e e EE e o due Ear etu dd Rea Asada aos 11 4 5 8 Error Control Service and Bus Redundanocy sse 11 4 6 G mmunic tion ODICCIS RC 11 4 7 Process Data Object PDO vo ssosnsnsznssstevansssndeseonsdexagensoansanoidavausdanduep onicbvsaneiuadabosSdameanninats LI LA HT D D E E evhs E E 11 NIME Lei S e S E 11 LA 280 1700 nre eaa a a aaa aa E E a E EAE 12 AT RA ASYMCMIONOUS sossa
64. st ro ro rst 0x0 B_DEF 1 b_def Default CAN Bus Ttoggle ues 2000h Sub Index 2h Address 0x1048 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514 13 12 11 10 2 1 field reserved t toggle sdo host ro ro rst 0x0 T_TOGGLE 3 0 t_toggle Ttoggle value _ gt Ntoggle Index 2000h Sub Index 3h ALLUERE 0x104C i 31 30 29 28 27 26 2524 23 2221 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field reserved n toggle sdo host ro ro rst 0x0 N_TOGGLE n toggle Ntoggle value Ctoggle Index 2000h Sub Index 4h Address 0x1050 _ E gale field reserved sdo host ro ro rst 0x0 0x00 File name CAS RCCIPC DTS 0001 Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use RCCIPC Data Sheet Doc CAS RCCIPC DTS 0001 Issue 6 Date 08 05 2014 Page 40 of 53 c toggle Ctoggle value Node eee A IEEE 2002h Sub Index Oh Address aer 30 29 2812 23 22 21 20 t9 18 17 16 15 14 1 JACEE field reserved Nodepar_s0 sdo Ex host ro ro rst 0x000000 Ox1 T0 Nodepar so SubIndex 0 of Node Parameters entry
65. sub indexes defined as U8 U16 or U32 RCCIPC AO Total Bytes Sub Index len U8 U16 U32 32 32 64 128 64 64 128 256 128 128 256 512 254 254 508 1016 6 2 RCCIPC CANOpen Services The RCCIPC is in charge of supporting the following CANOpen services NMT state transitions Synch consumer Heartbeat receiver and producer SDO block Asynchronous RPDO and TPDO Redundancy manager The implementation of the RPDO TPDO and SDO services is performed by the specific Finite State Machine module HCCIPC FSM vha available in the SRC directory The FSM executes the following macro operations e Object Dictionary Initialisation RPDO elaboration TPDO elaboration SDO elaboration The FSM is implemented exploiting only combinational logic and it works as big multiplexers returning the execution code according to the input address Each macro operation is implemented as a sequence of Logic Arithmetic and Memory operations for e Registers loading with constants Operands moving among different registers Arithmetic operations Logic compare and bit check Read write memory operations In the next paragraphs how RCCIPC manages the RPDO TPDO and SDO services is explained 6 2 1 Receive PDO Service The RCCIPC supports only a single asynchronous RPDO service with a static structure to define the Communication and Mapping parameters RPDO Communication parameters Index Sub Index
66. ta Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use Doc CAS RCCIPC DTS 0001 l 6 S TAEL RCCIPC Data Sheet A Page 53 of 53 EDAC_enable Corrector function corr_out edac_error_mask Fig 14 1 EDAC protection The EDAC function is disabled at start up User is in charge of enabling it after RCCIPC initialization Since Double error detection represents a critical condition for the core because the management of wrong values can compromise the RCCIPC behaviour it is strictly recommended that user resets the RCCIPC core if this error occurs END OF DOCUMENT File name CAS RCCIPC DTS 0001 Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use
67. tes RCCIPC IRQ mask clear register EAD EXT 00001128 00000000 HOST reads RCCIPC IRQ status register BAD EXT 00000040 00000802 HOST reads RCCIPC AO memory DD D EZ D DDD DDD HAHA W GI D iw EAD EX 00000044 60000120 Tab 8 4 Log File example and explanation Because the time stamp value could vary depending on simulator used could be useful having a Log file without time stamp information The following command creates a Log file report val txt without time information gt cat report txt awk printf 5s s s s n S3 S4 S5 S6 gt report val txt 8 4 Test Procedures Simulation In this paragraph the instructions to perform the tests included in the DataBase and to define new test procedures are described 8 4 4 RCCIPC default tests All the tests corresponding to the RCCIPC test procedure can be easily executed exploiting the RCCIPC test sh shell script The RCCIPC test script executes the following steps e Generates specific test configuration file e Compiles the new VHDL testbench e Launches the simulation scripts At the end of simulation it automatically checks if the test is correctly passed comparing the produced output file with the correspondent reference output file To perform the tests reported in Tab 5 6 enter in your simulation directory File name CAS RCCIPC DTS 0001 Issue6 docx RCCIPC Data Sheet T
68. testbench parser vhd Emulator of CAN master and HOST interface CAN3MB AUCANS 8051 is an hdl model of CAN Controller interface for 8bit Can vhd microcontroller and it s used to emulate a CAN master node Interface vhd singleshot true vhd singleshot false vhd Tab 5 4 Test bench source files 5 2 2 CAN Bus Controller The RCCIPC core has been designed to embody the HurriCANe Core in its version 5 2 4 The source files are not directly included in the RCCIPC database because subjected to different patent restrictions ESA distributes the HurriCANe 5 2 4 core under its specific license To insert the HurriCANe controller in the RCCIPC database the HurriCANe 5 2 4 source files have to be simply copied in the CAN CORE directory The list of HurriCANe files is reported below e CANCore vhd CANCoreConfiguration vhd CANMessageStates vhd CANRx vhd CANTx vhd CRCCalc vhd ErrFrameGen vhd ErrorCounters vhd StuffHandler vhd Synchro 5 3 SIM Script Directory The SIM_SCRIPT directory contains all the files that compose the IP core test procedures and the scripts needed to build new input stimuli for RCCIPC simulation Name Description RCCIPCTestWriter pl Perl script to generate stimuli file for the parser module RCCIPC_test sh Shell script to perform automatically predefined RCCIPC test procedures Tab 5 5 Simulation scripts For each test procedure these files are included File name CAS RCCIPC DTS 00
69. the CAN controller can core and its interface manager RCCIPC_interface e Messages queues they store message received Msgin Controller and message to be transmitted MsgOut Controller The queues are implemented using memory devices Msg n Queue MsgOut Queue e Network Manager it is the manager of the Network Management Services controlling the NMT state and performing the Bus Redundancy management Network Manager File name CAS RCCIPC DTS 0001_Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use Doc CAS RCCIPC DTS 0001 Issue 6 Date 08 05 2014 Page 15 of 53 RCCIPC Data Sheet SITAEL e Object Dictionary Handler composed by an event scheduler event handler that controls the engine of the RCCIPC OD handler in order to elaborates the Communication services RPDO TPDO SDO e Memory controller it is the module that allows accessing the whole Object Dictionary The following figure illustrates the dependencies between the modules constituting the RCCIPC RCCIPC Network OD Event T Fig 5 2 RCCIPC SRC directory tree 5 2 1 LIBRARIES Directory The LIBRARIES subdirectory contains the files used to adapt the RCCIPC to different FPGA families
70. tion command for the VHDL files are defined as the VHDL Com Elab Variables VHDL Com VHDL compilation command VHDL_Elab Elaboration command W worklib VHDL compilation command VHDL Comp ncvhdl V93 WORK elaboration command VHDL_Elab ncelab ACCESS rw The W variable indicates the output directory for compiled files and tags The setup command section is assigned to build the tool specific Set up environment The following box shows the example of the Cadence NCsim simulator which requires the cds lib hdl var to link worklib and standard libraries setup mkdir worklib mkdir axcelerator echo DEFINE worklib worklib cds lib echo DEFINE ieee CDS ROOT tools inca files IEEE gt gt cds lib echo DEFINE std CDS ROOT tools inca files STD gt gt cds lib echo DEFINE synopsys CDS ROOT tools inca files SYNOPSYS gt gt cds lib echo DEFINE LIB MAP gt worklib gt worklib hdl var echo DEFINE WORK worklib gt gt hdl var echo timescale ins 10ps gt time v Relationships between the design sub module is explicitly indicated in the dependency section of the Makefile For example the notation of the following Box indicates that test bench VHDL entity RCCIPC_tb Top of simulation hierarchy depends on the RCCIPC vhdl and parser vhd Module that ha
71. undancy Management protocol Through this protocol RCCIPC is able to control two CAN buses nominal and redundant RCCIPC periphery is furnished with a bus selection flag that in a multiplexing way allows defining which is the currently CAN active bus Two parameters are available to control the redundancy protocol e Ttoggle counter e Ntoggle counter The Ttoggle counter defines the maximum number of Heartbeat events causing a bus switch The Ntoggle counter defines the maximum number of bus toggling before RCCIPC stops the redundancy process 4 6 Communication Objects 4 7 Process Data Object PDO The real time data transfer is performed by the PDO service Two kinds of PDO are supported e Transmit PDO TPDO RCCIPC transmits data e Receive PDO RPDO RCCIPC receives data 4 7 1 1 TPDO The RCCIPC supports only the Asynchronous transmission modes for TPDO service associated to a static Application Objects of 8 bytes 6001h 4 7 1 1 1 Asynchronous The transmission of this type of TPDO is associated to the following trigger e Event trigger external host device issues a TPDO transmission request The two timer parameters Event Time and Inhibit Time are not supported File name CAS RCCIPC DTS 0001 Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of
72. ve to be analysed before it W RCCIPC tb vhmdl W RCCIPC vhmdl W parser vhmdl When a new design is developed on the RCCIPC core these Makefile lines have to be edited to insert the new custom hierarchy A specific file Makefile mem is included in the Makefile and called during the compilation process defining which technology model has to be applied for RCCIPC simulation File name CAS RCCIPC DTS 0001 Issue6 docx RCCIPC Data Sheet The copyright of this document is vested in SITAEL S p A However no responsibility is assumed by SITAEL S p A for its use nor for any infringements of patents or other rights of third parties that may result from its use Doc CAS RCCIPC DTS 0001 l 6 S TAEL RCCIPC Data Sheet ia EN Page 29 of 53 MO RCCIPC DB SRC M1 MO LIBRARIES M2 M1 TECH GEN MPATH M0 M1 M2 W mem tech vhmdl W CCIPCconf vhmdl W tech generic vhmdl This Makefile includes only the instruction to compile the Generic technology model User has to add all the files and their dependencies needed to compile and simulate with the specific technology NCSIM tool example The simple steps to set up a new simulation directory and start simulating RCCIPC with the Cadence Ncsim tool are explained in this example Start creating the new YourSIM simulation directory gt mkdir YourSIM gt cd YourSIM

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