56F827 - Freescale Semiconductor
Contents
1. HTEVSIG cec sa IVIISHZEXVIN EE dr E mn MIEI HOLOSNNOO menn 42030803 S XP Noy NIZI cec sa NO398404 NISH Inosu us 7 Tes NIER inory AL eeu N3 NISH 1noeu ano Men Inozu ind TT NILH INOLH IG 8inoed SLA axa LNOEL NIEL s o Inozi NIEL ax INOLL NILL usa qoa a a 5 E 7 56F827EVM User Manual Rev 2 Freescale Semiconductor A 6 28p09 oeJejS Jg 9L ISS 9 V 9ANBIY 3 q I DL Jo 9 1eeusS ubisag 04050 Jeubiseg 1002 60 dy Aepuow ejeg g ANG Ol uo i Jequinw ezIS m EEN OCH 93009 03431S 1189 91 ISS suu 0LGZ Lp 08h XV4 0608 6Lv 081 IO EE EEN uuo 0 veo mo YY y v u 8298 euozuy dul l 4 9 295991 pe ELA peou 10 13 1583 0012 a HWVHI Ud SLIGTE HHISVN wyo 0 Kad GRIOMTAS v HOON TVINSS NIGO UOISIAIG SJINPOId PJEPUEIS dSq gt d wyo 0 0079 T T T 809 egw Kod 09 6 0 T T WOREN gt AS op CT T 0 t OND NOLNHS ani 3 yo 0 vag 7 SNS T 00 9T 0 0 T 15538 03400 Va Doan i 4029 AES OG QUA SSY4A8 sovra D ns Deet 1 1 O n 8 1 se E G 40 02 dn GER 0 1 0 ao IK 8318 spe foams JE A vino wih 8 ONASE 03000 MXA2. 2 14 Codec Analog GONG MAA 2 15 SES AAA 2 16 List of Figures Rev 2 Freescale Semiconductor iii 56F827EVM User Manual Rev 2 Freescale Semiconductor 1 1 2 1 22 2 3 2 4 2 5 2 6 g 28 2 9 2 10 LIST OF TABLES 56F827EVM Default Jumper Options 1 3 SPI Port Connector Descriptio a u u u y qa KEL Rd ER RV d abd db ded da 2 4 RS 232 Serial Connector NNN aid en dude cia ER E ded sen lass 2 5 Oeral Mode ICI v sau oye e a ef Ce AA ARA AAA 2 7 DE esed Na Ke oo REPRE eee R RRR e esos 2 9 Parallel JTAG Interface Disable Jumper Selection 2 9 Parallel JTAG Interface Connector Description 2 11 Codec Sample Rate Selector uL ia s E AR ART R ERRORES ERRAT ERE RE ADR 2 15 Memory Daughter Card Connector Description 2 17 Peripheral Daughter Card Connector Description 2 19 SAPONI nah Se db dd a ads ada 2 20 List of Tables Rev 2 Freescale Semiconductor V 56F827EVM User Manual Rev 2 vi Freescale Semiconductor Preface This reference manual describes in detail the hardware on the 56F827 Evaluation Module Audience This document is intended for application developers who are creating software for devices using the 56F827 part Organization This manual is organized into two chapters and two appendixes Chapter 1 Introduction provides an overview of the EVM and
3. 56F827 Evaluation Module User Manual 56F800 16 bit Digital Signal Controllers DSP56F827EVMUM Rev 2 07 2005 freescale com 4 NA freescale semiconductor 1 1 1 2 L3 2 1 aa 2 4 2 3 2 6 2 7 2 8 2 5 1 2 8 4 25 2 10 241 242 2 12 1 2 12 2 243 2 13 2443 2 TABLE OF CONTENTS Preface vii BENE REE eR RAIDER REL REPE DESIRES dE vii Se oh hho de qi did dd A dA ani dad dg dad ds vii MISAS M T vii Notation Conventions viil Definitions Acronyms and Abbreviations 1X EEE EEE EEE eht he eat x Chapter 1 Introduction EE GRESS eee De HORE ACD ee ded 1 1 eg rad ORR ee ss par ARAN 1 2 SOFO MC ON gt A eos qu pe dass AAA EE TE 1 3 Chapter 2 Technical Summary ly sda dida di EE d AA ia ESS eee Teer err er Tee eer eee Sd ikke 2 2 Pia and Data MEMO caia 3 ia rr he us dec S ddp AAA 2 3 SPI EEPROM Memory crios Ed Rep to PS ARP doa ds fiada drei as 2 4 RS 232 MENU COMMUNICATIONS siria e dd ad d dy Dada di 2 5 LO A ee ia Meee ES 2 6 Operating A aa pd a a dU radici TEO 2 7 IR LEDE 442224244544 criar pa DE REED EAE be X sikap Ad TP P 2 8 Debus noo nm 2 8 UM DEI 1 EEE Ka IT eh E T T TI ITIN 2 9 Parallel JT AG Interface COMMECIO as ices nc RER E irradia 2 10 EXE NED uid ern Rad REGE EE cae pus miner EO dolo a ee hes 2 12 DO RE cas ROTE PSI PI 2 13 00 A 2 14 BIO R RAPPORTO POP a EEE ISO kana 2 14
4. 56F827 CS4218 Codec Enable Logic A son PAL SDOUT SCLK FSYNC t RESET Figure 2 11 CS4218 Stereo Audio Codec 2 12 1 Analog Input Output The 56F827EVM uses jacks for line level stereo input line level stereo output and stereo headphone output A National Semiconductor LM4880 is used to provide the drive required for the use of headphones This device offers a THD which is superior to the CS4218 s on chip headphone drive circuitry by a factor of two The basic Analog codec connections are shown in Figure 2 10 2 12 2 Digital Interface The serial interface of the codec transfers digital audio data and control data into and out of the device The SSI port which consists of independent transmitter and receiver sections is used for serial communication with the codec On the controller side the Serial Transmit Data pin STD is an output when data is being transmitted to the codec The Serial Receive Data pin SRD is an input when data is being received from the codec These two pins are connected to the codec s Serial Data Input pin SDIN and Serial Data Output pin SDOUT The controller s Transmit Serial Clock pin STCK provides the serial bit rate clock for the SSI interface It is connected to the codec s Serial Port Clock pin SCLK Data is transmitted on the rising edge of SCLK and is received on the falling edge of SCLK 56F827EVM User Manual Rev 2 2 16 Freescale Semiconduct
5. Analog hnput Output EEE DEE SE 2 16 Digital MOG iudei san data DOR Dib FED ddr dg aaa dra hA 2 16 RET RR duo pesei a XS ntt dote OR eX s ee ec 2 17 Memory Daughter Card Expansion Connector 2 17 Peripheral Daughter Card Expansion Connector 2 18 Table of Contents Rev 2 Freescale Semiconductor RLE se TTT 2 20 GE A TENNER EEE EN 2 20 Appendix A 56F827EVM Schematics Appendix B 56F827EVM Bill of Material 56F827EVM User Manual Rev 2 ii Freescale Semiconductor id id 1 3 si os 2 3 2 4 2 5 2 6 27 2 8 2 9 2 10 NE LIST OF FIGURES Block Diagram of the 56F827EVM 1 2 S6F8275EV NI Jump r Reference d ch cons EX d bdo db RE RA RR ada AL dd 1 3 Connecting Qe SOPEZITBVM CABO Lu uua ed ey dE d Ee Rm Deda da aaa 1 4 Schematic Diagram of the External Memory Interface 2 3 SPI EEPROM Memory Block Diagram 2e e e x a NAAA 2 4 Schematic Diagram of the RS 232 Interface es aca aca a 2 5 Schematic Diagram of the Clock Interface Lieu ios ky e R ew deen er 2 6 Schematic Diagram of the Debug LED Interface 2 8 Block Diagram of the Parallel JTAG Interface 2 10 schematic Diagram of the User Interrupt Interface 2 12 Schematic Diagram of the RESET AO 3 8 A SEENEN EE CN dg 2 13 Schematic Diagram of the Power Supply
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7. www freescale com E mail support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this documen
8. 26 PD3 27 ANA4 28 ANAR 29 ss 30 PD4 31 SRCK 32 PD5 33 STFS 34 PD6 35 RESET 36 PD7 37 ANA6 38 ANA7 39 STD 40 RXD1 41 STCK 42 TXD1 43 IRQB 44 RXDO 45 IRQA 46 TXDO 47 3 3V 48 3 3V Technical Summary Rev 2 Daughter Card Connectors Freescale Semiconductor Table 2 9 Peripheral Daughter Card Connector Description Continued J2 Pin Signal Pin Signal 49 ANA8 50 ANAQ 51 GND 2 14 SCI Port 2 A separate connector J4 is provided to allow the easy connection of SCI Port 2 signals along with a reference GND signal Table 2 10 SCI Port 2 Connector J4 Signal Description 1 TXD2 2 RXD2 3 GND 2 15 Test Points The 56F827EVM board has a total of seven test points Three digital GND test points are located in corners of the board The 5 0VA and AGND test points are located in the bottom right analog corner of the board The 2 5V and 3 3V test points are located in the upper right power supply section of the board 56F827EVM User Manual Rev 2 2 20 Freescale Semiconductor Appendix A 56F827EVM Schematics Appendix A Rev 2 Freescale Semiconductor A 1 SG37 Bnq dq pue Jossa901d 278495 Lamb 3 q T OL Jj 188US ubiseg 0950 eufiseq 1002 60 Judy Kepuow areg 184 NSQ WA34284398dSQ ziener 8215 S031 91830 pue 108899014 179795490 0193 81 087 xv3 0609 ELb
9. oscillator bypass connectors JG4 and JG5 see Figure 2 4 If the input frequency is above 4MHz then the EXTAL input should be jumpered to ground by adding a jumper between JG4 pins 2 and 3 The input frequency would then be injected on JG5 s pin 2 If the controller needs to be synchronized to the codec s sample frequency then the controller s input frequency should be jumpered using the 12 2280MHz codec frequency If the input frequency is below 4MHz then the input frequency can be injected on JG4 s pin 2 EXTERNAL OSCILLATOR HEADERS 56F827 12 2880MHz Figure 2 4 Schematic Diagram of the Clock Interface 56F827EVM User Manual Rev 2 2 6 Freescale Semiconductor Operating Mode 2 6 Operating Mode The 56F827EVM provides a boot up MODE selection jumper JG6 This jumper is used to select the operating mode of the controller as it exits RESET Refer to the DSP56F827 User s Manual for a complete description of the chip s operating modes Table 2 3 shows the two operation modes available on the 56F827 Table 2 3 Operating Mode Selection Operating Mode JG6 Comment 0 1 2 Bootstrap from internal memory 3 No Jumper Bootstrap from external memory Technical Summary Rev 2 Freescale Semiconductor 2 7 2 7 Debug LEDs Six on board Light Emitting Diodes LEDs are provided to allow real time debugging for user programs These LEDs will allow the programmer to monitor program execution withou
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11. 0FM Freescale Semiconductor 2 DSP56F 826 827 Digital Signal Processor User s Manual DSP56F826 827UM Freescale Semiconductor 3 DSP56F827 Technical Data DSP56F827 Freescale Semiconductor DSP56F827EVM User Manual Rev 2 x Freescale Semiconductor Chapter 1 Introduction The 56F827EVM is used to demonstrate the abilities of the 56F827 and to provide a hardware tool allowing the development of applications that use the 56F827 The 56F827EVM is an evaluation module board that includes a 56F827 part 16 bit stereo codec external memory and a daughter card expansion interface The daughter card expansion connectors are for signal monitoring and user feature expandability The 56F827EVM is designed for the following purposes Allowing new users to become familiar with the features of the 56800 architecture The tools and examples provided with the 56F827EVM facilitate evaluation of the feature set and the benefits of the family Serving as a platform for real time software development The tool suite enables the user to develop and simulate routines download the software to on chip or on board RAM run it and debug it using a debugger via the JTAG OnCE port The breakpoint features of the OnCE port enable the user to easily specify complex break conditions and to execute user developed software at full speed until the break conditions are satisfied The ability to examine and modify all user accessible registers memory a
12. 1 LED4 Hewlett Packard HSMS C650 2 Yellow LED LED2 LED5 Hewlett Packard HSMY C650 3 Green LED LED3 LED6 LED7 Hewlett Packard HSMG C650 Diode 2 S2B FM401 D1 D2 D3 Vishay DL4001DICT 1 1Amp Bridge Rectifier D4 General Semiconductor DF02S Capacitors 1 470uF 16V DC C3 ELMA RV 16V471MH10R 18 0 1 uF C4 C6 C9 C22 C30 C32 C34 SMEC MCCE104K2NR T1 C36 C38 C42 C44 C46 C48 C50 C51 C53 C55 7 47uF 16V DC C5 C7 C23 C24 C56 C57 C58 ELMA RV2 16V470M R 2 0 33uF C8 C14 SMEC MCCE334K3NR T1 2 470pF C10 C12 SMEC MCCE471J2NO T1 12 1 0uF 25V DC C11 C13 C19 C20 C25 C29 SMEC MCCE105K3NR T1 C37 C40 C59 56F827EVM User Manual Rev 2 Freescale Semiconductor Qty Description Ref Designators Vendor Part s Capacitors Continued 2 0 0022uF C15 C16 SMEC MCCE222K2NR T1 3 0 47uF C17 C18 C21 SMEC MCCE474K3NR T1 9 0 01 uF C33 C35 C39 C41 C43 C45 C49 SMEC MCCE103K2NR T1 C52 C54 Jumpers 4 1 x 2 2mm Header JG1 JG3 JG6 SAMTEC TMM 102 03 S S 2 3 x 1 2mm Header JG4 JG5 SAMTEC TMM 103 03 S S 1 4 x 2 2mm Header JG7 SAMTEC TMM 104 03 S D Test Points 7 1 x 1 Pin TP1 TP7 Samtec TSW 101 06 S S Crystals 1 4 00MHz Crystal Y1 CTS ATSO4ASM T Connectors 1 2 1mm coax P1 Switchcraft RAPC 722 Power Connector 1 DB25M Connector P2 AMPHENOL 617 C025P AJ121 1 DE9S Connecto
13. 3o suowdpeaH seu 002 T 0 0 619 wyo 0 r IEN 00 87 0 0 0 s 0000 VYN 0015 NHd dd dn au Asa 129 DK Ant ZEI S BAN LAN 94 inet N i Or Wd ONE Jl dano ENG Ino8 I 1n008 93009 o gt gt aus 9d seu 029 Ps adues am I pj km wyo 0 uis 1 wm t FAN NIAS 93009 avy a TJ ET GN D Joi 9rd DR d ZX WE 1 002 3 DY 8124S0 HOL LAA 184 NOLNHS Oru er ONS JONG TE ZN wo 7 00 YOGA gi ovAo s T ANDA Me NITS 23005 GAO os Inoas 03002 OVNE Aur le anvo BNASS 4105 23000 osozaneszer 19 F E 69 Nag LE ONASS 93009 ano Ly aa EL VOA e xoi gr 48438 13838 or tee conis NT stu 07 annee 1300M8 MEL 984 E 1300N 2300MS 99 Hu zagon S g xoi E 300OMS m HAN gt gt ZHW982 21 n seu 408438 Lg 30270 sai BIN ke 120 KNN LAN VE 94M TIN sm E voy ENO a 819 xoi ar EN TNT NO ee em D l 199 8 call NIB AE Ge EN veep ye Jnzz00 0 4nzz000 29 DE oi 210 FR spe 031215 seu veg 919 19 TEAN wen KI EGON Foa inn Ly spe 021215 an ani 11017 nn O ino di ero Tot Ur 4001 DI t Vau 7IT0N re 219 T qet z 170 ONE EU mou e 1008 Mie NI di sd uo Y van E MOL dee vd NN 29 N dr H I DE Appendix A Rev 2 A 7 Freescale Semiconductor 1o 9 uuoo 9 LP pue 398J 9JU 30611 ISOH g LP JojeJed V eJnBiJ 3 q DL JO 1eeug ubisag 0480 Jaubiseg 1002 60 Judy Aepuow ayeq g
14. 8 AE E Ag et I dno 280 NOLLOSHSDd LASHA anyo leo L uod S 0 UB gouI lt lt e o O ES Mol NOLLNEHSNd Sat m ZHN8 lt DSO LXE S lt ZHN88Z ZL B IIX lt anyo 5 0 9 SL LH ZHINOO Y E ca VOUI lt lt WO OA zs SSVAAE DSO MOL NOLLOSHSNA WOYI wa e if A 3 Appendix A Rev 2 Freescale Semiconductor 56F827EVM User Manual Rev 2 Freescale Semiconductor A 4 AIOWSIN WO3d33 eos UG INL 181495 IS Y Y inBij OL JO 1eeus ubiseq adsa 1eubIseq 1002 60 dy Aepuow ejeq V J qunN eZ NSA WA3Z3849GdSA juawnooq IS AYOWAW NOddII VE WE Bios IJS SUL 0LSZ Lp 084 XV4 OGOG EL 084 JOj2npuoonuas v8268 euozuy duo 9 295991 peoy 101113 1583 00 LZ ca lt UOISIAIG S ONPOJd pJepuels ASA e dM MOL tou s34 MOL 06H AE ET OS HLOGOGSV LV STqeugH NOTAHH Appendix A Rev 2 A 5 Freescale Semiconductor 40 99UU0D pue ZEZ SY od IOS Gg einBi4 3 I q I 5 m OF JO GS 1eeus ubiseg adsa euBiseqg 1002 60 dy Aepuow 9160 Jequnn NSQ WA322849S8dSQ 1uawnood V ezIs HOLO3NNOO ANY 2 2 SHY 1HOd IOS entr OLSZ E LE 087 XVI 0606 61 08 19758 euozliy du peog 101113 1583 0017 UOISIAIG SI9NPOId pJepuels ASA
15. JTAG Interface 56F827EVM User Manual Rev 2 2 10 Freescale Semiconductor Table 2 6 Parallel JTAG Interface Connector Description P2 Pin Signal Pin Signal 1 NC 14 NC 2 PORT_RESET 15 PORT_IDENT 3 PORT_TMS 16 NC 4 PORT_TCK 17 NC 5 PORT_TDI 18 GND 6 PORT_TRST 19 GND 7 NC 20 GND 8 PORT_IDENT 21 GND 9 PORT_VCC 22 GND 10 NC 23 GND 11 PORT_TDO 24 GND 12 NC 25 GND 13 PORT_CONNECT Technical Summary Rev 2 Debug Support Freescale Semiconductor 2 9 External Interrupts Two on board push button switches are provided for external interrupt generation as shown in Figure 2 7 S2 allows the user to generate a hardware interrupt for signal line IRQA S3 allows the user to generate a hardware interrupt for signal line IRQB These two switches allow the user to generate interrupts for his user specific programs 56F827 IRQA Figure 2 7 Schematic Diagram of the User Interrupt Interface 56F827EVM User Manual Rev 2 2 12 Freescale Semiconductor Reset 2 10 Reset Logic is provided on the 56F827 to generate an internal Power On RESET Additional reset logic is provided to support the RESET signals from the JTAG connector the Parallel JTAG Interface and the user RESET push button refer to Figure 2 8 JTAG_RESET RESET MANUAL RESET TRST JTAG TAP RESET Figure 2 8 Schematic Diagram of the RESET Inter
16. MOTA UBTUA T SE T MOA L Y hh AOLV INOHA Cow 3 AE E AO S CHI GOOD KO li 10371 02v CH AE e YAHMOd avas 3114434 ANY anL 0 1 99 Ovaa 31 8834 VA0 S O AA AS T OD DaAOL MOTU erz SANS ANLy v6H PQV LO69266oN 21 959 avas aliuuad anp AST O AAA T 999 D E ETA e za AOL T T T dnp Lt 10692 0N G 10692 0N SH avag 3118433 dm NEO 1NOA 100 EM m 29 O 100A I 100A Or A0 G EIER inp Ac ERS qvas 3118833 or L00vAJ VAE S O WW br K Id 1 La ed OV OGACI L LNAaNI HHMOd TVNYHLXH 3 q o 8 I Y 56F827EVM User Manual Rev 2 Freescale Semiconductor A 10 A 11 i T J i j PN Id 999 99 292 Ae Aes Ae et DSO 8TZ DS i I i 40100 o anyo AE ET i AE ET NE E AE e Appendix A Rev 2 zm aed E n mL mn PW 6 9 seo veo eco LED 9 9 seo Freescale Semiconductor 56F827EVM User Manual Rev 2 A 12 Freescale Semiconductor Appendix B 56F827EVM Bill of Material Qty Description Ref Designators Vendor Part s Integrated Circuits 1 DSP56F827FG80 U1 Freescale DSP56F827FG80 1 GS72116 U2 GSI GS72116TP 12 1 MAX3245 U3 M
17. NA342849S8dSG JOQUNN aZIS jueuinaoq SHOLO3NNOO NOISNVdX3 QHVO H31HOflVO out 0LSZ Lp 084 XvJ OGOG EL 08v 18258 euozuy eduoe peoy 101113 1583 0017 UOISIAIG S ONPOJd PIEPUEIS ASA 9 295994 e 10399UUO 21104 edeudraed Asaubnea 10392UUO ej4eq sseappv 1saubneda IS c AND 6VNY amp ano eene HEI er ONO EE O ACEN OND gy Ly AND ACEN DON 1 K lt anp zSD ZS d E sy SOd AND ESD oaxx rv vv v ev LOXL Sv ch by ev taxa 5 or 6 vSOd aND ITY ano ZVNV aNd 9v 8 LE LY qd qu 9 se 0v 9dd sia ve Sd 089 S d vid ce LE q vdd aND LTY SS9d 0 63 9SOd and stv OND SVNV OND ELO ER Le 90 dd eia 9c Sc sa edd Ha ve c va AND VNV OND old ce L ga dd 02 61 n odd 6a AND g y QNS za 18d 8d 9 SE ta ano LVNV UND civ FL EL 00 VIS ELV S n HM evi ND 6TW LS0d L Hays 07 rad riv 8 A ONS LV AAD SLV 9 S 8Y cad Tso sa Y 6Y tad LIV z L IK Ir 3 a Si a v Appendix A Rev 2 A 9 Freescale Semiconductor saijddns Jomod 6 V 91n614 a I a I 2 m OL 40 6 1eeusg uBiseq qdSq 1eubIseq 1002 60 Judy Aepuow 9190 v NSA WAI3Z78499dSA JequinwN ezig 198 jueunooq SdllddfiS HIMOd AL 0LS2 Lv 087 XVA UOISIAIG S ONPOJd pJepuels dSA 18758 euozuy adwal peoy 101113 1562 0017 0609 1p 087 L 90A01 AS Z 103 I Eve UBTUA pe ML snr 564 UBTUY 299
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19. TAL crystal input for controller oscillator 1 2 JG6 Selects controller s Mode 0 operation upon exit from reset 1 2 JG7 Enable SPI EEPROM 1 2 3 4 5 6 amp 7 8 1 3 56F827EVM Connections An interconnection diagram is shown in Figure 1 3 for connecting the PC and the external 12 0V DC power supply or external 5 0V DC lab power supply to the 56F827EVM board Introduction Rev 2 Freescale Semiconductor 1 3 Parallel Extension Cable PC compatible Computer O Connect cable A P1 TBIET to Parallel Printer port 56F827EVM External 5 0V with rm 12 0V or Lab receptacle p connector sai SUP Figure 1 3 Connecting the 56F827EVM Cables Perform the following steps to connect the 56F827EVM cables Connect the parallel extension cable to the parallel port of the host computer Connect the other end of the parallel extension cable to P2 shown in Figure 1 3 on the 56F827EVM board This provides the connection which allows the host computer to control the board Make sure that the external 12 0V DC 1 2A switching power supply or the external 5 0V DC 1 0A lab power supply is not plugged into a 120V AC power source Connect the 2 1mm output power plug from the external switching power supply into P1 shown in Figure 1 3 on the 56F827EVM board Optionally attach an external 5 0V DC lab power supply via the 2 pin terminal block TB1 Apply powe
20. ait state accesses while the 56F827 is running at 70MHz However when running at 80MHz the memory bank operates with four wait state accesses This memory bank can be disabled by removing the jumper at JG3 56F827 GS72116 A0 A15 A1 A16 AO DQ0 DQ15 OE WE Jumper Pin 1 2 Enable SRAM Jumper Removed Disable SRAM Figure 2 1 Schematic Diagram of the External Memory Interface Technical Summary Rev 2 Freescale Semiconductor 2 3 2 3 SPI EEPROM Memory A 1M bit 3 3V SPI serial EEPROM Memory Atmel AT45DB011 SC is provided on the 56F827EVM reference Figure 2 2 This memory connects directly to the SPI Port through a header on the 56F827 It can be used to load program code and data into the 56F827 s internal or external memory spaces A jumper block is provided JG7 to allow the user to disconnect the on board SPI EEPROM from the SPI port and allow him to connect his own SPI port peripheral The header details are shown in Table 2 1 EEPROM Enable 56F827 SPI Port Connector Serial EEPROM MOS SDI MISO SDO SCLK GPIOF7 Figure 2 2 SPI EEPROM Memory Block Diagram Table 2 1 SPI Port Connector Description JG7 Pin Signal Pin Signal 1 SS GPIO7 2 cs 3 MISO 4 SDO 5 MOSI 6 SDI 7 SCLK 8 SCK 56F827EVM User Manual Rev 2 2 4 Freesca
21. axim MAX3245EEAI 1 AT45DB011 U4 Atmel AT45DB011 SC 1 CS4218 U5 Crystal Semiconductor CS4218 KQ 1 LM4880 U6 National Semiconductor LM4880M 1 12 288MHZ OSC U7 Epson SG 531P 12 288MC 1 74LCX244 U8 ON Semiconductor MC74LCX244ADW 1 74AC00 U9 Fairchild 74ACOOSC 1 3 3V Voltage Regulator U10 ON Semiconductor MC33269DT 3 3 1 74AC04 U11 ON Semiconductor MC74ACO4AD 1 2 5V Voltage Regulator U13 ON Semiconductor MC33269DT ADJ 1 5 0V Voltage Regulator U14 ON Semiconductor MC33269DT 5 Resistors 1 10M O R1 SMEC RC73L2A10MOHMJT 1 4700 R2 SMEC RC73L2A4700HMJT 11 2700 R3 R6 R9 R11 R13 R19 SMEC RC73L2A2700HMJT 10 47K Q R4 R5 R7 R8 R10 R12 R26 R29 SMEC RC73L2A47KOHMJT 4 54K Q R20 R23 R25 SMEC RC73L2A5 1KOHMJT Appendix B Rev 2 Freescale Semiconductor Qty Description Ref Designators Vendor Part s Resistors Continued 2 510 R21 R22 SMEC RC73L2A510HMJT 4 5 62K Q 1 R30 R33 SMEC RC73L2A5 62KOHMFT 2 39 2K Q 1 R34 R35 SMEC RC73L2A39 2KOHMFT 19 10KQ R36 R37 R42 R45 R67 R70 SMEC RC73L2A10KOHMJT R72 R82 R85 R87 R90 R93 4 20 0K Q 1 R38 R40 R46 SMEC RC73L20 0KOHMFT 12 1KQ R41 R55 R62 R68 R69 R86 SMEC RC73L2A1KOHMJT 12 00 R47 R54 R88 R89 R96 R97 SMEC RC73JP2A 2 243 Q 1 R94 R95 SMEC RC73L2430HMFT Inductors 4 1 0mH FERRITE BEAD L1 L2 L3 L4 Panasonic EXC ELSA35V LEDs 2 Red LED LED
22. ed to the Memory Daughter Card Expansion connector J1 Table 2 8 shows the port signal to pin assignments Table 2 8 Memory Daughter Card Connector Description J1 Pin Signal Pin Signal 1 A10 2 A11 3 A9 4 DS 5 A8 6 A15 7 A7 8 A14 9 GND 10 PCS7 Technical Summary Rev 2 Freescale Semiconductor 2 17 Table 2 8 Memory Daughter Card Connector Description J1 Pin Signal Pin Signal 11 WR 12 A13 13 DO 14 A12 15 D1 16 D8 17 D2 18 D9 19 GND 20 GND 21 D3 22 D10 23 D4 24 D11 25 D5 26 D12 27 D6 28 D13 29 PCS6 30 PCS5 31 D7 32 D14 33 PS 34 D15 35 AO 36 RD 37 A1 38 A6 39 PCS4 40 GND 41 A2 42 A5 43 A3 44 A4 45 PCS3 46 PCS2 47 3 3V 48 3 3V 49 GND 50 GND 51 GND 2 13 2 Peripheral Daughter Card Expansion Connector The controller s peripheral port signals are connected to the Peripheral Daughter Card Expansion connector J2 Table 2 9 shows the port signal to pin assignments 56F827EVM User Manual Rev 2 2 18 Freescale Semiconductor Table 2 9 Peripheral Daughter Card Connector Description J2 Pin Signal Pin Signal 1 PBO 2 PB1 3 CLKO 4 PB2 5 TAO 6 TAI 7 PB3 8 PB4 9 TA2 10 TA3 11 PB5 12 PB6 13 ANAO 14 ANA1 15 SRD 16 PB7 17 SRFS 18 PDO 19 SCLK 20 PD1 21 ANA2 22 ANA3 23 MOSI 24 PD2 25 MISO
23. est Action Group Preface ix JTAG 1 1 2 1 connector 2 9 JTAG Preface ix JTAG port interface 2 1 Jumper Group 1 3 JG1 1 3 JG2 1 3 JG3 1 3 JG4 1 3 JG5 1 3 JG6 1 3 JG7 1 3 L Low profile Quad Flat Pack Preface ix LQFP LQFP Preface ix MPIO MPIO Preface ix Multi Purpose Input Output port Preface ix O On board power regulation 2 2 OnCE 1 1 OnCE TM OnCE Preface ix On Chip Emulation Preface ix Operating Mode 2 7 Index Rev 2 Freescale Semiconductor Index i P Parallel JTAG Host Target Interface 2 1 PCB PCB Preface ix Phase Locked Loop Preface ix PLL PLL Preface ix Printed Circuit Board Preface ix Program memory 2 3 R RAM RAM Preface ix Random Access Memory Preface ix Read Only Memory Preface ix Real time debugging 2 8 ROM ROM Preface ix RS 232 interface 2 1 2 5 level converter 2 5 schematic diagram 2 5 RS 232 interface 2 1 S SCI SCI Preface ix SCI compatible peripheral 2 2 Serial Communications Interface port Preface ix Serial Peripheral Interface port Preface ix SPI 2 2 SPI Preface ix SRAM external data 2 1 external program 2 1 SRAM Preface ix SSI 2 2 SSI Preface ix Static Random Access Memory Preface ix Stereo 16 bit codec interface 2 1 Stereo headphone interface 2 1 Synchronous Serial Interface port Preface ix DSP56F827EVM User Manual Rev 2 Wait State Preface ix WS Preface ix Index ii Freescale Semiconductor How to Reach Us Home Page
24. face RESET PUSHBUTTON O Technical Summary Rev 2 Freescale Semiconductor 2 13 2 11 Power Supply The main power input 12 0V DC to the 56F827EVM is through a 2 1mm coax power jack P1 An optional 5 0V DC power supply input is available through a 2 pin terminal block TB1 A 1 2A power supply is provided with the 56F827EVM however less than 500mA is required by the EVM The remaining current is available for user daughter card applications when connected to the daughter card interface The power regulation on the 56F827EVM provides 5 0V DC voltage regulation for the codec s analog circuits and to the additional voltage regulation logic on the EVM The additional voltage regulation logic provides 2 5V DC voltage regulation for the controller s core and 3 3V DC voltage regulation for the controller s I O memory parallel JTAG interface and supporting logic refer to Figure 2 9 Power applied to the 56F827EVM is indicated with a Power On LED referenced as LED7 5 0V Power 5 0V DC Regulator Condition Analog 3 3V Regulator SERE 56F827EVM Parts 2 5V 56F827 Regulator Core Figure 2 9 Schematic Diagram of the Power Supply 2 12 Stereo Codec A 16 bit audio quality stereo codec Crystal Semiconductor CS4218 is connected to the 56F827 s SSI port to support audio voice and signal anal
25. interface connector for an external debug Host Target Interface J3 On board Parallel JTAG Host Target Interface with a connector for a PC printer port cable P2 RS 232 interface for easy connection to a host processor U3 and P3 16 bit stereo codec interface U5 P4 and P5 Stereo headphone interface U6 and P6 Technical Summary Rev 2 Freescale Semiconductor 2 1 2 1 Codec sample rate selector S4 Peripheral Daughter Card Expansion Connector to allow the user to connect his own SCI SSI SPI or GPIO compatible peripheral to the controller J2 Memory Daughter Card Expansion Connector to allow the user to connect his own memory or memory device to the controller J1 On board power regulation from an external 12V DC supplied power input P1 On board power regulation from an optional 5V DC supplied power input TB1 Light Emitting Diode LED power indicator LED7 Six on board real time user debugging LEDs LED 1 6 Manual RESET push button S1 Manual interrupt push button for IRQA S2 Manual interrupt push button for IRQB S3 56F827 The 56F827EVM uses a Freescale DSP56F827FG80 part designated as U1 on the board and in the schematics This part will operate at a maximum speed of 80MHz A full description of the 56F827 including functionality and user information is provided in these documents DSP56F827 Technical Data DSP56F827 Provides features list and specifications including signa
26. its features Chapter 2 Technical Summary describes in detail the 56F827 hardware Appendix A 56F827EVM Schematics contains the schematics of the DSP56F827EVM Appendix B 56F827EVM Bill of Material provides a list of the materials used on the DSP56F827EVM board Suggested Reading More documentation on the 56F827 and the DSP56F827EVM kit may be found at URL www freescale com Preface Rev 2 Freescale Semiconductor vii Notation Conventions This manual uses the following notational conventions Term or Value Symbol Examples Exceptions Active High Signals No special symbol AO Logic One attached to the CLKO signal name Active Low Signals Noted with an WE In schematic drawings Logic Zero overbar in text and OE Active Low Signals may be in most figures noted by a backslash Hexadecimal Begin with a OFFO Values symbol 80 Decimal Values No special symbol 10 attached to the 34 number Binary Values Begin with the letter b1010 b attached to the b0011 number Numbers Considered positive 5 Voltage is often shown as unless specifically 10 positive 3 3V noted as a negative value Blue Text Linkable on line refer to Figure 1 1 Bold Reference sources See paths emphasis http www freescale com DSP56F827EVM User Manual Rev 2 viii Freescale Semiconductor Definitions Acronyms and Abbreviations Definitions acronyms a
27. l descriptions DC power requirements AC timing requirements and available packaging DSP56F826 827 16 Bit Digital Signal Processor User s Manual DSP56F826 827UM Provides an overview description of the controller and detailed information about the on chip components including the memory and I O maps peripheral functionality and control status register descriptions for each subsystem DSP56800 Family Manual DSP56800FM Provides a detailed description of the core processor including internal status and control registers and a detailed description of the family instruction set Refer to these documents for detailed information about chip functionality and operation They can be found on this URL www freescale com 56F827EVM User Manual Rev 2 2 2 Freescale Semiconductor Program and Data Memory 2 2 Program and Data Memory The 56F827EVM uses one bank of 128Kx16 bit Fast Static RAM GSI GS72116 labelled U2 for external memory expansion see the FSRAM schematic diagram in Figure 2 1 This physical memory bank is split into two logical memory banks of 64Kx16 bits one for program memory and the other for data memory By using the controller s program strobe PS signal line along with the memory chip s AO signal line half of the memory chip is selected when program memory accesses are requested and the other half of the memory chip is selected when data memory access are requested This memory bank will operate with zero w
28. le Semiconductor RS 232 Serial Communications 2 4 RS 232 Serial Communications The 56F827EVM provides an RS 232 interface by the use of an RS 232 level converter Maxim MAX3245EEAI designated as U3 Refer to the RS 232 schematic diagram in Figure 2 3 The RS 232 level converter transitions the SCI UART s 3 3V signal levels to RS 232 compatible signal levels and connects to the host s serial port via connector P3 Flow control is not provided but could be implemented using uncommitted GPIO signals The pinout of connector P3 is listed in Table 2 2 The RS 232 level converter transceiver can be disabled by placing a jumper at JG2 RS 232 Level Converter Interface 56F827 T1in R1out FORCEOFF Jumper Removed Enable RS 232 Jumper Pin 1 2 Disable RS 232 Figure 2 3 Schematic Diagram of the RS 232 Interface Table 2 2 RS 232 Serial Connector Description P3 Pin Signal Pin Signal 1 Jumper to 6 amp 4 6 Jumper to 1 amp 4 2 TXD 7 Jumper to 8 3 RXD 8 Jumper to 7 4 Jumper to 1 amp 6 9 N C 5 GND Technical Summary Rev 2 Freescale Semiconductor 2 5 2 5 Clock Source The 56F827EVM uses a 4 00MHz crystal Y 1 connected to its External Crystal Inputs EXTAL and XTAL The 56F827 uses its internal PLL to multiply the input frequency by 20 achieving its 80MHz maximum operating frequency An external oscillator source can be connected to the controller by using the
29. nd abbreviations for terms used in this document are defined below for reference Codec EEPROM EVM GPIO IC JTAG LQFP MPIO OnCE PCB PLL ROM SCI SPI SRAM SSI WS COder DECoder a part used to convert analog signals to digital Coder and digital signals to analog Decoder Electrically Erasable Programmable Read Only Memory Evaluation Module a hardware platform which allows a customer to evaluate the silicon and develop their application General Purpose Input and Output Port does not share pin functionality with any other peripheral on the chip and can only be set as an input output or level sensitive interrupt input Integrated Circuit Joint Test Action Group a bus protocol interface used for test and debug Low profile Quad Flat Pack Multi Purpose Input Output Port shares package pins with other peripherals on the chip and can function as a GPIO On Chip Emulation a debug bus and port created by Freescale to enable designers to create a low cost hardware interface for a professional quality debug environment Printed Circuit Board Phase Locked Loop Random Access Memory Read Only Memory Serial Communications Interface Port Serial Peripheral Interface Port Static Random Access Memory Synchronous Serial Interface Port Wait State Preface Rev 2 Freescale Semiconductor ix References The following sources were referenced to produce this manual 1 DSP56800 Family Manual DSP5680
30. nd peripherals through the OnCE port greatly facilitates the task of the developer Serving as a platform for hardware development The hardware platform enables the user to connect external hardware peripherals The on board peripherals can be disabled providing the user with the ability to reassign any and all of the controller s peripherals The OnCE port s unobtrusive design means that all of the memory on the board and on the controller chip are available to the user 1 1 56F827EVM Architecture The 56F827EVM facilitates the evaluation of various features present in the 56F827 part The 56F827EVM can be used to develop real time software and hardware products based Introduction Rev 2 Freescale Semiconductor 1 1 on the 56F827 The 56F827EVM provides the features necessary for a user to write and debug software demonstrate the functionality of that software and interface with the customer s application specific device s The 56F827EVM is flexible enough to allow a user to fully exploit the 56F827 s features to optimize the performance of his product as shown in Figure 1 1 56F827 RESET SPI EEPROM LOGIC RESET SPI 1N bit IRQ IRQ Interface MODE RS 232 DSub mer PTE SCI Interface 9 Pin Program Memory Addre
31. or Daughter Card Connectors The device s GPIO PORT D Bit 0 pin PDO is programmed to control the codec s Active Low Reset signal RESET The Serial Transmit Frame Sync pin STFS is programmed to control the codec s Frame Sync signal FSYNC FSYNC is sampled by SCLK with a rising edge indicating a new frame is about to start The FSYNC frequency is always the system s sample rate It may be an input to the codec or it may be an output from the codec in data mode The basic codec digital connections are shown in Figure 2 11 The codec s MODE is set by the three MODE selection resistors R96 R98 In the factory default setting of MODE 4 the codec is set to be the Master of the SPI bus with its data word set at 32 bits per frame 1 e a 16 bit Left channel and a 16 bit Right channel The sample rate is selected on Sample Rate Selector switch S4 reference Table 2 7 for selection options Codec control information is sent over a separate serial port using PD1 as the Control Chip Select signal CCS PD2 as the Control Data Input signal CDIN and PD3 as the Control Clock signal CCLK 2 13 Daughter Card Connectors The EVM board contains two daughter card expansion connectors One connector J1 contains the controller s external memory bus signals The other connector J2 contains the device s peripheral port signals 2 13 1 Memory Daughter Card Expansion Connector The controller s external memory bus signals are connect
32. r Table 2 4 JTAG Connector Description J3 Pin Signal Pin Signal 1 TDI 2 GND 3 TDO 4 GND 5 TCK 6 GND 7 NC 8 KEY 9 RESET 10 TMS 11 3 3V 12 NC 13 NC 14 TRST When this connector is used with an external Host Target Interface the parallel JTAG interface should be disabled by placing a jumper in jumper block JG1 See Table 2 5 for this jumper s selection options Table 2 5 Parallel JTAG Interface Disable Jumper Selection JG1 Comment No jumpers On board Parallel JTAG Interface Enabled 1 2 Disable on board Parallel JTAG Interface Technical Summary Rev 2 Freescale Semiconductor 2 9 2 8 2 Parallel JTAG Interface Connector The Parallel JTAG Interface Connector P2 allows the 56F827 to communicate with a Parallel Printer Port on a Windows PC reference Figure 2 6 By using this connector the user can download programs and work with the 56F827 s registers Table 2 6 shows the pin out for this connector When using the parallel JTAG interface the jumper at JG1 should be removed as shown in Table 2 5 DB 25 Connector TDI Parallel JTAG Interface IN OUT TDO 56F827 OUT IN P TRST TMS OUT OUT TCK OUT P RESET OUT Jumper Removed Enable JTAG I F Jumper Pin 1 2 Disable JTAG I F Figure 2 6 Block Diagram of the Parallel
33. r P3 AMPHENOL 617 C009S AJ120 3 1 8 Stereo Jack P4 P6 Switchcraft 35RAPC4BHN2 2 51 Pin HD Connector J1 J2 FCI Framatome Conn 91930 21151 1 7 x 2 Bergstick J3 SAMTEC TSW 107 07 S D 1 2 Pin Terminal Block TB1 On Shore Technology ED500 2DS Switches 3 SPST Pushbutton S1 S3 Panasonic EVQ PADO5R 1 3 Position DIP SW S4 CTS 209 3LPST Transistors 1 2N2222A Q1 ZETEX FMMT2222ACT Appendix B Rev 2 Freescale Semiconductor Qty Description Ref Designators Vendor Part s Miscellaneous 8 2mm Shunt SH1 SH8 Samtec 2SN BK T 4 Rubber Feet RF1 RF4 3M SJ5018BLKC 56F827EVM User Manual Rev 2 B 4 Freescale Semiconductor Numerics 1 2A power supply 2 14 16 bit 2 5V 3 3V hybrid controller 2 1 16 bit stereo codec interface 2 1 1M bit Serial EEPROM 2 1 4 00MHz crystal oscillator 2 1 64Kx16 bits of data memory 2 1 64Kx16 bits of program memory 2 1 C Codec Preface ix D Data memory 2 3 Daughter Card Expansion interface 2 1 Debugging 2 8 Development Card 2 1 E EEPROM EEPROM Preface ix Electrically Erasable Programmable Read Only Memory Preface ix Evaluation Module Preface ix EVM EVM Preface ix External oscillator frequency input 2 1 F FSRAM 2 1 2 3 G General Purpose Input Output port Preface ix GPIO 2 2 GPIO Preface ix H Host Parallel Interface Connector 2 8 Host Target Interface 2 8 INDEX IC IC Preface ix Integrated Circuit Preface ix J Joint T
34. r to the external power supply The green Power On LED LED7 will illuminate when power is correctly applied 56F827EVM User Manual Rev 2 Freescale Semiconductor Chapter 2 Technical Summary The 56F827EVM is designed as a versatile controller development card for developing real time software and hardware products to support a new generation of applications in digital and wireless messaging digital answering machines feature phones modems and digital cameras The power of the 16 bit 56F827 controller combined with the on board 64K x 16 bit external program static RAM SRAM 64K x 16 bit external data SRAM RS 232 interface stereo 16 bit codec interface Daughter Card Expansion interface and parallel JTAG interface makes the 56F827EVM ideal for developing and implementing many audio and voice algorithms as well as for learning the architecture and instruction set of the 56F827 processor The main features of the 56F827EVM with board and schematic reference designators include 56F827 16 bit 2 5V 3 3V controller operating at 80MHz Ul External fast static RAM FSRAM memory U2 configured as 64Kx16 bits of program memory with O wait states at 70MHz 64Kx16 bits of data memory with 0 wait states at 70MHz 1M bit Serial EEPROM U4 4 00MHz crystal oscillator for controller frequency generation Y 1 Optional external oscillator frequency input connector JG4 and JG5 Joint Test Action Group JTAG port
35. sidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part lt o Z freescale semiconductor Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners This product incorporates SuperFlash technology licensed from SST Freescale Semiconductor Inc 2005 All rights reserved DSP56F827EVMUM Rev 2 07 2005
36. ss 64Kx16 bit Data amp SRAM Control Peripheral Data Memory Daughter 64Kx16 bit AID Card SRAM Connector Memory Daughter Card Connector AG JTAG ONCE Stereo 16 bit Stereo Line In Connector SSI Codec Stereo Line Out DSub Parallel I Amp Headphone Jack 25 Pin JTAG Interface GPIO e Debug LEDs 2 5V 3 3V 4 00MHz Power Supply Crystal E SOND 2 5V 3 3V amp 5 0V Figure 1 1 Block Diagram of the 56F827EVM 1 2 56F827EVM Configuration Jumpers Seven jumper groups JG1 JG7 shown in Figure 1 2 are used to configure various features on the 56F827EVM board Table 1 1 describes the default jumper group settings 56F827EVM User Manual Rev 2 1 2 Freescale Semiconductor 56F827EVM Connections Dad HEADPHONE J G 6 DSP56F827EVM s I n P6 LEDS O TROB ui P4 P5 US LINE LINE UT IN OUT Figure 1 2 56F827EVM Jumper Reference Table 1 1 56F827EVM Default Jumper Options put gaia Penya JG1 Enable on board Parallel JTAG Host Target Interface NC JG2 Enable RS 232 output NC JG3 Enable on board SRAM 1 2 JG4 Use on board EXTAL crystal input for controller oscillator 2 3 JG5 Use on board X
37. t Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees sub
38. t having to stop the program during debugging refer to Figure 2 5 User LEDI is controlled by Port B s PBO signal User LED2 is controlled by PB1 User LED3 is controlled by PB2 User LED4 is controlled by PB3 User LEDS is controlled by PB4 User LED6 is controlled by PBS Setting PBO PBI PB2 PB3 PB4 or PBS to a Logic One value will turn on the associated LED 56F827 INVERTING BUFFER RED LED PBO AA YELLOW LED AN GREEN LED KAN RED RN 4 YELLOW LED AR 4 GREEN LED vg YY Y YY Y Figure 2 5 Schematic Diagram of the Debug LED Interface 2 8 Debug Support The 56F827EVM provides an on board Parallel JTAG Host Target Interface and a JTAG interface connector for external Target Interface support Two interface connectors are provided to support each of these debugging approaches These two connectors are designated the JTAG connector and the Host Parallel Interface Connector 56F827EVM User Manual Rev 2 2 8 Freescale Semiconductor Debug Support 2 8 1 JTAG Connector The JTAG connector on the 56F827EVM allows the connection of an external Host Target Interface for downloading programs and working with the 56F827 s registers This connector is used to communicate with an external Host Target Interface which passes information and data back and forth with a host processor running a debugger program Table 2 4 shows the pin out for this connecto
39. ysis applications The codec is clocked with a 12 288MHz oscillator This allows the codec to operate between a sample frequency of 8kHz and 48kHz The sample rate can be manually set by setting the appropriate switch positions on dip switch S4 The sample rate selections possible using this three position dip switch are detailed in Table 2 7 The codec supports 3 3V digital levels eliminating the need for voltage level translation circuitry Additionally a set of zero ohm resistors are provided on the EVM to allow a user to disconnect the on board codec from the SSI port and to connect his own codec to the SSI port refer to Figure 2 11 The on board codec has analog signal conditioning 56F827EVM User Manual Rev 2 2 14 Freescale Semiconductor Stereo Codec logic allowing direct connection to its line level input and line level output signals through two 1 8 stereo jacks see Figure 2 10 Line level Input Table 2 7 Codec Sample Rate Selector SW 4 SW 4 SW 4 Position 3 Position 2 Position 1 Sample Rate MF6 MF7 MF8 ON ON ON 48 00kHz ON ON OFF 32 00kHz ON OFF ON 24 00kHz ON OFF OFF 19 20kHz OFF ON ON 16 00kHz OFF ON OFF 12 00KHz OFF OFF ON 9 60kHz OFF OFF OFF 8 00kHz Figure 2 10 Codec Analog Connections CS4218 LM4880 Technical Summary Rev 2 Line level Output Headphone Output Freescale Semiconductor
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