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ADXL375 (Rev. B)

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1. 10 0 2 04 5 0 6 n e 1 0 Z O co w 9 d e 9 N wea tow o 50 35 20 5 10 25 40 55 70 85 100 Uu Ww TTE T T 0 ETAN TEMPERATURE C OFFSET a Figure 4 X Axis Zero g Offset at 25 C Vs 2 5 V Figure 7 X Axis Offset Drift 15 Parts Soldered to PCB Vs 2 5 V 25 1 0 0 8 20 0 6 0 4 0 2 15 OFFSET DRIFT g o PERCENT OF POPULATION 95 a 3 0L l f l1 j 11669 201 10 0 2 04 0 6 0 8 3 0 U 1 0 t Se a 4 aw aw a d 9 w o 50 35 20 5 10 25 4 55 7 85 100 S T p a e en ee e FIE TEMPERATURE C OFFSET g Figure 5 Y Axis Zero g Offset at 25 C Vs 2 5 V Figure 8 Y Axis Offset Drift 15 Parts Soldered to PCB Vs 2 5V 16 1 0 14 0 8 S mln 0 6 gt 12 o 04 E 5 lt 10 5 K 02 a tc o a a 8 s 0 b i kt 6 i 02 a m o o 0 4 E 4 a H 0 6 2 3 0 8 S 0 1 0 o 0 94 a 9 99 94 9 w QO 50 3 20 5 10 25 4 55 7 8 100 EE MCCC d Eo E a TEMPERATURE C OFFSET a Figure 6 Z Axis Zero g Offset at 25 C Vs 2 5 V Figure 9 Z Axis Offset Drift 15 Part
2. Rev B Page 20 of 32 ADXL375 REGISTER DESCRIPTIONS All registers in the ADXL375 are eight bits in length Register OxOO DEVID Read Only D7 D6 D5 D4 D3 D2 D1 DO 1 1 1 0 0 1 0 1 The read only DEVID register holds the fixed device ID code of OxE5 345 octal Register 0x1D THRESH_SHOCK Read Write The THRESH SHOCK register contains the unsigned threshold value for shock interrupts The magnitude of the shock event is compared with the value in the THRESH_SHOCK register for shock detection The scale factor is 780 mg LSB A value of 0 may result in undesirable behavior if single shock double shock inter rupts are enabled Register Ox1E Register Ox1F Register Ox20 OFSX OFSY OFSZ Read Write The OFSX OFSY and OFSZ registers contain user configured offset adjustments in twos complement format with a scale factor of 0 196 g LSB The value stored in the offset registers is automat ically added to the acceleration data and the resulting value is stored in the output data registers Address 0x32 to Address 0x37 For more information about offset calibration and the use of the offset registers see the Offset Calibration section Register 0x21 DUR Read Write The DUR register contains an unsigned time value representing the maximum time that an event must be above the THRESH SHOCK threshold to qualify as a shock event The scale factor is 625 us LSB A value o
3. Offset Calibrations eite e e RS Data Formatting at Output Data Rates of 3200 Hz and 1600 Hz e t SHEER DURER ERES 28 Using Self Test 5 cett t ER RARE OR RR 29 Axes of Acceleration Sensitivity sss 30 Layout and Design Recommendations sss 31 Package Information sentent 31 Outline Dimensions RETE eS 32 Ordering Guide opwen iii 32 Rev B Page 2 of 32 ADXL375 SPECIFIGATIONS Ta 25 C Vs 2 5 V Vppyo 2 5 V acceleration 0 g Cs 10 uF tantalum Cro 0 1 uF output data rate ODR 800 Hz unless otherwise noted Table 1 Parameter Test Conditions Comments Min Typ Max Unit SENSOR INPUT Each axis Measurement Range 180 200 g Nonlinearity Percentage of full scale 0 25 Cross Axis Sensitivity 2 5 Yo SENSITIVITY Each axis Sensitivity at Xour Your Zour ODR 800 Hz 18 4 20 5 22 6 LSB g Scale Factor at Xour Your Zour 4 ODR x 800 Hz 44 49 54 mg LSB Sensitivity Change Due to Temperature 0 02 C 0 g OFFSET Each axis 0 g Output for Xour Your Zour 6000 400 6000 mg 049 Offset vs Temperature 10 mg C NOISE X y and z axes 5 mg VHz OUTPUT DATA RATE AND BANDWIDTH User selectable Output Data Rate ODR 0 1 3200 Hz SELF TEST Output Change in Z Axis 6 4 g POWER SUPPLY Operating Voltage Range Vs 2 0 2 5 3 6 V Interface Voltage Range Vooo 1 7 1 8 Vs V Supply Current Measurement Mode ODR 100 Hz 145 uA ODR lt 3
4. our 0g Zour 09 Xour 0g Xour 0g Your 0g Your 0g 3 Zout 19 Zout 19 E Figure 37 Output Response vs Orientation to Gravity Rev B Page 30 of 32 ADXL375 LAYOUT AND DESIGN RECOMMENDATIONS Figure 38 shows the recommended printed wiring board land pattern 3 3400 1 0500 L A i I 0 5500 U i T U t U I n 0 2500 3 0500 a 5 3400 0 2500 j lt 1 1450 j 11669 014 Figure 38 Recommended Printed Wiring Board Land Pattern Dimensions shown in millimeters PACKAGE INFORMATION Figure 39 and Table 19 provide information about the package branding for the ADXL375 11669 102 Figure 39 Product Information on Package Top View Table 19 Package Branding Information Branding Key Field Description 375B Part identifier for the ADXL375 RoHS compliant designation yww Date code VVVV Factory lot code CNTY Country of origin Rev B Page 31 of 32 ADXL375 OUTLINE DIMENSIONS PAD A1 BSC CORNER 3 00 0 49 BOTTOM VIEW 0 813 x 0 50 0 50 TOP VIEW T 0 49 gt 1 00 Je 0 95 END VIEW yo 974 0 85 0 69 s oo i SEATING 8 PLANE 3 Figure 40 14 Terminal Land Grid Array LGA CC 14 1 Dimensions shown in millimeters ORDERING GUIDE T
5. 9 a 100 L E O 10 a o 5 LI fa A 5 us 0 t e 100 110 120 130 140 150 160 170 180 190 200 0 50 100 150 200 CURRENT CONSUMPTION pA REFERENCE ACCELERATION 9 Figure 17 Current Consumption at 25 C 100 Hz Output Data Rate Vs 2 5 V Figure 20 Output Linearity over the Dynamic Range 160 1 2 140 a 1 0 T X AXIS 120 E Y AXIS z z Z AXIS E 100 E 08 S 7 2 80 a 0 6 o LI o N E 60 a z E E 40 E a z 20 0 2 i 0 A E 1 60 3 12 6 25 12 50 25 50 100 200 400 800 1600 3200 10 100 1000 OUTPUT DATA RATE Hz FREQUENCY Hz Figure 18 Current Consumption vs Output Data Rate at 25 C Figure 21 Frequency Response 10 Parts Soldered to PCB Vs 2 5 V Rev B Page 9 of 32 ADXL375 THEORY OF OPERATION The ADXL375 is a complete 3 axis acceleration measurement system with a measurement range of 200 g It measures both dynamic acceleration resulting from motion or shock and static acceleration such as gravity The sensor is a polysilicon surface micromachined structure built on top ofa silicon wafer Polysilicon springs suspend the structure over the surface of the wafer and provide resistance against forces due to applied acceleration Deflection of the structure is measured using differential capac itors that consist of independent fixed plates and plates attached to the moving mass Acceleration deflects the proof mass and unbalances the differential capacitor resulting in a sensor output whose amplitude is proportion
6. DATA MULTIPLE BYTE READ MASTER START SLAVE ADDRESS WRITE REGISTER ADDRESS START SLAVE ADDRESS READ ACK NACK STOP SLAVE ACK ACK ACK DATA DATA 1THIS START IS EITHER A REPEATED START OR A STOP FOLLOWED BY A START NOTES 1 THE SHADED AREAS REPRESENT WHEN THE DEVICE IS LISTENING 11669 033 Figure 29 PC Device Addressing Table 13 C Digital Input Output Specifications Limit Parameter Test Conditions Comments Min Max Unit DIGITAL INPUT Low Level Input Voltage Vi 0 3 x VoD yo V High Level Input Voltage Vi 0 7 X Voo yo V Low Level Input Current l Vs Vop yo 0 1 uA High Level Input Current liu Vs 0V 0 1 uA DIGITAL OUTPUT Low Level Output Voltage Voi Vopyo lt 2V lo 3 mA 0 2 X VoD yo V Vopyo 2V lo 3 mA 400 mV Low Level Output Current lot Vor Vot max 3 mA PIN CAPACITANCE fin 1 MHz Vs 2 5 V 8 pF Limits based on characterization results not production tested Rev B Page 18 of 32 ADXL375 Table 14 C Timing T4 25 C Vs 2 5 V Vppyo 1 8 V Limit Parameter Min Max Unit Description fsa 400 kHz SCL clock frequency ti 2 5 US SCL cycle time t 0 6 US SCL high time ts 1 3 US SCL low time ta 0 6 US Hold time for start repeated start condition ts 100 ns Data setup time te 45 0 0 9 US Data hold time t 0 6 US Setup time for repeated start condition ts 0 6 US Setup time for stop condition to 1 3 US Bus free time betwe
7. When using C mode it is required that the CS pin be connected to Vopyo and that the ALT ADDRESS pin be connected to either Vppyo or GND 11669 008 Figure 28 PC Connection Diagram Address 0x53 Due to communication speed limitations the maximum output data rate when using 400 kHz PC mode is 800 Hz which scales linearly with a change in the PC communication speed For example using PC mode at 100 kHz limits the maximum ODR to 200 Hz Operation at an output data rate above the recom mended maximum value may result in undesirable effects on the acceleration data including missing samples or additional noise If other devices are connected to the same I C bus the nominal operating voltage level of the other devices cannot exceed Vpop yo by more than 0 3 V External pull up resistors R are necessary for proper I C operation see Figure 28 To ensure proper opera tion refer to the UM10204 FC Bus Specification and User Manual Rev 03 19 June 2007 when selecting pull up resistor values SINGLE BYTE WRITE MASTER START SLAVE ADDRESS WRITE REGISTER ADDRESS DATA STOP SLAVE ACK ACK ACK MULTIPLE BYTE WRITE MASTER START SLAVE ADDRESS WRITE REGISTER ADDRESS DATA DATA STOP SLAVE ACK ACK ACK ACK SINGLE BYTE READ MASTER START SLAVE ADDRESS WRITE REGISTER ADDRESS START SLAVE ADDRESS READ NACK STOP SLAVE ACK ACK ACK
8. acceleration data To enable low power mode set the LOW POWER bit Bit D4 in the BW RATE register Address 0x2C Sleep mode also provides a low data rate and low power consump tion but it is not intended for data acquisition However when sleep mode is used in conjunction with the autosleep and link modes the part can automatically switch to a low power low sampling rate mode when inactivity is detected To prevent the generation of redundant inactivity interrupts the inactivity interrupt is automatically disabled and the activity interrupt is enabled To enable autosleep mode set the AUTO SLEEP bit Bit D4 and the link bit Bit D5 in the POWER CTL register Address 0x2D When the ADXL375 is in sleep mode the host processor can also be placed into sleep mode or low power mode to save significant system power When activity is detected the accelerometer auto matically switches back to the original data rate of the application and provides an activity interrupt that can be used to wake up the host processor Similar to when inactivity occurs detection of activity events is disabled and detection of inactivity is enabled OFFSET CALIBRATION Accelerometers are mechanical structures containing elements that are free to move These moving parts can be very sensitive to mechanical stresses much more so than solid state electronics The 0 g bias or offset is an important accelerometer metric because it defines the baseline for
9. bit is cleared Measure Bit A setting of 0 in the measure bit places the part into standby mode a setting of 1 places the part into measurement mode The ADXL375 powers up in standby mode with minimum power consumption see the Power Sequencing section Sleep Bit A setting of 0 in the sleep bit places the part into the normal mode of operation a setting of 1 places the part into sleep mode Sleep mode suppresses the DATA READY interrupt stops trans mission of data to the FIFO buffer and switches the sampling rate to the rate specified by the wakeup bits Bits D1 D0 In sleep mode only the activity function can be used When the DATA READY interrupt is suppressed the output data registers Register 0x32 to Register 0x37 are still updated at the sampling rate set by the wakeup bits Before clearing the sleep bit it is recommended that the part be placed in standby mode set the measure bit Bit D3 to 0 After clearing the sleep bit reset the part to measurement mode set the measure bit Bit D3 to 1 Wakeup Bits The wakeup bits control the sampling rate during sleep mode see Table 16 ADXL375 Table 16 Sampling Rate in Sleep Mode Setting D1 DO Frequency Hz 0 0 8 0 1 4 1 0 2 1 1 1 Register OX2E INT ENABLE Read Write D7 D6 D5 D4 DATA READY SINGLE SHOCK DOUBLE SHOCK Activity D3 D2 D1 DO Inactivity 0 Watermark Overrun A setting of 1 for any bit in the
10. data is available these bits are not cleared but are overwritten by the new data Read the ACT SHOCK STATUS register before clearing the inter rupt Disabling an axis from participation in activity or shock events clears the corresponding source bit in this register when the next activity or single shock double shock event occurs The POWER CTL register can be used to configure the device for autosleep mode this register is also used to set the device to measurement mode or standby mode Link Bit The link bit serially links the activity and inactivity functions If both the activity and inactivity functions are enabled a setting of lin the link bit delays the start of the activity detection function until inactivity is detected After activity is detected inactivity detection begins preventing the detection of activity When this bit is set to 0 the inactivity and activity functions are concurrent For more information about the link feature see the Link Mode section Before clearing the link bit it is recommended that the part be placed in standby mode set the measure bit Bit D3 to 0 After clearing the link bit reset the part to measurement mode set the measure bit Bit D3 to 1 This configuration sequence ensures that the device is properly biased if sleep mode is manually disabled otherwise the first few samples of data after the link bit is cleared may have additional noise especially if the device is asleep when the
11. for proper operation Limits based on characterization results with fsax 5 MHz and bus load capacitance of 100 pF not production tested 3 The timing values are referred to the input thresholds Vi and Vi given in Table 11 Output rise and fall times measured with capacitive load of 150 pF ta and tr are not shown in Figure 25 to Figure 27 Rev B Page 17 of 32 ADXL375 IC MODE When the CS pin is tied high to Vppyo the ADXL375 is configured for PC mode PC mode requires a simple 2 wire connection as shown in Figure 28 The ADXL375 conforms to the UM10204 PC Bus Specification and User Manual Rev 03 19 June 2007 available from NXP Semiconductors The ADXL375 supports standard 100 kHz and fast 400 kHz data transfer modes if the bus parameters given in Table 13 and Table 14 are met Single or multiple byte reads and writes are supported as shown in Figure 29 When the ALT ADDRESS pin Pin 12 is tied high to Vpp ro the 7 bit IC address for the device is 0x1D followed by the R W bit In this configuration the write address is 0x3A and the read address is 0x3B An alternate IC address of 0x53 can be selected by grounding the ALT ADDRESS pin see Figure 28 In this configuration the write address is OXA6 and the read address is OXA7 Unused pins have no internal pull up or pull down resistors therefore the CS and ALT ADDRESS pins have no known state or default state if the pins are left floating or unconnected
12. rc Lad rc 6 851 ALIALLISN3S 802 699 11 Ye NOIL V IndOd 4O 1N32H3d 50 35 10 2 40 55 70 85 10 TEMPERATURE C 20 UEZ 9 cc 9 cc voc eec ozz 8c 9 1c vic eic ole 8 02 9 02 voz zoz 0 0c 8 6L A6L vel c 6L 06L 8 8L 9 84 vst e 8L 0 8L SENSITIVITY LSB g Z Axis Sensitivity at 25 CB Z Axis Sensitivity vs Temperature 16 Parts Soldered to P Figure 15 C Vs 2 5 V Figure 12 Vs 2 5V Rev B Page 8 of 32 ADXL375 25 200 20 150 6 G 3 Sous S 3 100 a 2 6 gt E S z a LI 2 9 o T 50 a 5 0 0 di Smonononononononononoeae 2 0 2 4 2 8 3 2 3 6 5 aa EE L a S 8 UU SUPPLY VOLTAGE V 8 SELF TEST RESPONSE LSB Figure 16 Z Axis Self Test Response at 25 C Vs 2 5 V Figure 19 Supply Current vs Supply Voltage Vs at 25 C 25 200 X AXIS DUT1 Z 20 X AXIS DUT2 150 Y AXIS DUT1 Y AXIS DUT2 G Z AXIS DUT1 3 i5 e Z AXIS DUT2 2 S E
13. savings In low power mode the internal sampling rate is reduced allowing for power savings in the 12 5 Hz to 400 Hz data rate range at the expense of slightly greater noise To enter low power mode set the LOW POWER bit Bit D4 in the BW RATE register Address 0x2C Table 8 shows the current consumption in low power mode for output data rates where there is an advantage to using low power mode ADXL375 FIFO BUFFER The ADXL375 contains patented technology for an embedded memory management system with a 32 level FIFO buffer that can be used to minimize host processor burden This buffer has four modes bypass FIFO stream and trigger Each mode can be selected by setting the FIFO MODE bits Bits D7 D6 in the FIFO_CTL register Address 0x38 see Table 9 Table 9 FIFO Modes FIFO CTL Register Address 0x38 Setting FIFO Table 8 Typical Current Consumption vs Data Rate Low Power Mode Ta 25 C Vs 2 5 V Vppro 1 8 V D7 D6 Mode Description Output Data Bandwidth Rate Bits Rate Hz Hz loo pA 1100 400 200 90 1011 200 100 60 1010 100 50 50 1001 50 25 45 1000 25 12 5 40 0111 12 5 6 25 35 0 0 Bypass FIFO buffer is bypassed 0 1 FIFO FIFO buffer collects up to 32 samples and then stops collecting data collecting new data only when the buffer is not full 1 0 Stream FIFO buffer holds the last 32 samples When the buffer is full the oldest data is overwritten with newer d
14. x 1 mm 14 lead LGA FUNCTIONAL BLOCK DIAGRAM Vs Vppuyo SENSE ELECTRONICS SANS LI B SENSOR GND Rev B Trademarks andregistered trademarks are the property of their respective owners Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights ofthird parties that may result fromits use Specifications subjectto change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices FILTER 32 LEVEL FIFO Figure 1 One Tel 781 329 4700 Tech iL Q INT1 ADC mn DIGITAL S INTERRUPT INT2 Tr C SDA SDI SDIO ADDRESS L L SCL SCLK 11669 001 Technology Way P O Box 9106 Norwood MA 02062 9106 U S A 2013 2014 Analog Devices Inc All rights reserved nical Support www analog com ADXL375 TABLE OF CONTENTS FCAOUI S pee E onn yen onsondensossk sen senoyooad ons dossnsonossvs onn 1 Applications yo aaa kika oo UR E RD RE 1 General Description cacesevsisnscesossesscssiersscveseeadednssesdocnasnaseveseuseasevsenades 1 Functional Block Diagram eerte 1 Revision History zc eee esaye avan ae es 2 KT 3 Absolute Maximum Ratings seen 4 Thermal Resistance rt eere 4 ESD Caution netten tentent 4 Soldering Profile rrt R
15. ANALOG DEVICES FEATURES Low power as low as 35 pA in measurement mode and 0 1 pA in standby mode at Vs 2 5 V Power consumption scales automatically with bandwidth Embedded 32 level FIFO buffer minimizes processor load Bandwidth of up to 1 kHz Bandwidth selectable via serial command Shock event detection Activity inactivity monitoring Supply voltage range 2 0 V to 3 6 V UO voltage range 1 7 V to Vs SPI 3 or 4 wire and PC digital interfaces Wide temperature range 40 C to 85 C 10 000 g shock survival Pb free RoHS compliant Small and thin 3 mm x 5 mm x 1 mm LGA package APPLICATIONS Concussion and head trauma detection High force event detection GE 3 Axis 200 g Digital MEMS Accelerometer ADXL375 NERAL DESCRIPTION The ADXL375 is a small thin 3 axis accelerometer that provides low power consumption and high resolution measurement up to 200 g The digital output data is formatted as 16 bit twos complement data and is accessible through a SPI 3 or 4 wire or I An C digital interface integrated memory management system with a 32 level first in first out FIFO buffer can be used to store data to minimize host processor activity and lower overall system power consumption Low power modes enable intelligent motion based power management with threshold sensing and active acceleration measurement at extremely low power dissipation The ADXL375 is supplied in a small thin 3 mm x 5mm
16. E pon on aka ETHER 5 Pin Configuration and Function Descriptions 6 Typical Performance Characteristics sees 7 Theory of Operation ss Power Sequencing sse 10 Current Consumption and Output Data Rate 10 Power Saving Modes serene 11 FIPO Butet esempi eiat 11 Self Testis nie Ee das kos bot dote bod tete P Pu ot babe dok eaaet 12 Intertupts accepere iter iei reip aen 13 Enabling and Disabling Interrupts sss 13 Clearitig Interr pts rere 13 Bits in the Interrupt Registers see 13 REVISION HISTORY 4 14 Rev A to Rev B Changes to Figure 24 aene tene ees 15 Changes to Register Ox1E Register Ox1F Register 0x20 OFSX OFSY OFSZ Read Write Section sese 21 9 13 Rev 0 to Rev A Added MEMS to Product Title sees 1 8 13 Revision 0 Initial Version Serial Communications sese 15 SPE MO Ge che Taa TTT aT 15 C Mode act HD 18 Regist r Map sse eet tee ete eere teres 20 Register Descriptions ecrire 21 Applications Information sees ereenn 26 Power Supply Decoupling eere 26 Mechanical Considerations for Mounting 26 Shock D tection sa sousa eee DR eH eee Rubens 26 Threshold Detection and Bandwidth 27 Link Mode ette RR Ee RR ER HERRERA 27 Sleep Mode vs Low Power Mode
17. Hz 35 uA Standby Mode 0 1 UA Turn On and Wake Up Time ODR 3200 Hz 1 4 ms TEMPERATURE Operating Temperature Range 40 85 C WEIGHT Device Weight 30 mg 1 Typical specifications are for at least 68 of the population of parts and are based on the worst case of mean 1 o distribution except for sensitivity which represents the target value Minimum and maximum specifications represent the worst case of mean 3 o distribution and are not guaranteed in production 3 Cross axis sensitivity is defined as coupling between any two axes The output format for the 1600 Hz and 3200 Hz output data rates is different from the output format for the other output data rates For more information see the Data Formatting at Output Data Rates of 3200 Hz and 1600 Hz section gt Bandwidth is the 3 dB frequency and is half the output data rate bandwidth ODR 2 Output data rates 6 25 Hz exhibit additional offset shift with increased temperature 7 Self test change is defined as the output g when the SELF TEST bit 1 DATA FORMAT register Address 0x31 minus the output g when the SELF TEST bit 0 Due to device filtering the output reaches its final value after 4 x x when enabling or disabling self test where t 1 data rate For the self test to operate correctly the part must be in normal power operation LOW POWER bit 0 in the BW RATE register Address Ox2C Turn on and wake up times are determined by the user define
18. INT ENABLE register enables the specified function to generate interrupts a setting of 0 for any bit in this register prevents the function from generating interrupts The DATA READY watermark and overrun bits enable only the interrupt output the functions are always enabled It is recommended that interrupts be configured in Register Ox2F before their outputs are enabled in this register For more information about the interrupts see the Bits in the Interrupt Registers section Register OX2F INT MAP Read Write D7 D6 D5 D4 DATA READY SINGLE SHOCK DOUBLE SHOCK Activity D3 D2 D1 DO Inactivity 0 Watermark Overrun A setting of 0 for any bit in the INT MAP register causes the specified interrupt to be sent to the INTI pin a setting of 1 for any bit in this register causes the specified interrupt to be sent to the INT2 pin All selected interrupts for a given pin are ORed Register 0x30 INT SOURCE Read Only D7 D6 D5 D4 DATA READY SINGLE SHOCK DOUBLE SHOCK Activity D3 D2 D1 DO Inactivity x Watermark Overrun 1X ignore this bit A setting of 1 for any bit in the INT SOURCE register indicates that the specified function has triggered an interrupt a setting of 0 for any bit in this register indicates that the specified function has not triggered an interrupt The DATA READY watermark and overrun bits are always set if the corresponding interrupt occurs regardles
19. MHz the total delay necessary is at most 3 4 us When PC mode is enabled on the part the communication rate is low enough to ensure a sufficient delay between FIFO reads SELF TEST The ADXL375 incorporates a self test feature that effectively tests its mechanical and electronic systems simultaneously When the self test function is enabled via the SELF TEST bit in the DATA FORMAT register Address 0x31 an electrostatic force is exerted on the mechanical sensor This electrostatic force moves the mechanical sensing element in the same manner as acceleration and it is additive to the external acceleration experienced by the device This added electrostatic force results in an output change in the x y and z axes Because the electrostatic force is proportional to Vs the output change varies with Vs The self test response in the x and y axes exhibits bimodal behavior and therefore is not always a reliable indicator of sensor health or potential shift in device sensitivity For this reason perform the self test check in the z axis Use of the self test feature at data rates of less than 100 Hz or at 1600 Hz may yield values outside the limits shown in Figure 16 For the self test function to operate correctly the part must be in normal power operation LOW POWER bit 0 in the BW RATE register Address 0x2C and be configured for a data rate from 100 Hz to 800 Hz or for a data rate of 3200 Hz see Table 6 For more info
20. SHOCK WINDOW LATENT I TIME LIMIT Pod FOR SHOCKS g INVALIDATES e DOUBLE SHOCK AT END OF DUR ACCELERATION 11669 039 Figure 35 Shock Interrupt Function with Invalid Double Shocks ADXL375 Single shocks double shocks or both can be detected by setting the appropriate bits in the INT ENABLE register Address Ox2E Participation of each of the three axes in single shock double shock detection is controlled by setting the appropriate bits in the SHOCK AXES register Address 0x2A For the double shock function to operate both the latent and window registers must be set to a nonzero value Every mechanical system has somewhat different shock responses based on the mechanical characteristics of the system Therefore some experimentation with values for the DUR latent window and THRESH SHOCK registers is required Setting a very low value in the latent window or THRESH_ SHOCK register can result in unpredictable responses due to the accelerometer picking up echoes of the shock inputs After a shock interrupt is received the first axis to exceed the THRESH SHOCK level is reported in the ACT SHOCK STATUS register Address 0x2B This register is never cleared but is overwritten with new data THRESHOLD DETECTION AND BANDWIDTH Lower output data rates are achieved by decimating a common sampling frequency inside the device The activity and single shock double shock detection functions are performed us
21. THRESH INACT registers to determine whether activity or inactivity is detected In ac coupled operation for activity detection the acceleration value at the start of activity detection is taken as a reference value New samples of acceleration data are then compared to this ref erence value and if the magnitude of the difference exceeds the THRESH ACT value an activity interrupt is triggered Similarly in ac coupled operation for inactivity detection a refer ence value is used for comparison and is updated whenever the device exceeds the inactivity threshold After the reference value is selected the device compares the magnitude of the difference between the reference value and the current acceleration with the THRESH INACT value If the difference is less than the value in the THRESH INACT register for the time specified in the TIME INACT register the device is considered inactive and the inactivity interrupt is triggered Rev B Page 21 of 32 ADXL375 ACT x Enable and INACT x Enable Bits A setting of 1 for the ACT x enable and INACT x enable bits enables x y or z axis participation in detecting activity or inactivity A setting of 0 excludes the selected axis from participa tion If all axes are excluded the function is disabled For activity detection all participating axes are logically ORed causing the activity function to be triggered when any participating axis exceeds the activity threshold For inactivity d
22. Value Description 0x00 0 DEVID R 11100101 Device ID 0x01 to Ox1C 1to 28 Reserved N A N A Reserved do not access Ox1D 29 THRESH SHOCK R W 00000000 Shock threshold Ox1E 30 OFSX RAW 00000000 X axis offset Ox1F 31 OFSY RAW 00000000 Y axis offset 0x20 32 OFSZ R W 00000000 Z axis offset 0x21 33 DUR R W 00000000 Shock duration 0x22 34 Latent R W 00000000 Shock latency 0x23 35 Window R W 00000000 Shock window 0x24 36 THRESH ACT R W 00000000 Activity threshold 0x25 37 THRESH INACT R W 00000000 Inactivity threshold 0x26 38 TIME INACT R W 00000000 Inactivity time 0x27 39 ACT INACT CTL R W 00000000 Axis enable control for activity and inactivity detection Ox2A 42 SHOCK AXES R W 00000000 Axis control for single shock double shock Ox2B 43 ACT SHOCK STATUS R 00000000 Source of single shock double shock Ox2C 44 BW RATE R W 00001010 Data rate and power mode control Ox2D 45 POWER CTL R W 00000000 Power saving features control Ox2E 46 INT ENABLE R W 00000000 Interrupt enable control Ox2F 47 INT MAP R W 00000000 Interrupt mapping control 0x30 48 INT SOURCE R 00000010 Interrupt source 0x31 49 DATA FORMAT R W 00000000 Data format control 0x32 50 DATAXO R 00000000 X Axis Data O 0x33 51 DATAX1 R 00000000 X Axis Data 1 0x34 52 DATAYO R 00000000 Y Axis Data 0 0x35 53 DATAY1 R 00000000 Y Axis Data 1 0x36 54 DATAZO R 00000000 Z Axis Data 0 0x37 55 DATAZ1 R 00000000 Z Axis Data 1 0x38 56 FIFO CTL R W 00000000 FIFO control 0x39 57 FIFO STATUS R 00000000 FIFO status
23. al to acceleration Phase sensitive demodulation is used to determine the magnitude and polarity of the acceleration POWER SEQUENCING Power can be applied to Vs or Vppyo in any sequence without damaging the ADXL375 Table 7 provides a description of all the power modes The interface voltage level is set using the interface supply voltage Vppyo which must be present to ensure that the ADXL375 does not create a conflict on the communi cation bus For single supply operation Vonyo can be the same as the main supply Vs In a dual supply application however Vpp vo can differ from Vs to accommodate the desired interface voltage as long as Vs is greater than or equal to Von yo After Vs is applied the device enters standby mode In standby mode power consumption is minimized the device waits for Vopvyo to be applied and for the command to enter measurement mode This command can be initiated by setting the measure bit Bit D3 in the POWER CTL register Address 0x2D Table 7 Power Modes When the device is in standby mode any register can be written to or read from It is recommended that the device be configured in standby mode before enabling measurement mode Clearing the measure bit returns the device to standby mode CURRENT CONSUMPTION AND OUTPUT DATA RATE The ADXL375 automatically modulates its current consumption in proportion to its output data rate see Table 6 The device bandwidth and output data rate are specified
24. ata 1 1 Trigger FIFO buffer holds the last samples before the trigger event and continues to collect data until full New data is collected only when the buffer is not full For data rates not shown in Table 8 the use oflow power mode does not provide any advantage over normal power mode There fore it is recommended that low power mode be used only for the data rates shown in Table 8 Autosleep Mode Additional power can be saved if the ADXL375 automatically switches to sleep mode during periods of inactivity To enable the autosleep mode feature 1 Set the THRESH INACT register Address 0x25 and the TIME INACT register Address 0x26 to values that signify inactivity The appropriate values depend on the application 2 Setthe AUTO SLEEP bit Bit D4 and the link bit Bit D5 in the POWER CTI register Address 0x2D Current consumption at the sub 12 5 Hz data rates that are used in autosleep mode is typically 35 uA for Vs 2 5 V For information about the advantages of using low power mode vs autosleep mode see the Sleep Mode vs Low Power Mode section Standby Mode For even lower power operation standby mode can be used In standby mode current consumption is reduced to 0 1 pA typical In this mode no measurements are made but the contents of the FIFO buffer are preserved To enter standby mode clear the measure bit Bit D3 in the POWER CTL register Address 0x2D For an in depth descripti
25. ation time is not exceeded If both the single and double shock functions are in use the single shock interrupt is triggered when the double shock event is either validated or invalidated Rev B Page 26 of 32 Several events invalidate the second shock of a double shock event e Ifthe suppress bit in the SHOCK AXES register Bit D3 Address 0x24 is set any acceleration spike above the threshold during the latency time set by the latent register invalidates the double shock detection see Figure 34 m INVALIDATES DOUBLE SHOCK IF SUPPRESS BIT SET ACCELERATION TIME LIMIT gt FOR SHOCKS LATENCY TIME WINDOW FOR SECOND DUR TIME LATENT SHOCK WINDOW 11669 038 Figure 34 Double Shock Event Invalid Due to High g Event When the Suppress Bit Is Set e lt A double shock event can be invalidated if acceleration above the threshold is detected at the start of the time window for the second shock set by the window register resulting in an invalid double shock at the start of this window see Figure 35 e A double shock event can be invalidated if acceleration exceeds the time limit for shocks set by the DUR register resulting in an invalid double shock at the end of the DUR time limit for the second shock event see Figure 35 INVALIDATES DOUBLE SHOCK AT START OF WINDOW ACCELERATION M OR SHOCKS 5 FOR SHOCK aa i DUR TIME LIMIT j FOR SHOCKS LATENCY TIME WINDOW FOR DUR i TME SECOND
26. aximum 8 minutes maximum ADXL375 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADXL375 TOP VIEW Not to Scale SCL SCLK Vpp 1 0 i SDA SDI SDIO GND SDO ALT ADDRESS RESERVED i RESERVED GND NC GND i INT2 Vs INT1 NOTES 1 NC lt NOT INTERNALLY CONNECTED 11669 002 Figure 3 Pin Configuration Table 5 Pin Function Descriptions Pin No Mnemonic Description 1 Vop vo Digital Interface Supply Voltage 2 GND Ground This pin must be connected to ground 3 RESERVED Reserved This pin must be connected to Vs or left open 4 GND Ground This pin must be connected to ground 5 GND Ground This pin must be connected to ground 6 Vs Supply Voltage 7 CS Chip Select 8 INT1 Interrupt 1 Output 9 INT2 Interrupt 2 Output 10 NC Not Internally Connected 11 RESERVED Reserved This pin must be connected to ground or left open 12 SDO ALT ADDRESS SPI 4 Wire Serial Data Output SDO I C Alternate Address Select ALT ADDRESS 13 SDA SDI SDIO PC Serial Data SDA SPI 4 Wire Serial Data Input SDI SPI 3 Wire Serial Data Input and Output SDIO 14 SCL SCLK lC Serial Communications Clock SCL SPI Serial Communications Clock SCLK Rev B Page 6 of 32 ADXL375 TYPICAL PERFORMANCE CHARACTERISTICS 25 1 0 0 8 0 6 N eo 0 4 15 0 2 OFFSET DRIFT g o PERCENT OF POPULATION 95
27. bit is cleared Rev B Page 22 of 32 AUTO SLEEP Bit If the link bit is set a setting of 1 in the AUTO SLEEP bit enables the autosleep function In autosleep mode the ADXL375 automatically switches to sleep mode if the inactivity function is enabled and inactivity is detected that is when acceleration is below the THRESH INACT value for at least the time specified by the TIME INACT value If activity detection is also enabled the ADXL375 automatically wakes up from sleep after detecting activity and returns to operation at the output data rate set in the BW RATE register A setting of 0 in the AUTO SLEEP bit disables automatic switching to sleep mode If the link bit is not set the AUTO SLEEP feature is disabled and setting the AUTO SLEEP bit has no effect on device operation For more information about the link feature see the Link Bit section and the Link Mode section For more information about autosleep mode see the Autosleep Mode section Before clearing the AUTO SLEEP bit it is recommended that the part be placed in standby mode set the measure bit Bit D3 to 0 After clearing the AUTO SLEEP bit reset the part to measure ment mode set the measure bit Bit D3 to 1 This configuration sequence ensures that the device is properly biased if sleep mode is manually disabled otherwise the first few samples of data after the AUTO SLEEP bit is cleared may have additional noise especially if the device is asleep when the
28. d Write The TIME_INACT register contains an unsigned time value representing the amount of time that acceleration must be less than the value in the THRESH_INACT register for inactivity to be detected The scale factor is 1 sec LSB Unlike the other interrupt functions which use unfiltered output data see the Threshold Detection and Bandwidth section the inactivity function uses filtered output data At least one output sample must be generated for the inactivity interrupt to be triggered For this reason the inactivity function may appear to be unresponsive if the TIME_INACT register is set to a value less than the time constant of the output data rate A value of 0 results in an interrupt when the output data is less than the value in the THRESH_INACT register The maximum value for TIME_INACT is 255 sec Register 0x27 ACT INACT CTL Read Write D7 D6 D5 D4 ACT AC DC ACT_Xenable ACT Yenable ACT Z enable D3 D2 D1 DO INACT AC DC INACT X enable INACT Y enable INACT Z enable The ACT INACT CTI register selects dc coupled or ac coupled operation and selects the axes that participate in activity and inactivity detection ACT AC DC and INACT AC DC Bits A setting of 0 for the ACT AC DC and INACT AC DC bits selects dc coupled operation a setting of 1 selects ac coupled operation In dc coupled operation the current acceleration magnitude is compared directly with the values in the THRESH_ ACT and
29. d bandwidth At a 100 Hz data rate the turn on and wake up times are each approximately 11 1 ms For other data rates the turn on and wake up times are each approximately t 1 1 ms where t 1 data rate Rev B Page 3 of 32 ADXL375 ABSOLUTE MAXIMUM RATINGS Table 2 Parameter Rating Acceleration Any Axis Unpowered 10 000 g Powered 10 000 g Vs 0 3V to 3 9V Vop vo 0 3V to 3 9 V Digital Pins 0 3 V to Vooo 0 3 V or 3 9 V whichever is less Output Short Circuit Duration Indefinite Any Pin to Ground Temperature Range Powered 40 C to 105 C Storage 40 C to 105 C THERMAL RESISTANCE Oya is specified for the worst case conditions that is a device soldered in a circuit board for surface mount packages Table 3 Package Characteristics Package Type Osa Bic Unit 14 Terminal LGA 150 85 C W ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge A without detection Although this product features patented or proprietary protection circ
30. e device bandwidth and output data rate this register also enables and disables low power mode LOW POWER Bit A setting of 0 in the LOW POWER bit selects normal opera tion a setting of 1 selects reduced power operation which has somewhat higher noise For more information see the Low Power Mode section Rate Bits The rate bits select the device bandwidth and output data rate see Table 6 and Table 8 The default value for these bits is OxOA which translates to a 100 Hz output data rate The selected output data rate must be appropriate for the communication protocol and frequency selected Selecting an output data rate that is too high for the communication speed may result in samples being discarded for more information see the Serial Communications section Register Ox2D POWER_CTL Read Write D7 D6 D5 D4 D3 D2 D1 DO 0 0 Link AUTO_SLEEP Measure Sleep Wakeup D7 D6 D5 D4 0 ACT_X source ACT_Y source ACT_Z source D3 D2 D1 DO Asleep SHOCK X source SHOCK Y source SHOCK Z source The read only ACT SHOCK STATUS register indicates the first axis involved in an activity or shock event ACT xSource and SHOCK x Source Bits The ACT x source and SHOCK x source bits indicate the first axis involved in an activity or shock event A setting of 1 corresponds to involvement in the event a setting of 0 corre sponds to no involvement When new
31. emperature Measurement Specified Package Model Range Range g Voltage V Package Description Option ADXL375BCCZ 40 C to 85 C 200 2 5 14 Terminal Land Grid Array LGA CC 14 1 ADXL375BCCZ RL 40 C to 85 C 200 2 5 14 Terminal Land Grid Array LGA CC 14 1 ADXL375BCCZ RL7 40 C to 85 C 200 2 5 14 Terminal Land Grid Array LGA CC 14 1 EVAL ADXL375Z 40 C to 85 C Evaluation Board EVAL ADXL375Z M EVAL ADXL375Z S Inertial Sensor Evaluation System Includes ADXL375 Satellite ADXL375 Satellite Standalone can be used with other inertial sensor evaluation systems 1Z RoHS Compliant Part PC refers to a communications protocol originally developed by Philips Semiconductors now NXP Semiconductors 2013 2014 Analog Devices Inc All rights reserved Trademarks and registered trademarks are the property of their respective owners D11669 0 4 14 B ANALOG DEVICES Rev B Page 32 of 32 www analog com
32. en a stop condition and a start condition tio 300 ns Rise time of SCL and SDA when receiving 0 ns Rise time of SCL and SDA when receiving or transmitting tu 300 ns Fall time of SCL and SDA when receiving 250 ns Fall time of SCL and SDA when transmitting Cb 400 pF Capacitive load for each bus line Limits based on characterization results with fsc 400 kHz and a 3 mA sink current not production tested The timing values are referred to the input thresholds Vi and Vin given in Table 13 3 te is the data hold time that is measured from the falling edge of SCL It applies to data during the transmission and acknowledge phases To bridge the undefined region of the falling edge of SCL a transmitting device must internally provide an output hold time of at least 300 ns for the SDA signal with respect to Vin mn of the SCL signal The maximum value for ts must be met only if the device does not stretch the low period ts of the SCL signal The maximum value for te is a function of the clock low time ts the clock rise time tio and the minimum data setup time tsa This value is calculated as tema ts tio taii SDA SCL START CONDITION REPEATED STOP 3 START CONDITION 2 CONDITION i Figure 30 PC Timing Diagram Rev B Page 19 of 32 ADXL375 REGISTER MAP All registers in the ADXL375 are eight bits in length Table 15 Register Map Address Hex Decimal Register Name Access Type Reset
33. er Test Conditions Comments Min Max Unit DIGITAL INPUT Low Level Input Voltage Vi 0 3 X Voo yo V High Level Input Voltage Vi 0 7 X VoD yo V Low Level Input Current Iu Vs Voo yo 0 1 uA High Level Input Current liu Vs OV 0 1 uA DIGITAL OUTPUT Low Level Output Voltage Voi lo 10 mA 0 2 X Vpp yo V High Level Output Voltage Vou lou 4 mA 0 8 x Vpp yo V Low Level Output Current lot Vor Vou max 10 mA High Level Output Current lon Vou Vou min 4 mA PIN CAPACITANCE fn 1 MHz Vs 2 5 V 8 pF Limits based on characterization results not production tested Table 12 SPI Timing Ta 25 C Vs 2 5 V Vppyo 1 8 V Limit Parameter Min Max Unit Description fscux 5 MHz SPI clock frequency tscik 200 ns Mark space ratio 1 SPI clock frequency for the SCLK input is 40 60 to 60 40 tpeLAY 5 ns CS falling edge to SCLK falling edge tout 5 ns SCLK rising edge to CS rising edge tois 10 ns CS rising edge to SDO SDIO disabled tcs pis 150 ns CS deassertion between SPI communications ts 0 3 x tsak ns SCLK low pulse width space tm 0 3 x tsak ns SCLK high pulse width mark tsetup 5 ns SDI SDIO valid before SCLK rising edge thou 5 ns SDI SDIO valid after SCLK rising edge tspo 40 ns SCLK falling edge to SDO SDIO output transition ta 20 ns SDO SDIO output high to output low transition te 20 ns SDO SDIO output low to output high transition The CS SCLK SDI and SDO pins are not internally pulled up or down they must be driven
34. ess 0x38 to 00 3 Configure the device for trigger mode by setting Bits D7 D6 at Address 0x38 to 11 Retrieving Data from the FIFO Buffer When the FIFO buffer operates in FIFO stream or trigger mode FIFO data can be read from the data registers Address 0x32 to Address 0x37 Each time data is read from the FIFO buffer the oldest x y and z axis data is moved into the DATAX DATAY and DATAZ registers Ifa single byte read operation is performed the remaining bytes of data for the current FIFO sample are lost Therefore data for all axes of interest must be read in a burst multiple byte read operation To ensure that the FIFO buffer is empty that is all new data has moved into the data registers an interval of at least 5 us must elapse between the end of the readback from the data registers and the start of a new read of the data registers or the FIFO STATUS register Address 0x39 The end of a read operation from the data registers is signified by the transition from Register 0x37 to Register 0x38 or by the cs pin going high When SPI operation is enabled at a frequency of 1 6 MHz or lower the register addressing portion of the transmission provides a sufficient delay to ensure that the FIFO buffer has completely emptied When SPI operation is enabled at a frequency higher than 1 6 MHz the CS pin must be deasserted to ensure a total delay of 5 us otherwise the delay is not sufficient When SPI operation is enabled at 5
35. etection all parti cipating axes are logically ANDed causing the inactivity function to be triggered only if all participating axes are below the inactivity threshold for the specified time Register OX2A SHOCK AXES Read Write Asleep Bit A setting of 1 in the asleep bit indicates that the part is asleep a setting of 0 indicates that the part is not asleep This bit toggles only if the device is configured for autosleep For more informa tion about the autosleep mode see the AUTO SLEEP Bit section Register OxX2C BW RATE Read Write D7 D6 D5 D4 D3 D2 D1 DO 0 0 0 LOW_POWER Rate D7 D6 D5 D4 0 0 0 0 D3 D2 D1 DO Suppress SHOCK X enable SHOCK Y enable SHOCK Z enable The SHOCK AXES register specifies the participation of each of the three axes in single shock double shock detection Suppress Bit Setting the suppress bit suppresses double shock detection if acceleration greater than the value in the THRESH SHOCK register is present during the latency time between shocks For more information see the Shock Detection section SHOCK x Enable Bits A setting of 1 in the SHOCK X enable SHOCK Y enable or SHOCK Z enable bit enables x y or z axis participation in shock detection A setting of 0 excludes the selected axis from participation in shock detection Register OXx28 ACT SHOCK STATUS Read Only The BW RATE register configures th
36. f 0 disables the single shock and double shock functions Register 0x22 Latent Read Write The latent register contains an unsigned time value representing the wait time from the detection of a shock event to the start of the time window specified by the window register during which a possible second shock event can be detected The scale factor is 1 25 ms LSB A value of 0 disables the double shock function Register 0x23 Window Read Write The window register contains an unsigned time value repre senting the amount of time after the expiration of the latency time specified by the latent register during which a second valid shock can begin The scale factor is 1 25 ms LSB A value of 0 disables the double shock function Register OX24 THRESH ACT Read Write The THRESH_ACT register contains the unsigned threshold value for detecting activity The magnitude of the activity event is compared with the value in the THRESH_ACT register The scale factor is 780 mg LSB A value of 0 may result in undesirable behavior if the activity interrupt is enabled Register 0x25 THRESH_INACT Read Write The THRESH_INACT register contains the unsigned threshold value for detecting inactivity The magnitude of the inactivity event is compared with the value in the THRESH_INACT register The scale factor is 780 mg LSB A value of 0 may result in undesirable behavior if the inactivity interrupt is enabled Register OX26 TIME INACT Rea
37. fer must be set After the register address byte and the first byte of data each subsequent set of eight clock pulses causes the ADXL375 to point to the next register for a read or write This shifting continues until the clock pulses cease and CS is deasserted To perform reads or writes on different nonsequential registers CS must be deasserted between transmissions and the new register must be addressed separately Figure 25 and Figure 26 show the timing diagrams for 4 wire SPI writes and reads respectively Figure 27 shows the timing diagram for 3 wire SPI reads or writes For correct operation of the part the logic thresholds and timing parameters in Table 11 and Table 12 must be met at all times Use of the 3200 Hz and 1600 Hz output data rates is recom mended only with SPI communication speeds greater than or equal to 2 MHz The 800 Hz output data rate is recommended only with communication speeds greater than or equal to 400 kHz and the remaining data rates scale proportionally For example the minimum recommended communication speed for a 200 Hz output data rate is 100 kHz Operation at an output data rate above the recommended maximum value may result in undesirable effects on the acceleration data including missing samples or additional noise Preventing Bus Traffic Errors The ADXL375 CS pin is used both for initiating SPI transactions and for enabling C mode When the ADXL375 is used on a SPI bus with multiple devices it
38. hed and can be cleared as follows 1 Read the data registers Address 0x32 to Address 0x37 to clear the data related interrupts 2 ReadtheINT SOURCE register Address 0x30 to clear the remaining interrupts Table 10 Interrupt Pin Digital Output Specifications ADXL375 BITS IN THE INTERRUPT REGISTERS This section describes the interrupts that can be set in the INT ENABLE register Address Ox2E and monitored in the INT SOURCE register Address 0x30 For an in depth description of the FIFO buffer and the inter rupt bits see the AN 1025 Application Note Utilization of the First In First Out FIFO Buffer in Analog Devices Inc Digital Accelerometers DATA READY Bit The DATA READY bit is set when new data is available and is cleared when no new data is available SINGLE SHOCK Bit The SINGLE SHOCK bit is set when a single acceleration event that is greater than the value in the THRESH SHOCK register Address Ox1D occurs for less time than is specified by the DUR register Address 0x21 For more information see the Shock Detection section DOUBLE SHOCK Bit The DOUBLE SHOCK bit is set when two acceleration events that are greater than the value in the THRESH SHOCK register Address Ox1D occur for less time than is specified by the DUR register Address 0x21 The second shock event starts after the time specified by the latent register Address 0x22 but within the time specified by the window register Address 0
39. ied LSB mode with sign extension Register 0x32 to Register 0x37 DATAXO DATAX1 DATAYO DATAY1 DATAZO DATAZI Read Only These six bytes Register 0x32 to Register 0x37 are each eight bits in length and contain the output data for each axis e Register 0x32 and Register 0x33 contain the output data for the x axis e Register 0x34 and Register 0x35 contain the output data for the y axis e Register 0x36 and Register 0x37 contain the output data for the z axis The output data is in twos complement format DATAxO is the least significant byte and DATAx1 is the most significant byte x represents X Y or Z The DATA FORMAT register Address 0x31 controls the format of the data It is recommended that a multiple byte read of all six registers be performed to prevent a change in data between reads of sequential registers When using the 3200 Hz or 1600 Hz output data rate the LSB of the output data word is always 0 When the data is right justified the LSB corresponds to Bit DO of the DATAxO register when the data is left justified the LSB corresponds to Bit D3 ofthe DATAxO register The FIFO CTL register is used to configure the FIFO buffer for the device For more information see the FIFO Buffer section For an in depth description of the FIFO buffer see the AN 1025 Application Note Utilization of the First In First Out FIFO Buffer in Analog Devices Inc Digital Accelerometers FIFO MODE Bits These bits
40. igure 32 Incorrectly Placed Accelerometers SHOCK DETECTION The shock interrupt function can detect mechanical shock events based on amplitude and pulse width Figure 33 illustrates the following parameters for a valid single shock event and a valid double shock event e Shock detection threshold defined by the THRESH_ SHOCK register Address 0x1D e Maximum shock duration time time limit for shocks defined by the DUR register Address 0x21 e Shock latency time defined by the latent register Address 0x22 The latency time is the waiting period from the end of the first shock until the start of the time window when a second shock can be detected e Time window for second shock defined by the window register Address 0x23 The time window is the interval after the latency time set by the latent register Although a second shock must begin after the latency time expires it need not finish before the end of the time defined by the window register FIRST SHOCK SECOND SHOCK THRESHOLD ACCELERATION Li TIME LIMIT FOR i pr SHOCKS DUR A haremet l TIME WINDOW FOR ME p M EY LATENT WINDOW SINGLE SHOCK DOUBLE SHOCK INTERRUPT INTERRUPT INTERRUPTS 11669 037 Figure 33 Shock Interrupt Function with Valid Single and Double Shocks If only the single shock function is in use the single shock interrupt is triggered when the acceleration goes below the threshold as long as the dur
41. ing undecimated data Because the bandwidth of the output data varies with the data rate and is lower than the bandwidth of the undecimated data the high frequency and high g data that is used to determine activity and single shock double shock events may not be present if the output of the accelerometer is examined This may result in the triggering of these functions when acceleration data does not appear to meet the conditions set by the user for the corresponding function LINK MODE The link bit Bit D5 in the POWER CTL register Address 0x2D can be used to reduce the number of activity interrupts that the processor must service The link bit configures the device to look for activity only after inactivity For proper operation of this feature the processor must still respond to the activity and inactivity interrupts by reading the INT SOURCE register Address 0x30 and therefore clearing the interrupts If an activity interrupt is not cleared the part cannot enter autosleep mode The asleep bit Bit D3 in the ACT SHOCK STATUS register Address 0x2B indicates whether the part is asleep Rev B Page 27 of 32 ADXL375 SLEEP MODE vs LOW POWER MODE In applications where a low data rate and low power consumption are desired at the expense of noise performance it is recom mended that low power mode be used Low power mode preserves the functionality of the DATA READY interrupt and the FIFO buffer for postprocessing of the
42. is respectively The values measured for Xog and Yog correspond to the x and y axis offsets and compensation is performed by subtracting these values from the output of the accelerometer to obtain the actual acceleration as follows XAcrvaL Xmeas Xog Yacruat YmEAs Yog Because the z axis measurement is performed in a 1 g field a no turn or single point calibration scheme assumes an ideal sensitivity Sz for the z axis This value is subtracted from Z g to obtain the z axis offset which is then subtracted from future measured values to obtain the actual value as follows Log Zug m Sz ZACTUAL ZMEAS m Log The ADXL375 can automatically compensate the output for offset by using the offset registers Register Ox1E Register Ox1F and Register 0x20 These registers contain an 8 bit twos complement value that is automatically added to all measured acceleration values the result is then placed into the data registers Because the value placed in an offset register is additive a negative value in the register eliminates a positive offset and a positive value in the register eliminates a negative offset The register has a scale factor of 1 56 g LSB As with all registers in the ADXL375 the offset registers do not retain the values written into them when power is removed from the part Power cycling the ADXL375 returns the offset registers to their default value of 0x00 Because the no turn or single point calibra
43. it D4 in the BW RATE register Address 0x2C 3 After the part is configured for accurate self test measure ment retrieve samples of x y and z axis acceleration data from the sensor and average them together The number of samples averaged is selected by the system designer but a recommended starting point is 0 1 sec worth of data for data rates of 100 Hz or greater that is 10 samples at the 100 Hz data rate 4 Store the averaged values and label them appropriately as the values with self test disabled that is XST OFF YST OFE and ZST OFF 5 Enable self test by setting the SELF TEST bit Bit D7 in the DATA FORMAT register Address 0x31 The output requires some time approximately four samples to settle after self test is enabled 6 After allowing the output to settle retrieve samples of x y and z axis acceleration data and average them together It is recommended that the same number of samples be taken for the self test average as was done for the non self test average ADXL375 7 Store the averaged values and label them appropriately as the values with self test enabled that is XST_ON YST_ON and ZST_ON 8 Disable self test by clearing the SELF_TEST bit Bit D7 in the DATA_FORMAT register Address 0x31 With the stored values for self test enabled and disabled the self test change is as follows Xsr Xst_on Xsr orr Ysr Ysr on Ysr orr Zsr Zst on Zst orr Because the measured ou
44. measuring acceleration Additional stresses can be applied during assembly of a system containing an accelerometer These stresses can come from but are not limited to component soldering board stress during mounting and application of any compounds on or over the component If calibration is deemed necessary it is recommended that it be performed after system assembly to compensate for these effects A simple method of calibration is to measure the offset while assuming that the sensitivity of the ADXL375 is as specified in Table 1 The offset can then be automatically accounted for by using the built in offset registers The result of this calibration is that the data acquired from the data registers already compensates for any offset In a no turn or single point calibration scheme the part is oriented such that one axis typically the z axis is in the 1 g field of gravity and the remaining axes typically the x and y axes are in a 0 g field The output is then measured by taking the average of a series of samples The number of samples averaged is selected by the system designer but a recommended starting point is 0 1 sec worth of data for data rates of 100 Hz or greater that is 10 samples at the 100 Hz data rate For data rates less than 100 Hz it is recom mended that at least 10 samples be averaged These values are stored as Xog Yog and Zi for the 0 g measurements on the x and y axes and the 1 g measurement on the z ax
45. on of the FIFO buffer and FIFO modes see the AN 1025 Application Note Utilization of the First In First Out FIFO Buffer in Analog Devices Inc Digital Accelerometers Bypass Mode In bypass mode the FIFO buffer is not operational and there fore remains empty FIFO Mode In FIFO mode data from measurements of the x y and z axes is stored in the FIFO buffer When the number of samples in the FIFO buffer equals the level specified by the samples bits of the FIFO CTL register Address 0x38 the watermark interrupt is set see the Watermark Bit section The FIFO buffer continues to accumulate samples until it is full 32 samples from measure ments of the x y and z axes and then stops collecting data After the FIFO buffer stops collecting data the device continues to operate therefore features such as shock detection can be used after the FIFO buffer is full The watermark interrupt bit remains set until the number of samples in the FIFO buffer is less than the value stored in the samples bits of the FIFO CTL register Stream Mode In stream mode data from measurements of the x y and z axes is stored in the FIFO buffer When the number of samples in the FIFO buffer equals the level specified by the samples bits of the FIFO CIL register Address 0x38 the watermark interrupt is set see the Watermark Bit section The FIFO buffer continues to accumulate samples the buffer stores the latest 32 samples from measu
46. own in Figure 22 and Figure 23 Clearing the SPI bit Bit D6 in the DATA FORMAT register Address 0x31 selects 4 wire mode setting the SPI bit selects 3 wire mode The maxi mum SPI clock speed is 5 MHz with 100 pF maximum loading The timing scheme requires clock polarity CPOL 1 and clock phase CPHA 1 If power is applied to the ADXL375 before the clock polarity and phase of the host processor are configured take the CS pin high before changing the clock polarity and phase When using 3 wire SPI mode it is recommended that the SDO pin be either pulled up to Vpp yo or pulled down to GND via a 10 kQ resistor ADXL375 PROCESSOR 11669 004 11669 003 Figure 23 4 Wire SPI Connection Diagram CS is the serial port enable line and is controlled by the SPI master This line must go low at the start ofa transmission and high at the end ofa transmission as shown in Figure 25 to Figure 27 SCLK is the serial port clock and is supplied by the SPI master SCLK should idle high during a period of no transmission In 4 wire SPI mode SDI and SDO are the serial data input and output respectively In 3 wire SPI mode SDIO functions as both the serial data input and output Data is updated on the falling edge of SCLK and should be sampled on the rising edge of SCLK ADXL375 To read or write multiple bytes in a single transmission the multiple byte bit MB in Figure 25 to Figure 27 located after the R W bit in the first byte trans
47. rements of the x y and z axes discarding older data as new data arrives The watermark interrupt bit remains set until the number of samples in the FIFO buffer is less than the value stored in the samples bits of the FIFO_CTL register Rev B Page 11 of 32 ADXL375 Trigger Mode In trigger mode the FIFO buffer accumulates samples storing the latest 32 samples from measurements ofthe x y and z axes After a trigger event occurs an interrupt is sent to the INT1 or INT2 pin determined by the trigger bit in the FIFO CTL register and the FIFO TRIG bit Bit D7 is set in the FIFO STATUS register Address 0x39 The FIFO buffer keeps the last n samples n is the value specified by the samples bits in the FIFO_CTL register and then operates in FIFO mode collecting new samples only when the FIFO buffer is not full A delay of at least 5 us must elapse between the occur rence of the trigger event and the start of data readback from the FIFO buffer to allow the buffer to discard and retain the necessary samples Additional trigger events cannot be recognized until the part is reset to trigger mode To reset the part to trigger mode l Ifdesired read data from the FIFO buffer see the Retrieving Data from the FIFO Buffer section Before resetting the part to trigger mode read back the FIFO data placing the device into bypass mode clears the FIFO buffer 2 Configure the device for bypass mode by setting Bits D7 D6 at Addr
48. rmation about the self test feature see the Using Self Test section Rev B Page 12 of 32 INTERRUPTS The ADXL375 provides two output pins for driving interrupts INTI and INT2 Both interrupt pins are push pull low impedance pins see Table 10 for output specifications The default config uration of the interrupt pins is active high The polarity can be changed to active low by setting the INT INVERT bit Bit D5 in the DATA FORMAT register Address 0x31 All interrupt functions can be enabled simultaneously but some functions may need to share the same interrupt pin ENABLING AND DISABLING INTERRUPTS Interrupts are enabled by setting the appropriate bits in the INT ENABLE register Address 0x2E the interrupt is mapped to the INTI pin or the INT2 pin based on the contents of the INT MAP register Address Ox2F When the user configures the interrupt pins for the first time it is recommended that the functions and interrupt mapping be configured before the interrupts are enabled When changing the configuration of an interrupt follow this procedure l Disable the interrupt by clearing the bit corresponding to the function in the INT ENABLE register 2 Reconfigure the interrupt function 3 Reenable the interrupt in the INT ENABLE register Configuration of the functions while the interrupts are disabled helps to prevent the accidental generation of an interrupt CLEARING INTERRUPTS The interrupt functions are latc
49. s Soldered to PCB Vs 2 5 V Rev B Page 7 of 32 ADXL375 602 69911 Mi e a sey am ces m e CC OG e o o o o or 23 0 22 5 22 0 6 891 ALIALLISN3S 902 69911 25 2 1 o uw o N NOLLW1NdOd 40 1N32H3d 10 25 40 55 70 85 10 TEMPERATURE C 20 50 35 o ez 8 cc 9 cc baz ez ozz 8c Ole vic etc ole 8 02 9 02 v oc zoz 0 02 86L 9 6L TBL z6L 06L 8 8L 9 8r v 8l eek 0 81 SENSITIVITY LSB g X Axis Sensitivity at 25 CB 16 Parts Soldered to P X Axis Sensitivity vs Temperature Figure 13 C Vs 2 5 V Figure 10 Vs 2 5V 012 699L1 100 85 70 55 40 25 10 TEMPERATURE C e a i 8 8 o w o Q Q o Q o Q oi ma A A r O O Q Q o o N N N N A A N r m ml r 6 851 ALIALLISN3S 102 6991 L Ye NOIL V IndOd 40 1N32H3d SENSITIVITY LSB g Y Axis Sensitivity at 25 CB 16 Parts Soldered to P Y Axis Sensitivity vs Temperature Figure 14 C Vs 2 5V p Figure 11 Vs 2 5V LLZ 699LL eo w eo w o w o w o w o e a a e e o o e e N N N N N N N
50. s cs pin is held high while the master communicates with the other devices There may be conditions where a SPI command transmitted to another device looks like a valid PC command In this case the ADXL375 interprets this command as an attempt to communicate in PC mode and may interfere with other bus traffic Unless bus traffic can be ade quately controlled to ensure that such a condition never occurs it is recommended that a logic gate be added in front of Pin 13 SDA SDI SDIO as shown in Figure 24 This OR gate holds the SDA line high when CS is high to prevent SPI bus traffic at the ADXL375 from appearing as an I C start command ADXL375 PROCESSOR 11669 104 Figure 24 Recommended SPI Connection Diagram When Using Multiple SPI Devices on a Single Bus Rev B Page 15 of 32 ADXL375 SCLK tsetup SDI v DATA BITS Figure 25 SPI 4 Wire Write Timing Diagram SDO tquiet 11669 017 tes pis 11669 018 SCLK tsetup J ipis gt spo O on Com L y DATA BITS Figure 26 SPI 4 Wire Read Timing Diagram cs e eu tpELAY tscLk tm ts SCLK SDIO tauieT lcs pis Y NS ADDRESS BITS DATA BITS NOTES 1 tspo IS ONLY PRESENT DURING READS Figure 27 SPI 3 Wire Read Write Timing Diagram Rev B Page 16 of 32 tspo JA J 11669 019 ADXL375 Table 11 SPI Digital Input Output Specifications Limit Paramet
51. s of the settings in the INT ENABLE register these bits are cleared by reading data from the data registers Address 0x32 to Address 0x37 The DATA READY and water mark bits may require multiple reads to be cleared Other bits and their corresponding interrupts are cleared by reading the INT SOURCE register Rev B Page 23 of 32 ADXL375 Register 0x31 DATA FORMAT Read Write Register 0x38 FIFO CTL Read Write D7 D6 D5 D4 D3 D2 D1 DO D7 D6 D5 D4 D3 D2 D1 DO SELF TEST SPI INT_INVERT 0 1 Justify 1 1 FIFO_MODE Trigger Samples The DATA_FORMAT register controls the presentation of data to Register 0x32 through Register 0x37 SELF_TEST Bit A setting of 1 in the SELF_TEST bit applies a self test force to the sensor causing a shift in the output data A value of 0 disables the self test force For more information about the self test function see the Self Test section and the Using Self Test section SPI Bit A value of 1 in the SPI bit configures the device for 3 wire SPI mode a value of 0 configures the device for 4 wire SPI mode INT_INVERT Bit A value of 0 in the INT_INVERT bit sets the polarity of the interrupt pins to active high a value of 1 sets the polarity of the interrupt pins to active low Justify Bit A setting of 1 in the justify bit selects left justified MSB mode a setting of 0 selects right justif
52. s set when the number of samples in the FIFO buffer equals the value stored in the samples bits Bits D4 D0 of the FIFO_CTL register Address 0x38 The watermark bit is cleared automatically when the FIFO buffer is read and the FIFO contents return to a value below the value specified by the samples bits Overrun Bit The overrun bit is set when new data replaces unread data The precise operation of the overrun function depends on the FIFO mode see the FIFO Buffer section e In bypass mode the overrun bit is set when new data replaces unread data in the data registers Address 0x32 to Address 0x37 e In FIFO mode stream mode and trigger mode the overrun bit is set when the FIFO buffer is full The overrun bit is automatically cleared when the FIFO buffer contents are read Rev B Page 14 of 32 SERIAL COMMUNICATIONS The ADXL375 supports IC and SPI digital communications In both cases the ADXL375 operates as a slave device When the cs pin is tied high to Vppyo C mode is enabled The CS pin must be tied high to Vppyo or be driven by an external controller If the CS pin is left unconnected the user may not be able to communi cate with the part In SPI mode the CS pin is controlled by the bus master In both SPI and PC modes of operation ignore data transmitted from the ADXL375 to the master device during writes to the ADXL375 SPI MODE The ADXL375 can be configured for 3 wire SPI mode or 4 wire SPI mode as sh
53. set the FIFO mode as described in Table 17 Table 17 FIFO Modes Setting FIFO D7 D6 Mode Description 0 0 Bypass FIFO buffer is bypassed 0 1 FIFO FIFO buffer collects up to 32 samples and then stops collecting data collecting new data only when the buffer is not full 1 0 Stream FIFO buffer holds the last 32 samples When the buffer is full the oldest data is overwritten with newer data 1 1 Trigger FIFO buffer holds the last samples before the trigger event and continues to collect data until full New data is collected only when the buffer is not full Trigger Bit A value of 0 in the trigger bit links the trigger event of trigger mode to the INT1 pin and a value of 1 links the trigger event to the INT2 pin Samples Bits The function of the samples bits depends on the FIFO mode selected see Table 18 Entering a value of 0 in the samples bits immediately sets the watermark bit in the INT_SOURCE register regardless of the FIFO mode selected Undesirable operation may occur if a value of 0 is used for the samples bits when trigger mode is used Table 18 Samples Bits Functions FIFO Mode Samples Bits Function Bypass None FIFO Specifies how many FIFO entries are needed to trigger a watermark interrupt Stream Specifies how many FIFO entries are needed to trigger a watermark interrupt Trigger Specifies how many FIFO samples are retained in the FIFO buffer before a trigger e
54. sing the bypass capacitance on Vs to a 10 uP tantalum capacitor in parallel with a 0 1 uF ceramic capacitor may also improve noise performance Make sure that the connection from the ADXL375 ground to the power supply ground has low impedance because noise trans mitted through ground has an effect similar to noise transmitted through Vs It is recommended that Vs and Vppyo be separate supplies to minimize digital clocking noise on the Vs supply If it is not possible to use separate supplies additional filtering of the supplies as previously mentioned may be necessary Vs Vpp vo Vpp vo ADXL375 INTERRUPT S RES SPI OR PC CONTROL INTERFACE 11669 016 Figure 31 Application Diagram MECHANICAL CONSIDERATIONS FOR MOUNTING Mount the ADXL375 on the PCB in a location close to a hard mounting point of the PCB to the case Mounting the ADXL375 at an unsupported PCB location as shown in Figure 32 may result in large apparent measurement errors due to undampened PCB vibration Locating the accelerometer near a hard mounting point ensures that any PCB vibration at the accelerometer is above the mechanical sensor resonant frequency of the accelerometer and is therefore effectively invisible to the accelerometer Multiple mounting points close to the sensor and or a thicker PCB also help to reduce the effects of system resonance on the performance of the sensor ACCELEROMETERS PCB kot 4 MOUNTING POINTS 11669 036 F
55. tion method assumes an ideal sensitivity in the z axis any error in the sensitivity results in offset error DATA FORMATTING AT OUTPUT DATA RATES OF 3200 HZ AND 1600 HZ When using the 3200 Hz or 1600 Hz output data rate the LSB of the output data word is always 0 When the data is right justified the LSB corresponds to Bit DO of the DATAxO register when the data is left justified the LSB corresponds to Bit D3 of the DATAxO register Rev B Page 28 of 32 USING SELF TEST The self test change is defined as the difference between the acceleration output of an axis with self test enabled and the acceleration output of the same axis with self test disabled Due to device filtering the output reaches its final value after 4 x t when enabling or disabling self test where t 1 data rate This definition assumes that the sensor does not move between these two measurements if the sensor moves a non self test related shift corrupts the test Proper configuration of the ADXL375 is necessary for an accurate self test measurement To configure the part for self test follow this procedure 1 Set the data rate from 100 Hz to 800 Hz or set the data rate to 3200 Hz by writing to the rate bits Bits D3 D0 in the BW RATE register Address 0x2C Write a value from Ox0A to OxOD or write OxOF to the BW RATE register 2 For accurate self test measurements configure the part for normal power operation by clearing the LOW_POWER bit B
56. tput for each axis is expressed in LSBs Xsr Ysr and Zsr are also expressed in LSBs These values can be converted to acceleration g by multiplying each value by the 49 mg LSB scale factor If the self test change is within the valid range the test is considered successful Generally a part is considered to pass if the minimum magnitude of change is achieved However a part that changes by more than the maximum magnitude is not necessarily a failure The self test response in the x and y axes exhibits bimodal behavior and therefore is not always a reliable indicator of sensor health or potential shift in device sensitivity For this reason perform the self test check in the z axis Another effective method for using the self test to verify accel erometer functionality is to toggle the self test at a certain rate and then perform an FFT on the output The FFT should have a corresponding tone at the frequency where the self test was toggled Using an FFT in this way removes the dependency of the test on supply voltage and self test magnitude which can vary within a rather wide range Rev B Page 29 of 32 ADXL375 AXES OF ACCELERATION SENSITIVITY Az Ay Ax 11669 021 Figure 36 Axes of Acceleration Sensitivity Corresponding Output Voltage Increases When Accelerated Along the Sensitive Axis Xour 19 Your 0g Zour 0g GRAVITY Xout 0g wl Xour 09 Your 19 Your 19 Zour 09 Zour 09 Your n
57. uitry damage dy A may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Rev B Page 4 of 32 SOLDERING PROFILE Figure 2 and Table 4 provide information about the recommended soldering profile TEMPERATURE RAMP UP ts PREHEAT RAMP DOWN t25 C TO PEAK TIME CRITICAL ZONE T TO Tp 11669 015 Figure 2 Recommended Soldering Profile Table 4 Recommended Soldering Profile Limits ADXL375 Profile Feature Sn63 Pb37 Pb Free Average Ramp Rate T to Tp Preheat Minimum Temperature Tsmin Maximum Temperature Tsmax Time from Tsmi to Tsmax ts Ramp Up Rate Tsmax to TU Liquidous Temperature Ti Time Maintained Above Ti ti Peak Temperature Tp Time Within 5 C of Actual Tp te Ramp Down Rate Time 25 C t25 C to Peak Temperature Based on JEDEC Standard J STD 020D 1 For best results the soldering profile should be in accordance with the recommendations of the manufacturer of the solder paste used 3 C sec maximum 100 C 150 C 60 sec to 120 sec 3 C sec maximum 183 C 60 sec to 150 sec 240 C 0 C 5 C 10 sec to 30 sec 6 C sec maximum 6 minutes maximum Rev B Page 5 of 32 3 C sec maximum 150 C 200 C 60 sec to 180 sec 3 C sec maximum 217 C 60 sec to 150 sec 260 C 0 C 5 C 20 sec to 40 sec 6 C sec m
58. using the rate bits Bits D3 D0 in the BW RATE register Address 0x2C Table 6 Typical Current Consumption vs Data Rate Ta 25 C Vs 2 5 V Vppyo 1 8 V Output Data Bandwidth Rate Bits Rate Hz Hz lbo HA 1111 3200 1600 145 1110 1600 800 90 1101 800 400 140 1100 400 200 140 1011 200 100 140 1010 100 50 140 1001 50 25 90 1000 25 12 5 60 0111 12 5 6 25 50 0110 6 25 3 13 40 0101 3 13 1 56 35 0100 1 56 0 78 35 0011 0 78 0 39 35 0010 0 39 0 20 35 0001 0 20 0 10 35 0000 0 10 0 05 35 Power Mode Vs Vooo Description Power Off Off Off Bus Disabled On Off Bus Enabled Off On Standby or Measurement On On The device is completely off but it is still possible for the device to create a conflict on the communication bus The device is on in standby mode but communication is unavailable and the device can create a conflict on the communication bus Minimize the duration of the bus disabled state during power up to prevent a conflict on the communication bus No functions are available but the device does not create a conflict on the communication bus At power up the device is in standby mode awaiting a command to enter measurement mode and all sensor functions are off After the device is instructed to enter measurement mode all sensor functions are available Rev B Page 10 of 32 POWER SAVING MODES Low Power Mode A low power mode is available for additional power
59. vent Rev B Page 24 of 32 ADXL375 Register 0x39 FIFO STATUS Read Only D7 D6 D5 D4 D3 D2 D1 DO FIFO TRIG 0 Entries The read only FIFO STATUS register indicates whether a trigger event has occurred and reports the number of data values stored in the FIFO buffer FIFO TRIG Bit When the FIFO TRIG bit is set to 1 a trigger event has occurred when the FIFO TRIG bit is set to 0 no trigger event has occurred Entries Bits The entries bits report how many data values are stored in the FIFO buffer The data stored in the FIFO buffer is accessed by reading the data registers Address 0x32 to Address 0x37 FIFO reads must be done in burst mode multiple byte mode because each FIFO level is cleared after any read single or multiple byte of the FIFO buffer The FIFO buffer stores a maximum of 32 entries which equates to a maximum of 33 entries available at any given time because an additional entry is available at the output filter of the device Rev B Page 25 of 32 ADXL375 APPLICATIONS INFORMATION POWER SUPPLY DECOUPLING A 1 uF tantalum capacitor Cs at Vs and a 0 1 uF ceramic capac itor Cro at Von vo placed close to the ADXL375 supply pins are recommended to adequately decouple the accelerometer from noise on the power supply If additional decoupling is necessary a resistor or ferrite bead no larger than 100 Q in series with Vs may be helpful Additionally increa
60. x23 For more information see the Shock Detection section Activity Bit The activity bit is set when acceleration greater than the value stored in the THRESH ACT register Address 0x24 is experi enced on any participating axis Participating axes are specified bythe ACT INACT CTL register Address 0x27 Limit Parameter Test Conditions Comments Min Max Unit DIGITAL OUTPUT Low Level Output Voltage Voi lo 300 pA 0 2 X VoD yo V High Level Output Voltage Vou lou 150 pA 0 8 X Vpp vo V Low Level Output Current lot Vor Vot max 300 uA High Level Output Current lon Von Von MIN 150 uA PIN CAPACITANCE hu 1 MHz Vs 2 5 V 8 pF RISE FALL TIME Cioap 150 pF Rise Time tr 210 ns Fall Time tc 150 ns Limits based on characterization results not production tested Rise time is measured as the transition time from Vo max to Vou min of the interrupt pin 3 Fall time is measured as the transition time from Von mn to Vo max of the interrupt pin Rev B Page 13 of 32 ADXL375 Inactivity Bit The inactivity bit is set when acceleration less than the value stored in the THRESH_INACT register Address 0x25 is experienced for more time than is specified by the TIME_INACT register Address 0x26 on all participating axes Participating axes are specified by the ACT_INACT_CTL register Address 0x27 The maximum value for TIME_INACT is 255 sec Watermark Bit The watermark bit i

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