M16C/65C Group Application Note Using the Voltage Detector
Contents
1. 5 2 to Figure 5 5 show register settings associated with voltage detectors Setting voltage detector 0 7 PTET Protect register PRCR PRC3 Protect bit 3 Enable writing to registers VCR2 VWCE VD1LS VWOC VW1C and VW2C 1 Write enabled Toiy CEE detector operation enable register VC25 Voltage detector 0 enable bit The detector operates when td E A 1 Voltage detector 0 enabled elapses after the VC25 bit is set to 1 Wait for td E A a f fafa 1 1 Voltage monitor 0 control register ait for t t VWOCO Voltage monitor 0 reset enable bit l 1 Enabled l L Reserved bit Set to 1 bi ARARONEN Protect register PRCR PRC3 Protect bit 3 Enable writing to registers VCR2 VWCE VD1LS VWOC VW1C and VW2C 1 Write disabled Figure 5 2 Setting Registers Associated with Voltage Monitor 0 RO1AN0679EJ0100 Rev 1 00 2tENESAS Page 10 of 16 Sep 30 2011 M16C 65C Group Using the Voltage Detector Setting voltage detector 1 b7 bO 1 Protect register PRCR PRC3 Protect bit 3 Enable writing to registers VCR2 VWCE VD1LS VWOC VW1C and VW2C 1 Write enabled bi 0 00 0 o o o 1 Voltage monitor function select register VWCE VW12E Voltage monitors 1 and 2 enable bit 1 Voltage monitors 1 and 2 enabled l _ Reserved bits Set to 0 bO 0 0 o o o 1 1 0 Voltage detector 1 level select register VD1LS VD1LS3 to VD1LSO Vdet1 select bit 0110 Vdet1 6 102. an on chip power on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited The reserved addresses are provided for the possible future expansion of functions Do not access these addresses the correct operation of LSI is not guaranteed if they are accessed Clock Signals After applying a reset only release the reset line after the operating clock signal has become stable When switching the clock signal during program execution wait until the target clock signal has stabilized When the clock signal is generated with an external resonator or from an external oscillator during a reset ensure that the reset line is only released after full stabilization of the clock signal Moreover when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress wait until the target clock signal is stable Differences between Products Before changing from one product to another i e to one with a different part number confirm that the change will not lead to problems The characteristics of MPU MCU in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern When changing to products of different part numbers im
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5. the message Over Vdet2 to the PC Figure 5 6 Interrupt Handling and Register Setting 1 2 RO1AN0679EJ0100 Rev 1 00 ztENESAS Page 14 of 16 Sep 30 2011 M16C 65C Group Using the Voltage Detector 3 Vdet1 passage When passed downward through Vdet1 1 Change the conditions to generate the voltage monitor 1 interrupt b7 b0 Voltage monitor 1 control register AIII wre VW1C0 Voltage monitor 1 interrupt reset enable bit 0 Disabled Voltage monitor 1 control register VW1C VW1C7 Voltage monitor 1 interrupt reset generation condition select bit 0 When VCC1 reaches or goes above Vdet1 Voltage monitor 1 control register VW1C VW1C2 Voltage change detection flag 0 Not detected PTT TTT ne monitor 1 control register T VW1C0 Voltage monitor 1 interrupt reset enable bit 1 Enabled 1 Transmit the message Under Vdet1 to the PC When passed upward through Vdet1 1 Change the conditions to generate the voltage monitor 1 interrupt b7 2 Voltage monitor 1 control register AILI o wre VW1C0 Voltage monitor 1 interrupt reset enable bit 0 Disabled Voltage monitor 1 control register VW1C VW1C7 Voltage monitor 1 interrupt reset generation condition select bit 1 When VCC1 reaches or goes below Vdet1 b7 bo eee ee VW1C2 Voltage change detection flag 0 Not detected b7 bo Voltage monitor 1 control register FLEE EEL Ey wwe L VW1CO0 Voltage monitor 1 interrupt res
6. 11 Vdet1_B 1111 Vdet1_F Only set the values listed above Reserved bits Set to 0 b7 bO PITIT Cee detector operation enable register The detector operates when td E A VC26 Voltage detector 1 enable bit RE 1 1 l elapses after the VC26 bit is set to 1 1 Voltage detector 1 enabled Wait for td E A Continued on next page Figure 5 3 Setting Registers Associated with Voltage Monitor 1 1 2 RO1AN0679EJ0100 Rev 1 00 2tENESAS Page 11 of 16 Sep 30 2011 M16C 65C Group Using the Voltage Detector Continued from previous page Setting voltage detector 1 b7 b0 When using the digital filter select the Voltage monitor 1 control register sampling clock for the digital filter A VW1C iit VW1C7_ Voltage monitor 1 interrupt reset generation condition select bit 0 When VCC1 reaches or goes above Vdet1 1 When VCC1 reaches or goes below Vdet1 VWIC 7 VW1C1 Voltage monitor 1 digital filter disable mode select bit 0 Digital filter enabled 1 Digital filter disabled b0 1 Voltage monitor 1 control register T When using the digital filter set this bit to 0 digital filter enabled b0 of wie monitor 1 control register VW1C6 Voltage monitor 1 mode select bit 0 Voltage monitor 1 interrupt at Vdet1 passage 1 Voltage monitor 1 reset at Vdet1 passage bO Voltage monitor 1 control register VW1C gee changa detection fag When using the digital filter add process
7. RENESAS APPLICATION NOTE M16C 65C Group RO1AN0679EJ0100 A Rev 1 00 Using the Voltage Detector Sep 30 2011 1 Abstract This document describes an application example for using the voltage detector The sample code shows how to detect the rise or fall of VCC1 input voltage using the voltage detector 2 introduction The application example described in this document applies to the following microcomputer MCU e MCU M16C 65C Group When using this application note with other Renesas MCUs careful evaluation is recommended after making modifications to comply with the alternate MCU The sample code operates under following conditions e XIN frequency 8 MHz e Message transmission Channel UART1 Communication settings e Baud rate 38400 bps e Data length 8 bits e Parity None e Stop bit 1 bit e Flow control None Depending on the MCU used the surrounding temperature and other variables characteristics for the voltage detector such as the detection voltage and detection time will vary within the range listed in the Electrical Characteristics chapter of the User s Manual Hardware The settings described in this document are examples used only for reference The variation in the electrical characteristics should be considered when designing your system Refer to the User s Manual Hardware for details on electrical characteristics RO1AN0679EJ0100 Rev 1 00 7tENESAS Page 1 of 16 Sep 30 2011 M16C 65C Group Us
8. able 4 2 shows Procedure for Setting Voltage Monitor 0 Reset Related Bits Table 4 3 shows Procedure for Setting Voltage Monitor 1 Interrupt Reset Related Bits Table 4 4 shows Procedure for Setting Voltage Monitor 2 Interrupt Reset Related Bits Table 4 2 Procedure for Setting Voltage Monitor 0 Reset Related Bits Processing Set the VC25 bit in the VCR2 register to 1 voltage detector 0 enabled Wait for td E A Set the VWOCO bit in the VWOC register to 1 voltage monitor 0 reset enabled RO1AN0679EJ0100 Rev 1 00 ztENESAS Page 6 of 16 Sep 30 2011 M16C 65C Group Using the Voltage Detector Table 4 3 Procedure for Setting Voltage Monitor 1 Interrupt Reset Related Bits When Using the Digital Filter When Not Using the Digital Filter Voltage monitor 1 interrupt Voltage monitor 1 reset Voltage monitor 1 interrupt Voltage monitor 1 reset Set the VW12E bit in the VWCE register to 1 voltage monitors 1 and 2 enabled Set bits VD1LS3 to VD1LSO in the VD1LS register to select Vdet1 Set the VC26 bit in the VCR2 register to 1 voltage detector 1 enabled Wait for td E A Use bits VW1F1 and VW1F0 in the VWW1C register to select the digital filter sampling clock Use the VW1C7 bit in the VW1C register to select the timing of the interrupt and reset request 1 Set the VW1C1 bit in the VW1C register to 0 digital filter enabled Set the VW1C1 bit in th
9. al to or above Vdet2 and the voltage monitor 2 interrupt occurs e Transmit the message Over Vdet2 to the PC e Change the condition for the voltage monitor 2 interrupt to VCC1 lt Vdet2 Operation when the voltage monitor 1 interrupt occurs When VCC1 is equal to or below Vdet1 and the voltage monitor 1 interrupt occurs e Transmit the message Under Vdet1 to the PC e Change the condition for the voltage monitor 1 interrupt to VCC1 2 Vdet1 When VCC1 is equal to or above Vdet1 and the voltage monitor 1 interrupt occurs e Transmit the message Over Vdet1 to the PC e Change the condition for the voltage monitor 1 interrupt to VCC1 lt Vdet1 C Operation when the voltage monitor 0 reset occurs Reset is executed Note 1 Count ports P4_0 to P4_2 Alarm port P4_3 RO1AN0679EJ0100 Rev 1 00 2tENESAS Page 2 of 16 Sep 30 2011 M16C 65C Group Using the Voltage Detector 3 2 Circuit Example Figure 3 1 shows the Power On Reset Circuit 4 7kQ reference Figure 3 1 Power On Reset Circuit 3 3 Operation Table 3 1 lists the operations when the voltage transitions as shown in Figure 3 2 5 0 V Vdet2_0 Vdet1_6 Vdet0_2 Figure 3 2 Voltage Transition Table 3 1 Operations for 1 to 10 in Figure 3 2 Operation Condition Power on reset When VCC 1 is equal to or above Vdet0 Start incrementing the count port VCC1 is equal to or above Vdet2 for 100 Transmit the mes
10. assage not detected Set the CM14 bit in the CM1 register to 0 125 _ kHz on chip oscillator on Wait for digital filter sampling clock x 3 cycles no wait time RO1AN0679EJ0100 Rev 1 00 Set the VW2CO0 bit in the VW2C register to 1 voltage monitor 2 interrupt reset enabled Set the VW2C7 bit to 1 for the voltage monitor 2 reset when VCC1 reaches or goes below Vdet2 When the VW2C0 bit is 0 steps 4 5 and 6 can be executed simultaneously with one instruction If the above settings are performed while the voltage monitor 2 interrupt reset is disabled VW2C0 bit in the VW2C register is 0 VC27 bit in the VCR2 register is 0 and VCC1 lt Vdet2 or VCC1 gt Vdet2 is detected before enabling the voltage monitor 2 interrupt reset step 10 an interrupt is not generated When VCC1 lt Vdet2 or VCC1 gt Vdet2 is detected while executing steps 8 to 10 the VW2C2 bit becomes 1 When using the detection results from steps 8 to 10 read the VW2C2 bit after step 10 If the bit is 1 execute the process to be performed after detecting VCC1 lt Vdet2 or VCC1 gt Vdet2 When ignoring the detection results from steps 8 to 10 set the VW2C2 bit to 0 after step 10 2tENESAS Sep 30 2011 Page 8 of 16 M16C 65C Group Using the Voltage Detector 5 Setting Method The setting procedures and values in this chapter are used to achieve the example described in 3 Application Example Refer to the U
11. ck counter Message transmission Please set 5 0V Reset the 10 ms counter To normal operation Figure 3 3 Determining When VCC1 2 Vdet2 RO1AN0679EJ0100 Rev 1 00 2tENESAS Page 4 of 16 Sep 30 2011 M16C 65C Group Using the Voltage Detector 3 5 Determining the Voltage Monitor Interrupt Source Read the voltage change detection flag in the interrupt handler to determine whether the source is the voltage monitor 1 interrupt or voltage monitor 2 interrupt Chattering check is not performed here Figure 3 4 shows a flowchart for determining the voltage monitor interrupt source Write enabled Yes VW2C2 is 1 Passed downward No VC13 is 1 through Vdet2 Yes VC13 is 0 Disable voltage monitor 2 interrupt VW2C0 lt 0 Change the generation condition of voltage monitor 2 interrupt VW2C7 0 Clear the voltage change detection flag VW2C2 0 Disable voltage monitor 2 interrupt VW2C0 lt 0 Change the generation condition of voltage monitor 2 interrupt VW2C7 lt 1 Clear the voltage change detection flag VW2C2 0 Enable voltage monitor 2 interrupt VW2C0 lt 1 Message transmission Under Vdet2 Enable voltage monitor 2 interrupt VW2C0 lt 1 Message transmission Over Vdet2 2i c Fa magva VW1C2 is 0 Yes VW1C2 is 1 Passed downward No VW1C3 is 1 through Vdet1 Yes VW1C3 is 0 Disable voltage monitor 1 interrupt vwico lt 0 Cha
12. e VW1C register to 1 digital filter disabled Set the VW1C6 bit in the VW1C register to 0 voltage monitor 1 interrupt Set the VW1CE6 bit in the VW1C register to 1 voltage monitor 1 reset Set the VW1CE6 bit in the VW1C register to 0 voltage monitor 1 interrupt Set the VW1CE6 bit in the VW1C register to 1 voltage monitor 1 reset Set the VW1C2 bit in the VW1C register to 0 Vdet1 passage not detected Set the CM14 bit in the CM1 register to 0 125 _ kHz on chip oscillator on Wait for digital filter sampling clock x 3 cycles no wait time Set the VW1CO bit in the VW1C register to 1 voltage monitor 1 interrupt reset enabled 1 Set the VW1C7 bit to 1 for the voltage monitor 1 reset when VCC1 reaches or goes below Vdet1 RO1AN0679EJ0100 Rev 1 00 When the VW1CO bit is 0 steps 5 6 and 7 can be executed simultaneously with one instruction If the above setting is performed while the voltage monitor 1 interrupt reset is disabled VW1CO bit in the VW1C register is 0 VC26 bit in the VCR2 register is 0 and VCC1 lt Vdet1 or VCC1 gt Vdet1 is detected before enabling the voltage monitor 1 interrupt reset step 11 an interrupt does not occur When VCC1 lt Vdet1 or VCC1 gt Vdet1 is detected while executing steps 9 to 11 the VW1C2 bit becomes 1 When using the detection results from steps 9 to 11 read the VW1C2 bit after step 11 If the bit is 1 execute
13. es here to set the CM14 bit in the CM1 register to 0 125 kHz on chip by b oscillator on and wait for 3 cycles of Voltage monitor 1 control register the sampling clock for the digital filter 1 VWIC VW1C0 Voltage monitor 1 interrupt reset enable bit 1 Enabled b7 b0 PTT fol TT Protect register PRCR PRC3 Protect bit 3 Enable writing to registers VCR2 VWCE VD1LS VWOC VW1C and VW2C 0 Write protected Figure 5 4 Setting Registers Associated with Voltage Monitor 1 2 2 RO1AN0679EJ0100 Rev 1 00 2tENESAS Page 12 of 16 Sep 30 2011 M16C 65C Group Using the Voltage Detector Setting voltage detector 2 Protect register PRCR PRC3 Protect bit 3 Enable writing to registers VCR2 VWCE VD1LS VWOC VW1C and VW2C 1 Write enabled ofofolo o 0 J Voltage monitor function select register VWCE TITIA I I tot VW12E Voltage monitors 1 and 2 enable bit ee ee ee 1 Voltage monitors 1 and 2 enabled IL Li L Reserved bits Set to 0 bo Volt detect ti bl ist The detector operates when td E A DEENEN O tage QeIecItor operation enagie register elapses after the VC27 bit is set to 1 VCR2 Wait for td E A VC27 Voltage detector 2 enable bit 1 Voltage detector 2 enabled When using the digital filter select the sampling clock for the digital filter PLE LTE VWS monitor 2 control register VW2C7 Voltage monitor 2 interrupt reset generation co
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16. et enable bit 1 Enabled 2 Transmit the message Over Vdet1 to the PC 4 Enable write protection b7 b0 PEREDE Protect register PRCR PRC3 Protect bit 3 Enable writing to registers VCR2 VWCE VD1LS VWOC VW1C and VW2C 0 Write protected Figure 5 7 Interrupt Handling and Register Setting 2 2 RO1AN0679EJ0100 Rev 1 00 2tENESAS Page 15 of 16 Sep 30 2011 M16C 65C Group Using the Voltage Detector 6 Sample Code Sample code can be downloaded from the Renesas Electronics website 7 Reference Documents M16C 65C Group User s Manual Hardware Rev 1 00 The latest version can be downloaded from the Renesas Electronics website Technical Update Technical News The latest information can be downloaded from the Renesas Electronics website C Compiler Manual M16C Series R8C Family C Compiler Package V 5 45 C Compiler User s Manual Rev 2 00 The latest version can be downloaded from the Renesas Electronics website Website and Support Renesas Electronics website http Awww renesas com Inquiries http Awww renesas com inquiry RO1AN0679EJ0100 Rev 1 00 2tENESAS Page 16 of 16 Sep 30 2011 M16C 65C Group Using the Voltage Detector Revision History Description Page Summary Seon o eons OOOO Rev Date All trademarks and registered trademarks are the property of their respective owners A 1 General Precautions in the Handling of MPU MCU Products The following usage note
17. ing the Voltage Detector 3 Application Example 3 1 Overview In this sample code the voltage of VCC1 is checked every 10 ms after the power on reset When VCC1 is equal to or above Vdet2 ten times consecutively i e VCC1 2 Vdet2 for 100 ms the program determines that the VCC1 voltage is stable at or above Vdet2 When VCC 1 is equal to or above Vdet2 after the power on reset 1 Configure the voltage monitor interrupt 2 Transmit the message Start to the personal computer hereinafter referred to as PC and perform normal operation When VCC 1 is equal to or below Vdet2 after the power on reset 1 Invert the alarm port every 1 second 1 2 Transmit the message Please set 5 0V to the PC When a rise or a fall is detected in the VCC1 voltage an interrupt occurs Read the VW2C2 bit in the VW2C register and the VW1C2 bit in the VW1C register in the interrupt handler then determine whether the source is the voltage monitor 2 interrupt or voltage monitor 1 interrupt The digital filter is not used here 1 Normal operation when voltage is stable Every 0 5 seconds the count port value is incremented and then output 1 2 Operation when the voltage monitor 2 interrupt occurs When VCC1 is equal to or below Vdet2 and the voltage monitor 2 interrupt occurs e Transmit the message Under Vdet2 to the PC e Change the condition for the voltage monitor 2 interrupt to VCC1 2 Vdet2 When VCC1 is equ
18. ion b7 TTT TAT Protect register PRCA PRC3 Protect bit 3 Enable writing to registers VCR2 VWCE VD1LS VWOC VW1C and VW2C 1 Write enabled 2 Vdet2 passage When passed downward through Vdet2 1 Change the conditions to generate the voltage monitor 2 interrupt b7 bo Voltage monitor 2 control register AIII wee VW2C0 Voltage monitor 2 interrupt reset enable bit 0 Disabled Voltage monitor 2 control register VW2C VW2C7 Voltage monitor 2 interrupt reset generation condition select bit 0 When VCC1 reaches or goes above Vdet2 b7 bo FET fol WSs monitor 2 control register VW2C2 Voltage change detection flag 0 Not detected Voltage monitor 2 control register VW2C L yweco Voltage monitor 2 interrupt reset enable bit Enabled 2 Transmit the message Under Vdet2 to the PC When passed upward through Vdet2 1 Change the conditions to generate the voltage monitor 2 interrupt Voltage monitor 2 control register b7 bo LTT TTT fo wee VW2C0 Voltage monitor 2 interrupt reset enable bit 0 Disabled Voltage monitor 2 control register VW2C VW2C7 Voltage monitor 2 interrupt reset generation condition select bit 1 When VCC1 reaches or goes below Vdet2 Voltage monitor 2 control register VW2C VW2C2 Voltage change detection flag 0 Not detected b7 TTT was monitor 2 control register L yweco Voltage monitor 2 interrupt reset enable bit 1 Enabled 2 Transmit
19. l implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life 8 You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges 9 Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products
20. ndition select bit 0 When VCC1 reaches or goes above Vdet2 1 When VCC1 reaches or goes below Vdet2 bO PL tT dy daly was monitor 2 control register VW2C1 Voltage monitor 2 digital filter disable mode select bit 0 Digital filter enabled 1 Digital filter disabled When using the digital filter set this bit to 0 digital filter enabled Voltage monitor 2 control register VW2C VW2C6 Voltage monitor 2 mode select bit 0 Voltage monitor 2 interrupt at Vdet2 passage 1 Voltage monitor 2 reset at Vdet2 passage bi ERRI fol wee monitor 2 control register VW2C2 Voltage change detection flag 0 Not detected When using the digital filter add processes here to set the CM14 bit in the CM1 register to 0 125 kHz on chip oscillator on and wait for 3 cycles of b7 bo the sampling clock for the digital filter tae elle wee monitor 2 control register VW2C0 Voltage monitor 2 interrupt reset enable bit 1 Enabled b7 bo Py fol 7 Protect register PRCR PRC3 Protect bit 3 Enable writing to registers VCR2 VWCE VD1LS VWOC VW1C and VW2C 0 Write protected Figure 5 5 Setting Registers Associated with Voltage Monitor 2 RO1AN0679EJ0100 Rev 1 00 2tENESAS Page 13 of 16 Sep 30 2011 M16C 65C Group Using the Voltage Detector 5 3 Interrupt Handling and Register Setting Figure 5 6 and Figure 5 7 show interrupt handling and register setting 1 Disable write protect
21. nge the generation condition of voltage monitor 1 interrupt vwic7 lt 0 Clear the voltage change detection flag vwic2 lt 0 Enable voltage monitor 1 interrupt Vwico lt 1 i Message transmission i Under Vdet1 Write protected Determining the Voltage Monitor Interrupt Source Figure 3 4 Disable voltage monitor 1 interrupt VW1C0 0 Change the generation condition of voltage monitor 1 interrupt VW1C7 amp 1 Clear the voltage change detection flag vwic2 0 Enable voltage monitor 1 interrupt VW1C0 lt 1 Over Vdet1 RO1AN0679EJ0100 Rev 1 00 Sep 30 2011 2tENESAS Page 5 of 16 M16C 65C Group Using the Voltage Detector 4 Setting Procedures 4 1 Setting Optional Function Select Address 1 OFS1 Enabling and disabling the voltage monitor 0 reset after hardware reset can be selected by setting the LVDAS bit in the OFS1 address In this sample code the voltage monitor 0 reset is enabled after hardware reset The OFS1 address is assigned to address FFFFFh in the M16C 65C Group Refer to User s Manual Hardware for the OFS1 address setting values Table 4 1 shows script examples for enabling the voltage monitor 0 reset after hardware reset in the M16C 65C Group Table 4 1 Script Examples for the OFS1 Address Tool Description Script in C language _asm ofsreg O9Fh Script in assembly language ofsreg O9Fh 4 2 Procedure for Setting Voltage Monitor Related Bits T
22. plement a system evaluation test for each of the products Notice 1 All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website 2 Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for
23. s are applicable to all MPU MCU products from Renesas For detailed usage notes on the products covered by this manual refer to the relevant sections of the manual If the descriptions under General Precautions in the Handling of MPU MCU Products and in the body of the manual differ from each other the description in the body of the manual takes precedence 1 Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual The input pins of CMOS products are generally in the high impedance state In operation with an unused pin in the open circuit state extra electromagnetic noise is induced in the vicinity of LSI an associated shoot through current flows internally and malfunctions occur due to the false recognition of the pin state as an input signal become possible Unused pins should be handled as described under Handling of Unused Pins in the manual Processing at Power on The state of the product is undefined at the moment when power is supplied The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied In a finished product where the reset signal is applied to the external reset pin the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed In a similar way the states of pins in a product that is reset by
24. sage Start to the PC ms Transmit the message Under Vdet2 to the PC Change the VW2C7 bit to 0 when VCC1 is equal to VCC1 passed downward through Vdet2 or above Vdet2 Transmit the message Under Vdet1 to the PC Change the VW1C7 bit to 0 when VCC1 is equal to VCC1 passed downward through Vdet1 or above Vdet1 Transmit the message Over Vdet1 to the PC Change the VW1C7 bit to 1 when VCC1 is equal to VCC1 passed upward through Vdet1 or below Vdet1 Transmit the message Over Vdet2 to the PC Change the VW2C7 bit to 1 when VCC1 is equal to VCC1 passed upward through Vdet2 or below Vdet2 Voltage monitor 0 reset VCC1 is below Vdeto Invert the alarm port in 1 second intervals and transmit the message Please set 5 0V to the PC VCC1 is equal to or above Vdet0 and below Vdet2 Start incrementing a count port Transmit the message Start to the PC RO1AN0679EJ0100 Rev 1 00 Sep 30 2011 2tENESAS VCC1 is equal to or above Vdet2 for 100 ms Page 3 of 16 M16C 65C Group Using the Voltage Detector 3 4 Determining When VCC1 2 Vdet2 Figure 3 3 shows how to read the VC13 bit in the VCR1 register to determine whether VCC1 is equal to or above Vdet2 Reset the 10 ms counter Reset the VC13 check counter VCC1 Vdet2 is confirmed 10 times consecutively VC13 check counter gt 10 10 ms counter 1 Reset the VC13 che
25. ser s Manual Hardware for details on registers 5 1 Setting Optional Function Select Address 1 OFS1 Figure 5 1 shows Setting Optional Function Select Address 1 OFS1 Optional function select address 1 OFS1 b7 bo EER BEE L WDTON ROMCP1 VDSEL1 OFS1 address is on the flash memory address FFFFFh Write to this address when writing a program to the flash memory When erasing the block which includes the OFS1 address the value of the OFS1 address becomes FFh Watchdog timer start select bit 0 Watchdog timer starts automatically after reset 1 Watchdog timer is stopped after reset Reserved bit Set to 1 ROM code protect cancel bit 0 ROM code protection cancelled 1 ROMCP1 bit enabled ROM code protect bit 0 ROM code protection enabled 1 ROM code protection disabled Reserved bit Set to 1 Vdet0O select bit 1 0 VdetO_2 1 Vdet0_0 Voltage detector 0 start bit 0 Voltage monitor 0 reset enabled after hardware reset 1 Voltage monitor 0 reset disabled after hardware reset After reset count source protection mode select bit 0 Count source protection mode enabled after reset 1 Count source protection mode disabled after reset Figure 5 1 Setting Optional Function Select Address 1 OFS1 RO1AN0679EJ0100 Rev 1 00 Sep 30 2011 7tENESAS Page 9 of 16 M16C 65C Group Using the Voltage Detector 5 2 Setting Registers Associated with Voltage Detectors Figure
26. the process to be performed after detecting VCC1 lt Vdet1 or VCC1 gt Vdet1 When ignoring the detection results from steps 9 to 11 set the VW1C2 bit to 0 after step 11 2tENESAS Sep 30 2011 Page 7 of 16 M16C 65C Group Using the Voltage Detector Table 4 4 Procedure for Setting Voltage Monitor 2 Interrupt Reset Related Bits When Using the Digital Filter When Not Using the Digital Filter Voltage monitor 2 interrupt Voltage monitor 2 reset Voltage monitor 2 interrupt Voltage monitor 2 reset Set the VW12E bit in the VWCE register to 1 voltage monitors 1 and 2 enabled Set the VC27 bit in the VCR2 register to 1 voltage detector 2 enabled Wait for td E A Set bits VW2F0 to VW2F1 in the VW2C register to select the digital filter sampling clock Set the VW2C7 bit in the VW2C register to select the timing of the interrupt and reset request 1 Set the VW2C1 bit in the VW2C register to 0 digital filter enabled Set the VW2C1 bit in the VW2C register to 1 digital filter disabled Set the VW2C6 bit in the VW2C register to 0 voltage monitor 2 interrupt Set the VW2CE6 bit in the VW2C register to 1 voltage monitor 2 reset Set the VW2CE6 bit in the VW2C register to 0 voltage monitor 2 interrupt Set the VW2CE6 bit in the VW2C register to 1 voltage monitor 2 reset Set the VW2C2 bit in the VW2C register to 0 Vdet2 p
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