GBT-SCA Updates and chip results - Indico
Contents
1. GBT SCA The Slow Control Adapter for the GBT system Alessandro Caratelli Kostas Kloukinas Cristian Paillard Sandro Bonacini Alessandro Marchioro Rui De Oliveira Paulo Moreira CERN PH ESE ME alessandro caratelli cern ch Outline e What the GBT SCA is Interfaces and communication Prototypes testing status and results Practical information The GBT Chipset GBTX 4 8 Gb s Transceiver Manages the communications between the counting room and the frontend modules GBT SCA Slow Control Adapter Experiment control and environment monitoring GBTIA 4 8 Gb s Transimpedance Amplifier Amplifies the weak photo current detected by the PIN diode GBLD 4 8 Gb s Laser Driver Modulates laser current to achieve electro optical conversion GBTX GBT SCA GBLD The SCA In the GBT system FE ASICs Data j d Timing E NM E E port Slow o Control T owe NE E sl E port User busses and I O for Control and monitoring Timing and Trigger P x jV 3 3 T Nu E port gt Aam nt Embedded electronics in the Control room detector Com mun ication Successfully tested SCAASIC can connect via an e link to any e port of the GBTX 40MHz double date rate 80 Mbps Point to point network topology with fixed bandwidth allocated by the GBTX Double redundancy scheme allowing connection f2. A drive strength TENET TMSFIFO i EN E E CHARL O Ho 5 eae GO BUSY iH MN Y x SPI serial bus master Interface sasas ia Full duplex synchronous serial bus with configurable bus transactions up to 128 bit long Longer transactions are possible by segmenting on consecutive channel commands e Supports all the standard SPI bus operating modes 00 01 10 and 11 8 Individual slave select lines e Bus frequency spans from 156KHz up to 20MHz in 128 user programmable steps Use standard IBM 130 digital lOs library pads with 12mA drive strength d TDO TDI HFO Ht CHARLEN IL GO BUSY RX EDGE TX EDGE TR DIR SERTE 0 Parallel Interface Adapter sios bugas 32 General Purpose digital IO lines Each line can be individually programmed as input or outpu Input signals are sampled and registered at the raising or falling edges of the system clock or of an external strobe signal from the user s application connected on a dedicated input line Any line configured as input can generate an interrupt request to the control room electronics Use standard IBM 130 digital lOs library pads with 4mA drive strength Output reg gt N Z enm Edge detect Int flags Clk select Int clock m Uv O pe Oo c aD c O Q C 2 ADC PRELIMINARY Test results 31 input analog multiplexer connected to a 12 bit analog to digital convert
3. Pitch BGA Chip Scale Package Ball Pitch 0 8 mm 9499 9 Size 12x 12mm 4444444444 99 999 GND D DVDD gt 4 DVDD i a rai D ral D VDD ai D e Height 1 7 mm Pin count 196 44444 N N im mm N N N 444 99 G Ww 2 ad MM yu Others information e 18 Prototype submitted for fabrication in July 2014 Part of the GBT chipset MPW run e Received 2 wafers 520 dies in middle of November 250 bare die chips 208 BGA packaged chips possibility to package 260 additional dies Distribute sample parts to system developers User manual Available on GBT sharepoint site httos espace cern ch GBT Project GBT SCA Manuals Forms Allltems aspx Latest version GBT SCA Manual Rev 0 GBT SCA The Slow Control Adapter ASIC for the GBT System A Caratelli S Bonacini K Kloukinas 4 Marchioro P Moreira C Paillard GBT SCA The Slow Control Adapter for the GBT system For additional information do not hesitate to contact me at alessandro caratelli cern ch
4. are Test Boards e GBT SCA communication handle e Interface board e Txand Rx FIFOs e Level translators ADCs DACs e Test routines python e HDLC encoding Voltage regulators Current monitors l e Interface python and C e SCA access classes e PCB control classes e Slave interfaces classes e Slave interfaces e etc e PCB components control toad boards BGA Socket CPGA ZIF socket AXILINX Deve lopemert card Radiation Performances Radiation tests will take place on the 20 April To address the TID requirements The SCA is implemented in a commercial 130 nm CMOS technology largely characterized for radiation tolerance To address the SEUS requirements The SCA adopt the Triple Modular Redundancy technique at the state machine level in the entire digital circuitry The clock tree was also triplicated to mitigate the effects of SET The SCA SEUS robustness has been strongly verified at simulation level e SEUS tests will take place on the April 20 in Louvain la Neuve Electrical characteristics e Analog supply voltage 1 5 V Standard Supplies by design Digital supply voltage 1 5V e Periphery supply voltage 1 5 V The GBT SCA digital functions have been successfully tested at 1 2V supply e ADC instead needs 1 5 V supply to correctly work P a ckag ng Successfully tested pa N 3 4 5 7 8 9 0 Package Low Profile Fine
5. bits 32 bits The Frame Check Sequence FCS field is calculated over the address control and Information fields using a CCITT standard 16 bit CRC Communication protocol scheme 8 bits 8 bits 8 bits 16 x N bits 16 bits 8 bits ARANA A 8 bits 8 bits 8 bits 8 bits O bits 16 bits 32 bits Command oriented protocol to address the on chip interface channels Bits within the field are transmitted from the least to the most significant bit ID Transaction identifier to associate request packets to the corresponding replies ID 0x00 and Oxff are reserved for spontaneously generated interrupt packets e CH Define the destination channel interface in the SCA e CMD indicates the operation to be performed ERR Indicate eventual error conditions encountered in the execution DATA Is a command dependent field whose length is defined by the LEN qualifier field The GBI SCA architecture SOS CLK SDA x16 XXI RX SCL x16 PO TX SLVS Cm 0 2V Dif 0 2V SCLK MISO MOS SPI master z SS x8 z a S gt DOG CLK TDO JTAG master gt Q TMS BE 9 gt RX RES c D lt TX SLVS E Cm 0 2V GPIO Dif 0 2V x32 Analog IN x31 SDA SCL 928JJ91U 32 19019 M Calibration A SEU counter Analog OUT x4 928JJ91U C master Successfully tested 16 independent I C master serial bus channels individually programmable Data transfer rates from 100KHz to 1MHz Implement bit
6. er One analog input internally connected to the embedded temperature sensor All inputs feature a switchable 100uA current source to facilitate the use of externally connected resistance temperature sensors RTD Time of conversion 760uS compatible with the conversion requirements of slow varying parameters like detector leakage current and temperature power supply voltages etc Analog input range 0 0 V to 1 0 V Implements internal Gain correction and Offset cancellation The gain calibration coefficient is evaluated during the testing phase for every chip and stored on the on chip e fuse bank The stored coefficient can be overridden to compensate for any possible drifts caused by the radiation environment DNL LSB INL LSB 512 512 1024 1024 1336 1536 2048 Code 2048 Code 2560 2560 PRELIMINARY Test results 3072 3584 4096 3072 3584 4096 Prototype test bench For precise ADC and DAC characterization For the final production testing Va Ji 1 Stand alone test bench For functional verification on bare die Irradiation performance testing on bare die and packaged parts af illi nga h s praece poo grt aXe Ef unici s TE 1 5 x DE T EE 255 I hos El SEAS rere ava bess ee p E ERE A oF Ga ear 2 A es AS ER AR ET 120 SA TAU ld ao r sa EA Ye xa Stand alone test bench Software Firmw
7. rom two GBTX links e Switching between masters requires a CONNECT command defined in the high level communication protocol Communication protocol scheme 8 bits 8 bits 8 bits 16 x N bits 16 bits 8 bits ARANA A 8 bits 8 bits 8 bits 8 bits O bits 16 bits 32 bits The e link ports implement a packet oriented full duplex transmission based on the HDLC standard ISO IEC 13239 2002 Not deterministic Bits within the frame are transmitted from the least significant to the most significant The frame delimiter is composed of six 1s The protocol assures that this combination is not found anywhere by stuffing a 0 in any sequence of five consecutive 1 Communication protocol scheme 8 bits 8 bits 8 bits 16 x N bits 16 bits 8 bits ARANA A 8 bits 8 bits 8 bits 8 bits O bits 16 bits 32 bits The CONTROL field contains the frame sequence number of the currently transmitted frame and of the last correctly received frame to implement an acknowledgement handshake between the SCA and the control room electronics The CONTROL field is also used to convey three supervisory level commands e CONNECT To select the active interface between primary and auxiliary e port RESET To remotely reset the SCA chip TEST Loopback mode for communication verification Communication protocol scheme 8 bits 8 bits 8 bits 16 x N bits 16 bits 8 bits AAA YAA __ 8 bits 8 bits 8 bits 8 bits O bits 16
8. s and 10 bits addressing standard Read Write and Read Modify Write operations Single byte and multi byte modes up to 16 Reply packet return user data and status flags D pO 6 T ap 2 c Uv c O O C 2 I2C Kh protocol Ba SDA state machine 23 Command buffer e E Config registers gt SCL e SCL lines use digital lOs pads with 4mA drive strength configured as output SDA lines use digital lOs pads with 4mA drive strength configured as bidirectional forcing only the 0 value on the bus open drain emulated Necessity of an external pull up for the SDA lines Example of I C operation Supposing that you want to execute I2C single byte write operation using the I2C master number 4 in 7bit addressing mode The sent packet will be HDLC frame MA CS 2 I2C WRITE I2Caddress DATA BYTE And you will receive at the end of the operation Te Status ACK JTAG master nte race Successfully tested Configurable bus transactions length up to 128 bit Longer transactions are possible by segmenting on consecutive channel commands Asynchronous reset line of configurable pulse width Bus frequency spans from 156KHz up to 20MHz in 128 user programmable steps JTAG Tap controller state machine need to be implemented in the FPGA circuitry in the control room electronics Use standard IBM 130 digital lOs library pads with 12m
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