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Using as - No Frontend of Virtual Engine!

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1. 22 k command line option ARM 97 KPIC eg EE 172 KPIC option MIPS 21 22 90 0 9 REIP 192 EEN 22 I option MOSZ rrr e Ite Ren 176 lt little option MISE ees dee yrs 172 cH 23 m no 68851 command line option M680x0 m EET 176 m no 68881 command line option M680x0 EET 176 m no div command line option M680x0 176 m no emac command line option M680x0 176 m no float command line option M680x0 AS Index m no mac command line option M680x0 176 m no usp command line option M680x0 176 pubbl 220 sib 045 Lio icto lice E URS LEUR 220 Sm OD PE PEE EET 221 aula PETIT 221 nb acu uc Se eni baa e heeded 221 mL EE 221 DUNEDIN owns hace en oe E AEN A ales 221 HMR Leni te EETA 221 SREL gene dE eed NOR RE olan 221 EH 34 oisoleseib bee ME iia EH ER EEN 221 inl l S4u usse bercerseverr e repete DRE Pu e et 221 fl E sitis be perl a IDA Rr RE Re ca eens 221 inll 40 e elk y bre te Re cats 221 zdnll AA ili pieciilPle s ile e Re IPIE REY takes 221 STATA PC 221 SMT SO E 221 ouibus CH 221 subo 221 CH DR 221 em Oe PE DEREN 221 CH Die cce rrr 221 SMM 83 LEER 221 STM BAG ee EES 221 HBK EG 221 M11 94s cei eiiisidds ERREUR evedaitdidads 221 mi6c option MIGG ws essere ee 170 em31 option 5390 Ee A dee SEN RS 231 m32 option TILE GZ cernere SCT ma2bit doubles SE dees Set xui d 228 n326 option EE B
2. 85 line comment character ARC 91 line comment character ARM 98 line comment character AN 109 line comment character CR16 119 line comment character DIOV 126 line comment character D30V 129 line comment character Epiphany 133 line comment character H8 300 134 line comment character i386 0 148 line comment character i860 Lus 158 line comment character 2000 162 line comment character I A 64 164 line comment character IP2K 166 line comment character LM32 169 line comment character M32C 171 line comment character M680x0 183 line comment character M68HC11 185 line comment character Meta 190 line comment character MicroBlaze 191 line comment character MIPS 202 line comment character MSP 430 211 line comment character Nios II 215 line comment character NS32K 218 line comment character PI 223 line comment character PowerPC 226 line comment character RL78 227 line comment character HS 230 line comment character s 00 231 line comment character SCORE 247 line comment character SH 248 line comment character SH64 251 line
3. 4 4 4 4 4 0 16 20 24 28 31 RRS format lt insn gt R1 R2 M3 D4 B4 4 4 4 4 4 4 4 4 OpCode R1 R3 B4 D4 M3 OpCode 4 4 4 4 4 4 4 4 0 8 12 16 20 32 36 40 47 RS format lt insn gt R1 R3 D2 B2 4 4 4 4 4 OpCode R1 R3 B2 D2 Using as Chapter 9 Machine Dependent Features 4 4 4 4 4 0 8 12 16 20 31 RSE format lt insn gt R1 R3 D2 B2 4 4 4 4 4 4 4 OpCode R1 R3 B2 D2 I OpCode 4 4 4 4 4 4 4 0 8 12 16 20 32 40 47 RSI format lt insn gt R1 R3 12 4 4 4 4 OpCode R1 R3 I2 4 4 4 4 0 8 12 16 47 RSY format lt insn gt R1 R3 D2 B2 4 4 4 4 4 4 4 OpCode R1 R3 B2 DL2 DH2 OpCode 4 4 4 4 4 4 4 0 8 12 16 20 32 40 47 RX format lt insn gt R1 D2 X2 B2 4 4 4 4 4 OpCode R1 X2 B2 D2 4 4 4 4 4 0 8 12 16 20 31 RXE format lt insn gt R1 D2 X2 B2 4 4 4 4 4 4 4 OpCode R1 X2 B
4. 47 pseudo ops MMIX cece eee eee 207 psize directive iiie e erre ee ER PETS 67 PSR D1tS M 164 pstring directive TIC54X 0 270 psw register VR ccacinisiediicsveisead vier 299 purgem directive siete e be ere perdet 68 purpose of GNU assembler 17 pushsection directive 0 08 68 Q quad directive ic ces sex m erRERUREUPERTEX ERR 68 quad directive i386 00 eee 152 quad directive xX86 64 ssusrrcrerrrrrrrres 152 R real mode code 13886 eee e eee eee ee 153 ref directive TICBAX aa SEENEN EE 269 register directive DARC 263 register names A rch 82 register names Alpha 85 register names ARC 91 register names ARM 98 register names AND 110 register names CRIS niss 123 register names H8 300 005 134 register names LA 24 0c eee 164 register names LM a 167 Using as register names MMIX 206 register names MSP 430 212 register names Hparc 2 eee eee eee 256 register names TILE Gx 277 register names TILEPro 282 register names VS 297 register names MAN 295 register names iensg 308 register names Eder 287 register naming S300 ese es are wees 232 register operands i386 eee eee eee 147 register operands x86 64 00000 147 registers DIOV oce er tare est aoe
5. cesses 44 expressions etmnpta eee eee eens 43 expressions integer 2 ee eee eee eee 43 extAuxRegister directive ARC 92 extCondCode directive AR 92 extCoreRegister directive ARC 92 extend directive M 181 extend directive M68HC11 188 extend directive SCGATE nne 304 extended directive 2000 160 extern dmrectlyec sb eniE ses wb DUE 55 extInstruction directive ARC 92 AS Index F fall directives xs beeer RERO EPERESA Y 55 far mode directive TIC54X 268 faster processing UE 22 fatal signal Loris ean PURI I PRUDENS 315 felist directive TIC54X 268 fcnolist directive TIC5AX 268 fepe register VSbD pecrrdcredrerr s apinn 298 fepsw register VS 299 ffloat directive VAN 292 field directive TICRX 268 IiledduecllVe see pe d Pre REY YER 55 file directive MSP 430 213 file name logical rr RI iniret ssi 55 files including pet wee ede ttn Ree ees 58 Ales input is 424 eho eee de eva ed iz fill duectlvece z3 4e RERBA EP PIE 55 filling memory er ease adie ERES 12 13 ELIX EE 307 float directive fing e eR C Ce ben T ERE dene 56 float directive i886 cee eee eee 152 float directive Mot 181 float directive M68HC11 188 float directive RX ee NENNEN ceed 230 float directive TICRX 268 float dire
6. eee eee 101 SOL ee dieses seni ete he 200 handlerdata directive ARM 101 handlerdata directive TIC6X 275 DIM LETT 200 insn directive 8390 0 eee eee ee eee 244 inst directive ADM 101 1double directive ARM 101 Little directive M32RX suuus 174 slong directive EEN 244 ltorg directive A Arch 83 ltorg directive ARM 101 Ltorg directive 8390 sue ae nes 245 m32r directive M32R uuuussuuus 174 m32r2 directive M32R2 174 n32rx directive M32RX sssnsstssreicsissrsr 174 machine directive s 00 245 machinemode directive s 00 245 movsp directive ARM 101 nan directive MIPS usussuusus 201 no pointers directive XStormy16 305 nocmp directive loi 275 P 18 object arch directive ARM 101 packed directive ARM 102 pad directive ARM 99 102 param on D EN uber E RR Ry ERE ees 138 personality directive ARM 102 personality directive TIC6X 275 personalityindex directive ARM 102 personalityindex directive TIC6X 275 poo1 directive AArch 83 poo1 directive ADM 102 quad directive 8390 sis nionerns 244 red directive AArch i i ccscuscnrrisisisrccas 83 red directive ARM 102 require canonical reg names directive TILE EE EE 280 require canonical reg names directive
7. 33 Ad Background EE 33 AD Linker Secliong eoo ie kept E kg EE aan 34 4 3 Assembler Internal Sections 000 c cece eee eee 35 AVA E EE 35 dh DSS Section ices dae ee beer E E REDE OPCIEI RU es dado a 36 D OV MONS cos EE SES EARS RE EEN 39 Dil 3Labels zu ceu Ee Ae redu ter b odore anced ios EA 39 5 2 Giving Symbols Other Values 0 000 39 5 9 Symbol Nameg eege Ee ovd ERR EAR e 39 5 4 The Special Dot Symbol 20 20 cece cence eee eee Al 5 5 Symbol Attributes eer RR EE LOCO eU ERR ENEE tes 41 D b l Vallis ss eee cte rac nete saw nes dU ban e UR E 41 SOPORE 41 5 5 3 Symbol Attributes a out 42 5 5 9 1 Hegertpbog e dere EE EE e cages 42 bh Other ks cuis epe te beat bb decine AR ege 42 5 5 4 Symbol Attributes for OO 42 5 5 4 1 Primary Attributes srroidssssrseiasyacsc aorin ieres 42 5 5 4 2 Auxiliary Attnbutes eiee ni nri 42 5 5 5 Symbol Attributes for DON 42 6 Expressions icons cs Dust X eat eg Visi b e e e n 43 6 1 Empty Fepnresstong eese nee 43 6 2 Integer EXpr Ssions 0 see y me x e KEREN 43 6 2 1 Arguments s e 43 6 2 2 Operators dese NEE e ELe Y DOR ERES RR PURA E d 43 6 2 3 Prex Operator getrei Se t bere pedea as 43 6 24 Infix Operators ois vd Lus ced meg adiens docta re Pet o e s 44 7 Assembler Directves 47 EN EE 4T T2 ERREECHEN doe EA kt dq deeem ned 47 7 3 align abs expr abs expr abs expr sess 4T GA altm acrO iil2soleisleleD
8. 266 cosh math builtin TIC54X 266 cvf math builtin TIC54X 266 cvi math builtin TIC54X 266 EE 83 105 exp math builtin TIC54X 266 fabs math builtin TIC54X 266 firstch subsym builtin TIC54X 212 floor math builtin TIC54X 266 fmod math builtin TIC54X 266 int math builtin TIC54X 266 iscons subsym builtin TIC5AX 272 isdefed subsym builtin TIC54X 272 ismember subsym builtin TIC5AX 272 isname subsym builtin TIC5AX 273 isreg subsym builtin TIC54X 273 1astch subsym builtin TIC5AX 272 1dexp math builtin TIC54X 266 log math builtin TIC54X nn anunaannnannna 266 10g10 math builtin TIC54X 266 max math builtin TIC54X 266 min math builtin TIC54X 266 pow math builtin TIC54X 0 266 round math builtin TIC54X 266 Zeen math builtin TIC54X 266 sin math builtin TIC54X 266 sinh math builtin TIC54X 267 sqrt math builtin TIC54X 267 structacc subsym builtin TIC54X 273 structsz subsym builtin TIC5AX 273 symcmp subsym builtin TIC5AX 272 symlen subsym builtin
9. usuus 269 endm directive ics lee bori Tun EnEn ra Ei 64 endm directive TIChAX 269 endstruct directive TIC54X 241 endunion directive TIC54X uuuue 271 environment settings TIC54X 264 EOF newline must precede 28 ep register V850 23 seb o e HR d de nds 298 Epiphany line comment character 133 Epiphany line separator sseeeses 133 Epiphany options eere etre Ree 133 Epiphany support eee eR me 133 equ directive s cocnees et yvOPRER A eR EP Y 54 equ directive TIC54X ounererecrrrrerrn 270 equiv directive i ees cbe es re erede 54 egy directive oie een Rat ri E PR n PER phe E 54 err directive c oloso sep p pee EN r rye 54 error directe 54 error messages lll le eb uL RSL e d dps 18 error on valid mput 2 eee 315 errors caused by warnings crrrrrcre 26 errors continuing alter 26 ESA 390 floating point IEEE 143 ESA 390 support 142 ESA 390 Syntax eee eee eee eee 142 ESA 390 only directives 0 02 0005 143 escape codes character 29 eval directive TICBAX lssueessss 267 OVOL esie RR REX beens Peat UR REESE EE 291 even directive Most 181 even directive TICBAX ssssesesesss 267 exitm directives isi eme pee das cece me wets 64 expr internal section 35 expression arguments 0 00 a annemin 43 CXPTOSSIONS EELER 43 expressions comparison
10. LoadLoad defines that all loads appearing prior to the membar instruction must have been performed before any loads following the membar may be performed This corre sponds to membar mmask field bit 0 These values can be ored together for example membar Sync membar StoreLoad LoadLoad membar StoreLoad StoreStore The prefetch and prefetcha instructions take a prefetch function code The following prefetch function code constant mnemonics are available n_reads requests a prefetch for several reads and corresponds to a prefetch function code of 0 tone read requests a prefetch for one read and corresponds to a prefetch function code of 1 n_writes requests a prefetch for several writes and possibly reads and corresponds to a prefetch function code of 2 fone_write requests a prefetch for one write and corresponds to a prefetch function code of 3 Chapter 9 Machine Dependent Features 259 tpage requests a prefetch page and corresponds to a prefetch function code of 4 ftinvalidate requests a prefetch invalidate and corresponds to a prefetch function code of 16 funified requests a prefetch to the nearest unified cache and corresponds to a prefetch function code of 17 n_reads_strong requests a strong prefetch for several reads and corresponds to a prefetch function code of 20 one_read_strong requests a strong prefetch for one read and corre
11. as DEC writes it The indirect character is for Unix compatibility not as DEC writes it Chapter 9 Machine Dependent Features 295 The displacement sizing character is an accent grave for Unix compatibility not as DEC writes it The letter preceding may have either case G is not understood but all other letters b i 1 s w are understood Register names understood are rO r1 r2 r15 ap fp sp pc Upper and lower case letters are equivalent For instance tstb w 4 r5 Any expression is permitted in an operand Operands are comma separated 9 48 7 Not Supported on VAX Vax bit fields can not be assembled with as Someone can add the required code if they really need it 9 48 8 VAX Syntax 9 48 8 1 Special Characters The presence of a 4 appearing anywhere on a line indicates the start of a comment that extends to the end of that line If a appears as the first character of a line then the whole line is treated as a com ment but in this case the line can also be a logical line number directive see Section 3 3 Comments page 27 or a preprocessor control command see Section 3 1 Preprocessing page 27 The character can be used to separate statements on the same line 9 49 v850 Dependent Features 9 49 1 Options as supports the following additional command line options for the V850 processor family wsigned overflow Causes warnings to be
12. has no special meaning you may use it in symbol names Chapter 9 Machine Dependent Features 127 9 9 2 4 Register Names You can use the predefined symbols ro through r15 to refer to the D10V registers You can also use sp as an alias for r15 The accumulators are a0 and a1 There are special register pair names that may optionally be used in opcodes that require even numbered registers Register names are not case sensitive Register Pairs rO ri r2 r3 r4 r5 r6 r7 r8 r9 r10 ri1 r12 r13 r14 r15 The D10V also has predefined symbols for these control registers and status bits psw Processor Status Word bpsw Backup Processor Status Word pc Program Counter bpc Backup Program Counter rpt c Repeat Count rpt_s Repeat Start address rpt_e Repeat End address mod_s Modulo Start address mod_e Modulo End address iba Instruction Break Address 0 Flag 0 i1 Flag 1 c Carry flag 9 9 2 5 Addressing Modes as understands the following addressing modes for the D10V Rn in the following refers to any of the numbered registers but not the control registers Rn Register direct Rn Register indirect Rn Register indirect with post increment 128 Using as Rn Register indirect with post decrement SP Register indirect with pre decrement disp Rn Register indirect with displacement addr PC relative address for branch or rep imm Immediate data the is optional and ig
13. gp and sp respectively The 32 floating point registers are referred to as fn 9 2 3 3 Relocations Some of these relocations are available for ECOFF but mostly only for ELF They are modeled after the relocation format introduced in Digital Unix 4 0 but there are additions The format is tag or tag number where tag is the name of the relocation In some cases number is used to relate specific instructions The relocation is placed at the end of the instruction like so ldah 0 a 29 gprelhigh lda 0 a 0 gprellow ldq 1 b 29 literal 100 1dl 2 0 1 lituse_base 100 literal literal N Used with an 1dq instruction to load the address of a symbol from the GOT A sequence number N is optional and if present is used to pair lituse relo cations with this literal relocation The lituse relocations are used by the linker to optimize the code based on the final location of the symbol Note that these optimizations are dependent on the data flow of the program Therefore if any lituse is paired with a literal relocation then all uses of the register set by the literal instruction must also be marked with lituse relocations This is because the original literal instruction may be deleted or transformed into another instruction Also note that there may be a one to many relationship between literal and lituse but not a many to one That is if there are two code paths that load up the
14. half value value n uhalf value value n short value value n ushort value value n int value value n uint value value n word value value n uword value value n Place one or more values into consecutive words of the current section If a label is used it points to the word allocated for the first value encountered label symbol Define a special symbol to refer to the load time address of the current section program counter length width Set the page length and width of the output listing file Ignored list nolist Control whether the source listing is printed Ignored long value value n ulong value value n xlong value value n Place one or more 32 bit values into consecutive words in the current section The most significant word is stored first Long and ulong align the result on a longword boundary xlong does not loop count break condition endloop Repeatedly assemble a block of code loop begins the block and endloop marks its termination count defaults to 1024 and indicates the number of times the block should be repeated break terminates the loop so that assembly begins after the endloop directive The optional condition will cause the loop to terminate only if it evaluates to zero 270 Using as macro name macro parami param n mexit endm See the section on macros for more explanation See Secti
15. pri_prog or sec_prog param if present provides either relocation information for the procedure ar guments and result or a privilege level param may be argwn where n ranges from 0 to 3 and indicates one of four one word arguments rtnval the pro cedure s result or priv_lev privilege level For arguments or the result r Chapter 9 Machine Dependent Features 139 specifies how to relocate and must be one of no not relocatable gr argu ment is in general register fr in floating point register or fu upper half of float register For priv_lev r is an integer half n Define a two byte integer constant n synonym for the portable as directive Short import name typ Converse of export make a procedure available to call The arguments use the same conventions as the first two arguments for export label name Define name as a label for the current assembly location leave Not yet supported the assembler rejects programs containing this directive origin lc Advance location counter to Ic Synonym for the as portable directive org param name typ param r Similar to export but used for static procedures proc Use preceding the first statement of a procedure procend Use following the last statement of a procedure label reg expr Synonym for equ define label with the absolute expression expr as its value Space secnam
16. The value of an undefined symbol is treated in a special way If it is 0 then the symbol is not defined in this assembler source file and 1d tries to determine its value from other files linked into the same program You make this kind of symbol simply by mentioning a symbol name without defining it A non zero value represents a comm common declaration The value is how much common storage to reserve in bytes addresses The symbol refers to the first address of the allocated storage 5 5 2 Type The type attribute of a symbol contains relocation section information any flag settings indicating that a symbol is external and optionally other information for linkers and debuggers The exact format depends on the object code output format in use 42 Using as 5 5 3 Symbol Attributes a out 5 5 3 1 Descriptor This is an arbitrary 16 bit value You may establish a symbol s descriptor value by using a desc statement see Section 7 35 desc page 53 A descriptor value means nothing to as 5 5 3 2 Other This is an arbitrary 8 bit value It means nothing to as 5 5 4 Symbol Attributes for COFF The COFF format supports a multitude of auxiliary symbol attributes like the primary symbol attributes they are set between def and endef directives 5 5 4 1 Primary Attributes The symbol name is set with def the value and type respectively with val and type 5 5 4 2 Auxiliary Attributes The as directives dim line
17. You may add a passage of up to five words as a Front Cover Text and a passage of up to 25 words as a Back Cover Text to the end of the list of Cover Texts in the Modified Version Only one passage of Front Cover Text and one of Back Cover Text may be added by or through arrangements made by any one entity If the Document already includes a cover text for the same cover previously added by you or by arrangement made by the same entity you are acting on behalf of you may not add another but you may replace the old one on explicit permission from the previous publisher that added the old one The author s and publisher s of the Document do not by this License give permission to use their names for publicity for or to assert or imply endorsement of any Modified Version 5 COMBINING DOCUMENTS You may combine the Document with other documents released under this License under the terms defined in section 4 above for modified versions provided that you include in the combination all of the Invariant Sections of all of the original documents unmodified and list them all as Invariant Sections of your combined work in its license notice and that you preserve all their Warranty Disclaimers The combined work need only contain one copy of this License and multiple identical Invariant Sections may be replaced with a single copy If there are multiple Invariant Sections with the same name but different contents make the title of each such
18. arch directive x86 64 ee eee eee architecture options 29000 335 architecture options P2022 166 architecture options IP2K 166 architecture options M16C 170 architecture options M 170 architecture options M32R 5 172 architecture options M32R2 172 architecture options M32RX 172 architecture options M680x0 177 Architecture variant option CRIS 120 architectures Meta eee eee eee 190 architectures Power 224 architectures SCORE 00 e eee 246 architectures DARC 254 arguments for addttion 44 arguments for subtraction 44 arguments in e Dreams 43 arithmetic functions ven d ere d 43 arithmetic operands 00 eee eee ee 43 ARM datarelocations eee 98 ARM floating point rr 99 ARM identifiers eriten SNE EEN EEN ENEE ENER 98 ARM immediate character 98 ARM line comment character 98 ARM line separator 00 e eee eee eee 98 ARM machine directe 99 ARM opcodes ss ce e EELER 104 ARM options none ssrrrerrsssrrrrrere 95 ARM register names 0 eee eee eee 98 ARM support icc bah Ee E pe pd 95 ascii directive 4 e ole el e prp BEEN EE Ne 48 sciz EE 48 asg directive TIC54X lesse 267 assembler bugs reporting sr errrre 315 assembler crashigi uv dedieucwtes suet Steed nate 315 assem
19. at the start of a line also indicates a comment that extends to the end of that line The TIC54X assembler does not currently support a line separator character 274 Using as 9 43 TIC6X Dependent Features 9 43 1 TIC6X Options march arch Enable only instructions from architecture arch By default all instructions are permitted The following values of arch are accepted c62x c64x c64x c67x c67x c674x mdsbt mno dsbt The mdsbt option causes the assembler to generate the Tag ABI DSBT at tribute with a value of 1 indicating that the code is using DSBT addressing The mno dsbt option the default causes the tag to have a value of 0 in dicating that the code does not use DSBT addressing The linker will emit a warning if objects of different type DSBT and non DSBT are linked together mpid no mpid near mpid far The mpid option causes the assembler to generate the Tag ABI PID attribute with a value indicating the form of data addressing used by the code mpid no the default indicates position dependent data addressing mpid near indicates position independent addressing with GOT accesses using near DP addressing and mpid far indicates position independent addressing with GOT accesses using far DP addressing The linker will emit a warning if objects built with different settings of this option are linked together mpic mno pic The mpic option causes the ass
20. gcc 2 7 e The command arguments you gave the assembler to assemble your example and observe the bug To guarantee you will not omit something important list them all A copy of the Makefile or the output from make is sufficient If we were to try to guess the arguments we would probably guess wrong and then we might not encounter the bug e A complete input file that will reproduce the bug If the bug is observed when the assembler is invoked via a compiler send the assembler source not the high level language source Most compilers will produce the assembler source when run with the S option If you are using gcc use the options v save temps this will save the assembler source in a file with an extension of s and also show you exactly how as is being run e A description of what behavior you observe that you believe is incorrect For example Tt gets a fatal signal Of course if the bug is that as gets a fatal signal then we will certainly notice it But if the bug is incorrect output we might not notice unless it is glaringly wrong You might as well not give us a chance to make a mistake Even if the problem you experience is a fatal signal you should still say so explicitly Suppose something strange is going on such as your copy of as is out of sync or you have encountered a bug in the C library on your system This has happened Your copy might crash and ours would not If you told u
21. isdefed symbol Returns zero if the symbol symbol is not in the symbol table non zero other wise ismember symbol list Assign the first member of comma separated string list to symbol list is re assigned the remainder of the list Returns zero if list is a null string Both arguments must be subsyms Chapter 9 Machine Dependent Features 273 iscons expr Returns 1 if string expr is binary 2 if octal 3 if hexadecimal 4 if a character 5 if decimal and zero if not an integer isname name Returns 1 if name is a valid symbol name zero otherwise isreg reg Returns 1 if reg is a valid predefined register name ARO AR7 only structsz stag Returns the size of the structure or union represented by stag structacc stag Returns the reference point of the structure or union represented by stag Al Ways returns zero 9 42 11 Memory mapped Registers The following symbols are recognized as memory mapped registers 9 42 12 TIC54X Syntax 9 42 12 1 Special Characters d The presence of a appearing anywhere on a line indicates the start of a comment that extends to the end of that line If a appears as the first character of a line then the whole line is treated as a com ment but in this case the line can also be a logical line number directive see Section 3 3 Comments page 27 or a preprocessor control command see Section 3 1 Preprocessing page 27 The presence of an asterisk
22. lower16 and upper16 respectively For example to load the 32 bit address of foo into r0 MOVW rO lower16 foo MOVT rO upper16 foo 9 4 2 5 NEON Alignment Specifiers Some NEON load store instructions allow an optional address alignment qualifier The ARM documentation specifies that this is indicated by align However GAS already interprets the character as a line comment start so align is used instead For example vldi 8 q0 Teo 128 9 4 3 Floating Point The ARM family uses IEEE floating point numbers 9 4 4 ARM Machine Directives 2byte expression expression 4byte expression expression 8byte expression expression These directives write 2 4 or 8 byte values to the output section align expression expression This is the generic align directive For the ARM however if the first argument is zero ie no alignment is needed the assembler will behave as if the argument had been 2 ie pad to the next four byte boundary This is for compatibility with ARM s own assembler arch name Select the target architecture Valid values for name are the same as for the march commandline option Specifying arch clears any previously selected architecture extensions arch extension name Add or remove an architecture extension to the target architecture Valid values for name are the same as those accepted as architectural extensions by the mcpu commandl
23. start address of section 34 Using as e Is the reference to an address Program Counter relative In fact every address as ever uses is expressed as section offset into section Further most expressions as computes have this section relative nature For some object formats such as SOM for the HPPA some expressions are symbol relative instead In this manual we use the notation secname N to mean offset N into section sec name Apart from text data and bss sections you need to know about the absolute section When 1d mixes partial programs addresses in the absolute section remain unchanged For example address absolute 0 is relocated to run time address 0 by 1d Although the linker never arranges two partial programs data sections with overlapping addresses after linking by definition their absolute sections must overlap Address absolute 239 in one part of a program is always the same address when the program is running as address absolute 239 in any other part of the program The idea of sections is extended to the undefined section Any address whose section is unknown at assembly time is by definition rendered undefined U where U is filled in later Since numbers are always defined the only way to generate an undefined address is to mention an undefined symbol A reference to a named common block would be such a symbol its value is unknown at assembly time so it has section undefined
24. 0 indicates an octal value The value of the symbol can be overridden inside a source file via the use of a set pseudo op fast skip whitespace and comment preprocessing assume source is compiler output gen debug gstabs gstabs gdwarf 2 Generate debugging information for each assembler source line using whichever debug format is preferred by the target This currently means either S TABS ECOFF or DWARF2 Generate stabs debugging information for each assembler line This may help debugging assembler code if the debugger can handle it Generate stabs debugging information for each assembler line with GNU exten sions that probably only gdb can handle and that could make other debuggers crash or refuse to read your program This may help debugging assembler code Currently the only GNU extension is the location of the current working directory at assembling time Generate DWARF2 debugging information for each assembler line This may help debugging assembler code if the debugger can handle it Note this option is only supported by some targets not all of them gdwarf sections Instead of creating a debug line section create a series of debug_line foo sec tions where foo is the name of the corresponding code section For example a code section called text func will have its dwarf line number information placed into a section called debug line text func If the code section is just called
25. ADRL reg lt label gt pseudo op ARM ADRP ADD LDR STR group relocations AArch64 22i ege l9 Fem eR UR RIVE advancing location counter sess align directive sopce dee HERR RUPES align directive Nios DU align directive BDARC align directive TIC54X 000 aligned instruction bundle ssssscenenenu alignment for NEON instructions alignment of branch Loargets alignment of LOOP instructions Alpha floating point REF Alpha line comment character Alpha line separator esses STT y ASI ER PW REN ceed Alpha optionS 2 leis cese us ese e cease Alpha registers 2c eese el a ege Alpha relocations 00000 c eee e cece ee Alpha supports EENS NEEN seein dpud Alpha Baas e coed eue ENEE EE Eee Alpha only directives 0 00 eee eee Altera Nios II support ssssrenrresn altered difference table alternate syntax for the 680x0 ARC floating point DEER ARC line comment character ARC line separator esses ARC machine directives 000 0002000 ARG opcodes iere bv e bein yee REEF RI ARC options none ARC register namen E kB REY CER nd eee rcb arch ARC eeu bb esae ete ar esr arc6 atch ARG odes bre de re nex ere arc arcet ARG S esae e eek Ee REA sas arc8 rc8 ARG lo suoi sea ere c exe pu arch directive i386 0 00 eee eee ee eee arch directive Mont arch directive MSP 480
26. Aleon Asparclet Asparclite Av8plus Av8plusa Av8plusb Av8plusc Av8plusd Av8plusv Av9 Av9a Av9b Av9c Av9d Av9v Asparc Asparcvis Asparcvis2 Asparcfmaf Asparcima Asparcvis3 Asparcvis3r Use one of the A options to select one of the SPARC architectures explicitly If you select an architecture explicitly as reports a fatal error if it encounters an instruction or feature requiring an incompatible or higher level Av8plus Av8plusa Av8plusb Av8plusc Av8plusd and Av8plusv select a 32 bit environment Av9 Av9a Av9b Av9c Av9d and Av9v select a 64 bit envi ronment and are not available unless GAS is explicitly configured with 64 bit environment support Av8plusa and Av9a enable the SPARC V9 instruction set with Ultra SPARC VIS 1 0 extensions Av8plusb and Av9b enable the UltraSPARC VIS 2 0 instructions as well as the instructions enabled by Av8plusa and Av9a Av8plusc and Av9c enable the UltraSPARC Niagara instructions as well as the instructions enabled by Av8plusb and Av9b Av8plusd and Av9d enable the floating point fused multiply add VIS 3 0 and HPC extension instructions as well as the instructions enabled by Av8plusc and Av9c Av8plusv and Av9v enable the random transa
27. character can be used to separate statements on the same line Chapter 9 Machine Dependent Features 163 9 18 IA 64 Dependent Features 9 18 1 Options mconstant gp This option instructs the assembler to mark the resulting object file as using the constant GP model With this model it is assumed that the entire program uses a single global pointer GP value Note that this option does not in any fashion affect the machine code emitted by the assembler All it does is turn on the EF IA G4 CONS GP flag in the ELF file header mauto pic This option instructs the assembler to mark the resulting object file as using the constant GP without function descriptor data model This model is like the constant GP model except that it additionally does away with function descriptors What this means is that the address of a function refers directly to the function s code entry point Normally such an address would refer to a function descriptor which contains both the code entry point and the GP value needed by the function Note that this option does not in any fashion affect the machine code emitted by the assembler All it does is turn on the EF IA 64 NOFUNCDESC CONS GP flag in the ELF file header milp32 milp64 m1 p64 mp64 These options select the data model The assembler defaults to m1p64 LP64 data model mle mbe These options select the byte order The mle optio
28. minsn32 mno insn32 Only use 32 bit instruction encodings when generating code for the microMIPS processor This option inhibits the use of any 16 bit instructions This is equiv alent to putting set insn32 at the start of the assembly file mno insn32 turns off this option This is equivalent to putting set noinsn32 at the start of the assembly file By default mno insn32 is selected allowing all instructions to be used mfix7000 mno fix7000 Cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions mfix loongson2f jump mno fix loongson2f jump Eliminate instruction fetch from outside 256M region to work around the Loong son2F jump instructions Without it under extreme cases the kernel may crash The issue has been solved in latest processor batches but this fix has no side effect to them mfix loongson2f nop mno fix loongson2f nop Replace nops by or at at zero to work around the Loongson2F nop errata Without it under extreme cases the CPU might deadlock The issue has been solved in later Loongson2F batches but this fix has no side effect to them mfix vr4120 mno fix vr4120 Insert nops to work around certain VR4120 errata This option is intended to be used on GCC generated code it is not designed to catch all problems in hand written assembler code Chapter 9 Machine Dependent Features 195 mfix vr4
29. mno fix7000 Cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions Chapter 1 Overview 13 mdebug no mdebug Cause stabs style debugging output to go into an ECOFF style mdebug section instead of the standard ELF stabs sections mpdr mno pdr Control generation of pdr sections mgp32 mfp32 The register sizes are normally inferred from the ISA and ABI but these flags force a certain group of registers to be treated as 32 bits wide at all times mgp32 controls the size of general purpose registers and mfp32 controls the size of floating point registers mipsi6 no mipsi6 Generate code for the MIPS 16 processor This is equivalent to putting set mipsi6 at the start of the assembly file no mips16 turns off this option mmicromips mno micromips Generate code for the microMIPS processor This is equivalent to putting set micromips at the start of the assembly file mno micromips turns off this option This is equivalent to putting set nomicromips at the start of the assembly file msmartmips mno smartmips Enables the SmartMIPS extension to the MIPS32 instruction set This is equivalent to putting set smartmips at the start of the assembly file mno smartmips turns off this option mips3d no mips3d Generate code for the MIPS 3D Application Specific Extension This tells the assembler to ac
30. or jn 2 jmp 4 br label bltu label A polymorph instruction which is jlo label or jhs 2 br label bge label A polymorph instruction which is jge label or j1 4 br label bgeu label A polymorph instruction which is jhs label or jlo 4 br label bgt label A polymorph instruction which is jeq 2 jge label or jeq 6 j1 4 br label bgtu label A polymorph instruction which is jeq 2 jhs label or jeq 6 jlo 4 br label bleu label A polymorph instruction which is jeq label jlo label or jeq 2 jhs 4 br label Chapter 9 Machine Dependent Features 213 ble label A polymorph instruction which is jeq label jl label or jeq 2 jge 4 br label jump label A polymorph instruction which is jmp label or br label 9 29 3 Floating Point The MSP 430 family uses IEEE 32 bit floating point numbers 9 29 4 MSP 430 Machine Directives file This directive is ignored it is accepted for compatibility with other MSP 430 assemblers Warning in other versions of the GNU assembler file is used for the directive called app file in the MSP 430 support line This directive is ignored it is accepted for compatibility with other MSP 430 assemblers arch Sets the target microcontroller in the same way as the mmcu command line option cpu Sets the target architecture in the same way as the mcpu command line option
31. By analogy the word section is used to describe groups of sections in the linked program 1d puts all partial programs text sections in contiguous addresses in the linked program It is customary to refer to the tert section of a program meaning all the addresses of all partial programs text sections Likewise for data and bss sections Some sections are manipulated by 1d others are invented for use of as and have no meaning except during assembly 4 2 Linker Sections 1d deals with just four kinds of sections summarized below named sections text section data section These sections hold your program as and 1d treat them as separate but equal sections Anything you can say of one section is true of another When the pro gram is running however it is customary for the text section to be unalterable The text section is often shared among processes it contains instructions con stants and the like The data section of a running program is usually alterable for example C variables would be stored in the data section bss section This section contains zeroed bytes when your program begins running It is used to hold uninitialized variables or common storage The length of each partial program s bss section is important but because it starts out containing zeroed bytes there is no need to store explicit zero bytes in the object file The bss section was invented to eliminate those explicit zeros from object files Chapter 4
32. D1 B2 D2 4 4 4 4 4 4 4 0 8 12 16 20 32 36 4T SSE format lt insn gt D1 B1 D2 B2 4 4 4 4 4 OpCode B1 D1 B2 D2 4 4 4 4 4 0 8 12 16 20 32 36 4T SSF format lt insn gt D1 B1 D2 B2 R3 4 4 4 4 4 4 4 OpCode R3 OpCdl B1 D1 B2 D2 l 4 4 4 4 4 4 4 0 8 12 16 20 32 36 4T For the complete list of all instruction format variants see the Principles of Operation manuals 9 37 3 5 Instruction Aliases A specific bit pattern can have multiple mnemonics for example the bit pattern 0xa7000000 has the mnemonics tmh and tmlh In addition there are a number of mnemonics recognized by as that are not present in the Principles of Operation These are the short forms of the branch instructions where the condition code mask operand is encoded in the mnemonic This is relevant for the branch instructions the compare and branch instructions and the compare and trap instructions For the branch instructions there are 20 condition code strings that can be used as part of the mnemonic in place of a mask operand in the instruction format instruction short form Chapter 9 ber be bre brel Machine Dependent Features 239 M1 R2 M1 D2 X2 B2 VI VII b m r
33. L2DR L2D L3DR L3D SYS TRAP 9 32 5 Synthetic Instructions The JBR and JCC synthetic instructions are not supported yet Chapter 9 Machine Dependent Features 223 9 33 picoJava Dependent Features 9 33 1 Options as has two additional command line options for the picoJava architecture ml This option selects little endian data output mb This option selects big endian data output 9 33 2 PJ Syntax 9 33 2 1 Special Characters The presence of a or on a line indicates the start of a comment that extends to the end of the current line If a appears as the first character of a line then the whole line is treated as a comment but in this case the line could also be a logical line number directive see Section 3 3 Comments page 27 or a preprocessor control command see Section 3 1 Preprocessing page 27 The character can be used to separate statements on the same line 224 Using as 9 34 PowerPC Dependent Features 9 34 1 Options The PowerPC chip family includes several successive levels using the same core instruction set but including a few additional instructions at each level There are exceptions to this however For details on what instructions each variant supports please see the chip s architecture reference manual The following table lists all available PowerPC options a32 Generate ELF32 or XCOFF32 a64 Generate ELF64 or XCOFF64 K PIC Set EF PPC RELOCATABLE LIB
34. Permission is granted to copy distribute and or modify this document under the terms of the GNU Free Documentation License Version 1 3 or any later version published by the Free Software Foundation with no Invariant Sections no Front Cover Texts and no Back Cover Texts A copy of the license is included in the section entitled GNU Free Documentation License If you have Invariant Sections Front Cover Texts and Back Cover Texts replace the with Texts line with this with the Invariant Sections being list their titles with the Front Cover Texts being list and with the Back Cover Texts being list If you have Invariant Sections without Cover Texts or some other combination of the three merge those two alternatives to suit the situation If your document contains nontrivial examples of program code we recommend releasing these examples in parallel under your choice of free software license such as the GNU General Public License to permit their use in free software AS Index AS Index lp TET 28 FEA sedge esa Wei esca qi mend NEUE eed 2T SNO APP se mcn ete Re mRNA RUE eS 27 in symbol names 126 130 190 248 252 Ims 105 acos math builtin TIC54X 265 asin math builtin TIC54X 265 atan math builtin TIC54X 265 atan2 math builtin TIC54X 265 ceil math builtin TIC54X 266 cos math builtin TIC54X
35. TILEP DIR RR aan EE EREA 285 save directive ADM 102 scomm directive TTIOox 275 Secrel32 directive ARM 103 Set arche6p cii EES e 200 BOLD EE 198 jSet at regu ege gege EP Dee eu 198 set autoextend siete et LR een 200 set doubleflo8t m err rr RR Eve 202 Set dSDugusis toe rusos pere PERI E 202 BEE dSDI2 i25 onis Ye Feet e Seu 202 Set hardfloat e NR RENE EEN pe ye nd 202 Set insn32 na Rr REPRE rane 200 SOE MACIO resi dice gare ad gainers A dal sus 198 SBOE MCW sors daca eerte e cea ea esd se ee ae RS 202 HS OE EE 202 Set mips3d ie le s ner ebd 202 Set WIDE ies ER E 199 334 SOU m 202 Set DEE ou c a ye p EUR A IRERE nE dE EN 198 Set noautoextend ci oe ee REL ES 200 Ee EE 202 d Ee nodSpr2 e deeg Zeg GU RM eR LESE 202 set noinsu32 i bb EXE PRAG CFR 200 Set nomaCro ecl gu pk e rep 198 SST TOMO EE 202 Bet nomdHx EELER RENE EECH 202 Set nomips3d 2 11 oss Hele pede hides 202 Set MOME EE exe eme ey Seefe EE A 202 Set nosmartmipS s ecc einans inent na En 202 Set MOBYMI EE 198 M NOVELE E E Y Yr eH EE 202 BCU pop oueiemeeceesd e ud ee ee e puso 201 Set push di2 zre eres we x ace ta deseaes 201 Set singlefloat i 12 ae de Y ees 202 860 Snartmips isnsll e 19 ss e eper e ees 202 Set soOftfloat i wo x etx RES 202 Set SYM Z EE 198 dBet EE d dE e es c ee due E Ree 202 setfp directive ARM 102 Short directive s 00 02 eee eee 244 syntax
36. b w 1 or q respectively The x86 64 architecture adds an RIP instruction pointer relative addressing This addressing mode is specified by using rip as a base register Only constant offsets are valid For example AT amp T 1234 rip Intel rip 1234 Points to the address 1234 bytes past the end of the current instruction AT amp T symbol rip Intel rip symbol Points to the symbol in RIP relative way this is shorter than the default abso lute addressing Other addressing modes remain unchanged in x86 64 architecture except registers used are 64 bit instead of 32 bit 9 15 9 Handling of Jump Instructions Jump instructions are always optimized to use the smallest possible displacements This is accomplished by using byte 8 bit displacement jumps whenever the target is sufficiently close If a byte displacement is insufficient a long displacement is used We do not support word 16 bit displacement jumps in 32 bit mode i e prefixing the jump instruction with the data16 instruction prefix since the 80386 insists upon masking eip to 16 bits after the word displacement is added See also see Section 9 15 17 1386 Arch page 154 152 Using as Note that the jcxz jecxz loop loopz loope loopnz and loopne instruc tions only come in byte displacements so that if you use these instructions gcc does not use them
37. mf option far mode 2 eee ee 264 SIDEDJ ENEE 220 mfar mode option far mode 264 mfdpic command line option Blackfin 114 DOULEUR 219 mfloat abi command line option ARM 97 SMM P L dk orit PD o RR ERE 219 e EE 219 SPD peed ages de tea Se needa 219 mfpu command line option ARM 96 SMECC aDl EE 228 mgcc abi command line option V850 296 micache enabled command line option LM32 nr 167 mimplicit it command line option ARM 96 emint regisSter dee ee rre RETI 228 mip2022 option IP2K cose re 166 mip2022ext option P2022 166 SLL MM ORNA 220 332 mkell 22se e ssi t eet ve pesar 220 SMA DM RENE 220 lh E estere Rer HERE REG 220 SG Ch EE 220 mould 220 Ch EEN 220 mk lf i o weg Rer nearer ee eee 220 zmkdllh oiisemLIREebebR ewe EMPRESA RS 220 Amnkdllk 2 imet e eran rnae DEN EP 220 CN E EE 220 EN EE 220 Zmkevlla ieIleMRebe vIB pePR Godan bPIde 219 smilimited 18 sorori rearen t eV ere eb IS 219 mlittle endian cece ee eens 228 gg RTE 184 303 nlong do ble ree eee els 184 303 Err 184 E Ince ute e sexe eae pEU i 184 mmcu command line option AVR 108 zip 220 Inmicrocode z ea paa ee ACRES 220 mmnemonic option 1380 146 mmnemonic option x86 64 146 mmultiply enabled command line option LM32 EE 167 mun
38. scl size tag and weak can generate auxiliary symbol table information for COFF 5 5 5 Symbol Attributes for SOM The SOM format for the HPPA supports a multitude of symbol attributes set with the EXPORT and IMPORT directives The attributes are described in HP9000 Series 800 Assembly Language Reference Manual HP 92432 90001 under the IMPORT and EXPORT assembler directive documentation Chapter 6 Expressions 43 6 Expressions An expression specifies an address or numeric value Whitespace may precede and or follow an expression The result of an expression must be an absolute number or else an offset into a particular section If an expression is not absolute and there is not enough information when as sees the expression to know its section a second pass over the source program might be necessary to interpret the expression but the second pass is currently not implemented as aborts with an error message in this situation 6 1 Empty Expressions An empty expression has no value it is just whitespace or null Wherever an absolute expression is required you may omit the expression and as assumes a value of absolute 0 This is compatible with other assemblers 6 2 Integer Expressions An integer expression is one or more arguments delimited by operators 6 2 1 Arguments Arguments are symbols numbers or subexpressions In other contexts arguments are some times called arithmetic operands In this manual
39. the right value Chapter 9 hilo sdaoff tdaoff zdaof f ctoff Machine Dependent Features 301 Computes the 32 bit value of the given expression and stores it into the imme diate operand field of the given instruction which must be a mov instruction For example mov hilo here r6 computes the absolute address of label here and puts the result into register 6 Computes the offset of the named variable from the start of the Small Data Area whoes address is held in register 4 the GP register and stores the result as a 16 bit signed value in the immediate operand field of the given instruction For example ld w sdaoff a variable gp r6 loads the contents of the location pointed to by the label _a_variable into register 6 provided that the label is located somewhere within 32K of the address held in the GP register Note the linker assumes that the GP register contains a fixed address set to the address of the label called __gp This can either be set up automatically by the linker or specifically set by using the defsym __gp lt value gt command line option Computes the offset of the named variable from the start of the Tiny Data Area whoes address is held in register 30 the EP register and stores the result as a 4 5 7 or 8 bit unsigned value in the immediate operand field of the given instruction For example sld w tdaoff _a_variable ep r6
40. ular machine instruction depending on the displacement to the branch target jbXX Here jbXX stands for an entire family of pseudo operations where XX is a conditional branch or condition code test The full list of pseudo ops in this family is Chapter 9 Machine Dependent Features 189 jbcc jbeq jbge bet jbhi jbvs pl blo jbcs jbne jblt jble jbls jbvc jbmi For the cases of non PC relative displacements and long displacements as issues a longer code fragment in terms of NX the opposite condition to XX For example for the non PC relative case jbXX foo gives bNXs oof jmp foo oof 190 Using as 9 25 Meta Dependent Features 9 25 1 Options The Imagination Technologies Meta architecture is implemented in a number of versions with each new version adding new features such as instructions and registers For precise details of what instructions each core supports please see the chip s technical reference manual The following table lists all available Meta options mcpu metacii Generate code for Meta 1 1 mcpu metaci2 Generate code for Meta 1 2 mcpu metac21 Generate code for Meta 2 1 mfpu metac21 Allow code to use FPU hardware of Meta 2 1 9 25 2 Syntax 9 25 2 1 Special Characters is the line comment character You can use instead of a newline to separate statements Since has no special meaning you may use it in symbol names 9 25 2 2 Register Names Registers can b
41. 00 00a 202 global idu eda Gnas GRD EET RE 290 global CEET 56 global directive DIC45 269 got directive Nios IL esee nn 216 gotoff directive Nios I 216 gotoff hiadj directive Nios II 216 gotoff_lo directive Nios I 216 gp register MIPS wi cscseecssesecaes mener 199 Ep register V850 c Loose dE R REY deed 207 gprel directive Nios D 215 grouping dala ec Age UE RIRs 35 H H8 300 addressing mode 134 H8 300 floating point IEEE sss 135 H8 300 line comment character 134 H8 300 line separater 134 H8 300 machine directives none 136 H8 300 opcode summary esses 136 IER 134 H5 300 registerss i antea or RO DRLRIP DIM 134 H8 300 size suffixes EEN eee 136 H8 300 support As EE ENEE t needs 134 H8 300H assembling for 136 half directive AR 93 half directive Nios HU 216 half directive SPARC 0000 263 half directive TIC54X 006 269 hex character code Dsg 29 hexadecimal integers scsuscreresrrerer 30 hexadecimal prefix Z80 suususus 286 hfloat directive VAN 292 hi directive Nios DU 215 hi pseudo op ND 300 hiO pseudo op VS 300 hiadj directive Nios D 215 hidden directive 2 cee eee eee eee 56 high directive M32R deed 173 hilo pseudo op VSD0 eee eee eee 300 HPPA directives not supported 137 HPPA floating point DEER
42. 264 Using as 9 42 TIC54X Dependent Features 9 42 1 Options The TMS320C54X version of as has a few machine dependent options You can use the mfar mode option to enable extended addressing mode All addresses will be assumed to be gt 16 bits and the appropriate relocation types will be used This option is equivalent to using the far_mode directive in the assembly code If you do not use the mfar mode option all references will be assumed to be 16 bits This option may be abbreviated to mf 6 You can use the mcpu option to specify a particular CPU This option is equivalent to using the version directive in the assembly code For recognized CPU codes see See Section 9 42 9 version page 267 The default CPU version is 542 You can use the merrors to file option to redirect error output to a file this pro vided for those deficient environments which don t provide adequate output redirection This option may be abbreviated to me 9 42 2 Blocking A blocked section or memory block is guaranteed not to cross the blocking boundary usually a page or 128 words if it is smaller than the blocking size or to start on a page boundary if it is larger than the blocking size 9 42 3 Environment Settings C54XDSP_DIR and A_DIR are semicolon separated paths which are added to the list of di rectories normally searched for source and include files C54XDSP_DIR wil
43. 310 call instructions x86 64 0 0 2005 149 callj i960 Geeudo opcode 161 carriage return Deh eee EE gr 29 case sensitivity Z80 voci crrr rdiet Erens 08 287 cfi endproc directe 50 cfi sections directive 0 c eee eee 50 cfi startproc directive ac oes rte 50 char directive TIC54X seseseserceeseceu 267 character constant 280 287 character constanis d n pees ed 29 character escape code 29 character escapes Z80 000 cece eee eee 286 Character Single venenis ep ER RE EE EDU 30 characters used in smbols s ssrsruresn 28 clink directive TICS4X Lsuuuuusus 268 code16 directive i886 ec eee eee eee 153 codel6gcc directive i386 006 153 code32 directive 12906 153 code64 directive i386 ec eee eee eee 153 code64 directive x86 64 0 000 153 COFF auxiliary symbol information 53 COFF structure debugging suus 75 COFF symbol attributes 42 COFF symbol descriptor sses ersrsscscurinerii 53 COFF symbol storage dass 69 COFF symbol types tesrisarte oireiden niia 76 COFF symbols debugging 53 COFF value attribute 002 T COMDAT eases qucbz de eme Ih RE RUE Der ub 60 comm CDe ee RER reip rr RR 52 command line convention 17 AS Index command line options V850 295 command line options ignored VAX 291 comment character XStor
44. 9 7 1 CR16 Operand Qualifiers The National Semiconductor CR16 target of as has a few machine dependent operand qualifiers Operand expression type qualifier is an optional field in the instruction operand to deter mines the type of the expression field of an operand The is required CR16 architecture uses one of the following expression qualifiers S Specifies expression operand type as small m Specifies expression operand type as medium Specifies expression operand type as large c S Specifies the CR16 Assembler generates a relocation entry for the operand where pc has implied bit the expression is adjusted accordingly The linker uses the relocation entry to update the operand address at link time got GOT Specifies the CR16 Assembler generates a relocation entry for the operand offset from Global Offset Table The linker uses this relocation entry to update the operand address at link time cgot cGOT S Specifies the CompactRISC Assembler generates a relocation entry for the operand where pc has implied bit the expression is adjusted accordingly The linker uses the relocation entry to update the operand address at link time CR16 target operand qualifiers and its size in bits Immediate Operand s 4 bits Immediate Operand m 16 bits for movb and movw instructions Immediate Operand m 20 bits movd instructions Immediate Operand 1 32 bits Absolute Operand s Illegal
45. Set Architecture available upon request at www tilera com 9 44 2 2 Register Names General purpose registers are represented by predefined symbols of the form rN where N represents a number between 0 and 63 However the following registers have canonical names that must be used instead 278 Using as r54 sp r55 lr r56 sn r57 idnO r58 idnl r59 udn0 r60 udnl r61 udn2 r62 udn3 r63 Zero The assembler will emit a warning if a numeric name is used instead of the non numeric name The no require canonical reg names assembler pseudo op turns off this warn ing require canonical reg names turns it back on 9 44 2 3 Symbolic Operand Modifiers The assembler supports several modifiers when using symbol addresses in TILE Gx instruc tion operands The general syntax is the following modifier symbol The following modifiers are supported hwO This modifier is used to load bits 0 15 of the symbol s address hwi This modifier is used to load bits 16 31 of the symbol s address hw2 This modifier is used to load bits 32 47 of the symbol s address hw3 This modifier is used to load bits 48 63 of the symbol s address bw last This modifier yields the same value as hwO but it also checks that the value does not overflow hwi last This modifier yields the same value as hw1 but it also checks that the value does not overflow hw2 last This modifier yields the same value as hw2 but it also checks that the value d
46. Tag GNU Power ABI Vector 8 The vector ABI used by this object file The value will be e 0 for files not affected by the vector ABI e 1 for files using general purpose registers to pass vectors e 2 for files using AltiVec registers to pass vectors e 3 for files using SPE registers to pass vectors 8 2 Defining New Object Attributes If you want to define a new GNU object attribute here are the places you will need to modify New attributes should be discussed on the binutils mailing list e This manual which is the official register of attributes e The header for your architecture include elf to define the tag e The bfd support file for your architecture to merge the attribute and issue any appropriate link warnings e Test cases in 1d testsuite for merging and link warnings e binutils readelf c to display your attribute e GCO if you want the compiler to mark the attribute automatically Chapter 9 Machine Dependent Features 81 9 Machine Dependent Features The machine instruction sets are almost by definition different on each machine where as runs Floating point representations vary as well and as often supports a few additional directives or command line options for compatibility with other assemblers on a particu lar platform Finally some versions of as support special pseudo instructions for branch optimization This chapter discusses most of these differences though it doe
47. The presence of a on a line indicates the start of a comment that extends to the end of the current line Note that if a line starts with a character then it can also be a logical line number directive see Section 3 3 Comments page 27 or a preprocessor control command see Section 3 1 Preprocessing page 27 The ARC assembler does not support a line separator character 9 3 2 2 Register Names TODO 9 3 3 Floating Point The ARC core does not currently have hardware floating point support Software floating point support is provided by GCC and uses IEEE floating point numbers 9 3 4 ARC Machine Directives The ARC version of as supports the following additional machine directives 2byte expressions TODO 3byte expressions PODO 92 Using as Abyte expressions TODO extAuxRegister name address mode The ARCtangent A4 has extensible auxiliary register space The auxiliary registers can be defined in the assembler source code by using this directive The first parameter is the name of the new auxiallry register The second parameter is the address of the register in the auxiliary register memory map for the variant of the ARC The third parameter specifies the mode in which the register can be operated is and it can be one of r readonly w write only r w read or write For example extAuxRegister mulhi 0x12 w This specifies an extension auxiliary register called mulhi which is at
48. Thus you might assume that the name of a symbol you use in an example does not matter Well probably it does not but one cannot be sure Perhaps the bug is a stray memory reference which happens to fetch from the location where that name is stored in memory perhaps if the name were different the contents of that location would fool the assembler into doing the right thing despite the bug Play it safe and give a specific complete example That is the easiest thing for you to do and the most helpful Keep in mind that the purpose of a bug report is to enable us to fix the bug if it is new to us Therefore always write your bug reports on the assumption that the bug has not been reported previously Sometimes people give a few sketchy facts and ask Does this ring a bell This cannot help us fix a bug so it is basically useless We respond by asking for enough details to 316 Using as enable us to investigate You might as well expedite matters by sending them to begin with To enable us to fix the bug you should include all these things e The version of as as announces it if you start it with the version argument Without this we will not know whether there is any point in looking for the bug in the current version of as e Any patches you may have applied to the as source e The type of machine you are using and the operating system name and version number e What compiler and its version was used to compile as op
49. Using as Debug exception base address JTAG transmit JTAG receive Breakpoint 0 Breakpoint 1 Breakpoint 2 Breakpoint 3 Watchpoint 0 Watchpoint 1 Watchpoint 2 Watchpoint 3 9 20 2 2 Relocatable Expression Modifiers The assembler supports several modifiers when using relocatable addresses in LM32 instruc tion operands The general syntax is the following lo hi BP got gotofflolG gotoffhil6 modifier relocatable expression This modifier allows you to use bits 0 through 15 of an address expression as 16 bit relocatable expression This modifier allows you to use bits 16 through 23 of an address expression as 16 bit relocatable expression For example ori r4 r4 lo sym 10 orhi r4 r4 hi sym 10 This modified creates a 16 bit relocatable expression that is the offset of the symbol from the global pointer mva r4 gp sym This modifier places a symbol in the GOT and creates a 16 bit relocatable expression that is the offset into the GOT of this symbol lw r4 gp got sym This modifier allows you to use the bits 0 through 15 of an address which is an offset from the GOT This modifier allows you to use the bits 16 through 31 of an address which is an offset from the GOT orhi r4 r4 gotoffhii6 lsym addi r4 r4 gotofflo16 1lsym Chapter 9 Machine Dependent Features 169 9 20 2 3 Special Characters The presence of a on a line indicates the start of a comment that extends
50. Will place 0x1234 and Ox9abc into subsection 1 and 0x5678 into subsection 2 of section A Whilst Section A sSubsection 1 Now in section A subsection word 0x1234 Section B subsection 0 Now in section B subsection 0 word 0x5678 Subsection 1 Now in section B subsection word Ox9abc previous Now in section B subsection 0 word OxdefO Will place 0x1234 into section A 0x5678 and Oxdef0 into subsection 0 of section B and Ox9abc into subsection 1 of section B e pe In terms of the section stack this directive swaps the current section with the top section on the section stack 7 89 priut string as will print string on the standard output during assembly You must put string in double quotes 7 90 protected names This is one of the ELF visibility directives The other two are hidden see Section 7 59 Hidden page 56 and internal see Section 7 66 Internal page 59 This directive overrides the named symbols default visibility which is set by their bind ing local global or weak The directive sets the visibility to protected which means that any references to the symbols from within the components that defines them must be resolved to the definition in that component even if a definition in another component would normally preempt this 7 91 psize lines columns Use this directive to declare the number of lines and optionally the number of columns to use for each page when ge
51. and each start a comment anywhere on the line Thus you can t use the modulus and not operators in expressions normally associated with these two characters A is a line separator treated as a new line so separate instructions can be specified on a single line 9 28 3 2 Symbols The character is permitted in identifiers There are two exceptions to it being treated as any other symbol character if a symbol begins with it means that the symbol is in the global namespace and that the current prefix should not be prepended to that symbol see MMIX prefix page 209 The is then not considered part of the symbol For a symbol in the label position first on a line a at the end of a symbol is silently stripped off A label is permitted but not required to be followed by a as with many other assembly formats The character in an expression is a synonym for the current location In addition to the common forward and backward local symbol formats see Section 5 3 Symbol Names page 39 they can be specified with upper case B and F as in 8B and OF A local label defined for the current position is written with a H appended to the number 3H LDB 0 1 2 This and traditional local label formats cannot be mixed a label must be defined and referred to using the same format There s a minor caveat just as for the ordinary
52. example libgcc a contains generic routines used by the code produced by GCC for all versions of the v850 architecture together with support routines only used by the V850E architecture mv850e2 Specifies that the assembled code should be marked as being targeted at the V850E2 processor This allows the linker to detect attempts to link such code with code assembled for other processors mv850e2v3 Specifies that the assembled code should be marked as being targeted at the V850E2V3 processor This allows the linker to detect attempts to link such code with code assembled for other processors mv850e2v4 This is an alias for mv850e3v5 mv850e3v5 Specifies that the assembled code should be marked as being targeted at the V850E3V5 processor This allows the linker to detect attempts to link such code with code assembled for other processors mrelax Enables relaxation This allows the longcall and longjump pseudo ops to be used in the assembler source code These ops label sections of code which are either a long function call or a long branch The assembler will then flag these sections of code and the linker will attempt to relax them mgcc abi Marks the generated objecy file as supporting the old GCC ABI mrh850 abi Marks the generated objecy file as supporting the RH850 ABI This is the default m8byte align Marks the generated objecy file as supporting a maximum 64 bits of alignment for variables defined in the sou
53. far 187 M68HC11 assembler directive interrupt 188 M68HC11 assembler directive mode 187 M68HC11 assembler directive relax 187 M68HC11 assembler directive xrefb 188 M68HC11 assembler directives 187 M68HC11 branch improvement 188 M68HC11 floating poomt 188 M68HC11 line comment character 185 M68HC11 line separater 185 M68HC11 modifiers 2 000 e eee 187 M68HC11 opcodes 2 eese ei 188 M68HC11 options cece eee eee 184 M68HC11 pseudo opcodes 005 188 MO68HCLI Syntax ccs tee N IER ETE REN ees 185 M68HC12 assembler directives 187 machine dependencies 0 20 eee eee 81 machine directives AArch64 83 machine directives ARC 91 machine directives ARM 99 machine directives H8 300 none 136 machine directives 1900 156 machine directives 19000 160 machine directives MSP 430 213 machine directives Nios II 216 machine directives HH 250 machine directives Hoi 252 machine directives SPARC ss 262 machine directives TIC54X suuus 267 machine directives TIC6X 200 275 machine directives TILE Gx 280 machine directives TILEPro 285 machine directives VD 299 machine directives VAN 292 machine directives 280 14
54. including object file formats most assembler directives often called pseudo ops and assembler syntax as is primarily intended to assemble the output of the GNU C compiler gcc for use by the linker 1d Nevertheless we ve tried to make as assemble correctly everything that other assemblers for the same machine would assemble Any exceptions are documented explicitly see Chapter 9 Machine Dependencies page 81 This doesn t mean as always uses the same syntax as another assembler for the same architecture for example we know of several incompatible versions of 680x0 assembly language syntax Unlike older assemblers as is designed to assemble a source program in one pass of the source file This has a subtle impact on the org directive see Section 7 85 org page 65 1 3 Object File Formats The GNU assembler can be configured to produce several alternative object file formats For the most part this does not affect how you write assembly language programs but direc tives for debugging symbols are typically different in different file formats See Section 5 5 Symbol Attributes page 41 1 4 Command Line After the program name as the command line may contain options and file names Options may appear in any order and may be before after or between file names The order of file names is significant two hyphens by itself names the standard input file explicitly as one of the files for as to assemble
55. sdata2 Switch to sdata2 section Equivalent to section sdata2 Sdata Switch to sdata section Equivalent to section sdata bss Switch to bss section Equivalent to section bss Sbss Switch to sbss section Equivalent to section sbss 9 26 2 Syntax for the MicroBlaze 9 26 2 1 Special Characters The presence of a on a line indicates the start of a comment that extends to the end of the current line If a 4 appears as the first character of a line the whole line is treated as a comment but in this case the line can also be a logical line number directive see Section 3 3 Comments page 27 or a preprocessor control command see Section 3 1 Preprocessing page 27 The character can be used to separate statements on the same line 192 Using as 9 27 MIPS Dependent Features GNU as for MIPS architectures supports several different MIPS processors and MIPS ISA levels I through V MIPS32 and MIPS64 For information about the MIPS instruction set see MIPS RISC Architecture by Kane and Heindrich Prentice Hall For an overview of MIPS assembly conventions see Appendix D Assembly Language Programming in the same work 9 27 1 Assembler options The MIPS configurations of GNU as support these special options G num Set the small data limit to n bytes The default limit is 8 bytes See Section 9 27 4 Controlling the use of small data accesses page 199 EB EL Any MIPS configuration of as c
56. skip size fill This directive emits size bytes each of value fill Both size and fill are absolute expressions If the comma and fill are omitted fill is assumed to be zero This is the same as space 7 105 sleb128 expressions sleb128 stands for signed little endian base 128 This is a compact variable length rep resentation of numbers used by the DWARF symbolic debugging format See Section 7 116 uleb128 page 77 Chapter 7 Assembler Directives 73 7 106 space size fill This directive emits size bytes each of value fill Both size and fill are absolute expressions If the comma and fill are omitted fill is assumed to be zero This is the same as skip Warning space has a completely different meaning for HPPA targets use block as a substitute See HP9000 Series 800 Assembly Language Refer ence Manual HP 92432 90001 for the meaning of the space directive See Section 9 13 5 HPPA Assembler Directives page 137 for a summary 7 107 stabd stabn stabs There are three directives that begin stab All emit symbols see Chapter 5 Symbols page 39 for use by symbolic debuggers The symbols are not entered in the as hash table they cannot be referenced elsewhere in the source file Up to five fields are required string This is the symbol s name It may contain any character except 000 so is more general than ordinary symbol names Some debuggers used to code arbitrarily co
57. unlock inside assembler macros see Section 7 79 Macro page 62 bundle locked sequences may be nested That is a second bundle lock directive before the next bundle unlock directive has no effect 50 Using as except that it must be matched by another closing bundle_unlock so that there is the same number of bundle_lock and bundle_unlock directives 7 10 byte expressions byte expects zero or more expressions separated by commas Each expression is assembled into the next byte 7 11 cfi_sections section_list cfi_sections may be used to specify whether CFI directives should emit eh_frame section and or debug_frame section If section_list is eh_frame eh_frame is emitted if section_list is debug_frame debug_frame is emitted To emit both use eh_frame debug_frame The default if this directive is not used is cfi_sections eh_frame 7 12 cfi_startproc simple cfi_startproc is used at the beginning of each function that should have an entry in eh_frame It initializes some internal data structures Don t forget to close the function by cfi_endproc Unless cfi_startproc is used along with parameter simple it also emits some archi tecture dependent initial CFI instructions 7 13 cfi endproc cfi endproc is used at the end of a function where it closes its unwind entry previously opened by cfi startproc and emits it to eh frame 7 14 cfi personality encoding exp cfi personality defines pe
58. you may get an error message and incorrect code The AT amp T 80386 assembler tries to get around this problem by expanding jcxz foo to jcxz cx_zero jmp cx_nonzero cx_zero jmp foo cx_nonzero 9 15 10 Floating Point All 80387 floating point types except packed BCD are supported BCD support may be added without much difficulty These data types are 16 32 and 64 bit integers and single 32 bit double 64 bit and extended 80 bit precision floating point Each supported type has an instruction mnemonic suffix and a constructor associated with it Instruction mnemonic suffixes specify the operand s data type Constructors build these data types into memory H e Floating point constructors are float or single double and tfloat for 32 64 and 80 bit formats These correspond to instruction mnemonic suffixes s T and t t stands for 80 bit ten byte real The 80387 only supports this format via the fldt load 80 bit real to stack top and fstpt store 80 bit real and pop stack instructions e Integer constructors are word Long or int and quad for the 16 32 and 64 bit integer formats The corresponding instruction mnemonic suffixes are s single T long and q quad As with the 80 bit real format the 64 bit q format is only present in the fildq load quad integer to stack top and fist
59. 04 which pushes the value 4 onto the stack decrementing esp by 2 pushw 4 154 Using as The same code in a 16 bit code section would generate the machine opcode bytes 6a 04 i e without the operand size prefix which is correct since the processor default operand size is assumed to be 16 bits in a 16 bit code section 9 15 16 AT amp T Syntax bugs The UnixWare assembler and probably other AT amp T derived ix86 Unix assemblers generate floating point instructions with reversed source and destination registers in certain cases Unfortunately gcc and possibly many other programs use this reversed syntax so we re stuck with it For example fsub jet jet 3 results in 4st 3 being updated to 4st st 3 rather than the expected 4st 3 jet This happens with all the non commutative arithmetic floating point operations with two register operands where the source register is Ast and the destination register is sti 9 15 17 Specifying CPU Architecture as may be told to assemble for a particular CPU sub architecture with the arch cpu type directive This directive enables a warning when gas detects an instruction that is not supported on the CPU specified The choices for cpu type are 18086 1186 1286 1386 1486 1586 i686 pentium pentiumpro pentiumii pentiumiii pentium4 prescott nocona core cor
60. 0x1f or 0x03 subopcode Subopcode to be used Valid values are from 0x09 0x3f How ever the correct value also depends on syntaxclass suffixclass Determines the kinds of suffixes to be allowed Valid values are SUFFIX NONE SUFFIX COND SUFFIX FLAG which indicates the absence or presence of conditional suffixes and flag setting by the extension instruc tion It is also possible to specify that an instruction sets the flags and is conditional by using SUFFIX CODE SUFFIX FLAG syntaxclass Determines the syntax class for the instruction It can have the following values SYNTAX 20P 2 Operand Instruction SYNTAX 30P 3 Operand Instruction In addition there could be modifiers for the syntax class as described below Syntax Class Modifiers are DPI MUST BE IMM Modifies syntax class SYNTAX 3OP specifying that the first operand of a three operand instruction must be an im mediate De the result is discarded OP1 MUST BE IMM is used by bitwise ORing it with SYNTAX 30OP as given in the example below This could usually be used to set the flags using specific instructions and not retain results DPI IMM IMPLIED Modifies syntax class SYN TAX 20P it specifies that there is an implied immediate destination operand which does not appear in the syntax For example if the source code contains an instruction like inst r1 r2 it really means that the first argument is an implied immediate that is the result is discarded Thi
61. 120 print insn syntax 185 303 print opcodes i ies eee rre ses 185 303 register prefix optional option M680x0 eee 176 SHPO LAK DERE 248 relax command line option MMIX 204 rename section oie a ee e eee eed vende 306 TENCSAS i sede E eed Tawa cease REY 248 lt short branch s EES 184 mier ECH EE 248 Se D else gui Ree RERO ocean ma eae 25 strict direct mode 0 ee eee 184 2ctarget align sagcaseia kp RAS RES 306 text section literals 306 traditional forimat e Rh 25 SSES fori rege nen UR I IE 306 underscore command line option CRIS 120 mai lg T LC ER 26 x32 Option EE 145 x32 option x86 64 ics EE as 145 xgate ramoffset cies 184 i option VAXZ IVMS cee eee eee ee 292 32addr command line option Alpha 84 pr eT 21 A options 1960 2 eee eee 159 B ulnsensbert eca EE 21 sAd iriser EE aE A 21 MAC ETT 21 EENEG 21 M EUER 21 BAIGOHio higg eret E E E E 254 AM a en aed out ete pc oen a E Pure 21 e EE EEN 21 S SDATO Lr Dee teed dete doe seta date de EE 254 BEER 254 SNS PAP CAMA ederi hinen nerenin REM ORE MES 254 sparclet i ee emis See SE AE 254 sparclite o e eg kh es pg Y eae 254 c sparcviS ced gna neg ae ie e bres RERBPS 254 Using as C SparCwi82 ida ue e nb ec eae wes 254 C SparcviS3
62. 137 HPPA EEN 137 HPPA only directives sees eee eee 138 hword directives ce rr err EE EI EE 5T I 1910 SUppOtTU EE 142 1386 16 bit code iiic dere eed eet 153 1386 arch directive e de AE sundaes 154 340 1386 att syntax pseudo op 147 1386 conversion Instruchiong s e e 148 1386 floating Point AEN e mE SERES 152 i386 immediate operands uussus 147 1386 instruction naming 008 148 1386 instruction Drees 150 1386 intel syntax pseudo op 147 1386 jump optimization sss 151 1386 jump call return eco 147 1386 jump call operands usseseeeeeeeen 147 1386 line comment character 148 1386 line separator ecce cage ee itii 148 1386 memory references ccrerrcrrsre 150 1386 mnemonic compatibility 149 1386 mul imul Instruction 155 1980 ODUIOTIS seus eI ERREUR EDS RENREPE MR 145 1386 register operands 147 1980 LEPISLETS eo cete rec ERI eb eee See 149 1986 Sections da red RR p Save sk E RE RES 148 1986 size SUMRES uere rr ER ree ER p Eas 147 1386 source destination operands 147 1380 SUPPOrts a SERA AE 145 1386 syntax compatibility 147 180386 suppott i ea 9 cdots ROESER ene dened 145 i860 line comment character 158 i860 line separator s susrsrerererrrnnnns 158 i860 machine directives 0 eee ee 156 1860 OpCcOd S cs2 eu EES EREN EEN NEEN dE EE
63. 14 ESA 390 Dependent Features 142 9 14 1 Notes iie ee adda deny a Roca dna 142 9 14 2 OptiONns ii oesce sexe NA EES NEE R d 142 9 I4 9 SE ae iie eco cr rv EP DRIED eerr ERPRENDER A AEG 142 9 14 4 Floating Port scenic RR EERTRIA tae REED E 143 9 14 5 ESA 390 Assembler Directives sseseseesees 143 9 14 6 Opcodes iesiuii e eed oe de bre aT P Ree Rd 144 9 15 80386 Dependent Features 0 00 e eects 145 9 15 1 OptiOlis 223 pisent ae IP ER RP RR ERE 145 9 15 2 x86 specific Directives eese 147 9 15 3 i386 Syntactical Considerations 0000s 147 9 15 3 1 AT amp T Syntax versus Intel Syntax 147 9 15 3 2 Special Characters 00 cc ccc eee ences 148 vii viii 9 15 4 Instruction Naming e 148 9 15 5 AT amp T Mnemonic versus Intel Mnemonic 149 9 15 60 gt Register Naming idees brace RETRO REA E etas 149 9 15 7 Instruction Preise 150 9 15 8 Memory References 0 cece eee eee 150 9 15 9 Handling of Jump Instructions 000 151 9 15 10 Floating Point tenets asenna oct pee dee nis 152 9 15 11 Intel s MMX and AMD s 3DNow SIMD Operations 152 9 15 12 AMD s Lightweight Profiling Instructions 153 9 15 13 Bit Manipulation Instruction 153 9 15 14 AMD s Trailing Bit Manipulation Instructions 153 9 15 15 Writing 16 bit Code 153 9 15 16 AT amp T Syntax bugs 154 9 15 17 Specifying CPU Architecture 154 9
64. 153 TBM Xx 86 04 ue Lose beret nee EUR LeU p E urs 153 tdaoff pseudo op VRD0 301 temporary symbol name 40 text and data sections joining 25 text dif oblVe lau epe ew rr HIE 75 text Secblon ege nra ERE HR RR EN DEM 34 tfloat directive i386 ee eee eee 152 tfloat directive x86 64 0000 152 Thumb suppot ene d deg 82 95 TIC54X builtin math functions 265 TIC54X line comment character 273 TIC54X line separater 273 TIC54X machine directives 0 267 TIC54X memory mapped registers 273 CES Options cere tr annei REED 264 TIC54X subsym baultuns s s isricinssi cessera 272 IC5AX SUDDOEU scher emm heen eee mts 264 TIC54X specific macros 0 eee eee eee 272 TIC6X big endian output sssresreseuue 274 TIC6X line comment character 274 TIC6X line separator ee eee eee 274 TIC6X little endian ott 274 TIC6X machine directives 00 275 349 TICOX Option nu het Rr n Rr 274 TICGX Oe EE 274 TILE Gx machine directives 280 TTILE Gx modiflers a oii is erre RR beeen 278 TILE Gx opcode names 0002 eee 277 TILE Gx register names rrun 207 TILE Gx SUDpOobt s ie Seesaw a e i 200 NIE Syntax atte teenie ages ens 207 TILEPro machine drechen 285 TILEPro modiiers eu siere meh ceed 283 TILEPro opcode names ssesssesese 282 TILEPro register na
65. 167 Options for Meta east ba ee Ne dE es 190 options for MSP430 none Eu options for Niog IL EELER NN ee 215 options for PDP 1L enters 219 options for Dowerbti 224 options for s 00 eee eee 231 options for SCORE 0 0 eee eee eee 246 options for DARC 254 options for TICE 274 options for V850 none 0005 295 options for VAX VMS o ssuressssseerrrr 291 options for 90 04 145 options for Z80 casses cae Sariro eee nat 286 options all versions of assembler 21 options command ne 17 Options ORIS oiesecreR IRE Rer E PIRE RAD 120 Options DION ioa obe bro rose at dtes 125 Options D30V tasers ri A bLLIRSA PIC TREES 129 options Epiphany NEESS eee eene 133 options H8 300 erezett ele Dee eere eg 134 options IERENS 159 options IP2K usce eere rrr entm 166 options EE 170 Options MISE sacs caus ain trn DR Uere ERR 172 345 options MO80x0 nerit n trt En die 176 options M68HC11 cic ber RR RR E 184 options MMIX EEN 204 options PI EEN 223 Options LBs sisse t e oe eR eI ERI AES 227 Options E Lco ise I REIP RIEF RET 228 Options DE ize iere ern iere pir 248 options Sp ee pate EELER NUES 251 EI EUREN EE 264 options SCGATb c cece eee eee 303 options 28000 289 org directive cis yeni crane me eon eaeeceniens 65 other attribute of a out symbol 42 OS 18 P p2align directive c les le nee eee ewes 66 p2alignl
66. 24 r24 general register 25 r25 general register 26 r26 general register 27 r27 general register 28 r28 general register 29 r29 general register 30 r30 ep general register 31 r31 Ip system register 0 eipc system register 1 eipsw Using as Chapter 9 Machine Dependent Features 299 system register 2 fepc system register 3 fepsw system register 4 ecr system register 5 psw system register 16 ctpc system register 17 ctpsw system register 18 dbpc system register 19 dbpsw system register 20 ctbp 9 49 3 Floating Point The V850 family uses IEEE floating point numbers 9 49 4 V850 Machine Directives offset expression Moves the offset into the current section to the specified amount Section name type v850 v850e v850e1 v850e2 This is an extension to the standard section directive It sets the current section to be type and creates an alias for this section called name Specifies that the assembled code should be marked as being targeted at the V850 processor This allows the linker to detect attempts to link such code with code assembled for other processors Specifies that the assembled code should be marked as being targeted at the V850E processor This allows the linker to detect attempts to link such code with code assembled for other processors Specifies that the assembled code should be marked as being targeted
67. 30 2 Syntax 9 30 2 1 Special Characters 6 4t is the line comment character is the line separator character 9 30 3 Nios II Machine Relocations hiadj expression Extract the upper 16 bits of expression and add one if the 15th bit is set The value of Zhiadj expression is Cexpression gt gt 16 amp Oxffff expression gt gt 15 amp 0x01 The Zhiadj relocation is intended to be used with the addi 1d or st instruc tions along with a 1o in order to load a 32 bit constant movhi r2 hiadj symbol addi r2 r2 lo symbol Ahi Cexpression Extract the upper 16 bits of expression Alo Cexpression Extract the lower 16 bits of expression Agprel expression Subtract the value of the symbol _gp from expression The intention of the 4gpre1 relocation is to have a fast small area of memory which only takes a 16 bit immediate to access Section sdata fastint int 123 216 Using as Section text ldw r4 gprel fastint gp call expression got expression gotoff expression gotoff lo expression gotoff hiadj expression Atls_gd expression tls_ie expression 4tls le expression 4tls ldm expression Atlas ldo expression These relocations support the ABI for Linux Systems documented in the Nios II Processor Reference Handbook 9 30 4 Nios II Machine Directives align expression expression This is the generic align directive however this aligns to a power of
68. 47 overflow check movk x0 abs_gi_nc foo bits 16 31 no overflow check movk x0 abs_gO_nc foo bits 0 15 no overflow check Relocations for ADRP and ADD LDR or STR instructions can be generated by prefixing the label with pg_hi21 and 1012 respectively For example to use 33 bit 4GB pc relative addressing to load the address of foo into x0 adrp x0 pg_hi21 foo add x0 x0 1012 foo Or to load the value of foo into x0 adrp x0 pg_hi21 foo ldr x0 xO 1012 foo Note that pg_hi21 is optional adrp x0 foo is equivalent to adrp x0 pg_hi21 foo Chapter 9 Machine Dependent Features 83 9 1 3 Floating Point The AArch64 architecture uses IEEE floating point numbers 9 1 4 AArch64 Machine Directives bss This directive switches to the bss section ltorg This directive causes the current contents of the literal pool to be dumped into the current section which is assumed to be the text section at the current location aligned to a word boundary GAS maintains a separate literal pool for each section and each sub section The 1torg directive will only affect the literal pool of the current section and sub section At the end of assembly all remaining un empty literal pools will automatically be dumped Note older versions of GAS would dump the current literal pool any time a section change occurred This is no longer done since it prevents accurate contro
69. 9 23 6 2 Special Characters 0 00 ccc eee eens 183 9 24 M68HC11 and M68HC12 Dependent Features 184 9 24 1 M68HC11 and M68HC12 Omtions 184 0 2 9 Sy Mba me eee hace ds ceca ert or E eo OGG ML ELE 185 9 24 3 Symbolic Operand Modterg 000 187 9 24 4 Assembler Directives 2000 e cece ences 187 9 24 5 Floating Porn uui iet Dex CR ce rete pue 188 9 24 6 Opeodesc siccis dere Ee pp RODCRR UR SE VADE 188 9 24 6 1 Branch Improvement eeen cece eee eee 188 9 25 Meta Dependent beatures 00 cece eee nee eee 190 9 25 1 OptlOns ia2ccceeeeeiiae ded ad one ANER SE AN 190 9 25 2 SynhlaX eebe e ada eR oido dior e Pr odas 190 9 25 2 1 Special Characters 0 0 ccc eee eee ees 190 9 25 2 2 Register Name 190 9 26 MicroBlaze Dependent Features 191 9 20 1 DirectlVeSesseeec cene SEENEN E ER 191 9 26 2 Syntax for the Microb laze 2c eee eee eee 191 9 26 2 1 Special Character 191 9 27 MIPS Dependent Features 0 0 0 c cece eee eee 192 9 27 1 Assembler option 192 9 27 2 High level assembly macros 0 0 cee eee eee 197 9 27 3 Directives to override the size of symbols 198 9 27 4 Controlling the use of small data accesses 199 9 27 5 Directives to override the ISA eye 199 9 27 6 Directives to control code generation 200 9 27 7 Directives for extending MIPS 16 bit instructions 200 9 27 8 Directive to mark data as an instruc
70. 9 42 2 TIC54X 272 Using as Block page 264 alignment flag indicates whether the section should be longword aligned var sym sym n Define a subsym to be a local variable within a macro See See Section 9 42 10 TIC54X Macros page 272 version version Set which processor to build instructions for Though the following values are accepted the op is ignored 541 542 543 545 545LP 546LP 548 549 9 42 10 Macros Macros do not require explicit dereferencing of arguments i e NARG During macro expansion the macro parameters are converted to subsyms If the number of arguments passed the macro invocation exceeds the number of parameters defined the last parameter is assigned the string equivalent of all remaining arguments If fewer arguments are given than parameters the missing parameters are assigned empty strings To include a comma in an argument you must enclose the argument in quotes The following built in subsym functions allow examination of the string value of subsyms or ordinary strings The arguments are strings unless otherwise indicated subsyms passed as args will be replaced by the strings they represent symlen str Returns the length of str symcmp stri str2 Returns 0 if str str2 non zero otherwise firstch str ch Returns index of the first occurrence of character constant ch in str 1astch str ch Returns index of the last occurrence of character constant ch in str
71. CPU This option specifies a processor to optimize for When used in conjunction with the march option only instructions of the processor specified by the march option will be generated Valid CPU values are identical to the processor list of march CPU msse2avx This option specifies that the assembler should encode SSE instructions with VEX prefix msse check none msse check warning msse check error These options control if the assembler should check SSE instructions msse check none will make the assembler not to check SSE instructions which is the default msse check warning wil make the assembler issue a warning for any SSE instruction msse check error will make the assembler issue an error for any SSE instruction mavxscalar 128 mavxscalar 256 These options control how the assembler should encode scalar AVX instruc tions mavxscalar 128 will encode scalar AVX instructions with 128bit vector length which is the default mavxscalar 256 will encode scalar AVX instructions with 256bit vector length mevexlig 128 mevexlig 256 mevexlig 512 These options control how the assembler should encode length ignored LIG EVEX instructions mevexlig 128 will encode LIG EVEX instructions with 128bit vector length which is the default mevexlig 256 and mevexlig 512 will encode LIG EVEX instructions with 256bit and 512bit vector length respectively mevexwi
72. Chapter 9 Machine Dependent Features 207 Similarly for special registers local and global symbols can be used Also symbols equated from numbers and constant expressions are allowed in place of a special reg ister except when either of the options no predefined syms and fixed special register names are specified Then only the special register names above are allowed for the instructions having a special register operand GET and PUT 9 28 3 4 Assembler Directives LOC LOCAL IS GREG The LOC directive sets the current location to the value of the operand field which may include changing sections If the operand is a constant the section is set to either data if the value is 0x2000000000000000 or larger else it is set to text Within a section the current location may only be changed to monotonically higher addresses A LOC expression must be a previously defined symbol or a pure constant An example which sets the label prev to the current location and updates the current location to eight bytes forward prev LOC 8 When a LOC has a constant as its operand a symbol __ MMIX start text or __ MMIX start data is defined depending on the address as mentioned above Each such symbol is interpreted as special by the linker locating the section at that address Note that if multiple files are linked the first object file with that section will be mapped to that address not necessarily the file with the LOC defin
73. DA4 B4 cij lt m gt R1 12 14 cgij lt m gt R1 I2 IA4 crt amp m RLR2 cert lt m gt RLR2 cit lt m gt R12 cgit lt m gt R1 I2 clrb lt m gt R1 R2 D4 B4 clgrb lt m gt R1 R2 D4 B4 clrjem R1 R2 14 clgerj lt m gt R1 R2 14 clib lt m gt R1 12 D4 B4 clgib lt m gt R1 12 D4 B4 Chapter 9 Machine Dependent Features clj R1 12 M3 14 clgij R1 12 M3 14 chrt R1 R2 M3 clert R1 R2 M3 clfit R1 I2 M3 clgit R1 I2 M3 241 clij lt m gt R1 I2 I4 clgij lt m gt R1 12 4 clrt lt m gt R1 R2 clert lt m gt R1 R2 clfit lt m gt R1 12 clgit m R1 I2 In the mnemonic for a compare and branch and compare and trap instruction the con dition code string m can be any of the following h jump on A high nle jump on not low or equal l jump on A low nhe jump on not high or equal ne jump on A not equal B Ih jump on low or high e jump on A equal B nlh jump on not low or high nl jump on A not low he jump on high or equal nh jump on A not high le jump on low or equal 9 37 3 6 Instruction Operand Modifier If a symbol modifier is attached to a symbol in an expression for an instruction operand field the symbol term is replaced with a reference to an object in the global offset table GOT or the procedure linkage table PLT The following expressions are allowed symbol modifier constant symbol modifier label constant and symbol modifier label constant The term symbol is t
74. Features 193 controls the size of general purpose registers and mfp32 controls the size of floating point registers The set gp 32 and set fp 32 directives allow the size of registers to be changed for parts of an object The default value is restored by set gp default and set fp default On some MIPS variants there is a 32 bit mode flag when this flag is set 64 bit instructions generate a trap Also some 32 bit OSes only save the 32 bit registers on a context switch so it is essential never to use the 64 bit registers mgp64 mfp64 Assume that 64 bit registers are available This is provided in the interests of symmetry with mgp32 and mfp32 The set gp 64 and set fp 64 directives allow the size of registers to be changed for parts of an object The default value is restored by set gp default and set fp default mipsi6 no mips16 Generate code for the MIPS 16 processor This is equivalent to putting set mipsi6 at the start of the assembly file no mips16 turns off this option mmicromips mno micromips Generate code for the microMIPS processor This is equivalent to putting set micromips at the start of the assembly file mno micromips turns off this option This is equivalent to putting set nomicromips at the start of the assembly file msmartmips mno smartmips Enables the Smart MIPS extensions to the MIPS32 instruction set which pro vides a number of new instructions wh
75. Keith Knowles at the Open Software Foundation wrote the original MIPS back end tc mips c tc mips h and contributed Rose format support which hasn t been merged in yet Ralph Campbell worked with the MIPS code to support a out format Support for the Zilog Z8k and Renesas H8 300 processors tc z8k tc h8300 and IEEE 695 object file format obj ieee was written by Steve Chamberlain of Cygnus Support Steve also modified the COFF back end to use BFD for some low level operations for use with the H8 300 and AMD 29k targets John Gilmore built the AMD 29000 support added include support and simplified the configuration of which versions accept which directives He updated the 68k machine description so that Motorola s opcodes always produced fixed size instructions e g jsr while synthetic instructions remained shrinkable jbsr John fixed many bugs including true tested cross compilation support and one bug in relaxation that took a week and required the proverbial one bit fix Ian Lance Taylor of Cygnus Support merged the Motorola and MIT syntax for the 68k completed support for some COFF targets 68k 1386 SVR3 and SCO Unix added support for MIPS ECOFF and ELF targets wrote the initial RS 6000 and PowerPC assembler and made a few other minor patches 1 Any more details 320 Using as Steve Chamberlain made GAS able to generate listings Hewlett Packard contributed support for the HP9000 300 Jeff Law wr
76. Labels A label is written as a symbol immediately followed by a colon The symbol then represents the current value of the active location counter and is for example a suitable instruction operand You are warned if you use the same symbol to represent two different locations the first definition overrides any other definitions On the HPPA the usual form for a label need not be immediately followed by a colon but instead must start in column zero Only one label may be defined on a single line To work around this the HPPA version of as also provides a special directive label for defining labels more flexibly 5 2 Giving Symbols Other Values A symbol can be given an arbitrary value by writing a symbol followed by an equals sign followed by an expression see Chapter 6 Expressions page 43 This is equivalent to using the set directive See Section 7 100 set page 72 In the same way using a double equals sign here represents an equivalent of the eqv directive See Section 7 47 eqv page 54 Blackfin does not support symbol assignment with 5 3 Symbol Names Symbol names begin with a letter or with one of On most machines you can also use in symbol names exceptions are noted in Chapter 9 Machine Dependencies page 81 That character may be followed by any string of digits letters dollar signs unless otherwise noted for a particular target machine and underscores Ca
77. Lei ERE RE 217 Nios IL options dE EE EE 215 Nios II support 215 Nios SUppOrt cc0c20io ceceeeatacewasadenines 215 no absolute literals directive 314 no longcalls directe i624 ee e seeds 312 no relax command line option Nios II 215 no schedule directive 00 0 eee 312 no transform directe 312 nolist directive cece eee eee eee 65 nolist directive TTIORAN 269 NOP pseudo op ARM 104 notes for Alpha 84 NS32K line comment character 218 NS32K line separator esee 218 null terminated strings sssscrrerreresees 48 number constanis 2 exm Re neia ta 30 number of macros executed sssuussuu 64 numbered subsections sssssrerrrrrrru ru 35 numbers 16 bE dee EES 57 numeric VAIUES NEE EIERE NEE meee ean nia 43 nword directive SPARC osnnsnnnnnnnnnne 263 O object attributes ned err tr DR EEN T9 object file iere dnne sA Rdn echt dei 18 Object file format cessee ENEE errores 17 object file name 25 object file after errors i ccccsreririrriscarsinsas 26 obsolescent directives 2 cece eee eee 78 octa GiTeChiVE ss a ies rx eter eR EE na 65 octal character code Dddd 29 octal integers cis Steg raw bre peche pr 30 offset directiv iles Er per sacs 65 offset directive VR 299 opcode mnemonics MAX 293 opcode names TIk Os 277 opcode names TILEPro 282 opcode names Xtensa
78. R2 b m D2 X2 B2 jam 12 jg lt m gt I2 In the mnemonic for a branch instruction the condition code string m can be any of the following O nhe Ih ne nz nlh he nl nm le nh jump on overflow if ones jump on A high jump on plus jump on not low or equal jump on A low jump on minus jump on not high or equal jump on low or high jump on A not equal B jump on not zero if not zeros jump on A equal B jump on zero if zeroes jump on not low or high jump on high or equal jump on A not low jump on not minus if not mixed jump on low or equal jump on A not high 240 np no jump on not plus jump on not overflow if not ones Using as For the compare and branch and compare and trap instructions there are 12 condition code strings that can be used as part of the mnemonic in place of a mask operand in the instruction format instruction crb cgrb crj cgrj cib cgib cij cgi crt cert cit cgit clrb R1 R2 M3 D4 B4 R1 R2 M3 D4 B4 R1 R2 M3 4 R1 R2 M3 14 R1 12 M3 D4 B4 R1 12 M3 D4 B4 R1 12 M3 14 R1 12 M3 14 R1 R2 M3 R1 R2 M3 R1 I2 M3 R1 I2 M3 R1 R2 M3 D4 B4 clgrb R1 R2 M3 D4 B4 clrj clgrj clib R1 R2 M3 14 R1 R2 M3 14 R1 12 M3 D4 B4 clgib R1 I2 M3 D4 B4 short form crbem R1 R2 D4 B4 cgrb lt m gt R1 R2 D4 B4 crj lt m gt R1 R2 14 cerj lt m gt R1 R2 14 cib lt m gt RLI2 D4 B4 cgib lt m gt RLI2
79. RI 227 9 35 4 1 Special Character 227 9 36 RX Dependent Hoatures 0600s 228 9 36 1 RX Opflons de ere weenie RENE EE 228 9 36 2 Symbolic Operand Mode 229 9 36 3 Assembler Directives 00 00 cece eee eee eee 229 9 36 4 Floating Point eee e eR 230 9 36 5 Syntax for the bRi nee ee 230 9 36 5 1 Special Characters 0 0 cece eee eens 230 9 37 IBM S 390 Dependent Features 231 GE eg en 231 9 37 2 Special Characters SEENEN NEESS ENEE d NN 231 9 97 9 Instruction Syntax oce eue btt epi de wines ecards 231 9 87 8 1 Register naming cee eee eee eee 232 9 37 3 2 Instruction Munemontes 0 0 232 9 37 3 3 Instruction Operands 0 eee ee 233 9 37 3 4 Instruction Format 235 9 37 3 5 Instruction Aliases 0 ccc cece e eee eens 238 9 37 3 6 Instruction Operand Modifier 241 9 37 3 7 Instruction Marker 0 0 00 cece eee eee ees 243 9 37 3 8 Literal Pool Entries 0 cc cece eee eee 243 9 37 4 Assembler Directives 0 c cece sees 244 9 37 5 Floating Porti eie E pe aeter bp eg 245 9 38 SCORE Dependent Features 0 0 0 cece cece sese 246 9 38 L Optil ss weeds ure er Rt Rr RDUM ene ERb MERE qe 246 9 38 2 SCORE Assembler Directive 246 9 38 3 SCORE Syntax ike RI cease ENEE ORE REPOS 247 9 38 3 1 Special Characters 0 0 ccc eee eee eens 247 9 39 Renesas SuperH SH Dependent Features 248 9 39 1 Options seii RRRERER A OPERE A Pea e
80. STT_ lt TYPE_IN_UPPER_CASE gt type lt name gt lt type gt type lt name gt lt type gt type lt name gt lt type gt type lt name gt lt type gt The types supported are STT_FUNC function Mark the symbol as being a function name STT_GNU_IFUNC gnu_indirect_function Mark the symbol as an indirect function when evaluated during reloc processing This is only supported on assemblers targeting GNU systems STT_OBJECT object Mark the symbol as being a data object STT_TLS tls_object Mark the symbol as being a thead local data object STT_COMMON common Mark the symbol as being a common data object STT_NOTYPE notype Does not mark the symbol in any way It is supported just for completeness Chapter 7 Assembler Directives 77 gnu_unique_object Marks the symbol as being a globally unique data object The dynamic linker will make sure that in the entire process there is just one symbol with this name and type in use This is only supported on assemblers targeting GNU systems Note Some targets support extra types in addition to those listed above 7 116 ulebi28 expressions uleb128 stands for unsigned little endian base 128 This is a compact variable length rep resentation of numbers used by the DWARF symbolic debugging format See Section 7 105 sleb128 page 72 7 117 val addr This directive permitted only within def endef pairs records the address addr as the value attribute o
81. Section 7 99 section page 69 If you do not use any directives that place output in the text or data sections these sections still exist but are empty When as generates SOM or ELF output for the HPPA as can also generate what ever other named sections you specify using the space and subspace directives See HP9000 Series 800 Assembly Language Reference Manual HP 92432 90001 for details on the space and subspace assembler directives Additionally as uses different names for the standard text data and bss sections when generating SOM output Program text is placed into the CODE section data into DATA and BSS into BSS Within the object file the text section starts at address 0 the data section follows and the bss section follows the data section When generating either SOM or ELF output files on the HPPA the text section starts at address O the data section at address 0x4000000 and the bss section follows the data section To let 1d know which data changes when the sections are relocated and how to change that data as also writes to the object file details of the relocation needed To perform relocation 1d must know each time an address in the object file is mentioned e Where in the object file is the beginning of this reference to an address e How long in bytes is this reference e Which section does the address refer to What is the numeric value of address
82. Sections and Relocation 35 absolute section Address 0 of this section is always relocated to runtime address 0 This is useful if you want to refer to an address that 1d must not change when relocating In this sense we speak of absolute addresses being unrelocatable they do not change during relocation undefined section This section is a catch all for address references to objects not in the preceding sections An idealized example of three relocatable sections follows The example uses the tradi tional section names text and data Memory addresses are on the horizontal axis Partial program 1 text data bss ttttt dddd 00 Partial program 2 text data bss TTT DDDD 000 linked program text data bss TIT ttttt dddd DDDD 00000 addresses 0 4 3 Assembler Internal Sections These sections are meant only for the internal use of as They have no meaning at run time You do not really need to know about these sections for most purposes but they can be mentioned in as warning messages so it might be helpful to have an idea of their meanings to as These sections are used to permit the value of every expression in your assembly language program to be a section relative address ASSEMBLER INTERNAL LOGIC ERROR An internal assembler logic error has been found This means there is a bug in the assembler expr section The assembler stores complex expr
83. SunOS v9 assembler These options are equiva lent to Av8plus Av8plusa Av8plusb Av8plusc Av8plusd Av8plusv Av9 Av9a Av9b Av9c Av9d Av9v Asparc Asparcvis Asparcvis2 Asparcfmaf Asparcima Asparcvis3 and Asparcvis3r respectively bump Warn whenever it is necessary to switch to another level If an architecture level is explicitly requested GAS will not issue warnings until that level is reached and will then bump the level as required except between incompatible levels 32 64 Select the word size either 32 bits or 64 bits These options are only available with the ELF object file format and require that the necessary BFD support has been included 9 41 2 Enforcing aligned data SPARC GAS normally permits data to be misaligned For example it permits the Long pseudo op to be used on a byte boundary However the native SunOS assemblers issue an error when they see misaligned data You can use the enforce aligned data option to make SPARC GAS also issue an error about misaligned data just as the SunOS assemblers do The enforce aligned data option is not the default because gcc issues misaligned data pseudo ops when it initializes certain packed data structures structures defined using the packed attribute You may have to assemble with GAS in order to initialize packed data structures in your own code 9 41 3 Sparc Syntax The assembler syntax closely follows The Sparc Architecture Manu
84. TIC5AX 272 tens EPA RE gend EM Rs pel tat pags 105 tan math builtin TIC54X Lususuu 267 tanh math builtin TIC54X 267 trunc math builtin TIC54X 267 pc beeeE te 83 329 EEN 229 puo Em 229 Apidreg sais xiccee e er e eerie POLES TEE 229 t option MAXZINVMS eee eee eee ee 292 SP Eege iiU 17 es32 option 1986 hex saetep nes RR ER REESE 145 32 option HDD 145 2264 option 1380 2 2t REPRU Re ig 145 64 option x86 64 0 eee eee eee eee 145 absolute literals eere en 306 allow reg prefix c sik gs edes 248 alt rn te 2 0 0p Deel D IP E 21 base size default 16 ssusuu r base size default 32 0 Lee e ga sient aimee dase inde REPULSA sed anes 248 bitwise or option M680x0 176 disp size default 16 177 disp size default 32 177 divide option i886 0008 145 ie EE 248 emulation crisaout command line option CRIB A secuti ne Sey tul Une eee RR DA 120 emulation criself command line option CRIB vit tents tea URP tid cate aed ees 120 enforce aligned data 255 f tal warningsS ssi gsee IRRe E 26 eefdpiC ii siesdgged c e EE EE 248 fix v4bx command line option ARM 97 fixed special register names command line option MM
85. This directive is only supported for PE targets syntax unified divided This directive sets the Instruction Set Syntax as described in the Section 9 4 2 1 ARM Instruction Set page 98 section thumb This performs the same action as code 16 thumb func This directive specifies that the following symbol is the name of a Thumb en coded function This information is necessary in order to allow the assembler and linker to generate correct code for interworking between Arm and Thumb instructions and should be used even if interworking is not going to be per formed The presence of this directive also implies thumb This directive is not neccessary when generating EABI objects On these targets the encoding is implicit when generating Thumb code thumb set This performs the equivalent of a set directive in that it creates a symbol which is an alias for another symbol possibly not yet defined This directive also has the added property in that it marks the aliased symbol as being a thumb function entry point in the same way that the thumb func directive does tlsdescseq tls variable This directive is used to annotate parts of an inlined TLS descriptor trampoline Normally the trampoline is provided by the linker and this directive is not needed unreq alias name This undefines a register alias which was previously defined using the req dn Or qn directives For example foo req rO unreq foo An error occurs if
86. a logical line number directive see Section 3 3 Comments page 27 or a preprocessor control command see Section 3 1 Preprocessing page 27 The character can be used to separate statements on the same line 172 Using as 9 22 M32R Dependent Features 9 22 1 M32R Options The Renease M32R version of as has a few machine dependent options m32rx as can assemble code for several different members of the Renesas M32R fam ily Normally the default is to assemble code for the M32R microprocessor This option may be used to change the default to the M32RX microprocessor which adds some more instructions to the basic M32R instruction set and some additional parameters to some of the original instructions m32r2 This option changes the target processor to the M32R2 microprocessor m32r This option can be used to restore the assembler s default behaviour of assem bling for the M32R microprocessor This can be useful if the default has been changed by a previous command line option little This option tells the assembler to produce little endian code and data The default is dependent upon how the toolchain was configured EL This is a synonym for little big This option tells the assembler to produce big endian code and data EB This is a synonum for big KPIC This option specifies that the output of the assembler should be marked as position independent code PIC parallel This option tells the assembler
87. abs r2 r3 gt abs r4 r5 Execute these sequentially The instruction on the right is in the right container and is executed second abs r2 r3 lt abs r4 r5 Execute these reverse sequentially The instruction on the right is in the right container and is executed first abs r2 r3 abs r4 r5 Execute these in parallel ldw r2 r3 r4 mulx r6 r8 r9 Two line format Execute these in parallel mulx a0 r8 r9 stw r2 0 r3 r4 Two line format Execute these sequentially unless 0 option is used If the Q option is used the assembler will determine if the instructions could be done in parallel the above two instructions can be done in parallel and if so emit them as parallel instructions The assembler will put them in the proper containers In the above example the assembler will put the stw instruction in left container and the mulx instruction in the right container H stw r2 0 r3 r4 gt mulx a0 r8 r9 Two line format Execute the stw instruction followed by the mulx instruc tion sequentially The first instruction goes in the left container and the second instruction goes into right container The assembler will give an error if the machine ordering constraints are violated stw r2 0 r3 r4 lt mulx a0 r8 r9 Same as previous example except that the mulx instruction is executed before the stw instruction Since has no special meaning you may use it in symb
88. address 0x12 in the memory space and which is only writable extCondCode suffix value The condition codes on the ARCtangent A4 are extensible and can be specified by means of this assembler directive They are specified by the suffix and the value for the condition code They can be used to specify extra condition codes with any values For example extCondCode is_busy 0x14 add is busy ri1 r2 r3 bis busy main extCoreRegister name regnum mode shortcut Specifies an extension core register name for the application This allows a register name with a valid regnum between 0 and 60 with the following as valid values for mode r readonly w write only r w read or write The other parameter gives a description of the register having a shortcut in the pipeline The valid values are can_shortcut cannot_shortcut For example extCoreRegister mlo 57 r can_shortcut This defines an extension core register mlo with the value 57 which can shortcut the pipeline extInstruction name opcode subopcode suffixclass syntaxclass The ARCtangent A4 allows the user to specify extension instructions The extension instructions are not macros The assembler creates encodings for use Chapter 9 Machine Dependent Features 93 of these instructions according to the specification by the user The parameters are name Name of the extension instruction opcode Opcode to be used Bits 27 31 in the encoding Valid values 0x10
89. and 8 respectively 9 16 4 1860 Opcodes All of the Intel i860XR and 1860XP machine instructions are supported Please see either i860 Microprocessor Programmer s Reference Manual or i860 Microprocessor Architecture for more information 9 16 4 1 Other instruction support pseudo instructions For compatibility with some other i860 assemblers a number of pseudo instructions are supported While these are supported they are a very undesirable feature that should be avoided in particular when they result in an expansion to multiple actual i860 instructions Below are the pseudo instructions that result in expansions e Load large immediate into general register The pseudo instruction mov imm rn where the immediate does not fit within a signed 16 bit field will be expanded into orh large_imm h r0 rn or large_imm 1 rn rn e Load store with relocatable address expression For example the pseudo instruction 1d b addr_exp rx Arn will be expanded into orh addr_exp ha rx 7 r31 1d 1 addr_exp 1 r31 rn The analogous expansions apply to 1d x st x fld x pfld x fst x and pst x as well e Signed large immediate with add subtract If any of the arithmetic operations adds addu subs subu are used with an im mediate larger than 16 bits signed then they will be expanded For instance the pseudo instruction adds large_imm rx rn expands to orh large_imm h r0 r31 or large_imm 1 r31 r31 adds r31 rx rn
90. and the branch Whether as gives an error or expands the instruction depends on two choices you can make whether you use the no relax option and whether you use a Compare and Branch instruction or a Compare and Jump instruction The Jump instructions are always expanded if necessary the Branch instructions are expanded when necessary un less you specify no relax in which case as gives an error instead These are the Compare and Branch instructions their Jump variants and the instruc tion pairs they may expand into Compare and Branch Jump Expanded to bbc chkbit bno bbs chkbit bo cmpibe cmpije cmpi be cmpibg cmpijg cmpi bg cmpibge cmpijge cmpi bge cmpibl cmpijl cmpi bl cmpible cmpijle cmpi ble cmpibno cmpijno cmpi bno cmpibne cmpijne cmpi bne cmpibo cmpijo cmpi bo cmpobe cmpoje cmpo be cmpobg cmpojg cmpo bg cmpobge cmpojge cmpo bge cmpobl cmpojl cmpo bl cmpoble cmpojle cmpo ble cmpobne cmpojne cmpo bne 162 Using as 9 17 5 Syntax for the i960 9 17 5 1 Special Characters The presence of a on a line indicates the start of a comment that extends to the end of the current line If a 4 appears as the first character of a line the whole line is treated as a comment but in this case the line can also be a logical line number directive see Section 3 3 Comments page 27 or a preprocessor control command see Section 3 1 Preprocessing page 27 The
91. anything other than n64 9 27 4 Controlling the use of small data accesses It often takes several instructions to load the address of a symbol For example when addr is a 32 bit symbol the non PIC expansion of dla 4 addr is usually lui 4 hi addr daddiu 4 4 1o0 addr The sequence is much longer when addr is a 64 bit symbol See Section 9 27 3 Direc tives to override the size of symbols page 198 In order to cut down on this overhead most embedded MIPS systems set aside a 64 kilobyte small data area and guarantee that all data of size n and smaller will be placed in that area The limit n is passed to both the assembler and the linker using the command line option G n see Section 9 27 1 Assembler options page 192 Note that the same value of n must be used when linking and when assembling all input files to the link any inconsistency could cause a relocation overflow error The size of an object in the bes section is set by the comm or 1comm directive that defines it The size of an external object may be set with the extern directive For example extern sym 4 declares that the object at sym is 4 bytes in length while leaving sym otherwise undefined When no G option is given the default limit is 8 bytes The option G 0 prevents any data from being automatically classified as small It is also possible to mark specific objects as small by putting them in the specia
92. as 7 28 cfi_signal_frame Mark current function as signal trampoline 7 29 cfi_window_save SPARC register window has been saved 7 30 cfi escape expression Allows the user to add arbitrary bytes to the unwind info One might use this to add OS specific CFI opcodes or generic CFI opcodes that GAS does not yet support 7 31 cfi val encoded addr register encoding label The current value of register is label The value of label will be encoded in the output file according to encoding see the description of cf personality for details on this encoding The usefulness of equating a register to a fixed label is probably limited to the return address register Here it can be useful to mark a code segment that has only one return address which is reached by a direct branch and no copy of the return address exists in memory or another register 7 32 com symbol length comm declares a common symbol named symbol When linking a common symbol in one object file may be merged with a defined or common symbol of the same name in another object file If 1d does not see a definition for the symbol just one or more common symbols then it will allocate length bytes of uninitialized memory length must be an absolute expression If 1d sees multiple common symbols with the same name and they do not all have the same size it will allocate space using the largest size When using ELF or as a GNU extension PE the comm directive
93. at the V850E1 processor This allows the linker to detect attempts to link such code with code assembled for other processors Specifies that the assembled code should be marked as being targeted at the V850E2 processor This allows the linker to detect attempts to link such code with code assembled for other processors 300 v850e2v3 v850e2v4 v850e3v5 Using as Specifies that the assembled code should be marked as being targeted at the V850E2V3 processor This allows the linker to detect attempts to link such code with code assembled for other processors Specifies that the assembled code should be marked as being targeted at the V850E3V5 processor This allows the linker to detect attempts to link such code with code assembled for other processors Specifies that the assembled code should be marked as being targeted at the V850E3V5 processor This allows the linker to detect attempts to link such code with code assembled for other processors 9 49 5 Opcodes as implements all the standard V850 opcodes as also implements the following pseudo ops hid loQ hiQ Computes the higher 16 bits of the given expression and stores it into the immediate operand field of the given instruction For example mulhi hiO here there r5 r6 computes the difference between the address of labels here and there takes the upper 16 bits of this difference shifts it down 16 bits and then multiplies it by the lower 16 bi
94. attempt to shorten this call sequence if name is within a 22bit offset of the call Only valid if the mrelax command line switch has been enabled longjump name Indicates that the following sequence of instructions is a long jump to label name The linker will attempt to shorten this code sequence if name is within a 22bit offset of the jump Only valid if the mrelax command line switch has been enabled For information on the V850 instruction set see V850 Family 32 16 Bit single Chip Microcontroller Architecture Manual from NEC Ltd Chapter 9 Machine Dependent Features 303 9 50 XGATE Dependent Features 9 50 1 XGATE Options The Freescale XGATE version of as has a few machine dependent options mshort This option controls the ABI and indicates to use a 16 bit integer ABI It has no effect on the assembled instructions This is the default mlong This option controls the ABI and indicates to use a 32 bit integer ABI mshort double This option controls the ABI and indicates to use a 32 bit float ABI This is the default mlong double This option controls the ABI and indicates to use a 64 bit float ABI print insn syntax You can use the print insn syntax option to obtain the syntax description of the instruction when an error is detected print opcodes The print opcodes option prints the list of all the instructions with their syntax Once the list is printed as exits 9 50 2 Syntax In XGATE RISC s
95. be entered into the global offset table The value is a 32 bit index for that sym bol into the global offset table The name of the corresponding relocation is R_CRIS_32_GOT Example move d r0 extsym GOT r9 GOT16 Same as for GOT but the value is a 16 bit index into the global offset ta ble The corresponding relocation is R_CRIS_16_GOT Example move d r0 asymbol GOT16 r10 PLT This suffix is used for function symbols It causes a procedure linkage table an array of code stubs to be created at the time the shared object is created or linked against together with a global offset table entry The value is a pc relative offset to the corresponding stub code in the procedure linkage table This arrangement causes the run time symbol resolver to be called to look up and set the value of the symbol the first time the function is called at latest depending environment variables It is only safe to leave the symbol unresolved this way if all references are function calls The name of the relocation is R_CRIS_32_PLT_PCREL Example add d fnname PLT pc Chapter 9 Machine Dependent Features 123 PLTG Like PLT but the value is relative to the beginning of the global offset table The relocation is R_CRIS_32_PLT_GOTREL Example move d fnname PLTG r3 GOTPLT Similar to PLT but the value of the symbol is a 32 bit index into the global offset table This is somewhat of a mix between the ef
96. call to __tls_get_addr used to compute the address of the thread local storage variable whose descriptor was loaded with tlsgd N lituse tlsldm N Used with a register branch format instruction to indicate that the literal is the call to __tls_get_addr used to compute the address of the base of the thread local storage block for the current module The descriptor for the module must have been loaded with tlsldm N gpdisp N Used with 1dah and 1da to load the GP from the current address a la the 1dgp macro The source register for the 1dah instruction must contain the address of the 1dah instruction There must be exactly one 1da instruction paired with the 1dah instruction though it may appear anywhere in the instruction stream The immediate operands must be zero ber 26 foo ldah 29 0 26 gpdisp i lda 29 0 29 gpdisp i gprelhigh Used with an 1dah instruction to add the high 16 bits of a 32 bit displacement from the GP Chapter 9 Machine Dependent Features 87 gprellow gprel samegp It1sgd It1sgd N It1sldm It1sldm N gotdtprel Idtprelhi dtprello dtprel gottprel Itprelhi tprello tprel Used with any memory format instruction to add the low 16 bits of a 32 bit displacement from the GP Used with any memory format instruction to add a 16 bit displacement from the GP Used with any branch format instruction to skip the GP load at the target address T he referenced symbol must have the s
97. current address advancing r srrrrr 65 D D10V word moder 128 D10V addressing mode 127 DIOV floating point i cepere Rem 128 D10V line comment character 126 D10V opcode eummarg sosser irrncrirs ridire 128 DTOM optimization spice 9k dE EA 9 KUHN Eer Rn ef e e UR Zeen 125 IDIOV registefsS v2 v3 p E Ee AE ees 127 DIOV size modifiet8 Ibero per hne 125 D10V sub instruction ordering 126 D10V sub Anstruetions sese eeeeee 125 DION Supports eng E e ee 125 IDTON Syta kroone einen Ee bteqes re ure 125 D30V addressing mode 132 I930V floating point See were ke e b Rer 132 D30V Guarded Execution ssssss 131 D30V line comment character 129 D80N EE 9 D30V nops after 32 bit multiply 9 D30V opcode eummarg ccrisirsssroa esisin 132 D30V optimization e SN b RRRR t RR 9 DSOV Opting rere eret ete Rr REPRE 129 D30V regisbers ieirerire pe Sea nr ERR 131 D30V size modifierg cee eee sce geese mn 129 D30V sub instruction ordering 130 D30V sub instructions 00 eee ee 129 D30N support 2s eme nr RED RERPE Re naan 129 D30V sSynbiax ccncenecme peret gant enee SS 129 data alignment on DARC 255 data and text sections joining 25 data directive isle n e tap It DRE RR 53 data directive TIC54X ueneneneasnrernnun 268 data relocations ADM 98 Gata EE 34 data1 directive Mot 181 data2 directive Mot 181 datalabel SHG4 dad eg nade
98. eG RE RR D Eden 215 9 30 2 EE 215 9 30 2 1 Special Characters 0 00 ccc cece ees 215 9 30 3 Nios II Machine Relocations eee 215 9 30 4 Nios II Machine Directive 216 H ere siene Mee STE EE lon oh Gare ERU RUE 217 9 31 NS32K Dependent Features 218 EA E EE 218 9 31 1 1 Special Characters 02 c cee eee eee eens 218 9 32 PDP 11 Dependent Features 219 9 32 1 Cpt eomg NEE REESEN 219 9 32 1 1 Code Generation Options 2 2 nenne 219 9 32 1 2 Instruction Set Extension Options 219 9 32 1 3 CPU Model Options ssseeeeeseeeeeees 220 9 32 1 4 Machine Model Option 220 9 32 2 Assembler Directives 0000 e cece eens 221 9 32 3 PDP 11 Assembly Language Syntax issus 221 9 32 4 Instruction Naming 0 eee eee ee eee eee 221 Using as 9 32 5 Synthetic Instruction 222 9 33 picoJava Dependent Features 0 c cece eee eee eee 223 9 33 ene 223 9 33 2 PJ Syntax eg d dE E Ee SE P teo ine CEFRERI EE 223 9 33 21 Special Characters 53 c Eege Agen 223 9 34 PowerPC Dependent Features 224 dE e WE Gene 224 9 34 2 PowerPC Assembler Directives 000 eee e ee 226 934 3 PowerPG Synbtax eilog EEN lta washes dienes 226 9 34 3 1 Special Character 226 9 35 RL78 Dependent Features 227 9 35 1 RLS Options corretto rhet ne ert bore e 22 9 35 2 Symbolic Operand Mode 227 9 35 3 Assembler Directive 227 9 35 4 Syntax for the
99. eee ees 287 9 46 3 Floating POolnt ee EE eae N E ee we aeons 287 9 46 4 Z80 Assembler Directives 0 0 cece eee eee 287 9 40 5 OpCOdeS ius sien Retrato oe e joe peed Ra pcd ha 288 9 47 28000 Dependent Features 289 9AT Opis esee sacer tet ipa SOR asta codd ende ase ge hrs 289 9 41 2 Syntaxe c iicsite tie RE x REV IUE ERR DERE OPEP 289 9 47 2 1 Special Characters 00 cc cece eee eens 289 9 47 22 Register Names uices Eege Eeer etos 289 9 47 2 3 Addressing Moden 289 9 47 3 Assembler Directives for the 28000 290 DATA e 291 9 48 VAX Dependent Features 291 9 48 1 VAX Command Line Ontions eee 291 9 48 2 VAX Floating Pomt iios se pecerem meme RE 292 9 48 3 Vax Machine Directives 0 0c cece ee 292 9 48 4 VAX Opcodes eene 293 9 48 5 VAX Branch Improvement 00 0c eee eee eee 293 9 48 6 VAX Operands ssssssseessee ee 294 9 48 7 Not Supported on VAX cece eee eee ees 295 9 48 8 VAX Synta e e ER tamed Ree RA EELER EES 295 9 48 8 1 Special Character 295 9 49 v850 Dependent Features 295 9 40 1 Opts sooo bese cota peated ehe rey xe rre ebbe ee 295 9 49 2 Ee Aere AE ENN PER RUE ERSRENFEREEUQESe Y ia 296 9 49 2 1 Special Characters 0 0 ccc cece eens 297 9 49 2 2 Register Names 0 cc cece cee eee eens 297 9 49 3 Floating Polit ier RR Re toes 299 9 49 4 V850 Machine Directive 299 9 40 5 Opcodes cios sese ce EE RI housed KE RRd eda robs 300 9 5
100. enabled by default as it would otherwise pollute the symbol table mpid This option tells the assembler that the position independent data of the RX port of GCC is being used This results in the assembler generating an undefined reference to a symbol called __pid_base and also setting the RX_PID flag bit in the e flags field of the ELF header of the object file mint register num This option tells the assembler how many registers have been reserved for use by interrupt handlers This is needed in order to compute the correct values for the gpreg and 4pidreg meta registers Chapter 9 Machine Dependent Features 229 mgcc abi This option tells the assembler that the old GCC ABI is being used by the assembled code With this version of the ABI function arguments that are passed on the stack are aligned to a 32 bit boundary mrx abi This option tells the assembler that the official RX ABI is being used by the assembled code With this version of the ABI function arguments that are passed on the stack are aligned to their natural alignments This option is the default mcpu name This option tells the assembler the target CPU type Currently the rx200 rx600 and rx610 are recognised as valid cpu names Attempting to assemble an instruction not supported by the indicated cpu type will result in an error message being generated 9 36 2 Symbolic Operand Modifiers The assembler supports one modifier when using symbol addresses in RX in
101. example when a label is defined the next instruction will never be packaged with the previous one Whenever a branch and link instruction is called it will not be packaged with the next instruction so the return address will be valid Nops are automatically inserted when necessary If you do not want the assembler automatically making these decisions you can control the packaging and execution type parallel or sequential with the special execution symbols described in the next section 9 10 2 3 Special Characters 6 0 A semicolon can be used anywhere on a line to start a comment that extends to the end of the line 130 Using as If a 4 appears as the first character of a line the whole line is treated as a comment but in this case the line could also be a logical line number directive see Section 3 3 Comments page 27 or a preprocessor control command see Section 3 1 Preprocessing page 27 Sub instructions may be executed in order in reverse order or in parallel Instructions listed in the standard one per line format will be executed sequentially unless you use the 0 option To specify the executing order use the following symbols SE Sequential with instruction on the left first lt Sequential with instruction on the right first qP Parallel The D30V syntax allows either one instruction per line one instruction per line with the execution symbol or two instructions per line For example
102. expand into jbsb Jsb is already an instruction mnemonic so we chose jbsb byte displacement bsbb word displacement bsbw long displacement jsb jbr jr Unconditional branch byte displacement DYD word displacement brw long displacement jmp jCOND COND may be any one of the conditional branches neq nequ eql eqlu gtr geq 1ss gtru lequ vc vs gequ cc 1ssu cs COND may also be one of the bit tests bs bc bss bcs bsc bcc bssi bcci lbs 1bc NOTCOND is the opposite condition to COND byte displacement bCOND word displacement bNOTCOND foo brw foo long displacement bNOTCOND foo jmp foo jacbX X may beoneofbdfghlqw 294 jaobYYY jsobZZZ aobleq aoblss sobgeq sobgtr Using as word displacement OPCODE long displacement OPCODE foo brb bar foo jmp bar YYY may be one of 1ss leq ZZZ may be one of geq gtr byte displacement OPCODE word displacement OPCODE foo brb bar foo brw destination bar long displacement OPCODE foo brb bar foo jmp destination bar byte displacement OPCODE word displacement OPCODE foo brb bar foo brw destination bar long displacement OPCODE foo brb bar foo jmp destination bar 9 48 6 VAX Operands The immediate character is for Unix compatibility not
103. expression expression See extend ltorg This directive causes the current contents of the literal pool to be dumped into the current section which is assumed to be the text section at the current location aligned to a word boundary GAS maintains a separate literal pool for each section and each sub section The 1torg directive will only affect the literal pool of the current section and sub section At the end of assembly all remaining un empty literal pools will automatically be dumped Note older versions of GAS would dump the current literal pool any time a section change occurred This is no longer done since it prevents accurate control of the placement of literal pools movsp reg offset Tell the unwinder that reg contains an offset from the current stack pointer If offset is not specified then it is assumed to be zero 102 Using as object arch name Override the architecture recorded in the EABI object attribute section Valid values for name are the same as for the arch directive Typically this is useful when code uses runtime detection of CPU features packed expression expression This directive writes 12 byte packed floating point values to the output section These are not compatible with current ARM processors or ABIs pad count Generate unwinder annotations for a stack adjustment of count bytes A posi tive value indicates the function prologue allocated stack space by decrementing the
104. following statements into the bss section which is used for data that is uninitialized anywhere 9 38 3 SCORE Syntax 9 38 3 1 Special Characters The presence of a 4 appearing anywhere on a line indicates the start of a comment that extends to the end of that line If a 4 appears as the first character of a line then the whole line is treated as a com ment but in this case the line can also be a logical line number directive see Section 3 3 Comments page 27 or a preprocessor control command see Section 3 1 Preprocessing page 27 The character can be used to separate statements on the same line 248 Using as 9 39 Renesas SuperH SH Dependent Features 9 39 1 Options as has following command line options for the Renesas formerly Hitachi SuperH SH family little Generate little endian code big Generate big endian code relax Alter jump instructions for long displacements small Align sections to 4 byte boundaries not 16 dsp Enable sh dsp insns and disable sh3e sh4 insns renesas Disable optimization with section symbol for compatibility with Renesas as sembler allow reg prefix Allow as a register name prefix fdpic Generate an FDPIC object file isa sh4 sh4a Specify the sh4 or sh4a instruction set isa dsp Enable sh dsp insns and disable sh3e sh4 insns isa fp Enable sh2e sh3e sh4 and sh4a insn sets isa all Enable sh1 sh2 sh2e sh3 sh3e sh
105. for altered difference tables 22 Warning MESSAGES sei eit anee sate dete es 18 warnings causing erof 26 warnings M32E EE 174 warnings SuDDtesging e 26 warnings switching on 26 weak directive sre cesses eee e NN 77 weakref directe 78 Whitespace 222 iectsdvedied add LEES CRINE EOD 27 whitespace removed by preprocessor 27 wide floating point directives VAX 292 width directive TICACK 269 Width of continuation lines of disassembly output EE 23 Width of first line disassembly output 23 Width of source line output sessuecccecu 23 wmsg directive TIC54X 000 268 e 78 word directive ARC rosone ENEE ANEN E 94 word directive HS 200 136 word directive i386 ec cece eee eee 152 word directive Nios DU 216 word directive SPARC 2 00ee eee 263 Using as word directive TIC54X 0 0 0006 269 word directive x86 64 eee ee eee 152 writing patterns in MeEMOTy sssusrsrsuse 55 WV cd 290 X x86 machine directives sseususesereu 147 x86 64 arch directive 2 eee eee 154 x86 64 att_syntax pseudo op 147 x86 64 conversion instructions 148 x86 64 floating point scis rereeiieni riiseni 152 x86 64 immediate operands sssesrsrsrecs 147 x86 64 instruction naming sssssssseso 148 x86 64 intel syntax pseudo op 147 x86
106. further change the state of the directive without having to be aware of its outer state For example consider begin no transform L add a0 ai a2 begin transform M add a0 ai a2 end transform N add a0 ai a2 end no transform The ADD opcodes at L and N in the outer no transform region both result in ADD machine instructions but the assembler selects an ADD N instruction for the ADD at M in the inner transform region 312 Using as The advantage of this style is that it works well inside macros which can preserve the context of their callers The following directives are available 9 52 5 1 schedule The schedule directive is recognized only for compatibility with Tensilica s assembler begin no schedule end no schedule This directive is ignored and has no effect on as 9 52 5 2 longcalls The longcalls directive enables or disables function call relaxation See Section 9 52 4 2 Function Call Relaxation page 310 begin no longcalls end no longcalls Call relaxation is disabled by default unless the longcalls command line option is specified The longcalls directive overrides the default determined by the command line options 9 52 5 3 transform This directive enables or disables all assembler transformation including relaxation see Section 9 52 4 Xtensa Relaxation page 309 and optimization see Section 9 52 3 Xtensa Optimizations page 308 begin no transform end no tr
107. gear mre 252 dbpc register V8B 0 iis rere ene 299 dbpsw register V b eecerisiririrorrernri dipa 299 debuggers and symbol order 39 338 debugging COFF symbols 53 DEG Syntax ep e tI t EET E dant RaR anes 221 decimal integers csenesene ee deans sarees 30 def directiy ah onice mehRpSe REANO PIRE 93 def directive TIC54X 0 00 269 density Instruction 308 dependency racing 25 deprecated directives 2 0 eee eee eee 78 desc Gecke oe iuc cesset pce ne ad EE E 53 descriptor of a out symbol 42 dfloat directive VAN 292 difference tables altered 78 difference tables warning esses 22 differences mmieal 000s ee eee 209 dim directive uo leue eR aE Kin ELE Eaa aes 53 directives and mstruchionsg 28 directives for PowerPC Lssus 226 directives for GCORE 00 eee ee eee 246 directives Blackfin 00 00 e eee eee 116 directives M32R Ee RER d RE AE 173 directives Most 181 directives machine independent Ar directives Xtensa llle eee eee 311 directives 28000 2c cece eee eee ee eee 290 Disable floating point instructions 202 Disable single precision floating point operations ee delish UI Paducah E 202 displacement sizing character VAX 294 dollar local zembols 0 cece eee eee 41 dot Symbol de enges Sege 41 double directive 0 c
108. how these two types should be distinguished Most implementations followed the 1387 model in which the first bit of the significand is set for quiet NaNs and clear for signalling NaNs However the original MIPS implementation assigned the opposite meaning to the bit so that it was set for signalling NaNs and clear for quiet NaNs The 2008 revision of the standard formally suggested the 1387 choice and as from Sep 2012 the current release of the MIPS architecture therefore optionally supports that form Code that uses one NaN encoding would usually be incompatible with code that uses the other NaN encoding so MIPS ELF objects have a flag EF MIPS NAN2008 to record which encoding is being used Assembly files can use the nan directive to select between the two encodings nan 2008 says that the assembly file uses the IEEE 754 2008 encoding while nan legacy says that the file uses the original MIPS encoding If several nan directives are given the final setting is the one that is used The command line options mnan legacy and mnan 2008 can be used instead of nan legacy and nan 2008 respectively However any nan directive overrides the command line setting nan legacy is the default if no nan directive or mnan option is given Note that GNU as does not produce NaNs itself and therefore these directives do not affect code generation They simply control the setting of the EF_MIPS_NAN2008
109. how as assembles your file Errors which stop the assembly are still reported If you use the fatal warnings option as considers files that generate warnings to be in error You can switch these options off again by specifying warn which causes warnings to be output as usual 2 17 Generate Object File in Spite of Errors Z After an error message as normally produces no output If for some reason you are inter ested in object file output even after as gives an error message on your program use the Z option If there are any errors as continues anyways and writes an object file after a final warning message of the form n errors m warnings generating bad object file Chapter 3 Syntax 27 3 Syntax This chapter describes the machine independent syntax allowed in a source file as syntax is similar to what many other assemblers use it is inspired by the BSD 4 2 assembler except that as does not assemble Vax bit fields 3 1 Preprocessing The as internal preprocessor e adjusts and removes extra whitespace It leaves one space or tab before the keywords on a line and turns any other whitespace on the line into a single space e removes all comments replacing them with a single space or an appropriate number of newlines e converts character constants into the appropriate numeric values It does not do macro processing include file handling or anything else you may get from your C
110. in Intel syntax The instruction mnemonic suffixes are tacked on to this base name the from suffix before the to suffix Thus movsbl al Aedx is AT amp T syntax for move sign extend from al to edx Possible suffixes thus are b1 from byte to long bw from byte to word wl from word to long bq from byte to quadruple word wq from word to quadruple word and 1q from long to quadruple word Different encoding options can be specified via optional mnemonic suffix s suffix swaps 2 register operands in encoding when moving from one register to another d8 or d32 suffix prefers 8bit or 32bit displacement in encoding The Intel syntax conversion instructions e cbw sign extend byte in al to word in 4ax e cwde sign extend word in hax to long in Zeax e cwd sign extend word in Zax to long in 4dx Aax e cdq sign extend dword in eax to quad in 4edx Aeax e cdge sign extend dword in eax to quad in 4rax x86 64 only Chapter 9 Machine Dependent Features 149 e cqo sign extend quad in rax to octuple in 4rdx rax x86 64 only are called cbtw cwtl cwtd cltd cltq and cqto in AT amp T naming as accepts either naming for these instructions Far call jump instructions are lcall and l1jmp in AT amp T syntax but ar
111. in the R800 instruction set out c 0 Sends zero to the port pointed to by register c slim Equivalent to m m lt lt 1 1 the operand m can be any operand that is valid for sla One can use s11 as a synonym for sli op ix d r This is equivalent to ld r ix d opc r ld ix d r The operation opc may be any of res b set b rl ric rr rro sla sli sra and srl and the register r may be any of a b c d e h and 1 opc iytd r As above but with iy instead of ix The web site at http www z80 info is a good starting place to find more information on programming the Z80 Chapter 9 Machine Dependent Features 289 9 47 Z8000 Dependent Features The Z8000 as supports both members of the Z8000 family the unsegmented Z8002 with 16 bit addresses and the segmented Z8001 with 24 bit addresses When the assembler is in unsegmented mode specified with the unsegm directive an address takes up one word 16 bit sized register When the assembler is in segmented mode specified with the segm directive a 24 bit address takes up a long 32 bit register See Section 9 47 3 Assembler Directives for the Z8000 page 290 for a list of other Z8000 specific assembler directives 9 47 1 Options z8001 Generate segmented code by default 28002 Generate unsegmented code by de
112. increment disp Rn Register indirect with displacement RO Rn Register indexed disp GBR GBR offset RO GBR GBR indexed addr disp PC PC relative address for branch or for addressing memory The as implemen tation allows you to use the simpler form addr anywhere a PC relative address is called for the alternate form is supported for compatibility with other as semblers imm Immediate data 9 39 3 Floating Point SH2E SH3E and SH4 groups have on chip floating point unit FPU Other SH groups can use float directive to generate IEEE floating point numbers 250 Using as SH2E and SH3E support single precision floating point calculations as well as entirely PCAPI compatible emulation of double precision floating point calculations SH2E and SH3E instructions are a subset of the floating point calculations conforming to the IEEE754 standard In addition to single precision and double precision floating point operation capability the on chip FPU of SH4 has a 128 bit graphic engine that enables 32 bit floating point data to be processed 128 bits at a time It also supports 4 4 array operations and inner product operations Also a superscalar architecture is employed that enables simultaneous execution of two instructions including FPU instructions providing performance of up to twice that of conventional architectures at the same frequency 9 39 4 SH Machine Directives uaword ualong uaquad as
113. instructions For example if a series of instructions have underscore prefixes the assembler will not transform the individual instructions but it may insert other instructions between them e g to align a LOOP instruction To prevent the assembler from modifying a series of instructions as a whole use the no transform directive See Section 9 52 5 3 transform page 312 9 52 2 2 Register Names The assembly syntax for a register file entry is the short name for a TIE register file followed by the index into that register file For example the general purpose AR register file has a short name of a so these registers are named a0 a15 As a special feature sp is also supported as a synonym for a1 Additional registers may be added by processor configuration options and by designer defined TIE extensions An initial character is optional in all register names 9 52 3 Xtensa Optimizations The optimizations currently supported by as are generation of density instructions where appropriate and automatic branch target alignment 9 52 3 1 Using Density Instructions The Xtensa instruction set has a code density option that provides 16 bit versions of some of the most commonly used opcodes Use of these opcodes can significantly reduce code size When possible the assembler automatically translates instructions from the core Xtensa instruction set into equivalent instructions from the Xtensa code density option This trans
114. instructions that also work on R800 warn unportable instructions Wup Issue a warning for undocumented Z80 instructions that do not work on R800 forbid undocumented instructions Fud Treat all undocumented instructions as errors forbid unportable instructions Fup Treat undocumented Z80 instructions that do not work on R800 as errors 1 1 Structure of this Manual This manual is intended to describe what you need to know to use GNU as We cover the syntax expected in source files including notation for symbols constants and expressions the directives that as understands and of course how to invoke as This manual also describes some of the machine dependent features of various flavors of the assembler On the other hand this manual is not intended as an introduction to programming in assembly language let alone programming in general In a similar vein we make no attempt to introduce the machine architecture we do not describe the instruction set standard mnemonics registers or addressing modes that are standard to a particular archi tecture You may want to consult the manufacturer s machine architecture manual for this information Chapter 1 Overview 17 1 2 The GNU Assembler GNU as is really a family of assemblers If you use or have used the GNU assembler on one architecture you should find a fairly similar environment when you use it on another architecture Each version has much in common with the others
115. is created or linked against together with a global offset table entry The value is a pc relative offset to the corresponding stub code in the procedure linkage table This arrangement causes the run time symbol resolver to be called to look up and set the value of the symbol the first time the function is called at latest depending environment variables It is only safe to leave the symbol unresolved this way if all references are function calls This modifier is used to load the offset of the GOT entry of the symbol s TLS descriptor to be used for general dynamic TLS accesses tls_gd_1o16 This modifier is used to load the sign extended low 16 bits of the offset of the GOT entry of the symbol s TLS descriptor to be used for general dynamic TLS accesses tls_gd_hi16 This modifier is used to load the sign extended high 16 bits of the offset of the GOT entry of the symbol s TLS descriptor to be used for general dynamic TLS accesses tls_gd_ha16 tls_ie This modifier is like t1s ed hi16 but it adds one to the value if tls_gd_1016 of the input value is negative This modifier is used to load the offset of the GOT entry containing the offset of the symbol s address from the TCB to be used for initial exec TLS accesses tls ie 1016 This modifier is used to load the low 16 bits of the offset of the GOT entry containing the offset of the symbol s address from the TCB to be used for initial exec TLS accesses t
116. is not supported 2 10 Dependency Tracking MD as can generate a dependency file for the file it creates This file consists of a single rule suitable for make describing the dependencies of the main source file The rule is written to the file named in its argument This feature is used in the automatic updating of makefiles 2 11 Name the Object File o There is always one object file output when you run as By default it has the name a out or b out for Intel 960 targets only You use this option which takes exactly one filename to give the object file a different name Whatever the object file is called as overwrites any existing file of the same name 2 12 Join Data and Text Sections R R tells as to write the object file as if all data section data lives in the text section This is only done at the very last moment your binary data are the same but data section parts are relocated differently The data section part of your object file is zero bytes long because all its bytes are appended to the text section See Chapter 4 Sections and Relocation page 33 When you specify R it would be possible to generate shorter address displacements because we do not have to cross between text and data section We refrain from doing this simply for compatibility with older versions of as In future R may work this way When as is configured for COFF or ELF output this option
117. is only useful if you use sections named text and data R is not supported for any of the HPPA targets Using R generates a warning from as 2 13 Display Assembly Statistics statistics Use statistics to display two statistics about the resources used by as the maximum amount of space allocated during the assembly in bytes and the total execution time taken for the assembly in CPU seconds 2 14 Compatible Output traditional format For some targets the output of as is different in some ways from the output of some existing assembler This switch requests as to use the traditional format instead For example it disables the exception frame optimizations which as normally does by default on gcc output 6 2 15 Announce Version v You can find out what version of as is running by including the option v which you can also spell as version on the command line 26 Using as 6 2 16 Control Warnings W warn no warn fatal warnings as should never give a warning or error message when assembling compiler output But programs written by people often cause as to give a warning that a particular assumption was made All such warnings are directed to the standard error file If you use the W and no warn options no warnings are issued This only affects the warning messages it does not change any particular of
118. last tls le This modifier yields the same value as hwO t1s 1e but it also checks that the value does not overflow hwi last tls le This modifier is used to load bits 16 31 of the offset of the symbol s address from the TCB to be used for local exec TLS accesses It also checks that the value does not overflow tls gd call This modifier is used to tag an instrution as the call part of a calling sequence for a TLS GD reference of its operand tls ed add This modifier is used to tag an instruction as the add part of a calling sequence for a TLS GD reference of its operand tls ie load This modifier is used to tag an instruction as the load part of a calling sequence for a TLS IE reference of its operand 9 44 3 TILE Gx Directives align expression expression This is the generic align directive The first argument is the requested align ment in bytes allow suspicious bundles Turns on error checking for combinations of instructions in a bundle that prob ably indicate a programming error This is on by default no allow suspicious bundles Turns off error checking for combinations of instructions in a bundle that prob ably indicate a programming error Chapter 9 Machine Dependent Features 281 require canonical reg names Require that canonical register names be used and emit a warning if the nu meric names are used This is on by default no require canonical reg names Permit the use o
119. lation can be disabled by using underscore prefixes see Section 9 52 2 1 Opcode Names page 307 by using the no transform command line option see Section 9 52 1 Com mand Line Options page 306 or by using the no transform directive see Section 9 52 5 3 transform page 312 It is a good idea not to use the density instructions directly The assembler will au tomatically select dense instructions where possible If you later need to use an Xtensa processor without the code density option the same assembly code will then work without modification 9 52 3 2 Automatic Instruction Alignment The Xtensa assembler will automatically align certain instructions both to optimize per formance and to satisfy architectural requirements As an optimization to improve performance the assembler attempts to align branch targets so they do not cross instruction fetch boundaries Xtensa processors can be con figured with either 32 bit or 64 bit instruction fetch widths An instruction immediately following a call is treated as a branch target in this context because it will be the target of a return from the call This alignment has the potential to reduce branch penalties at some expense in code size This optimization is enabled by default You can disable it with the Chapter 9 Machine Dependent Features 309 no target align command line option see Section 9 52 1 Command Line Options page 306 The target alignment o
120. m32rx Specify which processor in the M32R family is the target The default is nor mally the M32R but this option changes it to the M32RX warn explicit parallel conflicts or Wp Produce warning messages when questionable parallel constructs are encoun tered 10 Using as no warn explicit parallel conflicts or Wnp Do not produce warning messages when questionable parallel constructs are encountered The following options are available when as is configured for the Motorola 68000 series 1 Shorten references to undefined symbols to one word instead of two m68000 m68008 m68010 m68020 m68030 m68040 m68060 m68302 m68331 m68332 m68333 m68340 mcpu32 m5200 Specify what processor in the 68000 family is the target The default is normally the 68020 but this can be changed at configuration time m68881 m68882 mno 68881 mno 68882 The target machine does or does not have a floating point coprocessor The default is to assume a coprocessor for 68020 68030 and cpu32 Although the basic 68000 is not compatible with the 68881 a combination of the two can be specified since it s possible to do emulation of the coprocessor instructions with the main processor m68851 mno 68851 The target machine does or does not have a memory management unit co processor The default is to assume an MMU for 68020 and up See Section 9 30 1 Nios II Options page 215 for the options availab
121. memory operands is determined from the last character of the instruction mnemonic Mnemonic suffixes of b w 1 and q specify byte 8 bit word 16 bit long 32 bit and quadruple word 64 bit memory references Intel syn tax accomplishes this by prefixing memory operands not the instruction mnemonics with byte ptr word ptr dword ptr and qword ptr Thus Intel mov al byte ptr foo is movb foo al in AT amp T syntax In 64 bit code movabs can be used to encode the mov instruction with the 64 bit displacement or immediate operand e Immediate form long jumps and calls are 1call 1jmp section offset in AT amp T syntax the Intel syntax is call jmp far section offset Also the far return in 148 Using as struction is lret stack adjust in AT amp T syntax Intel syntax is ret far stack adjust e The AT amp T assembler does not provide support for multiple section programs Unix style systems expect all programs to be single sections 9 15 3 2 Special Characters The presence of a 4 appearing anywhere on a line indicates the start of a comment that extends to the end of that line If a appears as the first character of a line then the whole line is treated as a com ment but in this case the line can also be a logical line number directive see Section 3 3 Comments page 27 or a preprocessor control command see Section 3 1 Prepro
122. nest these comments L The only way to include a newline n in a comment is to use this sort of comment This sort of comment does not nest 28 Using as Anything from a line comment character up to the next newline is considered a comment and is ignored The line comment character is target specific and some targets multiple comment characters Some targets also have line comment characters that only work if they are the first character on a line Some targets use a sequence of two characters to introduce a line comment Some targets can also change their line comment characters depending upon command line options that have been used For more details see the Syntax section in the documentation for individual targets If the line comment character is the hash sign then it still has the special ability to enable and disable preprocessing see Section 3 1 Preprocessing page 27 and to specify logical line numbers To be compatible with past assemblers lines that begin with have a special inter pretation Following the should be an absolute expression see Chapter 6 Expressions page 43 the logical line number of the nezt line Then a string see Section 3 6 1 1 Strings page 29 is allowed if present it is a new logical file name The rest of the line if any should be whitespace If the first non whitespace characters on the line are not numeric the line is ignored Just like
123. nodename portion of the alias should be the name of a node specified in the version script supplied to the linker when building a shared library If you are attempting to override a versioned symbol from a shared library then nodename should correspond to the nodename of the symbol you are trying to override If the symbol name is not defined within the file being assembled all references to name will be changed to name2 nodename If no reference to name is made name280nodename will be removed from the symbol table Another usage of the symver directive is symver name name200nodename In this case the symbol name must exist and be defined within the file being assembled It is similar to name2 nodename The difference is name2 nodename will also be used to resolve references to name2 by the linker The third usage of the symver directive is symver name name2000nodename When name is not defined within the file being assembled it is treated as name20nodename When name is defined within the file being assembled the symbol name name will be changed to name2 nodename 7 112 tag structname This directive is generated by compilers to include auxiliary debugging information in the symbol table It is only permitted inside def endef pairs Tags are used to link structure definitions in the symbol table with instances of those structures 7 113 text subsection Tells as to assemble the following statements onto the end of the
124. nop after a 32 bit multiply instruction is generated The following options are available when as is configured for the Adapteva EPIPHANY series See Section 9 11 1 Epiphany Options page 133 for the options available when as is configured for an Epiphany processor See Section 9 15 1 i386 Options page 145 for the options available when as is configured for an i386 processor The following options are available when as is configured for the Intel 80960 processor ACA ACA_A ACB ACC AKA AKB AKC AMC Specify which variant of the 960 architecture is the target b Add code to collect statistics about branches taken no relax Do not alter compare and branch instructions for long displacements error if necessary The following options are available when as is configured for the Ubicom IP2K series mip2022ext Specifies that the extended IP2022 instructions are allowed mip2022 Restores the default behaviour which restricts the permitted instructions to just the basic IP2022 ones The following options are available when as is configured for the Renesas M32C and M416C processors m32c Assemble M32C instructions mi6c Assemble M16C instructions the default relax Enable support for link time relaxations h tick hex Support H 00 style hex constants in addition to 0x00 style The following options are available when as is configured for the Renesas M32R formerly Mitsubishi M32R series
125. object file requires hardware floating point support or floating point arguments might be passed in integer registers if the object file supports processors with no hardware floating point unit Or if two objects are built for different generations of the same architecture the combination may require the newer generation at run time This information is useful during and after linking At link time 1d can warn about incompatible object files After link time tools like gdb can use it to process the linked file correctly Compatibility information is recorded as a series of object attributes Each attribute has a vendor tag and value The vendor is a string and indicates who sets the meaning of the tag The tag is an integer and indicates what property the attribute describes The value may be a string or an integer and indicates how the property affects this object Missing attributes are the same as attributes with a zero value or empty string value Object attributes were developed as part of the ABI for the ARM Architecture The file format is documented in ELF for the ARM Architecture 8 1 GNU Object Attributes The gnu_attribute directive records an object attribute with vendor gnu Except for Tag_compatibility which has both an integer and a string for its value GNU attributes have a string value if the tag number is odd and an integer value if the tag number is even The second bit tag amp 2 is set for architect
126. of entries in the table which follow immediately each is a word pointing to one of the labels illustrated above NEXT COUNT N BRLAB 1 n BRLAB N BRANCH TABLE layout The first word of the header is used to locate multiple branch tables since each object file may contain one Normally the links are maintained with a call to an initialization routine placed at the beginning of each function in the file The GNU C compiler generates these calls automatically when you give it a b option For further details see the documentation of gbr960 160 no relax Using as Normally Compare and Branch instructions with targets that require displace ments greater than 13 bits or that have external targets are replaced with the corresponding compare or chkbit and branch instructions You can use the no relax option to specify that as should generate errors instead if the target displacement is larger than 13 bits This option does not affect the Compare and Jump instructions the code emit ted for them is always adjusted when necessary depending on displacement size regardless of whether you use no relax 9 17 2 Floating Point as generates IEEE floating point numbers for the directives float double extended and single 9 17 3 1960 Machine Directives bss symbol length align Reserve length bytes in the bss section for a local s
127. of the line The character can be used to separate statements on the same line 9 51 2 XStormy16 Machine Directives 16bit_pointers Like the 16bit pointers command line option this directive indicates that the assembly code makes use of 16 bit pointers 32bit_pointers Like the 32bit pointers command line option this directive indicates that the assembly code makes use of 32 bit pointers no pointers Like the no pointers command line option this directive indicates that the assembly code does not makes use pointers 9 51 3 XStormy16 Pseudo Opcodes as implements all the standard XStormy16 opcodes as also implements the following pseudo ops lo Computes the lower 16 bits of the given expression and stores it into the im mediate operand field of the given instruction For example add r6 lo here there computes the difference between the address of labels here and there takes the lower 16 bits of this difference and adds it to register 6 hi Computes the higher 16 bits of the given expression and stores it into the immediate operand field of the given instruction For example addc r7 hi here there computes the difference between the address of labels here and there takes the upper 16 bits of this difference shifts it down 16 bits and then adds it along with the carry bit to the value in register 7 306 Using as 9 52 Xtensa Dependent Features
128. one year after the last time you distribute an Opaque copy directly or through your agents or retailers of that edition to the public It is requested but not required that you contact the authors of the Document well before redistributing any large number of copies to give them a chance to provide you with an updated version of the Document 4 MODIFICATIONS You may copy and distribute a Modified Version of the Document under the conditions of sections 2 and 3 above provided that you release the Modified Version under precisely this License with the Modified Version filling the role of the Document thus licensing distribution and modification of the Modified Version to whoever possesses a copy of it In addition you must do these things in the Modified Version A Use in the Title Page and on the covers if any a title distinct from that of the Document and from those of previous versions which should if there were any 324 N O Using as be listed in the History section of the Document You may use the same title as a previous version if the original publisher of that version gives permission List on the Title Page as authors one or more persons or entities responsible for authorship of the modifications in the Modified Version together with at least five of the principal authors of the Document all of its principal authors if it has fewer than five unless they release you from this requirement State on th
129. option will set the is stmt register in the debug line state machine to value which must be either 0 or 1 isa value This directive will set the isa register in the debug line state machine to value which must be an unsigned integer discriminator value This directive will set the discriminator register in the debug line state machine to value which must be an unsigned integer 62 Using as 7 76 loc_mark_labels enable When emitting DWARF2 line number information the loc_mark_labels directive makes the assembler emit an entry to the debug_line line number matrix with the basic_block register in the state machine set whenever a code label is seen The enable argument should be either 1 or 0 to enable or disable this function respectively Veit local names This directive which is available for ELF targets marks each symbol in the comma separated list of names as a local symbol so that it will not be externally visible If the symbols do not already exist they will be created For targets where the 1comm directive see Section 7 69 Lcomm page 60 does not accept an alignment argument which is the case for most ELF targets the Local directive can be used in combination with comm see Section 7 32 Comm page 52 to define aligned local common data 7 78 long expressions Long is the same as int See Section 7 65 int page 58 7 79 macro The commands macro and endm allow you to define macros t
130. or disable the use of the commercial instruction set which consists of these instructions ADDNI ADDN ADDPI ADDP ASHNI ASHN ASHPI ASHP CMPCI CMPC CMPNI CMPN CMPPI CMPP CVTLNI CVTLN CVTLPI CVTLP CVTNLI CVTNL CVTNPI CVTNP CVTPLI CVTPL CVTPNI CVTPN DIVPI DIVP L2DR L3DR LOCCI LOCC MATCI MATC MOVCI MOVC MOVRCI MOVRC MOVTCI MOVTC MULPI MULP SCANCT SCANC SKPCI SKPC SPANCI SPANC SUBNI SUBN SUBPI and SUBP mcsm mno csm Enable or disable the use of the CSM instruction meis mno eis Enable or disable the use of the extended instruction set which consists of these instructions ASHC ASH DIV MARK MUL RTT SOB SXT and XOR mfis mkevi1 mno fis mno kevi1 Enable or disable the use of the KEV11 floating point instructions FADD FDIV FMUL and FSUB mfpp mfpu mfp 11 mno fpp mno fpu mno fp 11 Enable or disable the use of FP 11 floating point instructions ABSF ADDF CFCC CLRF CMPF DIVF LDCFF LDCIF LDEXP LDF LDFPS MODF MULF NEGF SETD SETF SETI SETL STCFF STCFI STEXP STF STFPS STST SUBF and TSTF 220 Using as mlimited eis mno limited eis Enable or disable the use of the limited extended instruction set MARK RTT SOB SXT and XOR The mno limited eis options also implies mno eis mmfpt mno mfpt Enable or disable the use of the MFPT instruction mmultiproc mno multiproc Enable or disable the use of multip
131. or instruction with an immediate larger than 16 bits will be expanded into two instructions This is a very undesirable feature to rely on so this flag can help detect any code where it happens One use of it for instance has been to find and eliminate any place where gcc may emit these pseudo instructions mxp Enable support for the 1860XP instructions and control registers By default this option is disabled so that only the base instruction set i e i860XR is supported mintel syntax The i860 assembler defaults to AT amp T SVRA syntax This option enables the Intel syntax 9 16 3 1860 Machine Directives dual Enter dual instruction mode While this directive is supported the preferred way to use dual instruction mode is to explicitly code the dual bit with the d prefix Chapter 9 Machine Dependent Features 157 enddual Exit dual instruction mode While this directive is supported the preferred way to use dual instruction mode is to explicitly code the dual bit with the d prefix atmp Change the temporary register used when expanding pseudo operations The default register is r31 The dual enddual and atmp directives are available only in the Intel syntax mode Both syntaxes allow for the standard align directive However the Intel syntax addi tionally allows keywords for the alignment parameter align type where type is one of short long quad single double representing alignments of 2 4 16 4
132. produced when signed immediate values overflow the space available for then within their opcodes By default this option is disabled as it is possible to receive spurious warnings due to using exact bit patterns as immediate constants wunsigned overflow Causes warnings to be produced when unsigned immediate values overflow the space available for then within their opcodes By default this option is disabled as it is possible to receive spurious warnings due to using exact bit patterns as immediate constants mv850 Specifies that the assembled code should be marked as being targeted at the V850 processor This allows the linker to detect attempts to link such code with code assembled for other processors mv850e Specifies that the assembled code should be marked as being targeted at the V850E processor This allows the linker to detect attempts to link such code with code assembled for other processors 296 Using as mv850e1 Specifies that the assembled code should be marked as being targeted at the V850E1 processor This allows the linker to detect attempts to link such code with code assembled for other processors mv850any Specifies that the assembled code should be marked as being targeted at the V850 processor but support instructions that are specific to the extended vari ants of the process This allows the production of binaries that contain target specific code but which are also intended to be used in a generic fashion For
133. registers are called pc program counter a 16 bit register except on the H8 300H where it is 24 bits and ccr condition code register an 8 bit register r7 is used as the stack pointer and can also be called sp 9 12 2 3 Addressing Modes as understands the following addressing modes for the H8 300 rn Register direct rn Register indirect d rn d 16 rn d 24 rn Register indirect 16 bit or 24 bit displacement d from register n 24 bit dis placements are only meaningful on the H8 300H rn Register indirect with post increment rn Register indirect with pre decrement aa Qaa 8 Qaa 16 Qaa 24 Absolute address aa The address size 24 only makes sense on the H8 300H Chapter 9 Machine Dependent Features 135 XX xx 8 xx 16 xx 32 Immediate data xx You may specify the 8 16 or 32 for clarity if you wish but as neither requires this nor uses it the data size required is taken from context aa QQaa 8 Memory indirect You may specify the 8 for clarity if you wish but as neither requires this nor uses it 9 12 3 Floating Point The H8 300 family has no hardware floating point but the float directive generates IEEE floating point numbers for compatibility with other development tools 136 Using as 9 12 4 H8 300 Machine Directives as has the following machine dependent directives for the H8 300 h8300h Recognize and emit additional instruction
134. returning control to the exception handler Of course if an exception is not thrown the function that contains the save pseudo op restores these registers in the function epilogue as is done with the 1dmfd instruction above You do not have to save callee saved registers at the very beginning of the function and you do not need to use the save pseudo op immediately following the point at which the registers are saved However if you modify a callee saved register you must save it on the stack before modifying it and before calling any functions which might throw an exception And you must use the save pseudo op to indicate that you have done so The pad see pad page 99 pseudo op indicates a modification of the stack pointer that does not save any registers The argument is the number of bytes in decimal that are subtracted from the stack pointer On ARM CPUS the stack grows downwards so subtracting from the stack pointer increases the size of the stack The setfp see setfp pseudo op page 102 pseudo op indicates the register that contains the frame pointer The first argument is the register that is set which is typically fp The second argument indicates the register from which the frame pointer takes its value The third argument if present is the value in decimal added to the register specified by the second argument to compute the value of the frame pointer You should not modify the frame pointer in the body of
135. same address and feed the value to a single use then the use may not use a lituse relocation 86 Using as lituse base N Used with any memory format instruction e g 1d1 to indicate that the literal is used for an address load The offset field of the instruction must be zero During relaxation the code may be altered to use a gp relative load lituse_jsr N Used with a register branch format instruction e g jsr to indicate that the literal is used for a call During relaxation the code may be altered to use a direct branch e g bsr lituse_jsrdirect N Similar to lituse_jsr but also that this call cannot be vectored through a PLT entry This is useful for functions with special calling conventions which do not allow the normal call clobbered registers to be clobbered lituse bytoff N Used with a byte mask instruction e g extb1 to indicate that only the low 3 bits of the address are relevant During relaxation the code may be altered to use an immediate instead of a register shift lituse_addr N Used with any other instruction to indicate that the original address is in fact used and the original 1dq instruction may not be altered or deleted This is useful in conjunction with lituse_jsr to test whether a weak symbol is defined ldq 27 f00 29 literal 1 beq 27 is undef lituse addr 1 jsr 26 27 foo lituse_jsr 1 lituse_tlsgd N Used with a register branch format instruction to indicate that the literal is the
136. see Section 4 4 Sub Sections page 35 70 Using as ELF Version This is one of the ELF section stack manipulation directives The others are subsection see Section 7 110 SubSection page 74 pushsection see Section 7 93 PushSection page 68 popsection see Section 7 87 PopSection page 66 and previous see Section 7 88 Previous page 66 For ELF targets the section directive is used like this Section name flags Gtypel flag specific arguments l The optional flags argument is a quoted string which may contain any combination of the following characters a section is allocatable e section is excluded from executable and shared library W section is writable x section is executable M section is mergeable S section contains zero terminated strings G section is a member of a section group T section is used for thread local storage section is a member of the previously current section s group if any The optional type argument may contain one of the following constants progbits section contains data nobits section does not contain data i e section only occupies space note section contains data which is used by things other than the program init_array section contains an array of pointers to init functions fini_array section contains an array of pointers to finish functions preinit_array section contains an array of pointers to pre init functions Many targets only support t
137. see the ELF extension documentation ELF Handling For Thread Local Storage Chapter 9 Machine Dependent Features 243 9 37 3 7 Instruction Marker The thread local storage instruction markers are used by the linker to perform code opti mization tls load The tls load marker is used to flag the load instruction in the initial exec TLS model that retrieves the offset from the thread pointer to a thread local storage variable from the GOT tls_gdcall The tls_gdcall marker is used to flag the branch and save instruction to the tls get offset function in the global dynamic TLS model tls ldcall The tls ldcall marker is used to flag the branch and save instruction to the tls get offset function in the local dynamic TLS model For more information about the thread local storage instruction marker and the linker optimizations see the ELF extension documentation ELF Handling For Thread Local Storage 9 37 3 8 Literal Pool Entries A literal pool is a collection of values To access the values a pointer to the literal pool is loaded to a register the literal pool register Usually register r13 is used as the literal pool register Section 9 37 3 1 s390 Register page 232 Literal pool entries are created by adding the suffix lit1 lit2 lit4 or lit8 to the end of an expression for an instruction operand The expression is added to the literal pool and the operand is replaced with the offset to the literal in th
138. sizes Chapter 7 Assembler Directives 61 same_contents Warn if any of the duplicates do not have exactly the same contents tele list Control in conjunction with the nolist directive whether or not assembly listings are generated These two directives maintain an internal counter which is zero initially list increments the counter and nolist decrements it Assembly listings are generated whenever the counter is greater than zero By default listings are disabled When you enable them with the a command line option see Chapter 2 Command Line Options page 21 the initial value of the listing counter is one 7 74 1n line number 1n is a synonym for Line 7 75 loc fileno lineno column options When emitting DWARF2 line number information the 1oc directive will add a row to the debug line line number matrix corresponding to the immediately following assembly instruction The fileno lineno and optional column arguments will be applied to the debug line state machine before the row is added The options are a sequence of the following tokens in any order basic block This option will set the basic block register in the debug line state machine to true prologue end This option will set the prologue end register in the debug line state ma chine to true epilogue begin This option will set the epilogue begin register in the debug line state machine to true is stmt value This
139. space should be aligned on a page boundary if it would otherwise cross a page boundary If present alignment flag causes the assembler to allocate size on a long word boundary 268 Using as byte value value_n ubyte value value_n char value value_n uchar value value_n Place one or more bytes into consecutive words of the current section The upper 8 bits of each word is zero filled If a label is used it points to the word allocated for the first byte encountered clink section name Set STYP_CLINK flag for this section which indicates to the linker that if no symbols from this section are referenced the section should not be included in the link If section name is omitted the current section is used Cc mode TBD copy filename filename include filename filename Read source statements from filename The normal include search path is used Normally copy will cause statements from the included file to be printed in the assembly listing and include will not but this distinction is not currently implemented data Begin assembling code into the data section double value value n ldouble value value n float value value n xfloat value value n Place an IEEE single precision floating point representation of one or more floating point values into the current section All but xfloat align the result on a longword boundary Values are stored most si
140. specifier for this operand Absolute Operand m 20 bits movd instructions Displacement Operand s 8 bits Displacement Operand m 16 bits Chapter 9 Machine Dependent Features 119 Displacement Operand 1 24 bits For example 1 movw _myfun c r1 This loads the address of _myfun shifted right by 1 into r1 2 movd _myfun c r2 r1 This loads the address of _myfun shifted right by 1 into register pair r2 r1 3 myfun ptr long _myfun c loadd myfun ptr r1 r0 jal r1 r0 This long directive the address of _myfunc shifted right by 1 at link time 4 loadd _data1 GOT r12 r1 r0 This loads the address of _datal into global offset table ie GOT and its off set value from GOT loads into register pair r2 r1 5 loadd _myfunc cGOT r12 r1 r0 This loads the address of _myfun shifted right by 1 into global off set table ie GOT and its offset value from GOT loads into register pair r1 ro 9 7 2 CR16 Syntax 9 7 2 1 Special Characters The presence of a on a line indicates the start of a comment that extends to the end of the current line If the appears as the first character of a line the whole line is treated as a comment but in this case the line can also be a logical line number directive see Section 3 3 Comments page 27 or a preprocessor control command see Section 3 1 Preprocessing page 27 The character can be used to separate sta
141. storage and initialize them to zero Mark the beginning of a procedure call Only the special case with no arguments is allowed param value flag Specify a number of parameters and flags that define the environment for a procedure param may be any of frame frame size entry_gr end of general regis ter range entry_fr end of float register range entry_sr end of space register range The values for flag are calls or caller proc has subroutines no_calls proc does not call subroutines save_rp preserve return pointer save_sp proc preserves stack pointer no_unwind do not unwind this proc hpux_int proc is interrupt routine Assemble into the standard section called TEXT subsection CODE Copyright string In the SOM object format insert string into the object code marked as a copyright string copyright string enter entry exit In the ELF object format insert string into the object code marked as a version string Not yet supported the assembler rejects programs containing this directive Mark the beginning of a procedure Mark the end of a procedure export name typ param r Make a procedure name available to callers typ if present must be one of absolute code ELF only not SOM data entry data entry millicode plabel
142. terminal You may have to type ct1 D to tell as there is no more program to assemble Use if you need to explicitly name the standard input file in your command line If the source is empty as produces a small empty object file Filenames and Line numbers There are two ways of locating a line in the input file or files and either may be used in reporting error messages One way refers to a line number in a physical file the other refers to a line number in a logical file See Section 1 7 Error and Warning Messages page 18 Physical files are those files named in the command line given to as Logical files are simply names declared explicitly by assembler directives they bear no relation to physical files Logical file names help error messages reflect the original source file when as source is itself synthesized from other files as understands the directives emitted by the gcc preprocessor See also Section 7 53 file page 55 1 6 Output Object File Every time you run as it produces an output file which is your assembly language program translated into numbers This file is the object file Its default name is a out You can give it another name by using the o option Conventionally object file names end with oi The default name is used for historical reasons older assemblers were capable of assembling self contained programs directly into a runnable program For some formats this isn
143. text then debug line section will still be called just debug_line without any suffix size check error size check warning help Issue an error or warning for invalid ELF size directive Print a summary of the command line options and exit target help Idir Sch K Print a summary of all target specific options and exit Add directory dir to the search list for include directives Don t warn about signed overflow Issue warnings when difference tables altered for long displacements Chapter 1 Overview 7 L keep locals Keep in the symbol table local symbols These symbols start with system specific local label prefixes typically L for ELF systems or L for traditional a out systems See Section 5 3 Symbol Names page 39 listing lhs width number Set the maximum width in words of the output data column for an assembler listing to number listing lhs width2 number Set the maximum width in words of the output data column for continuation lines in an assembler listing to number listing rhs width number Set the maximum width of an input source line as displayed in a listing to number bytes listing cont lines number Set the maximum number of lines printed in a listing for a single line of input to number 1 o objfile Name the object file output from as objfile R Fold the data section into the text section Set the default size of GAS s hash tables to a pri
144. text is converted by as to a generic binary floating point number of more than sufficient precision This generic floating point number is converted to a particular computer s floating point format or formats by a portion of as specialized to that computer A flonum is written by writing in order e The digit 0 0 is optional on the HPPA e A letter to tell as the rest of the number is a flonum e is recommended Case is not important On the H8 300 Renesas SuperH SH and AMD 29K architectures the letter must be one of the letters DFPRSX in upper or lower case On the ARC the letter must be one of the letters DFRS in upper or lower case On the Intel 960 architecture the letter must be one of the letters DFT in upper or lower case On the HPPA architecture the letter must be E upper case only e An optional sign either or An optional integer part zero or more decimal digits An optional fractional part followed by zero or more decimal digits An optional exponent consisting of e An E or e e Optional sign either or e One or more decimal digits At least one of the integer part or the fractional part must be present The floating point number has the usual base 10 value as does all processing using integers Flonums are computed independently of any floating point hardware in the computer running as Chapter 4 Sections and Rel
145. text subsection numbered subsection which is an absolute expression If subsection is omitted subsection number zero is used 7 114 title heading Use heading as the title second line immediately after the source file name and pagenum ber when generating assembly listings This directive affects subsequent pages as well as the current page if it appears within ten lines of the top of a page 76 Using as 7 115 type This directive is used to set the type of a symbol COFF Version For COFF targets this directive is permitted only within def endef pairs It is used like this type int This records the integer int as the type attribute of a symbol table entry ELF Version For ELF targets the type directive is used like this type name type description This sets the type of symbol name to be either a function symbol or an object symbol There are five different syntaxes supported for the type description field in order to provide compatibility with various other assemblers Because some of the characters used in these syntaxes such as and are comment characters for some architectures some of the syntaxes below do not work on all architec tures The first variant will be accepted by the GNU assembler on all architectures so that variant should be used for maximum portability if you do not need to assemble your code with other assemblers The syntaxes supported are type lt name gt
146. the m cpu selection options without the m enclosed in double quotes push or pop machine push saves the currently se lected cpu which may be restored with machine pop 9 34 3 PowerPC Syntax 9 34 3 1 Special Characters The presence of a on a line indicates the start of a comment that extends to the end of the current line If a 4 appears as the first character of a line then the whole line is treated as a comment but in this case the line could also be a logical line number directive see Section 3 3 Comments page 27 or a preprocessor control command see Section 3 1 Preprocessing page 27 If the assembler has been configured for the ppc solaris target then the charac ter also acts as a line comment character This can be disabled via the mno solaris command line option The character can be used to separate statements on the same line Chapter 9 Machine Dependent Features 227 9 35 RL78 Dependent Features 9 35 1 RL78 Options relax Enable support for link time relaxation mg10 Mark the generated binary as targeting the G10 variant of the RL78 architec ture 9 35 2 Symbolic Operand Modifiers The RL78 has three modifiers that adjust the relocations used by the linker 1016 When loading a 20 bit or wider address into registers this modifier selects the 16 least significant bits movw ax 1016 _sym 7i16 When loading a 20 bit or wider address into regist
147. the function If you do not use a frame pointer then you should not use the setfp pseudo op If you do not use a frame pointer then you should avoid modifying the stack pointer outside of the function prologue Otherwise the run time library will be unable to find saved registers when it is unwinding the stack The pseudo ops described above are sufficient for writing assembly code that calls func tions which may throw exceptions If you need to know more about the object file format used to represent unwind information you may consult the Exception Handling ABI for the ARM Architecture available from http infocenter arm com 108 Using as 9 5 AVR Dependent Features 9 5 1 Options mmcu mcu Specify ATMEL AVR instruction set or MCU type Instruction set avrl is for the minimal AVR core not supported by the C com piler only for assembler programs MCU types at90s1200 attinyll attiny12 attiny15 attiny28 Instruction set avr2 default is for the classic AVR core with up to 8K program memory space MCU types at90s2313 at90s2323 at90s2333 at90s2343 attiny22 attiny26 at90s4414 at90s4433 at90s4434 at90s8515 at90c8534 at90s8535 Instruction set avr25 is for the classic AVR core with up to 8K program mem ory space plus the MOVW instruction MCU types attiny13 attinyl3a at tiny2313 attiny2313a attiny24 attiny24a attiny4313 attiny44 attiny44a attiny84 attiny84a attiny25 attiny45 attiny85 atti
148. the native assembler l his section describes them only briefly 88 Using as These are the additional directives in as for the Alpha arch cpu Specifies the target processor This is equivalent to the mcpu command line option See Section 9 2 2 Alpha Options page 84 for a list of values for cpu ent function n Mark the beginning of function An optional number may follow for compat ibility with the OSF 1 assembler but is ignored When generating mdebug information this will create a procedure descriptor for the function In ELF it will mark the symbol as a function a la the generic type directive end function Mark the end of function In ELF it will set the size of the symbol a la the generic size directive mask mask offset Indicate which of the integer registers are saved in the current function s stack frame mask is interpreted a bit mask in which bit n set indicates that register n is saved The registers are saved in a block located offset bytes from the canonical frame address CFA which is the value of the stack pointer on entry to the function The registers are saved sequentially except that the return address register normally 26 is saved first This and the other directives that describe the stack frame are currently only used when generating mdebug information They may in the future be used to generate DWARF2 debug frame unwind information for hand written as sembly fmask mask o
149. the s390 as insn short long quad This directive permits the numeric representation of an instructions and makes the assembler insert the operands according to one of the instructions formats for insn Section 9 37 3 4 s390 Formats page 235 For example the instruction 1 4r1 24 r15 could be written as insn rx 0x58000000 r1 24 r15 This directive places one or more 16 bit short 32 bit long or 64 bit quad values into the current section If an ELF or TLS modifier is used only the following expressions are allowed symbol modifier constant symbol modifier label constant and symbol modifier label constant The following modifiers are available got got12 The got modifier can be used for short long and quad The got12 modifier is synonym to got The symbol is added to the GOT The symbol term is replaced with offset from the start of the GOT to the GOT slot for the symbol gotoff The gotoff modifier can be used for short Jong and quad The symbol term is replaced with the offset from the start of the GOT to the address of the symbol gotplt The gotplt modifier can be used for Jong and quad A procedure linkage table entry is generated for the symbol and a jump slot for the symbol is added to the GOT The symbol term is replaced with the offset from the start of the GOT to the jump slot for the symbol plt The plt modifier can be used for l
150. the various native assemblers for these systems which GAS must emulate GAS also provides balign and p2align directives described later which have a consistent behavior across all architectures but are specific to GAS 48 Using as 7 4 altmacro Enable alternate macro mode enabling LOCAL name One additional directive LOCAL is available It is used to generate a string replacement for each of the name arguments and replace any instances of name in each macro expansion The replacement string is unique in the assembly and different for each separate macro expansion LOCAL allows you to write macros that define symbols without fear of conflict between separate macro expansions String delimiters You can write strings delimited in these other ways besides string string You can delimit strings with single quote characters lt string gt You can delimit strings with matching angle brackets single character string escape To include any single character literally in a string even if the character would otherwise have some special meaning you can prefix the character with an exclamation mark For example you can write lt 4 3 gt 5 4 gt to get the literal text 4 3 gt 5 4 Expression results as strings You can write 4expr to evaluate the expression expr and use the result as a string 7 5 ascii string ascii expects zero or more string literals see Section 3 6 1 1 String
151. to attempts to combine two sequential instruc tions into a single parallel instruction where it is legal to do so no parallel This option disables a previously enabled parallel option no bitinst This option disables the support for the extended bit field instructions provided by the M32R2 If this support needs to be re enabled the bitinst switch can be used to restore it 0 This option tells the assembler to attempt to optimize the instructions that it produces This includes filling delay slots and converting sequential instructions into parallel ones This option implies parallel warn explicit parallel conflicts Instructs as to produce warning messages when questionable parallel instruc tions are encountered This option is enabled by default but gcc disables it when it invokes as directly Questionable instructions are those whose be haviour would be different if they were executed sequentially For example the code fragment mv ri r2 mv r3 r1 produces a different result from mv ri r2 n mv r3 r1 since the former moves rl into r3 and then r2 into rl whereas the later moves r2 into r1 and r3 Wp This is a shorter synonym for the warn explicit parallel conflicts option Chapter 9 Machine Dependent Features 173 no warn explicit parallel conflicts Instructs as not to produce warning messages when questionable parallel in structions are encountered Wnp This is a shorter synonym for the no war
152. to avoid confusing them with the instruction operands of the machine language we use the term argument to refer to parts of expressions only reserving the word operand to refer only to machine instruction operands Symbols are evaluated to yield section NNN where section is one of text data bss absolute or undefined NNN is a signed 2 s complement 32 bit integer Numbers are usually integers A number can be a flonum or bignum In this case you are warned that only the low order 32 bits are used and as pretends these 32 bits are an integer You may write integer manipulating instructions that act on exotic constants compatible with other assemblers Subexpressions are a left parenthesis followed by an integer expression followed by a right parenthesis or a prefix operator followed by an argument 6 2 2 Operators Operators are arithmetic functions like or Prefix operators are followed by an argu ment Infix operators appear between their arguments Operators may be preceded and or followed by whitespace 6 2 3 Prefix Operator as has the following prefix operators They each take one argument which must be absolute Negation Two s complement negation Complementation Bitwise not 44 Using as 6 2 4 Infix Operators Infix operators take two arguments one on either side Operators have precedence but operations with equal precedence are performed left to right Apart
153. two half expression Create an aligned constant 2 bytes in size word expression Create an aligned constant 4 bytes in size dword expression Create an aligned constant 8 bytes in size 2byte expression Create an unaligned constant 2 bytes in size 4byte expression Create an unaligned constant 4 bytes in size 8byte expression Create an unaligned constant 8 bytes in size 16byte expression Create an unaligned constant 16 bytes in size set noat Allows assembly code to use at register without warning Macro or relaxation expansions generate warnings Set at Assembly code using at register generates warnings and macro expansion and relaxation are enabled Set nobreak Allows assembly code to use ba and bt registers without warning Set break Turns warnings back on for using ba and bt registers Set norelax Do not replace any branches or calls Chapter 9 Machine Dependent Features 217 Set relaxsection Replace identified out of range branches with jmp sequences default Set relaxsection Replace all branch and call instructions with jmp and callr sequences set Al other set are the normal use 9 30 5 Opcodes as implements all the standard Nios II opcodes documented in the Nios IT Processor Ref erence Handbook including the assembler pseudo instructions 218 Using as 9 31 NS32K Dependent Features 9 31 1 Syntax 9 31 1 1 Special Characters The presence of a appearing anywh
154. will examine the code that G generates for the following C input void callee int int caller int i callee ki return i This example does not show how to throw or catch an exception from assembly code That is a much more complex operation and should always be done in a high level language such as C that directly supports exceptions The code generated by one particular version of G when compiling the example above is _Z6callerv 106 Using as fnstart LFB2 Function supports interworking Q0 args 0 pretend 0 frame 8 Q0 frame needed 1 uses anonymous args 0 stmfd sp fp lr save fp lr LCFIO Setfp fp sp 4 add fp sp 4 LCFI1 pad 8 sub Sp sp 8 LCFI2 sub r3 fp 8 mov r0 r3 bl _Z6calleePi ldr r3 fp 8 mov r0 r3 sub Sp fp 4 ldmfd sp fp lr bx lr LFE2 fnend Of course the sequence of instructions varies based on the options you pass to GCC and on the version of GCC in use The exact instructions are not important since we are focusing on the pseudo ops that are used to generate unwind information An important assumption made by the unwinder is that the stack frame does not change during the body of the function In particular since we assume that the assembly code does not itself throw an exception the only point where an exception can be thrown is from a call such as the b1 instruction above At each call site the same saved
155. with care as producing mixed endian binary files is fraught with danger 9 22 3 M32R Warnings There are several warning and error messages that can be produced by as which are specific to the M32R output of 1st instruction is the same as an input to 2nd instruction is this intentional This message is only produced if warnings for explicit parallel conflicts have been enabled It indicates that the assembler has encountered a parallel in struction in which the destination register of the left hand instruction is used Chapter 9 Machine Dependent Features 175 as an input register in the right hand instruction For example in this code fragment mv r1 r2 neg r3 r1 register rl is the destination of the move instruction and the input to the neg instruction output of 2nd instruction is the same as an input to ist instruction is this intentional This message is only produced if warnings for explicit parallel conflicts have been enabled It indicates that the assembler has encountered a parallel in struction in which the destination register of the right hand instruction is used as an input register in the left hand instruction For example in this code fragment mv ri r2 neg r2 r3 register r2 is the destination of the neg instruction and the input to the move instruction instruction is for the M32RX only This message is produced when the assembler encounters an instruction which is only supported
156. with up to 64K program memory space and greater than 64K data space MCU types atxmega64al atxmega64alu Instruction set avrxmega6 is for the XMEGA AVR core with up to 256K pro gram memory space and less than 64K data space MCU types atxmegal128a3 atxmegal28d3 atxmegal92a3 atxmegal28bl atxmegal92d3 atxmega256a3 atxmega256a3b atxmega256a3bu atxmegal92d3 Instruction set avrxmega7 is for the XMEGA AVR core with up to 256K program memory space and greater than 64K data space MCU types atxmegal28al atxmegal28alu mall opcodes Accept all AVR opcodes even if not supported by mmcu mno skip bug This option disable warnings for skipping two word instructions mno wrap This option reject rjmp rcall instructions with 8K wrap around 9 5 2 Syntax 9 5 2 1 Special Characters The presence of a anywhere on a line indicates the start of a comment that extends to the end of that line If a 4 appears as the first character of a line the whole line is treated as a comment but in this case the line can also be a logical line number directive see Section 3 3 Comments page 27 or a preprocessor control command see Section 3 1 Preprocessing page 27 The character can be used instead of a newline to separate statements 110 Using as 9 5 2 2 Register Names The AVR has 32 x 8 bit general purpose working registers r0 ri r31 Six of the 32 registers can be used as three 16 bit i
157. 0 4 Opcodes For detailed information on the SH64 machine instruction set see SuperH 64 bit RISC Series Architecture Manual SuperH Inc as implements all the standard SH64 opcodes In addition the following pseudo opcodes may be expanded into one or more alternate opcodes movi If the value doesn t fit into a standard movi opcode as will replace the movi with a sequence of movi and shori opcodes pt This expands to a sequence of movi and shori opcode followed by a ptrel opcode or to a pta or ptb opcode depending on the label referenced 254 Using as 9 41 SPARC Dependent Features 9 41 1 Options The SPARC chip family includes several successive versions using the same core instruction set but including a few additional instructions at each version There are exceptions to this however For details on what instructions each variant supports please see the chip s architecture reference manual By default as assumes the core instruction set SPARC v6 but bumps the archi tecture level as needed it switches to successively higher architectures as it encounters instructions that only exist in the higher levels If not configured for SPARC v9 sparc64 GAS will not bump past sparclite by default an option must be passed to enable the v9 instructions GAS treats sparclite as being compatible with v8 unless an architecture is explicitly requested SPARC v9 is always incompatible with sparclite Av6 Av7 Av8
158. 0 XGATE Dependent Features 303 9 50 1 XGATE Option 303 9 50 2 Syntax cocoa deste RR see x ese UO REPERI QE RC PEE 303 9 50 3 Assembler TDi rectiwves 0000 e eee eee eee eee 304 9 50 4 Floating Point eer Ree Rex 304 9 50 25 CODGCOGGS Sessor int bebe EE 305 9 51 XStormy16 Dependent bontures 0c eee ee eee 305 xii xiv 9 bl l Syhiax i eR RIRICLCT RT ERG d ERI Oe 305 9 51 1 1 Special Characters ssssseeeeeeseeeeeeee 305 9 51 2 XStormy16 Machine Directive 305 9 51 3 XStormy16 Pseudo Opcodes 0c eee eee eee 305 9 52 Xtensa Dependent Features 0000 eee eee eee eee ee 306 9 52 1 Command Line Options 0 0 cece eee eee 306 9 52 2 Assembler Syntax 0 00 c cece eects 307 9 52 2 1 Opcode Names 0c cece cece teen e eee 307 9 52 2 2 Register Names esiisa romni t ereid a ee eee eees 308 9 52 38 Xtensa Optimizations 0 0 c cee eee eee eee 308 9 52 3 1 Using Density Instructions 0000 308 9 52 3 2 Automatic Instruction Alignment 308 9 52 4 Xtensa Relaxation cece eee eee eri iine 309 9 52 4 1 Conditional Branch Relaxation 309 9 52 4 2 Function Call Belasation eee 310 9 52 4 3 Other Immediate Field Relaxation 310 9 52 5 DIRECTIVES 2 ise ete Lee ER Ge peteret bab pedes 311 90 52 5 L schedule ue NEEN EEN DEDE 312 9 52 5 2 longeallSesrsrsisssus e mee geet een oe aioe 212 9 52 9 9 DEBIISIOFIL aat svp
159. 00008000 add3 r0 rO f1ow 0x00008000 Produces the correct result in r0 whereas seth r0 shigh 0x00008000 or3 r0 rO low 0x00008000 Stores Oxffff8000 into r0 Note the shigh directive does not know where in the assembly source code the lower 16 bits of the value are going set so it cannot check to make sure that an or3 instruction is being used rather than an add3 instruction It is up to the programmer to make sure that correct directives are used The directive performs a similar thing as the m32r command line option It tells the assembler to only accept M32R instructions from now on An instruc tions from later M32R architectures are refused The directive performs a similar thing as the m32rrz command line option It tells the assembler to start accepting the extra instructions in the M32RX ISA as well as the ordinary M32R ISA The directive performs a similar thing as the m32r2 command line option It tells the assembler to start accepting the extra instructions in the M32R2 ISA as well as the ordinary M32R ISA The directive performs a similar thing as the little command line option It tells the assembler to start producing little endian code and data This option should be used with care as producing mixed endian binary files is fraught with danger The directive performs a similar thing as the big command line option It tells the assembler to start producing big endian code and data This option should be used
160. 010110KKddKKKK 10010111KKddKKKK 10011000pppppsss 10011010pppppsss 10011001pppppsss 10011011pppppsss 1111011111111000 1111001111111000 1111001111111001 1111011111111100 1111011111111101 1111001111111101 1111011111111111 1111001111111111 1111001111111000 ijmp lpm lpm elpm elpm nop ret reti Sleep break wdr spm adc add cp cpc cpse eor mov mul or sbc sub clr Isi rol tst andi cbr ldi ser ori sbr cpi sbci subi sbrc sbrs bld bst in out adiw sbiw Chi sbi sbic sbis brcc brcs breq brge brhc brhs brid brie brlo RN AON HHHHH HH HHHHuH Bx D GO GG BB DH HH HHH HHH HHH HHH H LS SS GGG H D r s Dm mp mp Gi GH mm Nn iii HHH HHH Hi imO OO sg sg mOH HH Using as Chapter 9 Machine Dependent Features 113 1111001111111100 brlt 1111001111111010 brmi 1111011111111001 brne 1111011111111010 brpl 1111011111111000 brsh 1111011111111110 brtc 1111001111111110 brts 1111011111111011 brvc 1111001111111011 brvs 1111011111111sss brbc 1111001111111sss brbs 1101LLLLLLLLLLLL rcall 1100LLLLLLLLLLLL rjmp 1001010hhhhh111h call 1001010hhhhh110h jmp 1001010rrrrr0101 asr 1001010rrrrr0000 com 1001010rrrrri010 dec 1001010rrrrr0011 inc 1001010rrrrr0110 lsr 1001010rrrrr0001 neg 1001000rrrrriiii pop 1001001rrrrriiii push 1001010rrrrr0111 ror 1001010rrrrr0010 swap 00000001ddddrrrr movw 00000010ddddrrrr muls 000000110dddOrrr mulsu 000000110dddirrr fmul 000000111dddOrrr fmuls 000000111
161. 09 the value 011 30 Using as x hex digits A hex character code All trailing hex digits are combined Either upper or lower case x works Represents one character Gn Represents one character Needed in strings to represent this character because an unescaped would end the string anything else Any other character when escaped by gives a warning but assembles as if the was not present The idea is that if you used an escape sequence you clearly didn t want the literal interpretation of the following character However as has no other interpretation so as knows it is giving you the wrong code and warns you of the fact Which characters are escapable and what those escapes represent varies widely among assemblers The current set is what we think the BSD 4 2 assembler recognizes and is a subset of what most C compilers recognize If you are in doubt do not use an escape sequence 3 6 1 2 Characters A single character may be written as a single quote immediately followed by that character The same escapes apply to characters as to strings So if you want to write the character backslash you must write where the first escapes the second As you can see the quote is an acute accent not a grave accent A newline immediately following an acute accent is taken as a literal character and does not count as the end of a statement The value of a character constant in a numeric express
162. 1 mwarn deprecated command line option ARM vr 97 mzarch option s390 0 cece eee eee 231 N command line option CRIS 120 nIp option M32RX eee 173 eno bitinst M32R2 2 2 Su See 172 no ignore parallel conflicts option M32RX TRE 173 no mdebug command line option Alpha 84 no parallel option M32RX 172 no relax option 1900 cert 159 no warn explicit parallel conflicts option MS2EX ences eEEIDPRLDS ER RE RE RUPEE 173 no warn unmatched high option M32R 173 nocpp ignored MIPDZ 196 noreplace command line option Alpha 84 SO ss ee Olas Sees Ree cee eee ERE Oe eats 25 sl option M32EX iss eR eee dr acne 172 parallel option M32RX 172 ziv M P TED T 25 r800 command line option Z80 286 AS Index relax command line option Alpha 84 replace command line option Alpha 84 8 ignored on VAN 291 t ignored on VAX ENEE esas 291 T ignored on VAN 291 l hss teeter aoe ne sbatadiae ed ae hae eee eal 25 V redundant on MAN 291 EE 25 SW DEE 26 warn explicit parallel conflicts option MBIR Ee Ee EE Se 172 warn unmatched high option M32R 173 Wnp option M32RX SEENEN 173 Wnuh option M 2bR ee eee 173 Wp option M32RX siet ae getters eas 172 wsigned overflow command line option V850 EE 295 W h option M32RX ENEE EELER eels 178 w
163. 11 literal L1 2040 132r ai L1 add al a0 al 132i ai ai 0 If the load destination and source address register are the same an out of range offset causes an error The Xtensa ADDI instruction only allows immediate operands in the range from 128 to 127 There are a number of alternate instruction sequences for the ADDI operation First if the immediate is 0 the ADDI will be turned into a MOV N instruction or the equivalent OR instruction if the code density option is not available If the ADDI immediate is outside of the range 128 to 127 but inside the range 32896 to 32639 an ADDMI instruction or ADDMI ADDI sequence will be used Finally if the immediate is outside of this range and a free register is available an L32R ADD sequence will be used with a literal allocated from the literal pool For example addi ab a6 0 addi ab a6 512 addi ab a6 513 addi ab a6 50000 is assembled into the following literal Lt 50000 mov n ab a6 addmi ab a6 0x200 addmi ab a6 0x200 addi ab ab 1 132r ab L1 add ab a6 ab D 9 52 5 Directives The Xtensa assembler supports a region based directive syntax begin directive options fond directive All the Xtensa specific directives that apply to a region of code use this syntax The directive applies to code between the begin and the end The state of the option after the end reverts to what it was before the begin A nested begin end region can
164. 130 mno fix vr4130 Insert nops to work around the VR4130 mflo mfhi errata mfix 24k mno fix 24k Insert nops to work around the 24K eret deret errata mfix cn63xxpi mno fix cn63xxp1 Replace pref hints 0 4 and 6 24 with hint 28 to work around certain CN63XXPI errata m4010 no m4010 Generate code for the LSI R4010 chip This tells the assembler to accept the R4010 specific instructions addciu ffc etc and to not schedule nop instructions around accesses to the HI and LO registers no m4010 turns off this option m4650 no m4650 Generate code for the MIPS R4650 chip This tells the assembler to accept the mad and madw instruction and to not schedule nop instructions around accesses to the HI and LO registers no m4650 turns off this option m3900 no m3900 m4100 no m4100 For each option mnnnn generate code for the MIPS Rnnnn chip This tells the assembler to accept instructions specific to that chip and to schedule for that chip s hazards march cpu Generate code for a particular MIPS CPU It is exactly equivalent to mcpu except that there are more value of cpu understood Valid cpu value are 2000 3000 3900 4000 4010 4100 4111 vr4120 vr4130 vr4181 4300 4400 4600 4650 5000 rm5200 rm5230 rm5231 rm5261 rm5721 vr5400 vr5500 6000 rm7000 8000 rm9000 10000 12000 14000 16000
165. 15 18 NObeSu iie Seek xar Le eed duces dr EEN 155 9 16 Intel i860 Dependent boatures 00 cece cece 156 9 10 1 1860 NGtES eis sie debet pela Hos ado BH Ra 156 9 16 2 1860 Command line Option 156 9 16 2 1 SVRA compatibility option 156 9 16 2 2 Other options 000 c cece e 156 9 16 3 i860 Machine Directive 156 9 16 4 1860 Opcodes Aa es es bee Pn ebbe ERR Oh 157 9 16 4 1 Other instruction support pseudo instructions 157 9 16 5 1860 Syntax cie di epe RUE RERIR RE enn e ER 158 9 16 5 1 Special Characters 0 00 ccc eee eens 158 9 17 Intel 80960 Dependent Features 0 00 cece eee 159 9 17 1 i960 Command line Option 159 9 17 2 Floating Pont veces rro he ERI ER DRE ee 160 9 17 3 1960 Machine Directive 160 9 17 4 1960 Opcodes cde peii ente t e eR E eo Are 161 O IT CN EEN 161 9 17 4 2 CGompare and Branch 0 cece eee eee ee 161 9 17 5 Syntax tor the 1900 5 sess sedge een ERR ele nian 162 9 17 5 1 Special Character 162 9 18 IA 64 Dependent Features 000 ccc cece eee eens 163 OAR OPMONS choc NEE TEE dade Medes aoe ee 163 0 18 2 ERR xac ate sucre ba ord IE RD Ragin cots do ue ban SR 164 9 18 2 1 Special Character 164 9 18 2 2 Register Names drier si eee eee eee eees 164 9 18 2 3 IA 64 Processor Status Register PSR Bit Names em 164 9 18 2 4 Relocations 2e ere et eS res RW xA 164 9 183 XOpCcOdeSu isses toner e de msc RTI Rea due I leone 165 9 19 IP2K Dependent H
166. 157 1860 SUDDOEU EE 156 1960 architecture option 159 1960 branch recording ic rereirrotrpireitirisi 159 1960 ca11j pseudo opcode 161 1960 compare and jump expansions 161 1960 compare branch instructions 161 1960 floating point DEER 160 1960 line comment character 162 1960 line separator 2 cece eee eee 162 i960 machine directives 2 2000s 160 19060 OPCOdES eter Rr MES EES E 161 1960 optionS iler EIL Ex Ra Xe EERARREQRAE RAS 159 1960 SUPPO rassa e die RRIR3RGRG Xe URS ERE 159 IA 64 line comment character 164 IA 64 line separator ssssseesessee 164 IA 64 option 163 IA 64 Processor status Register bit names 164 TA 64 registers Ae ENEE RR RR RR Re 164 TA 64 relocations vectes 164 EE TEEN 163 TAS64 Synt xsesesc seer ebbe Eee v EH PY lees 164 ident directive i sc haateu p bel iere idi 57 identifiers ARM 98 identifiers MSP 430 Lssssusus 212 TE GITECHIVE nov Cenc ps acd enes ata de end PY e 57 E EEN 57 ifc CiTECHVE lesus hi piense ber her ege a 5T ifdef direclive ise es v eR npe RR FE e 5T ifeq dire6UuVve creme RR RI RARE Rx be desiaced 57 ifegs direcblVe cer er ze et epERRPI PE UR 57 Using as lfge directive cese recep e eR RT 57 ifgt directive eners risp ia sede r sirieni eei 57 ifle directive ses sacks saws sens dee 57 iflt directive cic csacendages SEELEN 58 ifnb direc lve isreini a RR ERR Rer NX 58 i
167. 2 D2 I OpCode 4 4 4 4 4 4 4 0 8 12 16 20 32 40 AT RXF format lt insn gt R1 R3 D2 X2 B2 4 4 4 4 4 4 4 4 OpCode R3 X2 B2 D2 R1 OpCode 4 4 4 4 4 4 4 4 0 8 12 16 20 32 36 40 4T RXY format lt insn gt R1 D2 X2 B2 4 4 4 4 4 4 4 OpCode R1 X2 B2 DL2 DH2 OpCode 4 4 4 4 4 4 4 0 8 12 16 20 32 36 40 47 S format lt insn gt D2 B2 4 4 4 OpCode B2 D2 4 4 4 0 16 20 31 SI format lt insn gt D1 B1 12 4 4 4 4 237 238 Using as OpCode 12 B1 D1 4 4 4 4 0 8 16 20 31 SIY format lt insn gt D1 B1 U2 4 4 4 4 4 4 OpCode I2 Bi DL1 DH1 OpCode 4 4 4 4 4 4 0 8 16 20 32 36 40 4T SIL format lt insn gt D1 B1 I2 4 4 4 4 OpCode B1 D1 12 4 4 4 4 0 16 20 32 4T SS format lt insn gt D1 R1 B1 D2 B3 R3 4 4 4 4 4 4 4 OpCode R1 R3 B1
168. 2 y dn d3 32 z dn d4 32 1 vmul x y z This is equivalent to writing the following vmul f32 d2 d3 d4 1 Aliases created using dn or qn can be destroyed using unreq eabi attribute tag value Set the EABI object attribute tag to value The tag is either an attribute number or one of the following Tag CPU raw name Tag CPU name Tag CPU arch Tag CPU arch profile Tag ARM ISA use Tag THUMB ISA use Tag FP arch Tag WMMX arch Tag Advanced SIMD arch Tag PCS config Tag ABI PCS R9 use Tag ABI PCS RW data Tag ABI PCS RO data Tag ABI PCS GOT use Tag ABI PC8 wchar t Tag ABI FP rounding Tag ABI FP denormal Tag ABI FP exceptions Tag ABI FP user exceptions Tag ABI FP number model Tag ABI align needed Tag ABI align preserved Tag ABI enum size Tag ABI HardFP use Tag ABI VFP args Tag ABI WMMX args Tag ABI optimization goals Tag ABI FP optimization goals Tag compatibility Tag CPU unaligned access Tag FP HP extension Tag ABI FP 16bit format Tag MPextension use Tag DIV use Tag nodefaults Tag also compatible with Tag conformance Tag T2EE use Tag Virtualization use The value is either a number string or number string depending on the tag Chapter 9 Machine Dependent Features 101 Note the following legacy values are also accepted by tag Tag_VFP_arch Tag_ ABI align8 needed Tag_ABI_align8_preserved Tag VFP HP extension ev
169. 261 sizes operands i386 000 e cece eee eee 147 sizes operands x86 64 000 e eee eee 147 skip directives ise equ a pru bec we ER Y IARE 72 skip directive M t 181 skip directive SPAD 263 S16b128 directive SH ees eed Ratte ES 72 small data MIPS 5 leer m eri ew 199 SmartMIPS instruction generation override 202 SOM symbol attributes ercsi sr cicsrisrrierai 42 source program scd pee una e eer E e source destination operands i386 147 source destination operands x86 64 147 SP TeGISteL icici aden Sead d ee RR Ree 308 Sp register V850 sc ecsos e aree eda 297 Space directive cale cicarveaigiedeans senses 3 space directive ICH 270 space used maximum for assembly 25 SPARC architectures slseesseesssss 254 Spare constants serrer aeree e pEE REDE 258 348 SPARC data alignment esses 255 SPARC floating point IEEE sss 262 Sparc line comment character 256 Sparc line separator 000 eee eee ee eee 256 SPARC machine d rectives iussus 262 SPARC options 0000 cece eee eens 254 Spare registers scssi bee RERDE RR E bess 256 Sparc relocations eee eee eee eee 259 Sparc size translations eee 261 SIE EE 254 SPARC Syntax ose woadeteewer ere xd POI 255 special characters Most 183 special purpose registers MSP 430 212 sslist directive TIC54X 04 270 ssnolist directive TIC54
170. 296 mex abl eer be Sten Gest puente 229 SM SHOPG ele Ee eae TEES 184 303 mshort double ee eee eee eee 184 303 msign extend enabled command line option M32 bot orsstretes aed yee es wate oe aaa tea 167 msmall data limit 00 cece eee 228 mspliioiemeebRel bide bee RE PRI Perg 9 EXPE 220 msse check option i386 146 msse check option x86 64 146 msse2avx option i386 0 eee 146 msse2avx option HDD 146 SE 196 msyntax option i3886 0 ee 146 msyntax option HDD 146 Dum PE Em 220 mthumb command line option ARM 96 mthumb interwork command line option ARM EE 96 mtune option 380 145 mtune option HDD 145 muse conventional section names 228 muse renesas section names 228 muser enabled command line option LM32 167 mv850 command line option V850 295 mv850any command line option V850 296 mv850e command line option V850 295 mv850e1 command line option V850 295 mv850e2 command line option V850 296 mv850e2v3 command line option V850 296 mv850e2v4 command line option V850 296 mv850e3v5 command line option V850 296 mvxworks pic option MIPS 192 mwarn areg zero option s390 23
171. 4 sh4a and sh dsp insn sets h tick hex Support H 00 style hex constants in addition to 0x00 style 9 39 2 Syntax 9 39 2 1 Special Characters is the line comment character You can use instead of a newline to separate statements If a 4 appears as the first character of a line then the whole line is treated as a comment but in this case the line could also be a logical line number directive see Section 3 3 Comments page 27 or a preprocessor control command see Section 3 1 Preprocessing page 27 Since has no special meaning you may use it in symbol names Chapter 9 Machine Dependent Features 249 9 39 2 2 Register Names You can use the predefined symbols ro r1 r2 r3 r4 r5 rO rT r8 r9 r10 r11 r12 r13 r14 and r15 to refer to the SH registers The SH also has these control registers pr procedure register holds return address pe program counter mach macl high and low multiply accumulator registers sr status register gbr global base register vbr vector base register for interrupt vectors 9 39 2 3 Addressing Modes as understands the following addressing modes for the SH Rn in the following refers to any of the numbered registers but not the control registers Rn Register direct Rn Register indirect Rn Register indirect with pre decrement Rn Register indirect with post
172. 4db2 db3 db6 and db7 e the 2 test registers 4tr6 and rr e the 8 floating point register stack Ast or equivalently Ast 0 Ast 1 Ast 2 hst 3 Ast 4 st 5 st 6 and Ast 7 These registers are overloaded by 8 MMX registers mm0 mm 1 mm2 mm3 mm4 4mm5 4mm6 and Amm e the 8 SSE registers registers xmmO xmm1 xmm2 xmm3 emm A xmmb5 xmm6 and AxmmT7 The AMD x86 64 architecture extends the register set by e enhancing the 8 32 bit registers to 64 bit Arax the accumulator Arbx Arcx Ardx Ardi Arsi rbp the frame pointer Arsp the stack pointer e the 8 extended registers 4r8 4r15 e the 8 32 bit low ends of the extended registers r8d ribd e the 8 16 bit low ends of the extended registers r8w Aribw e the 8 8 bit low ends of the extended registers Ar8b Aribb e the 4 8 bit registers Zeil 4dil 4bpl spl e the 8 debug registers 4db8 Adb15 e the 8 SSE registers xmm8 xmm15 150 Using as 9 15 7 Instruction Prefixes Instruction prefixes are used to modify the following instruction They are used to re peat string instructions to provide section overrides to perform bus lock operations and to change operand and address sizes Most instructions that normally operate on 32 bit operands will use 16 bit operands if the instr
173. 4kc 4km 4kp 4ksc 4kec 4kem 4kep 4ksd m4k m4kp m14k m14kc m14ke m14kec 24kc 24kf2_1 24kf 24kf1_1 24kec 24kef2 1 24kef 24kefl 1 34kc 34kf2_1 34kf 34kf1_1 34kn TAkc 74kf2_1 74kf TAkf1 1 74kf8_2 1004kc 1004kf2_1 1004kf 1004kf1_1 5kc 5kf 20kc 25kf sb1 sbla loongson2e loongson2f loongson3a octeon octeon octeon2 xlr xlp For compatibility reasons nx and bfx are accepted as synonyms for nf1_1 These values are deprecated 196 Using as mtune cpu Schedule and tune for a particular MIPS CPU Valid cpu values are identical to march cpu mabi abi Record which ABI the source code uses The recognized arguments are 32 n32 064 64 and eabi msym32 mno sym32 Equivalent to adding set sym32 or set nosym32 to the beginning of the as sembler input See Section 9 27 3 MIPS Symbol Sizes page 198 nocpp This option is ignored It is accepted for command line compatibility with other assemblers which use it to turn off C style preprocessing With GNU as there is no need for nocpp because the GNU assembler itself never runs the C preprocessor msoft float mhard float Disable or enable floating point instructions Note that by default floating point instructions are always allowed even with CPU targets that don t have support for these instructions msingle float mdouble float Disable or enable double precision floating p
174. 5 1617 8 EB EL Target ARM options mcpu processor extension march architecture textension mfpu floating point format mfloat abi abi meabi ver mthumb EB EL mapcs 32 mapcs 26 mapcs float mapcs reentrant mthumb interwork Lk Target Blackfin options mcpuzprocessor sirevision mfdpic mno fdpic mnopic Target CRIS options underscore no underscore pic N emulation criself emulation crisaout 4march v0_v10 march v10 march v32 march common_v10_v32 Target D10V options 0 Target D30V options O n N Target EPIPHANY options mepiphany mepiphany16 Target H8 300 options h tick hex Target i386 options 32 x32 64 Lal march CPU EXTENSION mtune CPU Target i960 options ACA ACA A ACB ACCI AKA AKB AKC AMC b no relax Target 14 64 options mconstant gp mauto pic milp32 milp64 mlp64 mp64 mle mbe mtune itaniuml mtune itanium2 munwind check warning munwind check error mhint b ok mhint b warning mhint b error x xexplicit xauto xdebug Target IP2K options mip2022 mip2022ext Target M32C options m32c m16c relax h tick hex Target M32R options m32rx no warn explicit parallel conflicts W n p Target M680X0 options LI m68000 m68010 m68020 Target
175. 6 SCORE directives i o eR EIER 246 SCORE line comment character 247 SCORE line separator 0 0 e eee ee 247 SCORE Options Eed ENER IDEA teed 246 SCORE processor 00ccee eri eee eee 246 sdaoff pseudo op VS 301 search path for include suus 22 sect directive TIC54X ssussurursrresrreue 270 section directive COFF version 69 section directive ELF version 70 section directive VRn0 eee ee 299 section override prefixes i386 150 ection Black sre eere 66 68 70 74 section relative addressing 04 34 e 39 sections in messages internal 35 Sections SEN 148 sections e EE 34 sections X86 64 csi ssi e ewe gan er Rer wr 148 seg directive DARC 263 SO QM beten er hb wad a PERE REEERE Goapele hea ade 290 set at directive Nios I 216 set break directive Nios II 216 Seb CDEN oce Eed enee Padi rios id 72 set directive Nios DU 217 set directive TIC54X 0 eee ee eee 270 set noat directive Nios I 216 set nobreak directive Nios I 216 set norelax directive Nios I 216 set relaxall directive Nios II 217 set relaxsection directive Nios II 216 SH addressing modeg eidg 249 347 SH floating point DEER 249 SH line comment character 248 SH line Separa
176. 64 jump optimization csssrsss 4 151 x86 64 jump call return 04 147 x86 64 jump call operands seieiseeen 147 x86 64 memory references 08 150 x86 04 Options RR deer A s 145 x86 64 register operands ssrerrereeres 147 x86 04 regisbers o sa eee erbe reme 149 x86 04 SectIOnS ceo e E DC ORDRE TXRERDRY 148 x86 64 size suffixes 0 00 cece e eee eee 147 x86 64 source destination operands 147 XSO O4 SUPPOTt EE 145 x86 64 syntax compatibility 147 xfloat directive TIC54X cee crcrorrccrrerersi 268 XGATE addressing moden suus 303 XGATE assembler directives suus 304 XGATE floating point 304 XGATE line comment character 303 XGATE line senarator enneren 303 XGATE opcodes 000 eee eee eee 305 XGATE options 0 02 cece e cece 303 XGATE e IR eee eae shes 303 XGATE syntax ices csi e Dey evan aes 303 xlong directive TIORAN c norrsiso roiu ssrmare 269 XStormy16 comment character 305 XStormy16 line comment character 305 XStormy16 line separator cceereeree 305 XStormy16 machine directives 305 XStormy16 Goeudo opcodes 305 XStormyl6 support my 305 Xtensa architecture 0 cece ee eee eee 306 Xtensa assembler syntax crcrerrerreen 307 Xtensa directives cece eee eee eee 311 Xtensa opcode namen 307 Xtensa register namen 308 xword dire
177. 6gcc then byte offset conditional jumps will be promoted when necessary to a two instruction sequence consisting of a conditional jump of the opposite sense around an unconditional jump to the target Following the CPU architecture but not a sub architecture which are those starting with a dot you may specify jumps or nojumps to control automatic promotion of conditional jumps jumps is the default and enables jump promotion All external jumps will be of the long variety and file local jumps will be promoted as necessary see Section 9 15 9 i386 Jumps page 151 nojumps leaves external conditional jumps as byte offset jumps and warns about file local conditional jumps that as promotes Unconditional jumps are treated as for jumps For example arch i8086 nojumps 9 15 18 Notes There is some trickery concerning the mul and imul instructions that deserves mention The 16 32 64 and 128 bit expanding multiplies base opcode Ox 6 extension 4 for mul and 5 for imul can be output only in the one operand form Thus imul 4ebx Aeax does not select the expanding multiply the expanding multiply would clobber the 4edx register and this would confuse gcc output Use imul ebx to get the 64 bit product in hedx eax We have added a two operand form of imul when the first operand is an immediate mode expression and the second operand is a register This is j
178. 7 Global page 56 Operand syntax is a bit stricter with as than mmixal For example you can t say addu 1 2 3 instead you must write addu 1 2 3 210 Using as You can t LOC to a lower address than those already visited i e backwards A LOC directive must come before any emitted code Predefined symbols are visible as file local symbols after use In the ELF file that is the linked mmo file has no notion of a file local symbol Some mapping of constant expressions to sections in LOC expressions is attempted but that functionality is easily confused and should be avoided unless compatibility with mmixal is required A LOC expression to 0x2000000000000000 or higher maps to the data section and lower addresses map to the text section see MMIX loc page 207 The code and data areas are each contiguous Sparse programs with far away LOC directives will take up the same amount of space as a contiguous program with zeros filled in the gaps between the LOC directives If you need sparse programs you might try and get the wanted effect with a linker script and splitting up the code parts into sections see Section 7 99 Section page 69 Assembly code for this to be compatible with mmixal would look something like if 0 LOC away_expression else Section away ax fi as will not execute the LOC directive and mmixal ignores the lines with This construct can be used generally to help compati
179. 7 machine directives XStormy16 305 machine independent directives 47 machine instructions not covered 16 machine relocations Nios IL 215 machine independent owvntaz suus 27 Macro directive 4 qe aie NEEN NEE EEN SEENEN e 62 macro directive IICOR4AX 269 PACT OS DN 62 macros count executed e eee eee 64 Macros KSE 22052400 bet A e 211 macros hIQD4X ccibaebese rbee RE PPP 272 Make ruler eene EEE Ee Ce 25 manual structure and purpose 16 math builtins TICBAX srce hcsceendebsancers 265 Maximum number of continuation lines 23 memory references i386 150 memory references 20 04 150 memory mapped registers TIC54X 213 343 merging text and data sections 25 messages from assembler uusuerrrrrrren 18 Meta architectures 0 0 e eee ee eee 190 Meta line comment character 190 Meta line separator 2 0 c eee eee eee 190 Meta options 2 cece eee eee eee eens 190 Meta r misterg eg sss ee erre nts E YR 190 Meta support Ave ES e dead scence ed 190 MicroBlaze architectures susucucueen 191 MicroBlaze ditectives cere ee ee 191 MicroBlaze line comment character 191 MicroBlaze line separator cscrcceunun 191 MicroBlaze support 191 minus permitted arguments 44 MIPS 32 bit microMIPS instruction generati
180. Appendix A GNU Free Documentation License Version 1 3 3 November 2008 Copyright 2000 2001 2002 2007 2008 Free Software Foundation Inc http fsf org Everyone is permitted to copy and distribute verbatim copies of this license document but changing it is not allowed 0 PREAMBLE The purpose of this License is to make a manual textbook or other functional and useful document free in the sense of freedom to assure everyone the effective freedom to copy and redistribute it with or without modifying it either commercially or non commercially Secondarily this License preserves for the author and publisher a way to get credit for their work while not being considered responsible for modifications made by others This License is a kind of copyleft which means that derivative works of the document must themselves be free in the same sense It complements the GNU General Public License which is a copyleft license designed for free software We have designed this License in order to use it for manuals for free software because free software needs free documentation a free program should come with manuals providing the same freedoms that the software does But this License is not limited to software manuals it can be used for any textual work regardless of subject matter or whether it is published as a printed book We recommend this License principally for works whose purpose is instruction or reference APPLICABIL
181. Both spellings globl and global are accepted for compatibility with other as semblers On the HPPA global is not always enough to make it accessible to other partial programs You may need the HPPA only EXPORT directive as well See Section 9 13 5 HPPA Assembler Directives page 137 7 58 enn attribute tag value Record a GNU object attribute for this file See Chapter 8 Object Attributes page 79 7 59 hidden names This is one of the ELF visibility directives The other two are internal see Section 7 66 internal page 59 and protected see Section 7 90 protected page 67 This directive overrides the named symbols default visibility which is set by their bind ing local global or weak The directive sets the visibility to hidden which means that the symbols are not visible to other components Such symbols are always considered to be protected as well Chapter 7 Assembler Directives 57 7 60 hword expressions This expects zero or more expressions and emits a 16 bit number for each t This directive is a synonym for short depending on the target architecture it may also be a synonym for word 7 61 ident This directive is used by some assemblers to place tags in object files The behavior of this directive varies depending on the target When using the a out object file format as simply accepts the directive for source file compatibility with existing assemblers bu
182. CPU All CPUs supported by the march command line option are also selectable by this directive The original value is restored by set arch default The directive set mipsi6 puts the assembler into MIPS 16 mode in which it will assemble instructions for the MIPS 16 processor Use set nomips16 to return to normal 32 bit mode Traditional MIPS assemblers do not support this directive The directive set micromips puts the assembler into microMIPS mode in which it will assemble instructions for the microMIPS processor Use set nomicromips to return to normal 32 bit mode Traditional MIPS assemblers do not support this directive 9 27 6 Directives to control code generation The directive set insn32 makes the assembler only use 32 bit instruction encodings when generating code for the microMIPS processor This directive inhibits the use of any 16 bit instructions from that point on in the assembly The set noinsn32 directive allows 16 bit instructions to be accepted Traditional MIPS assemblers do not support this directive 9 27 7 Directives for extending MIPS 16 bit instructions By default MIPS 16 instructions are automatically extended to 32 bits when necessary The directive set noautoextend will turn this off When set noautoextend is in effect any 32 bit instruction must be explicitly extended with the e modifier e g li e 4 1000 The directive set autoextend may be used to once again automatically extend instru
183. DB specific debug infor mation and the 68k series machines most of the preprocessing pass and extensive changes in messages c input file c write c K Richard Pixley maintained GAS for a while adding various enhancements and many bug fixes including merging support for several processors breaking GAS up to handle multiple object file format back ends including heavy rewrite testing an integration of the coff and b out back ends adding configuration including heavy testing and verifica tion of cross assemblers and file splits and renaming converted GAS to strictly ANSI C including full prototypes added support for m680 34 0 and cpu32 did considerable work on i960 including a COFF port including considerable amounts of reverse engineering a SPARC opcode file rewrite DECstation rs6000 and hp300hpux host ports updated know assertions and made them work much other reorganization cleanup and lint Ken Raeburn wrote the high level BFD interface code to replace most of the code in format specific I O modules The original VMS support was contributed by David L Kashtan Eric Youngdale has done much work with it since The Intel 80386 machine description was written by Eliot Dresselhaus Minh Tran Le at IntelliCorp contributed some AIX 386 support The Motorola 88k machine description was contributed by Devon Bowen of Buffalo University and Torbjorn Granlund of the Swedish Institute of Computer Science
184. E 1380 ined etre hort tpe E RE 153 S oos rit RUPEE ees eel Laney 153 branch improvement M680x0 182 branch improvement M68HC11 188 branch improvement MAX 293 branch instructions relaxation 309 branch recording i960 00 159 branch statistics table i960 159 branch target alignment 308 break directive TICA4N 269 BSD syntax oeRbesrRepenerbeserpers edges 221 Using as bss directive 1900 cesse e tm net 160 bss directive TICBAX aus tem 267 DSS SECTION EE 34 36 DUG CHET ais eere oer prr ERE REPE URPERTPU 315 DUG TeDoris osenee ee iona na Erana EIER 315 bugs in asgembler eee e eee ee 315 Built in symbols CRIS 000 121 builtin math functions TIC54X 265 builtin subsym functions TIC54X 272 bundle iiie lle esum pecu PR Air EET 49 bundle locked em etre eni Essas 49 bundle align mode directive 49 bundle lock directive llle eee 49 bundle unlock directive lesse eee 49 bus lock prefixes 1386 2 00 2 eee eee 150 BVA DEE 290 byte directive oisi e uera mier erated an 50 byte directive TICA43x 00 eee 267 C c mode directive DIORX 268 C54XDSP_DIR environment variable TIC54X EE 264 call directive Nios H 216 call instructions i3886 e cence 149 call instructions relaxation
185. EGO PRELD PREST PUSHGO STBU STB STCO STHT STOU STSF STTU STT STUNC SYNCD SYNCID can have a value nearby an initial value in place of its second and third operands Here nearby is defined as within the range 0 255 from the initial value of such an allocated register bufferi BYTE 0 0 0 0 0 buffer2 BYTE 0 0 0 0 0 GREG bufferi LDOU 42 buffer2 In the example above the Y field of the LDOUI instruction LDOU with a constant Z will be replaced with the global register allocated for buffer1 and the Z field will have the value 5 the offset from buffer1 to buffer2 The result is equivalent to this code bufferi BYTE 0 0 0 0 0 buffer2 BYTE 0 0 0 0 0 tmpreg GREG bufferi LDOU 42 tmpreg buffer2 buffer1 Global registers allocated with this directive are allocated in order higher to lower within a file Other than that the exact order of register allocation and elimination is undefined For example the order is undefined when more than one file with such directives are linked together With the options x and linker allocated gregs GREG directives for two operand cases like the one mentioned above can be omitted Sufficient global registers will then be allocated by the linker The BYTE directive takes a series of operands separated by a comma If an operand is a string see Sec
186. Examples of suitable formats for Transparent copies include plain ASCII without markup Texinfo input format LaTEX input format SGML or XML using a publicly available DTD and standard conforming simple HTML PostScript or PDF designed for human modification Examples of transparent image formats include PNG XCF and JPG Opaque formats include proprietary formats that can be read and edited only by proprietary word processors SGML or XML for which the DTD and or processing tools are not generally available and the machine generated HTML PostScript or PDF produced by some word processors for output purposes only The Title Page means for a printed book the title page itself plus such following pages as are needed to hold legibly the material this License requires to appear in the title page For works in formats which do not have any title page as such Title Page means the text near the most prominent appearance of the work s title preceding the beginning of the body of the text The publisher means any person or entity that distributes copies of the Document to the public A section Entitled XYZ means a named subunit of the Document whose title either is precisely XYZ or contains XYZ in parentheses following text that translates XYZ in another language Here XYZ stands for a specific section name mentioned below such as Acknowledgements Dedications Endorsements or History To Prese
187. Except for any command line argument that begins with a hyphen is an option Each option changes the behavior of as No option changes the way another option works An option is a followed by one or more letters the case of the letter is important All options are optional Some options expect exactly one file name to follow them The file name may either immediately follow the option s letter compatible with older assemblers or it may be the next command argument GNU standard These two command lines are equivalent as o my object file o mumble s as omy object file o mumble s 1 5 Input Files We use the phrase source program abbreviated source to describe the program input to one run of as The program may be in one or more files how the source is partitioned into files doesn t change the meaning of the source The source program is a concatenation of the text in all the files in the order specified Each time you run as it assembles exactly one source program The source program is made up of one or more files The standard input is also a file 18 Using as You give as a command line that has zero or more input file names The input files are read from left file name to right A command line argument in any position that has no special meaning is taken to be an input file name If you give as no file names it attempts to read one input file from the as standard input which is normally your
188. I field Dependent on the instruction the I field is either signed or unsigned A storage operand consists of an address and a length The address of a storage operands can be specified in any of these ways e The content of a single general R e The sum of the content of a general register called the base register B plus the content of a displacement field D e The sum of the contents of two general registers called the index register X and the base register B plus the content of a displacement field e The sum of the current instruction address and a 32 bit signed immediate field multi plied by two The length of a storage operand can be Implied by the instruction Specified by a bitmask Specified by a four bit or eight bit length field L Specified by the content of a general register The notation for storage operand addresses formed from multiple fields is as follows Dn Bn the address for operand number n is formed from the content of general register Bn called the base register and the displacement field Dn Dn Xn Bn the address for operand number n is formed from the content of general register Xn called the index register general register Bn called the base register and the displacement field Dn Dn Ln Bn the address for operand number n is formed from the content of general regiser Bn called the base register and the displacement field Dn The length of the operand n is specified by the field Ln The base reg
189. ITY AND DEFINITIONS This License applies to any manual or other work in any medium that contains a notice placed by the copyright holder saying it can be distributed under the terms of this License Such a notice grants a world wide royalty free license unlimited in duration to use that work under the conditions stated herein The Document below refers to any such manual or work Any member of the public is a licensee and is addressed as you You accept the license if you copy modify or distribute the work in a way requiring permission under copyright law A Modified Version of the Document means any work containing the Document or a portion of it either copied verbatim or with modifications and or translated into another language A Secondary Section is a named appendix or a front matter section of the Document that deals exclusively with the relationship of the publishers or authors of the Document to the Document s overall subject or to related matters and contains nothing that could fall directly within that overall subject Thus if the Document is in part a textbook of mathematics a Secondary Section may not explain any mathematics The relationship could be a matter of historical connection with the subject or with related matters or of legal commercial philosophical ethical or political position regarding them The Invariant Sections are certain Secondary Sections whose titles are designated as bein
190. KHAT wal addr EE 77 GATS versi n string i ieravad oe E E ERTE Ti 7 119 vtable_entry table offset lees eese riri 7 120 vtable inherit child parent sese sse T 6GI2L warning String Li og EE EE ER AP eX 77 1 122 Weak names ee EEN REENEN eee Ide e deena 77 1 123 weakref alias target cece oki sati tarr ona 78 124 word expressionS o uva eta y eR EE T8 7 125 Deprecated urectves eee eens 78 8 Object Attributes oso e e ows 79 8 1 GNU Object Attributes si eies e cece eee ees 79 8 1 1 Common GNU attributes 0 0 0 eee eee eee 79 8 12 MIPS Attributes 0 00024 sacri EENS QUA oe pee ed T9 8 1 8 PowerPC Attributes eee 80 8 2 Defining New Object Attributes 0 00 cece eee eee 80 9 Machine Dependent Features 81 9 1 AArch64 Dependent Features 82 Old ODUOBS eicere EES 82 9 1 2 Sy EE 82 9 1 2 1 Special Characters ien Re eRRP RERO 82 9 1 2 2 Register Names cic sees eed t ion Det brem eco d oh 82 9 1 2 3 Relocations esi EELER EE EN d ones 82 9 1 3 Floating Point ERE PER 83 9 1 4 AArch64 Machine Directive 83 9 1 5 Opcodes s costes p c petet EE EES 83 9 1 6 Mapping Symbols ent yer eee 83 9 2 Alpha Dependent Features 84 9 2 NOUeScseseeesthee RM SORS E CHR eR Gd ea EE eee RE RE 84 9 2 2 ODUOIIS iere E TE den E PS DR RR 84 DAS dion cuidate ate hse leede See wee eae erer 85 9 2 3 1 Special Characters 06 c cece eee eee eee eee 85 9 2 3 2 Re
191. LS_IE_ADD is requested using tie add H SPARC TLS LE HIX22 is requested using Ztle_hix22 e R SPARC TLS LE LOX10 is requested using tle_lox10 Here are some example TLS model sequences First General Dynamic sethi tgd hi22 symbol 711 add 11 red loiO0 symbol 11 add 17 411 00 tgd add symbol call tls get addr red call symbol nop Local Dynamic sethi tldm hi22 symbol 11 add 11 tldm loiO symbol 11 add 17 11 00 tldm add symbol call tls get addr tldm call symbol nop sethi tldo hix22 symbol 411 xor 11 tldo_lox10 symbol 11 add 00 411 411 tldo_add symbol Initial Exec sethi Arie hi22 symbol 711 add hilt Arie loiO symbol 11 ld 417 411 00 rie ld symbol add hel joen 00 rie add symbol sethi tie_hi22 symbol 11 add li Arie loiO symbol 11 ldx 417 411 00 tie_ldx symbol add g ho0 00 tie add symbol And finally Local Exec sethi tle_hix22 symbol 411 add 11 Atle loxiO symbol 11 add hel Ali 411 When assembling for 64 bit and a secondary constant addend is specified in an address expression that would normally generate an R SPARC L010 relocation the assembler will emit an R SPARC OLO10 instead 9 41 3 5 Size Translations Often it is desirable to write code in an operand size agnostic manner as provides support for this via operand size opcode translations Translations are supported for loads stores
192. M68HC11 options m68hc11 m68hc12 m68hcs12 mm9s12x mm9s12xg mshort mlong mshort double mlong double force long branches short branches strict direct mode print insn syntax print opcodes generate example Target MCORE options jsri2bsr sifilter relax mcpu 210 340 Using as Chapter 1 Overview Target Meta options mcpu cpu mfpu cpu mdsp cpu Target MICROBLAZE options Target MIPS options nocpp EL EB O optimization level g debug level G num KPIC call shared non shared xgot mvxworks pic mabi ABI 32 n32 64 mfp32 mgp32 march CPU mtune CPU mips1 mips2 mips3 mips4 mips5 mips32 mips32r2 mips64 mips64r2 construct floats no construct floats mnan encoding trap no break break no trap mips16 no mips16 mmicromips mno micromips msmartmips mno smartmips mips3d no mips3d mdmx no mdmx mdsp mno dsp mdspr2 mno dspr2 mmt mno mt mmcu mno mcu minsn32 mno insn32 mfix7000 mno fix7000 mfix vr4120 mno fix vr4120 mfix vr4130 mno fix vr4130 mdebug no mdebug mpdr mno pdr Target MMIX options fixed special register names globalize symbols gnu syntax relax no predefined symbols no expand no merge gregs x linker allocated gregs Target Nios II options relax al
193. Options The Motorola 680x0 version of as has a few machine dependent options march architecture This option specifies a target architecture The following architectures are rec ognized 68000 68010 68020 68030 68040 68060 cpu32 isaa isaaplus isab isac and cfv4e mcpu cpu This option specifies a target cpu When used in conjunction with the march option the cpu must be within the specified architecture Also the generic features of the architecture are used for instruction generation rather than those of the specific chip m no 68851 m no 68881 n no div m no usp m no float n no mac n no emac Enable or disable various architecture specific features If a chip or architecture by default supports an option for instance march isaaplus includes the mdiv option explicitly disabling the option will override the default e You can use the 1 option to shorten the size of references to undefined sym bols If you do not use the 1 option references to undefined symbols are wide enough for a full long 32 bits Since as cannot know where these symbols end up as can only allocate space for the linker to fill in later Since as does not know how far away these symbols are it allocates as much space as it can If you use this option the references are only one word wide 16 bits This may be useful if you want the objec
194. R dresis 312 literal pool entries s 200 243 literal position directive 313 literal prefix directe 314 little endian output MIPS 12 little endian output PI 10 little endian output MIPS ssse 192 little endian output TIC6X Lsse 274 LM32 line comment character 169 LM32 line separator se cec nm etr 169 LM32 modifiers ipo b hte irene RR RR 168 LM32 opcode eummara 169 LM32 options none 167 LM32 register namen 167 Using as L M32 SUppOEb nete Rh pesi 167 RE KEE 61 lo directive Nios LL ge e Rex 215 lo pseudo op VS 300 N T 61 loc mark labels directe 62 local common symbols cscs curecsrisricsssenisia 60 local directives sessi ei Rl eene RITU 62 local labels dl p m recipe tat aet edie eras 40 local symbol names rric ccrrecerisincsr rissie 39 local symbols retaining in output 22 location counter 5 2zilek RRE EE 41 location counter adhvancing 65 location counter 280 286 logical hile name ie Rr Rh Rr 55 logical line number 2 e emet 60 logical line numbers 0020005 28 long directive eme emere ets 62 long directive ARC 94 long directive 1386 5 cce ene 152 long directive TIC54X 00 eee 269 long directive 2809 0941 152 longcall pseudo op VS 301 longcalls directive cise e temen 312 longjump pseudo op VS 302 loop directive TICRAX osscrucrerrerr
195. REG base page 208 without a matching GREG directive is treated as an error by as When the option linker allocated gregs Chapter 9 Machine Dependent Features 205 is in effect they are instead passed through to the linker which will allocate as many global registers as is needed 9 28 2 Instruction expansion When as encounters an instruction with an operand that is either not known or does not fit the operand size of the instruction as and 1d will expand the instruction into a sequence of instructions semantically equivalent to the operand fitting the instruction Expansion will take place for the following instructions GETA Expands to a sequence of four instructions SETL INCML INCMH and INCH The operand must be a multiple of four Conditional branches A branch instruction is turned into a branch with the complemented condition and prediction bit over five instructions four instructions setting 255 to the operand value which like with GETA must be a multiple of four and a final GO 255 255 0 PUSHJ Similar to expansion for conditional branches four instructions set 255 to the operand value followed by a PUSHGO 255 255 0 JMP Similar to conditional branches and PUSHJ The final instruction is GO 255 255 0 The linker 1d is expected to shrink these expansions for code assembled with relax though not currently implemented 9 28 3 Syntax The assembly syntax is suppo
196. S SIONS separated by commas For each expression a 32 bit little endian con stant is emitted syntax ARGUMENT The syntax directive takes as ARGUMENT one of the following case sensitive choices no_register_prefix The syntax no_register_prefix directive makes a character prefix on all registers optional It overrides a previous setting in cluding the corresponding effect of the option no underscore 6 9 If this directive is used when ordinary symbols do not have a _ character prefix care must be taken to avoid ambiguities whether 124 Using as an operand is a register or a symbol using symbols with names the same as general or special registers then invoke undefined behavior register_prefix This directive makes a character prefix on all registers manda tory It overrides a previous setting including the corresponding effect of the option underscore leading_underscore This is an assertion directive emitting an error if the no underscore option is in effect no_leading_underscore This is the opposite of the syntax leading_underscore directive and emits an error if the option underscore is in effect arch ARGUMENT This is an assertion directive giving an error if the specified ARGUMENT is not the same as the specified or default value for the march architecture option see march option page 120 Chapter 9 Machine Dependent Features 125 9 9 D10V D
197. Section 9 52 2 1 Opcode Names page 307 the no transform command line op 310 Using as tion see Section 9 52 1 Command Line Options page 306 or the no transform directive see Section 9 52 5 3 transform page 312 9 52 4 2 Function Call Relaxation Function calls may require relaxation because the Xtensa immediate call instructions CALLO CALL4 CALL8 and CALL12 provide a PC relative offset of only 512 Kbytes in either direction For larger programs it may be necessary to use indirect calls CALLXO CALLX4 CALLX8 and CALLX12 where the target address is specified in a register The Xtensa assembler can automatically relax immediate call instructions into indirect call instructions This relaxation is done by loading the address of the called function into the callee s return address register and then using a CALLX instruction So for example call8 func might be relaxed to literal L1 func 132r a8 L1 callx8 a8 Because the addresses of targets of function calls are not generally known until link time the assembler must assume the worst and relax all the calls to functions in other source files not just those that really will be out of range The linker can recognize calls that were unnecessarily relaxed and it will remove the overhead introduced by the assembler for those cases where direct calls are sufficient Call relaxation is disabled by default because it can have a negative effect on both code size an
198. TX wes nessenemeierRmtt re E ea eee 204 force long bra ches sic ssrinrrrssrsnnnia 185 generate example 0c cee eee 185 globalize symbols command line option IMIMITX ere AE 204 gnu syntax command line option MMIX 204 hash size number esses eese 7 linker allocated gregs command line option MMIX base Sg AE d 204 Jisting cont lineS lm ees 23 listing Ihs width 0 bI ER one 23 listing lhs width2 22 ss ens 23 listing rhs width iil gud ku yh 23 keet E GER 248 SHHONG CALLS EE 306 march architecture command line option CRIS cases 120 MD cc ahs detect ipie idv tuer d Ses Gus 25 mul bug abort command line option CRIS ETT em 120 330 no expand command line option MMIX 204 no long6alls 2 24 eR RR aded 306 no merge gregs command line option MMIX EE 204 no mul bug abort command line option CRIS EE 120 no predefined syms command line option CC 204 no pushj stubs command line option MMIX pL ES 204 no stubs command line option MMIX 204 no target align i i n e AE 306 no text section literals 306 no transfOrm i ck ca gu xd EREE SEEEN 306 no underscore command line option CRIS c PEP ES 120 CCDO WAIBR ua adu Xa Xe RUE YA RE TRAE REE ee 26 pire DEE 177 pic command line option CRIS
199. The absolute literals and no absolute literals directives control the absolute vs PC relative mode for L32R instructions T hese are relevant only for Xtensa configurations that include the absolute addressing option for L32R instructions begin no absolute literals end no absolute literals These directives do not change the L32R mode they only cause the assembler to emit the appropriate kind of relocation for L32R instructions and to place the literal values in the appropriate section To change the L32R mode the program must write the LITBASE special register It is the programmer s responsibility to keep track of the mode and indicate to the assembler which mode is used in each region of code If the Xtensa configuration includes the absolute L32R addressing option the default is to assume absolute L32R addressing unless the no absolute literals command line option is specified Otherwise the default is to assume PC relative L32R addressing The absolute literals directive can then be used to override the default determined by the command line options Chapter 10 Reporting Bugs 315 10 Reporting Bugs Your bug reports play an essential role in making as reliable Reporting a bug may help you by bringing a solution to your problem or it may not But in any case the principal function of a bug report is to help the entire community by making the next version of as work better Bug reports are your contribution to the main
200. This chapter covers features of the GNU assembler that are specific to the Xtensa architec ture For details about the Xtensa instruction set please consult the Xtensa Instruction Set Architecture ISA Reference Manual 9 52 1 Command Line Options text section literals no text section literals Control the treatment of literal pools The default is no text section literals which places literals in separate sections in the output file This allows the literal pool to be placed in a data RAM ROM With text section literals the literals are interspersed in the text section in order to keep them as close as possible to their references This may be necessary for large assembly files where the literals would otherwise be out of range of the L32R instructions in the text section These options only affect literals referenced via PC relative L32R instructions literals for absolute mode L32R instructions are handled separately See Section 9 52 5 4 literal page 312 absolute literals no absolute literals Indicate to the assembler whether L32R instructions use absolute or PC relative addressing If the processor includes the absolute addressing option the default is to use absolute L32R relocations Otherwise only the PC relative L32R relo cations can be used target align no target align Enable or disable automatic alignment to reduce branch penalties at some ex pense in code size See Section 9 52 3 2 Auto
201. Using as The GNU Assembler GNU Binutils Version 2 24 0 The Free Software Foundation Inc thanks The Nice Computer Company of Australia for loaning Dean Elsner to write the first Vax version of as for Project GNU The proprietors management and staff of TNCCA thank FSF for distracting the boss while they got some work done Dean Elsner Jay Fenlason amp friends Using as Edited by Cygnus Support Copyright 1991 2013 Free Software Foundation Inc Permission is granted to copy distribute and or modify this document under the terms of the GNU Free Documentation License Version 1 3 or any later version published by the Free Software Foundation with no Invariant Sections with no Front Cover Texts and with no Back Cover Texts A copy of the license is included in the section entitled GNU Free Documentation License Table of Contents l Overview 3 Lodel ew aioe 1 Ll Structure of this Mangal ae A erre temere xe 16 1 2 The GNU Assembler 0 00 ccc cece eee eee 17 L3 Object Pile Beats lt tc Nee NEIER tme ex ate A 17 LA Command Le 2 gsnsesdnx ees dege EE Ee Fr Input Ple8 er Fos RRSUREE REN ON Ec Ee a ee kes 17 Lo Outp t Object Bien E ERR E A ee kai erui 18 1 7 Error and Warning Messages sss 18 2 Command Line Options 21 2 1 Enable Listings alcdghlns 0 eee eee 21 2 2 alternate ico re LS P AE PED 21 2 9 eeh 22 2 4 Work Paster Za d
202. V850 opcodes 0 cece cece eee tenn eees 300 V850 options none 295 V850 register namen 297 300 V 850 SUDDOELU exper rte a anita AN 295 val directives serso nrerin n r E Enee AREETA Tr value attribute COFF uuessss Fa value of a symbol cer remet 41 var directive TIC54X 0 eee eee 272 VAX bitfields not supported 295 VAX branch improvement 05 293 VAX command line options ignored 291 VAX displacement sizing character 294 VAX floating point 292 VAX immediate character 294 VAX indirect character 294 VAX line comment character 295 VAX line separator 20 e eee eee ee 295 VAX machine directives 0 200005 292 VAX opcode mnemoniecn s s s ees enere 293 VAX operand notation 00 00 294 VAX register NAMES sssssrrrerrererrere 295 ER ct dueeedee neato sterner des 291 Vax 11 C compatibility ENEE 291 VAXJ VMS options s6ss re Rp 291 version direciive issseninednie e E el i REED 77 version directive TIC54X 0 212 version of assembler 000s ee eeee 25 versions of Symbols 34 erre rl b eh aus 74 Virtualization instruction generation override TT 202 Visibility 42 22 slkaen rk ee poU RARI 56 59 67 VMS VAX optiong reerdrersrd vrrirees 291 vtable_entry directe 77 vtable_inherit d rective lesse sess 77 W Warning directive cis eL Y Rev ENEE ee warning
203. V9 floating point registers state is referred to as Afprs e The V9 version register is referred to as hver e The V9 window state register is referred to as 4 wstate e The Y register is referred to as Ay e The V8 window invalid mask register is referred to as wim e The V8 processor state register is referred to as per e The V9 global register level register is referred to as Ag1 Several special register names exist for hypervisor mode code e The hyperprivileged processor state register is referred to as hpstate e The hyperprivileged trap state register is referred to as htstate e The hyperprivileged interrupt pending register is referred to as Ahintp e The hyperprivileged trap base address register is referred to as 4htba e The hyperprivileged implementation version register is referred to as Ahver e The hyperprivileged system tick compare register is referred to as Ahstick cmpr Note that there is no A4hstick register the normal stick is used 258 Using as 9 41 3 3 Constants Several Sparc instructions take an immediate operand field for which mnemonic names exist Two such examples are membar and prefetch Another example are the set of V9 memory access instruction that allow specification of an address space identifier The membar instruction specifies a memory barrier that is the defined by the operand which is a bitmask The supported mask mnemonics are Sync
204. X 270 Stabd directive c uis hgadeed sincere Sage ROS ad 73 Stabn directive eec pere ss Scere eisa 73 Stabs directive i e ele entera T3 Stabs directives osse p Re p Snn SERAS Etas T3 standard assembler sections 33 standard input as input file L7 statement separator character 28 statement separator AArch64 82 statement separator Alpha 85 statement separator ARC 91 statement separator ARM 98 statement separator AND 109 statement separator CR16 119 statement separator Epiphany 133 statement separator HS 200 134 statement separator 13886 006 148 statement separator i860 0 158 statement separator 1960 0 162 statement separator IA 24 164 statement separator IP2K 166 statement separator LM32 169 statement separator M32C Gei statement separator M68HC11 185 statement separator Meta 190 statement separator MicroBlaze 191 statement separator MIPS 203 statement separator MSP 430 211 statement separator NS32K 218 statement separator DI 223 statement separator PowerPC 226 statement separator RL78 227 statement separator HX 230 statement separator s390 0 231 st
205. X mode This mode is similar to m68hc12 but specifies to assemble for the S12X series which is a superset of the HCS12 This option switches the assembler into the XGATE mode for the RISC co processor featured on some 12X family chips xgate ramoffset mshort mlong This option instructs the linker to offset RAM addresses from S12X address space into XGATE address space This option controls the ABI and indicates to use a 16 bit integer ABI It has no effect on the assembled instructions This is the default This option controls the ABI and indicates to use a 32 bit integer ABI mshort double This option controls the ABI and indicates to use a 32 bit float ABI This is the default mlong double This option controls the ABI and indicates to use a 64 bit float ABI strict direct mode You can use the strict direct mode option to disable the automatic trans lation of direct page mode addressing into extended mode when the instruction does not support direct mode For example the clr instruction does not sup port direct page mode addressing When it is used with the direct page mode as will ignore it and generate an absolute addressing This option prevents as from doing this and the wrong usage of the direct page mode will raise an error Chapter 9 Machine Dependent Features 185 short branches The short branches option turns off the translation of relative branches into absolute
206. a aren reei 166 IP2K OopUlOnDs 2 cce Ee See Ee 166 IP2K support ad EN St SEENEN hn 166 irp directive is e eer cies RE RE camels 59 irpc directive isses bebe Re wey ai 59 ISA options SOHO annann 251 J joining text and data sections 25 jump instructions 1290 149 jump instructions x86 64 149 jump optimization 1290 151 jump optimization HDD 151 jump call operands 290 147 jump call operands x86 64 0005 147 L L16SI instructions relaxation 310 L16UI instructions relaxation 310 L32I instructions relaxation 310 L8UI instructions relaxation 310 label 5j Rb eb Garand teas pede aria EDU ES 29 label directive TIOB4N 269 UE TEE 39 lconm directive Ee il p eec Ret Ere 60 lcomm directive COFF ssusus 147 ld ilivbvessseeepebRreenerg eases Pew REIS I 18 ldouble directive Most 181 ldouble directive M68HC11 188 ldouble directive SOATE enn 304 ldouble directive TIC54X sssuss 268 LDR reg lt expr gt pseudo op AArch64 83 LDR reg lt label gt pseudo op ARM 104 leafproc directive 1000 160 length directive TIODAN 269 length of symbols cero rem emet 28 lflags directive ignored suueuuue 60 line comment character 27 341 line comment character AArch64 82 line comment character Alpha
207. a comment This is an ordinary comment 42 6 new_file_name New logical file name This is logical line 36 This feature is deprecated and may disappear from future versions of as 3 4 Symbols A symbol is one or more characters chosen from the set of all letters both upper and lower case digits and the three characters _ On most machines you can also use in symbol names exceptions are noted in Chapter 9 Machine Dependencies page 81 No symbol may begin with a digit Case is significant There is no length limit all characters are significant Multibyte characters are supported Symbols are delimited by characters not in that set or by the beginning of a file since the source program must end with a newline the end of a file is not a possible symbol delimiter See Chapter 5 Symbols page 39 3 5 Statements A statement ends at a newline character n or a line separator character The line separator character is target specific and described in the Syntax section of each target s documentation Not all targets support a line separator character The newline or line separator character is considered to be part of the preceding statement Newlines and separators within character constants are an exception they do not end statements It is an error to end any statement with end of file the last character of any input file should be a newline An empty statement is allowed and may include whitespa
208. accepted or the command line options msoft float and mhard float The directives set singlefloat and set doublefloat provide finer control of dis abling and enabling double precision float point operations These directives always over ride the default that double precision operations are accepted or the command line options msingle float and mdouble float Traditional MIPS assemblers do not support these directives 9 27 13 Syntactical considerations for the MIPS assembler 9 27 13 1 Special Characters The presence of a on a line indicates the start of a comment that extends to the end of the current line Chapter 9 Machine Dependent Features 203 If a 4 appears as the first character of a line the whole line is treated as a comment but in this case the line can also be a logical line number directive see Section 3 3 Comments page 27 or a preprocessor control command see Section 3 1 Preprocessing page 27 The character can be used to separate statements on the same line 204 Using as 9 28 MMIX Dependent Features 9 28 1 Command line Options The MMIX version of as has some machine dependent options When fixed special register names is specified only the register names speci fied in Section 9 28 3 3 MMIX Regs page 206 are recognized in the instructions PUT and GET You can use the globalize symbols to make all symbols global This option is
209. acement into the literal pool using the current base register as last declared with the using directive 9 14 4 Floating Point The assembler generates only IEEE floating point numbers The older floating point formats are not supported 9 14 5 ESA 390 Assembler Directives as for the ESA 390 supports all of the standard ELF SVRA assembler directives that are documented in the main part of this documentation Several additional directives are supported in order to implement the ESA 390 addressing model The most important of these are using and ltorg These are the additional directives in as for the ESA 390 dc A small subset of the usual DC directive is supported drop regno Stop using regno as the base register The regno must have been previously declared with a using directive in the same section as the current section ebcdic string Emit the EBCDIC equivalent of the indicated string The emitted string will be null terminated Note that the directives string etc emit ascii strings by default EQU The standard HLASM style EQU directive is not supported however the stan dard as directive equ can be used to the same effect ltorg Dump the literal pool accumulated so far begin a new literal pool The literal pool will be written in the current section in order to generate correct assembly a using must have been previously specified in the same section using expr regno Use regno as the base register for all s
210. ad Local Storage ltorg This directive causes the current contents of the literal pool to be dumped to the current location Section 9 37 3 8 s390 Literal Pool Entries page 243 machine string This directive allows you to change the machine for which code is generated string may be any of the march selection options without the march push or pop machine push saves the currently selected cpu which may be restored with machine pop Be aware that the cpu string has to be put into double quotes in case it contains characters not appropriate for identifiers So you have to write z9 109 instead of just z9 109 machinemode string This directive allows to change the architecture mode for which code is be ing generated string may be esa zarch zarch_nohighgprs push or pop machinemode zarch nohighgprs can be used to prevent the highgprs flag from being set in the ELF header of the output file T his is useful in situations where the code is gated with a runtime check which makes sure that the code is only executed on kernels providing the highgprs feature machinemode push saves the currently selected mode which may be restored with machinemode pop 9 37 5 Floating Point The assembler recognizes both the IEEE floating point instruction and the hexadecimal floating point instructions The floating point constructors float single and double always emit the IEEE format To assemble hexadecimal
211. al versions 8 and 9 as well as most extensions defined by Sun for their UltraSPARC and Niagara line of processors 256 Using as 9 41 3 1 Special Characters A l character appearing anywhere on a line indicates the start of a comment that extends to the end of that line If a appears as the first character of a line then the whole line is treated as a comment but in this case the line could also be a logical line number directive see Section 3 3 Comments page 27 or a preprocessor control command see Section 3 1 Preprocessing page 27 can be used instead of a newline to separate statements 9 41 3 2 Register Names The Sparc integer register file is broken down into global outgoing local and incoming e The 8 global registers are referred to as hgn e The 8 outgoing registers are referred to as fon e The 8 local registers are referred to as ln e The 8 incoming registers are referred to as Zin e The frame pointer register i6 can be referenced using the alias fp e The stack pointer register 406 can be referenced using the alias Asp Floating point registers are simply referred to as 4fn When assembling for pre V9 only 32 floating point registers are available For V9 and later there are 64 but there are restrictions when referencing the upper 32 registers They can only be accessed as double or quad and thus only even or quad numbered accesses are
212. aligns the output to an even byte boundary This directive is identical to a space directive Select the target architecture and extension features Valid values for name are the same as for the march command line option This directive cannot be specified after any instructions have been assembled If it is given multiple times or in conjunction with the march option all uses must be for the same architecture and extension set Select the target cpu Valid valuse for name are the same as for the mcpu command line option This directive cannot be specified after any instructions have been assembled If it is given multiple times or in conjunction with the mopt option all uses must be for the same cpu 182 Using as 9 23 6 Opcodes 9 23 6 1 Branch Improvement Certain pseudo opcodes are permitted for branch instructions They expand to the shortest branch instruction that reach the target Generally these mnemonics are made by substi tuting j for b at the start of a Motorola mnemonic The following table summarizes the pseudo operations A flags cases that are more fully described after the table jbsr jra jXX Displacement n 68020 68000 10 not PC relative OK Pseudo Op BYTE WORD LONG ABSOLUTE LONG JUMP KE n jbsr bsrs bsrw bsrl jsr jra bras braw bral jmp jXX bXXs bXXw bXXl bNXs jmp dbXX N A dbXXw dbXX bras bral dbXX bras jmp jXX N A fbXXw fbXXl N A condit
213. all characters up to the end of the line to be ignored A character is handled as a line separator equivalent to a logical new line character except in a comment so separate instructions can be specified on a single line 9 8 4 2 Symbols in position independent code When generating position independent code SVR4 PIC for use in cris axis linux gnu or crisv32 axis linux gnu shared libraries symbol suffixes are used to specify what kind of run time symbol lookup will be used expressed in the object as different relocation types Usually all absolute symbol values must be located in a table the global offset table leaving the code position independent independent of values of global symbols and independent of the address of the code The suffix modifies the value of the symbol into for example an index into the global offset table where the real symbol value is entered or a PC relative value or a value relative to the start of the global offset table All symbol suffixes start with the character omitted in the list below Every symbol use in code or a read only section must therefore have a PIC suffix to enable a useful shared library to be created Usually these constructs must not be used with an additive constant offset as is usually allowed i e no 4 as in symbol 4 is allowed This restriction is checked at link time not at assembly time GOT Attaching this suffix to a symbol in an instruction causes the symbol to
214. allowed For example 4 34 is a legal floating point register but 35 is not Certain V9 instructions allow access to ancillary state registers Most simply they can be referred to as 4asrn where n can be from 16 to 31 However there are some aliases defined to reference ASR registers defined for various UltraSPARC processors e The tick compare register is referred to as 4tick cmpr e The system tick register is referred to as hstick An alias sys tick exists but is deprecated and should not be used by new software e The system tick compare register is referred to as 4stick cmpr An alias Sys tick cmpr exists but is deprecated and should not be used by new software e The software interrupt register is referred to as Asoftint e The set software interrupt register is referred to as jeet softint The mnemonic hsoftint setis provided as an alias e The clear software interrupt register is referred to as Aclear softint The mnemonic hsoftint clear is provided as an alias e The performance instrumentation counters register is referred to as Apic e The performance control register is referred to as pcr e The graphics status register is referred to as Agsr e The V9 dispatch control register is referred to as ider Various V9 branch and conditional move instructions allow specification of which set of integer condition codes to test These are referred to as 4xcc and ice Cha
215. ame GP as the source object file and it must be declared to either not use 27 or perform a standard GP load in the first two instructions via the prologue directive Used with an lda instruction to load the address of a TLS descriptor for a symbol in the GOT The sequence number N is optional and if present it used to pair the descriptor load with both the literal loading the address of the __tls_get_addr function and the lituse_tlsgd marking the call to that function For proper relaxation both the t1sgd literal and lituse relocations must be in the same extended basic block That is the relocation with the lowest address must be executed first at runtime Used with an 1da instruction to load the address of a TLS descriptor for the current module in the GOT Similar in other respects to t1sgd Used with an 1dq instruction to load the offset of the TLS symbol within its module s thread local storage block Also known as the dynamic thread pointer offset or dtp relative offset Like gprel relocations except they compute dtp relative offsets Used with an ldq instruction to load the offset of the TLS symbol from the thread pointer Also known as the tp relative offset Like gprel relocations except they compute tp relative offsets 9 2 4 Floating Point The Alpha family uses both IEEE and VAX floating point numbers 9 2 5 Alpha Assembler Directives as for the Alpha supports many additional directives for compatibility with
216. ame effect A colon may immediately follow a label definition This is simply for compatibility with how most assembly language programmers write code is the line comment character can be used instead of a newline to separate statements Since has no special meaning you may use it in symbol names Registers can be given the symbolic names r0 r15 fm fp2 fp4 fp6 By using thesse symbolic names as can detect simple syntax errors The name rarg or r arg is a synonym for r11 rtca or r tca for r12 sp r sp dsa r dsa for r13 lr or r Ir for r14 rbase or r base for r3 and rpgt or r pgt for r4 is the current location counter Unlike it is always relative to the last USING di rective Note that this means that expressions cannot use multiplication as any occurrence of will be interpreted as a location counter All labels are relative to the last USING Thus branches to a label always imply the use of base displacement Many of the usual forms of address constants address literals are supported Thus using r3 L r 5 A some routine LM r6 r7 V some longlong extern A ri F 12 AH r0 H 42 ME r6 E 3 1416 MD r6 D 3 14159265358979 Chapter 9 Machine Dependent Features 143 0 r6 XL4 cacad0d0 ltorg should all behave as expected that is an entry in the literal pool will be created or reused if it already exists and the instruction operands will be the displ
217. an select big endian or little endian output at run time unlike the other GNU development tools which must be configured for one or the other Use EB to select big endian output and EL for little endian KPIC Generate SVR4 style PIC This option tells the assembler to generate SVR4 style position independent macro expansions It also tells the assembler to mark the output file as PIC mvxworks pic Generate VxWorks PIC This option tells the assembler to generate VxWorks style position independent macro expansions mipsi mips2 mips3 mips4 mipsb5 mips32 mips32r2 mips64 mips64r2 Generate code for a particular MIPS Instruction Set Architecture level mipsi corresponds to the R2000 and R3000 processors mips2 to the R6000 processor mips3 to the R4000 processor and mips4 to the R8000 and R10000 processors mips5 mips32 mips32r2 mips64 and mips64r2 correspond to generic MIPS V MIPS32 MIPS32 Release 2 MIPS64 and MIPS64 Release 2 ISA processors respectively You can also switch instruction sets during the assembly see Section 9 27 5 MIPS ISA page 199 mgp32 mfp32 Some macros have different expansions for 32 bit and 64 bit registers The register sizes are normally inferred from the ISA and ABI but these flags force a certain group of registers to be treated as 32 bits wide at all times mgp32 Chapter 9 Machine Dependent
218. ansform Transformations are enabled by default unless the no transform option is used The transform directive overrides the default determined by the command line options An underscore opcode prefix disabling transformation of that opcode always takes precedence over both directives and command line flags 9 52 5 4 literal The literal directive is used to define literal pool data i e read only 32 bit data accessed via L32R instructions literal label value value This directive is similar to the standard word directive except that the actual location of the literal data is determined by the assembler and linker not by the position of the literal directive Using this directive gives the assembler freedom to locate the literal data in the most appropriate place and possibly to combine identical literals For example the code entry sp 40 literal L1 sym 132r a4 L1 can be used to load a pointer to the symbol sym into register a4 The value of sym will not be placed between the ENTRY and L32R instructions instead the assembler puts the data in a literal pool Chapter 9 Machine Dependent Features 313 Literal pools are placed by default in separate literal sections however when using the text section literals option see Section 9 52 1 Command Line Options page 306 the literal pools for PC relative mode L32R instructions are placed in the current section These text section literal pools a
219. ant octa 0x123456789abcdef0123456789ABCDEFO A bignum float 0f 314159265358979323846264338327N 95028841971 693993751E 40 pi a flonum 3 6 1 Character Constants There are two kinds of character constants A character stands for one character in one byte and its value may be used in numeric expressions String constants properly called string literals are potentially many bytes and their values may not be used in arithmetic expressions 3 6 1 1 Strings A string is written between double quotes It may contain double quotes or null characters The way to get special characters into a string is to escape these characters precede them with a backslash character For example represents one backslash the first is an escape which tells as to interpret the second character literally as a backslash which prevents as from recognizing the second as an escape character The complete list of escapes follows b Mnemonic for backspace for ASCII this is octal code 010 f Mnemonic for FormFeed for ASCII this is octal code 014 n Mnemonic for newline for ASCII this is octal code 012 r Mnemonic for carriage Return for ASCII this is octal code 015 t Mnemonic for horizontal Tab for ASCII this is octal code 011 digit digit digit An octal character code The numeric code is 3 octal digits For compatibility with other Unix systems 8 and 9 are accepted as digits for example 008 has the value 010 and 0
220. any un documented instructions as errors forbid undocumented instructions Fud Treat all undocumented z80 instructions as errors forbid unportable instructions Fup Treat undocumented z80 instructions that do not work on R800 as errors r800 Produce code for the R800 processor The assembler does not support undoc umented instructions for the R800 In line with common practice as uses Z80 instruction names for the R800 processor as far as they exist 9 46 2 Syntax The assembler syntax closely follows the Z80 family CPU User Manual by Zilog In expressions a single may be used as is equal to comparison operator Suffices can be used to indicate the radix of integer constants H or h for hexadecimal D or d for decimal Q 0 q or o for octal and B for binary The suffix b denotes a backreference to local label 9 46 2 1 Special Characters The semicolon is the line comment character If a 4 appears as the first character of a line then the whole line is treated as a comment but in this case the line could also be a logical line number directive see Section 3 3 Comments page 27 or a preprocessor control command see Section 3 1 Preprocessing page 27 The Z80 assembler does not support a line separator character The dollar sign can be used as a prefix for hexadecimal numbers and as a symbol deno
221. are omitted then the first register is taken as the base register and the second as the index register Postindex number apc register size scale onumber The onumber or the register or both may be omitted Either the number or the apc may be omitted but not both Chapter 9 Machine Dependent Features 181 Preindex C number apc register size scale onumber The number or the apc or the register or any two of them may be omitted The onumber may be omitted The register and the apc may appear in either order If both apc and register are address registers and the size and scale are omitted then the first register is taken as the base register and the second as the index register 9 23 4 Floating Point Packed decimal P format floating literals are not supported Feel free to add the code The floating point formats generated by directives are these float double extend double Single precision floating point constants Double precision floating point constants Extended precision long double floating point constants 9 23 5 680x0 Machine Directives In order to be compatible with the Sun assembler the 680x0 assembler understands the following directives datal data2 even Skip arch name cpu name This directive is identical to a data 1 directive This directive is identical to a data 2 directive This directive is a special case of the align directive it
222. art of a comment that extends to the end of that line If a 4 appears as the first character of a line then the whole line is treated as a comment but in this case the line could also be a logical line number directive see Section 3 3 Comments page 27 or a preprocessor control command see Section 3 1 Preprocessing page 27 The character can be used instead of a newline to separate statements Either or can be used to indicate immediate operands TODO Explain about data modifier on symbols 9 4 2 3 Register Names TODO Explain about ARM register naming and the predefined names 9 4 2 4 ARM relocation generation Specific data relocations can be generated by putting the relocation name in parentheses after the symbol name For example word foo TARGET1 This will generate an R_ARM_TARGET1 relocation against the symbol foo The following relocations are supported GOT GOTOFF TARGET1 TARGET2 SBREL TLSGD TLSLDM TLSLDO TLSDESC TLSCALL GOTTPOFF GOT_PREL and TPOFF For compatibility with older toolchains the assembler also accepts PLT after branch targets On legacy targets this will generate the deprecated R_ARM_PLT32 relocation On EABI targets it will encode either the R_ARM_CALL or R_ARM_JUMP24 relocation as appropriate Chapter 9 Machine Dependent Features 99 Relocations for MOVW and MOVT instructions can be generated by prefixing the value with
223. atement char a he said it s 50 off is represented in Z8000 assembly language shown with the assembler output in hex at the left as Chapter 9 Machine Dependent Features 291 68652073 sval he said 22it 27s 50 25 off 422 400 61696420 22697427 73203530 25206F66 662200 rsect synonym for section block synonym for space even special case of align aligns output to even byte boundary 9 47 4 Opcodes For detailed information on the Z8000 machine instruction set see Z8000 Technical Manual 9 48 VAX Dependent Features 9 48 1 VAX Command Line Options The Vax version of as accepts any of the following options gives a warning message that the option was ignored and proceeds These options are for compatibility with scripts designed for other people s assemblers D Debug S Symbol Table T Token Trace These are obsolete options used to debug old assemblers d Displacement size for JUMPs This option expects a number following the d Like options that expect file names the number may immediately follow the d old standard or constitute the whole of the command line argument that follows d GNU standard V Virtualize Interpass Temporary File Some other assemblers use a temporary file This option commanded them to keep the information in active memory rather than in a disk file as always does this so this option is redundant J JUMPify Longer Branches Many 32 b
224. atement separator SCORE 247 statement separator SH 00 248 statement separator SH64 251 statement separator Sparc 0005 256 statement separator TIC54X 213 statement separator TICo3x 274 statement separator V8D0 297 statement separator MAX 295 statement separator XGATE 303 statement separator XStormy16 305 Using as statement separator 280 286 statement separator Z8000 04 289 statements structure of 28 statistics about assembly sucrcrercrcre 25 stopping the assembly 0 204 AT string constants weve eee ce cae eee cee e me 29 String directive iiie d Re t Re Ne T4 string directive on HPPA 139 string directive TIC54X 006 270 string literals teg deele deiere Se 48 string copying to object De 74 String lG directives sser d dele eer per a 74 string16 copying to object file 74 string32 directive ciere ree br n 74 string32 copying to object file 74 string64 directive EE trr e een 74 string64 copying to object Die 74 Strings GirectiVe seu sissies cs ceered pias ears 74 string8 copying to object De 74 Struct GiPECtiVEs eer ser Rb E E RE ERES 74 struct directive TIONAL 271 structure debugging COFF 75 sub instruction ordering D10V 126 sub instru
225. atmega644pa atmega645 atmega645a atmega645p atmega6450 atmega6450a atmega6450p atmega649 atmega649a atmega649p atmega6490 atmega6490a atmega6490p atmega64rfr2 atmega644rfr2 atmegal6hva atmegal6hva2 atmegal6hvb atmegal6hvbrevb atmega32hvb atmega32hvbrevb atmega64hve at90can32 at90can64 at90pwml61 Chapter 9 Machine Dependent Features 109 at90pwm216 at90pwm316 atmega32cl atmega64cl atmegal6ml at mega32ml atmega64ml atmegal6u4 atmega32u4 atmega32u6 at90usb646 at90usb647 at94k at90scr100 Instruction set avr51 is for the enhanced AVR core with exactly 128k program memory space MCU types atmegal28 atmegal280 atmegal28l atmegal284p atmegal28rfal atmegal28rfr2 atmegal284rfr2 at90can128 at90usb1286 at90usb1287 m3000 Instruction set avr6 is for the enhanced AVR core with a 3 byte PC MCU types atmega2560 atmega2561 atmega256rfr2 atmega2564rfr2 Instruction set avrxmega2 is for the XMEGA AVR core with 8K to 64K pro gram memory space and less than 64K data space MCU types atxmegal6a4 atxmegal6d4 atxmegal6xl atxmega32a4 atxmega32d4 atxmega32x1 Instruction set avrxmega3 is for the XMEGA AVR core with 8K to 64K program memory space and greater than 64K data space MCU types none Instruction set avrxmega4 is for the XMEGA AVR core with up to 64K pro gram memory space and less than 64K data space MCU types atxmega64a3 atxmega64d3 Instruction set avrxmegad is for the XMEGA AVR core
226. aults to being the same as the value specified for listing lhs width If neither switch is used the default is to one listing rhs width number Sets the maximum width in characters of the source line that is displayed alongside the hex dump The default value for this parameter is 100 The source line is displayed on the right hand side of the listing output listing cont lines number Sets the maximum number of continuation lines of hex dump that will be dis played for a given single line of source input The default value is 4 2 9 Assemble in MRI Compatibility Mode A The M or mri option selects MRI compatibility mode This changes the syntax and pseudo op handling of as to make it compatible with the ASM68K or the ASM960 depending upon the configured target assembler from Microtec Research The exact nature of the MRI syntax will not be documented here see the MRI manuals for more information Note in particular that the handling of macros and macro arguments is somewhat different The purpose of this option is to permit assembling existing MRI assembler code using as The MRI compatibility is not complete Certain operations of the MRI assembler de pend upon its object file format and can not be supported using other object file formats Supporting these would require enhancing each object file format individually These are e global symbols in common section The m68k MRI assembler supports
227. ay 32769 5 The implementation of these symbolic offsets depends on several factors such as whether the assembler is generating SVR4 style PIC selected by KPIC see Section 9 27 1 Assembler options page 192 the size of symbols see Section 9 27 3 Direc tives to override the size of symbols page 198 and the small data limit see Section 9 27 4 Controlling the use of small data accesses page 199 Sometimes it is undesirable to have one assembly instruction expand to several machine instructions The directive set nomacro tells the assembler to warn when this happens set macro restores the default behavior Some macro instructions need a temporary register to store intermediate results This register is usually 1 also known as at but it can be changed to any core register reg using set at reg Note that at always refers to 1 regardless of which register is being used as the temporary register Implicit uses of the temporary register in macros could interfere with explicit uses in the assembly code The assembler therefore warns whenever it sees an explicit use of the temporary register The directive set noat silences this warning while set at restores the default behavior It is safe to use set noat while set nomacro is in effect since single instruction macros never need a temporary register Note that while the GNU assembler provides these macros for compatibility it does not make any attempt to optimize th
228. bility Symbols can t be defined twice not even to the same value Instruction mnemonics are recognized case insensitive though the IS and GREG pseudo operations must be specified in upper case characters There s no unicode support The following is a list of programs in mmix tar gz available at http www cs faculty stanford edu last checked with the version dated 2001 08 25 md5sum c393470cfc86fac040487d22d2bf0172 that assemble with mmixal but do not assemble with as silly mms LOC to a previous address sim mms Redefines symbol Done test mms Uses the serial operator amp Chapter 9 Machine Dependent Features 211 9 29 MSP 430 Dependent Features 9 29 1 Options mmcu selects the mpu arch If the architecture is 430Xv2 then this also enables NOP generation unless the mN is also specified mcpu selects the cpu architecture If the architecture is 430Xv2 then this also enables NOP generation unless the mN is also specified mP enables polymorph instructions handler mQ enables relaxation at assembly time DANGEROUS ml indicates that the input uses the large code model mN disables the generation of a NOP instruction following any instruction that might change the interrupts enabled disabled state For the 430Xv2 architec ture the instructions EINT DINT BIC 8 SR BIS 8 SR and MOV W lt gt SR must be followed by a NOP instruction in order to ensure the c
229. bler directive 3byte RX 229 assembler directive arch CRIS 124 assembler directive dword CRIS 123 assembler directive far M68HC11 187 assembler directive fetchalign RX 229 assembler directive interrupt M68HC11 188 assembler directive mode M68HC11 187 assembler directive relax M68HC11 187 assembler directive syntax CRIS 123 assembler directive xrefb M68HC11 188 assembler directive BSPEC MMIX 209 assembler directive BYTE MMIX 208 assembler directive ESPEC MMIX 209 assembler directive GREG MMIX 207 assembler directive IS MMIX 207 assembler directive LOC MMIX 207 assembler directive LOCAL MMIX 207 assembler directive OCTA MMIX 208 assembler directive PREFIX MMIX 209 assembler directive TETRA MMIX 208 assembler directive WYDE MMIX 208 assembler directives CRIS sussereseueua 123 assembler directives M68HC11 187 assembler directives M68HC12 187 336 assembler directives MMIX 207 assembler directives BLO 227 assembler directives RX 229 assembler directives XGATE 304 assembler internal logic error 35 assembler version 25 assembler and linker 200 0000 33 assembly listing
230. bler to use either the short or long form of the instruction you can append either s short or 1 long to it For example if you are writing an assembly program and you want to do a branch to a symbol that is defined later in your program you can write bra s foo Objdump and GDB will always append s or 1 to instructions which have both short and long forms 9 9 2 2 Sub Instructions The D10V assembler takes as input a series of instructions either one per line or in the special two per line format described in the next section Some of these instructions will be short form or sub instructions These sub instructions can be packed into a single in struction The assembler will do this automatically It will also detect when it should not pack instructions For example when a label is defined the next instruction will never be packaged with the previous one Whenever a branch and link instruction is called it will not be packaged with the next instruction so the return address will be valid Nops are automatically inserted when necessary 126 Using as If you do not want the assembler automatically making these decisions you can control the packaging and execution type parallel or sequential with the special execution symbols described in the next section 9 9 2 3 Special Characters 6 3 A semicolon can be used anywhere on a line to start a comment that extends to the end of the line I
231. branches when the branch offset is out of range By default as transforms the relative branch bsr bgt bge beq bne ble blt phi bcc bls bcs bmi bvs bvs bra into an absolute branch when the offset is out of the 128 127 range In that case the bsr instruction is translated into a jsr the bra instruction is translated into a jmp and the conditional branches instructions are inverted and followed by a jmp This option disables these translations and as will generate an error if a relative branch is out of range This option does not affect the optimization associated to the jbra jbsr and jbXX pseudo opcodes force long branches The force long branches option forces the translation of relative branches into absolute branches This option does not affect the optimization associated to the jbra jbsr and jbXX pseudo opcodes print insn syntax You can use the print insn syntax option to obtain the syntax description of the instruction when an error is detected print opcodes The print opcodes option prints the list of all the instructions with their syntax The first item of each line represents the instruction name and the rest of the line indicates the possible operands for that instruction The list is printed in alphabetical order Once the list is pr
232. by the M32Rx processor and the m32rx command line flag has not been specified to allow assembly of such instructions unknown instruction This message is produced when the assembler encounters an instruction which it does not recognize only the NOP instruction can be issued in parallel on the m32r This message is produced when the assembler encounters a parallel instruction which does not involve a NOP instruction and the m32rx command line flag has not been specified Only the M32Rx processor is able to execute two instructions in parallel instruction cannot be executed in parallel This message is produced when the assembler encounters a parallel instruction which is made up of one or two instructions which cannot be executed in parallel Instructions share the same execution pipeline This message is produced when the assembler encounters a parallel instruction whoes components both use the same execution pipeline Instructions write to the same destination register This message is produced when the assembler encounters a parallel instruction where both components attempt to modify the same register For example these code fragments will produce this message mv r1 r2 neg r1 r3 jl r0 mv r14 ri st r2 r1 mv ri r3 mv r1 r2 ld rO Gri cmp ri r2 addx r3 r4 Both write to the condition bit 176 Using as 9 23 M680x0 Dependent Features 9 23 1 M680x0
233. ce It is ignored A statement begins with zero or more labels optionally followed by a key symbol which determines what kind of statement it is The key symbol determines the syntax of the rest of the statement If the symbol begins with a dot then the statement is an assembler directive typically valid for any computer If the symbol begins with a letter the statement Chapter 3 Syntax 29 is an assembly language instruction it assembles into a machine language instruction Different versions of as for different computers recognize different instructions In fact the same symbol may represent a different instruction in a different computer s assembly language A label is a symbol immediately followed by a colon Whitespace before a label or after a colon is permitted but you may not have whitespace between a label s symbol and its colon See Section 5 1 Labels page 39 For HPPA targets labels need not be immediately followed by a colon but the definition of a label must begin in column zero This also implies that only one label may be defined on each line label directive followed by something another label This is an empty statement instruction operand 1 operand 2 3 6 Constants A constant is a number written so that its value is known by inspection without knowing any context Like this byte 74 0112 092 Ox4A OX4a J J All the same value ascii Ring the bell 7 A string const
234. cept MIPS 3D instructions no mips3d turns off this option mdmx no mdmx Generate code for the MDMX Application Specific Extension This tells the assembler to accept MDMX instructions no mdmx turns off this option mdsp mno dsp Generate code for the DSP Release 1 Application Specific Extension This tells the assembler to accept DSP Release 1 instructions mno dsp turns off this option mdspr2 mno dspr2 Generate code for the DSP Release 2 Application Specific Extension This option implies mdsp This tells the assembler to accept DSP Release 2 in structions mno dspr2 turns off this option 14 Using as mmt mno mt Generate code for the MT Application Specific Extension This tells the as sembler to accept MT instructions mno mt turns off this option mmcu mno mcu Generate code for the MCU Application Specific Extension This tells the assembler to accept MCU instructions mno mcu turns off this option minsn32 mno insn32 Only use 32 bit instruction encodings when generating code for the microMIPS processor This option inhibits the use of any 16 bit instructions This is equiv alent to putting set insn32 at the start of the assembly file mno insn32 turns off this option This is equivalent to putting set noinsn32 at the start of the assembly file By default mno insn32 is selected allowing all instructions to be used construct floats no construc
235. cessing page 27 If the divide command line option has not been specified then the character appearing anywhere on a line also introduces a line comment The character can be used to separate statements on the same line 9 15 4 Instruction Naming Instruction mnemonics are suffixed with one character modifiers which specify the size of operands The letters b w I and q specify byte word long and quadruple word operands If no suffix is specified by an instruction then as tries to fill in the missing suffix based on the destination register operand the last one by convention Thus mov hax bx is equivalent to movw Zax Abx also mov 1 bx is equivalent to movw 1 bx Note that this is incompatible with the AT amp T Unix assembler which assumes that a missing mnemonic suffix implies long operand size This incompatibility does not affect compiler output since compilers always explicitly specify the mnemonic suffix Almost all instructions have the same names in AT amp T and Intel format There are a few exceptions The sign extend and zero extend instructions need two sizes to specify them They need a size to sign zero extend from and a size to zero extend to This is accomplished by using two instruction mnemonic suffixes in AT amp T syntax Base names for sign extend and zero extend are movs and movz in AT amp T syntax movsx and movzx
236. cilities for anybody to edit those works A public wiki that anybody can edit is an example of such a server A Massive Multiauthor Collaboration or MMC contained in the site means any set of copyrightable works thus published on the MMC site CC BY SA means the Creative Commons Attribution Share Alike 3 0 license pub lished by Creative Commons Corporation a not for profit corporation with a principal place of business in San Francisco California as well as future copyleft versions of that license published by that same organization Incorporate means to publish or republish a Document in whole or in part as part of another Document An MMC is eligible for relicensing if it is licensed under this License and if all works that were first published under this License somewhere other than this MMC and subsequently incorporated in whole or in part into the MMC 1 had no cover texts or invariant sections and 2 were thus incorporated prior to November 1 2008 The operator of an MMC Site may republish an MMC contained in the site under CC BY SA on the same site at any time before August 1 2009 provided the MMC is eligible for relicensing 328 Using as ADDENDUM How to use this License for your documents To use this License in a document you have written include a copy of the License in the document and put the following copyright and license notices just after the title page Copyright C year your name
237. ck only this identifier for being the subject to parameter substitution So for example this macro definition macro label 1 M endm might not work as expected Invoking label foo might not create a label called foo but instead just insert the text l into the assembler source probably generating an error about an unrecognised identifier 64 endm exitm LOCAL name Using as Similarly problems might occur with the period character which is often allowed inside opcode names and hence identifier names So for example constructing a macro to build an opcode from a base name and a length specifier like this macro opcode base length base length endm and invoking it as opcode store 1 will not create a store 1 instruction but instead generate some kind of error as the assembler tries to interpret the text base length There are several possible ways around this problem Insert white space If it is possible to use white space characters then this is the simplest solution eg macro label 1 Xl 23 endm Use NO The string N can be used to separate the end of a macro argu ment from the following text eg macro opcode base length base length endm Use the alternate macro syntax mode In the alternative macro syntax mode the ampersand character amp can be used as a separator eg altmacro macro label 1 l amp endm No
238. code to run in real mode or in 16 bit protected mode code segments To do this put a code16 or code16gcc directive before the assembly language instructions to be run in 16 bit mode You can switch as to writing 32 bit code with the code32 directive or 64 bit code with the code64 directive codei6gcc provides experimental support for generating 16 bit code from gcc and differs from code16 in that call ret enter leave push pop pusha popa pushf and popf instructions default to 32 bit size This is so that the stack pointer is manipulated in the same way over function calls allowing access to function parameters at the same stack offsets as in 32 bit mode code16gcc also automatically adds address size prefixes where necessary to use the 32 bit addressing modes that gcc generates The code which as generates in 16 bit mode will not necessarily run on a 16 bit pre 80386 processor To write code that runs on such a processor you must refrain from using any 32 bit constructs which require as to output address or operand size prefixes Note that writing 16 bit code instructions by explicitly specifying a prefix or an instruc tion mnemonic suffix within a 32 bit code section generates different machine instructions than those generated for a 16 bit code segment In a 32 bit code section the following code generates the machine opcode bytes 66 6a
239. comment character Sparc 256 line comment character TIC54X 273 line comment character TIC6X 274 line comment character V850 297 line comment character VAX 295 line comment character XGATE 303 line comment character XStormy16 305 line comment character 280 286 line comment character Z8000 289 line comment characters CRIS 122 line comment characters MMIX 205 line directive llli ee rr ye mre 60 line directive MSP 430 sus 213 line numbers in input Des 18 line numbers in warnings errors 18 line separator character 28 line separator character Nios II 215 line separator A Archp 82 line separator Alpha 85 line separator ARC 91 line separator ARM 98 line separator AND 109 line separator CHRI8 119 line separator Epiphany 133 line separator HS 200 0s eee eee ee 134 342 line separator i386 2 cece eee eee ee 148 line separator i860 2 srani suis 158 line separator 1900 cese nte teh 162 line separator LA O4 164 line separator IP2K uuueeesss 166 line separator LAM 169 line separator M 171 line separator Most 183 line separator M68HC11 ossssseeerunnnn 185 line separator Meta 2 cece eee eee 190 line separator Micr
240. common sections which are merged by the linker Other object file formats do not support this as handles common sections by treating them as a single common symbol It permits local symbols to be defined within a common section but it can not support global symbols since it has no way to describe them e complex relocations The MRI assemblers support relocations against a negated section address and reloca tions which combine the start addresses of two or more sections These are not support by other object file formats e END pseudo op specifying start address The MRI END pseudo op permits the specification of a start address This is not supported by other object file formats The start address may instead be specified using the e option to the linker or in a linker script e IDNT ident and NAME pseudo ops The MRI IDNT ident and NAME pseudo ops assign a module name to the output file This is not supported by other object file formats 24 Using as ORG pseudo op The m68k MRI ORG pseudo op begins an absolute section at a given address This differs from the usual as org pseudo op which changes the location within the current section Absolute sections are not supported by other object file formats The address of a section may be assigned within a linker script There are some other features of the MRI assembler which are not supported by as typically either because they are difficult or because they seem of little c
241. compiler s preprocessor You can do include file processing with the include directive see Section 7 64 include page 58 You can use the GNU C compiler driver to get other CPP style preprocessing by giving the input file a S suffix See Section Options Controlling the Kind of Output in Using GNU CC Excess whitespace comments and character constants cannot be used in the portions of the input text that are not preprocessed If the first line of an input file is NO_APP or if you use the f option whitespace and comments are not removed from the input file Within an input file you can ask for whitespace and comment removal in specific portions of the by putting a line that says APP before the text that may contain whitespace or comments and putting a line that says NO_APP after this text This feature is mainly intend to support asm statements in compilers whose output is otherwise free of comments and whitespace 3 2 Whitespace Whitespace is one or more blanks or tabs in any order Whitespace is used to separate symbols and to make programs neater for people to read Unless within character constants see Section 3 6 1 Character Constants page 29 any whitespace means the same as exactly one space 3 3 Comments There are two ways of rendering comments to as In both cases the comment is equivalent to one space Anything from through the next is a comment This means you may not
242. ct bits 9 0 of their operand V9 code model relocations can be requested as follows R_SPARC_HH22 is requested using Zhh It can also be generated using huhi R_SPARC_HM10 is requested using 4hm It can also be generated using hulo R_SPARC_LM22 is requested using 1m R_SPARC_H44 is requested using 4h44 260 Using as e R_SPARC_M44 is requested using m44 e R_SPARC_L44 is requested using 144 or 4134 e R_SPARC_H34 is requested using 4h34 The 4134 generates a RLSPARC_L44 relocation because it calculates the necessary value and therefore no explicit RB SPARC L34 relocation needed to be created for this purpose The 4h34 and 4134 relocations are used for the abs34 code model Here is an example abs34 address generation sequence sethi Ah34 symbol Agi sllx jet 2 Zei or Agi 4Al34 symbol Agi The PC relative relocation RLSPARC_PC22 can be obtained by enclosing an operand inside of pc22 Likewise the RLSPARC_PC10 relocation can be obtained using pci10 These are mostly used when assembling PIC code For example the standard PIC sequence on Sparc to get the base of the global offset table PC relative into a register can be performed as sethi pc22 _GLOBAL_OFFSET_TABLE_ 4 17 add 17 pciO GLOBAL OFFSET TABLE 44 417 Several relocations exist to allow the link editor to potentially optimize GOT data refer ences The RB SPARC GOTDATA OP HIX22 reloca
243. ction ordering D30V 130 sub instructions D10V 2 2000s 125 sub instructions D30V 0 e eee 129 SubexpressiOns l2esd4l eR eerca tr Erenet 43 subsection directive eee ee eee 74 subsym builtins TIC54X usuuuuus 212 subtitles for listings ecri srce itinrrrciiesstp tes 69 subtraction permitted arguments 44 summary of options ENEE e e er heu 1 BUDEOER ed ENT er Seed CR AN EES EN 137 supporting files including 58 suppressing warnings eee eee eee 26 SVG oii aca 9e eee see ari hed oad ERE RET 290 symbol attributes ex EE Rb RE UR 41 symbol attributes a out 42 symbol attributes CO 42 symbol attributes OM 42 symbol descriptor CO 53 symbol modifiers 110 168 170 187 symbol modifiers TILE Gx 278 symbol modifiers TILEPro 283 symbol names eere Rr ree wed devout 39 symbol names in 126 130 190 248 252 symbol names Jocal rrini ri eran skii 39 symbol names Lemporar AO symbol storage class COFF 69 Symbol ty pe ies ve viv d ERR EE wee Mead is 41 symbol type COFFE RER e 76 symbol type ELE ga n Rr eem 76 symbol value v ed mer Rer Y eer aas 41 symbol value setting 0 008 T2 symbol values aeiguing 39 symbol versioning 20s eee eee ee 74 symbol COMMON 45525 veda ss
244. ctional memory floating point unfused multiply add integer multiply add and cache sparing store in structions as well as the instructions enabled by Av8plusd and Av9d Asparc specifies a v9 environment It is equivalent to Av9 if the word size is 64 bit and Av8plus otherwise Asparcvis specifies a v9a environment It is equivalent to Av9a if the word size is 64 bit and Av8plusa otherwise Chapter 9 Machine Dependent Features 255 Asparcvis2 specifies a v9b environment It is equivalent to Av9b if the word size is 64 bit and Av8plusb otherwise Asparcfmaf specifies a v9b environment with the floating point fused multiply add instructions enabled Asparcima specifies a v9b environment with the integer multiply add instruc tions enabled Asparcvis3 specifies a v9b environment with the VIS 3 0 HPC and floating point fused multiply add instructions enabled Asparcvis3r specifies a v9b environment with the VIS 3 0 HPC transac tional memory random and floating point unfused multiply add instructions enabled xarch v8plus xarch v8plusa xarch v8plusb xarch v8plusc xarch v8plusd xarch v8plusv xarch v9 xarch v9a xarch v9b xarch v9c xarch v9d xarch v9v xarch sparc xarch sparcvis xarch sparcvis2 xarch sparcfmaf xarch sparcima xarch sparcvis3 xarch sparcvis3r For compatibility with the
245. ctions when necessary This directive is only meaningful when in MIPS 16 mode Traditional MIPS assemblers do not support this directive 9 27 8 Directive to mark data as an instruction The insn directive tells as that the following data is actually instructions This makes a difference in MIPS 16 and microMIPS modes when loading the address of a label which precedes instructions as automatically adds 1 to the value so that jumping to the loaded address will do the right thing The global and globl directives supported by as will by default mark the symbol as pointing to a region of data not code This means that for example any instructions following such a symbol will not be disassembled by objdump as it will regard them as data To change this behaviour an optional section name can be placed after the symbol name in the global directive If this section exists and is known to be a code section then the symbol will be marked as poiting at code not data Ie the syntax for the directive is global symbol section symbol section Here is a short example Chapter 9 Machine Dependent Features 201 global foo text bar baz data foo nop bar word 0x0 baz word Oxi 9 27 9 Directives to record which NaN encoding is being used The IEEE 754 floating point standard defines two types of not a number NaN data sig nalling NaNs and quiet NaNs The original version of the standard did not specify
246. ctive DDARC 263 yn PETERET 286 ZB Oi Ls ses epus to m PIN MEER RENE 287 Z80 Heating poil EE 287 Z80 line comment character 286 Z80 line separator ccc csc EEN dace EIERE 286 AS Index Z80 OPT NS scs cte ese E RIS Ure EE ER 286 ASO TEGISKETS uen AE t ARTE 287 280 SUPPO Ae det SE ge ee bu REEL EDEN 286 280 Syntax nern no a oE eter esse alee be es 286 ZU EE 286 Z80 case sensitivity cles 287 Z80 only directives 20 2 eee 287 Z800 addressing modes sussuerrrrecees 289 Z8000 directives eee cee ee eee 290 351 Z8000 line comment character 289 28000 line separator scsessrreresesrseu 289 48000 opcode summary 005 291 Z000 Options 424 ects sted cies te ce aaa ee 289 Z8000 Tegisters s e re ren OE nee EE ea oes 289 Z8000 Support ze rere REEL 289 zdaoff pseudo op ND 301 zero register VSbU ee eee ee eee 297 zero terminated sting 48
247. ctive MAX 292 float directive 90 04 152 float directive SOGOATE enne 304 floating point number 31 floating point numbers double 53 floating point numbers single 56 72 floating point AArch64 IEEE 83 floating point Alpha rr 87 floating point ARC Drrr 91 floating point ARM IEEE 99 floating point DIOV dees RR 128 floating point DIOV 0 eee eee 132 floating point ESA 390 IEEE 143 floating point H8 300 IEEE 135 floating point HPPA IEEE 137 floating point i886 0 0 eee eee ee eee 152 floating point i960 DEER 160 floating point Motet 181 floating point M68HC11 188 floating point MSP 430 IEEE 213 floating point RX vsics secc ss AER Rer 230 floating point s 200 0 cece eee ee eee 245 floating point SH rer 249 floating point SPARC IEEE 262 floating point V850 rr 299 floating point VAN 292 floating point 90 04 152 floating point SCGATb 304 floating point 280 287 HOMUMS s eiroet rinan ieee Ed 31 format of error mespages 18 format of warning Messages s srrrru 18 formfeed NE ais Nee 29 339 func diecllVe cessere Aere pre RUPEE 56 functions in expressions eeeeses esee 43 G gbr960 1960 postprocessor sess 159 gfloat directive VAX
248. ctive is only available for COFF based x86 targets 9 15 3 1386 Syntactical Considerations 9 15 3 1 AT amp T Syntax versus Intel Syntax as now supports assembly using Intel assembler syntax intel syntax selects Intel mode and att syntax switches back to the usual AT amp T mode for compatibility with the output of gcc Either of these directives may have an optional argument prefix or noprefix specifying whether registers require a A prefix AT amp T System V 386 assembler syntax is quite different from Intel syntax We mention these differences because almost all 80386 documents use Intel syntax Notable differences between the two syntaxes are e AT amp T immediate operands are preceded by Intel immediate operands are undelim ited Intel push 4 is AT amp T pushl 4 AT amp T register operands are preceded by 4 Intel register operands are undelimited AT amp T absolute as opposed to PC relative jump call operands are prefixed by they are undelimited in Intel syntax e AT amp T and Intel syntax use the opposite order for source and destination operands Intel add eax 4 is addl 4 eax The source dest convention is maintained for compatibility with previous Unix assemblers Note that bound invlpga and instructions with 2 immediate operands such as the enter instruction do not have reversed order Section 9 15 16 i386 Bugs page 154 e In AT amp T syntax the size of
249. ctive produces d format numbers 9 48 3 Vax Machine Directives The Vax version of the assembler supports four directives for generating Vax floating point constants They are described in the table below dfloat This expects zero or more flonums separated by commas and assembles Vax d format 64 bit floating point constants ffloat This expects zero or more flonums separated by commas and assembles Vax f format 32 bit floating point constants gfloat This expects zero or more flonums separated by commas and assembles Vax g g format 64 bit floating point constants Chapter 9 Machine Dependent Features 293 hfloat This expects zero or more flonums separated by commas and assembles Vax h format 128 bit floating point constants 9 48 4 VAX Opcodes All DEC mnemonics are supported Beware that case instructions have exactly 3 operands The dispatch table that follows the case instruction should be made with word statements This is compatible with all unix assemblers we know of 9 48 5 VAX Branch Improvement Certain pseudo opcodes are permitted They are for branch instructions They expand to the shortest branch instruction that reaches the target Generally these mnemonics are made by substituting j for b at the start of a DEC mnemonic This feature is included both for compatibility and to help compilers If you do not need this feature avoid these opcodes Here are the mnemonics and the code they can
250. d performance although the linker can usually eliminate the unnecessary overhead If a program is too large and some of the calls are out of range function call relaxation can be enabled using the longcalls command line option or the longcalls directive see Section 9 52 5 2 longcalls page 312 9 52 4 3 Other Immediate Field Relaxation The assembler normally performs the following other relaxations They can be disabled by using underscore prefixes see Section 9 52 2 1 Opcode Names page 307 the no transform command line option see Section 9 52 1 Command Line Options page 306 or the no transform directive see Section 9 52 5 3 transform page 312 The MOVI machine instruction can only materialize values in the range from 2048 to 2047 Values outside this range are best materialized with L32R instructions Thus movi a0 100000 is assembled into the following machine code literal L1 100000 132r a0 L1 The L8UI machine instruction can only be used with immediate offsets in the range from 0 to 255 The L16SI and L16UI machine instructions can only be used with offsets from 0 to 510 The L321 machine instruction can only be used with offsets from 0 to 1020 A load offset outside these ranges can be materialized with an L32R instruction if the destination register of the load is different than the source address register For example 132i ai a0 2040 is translated to Chapter 9 Machine Dependent Features 3
251. d the endp directive will be added to the exception table entry Must be preceded by a CFI block containing a cfi lsda directive nocmp Disallow use of C64x compact instructions in the current text section personalityindex index Sets the personality routine for the current function to the ABI specified com pact routine number index personality name Sets the personality routine for the current function to name 276 Using as Scomm symbol size align Like comm creating a common symbol symbol with size size and alignment align but unlike when using comm this symbol will be placed into the small BSS section by the linker Chapter 9 Machine Dependent Features 277 9 44 TILE Gx Dependent Features 9 44 1 Options The following table lists all available TILE Gx specific options m32 m64 Select the word size either 32 bits or 64 bits EB EL Select the endianness either big endian EB or little endian EL 9 44 2 Syntax Block comments are delimited by and End of line comments may be introduced by 4 Instructions consist of a leading opcode or macro name followed by whitespace and an optional comma separated list of operands opcode operand Instructions must be separated by a newline or semicolon There are two ways to write code either write naked instructions which the assembler is free to combine into VLIW bundles or specify the VLIW bundles explicitly Bundles are specified
252. dddirrr fmulsu 1001001ddddd0000 sts 1001000ddddd0000 lds 1000000dddddbooo ldd 100 000dddddee 1d 10o00ooirrrrrbooo std 100 001rrrrree st 1001010100011001 eicall 1001010000011001 eijmp m O CH HH HD MMA Dad HHH HHH HH HH PPDP D HHH H RPP H H Oo oO on P np D d 114 Using as 9 6 Blackfin Dependent Features 9 6 1 Options mcpu processor sirevision mfdpic mno fdpic mnopic This option specifies the target processor The optional sirevision is not used in assembler It s here such that GCC can easily pass down its mcpu option The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor The following processor names are recognized bf504 bf506 bf512 bf514 bf516 bf518 bf522 bf 523 bf524 bf525 bf 526 bf527 bf531 bf532 bf 533 bf 534 bf535 not implemented yet bf536 bf537 bf538 bf539 bf542 bf5b42m bf544 bf544m b 547 bf547m bf548 bf548m bf549 bf549m bf561 and bf592 Assemble for the FDPIC ABI Disable mfdpic 9 6 2 Syntax Special Characters Assembler input is free format and may appear anywhere on the line One instruction may extend across multiple lines or more than one instruction may appear on the same line White space space tab comments or newline may appear anywhere between tokens A token must not have embedded spaces Tokens include numbers register names keywords user identifi
253. defining debugging information for a symbol name the definition extends until the endef directive is encountered 7 35 desc symbol abs expression This directive sets the descriptor of the symbol see Section 5 5 Symbol Attributes page 41 to the low 16 bits of an absolute expression The desc directive is not available when as is configured for COFF output it is only for a out or b out object format For the sake of compatibility as accepts it but produces no output when configured for COFF 7 36 dim This directive is generated by compilers to include auxiliary debugging information in the symbol table It is only permitted inside def endef pairs 7 37 double flonums double expects zero or more flonums separated by commas It assembles floating point numbers The exact kind of floating point numbers emitted depends on how as is configured See Chapter 9 Machine Dependencies page 81 7 38 eject Force a page break at this point when generating assembly listings 7 39 else else is part of the as support for conditional assembly see Section 7 62 if page 57 It marks the beginning of a section of code to be assembled if the condition for the preceding if was false 7 40 elseif elseif is part of the as support for conditional assembly see Section 7 62 if page 57 It is shorthand for beginning a new if block that would otherwise fill the entire else section 7 41 end end marks th
254. digits Absolute symbol or digits The M68HC12 has other more complex addressing modes All of them are supported and they are represented below Constant Offset Indexed Addressing Mode number reg The number may be omitted in which case 0 is assumed The register can be either X Y SP or PC The assembler will use the smaller post byte definition according to the constant value 5 bit constant offset 9 bit constant offset or 16 bit constant offset If the constant is not known by the assembler it will use the 16 bit constant offset post byte and the value will be resolved at link time Offset Indexed Indirect number reg The register can be either X Y SP or PC Auto Pre Increment Pre Decrement Post Increment Post Decrement number reg number reg number reg number reg The number must be in the range 8 8 and must not be 0 The register can be either X Y SP or PC Accumulator Offset acc reg The accumulator register can be either A B or D The register can be either X P SP or PC Accumulator D offset indexed indirect D reg The register can be either X Y SP or PC For example ldab 1024 sp ldd 10 x orab 3 x stab 2 y ldx a pc sty d sp Chapter 9 Machine Dependent Features 187 9 24 3 Symbolic Ope
255. dir ctive 8 use ere te edes 66 p2alignw rette au EE eet ea 66 padding the location counter AT padding the location counter given a power of two n M 66 padding the location counter given number of BYOB wate ck Dale EN ine ated EP 48 page 1n listings ooien e SP eneit ay 53 paper size for listings 0000 67 paths for vinclude SEENEN naii dE 22 patterns writing in MeEMOTYy s s ssssuruo 55 PDP11 conmments 52 d A e Er ENEE dex 221 PDP 11 floating point register syntax 221 PDP 11 general purpose register syntax 221 PDP 11 instruction naming 221 PDP 11 line separator ssslslsess 221 PDP311 Supporti tac Breet dree a a peee 219 EUR syntax eesse n RR qure 221 PIC code generation for ARM 9i PIC code generation for M32R 172 PIC selection MIPS eroe KE EE E 192 PJ endianuess 2 A ra a DO b RISE S ber 10 PJ line comment character 223 PJ line separator 0 cece e eee eee eee 223 PJ ODUODS2 en nee UD REPRE Reb ee 223 PJ SUDDOEU usen sue ROS ase M REPRE ES 223 plus permitted argumente lesse 44 popsection directe 66 Position independent code CRIS 120 Position independent code symbols in CRIS 122 PowerPC architectures 0 0 20 eee 224 PowerP directives see metre tri 226 PowerPC line comment character 226 PowerPC lin
256. directive ARM 103 thumb directive ARM 103 thumb func directive ARM 103 thumb set directive ARM 103 tlsdescseq directive ARM 103 unreq directive A Arche 83 unreq directive ARM 103 unwind raw directive ARM 103 v850 directive VS 299 v850e directive V850 ee eee eee 299 v850e1 directive V850 00 eee eee ee 299 v850e2 directive VNRa0 0 eee eee 299 v850e2v3 directive VD 299 v850e2v4 directive VD 300 v850e3v5 directive Van 300 vsave directive ARM 103 z0O00T lg erred iuasekYoeeezd de 290 z8002 4906 PNE RII e dae niin weeded ae 290 label o bi epe EE E ere b e bai aes 29 hi pseudo op Atom 305 Glo pseudo op XStormyl16 sssss 305 word modifier D10V sosse ccsicosernsicssses 128 OPGOdE prefix side Sede user PIRE PRG REPE 307 Using as Vi doublequote character 30 NN CN character elec ber RR dade ier A 30 b backspace character ursrrrrrrrsss 29 ddd octal character code 29 f formfeed character 29 n newline character 29 r carriage return character 29 Wb Gab eiioRbenrse cepe epe RIED EEN 29 xd hex character code uueuuuu 29 1 16 bit code 1988 ENEE NNN tet 153 16bit pointers directive XStormy16 305 16byte directive Nios H 216 2 2byte directive AR 91 2byte directive Nios H 216 3 32bit_pointers directive XSto
257. do op This is the default m64bit doubles This option controls the ABI and indicates to use a 64 bit float ABI It has no effect on the assembled instructions but it does influence the behaviour of the double pseudo op mbig endian This option controls the ABI and indicates to use a big endian data ABI It has no effect on the assembled instructions but it does influence the behaviour of the short hword int word long quad and octa pseudo ops mlittle endian This option controls the ABI and indicates to use a little endian data ABI It has no effect on the assembled instructions but it does influence the behaviour of the short hword int word Long quad and octa pseudo ops This is the default muse conventional section names This option controls the default names given to the code text initialised data data and uninitialised data sections bss muse renesas section names This option controls the default names given to the code P initialised data D_1 and uninitialised data sections B_1 This is the default msmall data limit This option tells the assembler that the small data limit feature of the RX port of GCC is being used This results in the assembler generating an undefined reference to a symbol called __gp for use by the relocations that are needed to support the small data limit feature This option is not
258. ds 127 registers D30V s 2i se e ead eee ares 131 registers 1380 i el elsi asado dude D xa d Rire 149 registers Meta e v dE EPI RES ERE 190 fegisters SH ooeceieopre esti reve er rere dra 249 registers GHGS sucesos rr eR gene mec se ae 252 registers TIC54X memory mapped 273 registers X86 64 cose ce sur twee p Oe rn 149 registers Z8000 esee 289 relax all command line option Nios II 215 relax section command line option Nios II 215 E LEE 309 relaxation of ADDI instructions 311 relaxation of branch instructions 309 relaxation of call instructions 310 relaxation of immediate fields 310 relaxation of L16SI instructions 310 relaxation of L16UI instructions 310 relaxation of L32I instructions 310 relaxation of L8UI instructions 310 relaxation of MOVI instructions 310 e EE 68 relocation clades CESS ha eat tated E 33 relocation evample eee eee eee eee 35 relocations AArch64 0 eee eee eee 82 relocations Alpha 85 relocations Spate le ape Ree eR LEV 259 repeat prefixes i386 00 e eee eee 150 reporting bugs in assembler 315 r pt directive iss eee ie ERE A px 68 reserve directive SPARC 263 return instructions 1290 147 return instructions x86 64 147 REX prefixes 1386 2 22 00
259. e call far and jump far in Intel convention 9 15 5 AT amp T Mnemonic versus Intel Mnemonic as supports assembly using Intel mnemonic intel_mnemonic selects Intel mnemonic with Intel syntax and att_mnemonic switches back to the usual AT amp T mnemonic with AT amp T syntax for compatibility with the output of gcc Several x87 instructions fadd fdiv fdivp fdivr fdivrp fmul fsub fsubp fsubr and fsubrp are implemented in AT amp T System V 386 assembler with different mnemonics from those in Intel IA32 spec ification gcc generates those instructions with AT amp T mnemonic 9 15 6 Register Naming Register operands are always prefixed with 7 The 80386 registers consist of e the 8 32 bit registers eax the accumulator Zebx 4ecx hedx hedi hesi hebp the frame pointer and esp the stack pointer e the 8 16 bit low ends of these fax Abx Acx dx Adi Asi Abp and Asp e the 8 8 bit registers Aah Zei Abh RI Ach cl Adh and 4d1 These are the high bytes and low bytes of las bx ies and dx e the 6 section registers les code section Ads data section 4ss stack section pes hfs and figs e the 3 processor control registers Mer Zcr2 and Acra e the 6 debug registers 4dbO db
260. e params Switch to section secname creating a new section by that name if necessary You may only use params when creating a new section not when switching to an existing one secname may identify a section by number rather than by name If specified the list params declares attributes of the section identified by key words The keywords recognized are spnum exp identify this section by the number exp an absolute expression sort exp order sections according to this sort key when linking exp is an absolute expression unloadable sec tion contains no loadable data notdefined this section defined elsewhere and private data in this section not available to other programs Spnum secnam Allocate four bytes of storage and initialize them with the section number of the section named secnam You can define the section number with the HPPA Space directive String str Copy the characters in the string str to the object file See Section 3 6 1 1 Strings page 29 for information on escape sequences you can use in as strings Warning The HPPA version of string differs from the usual as definition it does not write a zero byte after copying str Stringz str Like string but appends a zero byte after copying str to object file 140 Using as subspa name params nsubspa name params Similar to space but selects a subsection name within the current section You may only sp
261. e You may specify more than one string to copy separated by commas Unless otherwise specified for a particular machine the assembler marks the end of each string with a 0 byte You can use any of the escape sequences described in Section 3 6 1 1 Strings page 29 The variants stringi6 string32 and string64 differ from the string pseudo opcode in that each 8 bit character from str is copied and expanded to 16 32 or 64 bits respectively The expanded characters are stored in target endianness byte order Example String32 BYE expands to String B O O OY O O OE O O 0O On little endian targets String O O OB O O OY O O OE On big endian targets 7 109 struct expression Switch to the absolute section and set the section offset to expression which must be an absolute expression You might use this as follows struct 0 fieldi Struct fieldi 4 field2 Struct field2 4 field3 This would define the symbol field1 to have the value 0 the symbol field2 to have the value 4 and the symbol field3 to have the value 8 Assembly would be left in the absolute section and you would need to use a section directive of some sort to change to some other section before further assembly 7 110 subsection name This is one of the ELF section stack manipulation directives The others are section see Section 7 99 Section page 69 pushsection see Section 7 93 PushSection page 68 popsection see Sec
262. e Title page the name of the publisher of the Modified Version as the publisher Preserve all the copyright notices of the Document Add an appropriate copyright notice for your modifications adjacent to the other copyright notices Include immediately after the copyright notices a license notice giving the public permission to use the Modified Version under the terms of this License in the form shown in the Addendum below Preserve in that license notice the full lists of Invariant Sections and required Cover Texts given in the Document s license notice Include an unaltered copy of this License Preserve the section Entitled History Preserve its Title and add to it an item stating at least the title year new authors and publisher of the Modified Version as given on the Title Page If there is no section Entitled History in the Docu ment create one stating the title year authors and publisher of the Document as given on its Title Page then add an item describing the Modified Version as stated in the previous sentence Preserve the network location if any given in the Document for public access to a Transparent copy of the Document and likewise the network locations given in the Document for previous versions it was based on These may be placed in the History section You may omit a network location for a work that was published at least four years before the Document itself or if the original publish
263. e Unsigned large immediate with logical operations Logical operations or andnot or xor also result in expansions The pseudo instruction or large_imm rx rn results in orh large imm6h rx r31 or large_imm 1 r31 rn Similarly for the others except for and which expands to 158 Using as andnot 1 large_imm h rx r31 andnot 1 large_imm 1 r31 rn 9 16 5 i860 Syntax 9 16 5 1 Special Characters The presence of a appearing anywhere on a line indicates the start of a comment that extends to the end of that line If a appears as the first character of a line then the whole line is treated as a com ment but in this case the line can also be a logical line number directive see Section 3 3 Comments page 27 or a preprocessor control command see Section 3 1 Preprocessing page 27 The character can be used to separate statements on the same line Chapter 9 Machine Dependent Features 159 9 17 Intel 80960 Dependent Features 9 17 1 i960 Command line Options ACA ACA_A ACB ACC AKA AKB AKC AMC Select the 80960 architecture Instructions or features not supported by the selected architecture cause fatal errors ACA is equivalent to ACA_A AKC is equivalent to AMC Synonyms are provided for compatibility with other tools If you do not specify any of these options as generates code for any instruction or feature that is supported by
264. e behavior of secondary def symbols common provides Fortran named common support It is only useful for data subspaces Symbols with the flag is_common retain this flag in shared links Referencing a is common symbol in a shared library from outside the library doesn t work Thus is common symbols must be output whenever they are needed common and dup_comm together provide Cobol common support The sub spaces in this case must all be the same length Otherwise this support is similar to the Fortran common support dup_comm by itself provides a type of one only support for code Only the first dup_comm subspace is selected There is a rather complex algorithm to compare subspaces Code symbols marked with the dup_common flag are hidden This support was intended for C duplicate inlines A simplified technique is used to mark the flags of symbols based on the flags of their subspace A symbol with the scope SS UNIVERSAL and type ST_ENTRY ST_CODE or ST_DATA is marked with the corresponding set tings of comdat common and dup_comm from the subspace respectively This avoids having to introduce additional directives to mark these symbols The HP assembler sets is_common from common However it doesn t set the dup_common from dup_comm It doesn t have comdat support Chapter 9 Machine Dependent Features 141 version str Write str a
265. e end of the assembly file as does not process anything in the file past the end directive 54 Using as 7 42 endef This directive flags the end of a symbol definition begun with def 7 43 endfunc endfunc marks the end of a function specified with func 7 44 endif endif is part of the as support for conditional assembly it marks the end of a block of code that is only assembled conditionally See Section 7 62 if page 57 7 45 equ symbol expression This directive sets the value of symbol to expression It is synonymous with set see Section 7 100 set page 72 The syntax for equ on the HPPA is symbol equ expression The syntax for equ on the Z80 is symbol equ expression On the Z80 it is an eror if symbol is already defined but the symbol is not protected from later redefinition Compare Section 7 46 Equiv page 54 7 46 equiv symbol expression The equiv directive is like equ and set except that the assembler will signal an error if symbol is already defined Note a symbol which has been referenced but not actually defined is considered to be undefined Except for the contents of the error message this is roughly equivalent to ifdef SYM err endif equ SYM VAL plus it protects the symbol from later redefinition 7 47 eqv symbol expression The eo directive is like equiv but no attempt is made to evaluate the expression or any part of it immediately Instead eac
266. e for processors with Hardware Transactional Memory instruc tions mpower4 mpwr4 Generate code for Power4 architecture mpowerb mpwrd mpwr5x Generate code for Powerd architecture mpower6 mpwr6 Generate code for Power6 architecture mpower 7 mpwr7 Generate code for Power7 architecture mpower8 mpwr8 Generate code for Powers architecture mcell mcell Generate code for Cell Broadband Engine architecture mcom Generate code Power PowerPC common instructions many Generate code for any architecture PWR PWRX PPC mregnames Allow symbolic names for registers mno regnames Do not allow symbolic names for registers mrelocatable Support for GCC s mrelocatable option mrelocatable lib Support for GCC s mrelocatable lib option memb Set PPC_EMB bit in ELF flags mlittle mlittle endian le Generate code for a little endian machine 226 Using as mbig mbig endian be Generate code for a big endian machine msolaris Generate code for Solaris mno solaris Do not generate code for Solaris nops count If an alignment directive inserts more than count nops put a branch at the beginning to skip execution of the nops 9 34 2 PowerPC Assembler Directives A number of assembler directives are available for PowerPC The following table is far from complete machine string This directive allows you to change the machine for which code is generated string may be any of
267. e literal pool liti The literal pool entry is created as an 8 bit value An operand modifier must not be used for the original expression lit2 The literal pool entry is created as a 16 bit value The operand modifier got may be used in the original expression The term x got 1it2 will put the got offset for the global symbol x to the literal pool as 16 bit value lit4 The literal pool entry is created as a 32 bit value The operand modifier got and plt may be used in the original expression The term x got 1it4 will put the got offset for the global symbol x to the literal pool as a 32 bit value The term x p1t 1it4 will put the plt offset for the global symbol x to the literal pool as a 32 bit value lit8 The literal pool entry is created as a 64 bit value The operand modifier got and plt may be used in the original expression The term x got 1it8 will put the got offset for the global symbol x to the literal pool as a 64 bit value The term x p1t 1it8 will put the plt offset for the global symbol x to the literal pool as a 64 bit value The assembler directive 1torg is used to emit all literal pool entries to the current position 244 Using as 9 37 4 Assembler Directives as for s390 supports all of the standard ELF assembler directives as outlined in the main part of this document Some directives have been extended and there are some additional directives which are only available for
268. e oe Het ewe Ned I ead 4 90 protected namHeS oe teme pea ep es eee eU d 7 91 psize lines columns sees 1 02 purger name i rece eR eR It Tam rp Eaa 7 93 pushsection name subsection flags Gtypel arguments ll esses 94 quad bignums NENNEN EERSTEN KEEN EN EC 7 95 reloc offset reloc name expression 96 Grept COUNT i248 ess ksek ana ee orte eer er TIT sbttl subheading WESSEN ses ees hy Ier srai LOS Scl CLASS csv RE vd Oe eia I OPER UPON NEC HERES 41 90 gectlon name icewsu yg emp ded dp ER E Rai 7 100 eet symbol expression sese GAOL Short expresSsioHlS xm deny cna cheep ORARE Na E naue 6 102 Single flon msi eStart tee tte ph Oat E 103 EE 104 skip size fill eee boe RR e e EN es 1 105 Slebi128 expressions ean D a ERRARE A aee 1060 space size s Fill iz retesese5e ER ee de GIL St bd stabi Stabs oeeeeseresicia Baier dE E Rr eR 7 108 string str string8 str stringl6 1 109 Str ct expression cseensne bete ER ERR I I tele 110 subsection name sedeo ev ek eee EE Using as GAUL Syve jac eee e dE RR ETUS be Urea d rA pa raa 74 CAI2 stag structname iucscssesine eta e ever E ers ee ad T5 13 E SUDSSCLIOl 2 Tie 0 vea ARN ats RII slaw hae eee S 75 GEI title heading o x Ove RO EE PEG 75 GIE Uypelesceseee eem eee cise Ren nee eae eo 76 T 1116 lebi28 expressions o e Re RE iT
269. e of 0x2000 These masks are primarily intended for use with the ssm sum and rsm rum instructions but they can be used anywhere else where an integer constant is expected 9 18 2 4 Relocations In addition to the standard IA 64 relocations the following relocations are implemented by as Chapter 9 Machine Dependent Features 165 slotcount V Convert the address offset V into a slot count This pseudo function is available only on VMS The expression V must be known at assembly time it can t reference undefined symbols or symbols in different sections 9 18 3 Opcodes For detailed information on the IA 64 machine instruction set see the IA 64 Assembly Language Reference Guide available at http developer intel com design itanium arch spec htm 166 Using as 9 19 IP2K Dependent Features 9 19 1 IP2K Options The Ubicom IP2K version of as has a few machine dependent options mip2022ext as can assemble the extended IP2022 instructions but it will only do so if this is specifically allowed via this command line option mip2022 This option restores the assembler s default behaviour of not permitting the extended IP2022 instructions to be assembled 9 19 2 IP2K Syntax 9 19 2 1 Special Characters The presence of a on a line indicates the start of a comment that extends to the end of the current line If a 4 appears as the first character of a line the whole line is treated as a commen
270. e separator 226 PowerPC options ena e t rere 224 PowerPO suppOrt erem ne emerit ue 224 precedence of operatorg 00 cee eee eee 44 precision floating point SL e EE 43 pr fixes 1980 4 cese race case se mens pb zu 150 346 PLEPLOCESSING i ccc sistas ENEE EE EENS RENE EA ses 27 preprocessing turning on and off 27 previous directve i zese EEN KEE ENEE 66 primary attributes COFF symbols 42 print directive roris opr firs per einetaas tens 67 proc directive BDARO 263 profiler directive MSP 430 213 profiling capability for MSP 430 213 protected directive sse tei ee e a E 67 pseudo op arch CRIS 22000 124 pseudo op dword CHRIS 123 pseudo op syntax CRIS 000 123 pseudo op BSPEC MMIX 209 pseudo op BYTE MMIX sseeeses 208 pseudo op ESPEC MMIX 209 pseudo op GREG MMIX 207 pseudo op IS MMIX 22 eae 207 pseudo op LOC MMIX 207 pseudo op LOCAL MMIX 207 pseudo op OCTA MMIX 208 pseudo op PREFIX MMIX 209 pseudo op TETRA MMIX 208 pseudo op WYDE MMIX nssssssssisssnscue 208 pseudo opcodes for XStormy16 305 pseudo opcodes Most 182 pseudo opcodes M68HC11 188 pseudo ops for branch VAN 293 pseudo ops GRIS 5 esr bh bes EE d 123 pseudo ops machine independent
271. e specified either using their mnemonic names such as DOReO or using the unit plus register number separated by a such as DO 0 Chapter 9 Machine Dependent Features 191 9 26 MicroBlaze Dependent Features The Xilinx MicroBlaze processor family includes several variants all using the same core instruction set This chapter covers features of the GNU assembler that are specific to the MicroBlaze architecture For details about the MicroBlaze instruction set please see the MicroBlaze Processor Reference Guide UG081 available at www xilinx com 9 26 1 Directives A number of assembler directives are available for MicroBlaze data8 expression This directive is an alias for byte Each expression is assembled into an eight bit value datal6 expression This directive is an alias for hword Each expression is assembled into an 16 bit value data32 expression This directive is an alias for word Each expression is assembled into an 32 bit value ent name label This directive is an alias for func denoting the start of function name at optional label end name label This directive is an alias for endfunc denoting the end of function name gpword label This directive is an alias for rva The resolved address of label is stored in the data section weakext label Declare that label is a weak external symbol rodata Switch to rodata section Equivalent to section rodata
272. e systems if the section is marked as containing code and the fill value is omitted the space is filled with no op instructions The third expression is also absolute and is also optional If it is present it is the maximum number of bytes that should be skipped by this alignment directive If doing the alignment would require skipping more bytes than the specified maximum then the alignment is not done at all You can omit the fill value the second argument entirely by simply using two commas after the required alignment this can be useful if you want the alignment to be filled with no op instructions when appropriate The way the required alignment is specified varies from system to system For the arc hppa 1386 using ELF i860 132000 m68k or32 s390 sparc tic4x tic80 and xtensa the first expression is the alignment request in bytes For example align 8 advances the location counter until it is a multiple of 8 If the location counter is already a multiple of 8 no change is needed For the tic54x the first expression is the alignment request in words For other systems including ppc i386 using a out format arm and strongarm it is the number of low order zero bits the location counter must have after advancement For example align 3 advances the location counter until it a multiple of 8 If the location counter is already a multiple of 8 no change is needed This inconsistency is due to the different behaviors of
273. e which should be added to the cycle counter zero if omitted extra any extra parameter zero if omitted For example global fxx type fxx function xx LFrameO0ffset fxx 0x08 profiler scdP fxx function entry we also demand stack value to be saved push rii push r10 push r9 push r8 profiler cdpt fxx 0 LFrameOffset_fxx check stack value at this point this is a prologue end note that spare var filled with the farme size mov ri5 r8 profiler cdE fxx check stack pop r8 pop r9 pop r10 pop rii profiler xcde fxx 3 exit adds 3 to the cycle counter ret cause ret insn takes 3 cycles Chapter 9 Machine Dependent Features 215 9 30 Nios II Dependent Features 9 30 1 Options relax section Replace identified out of range branches with PC relative jmp sequences when possible The generated code sequences are suitable for use in position independent code but there is a practical limit on the extended branch range because of the length of the sequences This option is the default relax all Replace branch instructions not determinable to be in range and all call in structions with jmp and callr sequences respectively This option gener ates absolute relocations against the target symbols and is not appropriate for position independent code no relax Do not replace any branches or calls EB Generate big endian output EL Generate little endian output This is the default 9
274. e2 corei7 liom klom k6 k6_2 athlon k8 amdfam10 pdver1 pdver2 pdver3 ptver1 ptver2 generic32 generic64 mmx sse sei sse3 ease Sse4 1 Sse4 2 sei avx vmx emx ept clflush movbe xsave xsaveopt aes pclmul fma fsgsbase rdrnd 16c avx2 bmi lzent invpcid vmfunc hle rtm adx rdseed prfchw smap mpx smap sha 3dnow 3dnowa sse4a Sseb syscall rdtscp svme abm lwp fma4 xop WAR padlock smap avx512f avxbi12cd avxbi2er avxb12pf 3dnow 3dnowa sse4a Sseb syscall rdtscp svme Chapter 9 Machine Dependent Features 155 D H H H abm lwp fma4 Xop cx16 padlock Apart from the warning there are only two other effects on as operation Firstly if you specify a CPU other than i486 then shift by one instructions such as sarl 1 eax will automatically use a two byte opcode sequence The larger three byte opcode sequence is used on the 486 and when no architecture is specified because it executes faster on the 486 Note that you can explicitly request the two byte opcode by writing sarl Zeax Secondly if you specify 18086 i186 or i286 and code16 or code1
275. eatures 0c cece eee e 166 9 19 1 IP2K Options iiie teet dette nen ages 166 9 19 2 IP2K Zonen een REESEN Pese RO EE RIO Ps 166 9 19 2 1 Special Characters 0 0 ccc cece ees 166 9 20 LM32 Dependent Features 0 0 0 cece cece eee ees 167 Using as 9 20 1 OptlOUBS SNE EE de EE 167 9 20 2 SYNTAR enesis eke a Ea eE See AE d inne 167 9 20 2 1 Register Names 0 ere eee eee eens 167 9 20 2 2 Relocatable Expression Modifiers 168 9 20 2 3 Special Characters 00 ccc eee eee ences 169 9 20 89 OpeodeSuccocee senec enh esgededag cones EREREESENW EE 169 9 21 M32C Dependent Features 170 9 21 1 M320 Options Rene rere RR eet eR d e 170 9 21 2 M32U Syntax EE e PR E et p SPESE ee die 170 9 21 2 1 Symbolic Operand Modifiers 0 170 9 21 2 2 Special Character T71 9 22 M32R Dependent Heatures 0c eee eee eee eee e 9 221 M32R Options a0 NEE poses eR EROR a Res 172 9 222 M32R Directives 4ss2 34 ro ERER RO RD OI EVE 173 9 22 3 M32R Warnings sssseeeeeee eee eees 174 9 22 M680x0 Dependent Features 176 9 23 4 M680x0 Omntions I 176 9 28 2 ube sisse tut ERR Rad E Y IRI EI RU RERMP REREOC EIE 179 9 28 9 Motorola Syntax 2 00000 REENEN SEENEN da gage RE a 180 9 28 4 Floating Point usus dE RR Rn REUS EA 181 9 23 5 680x0 Machine Directive 181 9 283 6 OpOcodeS censu cessxcr E EE er Ya Pe m due d 182 9 23 6 1 Branch Iuprovement cece 182
276. ece eee eee ees 53 double directive 080 152 double directive Mogtt 181 double directive MoSHCIT 188 double directive HS 230 double directive TIOR4 268 double directive VAN 292 double directive z8p p4 20 eee 152 double directive ZOGATR 304 doublequote DN entendu ese 30 drlist directive TIC5AX o siseirisisrssis eses 268 drnolist directive TIC54X 268 dual directive 1860 2 2052 0 s00 secre EE Ne 156 dword directive Nios II 0 216 E EB command line option Nios II 215 ecr register VR 299 eight byte Abee esezesteenpen ke RES rers 68 eipc register V850 eee e eee ee 298 eipsw register VSbU einni binio sis eia 298 eject directives ciue e EES 53 EL command line option Nios II 215 ELF symbol type 0 eee eee eee 76 else Celtes 53 elseif directive said defekter Pu mede 53 empty expressionS eseese en m nne 43 Using as emsg directive TIC54X 0 000 268 CMUlAtON 205 das40c poe Bl Aser Ra EN Te 14 encoding options 1290 148 encoding options x86 64 00000 148 end directive 25a phd errr nri tert re ace ga MES 53 enddual directive 1900 157 endef directiy6 ioc SE AIRgep e E e 54 endfiine directives isse LEES RR MES de 54 endianness MIDD 12 endianness PJ iiie toerien BEE 10 endif directive iei pe cuilibet eu A KAN 54 endloop directive TIC54X
277. ecified as part of a FLIX bundle the assembler will choose the smallest format where the opcode can be encoded and will fill unused instruction slots with no ops 9 52 2 1 Opcode Names See the Xtensa Instruction Set Architecture ISA Reference Manual for a complete list of opcodes and descriptions of their semantics If an opcode name is prefixed with an underscore character _ as will not trans form that instruction in any way The underscore prefix disables both optimization see Section 9 52 3 Xtensa Optimizations page 308 and relaxation see Section 9 52 4 Xtensa Relaxation page 309 for that particular instruction Only use the underscore prefix when it is essential to select the exact opcode produced by the assembler Using this feature un necessarily makes the code less efficient by disabling assembler optimization and less flexible by disabling relaxation Note that this special handling of underscore prefixes only applies to Xtensa opcodes not to either built in macros or user defined macros When an underscore prefix is used with a macro e g _MOV it refers to a different macro The assembler generally provides 308 Using as built in macros both with and without the underscore prefix where the underscore versions behave as if the underscore carries through to the instructions in the macros For example _MOV may expand to _MOV N The underscore prefix only applies to individual instructions not to series of
278. ecify params when you create a subsection in the first instance of subspa for this name If specified the list params declares attributes of the subsection identified by keywords The keywords recognized are quad expr quadrant for this subsection align expr alignment for beginning of this subsection a power of two access expr value for access rights field sort expr sorting order for this subspace in link code_only subsection contains only code unloadable subsection cannot be loaded into memory comdat subsection is comdat common subsection is common block dup_comm subsection may have duplicate names or zero subsection is all zeros do not write in object file nsubspa always creates a new subspace with the given name even if one with the same name already exists comdat common and dup_comm can be used to implement various flavors of one only support when using the SOM linker The SOM linker only supports specific combinations of these flags The details are not documented A brief description is provided here comdat provides a form of linkonce support It is useful for both code and data subspaces A comdat subspace has a key symbol marked by the is_comdat flag or ST_COMDAT Only the first subspace for any given key is selected The key symbol becomes universal in shared links This is similar to th
279. ection 3 1 Preprocessing page 27 The character can be used instead of a newline to separate statements 9 37 3 Instruction syntax The assembler syntax closely follows the syntax outlined in Enterprise Systems Architec ture 390 Principles of Operation SA22 7201 and the z Architecture Principles of Opera tion SA22 7832 232 Using as Each instruction has two major parts the instruction mnemonic and the instruction operands The instruction format varies 9 37 3 1 Register naming The as recognizes a number of predefined symbols for the various processor registers A register specification in one of the instruction formats is an unsigned integer between 0 and 15 The specific instruction and the position of the register in the instruction format denotes the type of the register The register symbols are prefixed with 7 rN the 16 general purpose registers 0 lt N lt 15 N the 16 floating point registers 0 lt N lt 15 aN the 16 access registers 0 lt N lt 15 cN the 16 control registers 0 lt N lt 15 lit an alias for the general purpose register r13 sp an alias for the general purpose register r15 9 37 3 2 Instruction Mnemonics All instructions documented in the Principles of Operation are supported with the mnemonic and order of operands as described The instruction mnemonic identifies the instruction format Section 9 37 3 4 s390 Formats page 235 and the specific operati
280. ective PREFIX 209 MMIX assembler directive TETRA 208 MMIX assembler directive WYDE 208 MMIX assembler directe 207 MMIX line comment characters 205 MMIX opntieong A eee NET EN eee 204 MMIX pseudo op BSPEC ssse 209 MMIX pseudo op BYTE 208 344 MMIX pseudo op ESP 209 MMIX pseudo op GRO 207 MMIX pseudo op IA 207 MMIX pseudo op LOC ss 207 MMIX pseudo op LOCAL 207 MMIX pseudo op OCTA sssssss 208 MMIX pseudo op PREFIX 209 MMIX pseudo op TETRA 208 MMIX pseudo op WYDE 208 MMIX pG eudo ops 2 cece eee eee eee 207 MMIX register namen 206 MMIX support ENEE C ER Ad 204 mmixal d ferences siariad 209 mmregs directive TIC54X 000 270 mmsg directive TIC54X 0 cece eens 268 OC E Dee durto aenea Se a 152 MMX X80 04 oi gunk cleans SE SE pn eens 152 mnemonic compatibility i886 149 mnemonic suffixes 280 147 mnemonic suffixes HDD 147 mnemonics for opcodes MAX 293 mnemonics AND 111 mnemonics DIN 128 mnemonics D30V x cep mer Re 132 mnemonics H8 300 lssssssssssssse 136 mnemonics LM32 sueeeesss 169 mnemonics SH 250 mnemonics Hoi 253 mnemonics Z8000 eee eee eee ees 291 mnolist directive TIC54X 0 270
281. ed by the character The character in jump instructions indicates current location and implemented only for TI syntax compatibility 9 29 2 3 Register Names General purpose registers are represented by predefined symbols of the form rN for global registers where N represents a number between 0 and 15 The leading letters may be in either upper or lower case for example r13 and R7 are both valid register names Register names PC SP and SR cannot be used as register names and will be treated as variables Use ro r1 and r instead 9 29 2 4 Assembler Extensions rN As destination operand being treated as O rn 0 rN As source operand being treated as rn jCOND N Skips next N bytes followed by jump instruction and equivalent to jCOND N 2 Also there are some instructions which cannot be found in other assemblers These are branch instructions which has different opcodes upon jump distance They all got PC relative addressing mode beq label A polymorph instruction which is jeq label in case if jump distance within allowed range for cpu s jump instruction If not this unrolls into a sequence of jne 6 br label bne label A polymorph instruction which is jne label or jeq 4 br label blt label A polymorph instruction which is jl label or jge 4 br label bltn label A polymorph instruction which is jn label
282. ed or unsegmented mode of the operand is in the instruction address rn Indexed the 16 or 24 bit address is added to the 16 bit register to produce the final address in memory of the operand rn imm rrn imm Base Address the 16 or 24 bit register is added to the 16 bit sign extended immediate displacement to produce the final address in memory of the operand rn rm rrn rm Base Index the 16 or 24 bit register rn or rrn is added to the sign extended 16 bit index register rm to produce the final address in memory of the operand xx Immediate data xx 9 47 3 Assembler Directives for the Z8000 The Z8000 port of as includes additional assembler directives for compatibility with other 48000 assemblers These do not begin with unlike the ordinary as directives segm z8001 Generate code for the segmented Z8001 unsegm z8002 Generate code for the unsegmented Z8002 name Synonym for file global Synonym for global wval Synonym for word lval Synonym for long bval Synonym for byte sval Assemble a string sval expects one string literal delimited by single quotes It assembles each byte of the string into consecutive addresses You can use the escape sequence ax where xx represents a two digit hexadecimal number to represent the character whose ASCII value is xx Use this feature to describe single quote and other characters that may not appear in string literals as themselves For example the C st
283. ediate value signed pc relative offset from 64 to 63 signed pc relative offset from 2048 to 2047 absolute code address call jmp immediate value from 0 to 7 S s 4 use this opcode entry if no parameters else use next opcode entry 4 DE D Gm mm H SH Co sg D SA 1001010010001000 clc 1001010011011000 clh 1001010011111000 cli 1001010010101000 cln 1001010011001000 cls 1001010011101000 clt 1001010010111000 clv 1001010010011000 elz 1001010000001000 sec 1001010001011000 seh 1001010001111000 sei 1001010000101000 sen 1001010001001000 ses 1001010001101000 set 1001010000111000 sev 1001010000011000 sez 100101001SSS1000 bclr S 1001010008881000 bset S 1001010100001001 icall 112 1001010000001001 1001010111001000 1001000ddddd010 1001010111011000 1001000ddddd011 0000000000000000 1001010100001000 1001010100011000 1001010110001000 1001010110011000 1001010110101000 1001010111101000 000111rdddddrrrr 000011rdddddrrrr 001000rdddddrrrr 000101rdddddrrrr 000001rdddddrrrr 000100rdddddrrrr 001001rdddddrrrr 001011rdddddrrrr 100111rdddddrrrr 001010rdddddrrrr 000010rdddddrrrr 000110rdddddrrrr 001001rdddddrrrr 000011rdddddrrrr 000111rdddddrrrr 001000rdddddrrrr 0111KKKKddddKKKK 0111KKKKddddKKKK 1110KKKKddddKKKK 11101111dddd1111 O110KKKKddddKKKK O110KKKKddddKKKK 0011KKKKddddKKKK O100KKKKddddKKKK O101KKKKddddKKKK 1111110rrrrr0sss 1111111rrrrrOsss 1111100ddddd0sss 1111101ddddd0sss 10110PPdddddPPPP 10111PPrrrrrPPPP 10
284. edium is called an aggregate if the copyright resulting from the compilation is not used to limit the legal rights of the compilation s users beyond what the individual works permit When the Document is included in an aggregate this License does not apply to the other works in the aggregate which are not themselves derivative works of the Document If the Cover Text requirement of section 3 is applicable to these copies of the Document then if the Document is less than one half of the entire aggregate the Document s Cover Texts may be placed on covers that bracket the Document within the aggregate or the electronic equivalent of covers if the Document is in electronic form Otherwise they must appear on printed covers that bracket the whole aggregate TRANSLATION Translation is considered a kind of modification so you may distribute translations of the Document under the terms of section 4 Replacing Invariant Sections with translations requires special permission from their copyright holders but you may include translations of some or all Invariant Sections in addition to the original versions of these Invariant Sections You may include a translation of this License and all the license notices in the Document and any Warranty Disclaimers provided that you also include the original English version of this License and the original versions of those notices and disclaimers In case of a disagreement between the translation and the orig
285. eeir ri ccc eee eee eee 56 hidden names isssas secte EE 56 hword expressions cea bee yer eia dere eos 57 E EE 57 jf absolute expressiOn e e Rar EROR RR wee 57 incbin file skipl count l ck Re 58 iii 64 include file ung uu Ub a Eg db eer ede 1 60 sint expressis ccisiricir di triant eee reese rh a ds 7 060 internal names EIER Et NEE ENNEN E Ee eia 607 irpsSymbol valueS eere ter noorie tyon RO eda 7 68 irpc ammbol values cee eee 1 60 lcomm symbol length eec etr awed te enews year P GOL Jine Iine number e RR Ed eg 2 linkonce typel uieeuernee bU Ree ue axes Pees du BUDS EE 6X4 Imlrne numnber ved e qe dee RERO EU Wa Vente bas 7 75 loc fileno lineno column loptions 7 76 loc mark labels enable sse eee GCC local fames pkcweeek asa ue pA ERU EAS a GU EEN TIS long expressions ves rere rera Re wed en E E E e erede ueeE EDEN ee tebe bese gee pM acci EE LSL noalUnacroliildueeberexr E dc 4 de oe sc ER REPRE 82 OVS Cris circa tua Ru thie REC UP SUHERR DUX cre tan tenes 83 sota bignudlBS 22g eux e E Rack ERU ERN I I oA ares G84 offset lOCiliuisie pese er Reb DEVE CU COE ERR Rs 85 org new lc fill iss sees erra a nano ones 7 86 p2align wl abs expr abs expr abs expr TST popsecbtlonzgiiscnensesnceer no baia ehe tes RE sani RR preViOUS ENER eee ek e e hr CR ERR E CES E rr ice 1S9 Jprint SELLING enre niori eerta Eu he
286. eenedd e ebd dude ores eerte d aed 48 GO ascll SCID i m we mees er eb PENES RE ORE caus E ERA 48 KO sasciz EE 48 7 7 balign wl abs expr abs expr abs expr 48 7 8 bundle align mode abs expr 6 ccc cece eee eee 49 7 9 bundle lock and bundle unlock 000s eee ee 49 GI byte expressiO0ns o d poke vba doesn donee ues 50 7 11 cfi sections section list sse esee 50 tidy cfi startproc simplel v 10 4 eser Y REPRE 50 GAS CET endprOoe curerb dc e teme ehe E ER DE RE deaneye eset 50 7 14 cfi personality encoding expl 50 7 15 ett Lada encoding exp cc cece eee eects 50 7 16 7 17 7 18 7 19 7 20 7 21 7 22 7 23 7 24 7 25 7 26 C27 7 28 7 29 7 30 7 31 7 32 7 33 7 34 7 35 7 36 7 37 7 38 7 39 7 40 7 41 7 42 7 43 7 44 7 45 7 46 7 47 7 48 7 49 1 50 7 51 1 52 1 53 7 04 1 55 1 56 7 07 1 58 1 59 1 60 7 61 7 62 7 63 cfi_def_cfa register offset 0 6 cee ees 50 cfi_def_cfa_register register sss eee 51 Gfi def cfa offset Offset e aada es 51 cfi adjust cfa offset offset 00s ccc eee 51 Cfi offset register offset essel 51 cfi rel offset register offeer cece ene 51 cfi register register1 regieter s 51 Cfi restore register ie si ss d ebbe re due 51 cfi undefined register eso dete cesta eee 51 cfi same value register cece eee ees 51 Cfi remember Sta
287. eline executes each instruction If the instructions cannot be bundled in the listed order the assembler will automatically try to find a valid pipeline assignment If there is no way to bundle the instructions together the assembler reports an error The assembler does not yet auto bundle automatically combine multiple instructions into one bundle but it reserves the right to do so in the future If you want to force an instruction to run by itself put it in a bundle explicitly with curly braces and use nop instructions not fnop to fill the remaining pipeline slots in that bundle 9 45 2 1 Opcode Names For a complete list of opcodes and descriptions of their semantics see TILE Processor User Architecture Manual available upon request at www tilera com 9 45 2 2 Register Names General purpose registers are represented by predefined symbols of the form rN where N represents a number between 0 and 63 However the following registers have canonical names that must be used instead r54 sp r55 Ir Chapter 9 Machine Dependent Features 283 r56 r57 r58 r59 r60 r61 r62 r63 sn idn0 idn1 udn0 udnl udn2 udn3 Zero The assembler will emit a warning if a numeric name is used instead of the canonical name The no require canonical reg names assembler pseudo op turns off this warn ing require canonical reg names turns it back on 9 45 2 3 Symbolic Operand Modifiers The assembler supports several m
288. em with the surrounding code 9 27 3 Directives to override the size of symbols The n64 ABI allows symbols to have any 64 bit value Although this provides a great deal of flexibility it means that some macros have much longer expansions than their 32 bit counterparts For example the non PIC expansion of dla 4 sym is usually lui 4 highest sym lui 1 hi sym daddiu 4 4 higher sym daddiu 1 1 10 sym ds1132 4 4 0 daddu 4 4 1 whereas the 32 bit expansion is simply lui 4 hi sym daddiu 4 4 410 sym n64 code is sometimes constructed in such a way that all symbolic constants are known to have 32 bit values and in such cases it s preferable to use the 32 bit expansion instead of the 64 bit expansion You can use the set sym32 directive to tell the assembler that from this point on all expressions of the form symbol or symbol offset have 32 bit values For example Set sym32 dla 4 sym Chapter 9 Machine Dependent Features 199 lw 4 sym 16 sw 4 sym 0x8000 4 will cause the assembler to treat sym sym 16 and sym 0x8000 as 32 bit values The handling of non symbolic addresses is not affected The directive set nosym32 ends a set sym32 block and reverts to the normal behavior It is also possible to change the symbol size using the command line options msym32 and mno sym32 These options and directives are always accepted but at present they have no effect for
289. embler to generate the Tag ABI PIC attribute with a value of 1 indicating that the code is using position independent code addressing The mno pic option the default causes the tag to have a value of 0 indicating position dependent code addressing The linker will emit a warning if objects of different type position dependent and position independent are linked together mbig endian mlittle endian Generate code for the specified endianness The default is little endian 9 43 2 TIC6X Syntax C29 The presence of a on a line indicates the start of a comment that extends to the end of the current line If a or appears as the first character of a line the whole line is treated as a comment Note that if a line starts with a character then it can also be a logical line number directive see Section 3 3 Comments page 27 or a preprocessor control command see Section 3 1 Preprocessing page 27 The character can be used instead of a newline to separate statements Chapter 9 Machine Dependent Features 275 Instruction register and functional unit names are case insensitive as requires fully specified functional unit names such as S1 L1X or D1T2 on all instructions using a functional unit For some instructions there may be syntactic ambiguity between register or functional unit names and the names of labels or other symbols To avoid this enclose the ambiguous
290. emn p e etre Hb ER et den a 312 952 54 literali iii dme tree ret EE Y ke ERES 312 9 52 5 5 literal poosttion 0 cece eee eee eh 313 9 52 5 6 literal pret 314 9 52 5 7 absolute literals 314 10 Reporting Bucs 5 oiscsi ccevsdcnreaas ru ERES 315 10 1 Have You Found a Bug 315 10 2 How to Report Dugs 2 cece eee cece eees 315 11 Acknowledgements 319 Appendix A GNU Free Documentation License 321 Using as Chapter 1 Overview 1 1 Overview This manual is a user guide to the GNU assembler as Here is a brief summary of how to invoke as For details see Chapter 2 Command Line Options page 21 as a cdghlns file alternate LD compress debug sections nocompress debug sections debug prefix map old new defsym sym val f g gstabs gstabs gdwarf 2 gdwarf sections help I dir J K L disting Ihs width NUM listing Ihs width2 NUM listing rhs width NUM isting cont lines NUM keep locals o objfile R reduce memory overheads statistics v version version W warn fatal warnings w x 2 FILE size check error warning target help target options I files Target AArch64 options EB EL mabi ABI Target Alpha options mcpu mdebug no mdebug replace noreplace relax g Gsize F 32addr Target ARC options marc
291. en This directive aligns to an even numbered address extend expression expression ldouble expression expression These directives write 12byte long double floating point values to the output section These are not compatible with current ARM processors or ABIs fnend Marks the end of a function with an unwind table entry The unwind index table entry is created when this directive is processed If no personality routine has been specified then standard personality routine 0 or 1 will be used depending on the number of unwind opcodes required fnstart Marks the start of a function with an unwind table entry force thumb This directive forces the selection of Thumb instructions even if the target processor does not support those instructions fpu name Select the floating point unit to assemble for Valid values for name are the same as for the mfpu commandline option handlerdata Marks the end of the current function and the start of the exception table entry for that function Anything between this directive and the fnend directive will be added to the exception table entry Must be preceded by personality or personalityindex directive inst opcode inst n opcode inst w opcode Generates the instruction corresponding to the numerical value opcode inst n and inst w allow the Thumb instruction size to be specified explicitly overriding the normal encoding rules ldouble
292. ence of a on a line indicates the start of a comment that extends to the end of the current line If a 4 appears as the first character of a line then the whole line is treated as a comment but in this case the line could also be a logical line number directive see Section 3 3 Comments page 27 or a preprocessor control command see Section 3 1 Preprocessing page 27 The character can be used to separate statements on the same line 134 Using as 9 12 H8 300 Dependent Features 9 12 1 Options The Renesas H8 300 version of as has one machine dependent option h tick hex Support H 00 style hex constants in addition to 0x00 style 9 12 2 Syntax 9 12 2 1 Special Characters is the line comment character can be used instead of a newline to separate statements Therefore you may not use in symbol names on the H8 300 9 12 2 2 Register Names You can use predefined symbols of the form rnh and rn1 to refer to the H8 300 registers as sixteen 8 bit general purpose registers n is a digit from 0 to 7 for instance both rOh and r71 are valid register names You can also use the eight predefined symbols rn to refer to the H8 300 registers as 16 bit registers you must use this form for addressing On the H8 300H you can also use the eight predefined symbols ern er0 er7 to refer to the 32 bit general purpose registers The two control
293. ency violation checker xdebugn This is a shortcut for xnone xdebug xdebugx This is a shortcut for xexplicit xdebug 9 18 2 Syntax The assembler syntax closely follows the IA 64 Assembly Language Reference Guide 9 18 2 1 Special Characters is the line comment token can be used instead of a newline to separate statements 9 18 2 2 Register Names The 128 integer registers are referred to as rn The 128 floating point registers are referred to as fn The 128 application registers are referred to as arn The 128 control registers are referred to as crn The 64 one bit predicate registers are referred to as pn The 8 branch registers are referred to as bn In addition the assembler defines a number of aliases gp r1 sp r12 rp b0 reto r8 rett r9 ret r10 ret3 r9 fargn f8tn and fretn f8 n For convenience the assembler also defines aliases for all named application and con trol registers For example ar bsp refers to the register backing store pointer ar17 Similarly cr eoi refers to the end of interrupt register cr67 9 18 2 3 IA 64 Processor Status Register PSR Bit Names The assembler defines bit masks for each of the bits in the LA 64 processor status register For example psr ic corresponds to a valu
294. entiate between the two labels in SHmedia sections will always have the least signifi cant bit set i e they will be odd which SHcompact labels will have the least significant bit reset i e they will be even If you need to reference the actual address of a label you can use the datalabel modifier as in this example long function long datalabel function In that example the first longword may or may not have the least significant bit set depending on whether the label is an SHmedia label or an SHcompact label The second longword will be the actual address of the label regardless of what type of label it is 9 40 3 SH64 Machine Directives In addition to the SH directives the SH64 provides the following directives mode shmedia shcompact isa shmedia shcompact Specify the ISA for the following instructions the two directives are equivalent Note that programs such as objdump rely on symbolic labels to determine when such mode switches occur by checking the least significant bit of the label s address so such mode isa changes should always be followed by a label in practice this is true anyway Note that you cannot use these directives if you didn t specify an ISA on the command line Chapter 9 Machine Dependent Features 253 abi 32164 Specify the ABI for the following instructions Note that you cannot use this di rective unless you specified an ABI on the command line and the ABIs specified must match 9 4
295. ependent Features 9 9 1 D10V Options The Mitsubishi D10V version of as has a few machine dependent options Q The D10V can often execute two sub instructions in parallel When this option is used as will attempt to optimize its output by detecting when instructions can be executed in parallel nowarnswap To optimize execution performance as will sometimes swap the order of in structions Normally this generates a warning When this option is used no warning will be generated when instructions are swapped gstabs packing no gstabs packing as packs adjacent short instructions into a single packed instruction no gstabs packing turns instruction packing off if gstabs is specified as well gstabs packing the default turns instruction packing on even when gstabs is specified 9 9 2 Syntax The D10V syntax is based on the syntax in Mitsubishi s D10V architecture manual The differences are detailed below 9 9 2 1 Size Modifiers The D10V version of as uses the instruction names in the D10V Architecture Manual However the names in the manual are sometimes ambiguous There are instruction names that can assemble to a short or long form opcode How does the assembler pick the correct form as will always pick the smallest form if it can When dealing with a symbol that is not defined yet when a line is being assembled it will always use the long form If you need to force the assem
296. eplacement might be ambiguous by placing colons on either side of the subsym The following code eval 10 x LAB X add 4x a When assembled becomes LAB10 add 10 a Smaller parts of the string assigned to a subsym may be accessed with the following syntax symbol char_index Evaluates to a single character string the character at char_index symbol start length Evaluates to a substring of symbol beginning at start with length length 9 42 6 Local Labels Local labels may be defined in two ways e N where N is a decimal number between 0 and 9 e LABEL where LABEL is any legal symbol name Local labels thus defined may be redefined or automatically generated The scope of a local label is based on when it may be undefined or reset This happens when one of the following situations is encountered e newblock directive see Section 9 42 9 newblock page 267 e The current section is changed sect text or data e Entering or leaving an included file e The macro scope where the label was defined is exited 9 42 7 Math Builtins The following built in functions may be used to generate a floating point value All return a floating point value except cvi int and sgn which return an integer value acos expr Returns the floating point arccosine of expr asin expr Returns the floating point arcsine of expr atan expr Returns the floating point arctangent of expr 266 Usin
297. equence involv ing another branch however this has not been implemented and if their target turns out of reach they produce an error even if branch relaxation is enabled Also no MIPS16 branches are ever relaxed By default no relax branch is selected causing any out of range branches to produce an error mnan encoding This option indicates whether the source code uses the IEEE 2008 NaN en coding mnan 2008 or the original MIPS encoding mnan legacy It is equivalent to adding a nan directive to the beginning of the source file See Section 9 27 9 MIPS NaN Encodings page 201 mnan legacy is the default if no mnan option or nan directive is used trap no break as automatically macro expands certain division and multiplication instruc tions to check for overflow and division by zero This option causes as to generate code to take a trap exception rather than a break exception when an error is detected The trap instructions are only supported at Instruction Set Architecture level 2 and higher break no trap Generate code to take a break exception rather than a trap exception when an error is detected This is the default mpdr mno pdr Control generation of pdr sections Off by default on IRIX on elsewhere mshared mno shared When generating code using the Unix calling conventions selected by KPIC or mcall_shared gas will normally generate code which ca
298. er of the version it refers to gives permission For any section Entitled Acknowledgements or Dedications Preserve the Title of the section and preserve in the section all the substance and tone of each of the contributor acknowledgements and or dedications given therein Preserve all the Invariant Sections of the Document unaltered in their text and in their titles Section numbers or the equivalent are not considered part of the section titles Delete any section Entitled Endorsements Such a section may not be included in the Modified Version Do not retitle any existing section to be Entitled Endorsements or to conflict in title with any Invariant Section Preserve any Warranty Disclaimers If the Modified Version includes new front matter sections or appendices that qualify as Secondary Sections and contain no material copied from the Document you may at your option designate some or all of these sections as invariant To do this add their Appendix A GNU Free Documentation License 325 titles to the list of Invariant Sections in the Modified Version s license notice These titles must be distinct from any other section titles You may add a section Entitled Endorsements provided it contains nothing but endorsements of your Modified Version by various parties for example statements of peer review or that the text has been approved by an organization as the authoritative definition of a standard
299. ere on a line indicates the start of a comment that extends to the end of that line If a appears as the first character of a line then the whole line is treated as a com ment but in this case the line can also be a logical line number directive see Section 3 3 Comments page 27 or a preprocessor control command see Section 3 1 Preprocessing page 27 If Sequent compatibility has been configured into the assembler then the character appearing as the first character on a line will also indicate the start of a line comment The character can be used to separate statements on the same line Chapter 9 Machine Dependent Features 219 9 32 PDP 11 Dependent Features 9 32 1 Options The PDP 11 version of as has a rich set of machine dependent options 9 32 1 1 Code Generation Options mpic mno pic Generate position independent or position dependent code The default is to generate position independent code 9 32 1 2 Instruction Set Extension Options These options enables or disables the use of extensions over the base line instruction set as introduced by the first PDP 11 CPU the KA11 Most options come in two variants a mextension that enables extension and a mno extension that disables extension The default is to enable all extensions mall mall extensions Enable all instruction set extensions mno extensions Disable all instruction set extensions mcis mno cis Enable
300. erm quad comes from contexts in which a word is two bytes hence quad word for 8 bytes 7 95 reloc offset reloc_name expression Generate a relocation at offset of type reloc name with value expression If offset is a number the relocation is generated in the current section If offset is an expression that resolves to a symbol plus offset the relocation is generated in the given symbol s section expression if present must resolve to a symbol plus addend or to an absolute value but note that not all targets support an addend e g ELF REL targets such as i386 store an addend in the section contents rather than in the relocation This low level interface does not support addends stored in the section 7 96 rept count Repeat the sequence of lines between the rept directive and the next endr directive count times For example assembling rept 3 Long 0 endr is equivalent to assembling Long 0 Long 0 Long 0 Chapter 7 Assembler Directives 69 7 97 sbttl subheading Use subheading as the title third line immediately after the title line when generating assembly listings This directive affects subsequent pages as well as the current page if it appears within ten lines of the top of a page 7 98 scl class Set the storage class value for a symbol This directive may only be used inside a def endef pair Storage class may flag whether a symbol is static or external or it may record further sy
301. ers and also some multicharacter special symbols like or Comments are introduced by the character and extend to the end of the current line If the appears as the first character of a line the whole line is treated as a comment but in this case the line can also be a logical line num ber directive see Section 3 3 Comments page 27 or a preprocessor control command see Section 3 1 Preprocessing page 27 Instruction Delimiting A semicolon must terminate every instruction Sometimes a complete instruc tion will consist of more than one operation There are two cases where this occurs The first is when two general operations are combined Normally a comma separates the different parts as in a0 r3 h r2 1 al r3 1 r2 h The second case occurs when a general instruction is combined with one or two memory references for joint issue The latter portions are set off by a token a0 r3 h r2 1 r1 p3 r4 i24 Multiple instructions can occur on the same line Each must be terminated by a semicolon character Chapter 9 Machine Dependent Features 115 Register Names The assembler treats register names and instruction keywords in a case insensi tive manner User identifiers are case sensitive Thus R3 l R3 L r3 l and r3 L are all equivalent input to the assembler Register names are reserved and may not be used as program identifiers Some operations such as Mo
302. ers this modifier selects the 16 most significant bits movw ax hi16 _sym 4hi8O When loading a 20 bit or wider address into registers this modifier selects the 8 bits that would go into CS or ES i e bits 23 16 mov es hi8 _sym 9 35 3 Assembler Directives In addition to the common directives the RL78 adds these double Output a constant in double format which is a 32 bit floating point value on RL78 bss Select the BSS section Sbyte Output a constant value in a three byte format int word Output a constant value in a four byte format 9 35 4 Syntax for the RL78 9 35 4 1 Special Characters 3 The presence of a appearing anywhere on a line indicates the start of a comment that extends to the end of that line If a appears as the first character of a line then the whole line is treated as a com ment but in this case the line can also be a logical line number directive see Section 3 3 Comments page 27 or a preprocessor control command see Section 3 1 Preprocessing page 27 The character can be used to separate statements on the same line 228 Using as 9 36 RX Dependent Features 9 36 1 RX Options The Renesas RX port of as has a few target specfic command line options m32bit doubles This option controls the ABI and indicates to use a 32 bit float ABI It has no effect on the assembled instructions but it does influence the behaviour of the double pseu
303. erve Seg Skip word xword Machine Dependent Features 263 This must be followed by a symbol name a positive number and bss This behaves somewhat like comm but the syntax is different This is functionally identical to short On the Sparc the nword directive produces native word sized value ie if as sembling with 32 it is equivalent to word if assembling with 64 it is equivalent to xword This directive is ignored Any text following it on the same line is also ignored This directive declares use of a global application or system register It must be followed by a register name g2 Dei g6 or V6g7 comma and the symbol name for that register If symbol name is scratch it is a scratch register if it is ignore it just suppresses any errors about using undeclared global register but does not emit any information about it into the object file This can be useful e g if you save the register before use and restore it after This must be followed by a symbol name a positive number and bss This behaves somewhat like 1comm but the syntax is different This must be followed by text data or data1 It behaves like text data or data 1 This is functionally identical to the space directive On the Sparc the word directive produces 32 bit values instead of the 16 bit values it produces on many other machines On the Sparc V9 processor the xword directive produces 64 bit values
304. es No h switch at all allows case hacking as described above A value of zero hO implies names should be upper case and inhibits the case hack A value of 2 h2 implies names should be all lower case with no case hack A value of 3 h3 implies that case should be preserved The value 1 is unused The H option directs as to display every mapped symbol during assembly Symbols whose names include a dollar sign are exceptions to the general name mapping These symbols are normally only used to reference VMS library names Such symbols are always mapped to upper case E The option causes as to truncate any symbol name larger than 31 char acters The option also prevents some code following the _main symbol normally added to make the object file compatible with Vax 11 C eq This option is ignored for backward compatibility with as version 1 x HI The H option causes as to print every symbol which was changed by case mapping 9 48 2 VAX Floating Point Conversion of flonums to floating point is correct and compatible with previous assemblers Rounding is towards zero if the remainder is exactly half the least significant bit D F G and H floating point formats are understood Immediate floating literals e g S 6 9 are rendered correctly Again rounding is towards zero in the boundary case The float directive produces f format numbers The double dire
305. es 248 9 30 2 e EEN ebe Eed BEE TUE EAR E dE deg ce 248 9 39 2 1 Special Characters 0 0 ccc eee eee ees 248 9 39 2 2 Register Names sesido iini EU um ete elitse 249 9 39 2 3 Addressing Modes 0c eee cece eens 249 xi xii 9 39 3 Floating Point e b e e RR 249 9 39 4 SH Machine Directive 250 9 99 5 OpCOdess gea v trafen vH RA ds 250 9 40 SuperH SH64 Dependent Features 251 9 40 1 OpliODSsu oe eere cbe ket exces Enero EA 251 9 40 2 EEN 251 9 40 2 1 Special Character 251 9 40 2 2 Register Names 0 eee e cece nn 252 9 40 2 3 Addressing Modes cece eee eee ees 252 9 40 3 SH64 Machine Directive 252 9 40 4 Opeodes cies eR Ae AE PC EUS 253 9 41 SPARC Dependent Features 0 ccc ccc 254 DALLA Gene 254 9 41 2 Enforcing aligned data 255 9 41 9 Spare DyhUaX gege d eg Ao AT Da A RU des 255 9 41 3 1 Special Characters lle 256 9 41 3 2 Register Name 256 9 41 3 8 ConstantiS ieen M gp dr RR RR UE 258 941 3 4 Relocations edd ee teet be hens 259 9 41 3 5 Size Translations esses 261 9 41 4 Floating Point occ iere Rene 262 9 41 5 Sparc Machine Directive 262 9 42 TIC54X Dependent Features 264 9 42 1 Options si cacveenecirerisedide AREE PIPER IRR e DEBES 264 942 2 Blocking sete heh aee ERR Eh 264 9 42 3 Environment Settings 20 c cece ee eee eee ee 264 9 42 4 Constants Syntax s eean a eee eens 264 9 42 5 String Substitution 2 4 0 os
306. ession Assembles the following section of code if the argument is zero ifeqs string1 string2 Another form of ifc The strings must be quoted using double quotes ifge absolute expression Assembles the following section of code if the argument is greater than or equal to zero ifgt absolute expression Assembles the following section of code if the argument is greater than zero 58 Using as ifle absolute expression Assembles the following section of code if the argument is less than or equal to Zero iflt absolute expression Assembles the following section of code if the argument is less than zero ifnb text Like ifb but the sense of the test is reversed this assembles the following section of code if the operand is non blank non empty ifnc stringi string2 Like ifc but the sense of the test is reversed this assembles the following section of code if the two strings are not the same ifndef symbol ifnotdef symbol Assembles the following section of code if the specified symbol has not been defined Both spelling variants are equivalent Note a symbol which has been referenced but not yet defined is considered to be undefined ifne absolute expression Assembles the following section of code if the argument is not equal to zero in other words this is equivalent to if ifnes string1 string2 Like ifeqs but the sense of the test is reversed this assembles the following section of code if the two str
307. ession internally as combinations of symbols When it needs to represent an expression as a symbol it puts it in the expr section 4 4 Sub Sections Assembled bytes conventionally fall into two sections text and data You may have separate groups of data in named sections that you want to end up near to each other in the object file even though they are not contiguous in the assembler source as allows you to use subsections for this purpose Within each section there can be numbered subsections with values from 0 to 8192 Objects assembled into the same subsection go into the object file 36 Using as together with other objects in the same subsection For example a compiler might want to store constants in the text section but might not want to have them interspersed with the program being assembled In this case the compiler could issue a text 0 before each section of code being output and a text 1 before each group of constants being output Subsections are optional If you do not use subsections everything goes in subsection number zero Each subsection is zero padded up to a multiple of four bytes Subsections may be padded a different amount on different flavors of as Subsections appear in your object file in numeric order lowest numbered to highest All this to be compatible with other people s assemblers The object file contains no representation of subsections ld and other programs that manipulate object
308. et processor The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor The following processor names are recognized armi arm2 arm250 arm3 arm6 arm60 arm600 arm610 arm620 arm7 arm 7m arm7d arm7dm arm7di arm7dmi arm70 arm700 arm700i arm710 arm710t arm720 arm720t arm740t arm710c arm7100 arm7500 arm7500fe arm7t arm7tdmi arm7tdmi s arm8 arm810 strongarm strongarmi strongarm110 strongarm1100 strongarmi110 arm9 arm920 arm920t arm922t arm940t arm9tdmi fa526 Faraday FA526 processor fa626 Faraday FA626 processor arm9e arm926e arm926ej s arm946e r0 arm946e arm946e s arm966e r0 arm966e arm966e s arm968e s armiOt armiOtdmi armi0e arm1020 armi1020t arm1020e arm1022e arm1026ej s fa606te Faraday FA606TE processor fa616te Faraday FA616TE processor fa626te Faraday FA626TE processor fmp626 Faraday FMP626 processor fa726te Faraday FA726TE processor arm1136j s armii36jf s arm1156t2 s armiib6t2f s armii76jz s armii76jzf s mpcore mpcorenovfp cortex a5 cortex a cortex a8 cortex a9 cortex al5 cortex r4 cortex r4f cortex r5 cortex r7 cortex m4 cortex m3 cortex mi cortex m0 cortex mOplus ep9312 ARM920 with Cirrus Maverick coprocessor 180200 Intel XScale processor iwmmxt Intel r XScale processor with Wireless MMX tm technology coprocessor and xscale The special name all may be used to allo
309. ette e ata eiie enas 170 en32r Option M32R 4 24 oL E Reda 172 m32rx option M32R2 00 172 m32rx option M32RX e crcsrsiusiariasissss 172 m4byte align command line option V850 296 em64 Option 8390 d EK srias erret 231 m64 option TILE Os 277 m64bit doubles cece eee eee eee eee 228 m68000 and related options dee SMO OWT A soi fo oet onde detenta 184 mo8hCci2 x plot Meera mmm md E 184 noghcBl2 scs obsessus E 184 m8byte align command line option V850 296 mabi command line option AArch64 82 madd bnd prefix option i386 147 madd bnd prefix option x86 64 147 SMa cs esp edi ple EAIP e ren E Saar ad 219 mall enabled command line option LM32 167 imall extensiOns izxo ekkc d br RRx Y ees 219 mall opcodes command line option AVR 109 mapcs 26 command line option ARM 97 mapcs 32 command line option ARM 97 mapcs float command line option ARM 97 mapcs reentrant command line option ARM o EE EE Se SE 97 marc 5161718 command line option ARC 91 march command line option ARM 96 331 march command line option M680x0 176 march command line option TIC6X 274 march option i386 eee eee eee 145 march option s390 2 c eee eee eee 231 march option HD DI 145 matpcs command l
310. eudo directive E format 4 OpCode 4 0 15 RI format lt insn gt R1 I2 4 4 4 4 OpCode R1 OpCd I2 4 4 4 4 0 8 12 16 31 236 RIE format lt insn gt R1 R3 12 4 4 4 4 4 4 4 OpCode R1 R3 I2 I OpCode 4 4 4 4 4 4 4 0 8 12 16 32 40 47 RIL format lt insn gt R1 12 4 4 4 4 OpCode R1 OpCdl 12 4 4 4 4 0 8 12 16 47 RILU format lt insn gt R1 U2 4 4 4 4 2 4 OpCode R1 OpCdl U2 4 4 4 4 2 0 8 12 16 47 RIS format lt insn gt R1 I2 M3 D4 B4 4 4 4 4 4 4 4 OpCode R1 M3 B4 D4 I2 Opcode 4 4 4 4 4 4 4 0 8 12 16 20 32 36 47 RR format lt insn gt R1 R2 4 4 4 4 OpCode R1 R2 4 4 4 4 0 8 12 15 RRE format lt insn gt R1 R2 4 4 4 4 4 OpCode 7 RA R2 4 4 4 4 4 0 16 24 28 31 RRF format lt insn gt R1 R2 R3 M4 4 4 4 4 4 4 OpCode R3 M4 R1 R2 4
311. eviated as D register or Dreg Data registers can be accessed as 32 bit registers or as two independent 16 bit registers The least significant 16 bits of each register is called the low half and is designated with L following the register name The most significant 16 bits are called the high half and is designated with H following the name R7 L r2 h r4 L RO H Pointer Registers The set of 32 bit registers P0 P1 P2 P3 P4 P5 SP and FP that normally contain byte addresses of data structures These are abbreviated as P register or Preg 116 Using as p2 p5 fp sp Stack Pointer SP The stack pointer contains the 32 bit address of the last occupied byte location in the stack The stack grows by decrementing the stack pointer Frame Pointer FP The frame pointer contains the 32 bit address of the previous frame pointer in the stack It is located at the top of a frame Loop Top LTO and LT1 These registers contain the 32 bit address of the top of a zero overhead loop Loop Count LCO and LC These registers contain the 32 bit counter of the zero overhead loop executions Loop Bottom LBO and LB1 These registers contain the 32 bit address of the bottom of a zero overhead loop Index Registers The set of 32 bit registers I0 I1 I2 I3 that normally contain byte addresses of data structures Abbreviated I register or Ireg Modify Registers The set of 32 bit registers M0 M1 M2 M3 that normally contain offse
312. f a 4 appears as the first character of a line the whole line is treated as a comment but in this case the line could also be a logical line number directive see Section 3 3 Comments page 27 or a preprocessor control command see Section 3 1 Preprocessing page 27 Sub instructions may be executed in order in reverse order or in parallel Instructions listed in the standard one per line format will be executed sequentially To specify the executing order use the following symbols iet Sequential with instruction on the left first lt Sequential with instruction on the right first p Parallel The D10V syntax allows either one instruction per line one instruction per line with the execution symbol or two instructions per line For example abs ai gt abs rO Execute these sequentially The instruction on the right is in the right container and is executed second abs rO lt abs al Execute these reverse sequentially The instruction on the right is in the right container and is executed first 1d2w r2 r8 mac a0 r0 r7 Execute these in parallel 1d2w r2 0r8 mac a0 r0 rT7 Two line format Execute these in parallel ld2w r2 r8 mac a0 r0 r7 Two line format Execute these sequentially Assembler will put them in the proper containers ld2w r2 r8 gt mac aO r0 r7 Two line format Execute these sequentially Same as above but second in struction will always go into right container Since
313. f a line starting a comment or affect using for starting a comment march CPU EXTENSION This option specifies the target processor The assembler will issue an error message if an attempt is made to assemble an instruction which will not ex ecute on the target processor The following processor names are recognized 18086 1186 1286 1386 1486 1586 1686 pentium pentiumpro pentiumii pentiumiii pentium4 prescott nocona core core2 corei7 liom klom k6 k6 2 athlon opteron k8 amdfami0 bdveri bdver2 bdver3 btver1 btver2 generic32 and generic64 In addition to the basic instruction set the assembler can be told to accept var ious extension mnemonics For example march i686 sse4 vmx extends i686 with sse4 and vmx The following extensions are currently supported 8087 287 387 no87 mmx nommx sse sse2 sse3 ssse3 sse4 1 sse4 2 sse4 nosse avx avx2 adx rdseed prfchw smap mpx sha avx512f avx512cd avx512er avx512pf noavx vmx vmfunc smx xsave xsaveopt aes pclmul fsgsbase rdrnd fi6c bmi2 fma movbe ept lzcnt hle rtm invpcid clflush lwp fma4 xop cx16 syscall rdtscp 3dnow 3dnowa sse4a sseb svme abm and padlock Note that rather than extending a basic instruction set the extension mnemonics starting with no revoke the respective functionality When the arch directive is used with march the arch directive will take precedent 146 Using as mtune
314. f a macro called reserve str with two argu ments The first argument has a default value but not the second After the definition is complete you can call the macro either as reserve str a b with p1 evaluating to a and p2 evaluating to b or as reserve str b with p1 evaluating as the default in this case 0 and p2 evaluating to b macro m pl req p2 0 p3 vararg Begin the definition of a macro called m with at least three ar guments The first argument must always have a value specified but not the second which instead has a default value The third formal will get assigned all remaining arguments specified at invo cation time When you call a macro you can specify the argument values either by position or by keyword For example sum 9 17 is equivalent to sum to 17 from 9 Note that since each of the macargs can be an identifier exactly as any other one permitted by the target architecture there may be occasional problems if the target hand crafts special meanings to certain characters when they occur in a special position For example if the colon is generally permitted to be part of a symbol name but the architecture specific code special cases it when occurring as the final character of a symbol to denote a label then the macro parameter replacement code will have no way of knowing that and consider the whole construct including the colon an identifier and che
315. f a symbol table entry 7 118 version string This directive creates a note section and places into it an ELF formatted note of type NT_VERSION The note s name is set to string 7 119 vtable_entry table offset This directive finds or creates a symbol table and creates a VTABLE_ENTRY relocation for it with an addend of offset 7 120 vtable_inherit child parent This directive finds the symbol child and finds or creates the symbol parent and then creates a VIABLE_INHERIT relocation for the parent whose addend is the value of the child symbol As a special case the parent name of 0 is treated as referring to the ABS section 7 121 warning string Similar to the directive error see Section 7 49 error string page 54 but just emits a warning 7 122 weak names This directive sets the weak attribute on the comma separated list of symbol names If the symbols do not already exist they will be created On COFF targets other than PE weak symbols are a GNU extension This directive sets the weak attribute on the comma separated list of symbol names If the symbols do not already exist they will be created On the PE target weak symbols are supported natively as weak aliases When a weak symbol is created that is not an alias GAS creates an alternate symbol to hold the default value 78 Using as 7 123 weakref alias target This directive creates an alias to the target symbol that enables the symbol to be re
316. f numeric names for registers that have canonical names 282 Using as 9 45 TILEPro Dependent Features 9 45 1 Options as has no machine dependent command line options for TILEPro 9 45 2 Syntax Block comments are delimited by and End of line comments may be introduced by 4 Instructions consist of a leading opcode or macro name followed by whitespace and an optional comma separated list of operands opcode operand Instructions must be separated by a newline or semicolon There are two ways to write code either write naked instructions which the assembler is free to combine into VLIW bundles or specify the VLIW bundles explicitly Bundles are specified using curly braces add r3 r4 r5 add r7 r8 r9 lw ri10 r1i1 A bundle can span multiple lines If you want to put multiple instructions on a line whether in a bundle or not you need to separate them with semicolons as in this example A bundle may contain one or more instructions up to the limit specified by the ISA currently three If fewer instructions are specified than the hardware supports in a bundle the assembler inserts fnop instructions automatically The assembler will prefer to preserve the ordering of instructions within the bundle putting the first instruction in a lower numbered pipeline than the next one etc This fact combined with the optional use of explicit fnop or nop instructions allows precise control over which pip
317. f the instruction extends a 32 bit operand to 64 bit g the operands are treated as 64 bit values h the operand uses a 16 bit halfword operand i the instruction uses an immediate operand the instruction uses unsigned logical operands m the instruction uses a mask or operates on multiple values r ifristhe last character the instruction operates on registers y the instruction uses 20 bit displacements There are many exceptions to the scheme outlined in the above lists in particular for the priviledged instructions For non priviledged instruction it works quite well for example the instruction clgfr c compare instruction l unsigned operands g 64 bit operands f 32 to 64 bit extension r register operands The instruction compares an 64 bit value in a register with the zero extended 32 bit value from a second register For a complete list of all mnemonics see appendix B in the Principles of Operation 9 37 3 3 Instruction Operands Instruction operands can be grouped into three classes operands located in registers im mediate operands and operands in storage 234 Using as A register operand can be located in general floating point access or control register The register is identified by a four bit field The field containing the register operand is called the R field Immediate operands are contained within the instruction and can have 8 16 or 32 bits The field containing the immediate operand is called the
318. fault 9 47 2 Syntax 9 47 2 1 Special Characters is the line comment character If a appears as the first character of a line then the whole line is treated as a comment but in this case the line could also be a logical line number directive see Section 3 3 Comments page 27 or a preprocessor control command see Section 3 1 Preprocessing page 27 You can use instead of a newline to separate statements 9 47 2 2 Register Names The Z8000 has sixteen 16 bit registers numbered 0 to 15 You can refer to different sized groups of registers by register number with the prefix r for 16 bit registers rr for 32 bit registers and rq for 64 bit registers You can also refer to the contents of the first eight of the sixteen 16 bit registers by bytes They are named rln and rhn byte registers r10 rhO rli rhi r12 rh2 r13 rh3 rl4 rh4 r15 rh5 r16 rh6 r17 rh7 word registers rO ri r2 r3 r4 rb r6 r7 r8 r9 r10 ril ri2 r13 ri4 r15 long word registers rrO rr2 rr4 rr6 rr8 rr 10 rri2 rr14 quad word registers rq0 rq4 rq8 rqi2 9 47 2 3 Addressing Modes as understands the following addressing modes for the Z8000 290 Using as rin rhn rn rrn rqn Register direct 8bit 16bit 32bit and 64bit registers rn rrn Indirect register rrn in segmented mode Grn in unsegmented mode addr Direct the 16 bit or 24 bit address depending on whether the assembler is in segment
319. fect of the GOT and the PLT suffix the difference to GOT is that there will be a procedure linkage table entry created and that the symbol is assumed to be a function entry and will be resolved by the run time resolver as with PLT The relocation is R_CRIS_32_GOTPLT Example jsr r0 fnname GOTPLT GOTPLT16 A variant of GOTPLT giving a 16 bit value Its relocation name is R_CRIS_16_GOTPLT Example jsr r0 fnname GOTPLT16 GOTOFF This suffix must only be attached to a local symbol but may be used in an expression adding an offset The value is the address of the symbol relative to the start of the global offset table The relocation name is R_CRIS_32_GOTREL Example move d r0 localsym GOTOFF r3 9 8 4 3 Register names A character may always prefix a general or special register name in an instruction operand but is mandatory when the option no underscore is specified or when the Syntax register prefix directive is in effect see crisnous page 123 Register names are case insensitive 9 8 4 4 Assembler Directives There are a few CRIS specific pseudo directives in addition to the generic ones See Chapter 7 Pseudo Ops page 47 Constants emitted by pseudo directives are in little endian order for CRIS There is no support for floating point specific directives for CRIS dword EXPRESSIONS The dword directive is a synonym for int expecting zero or more EXPRE
320. ferenced with weak symbol semantics but without actually making it weak If direct references or definitions of the symbol are present then the symbol will not be weak but if all references to it are through weak references the symbol will be marked as weak in the symbol table The effect is equivalent to moving all references to the alias to a separate assembly source file renaming the alias to the symbol in it declaring the symbol as weak there and running a reloadable link to merge the object files resulting from the assembly of the new source file and the old source file that had the references to the alias removed The alias itself never makes to the symbol table and is entirely handled within the assembler 7 124 word expressions This directive expects zero or more expressions of any section separated by commas The size of the number emitted and its byte order depend on what target computer the assembly is for Warning Special Treatment to support Compilers Machines with a 32 bit address space but that do less than 32 bit addressing require the following special treatment If the machine of interest to you does 32 bit addressing or doesn t require it see Chapter 9 Machine Dependencies page 81 you can ignore this issue In order to assemble compiler output into something that works as occasionally does strange things to word directives Directives of the form word symi sym2 are often emitted by c
321. ffix to their numeric value e g 55 They can also be distinguished from ordinary local labels by their transformed names which use ASCII character 001 control A as the magic character to distinguish them from ordinary labels For example the fifth definition of G may be named L6C 45 5 4 The Special Dot Symbol The special symbol refers to the current address that as is assembling into Thus the expression melvin long defines melvin to contain its own address Assigning a value to is treated the same as a org directive Thus the expression 4 is the same as saying space 4 5 5 Symbol Attributes Every symbol has as well as its name the attributes Value and Type Depending on output format symbols can also have auxiliary attributes If you use a symbol without defining it as assumes zero for all these attributes and probably won t warn you This makes the symbol an externally defined symbol which is generally what you would want 5 5 1 Value The value of a symbol is usually 32 bits For a symbol which labels a location in the text data bss or absolute sections the value is the number of addresses from the start of that section to the label Naturally for text data and bss sections the value of a symbol changes as 1d changes section base addresses during linking Absolute symbols values do not change during linking that is why they are called absolute
322. ffset Indicate which of the floating point registers are saved in the current stack frame The mask and offset parameters are interpreted as with mask frame framereg frameoffset retreg argoffset Describes the shape of the stack frame The frame pointer in use is framereg normally this is either fp or sp The frame pointer is frameoftset bytes below the CFA The return address is initially located in retreg until it is saved as indicated in mask For compatibility with OSF 1 an optional argoffset parameter is accepted and ignored It is believed to indicate the offset from the CFA to the saved argument registers prologue n Indicate that the stack frame is set up and all registers have been spilled The argument n indicates whether and how the function uses the incoming procedure vector the address of the called function in 27 0 indicates that 27 is not used 1 indicates that the first two instructions of the function use 27 to perform a load of the GP register 2 indicates that 27 is used in some non standard way and so the linker cannot elide the load of the procedure vector during relaxation usepv function which Used to indicate the use of the 27 register similar to prologue but without the other semantics of needing to be inside an open ent end block Chapter 9 Machine Dependent Features 89 The which argument should be either no indicating that 27 is not used or std indicating that the first two instruct
323. files see no trace of them They just see all your text subsections as a text section and all your data subsections as a data section To specify which subsection you want subsequent statements assembled into use a nu meric argument to specify it in a text expression or a data expression statement When generating COFF output you can also use an extra subsection argument with arbi trary named sections section name expression When generating ELF output you can also use the subsection directive see Section 7 110 SubSection page 74 to specify a subsection subsection expression Expression should be an absolute expression see Chapter 6 Expressions page 43 If you just say text then text 0 is assumed Likewise data means data 0 Assembly begins in text 0 For instance text 0 The default subsection is text 0 anyway ascii This lives in the first text subsection text 1 ascii But this lives in the second text subsection data 0 ascii This lives in the data section ascii in the first data subsection text O ascii This lives in the first text section ascii immediately following the asterisk Each section has a location counter incremented by one for every byte assembled into that section Because subsections are merely a convenience restricted to as there is no concept of a subsection location counter T here is no way to directly manipulate a
324. fined symbols ro through r63 to refer to the SH64 general registers crO through cr63 for control registers trO through tr7 for target address registers fro through fr63 for single precision floating point registers dro through dr62 even numbered registers only for double precision floating point registers fv0 through fv60 multiples of four only for single precision floating point vectors fp0 through fp62 even numbered registers only for single precision floating point pairs mtrx0 through mtrx48 multiples of 16 only for 4x4 matrices of single precision floating point registers pc for the program counter and fpscr for the floating point status and control register You can also refer to the control registers by the mnemonics sr ssr pssr intevt expevt pexpevt tra spc pspc resvec vbr tea dcr kero keri cto and usr 9 40 2 3 Addressing Modes SH64 operands consist of either a register or immediate value The immediate value can be a constant or label reference or portion of a label reference as in this example movi 4 r2 pt function tr4 movi function gt gt 16 amp 65535 r0 shori function amp 65535 rO ld 1 r0 4 r0 Instruction label references can reference labels in either SHmedia or SHcompact To differ
325. fixdd Let the assembler to insert bubbles 32 bit nop instruction 16 bit nop In struction if the source machine language instructions happen data dependency Set nofixdd Let the assembler to generate warnings if the source machine language instruc tions happen data dependency Default set rl Let the assembler not to generate warnings if the source program uses rl allow user to use rl Chapter 9 Machine Dependent Features 247 set nori Let the assembler to generate warnings if the source program uses rl Default sdata Tell the assembler to add subsequent data into the sdata section rdata Tell the assembler to add subsequent data into the rdata section frame frame register offset return pc register Describe a stack frame frame register is the frame register offset is the dis tance from the frame register to the virtual frame pointer return pc register is the return program register You must use ent before frame and only one frame can be used per ent mask bitmask frameoffset Indicate which of the integer registers are saved in the current function s stack frame this is for the debugger to explain the frame chain ent proc name Set the beginning of the procedure proc name Use this directive when you want to generate information for the debugger end proc name Set the end of a procedure Use this directive to generate information for the debugger bss Switch the destination of
326. flag Traditional MIPS assemblers do not support these directives 9 27 10 Directives to save and restore options The directives set push and set pop may be used to save and restore the current settings for all the options which are controlled by set The set push directive saves the current settings on a stack The set pop directive pops the stack and restores the settings These directives can be useful inside an macro which must change an option such as the ISA level or instruction reordering but does not want to change the state of the code which invoked the macro Traditional MIPS assemblers do not support these directives 202 Using as 9 27 11 Directives to control generation of MIPS ASE instructions The directive set mips3d makes the assembler accept instructions from the MIPS 3D Application Specific Extension from that point on in the assembly The set nomips3d directive prevents MIPS 3D instructions from being accepted The directive set smartmips makes the assembler accept instructions from the Smart MIPS Application Specific Extension to the MIPS32 ISA from that point on in the assembly The set nosmartmips directive prevents SmartMIPS instructions from being accepted The directive set mdmx makes the assembler accept instructions from the MDMX Ap plication Specific Extension from that point on in the assembly The set nomdmx directive prevents MDMX instructions from being accepted The directive set dsp ma
327. floating point constants the long and quad directives must be used 246 Using as 9 38 SCORE Dependent Features 9 38 1 Options The following table lists all available SCORE options G num This option sets the largest size of an object that can be referenced implicitly with the gp register The default value is 8 EB Assemble code for a big endian cpu EL Assemble code for a little endian cpu FIXDD Assemble code for fix data dependency NWARN Assemble code for no warning message for fix data dependency SCORE5 Assemble code for target is SCORES SCORE5U Assemble code for target is SCORES5U SCORE7 Assemble code for target is SCORET this is default setting SCORE3 Assemble code for target is SCORE3 march score7 Assemble code for target is SCORE7 this is default setting march score3 Assemble code for target is SCORE3 USE R1 Assemble code for no warning message when using temp register r1 KPIC Generate code for PIC This option tells the assembler to generate score position independent macro expansions It also tells the assembler to mark the output file as PIC 00 Assembler will not perform any optimizations V Sunplus release version 9 38 2 SCORE Assembler Directives A number of assembler directives are available for SCORE The following table is far from complete Set nwarn Let the assembler not to generate warnings if the source machine language instructions happen data dependency Set
328. fnc directives ccs sme 4e rb ERE EAR E 58 ifndef directe 58 ifne rechte eise E rinie trenari Eka 58 ifnes directive lll ele EEN Rees 58 ifnotdef directive isco ASSEN E A See 58 immediate character AArch64 82 immediate character ARM 98 immediate character M680x0 183 immediate character VAX 294 immediate fields relaxation suus 310 immediate operands i386 045 147 immediate operands x86 64 0 147 imul instruction 1290 155 imul instruction zHD D4 155 in bin O eeng BEEN euge E pes EP 58 include e ui ue eek ane p eke RUE te 58 include directive search path 22 indirect character VAX sssssuusss 294 infix operators s dew kgs xs tes E RERO 44 inhibiting interrupts i386 00 150 WMPUbs nier EEN 17 input file Dnenumbers ss cc ccrcrerisesirecsre 18 instruction aliases 200 238 instruction bundle osse eoa eee eas 49 instruction expansion CRIS 121 instruction expansion MMIX 205 instruction formats s 00 235 instruction marker 200 243 instruction mnemonics SO 232 instruction naming 1386 08 148 instruction naming Z8p DI 148 instruction operand modifier s390 241 instruction operands s200 233 instruction prefixes 2890 150 instruction set Most 182 instruction set MosHCHT 188 instruction se
329. following options are available when as is configured for the c54x architecture mfar mode Enable extended addressing mode All addresses and relocations will assume extended addressing usually 23 bits mcpu CPU VERSION Sets the CPU version being compiled for merrors to file FILENAME Redirect error output to a file for broken systems which don t support such behaviour in the shell The following options are available when as is configured for a MIPS processor G num This option sets the largest size of an object that can be referenced implicitly with the gp register It is only accepted for targets that use ECOFF format such as a DECstation running Ultrix The default value is 8 EB Generate big endian format output EL Generate little endian format output mipsi mips2 mips3 mips4 mipsb5 mips32 mips32r2 mips64 mips64r2 Generate code for a particular MIPS Instruction Set Architecture level mipsi is an alias for march r3000 mips2 is an alias for march r6000 mips3 is an alias for march r4000 and mips4 is an alias for march r8000 mips5 mips32 mips32r2 mips64 and mips64r2 correspond to generic MIPS V MIPS32 MIPS32 Release 2 MIPS64 and MIPS64 Release 2 ISA processors respectively march cpu Generate code for a particular MIPS CPU mtune cpu Schedule and tune for a particular MIPS CPU mfix7000
330. from or both arguments must be absolute and the result is absolute 1 Highest Precedence lt lt gt gt Multiplication Division Truncation is the same as the C operator Remainder Shift Left Same as the C operator lt lt Shift Right Same as the C operator gt gt 2 Intermediate precedence Bitwise Inclusive Or Bitwise And Bitwise Exclusive Or Bitwise Or Not 3 Low Precedence Addition If either argument is absolute the result has the section of the other argument You may not add together arguments from different sections Subtraction If the right argument is absolute the result has the section of the left argument If both arguments are in the same section the result is absolute You may not subtract arguments from different sections Is Equal To Is Not Equal To Is Less Than Is Greater Than Is Greater Than Or Equal To Is Less Than Or Equal To The comparison operators can be used as infix operators A true results has a value of 1 whereas a false result has a value of 0 Note these operators perform signed comparisons 4 Lowest Precedence amp amp Logical And Chapter 6 Expressions 45 Logical Or These two logical operations can be used to combine the results of sub expressions Note unlike the comparison operators a true result returns a value of 1 but a false results does still return 0 Also note that the logical or operato
331. fset but offset is a relative value that is added substracted from the previous offset 7 20 cfi offset register offset Previous value of register is saved at offset offset from CFA 7 21 cfi rel offset register offset Previous value of register is saved at offset offset from the current CFA register This is transformed to cfi offset using the known displacement of the CFA register from the CFA This is often easier to use because the number will match the code it s annotating 7 22 cfi register registeri register2 Previous value of registerl is saved in register register2 7 23 cfi restore register cfi restore says that the rule for register is now the same as it was at the beginning of the function after all initial instruction added by cfi startproc were executed 7 24 cfi undefined register From now on the previous value of register can t be restored anymore 7 25 cfi same value register Current value of register is the same like in the previous frame i e no restoration needed 7 26 cfi remember state First save all current rules for all registers by cfi remember state then totally screw them up by subsequent cfi directives and when everything is hopelessly bad use cfi_ restore state to restore the previous saved state 7 27 cfi return column register Change return column register i e the return address is either directly in register or can be accessed by rules for register 52 Using
332. fv4 mcfv4e Assemble for the ColdFire family of chips n68881 m68882 Assemble 68881 floating point instructions This is the default for the 68020 68030 and the CPU32 The 68040 and 68060 always support floating point instructions Chapter 9 Machine Dependent Features 179 mno 6888 1 Do not assemble 68881 floating point instructions This is the de fault for 68000 and the 68010 The 68040 and 68060 always support floating point instructions even if this option is used m68851 Assemble 68851 MMU instructions This is the default for the 68020 68030 and 68060 The 68040 accepts a somewhat different set of MMU instructions m68851 and m68040 should not be used together mno 68851 Do not assemble 68851 MMU instructions This is the default for the 68000 68010 and the CPU32 The 68040 accepts a somewhat different set of MMU instructions 9 23 2 Syntax This syntax for the Motorola 680x0 was developed at MIT The 680x0 version of as uses instructions names and syntax compatible with the Sun assembler Intervening periods are ignored for example movl is equivalent to mov 1 In the following table apc stands for any of the address registers 4a0 through 4a7 the program counter Apc the zero address relative to the program counter Azpe a suppressed address register 4za0 through za7 or it may be omitted entirely The use
333. g O0 mevexwig 1 These options control how the assembler should encode w ignored WIG EVEX instructions mevexwig 0 will encode WIG EVEX instructions with evex w 0 which is the default mevexwig 1 will encode WIG EVEX instructions with evex w 1 mmnemonic att mmnemonic intel This option specifies instruction mnemonic for matching instructions The att mnemonic and intel mnemonic directives will take precedent nsyntax att msyntax intel This option specifies instruction syntax when processing instructions The att syntax and intel syntax directives will take precedent Chapter 9 Machine Dependent Features 147 mnaked reg This opetion specifies that registers don t require a prefix The att syntax and intel syntax directives will take precedent madd bnd prefix This option forces the assembler to add BND prefix to all branches even if such prefix was not explicitly specified in the source code 9 15 2 x86 specific Directives lcomm symbol length alignment Reserve length an absolute expression bytes for a local common denoted by symbol The section and value of symbol are those of the new local common The addresses are allocated in the bss section so that at run time the bytes start off zeroed Since symbol is not declared global it is normally not visible to 1d The optional third parameter alignment specifies the desired alignment of the symbol in the bss section This dire
334. g as atan2 expri expr2 Returns the floating point arctangent of expr1 expr2 ceil expr Returns the smallest integer not less than expr as floating point cosh expr Returns the floating point hyperbolic cosine of expr cos expr Returns the floating point cosine of expr cvf expr Returns the integer value expr converted to floating point cvi expr Returns the floating point value expr converted to integer exp expr Returns the floating point value e expr fabs expr Returns the floating point absolute value of expr f1oor expr Returns the largest integer that is not greater than expr as floating point fmod expri expr2 Returns the floating point remainder of expr1 expr2 int expr Returns 1 if expr evaluates to an integer zero otherwise ldexp expri expr2 Returns the floating point value expr1 2 expr2 1ogi0 expr Returns the base 10 logarithm of expr log expr Returns the natural logarithm of expr max expri expr2 Returns the floating point maximum of expr and expr2 min expri expr2 Returns the floating point minimum of expr1 and expr2 pow expri expr2 Returns the floating point value expri expr2 round expr Returns the nearest integer to expr as a floating point number sgn expr Returns 1 0 or 1 based on the sign of expr Chapter 9 Machine Dependent Features 267 sin expr Returns the floating point sine of expr sinh expr Retu
335. g those of Invariant Sections in the notice that says that the Document is released 322 2 Using as under this License If a section does not fit the above definition of Secondary then it is not allowed to be designated as Invariant The Document may contain zero Invariant Sections If the Document does not identify any Invariant Sections then there are none The Cover Texts are certain short passages of text that are listed as Front Cover Texts or Back Cover Texts in the notice that says that the Document is released under this License A Front Cover Text may be at most 5 words and a Back Cover Text may be at most 25 words A Transparent copy of the Document means a machine readable copy represented in a format whose specification is available to the general public that is suitable for revising the document straightforwardly with generic text editors or for images com posed of pixels generic paint programs or for drawings some widely available drawing editor and that is suitable for input to text formatters or for automatic translation to a variety of formats suitable for input to text formatters A copy made in an otherwise Transparent file format whose markup or absence of markup has been arranged to thwart or discourage subsequent modification by readers is not Transparent An image format is not Transparent if used for any substantial amount of text A copy that is not Transparent is called Opaque
336. gister Name 85 9 2 3 9 Rel catiols cre up cada ERENEPERER T ERG 85 9 2 4 Ploatine Pont cen iet HIE S deans RE adea 87 9 2 5 Alpha Assembler Directives 0020 cece eee eee 87 9 2 0 peche 3 eet ceret es tae pea ra ER ede os 90 9 3 ARC Dependent Features 91 9 3 1 Options R X eRkeRRRRU UH REEPOOIPELI adbeacax agen 91 Un Mun CP REESEN Age ec 91 9 3 2 1 Special Oharacterg ccc cece c eee eee 91 vi 9 3 2 2 Register Name 91 9 3 3 Floating Point eesi orersecrise Tv b rrr e EEN 91 9 3 4 ARC Machine Directive 91 9 3 5 Opcodes scie cbe e gx ce I ADR RR RITE Eee 94 9 4 ARM Dependent Features 95 921 1 OptolSiezoresetpere ee ERIT PRR Ce EE Rec ERREUR deuda 95 9 2 ENEE ela mu EE A EP 98 9 4 2 1 Instruction Set Syntax sse 98 9 4 2 2 Special Ch araeters szikezdexss bee m te ERR ER dg iai 98 9 4 2 3 Register Name 98 9 4 2 4 ARM relocation generation 000 ee eee 98 9 4 2 5 NEON Alignment Specifiers 0 00005 99 0 4 3 Floating Point ccc basen deena peace Dp oe RR ERR 99 9 4 4 ARM Machine Directives usuusuus urnen nennen 99 9 4 5 peard LEE waa 104 9 4 6 Mapping GBvmbols 0 0 cece e L E 105 OA EE el 105 9 5 AVR Dependent Features 00 0 c ccc eee eee eas 108 9 5 1 OPtHONS c eshe ob eee SEENEN EN 108 O52 Oy ibakace ds Dee Ge 109 9 5 2 1 Special Characters 0 00 cece eee eee ees 109 9 5 2 2 Register Name 110 9 5 2 3 Relocatable Expression Modifier
337. gnificant word first drlist drnolist Control printing of directives to the listing file Ignored emsg string mmsg string wnsg string Emit a user defined error message or warning respectively far mode Use extended addressing when assembling statements l his should appear only once per file and is equivalent to the mfar mode option see Section 9 42 1 mf ar mode page 264 fclist fcnolist Control printing of false conditional blocks to the listing file field value size Initialize a bitfield of size bits in the current section If value is relocatable then size must be 16 size defaults to 16 bits If value does not fit into size Chapter 9 Machine Dependent Features 269 bits the value will be truncated Successive field directives will pack starting at the current word filling the most significant bits first and aligning to the start of the next word if the field size does not fit into the space remaining in the current word A align directive with an operand of 1 will force the next field directive to begin packing into a new word If a label is used it points to the word that contains the specified field global symbol symbol n def symbol symbol n ref symbol symbol n def nominally identifies a symbol defined in the current file and available to other files ref identifies a symbol used in the current file but defined elsewhere Both map to the standard global directive
338. h time the resulting symbol is used in an expression a snapshot of its current value is taken 7 48 err If as assembles a err directive it will print an error message and unless the Z option was used it will not generate an object file This can be used to signal an error in conditionally compiled code 7 49 error string Similarly to err this directive emits an error but you can specify a string that will be emit ted as the error message If you don t specify the message it defaults to error directive invoked in source file See Section 1 7 Error and Warning Messages page 18 Chapter 7 Assembler Directives 55 error This code has not been assembled and tested 7 50 exitm Exit early from the current macro definition See Section 7 79 Macro page 62 7 51 extern extern is accepted in the source program for compatibility with other assemblers but it is ignored as treats all undefined symbols as external 7 52 fail expression Generates an error or a warning If the value of the expression is 500 or more as will print a warning message If the value is less than 500 as will print an error message l he message will include the value of expression This can occasionally be useful inside complex nested macros or conditional assembly 7 53 file There are two different versions of the file directive Targets that support DWARF2 line number information use the DWARF 2 version of file O
339. hat generate assembly output For example this definition specifies a macro sum that puts a sequence of numbers into memory macro sum from 0 to 5 Long from if to from sum Nfromti Nto endif endm With that definition SUM 0 5 is equivalent to this assembly input long long long long long long oP GO H tz CH macro macname macro macname macargs Begin the definition of a macro called macname If your macro definition requires arguments specify their names after the macro name separated by commas or spaces You can qualify the macro argument to indicate whether all invocations must specify a non blank value through req or whether it takes all of the remaining arguments through vararg You can supply a default value for any macro argument by following the name with deflt Chapter 7 Assembler Directives 63 You cannot define two macros with the same macname unless it has been sub ject to the purgem directive see Section 7 92 Purgem page 68 between the two definitions For example these are all valid macro statements macro comm Begin the definition of a macro called comm which takes no argu ments macro plus1 p pl macro plusi p pl Either statement begins the definition of a macro called plus which takes two arguments within the macro definition write p or p1 to evaluate the arguments macro reserve str p1 0 p2 Begin the definition o
340. he 32 bit double ABI mlong double Specify to use the 64 bit double ABI force long branches Relative branches are turned into absolute ones This concerns conditional branches unconditional branches and branches to a sub routine S short branches Do not turn relative branches into absolute ones when the offset is out of range strict direct mode Do not turn the direct addressing mode into extended addressing mode when the instruction does not support direct addressing mode print insn syntax Print the syntax of instruction in case of error print opcodes Print the list of instructions with syntax and then exit generate example Print an example of instruction for each possible instruction and then exit This option is only useful for testing as The following options are available when as is configured for the SPARC architecture Av6 Av7 Av8 Asparclet Asparclite Av8plus Av8plusa Av9 Av9a Explicitly select a variant of the SPARC architecture Av8plus and Av8plusa select a 32 bit environment Av9 and Av9a select a 64 bit environment Av8plusa and Av9a enable the SPARC V9 instruction set with Ultra SPARC extensions 12 Using as xarch v8plus xarch v8plusa For compatibility with the Solaris v9 assembler These options are equivalent to Av8plus and Av8plusa respectively bump Warn when the assembler switches to another architecture The
341. he fill pattern as a four byte longword value For example p2alignw 2 0x368d will align to a multiple of 4 If it skips two bytes they will be filled in with the value 0x368d the exact placement of the bytes depends upon the endianness of the processor If it skips 1 or 3 bytes the fill value is undefined 7 87 popsection This is one of the ELF section stack manipulation directives The others are section see Section 7 99 Section page 69 subsection see Section 7 110 SubSection page 74 pushsection see Section 7 93 PushSection page 68 and previous see Section 7 88 Previous page 66 This directive replaces the current section and subsection with the top section and subsection on the section stack This section is popped off the stack 7 88 previous This is one of the ELF section stack manipulation directives The others are section see Section 7 99 Section page 69 subsection see Section 7 110 SubSection page 74 pushsection see Section 7 93 PushSection page 68 and popsection see Section 7 87 PopSection page 66 This directive swaps the current section and subsection with most recently referenced section subsection pair prior to this one Multiple previous directives in a row will flip between two sections and their subsections For example Section A Subsection 1 Wword 0x1234 Subsection 2 word 0x5678 previous Chapter 7 Assembler Directives 67 word Ox9abc
342. he first three section types Note on targets where the character is the start of a comment eg ARM then another character is used instead For example the ARM port uses the character If flags contains the M symbol then the type argument must be specified as well as an extra argument entsize like this Section name flags M type entsize Sections with the M flag but not S flag must contain fixed size constants each entsize octets long Sections with both M and S must contain zero terminated strings where each character is entsize bytes long The linker may remove duplicates within sections with the Chapter 7 Assembler Directives 71 same name same entity size and same flags entsize must be an absolute expression For sections with both M and S a string which is a suffix of a larger string is considered a duplicate Thus def will be merged with abcdef A reference to the first def will be changed to a reference to abcdef 3 If flags contains the G symbol then the type argument must be present along with an additional field like this Section name flags G type GroupName linkage The GroupName field specifies the name of the section group to which this particular section belongs The optional linkage field can contain comdat indicates that only one copy of this section should be retained gnu linkonce an alias for comdat Note if both the M and G flags are present then the fields for the Merge flag shou
343. he full range of HLASM semantics 9 14 6 Opcodes For detailed information on the ESA 390 machine instruction set see ESA 390 Principles of Operation IBM Publication Number DZ9ARO004 Chapter 9 Machine Dependent Features 145 9 15 80386 Dependent Features The i386 version as supports both the original Intel 386 architecture in both 16 and 32 bit mode as well as AMD x86 64 architecture extending the Intel architecture to 64 bits 9 15 1 Options The i386 version of as has a few machine dependent options 32 x32 64 n divide Select the word size either 32 bits or 64 bits 32 implies Intel i386 archi tecture while x32 and 64 imply AMD x86 64 architecture with 32 bit or 64 bit word size respectively These options are only available with the ELF object file format and require that the necessary BFD support has been included on a 32 bit platform you have to add enable 64 bit bfd to configure enable 64 bit usage and use x86 64 as target platform By default x86 GAS replaces multiple nop instructions used for alignment within code sections with multi byte nop instructions such as leal 0 esi 1 esi This switch disables the optimization On SVR4 derived platforms the character is treated as a comment character which means that it cannot be used in expressions The divide option turns 7 into a normal character This does not disable at the beginning o
344. he most recent previous definition of that label write Nb using the same number as when you defined the label To refer to the next definition of a local label write NEI he b stands for backwards and the f stands for forwards There is no restriction on how you can use these labels and you can reuse them too So that it is possible to repeatedly define the same local label using the same number N although you can only refer to the most recently defined local label of that number for a backwards reference or the next definition of a specific local label for a forward reference It is also worth noting that the first 10 local labels 0 9 are implemented in a slightly more efficient manner than the others Here is an example 1 branch 1f 2 branch 1b 1 branch 2f 25 branch 1b Which is the equivalent of label 1 branch label 3 label_2 branch label 1 label_3 branch label 4 label_4 branch label 3 Local label names are only a notational device They are immediately transformed into more conventional symbol names before the assembler uses them The symbol names are stored in the symbol table appear in error messages and are optionally emitted to the object file The names are constructed using these parts local label prefix All local symbols begin with the system specific local label prefix Normally both as and 1d forget symbols that start with the local label prefix These labe
345. he symbol that will be entered into the GOT or PLT label is a local label and constant is an arbitrary expression that the assembler can evaluate to a constant value 242 Using as The term symbol constant1 modifier label constant2 is also accepted but a warning message is printed and the term is converted to symbol modifier label constanti constant2 Ogot got12 The got modifier can be used for displacement fields 16 bit immediate fields and 32 bit pc relative immediate fields The got12 modifier is synonym to got The symbol is added to the GOT For displacement fields and 16 bit immediate fields the symbol term is replaced with the offset from the start of the GOT to the GOT slot for the symbol For a 32 bit pc relative field the pc relative offset to the GOT slot from the current instruction address is used gotent The gotent modifier can be used for 32 bit pc relative immediate fields The symbol is added to the GOT and the symbol term is replaced with the pc relative offset from the current instruction to the GOT slot for the symbol gotoff The gotoff modifier can be used for 16 bit immediate fields The symbol term is replaced with the offset from the start of the GOT to the address of the symbol gotplt The gotplt modifier can be used for displacement fields 16 bit immediate fields and 32 bit pc relative immediate fields A procedure linkage table entry is generated for the sy
346. hem If a label is used with space it points to the first word reserved With bes the label points to the last word reserved sslist Ssnolist Controls the inclusion of subsym replacement in the listing output Ignored string string string n pstring string string n Place 8 bit characters from string into the current section string zero fills the upper 8 bits of each word while pstring puts two characters into each Chapter 9 Machine Dependent Features 271 word filling the most significant bits first Unused space is zero filled If a label is used it points to the first word initialized stag struct offset name 1 element count 1 name 2 element count 2 tname tag stagx tcount name n element count n ssize endstruct label tag stag tab Assign symbolic offsets to the elements of a structure stag defines a symbol to use to reference the structure offset indicates a starting value to use for the first element encountered otherwise it defaults to zero Each element can have a named offset name which is a symbol assigned the value of the elements offset into the structure If stag is missing these become global symbols count adjusts the offset that many times as if element were an array element may be one of byte word long float or any equivalent of those and the structure offset is adjusted accordingly field and string are also allowed the size of fie
347. ich target smartcard and cryptographic applications This is equivalent to putting set smartmips at the start of the assembly file mno smartmips turns off this option mips3d no mips3d Generate code for the MIPS 3D Application Specific Extension This tells the assembler to accept MIPS 3D instructions no mips3d turns off this option mdmx no mdmx Generate code for the MDMX Application Specific Extension This tells the assembler to accept MDMX instructions no mdmx turns off this option mdsp mno dsp Generate code for the DSP Release 1 Application Specific Extension This tells the assembler to accept DSP Release 1 instructions mno dsp turns off this option 194 Using as mdspr2 mno dspr2 Generate code for the DSP Release 2 Application Specific Extension This option implies mdsp This tells the assembler to accept DSP Release 2 in structions mno dspr2 turns off this option mmt mno mt Generate code for the MT Application Specific Extension This tells the as sembler to accept MT instructions mno mt turns off this option mmcu mno mcu Generate code for the MCU Application Specific Extension This tells the assembler to accept MCU instructions mno mcu turns off this option mvirt mno virt Generate code for the Virtualization Application Specific Extension This tells the assembler to accept Virtualization instructions mno virt turns off this option
348. ify a section override which coincides with the default section register as does not output any section register override prefixes to assemble the given instruction Thus section overrides can be specified to emphasize which section register is used for a given memory operand Here are some examples of Intel and AT amp T style memory references AT amp T 4 ebp Intel Lebp 4 base is Zebp disp is 4 section is missing and the default section is used les for addressing with 4ebp as the base register index scale are both missing AT amp T foot Zeax 4 Intel foo eax 4 index is eax scaled by a scale 4 disp is foo All other fields are missing The section register here defaults to Ads AT amp T f00 1 Intel foo This uses the value pointed to by foo as a memory operand Note that base ON and index are both missing but there is only one This is a syntactic exception AT amp T Ags foo Intel gs foo This selects the contents of the variable foo with section register section being Yes Absolute as opposed to PC relative call and jump operands must be prefixed with If no is specified as always chooses PC relative addressing for jump call labels Any instruction that has a memory operand but no register operand must specify its size byte word long or quadruple with an instruction mnemonic suffix
349. ify that the output generated by the assembler should be marked as supporting the indicated version of the Arm Procedure Calling Standard matpcs This option specifies that the output generated by the assembler should be marked as supporting the Arm Thumb Procedure Calling Standard If enabled this option will cause the assembler to create an empty debugging section in the object file called arm atpcs Debuggers can use this to determine the ABI being used by mapcs float This indicates the floating point variant of the APCS should be used In this variant floating point arguments are passed in FP registers rather than integer registers mapcs reentrant This indicates that the reentrant variant of the APCS should be used This variant supports position independent code mfloat abi abi This option specifies that the output generated by the assembler should be marked as using specified floating point ABI The following values are recog nized soft softfp and hard meabi ver This option specifies which EABI version the produced object files should con form to The following values are recognized gnu 4 and 5 EB This option specifies that the output generated by the assembler should be marked as being encoded for a big endian processor EL This option specifies that the output generated by the assembler should be marked as being encoded for a little endian processor k This option specifies that the output of the asse
350. igh expression The high directive computes the value of its expression and places the upper 16 bits of the result into the immediate field of the instruction For example seth r0 high 0x12345678 compute rO 0x12340000 seth rO high fred compute r0 upper 16 bits of address of fred shigh expression The shigh directive is very similar to the high directive It also computes the value of its expression and places the upper 16 bits of the result into the immediate field of the instruction The difference is that shigh also checks to see if the lower 16 bits could be interpreted as a signed number and if so it assumes that a borrow will occur from the upper 16 bits To compensate for this the shigh directive pre biases the upper 16 bit value by adding one to it For example For example 174 m32r m32rx m32r2 little big Using as 0x12340000 0x00010000 seth r0 shigh 0x12345678 compute rO seth r0 shigh 0x00008000 compute rO In the second example the lower 16 bits are 0x8000 If these are treated as a signed value and sign extended to 32 bits then the value becomes Oxffff8000 If this value is then added to 0x00010000 then the result is 0x00008000 This behaviour is to allow for the different semantics of the or3 and add3 instructions The or3 instruction treats its 16 bit immediate argument as un signed whereas the add3 treats its 16 bit immediate as a signed value So for example seth r0 shigh 0x
351. in ELF flags mpwrx mpwr2 Generate code for POWER 2 RIOS2 mpwr Generate code for POWER RIOS1 m601 Generate code for PowerPC 601 mppc mppc32 m603 m604 Generate code for PowerPC 603 604 m403 m405 Generate code for PowerPC 403 405 m440 Generate code for PowerPC 440 BookE and some 405 instructions m464 Generate code for PowerPC 464 m476 Generate code for PowerPC 476 m7400 m7410 m7450 m7455 Generate code for PowerPC 7400 7410 7450 7455 m750cl Generate code for PowerPC 750CL mppc64 m620 Generate code for PowerPC 620 625 630 me500 me500x2 Generate code for Motorola e500 core complex me500mc Generate code for Freescale e500mc core complex me500mc64 Generate code for Freescale e500mc64 core complex me5500 Generate code for Freescale e5500 core complex me6500 Generate code for Freescale e6500 core complex mspe Generate code for Motorola SPE instructions mtitan Generate code for AppliedMicro Titan core complex Chapter 9 Machine Dependent Features 225 mppc64bridge Generate code for PowerPC 64 including bridge insns mbooke Generate code for 32 bit BookE ma2 Generate code for A2 architecture me300 Generate code for PowerPC e300 family maltivec Generate code for processors with AltiVec instructions mvle Generate code for Freescale PowerPC VLE instructions mvsx Generate code for processors with Vector Scalar VSX instructions mhtm Generate cod
352. inal version of this License or a notice or disclaimer the original version will prevail If a section in the Document is Entitled Acknowledgements Dedications or His tory the requirement section 4 to Preserve its Title section 1 will typically require changing the actual title TERMINATION You may not copy modify sublicense or distribute the Document except as expressly provided under this License Any attempt otherwise to copy modify sublicense or distribute it is void and will automatically terminate your rights under this License However if you cease all violation of this License then your license from a particular copyright holder is reinstated a provisionally unless and until the copyright holder explicitly and finally terminates your license and b permanently if the copyright holder fails to notify you of the violation by some reasonable means prior to 60 days after the cessation Moreover your license from a particular copyright holder is reinstated permanently if the copyright holder notifies you of the violation by some reasonable means this is the first time you have received notice of violation of this License for any work from that copyright holder and you cure the violation prior to 30 days after your receipt of the notice Termination of your rights under this section does not terminate the licenses of parties who have received copies or rights from you under this License If your
353. ine also marks the start of a line comment but in this case it could also be a logical line number directive see Section 3 3 Comments page 27 or a preprocessor control command see Section 3 1 Preprocessing page 27 If the hash character appears elsewhere on a line it is used to introduce an immediate value This is for compatibility with Sun s assembler Multiple statements on the same line can appear if they are separated by the character 184 Using as 9 24 M68HC11 and M68HC12 Dependent Features 9 24 1 M68HC11 and M68HC12 Options The Motorola 68HC11 and 68HC12 version of as have a few machine dependent options m68hc11 m68hc12 m68hcs12 mm9s12x mm9si2xg This option switches the assembler into the M68HC11 mode In this mode the assembler only accepts 68HC11 operands and mnemonics It produces code for the 68HC11 This option switches the assembler into the M68HC12 mode In this mode the assembler also accepts 68HC12 operands and mnemonics It produces code for the 68HC12 A few 68HC11 instructions are replaced by some 68HC12 instructions as recommended by Motorola specifications This option switches the assembler into the M68HCS12 mode This mode is similar to m68hc12 but specifies to assemble for the 68HCS12 series The only difference is on the assembling of the movb and movw instruction when a PC relative operand is used This option switches the assembler into the M9812
354. ine option arch extension may be used multiple times to add or remove extensions incrementally to the architecture being compiled for arm This performs the same action as code 32 pad count Generate unwinder annotations for a stack adjustment of count bytes A posi tive value indicates the function prologue allocated stack space by decrementing the stack pointer bss This directive switches to the bss section 100 Using as cantunwind Prevents unwinding through the current function No personality routine or exception table data is required or permitted code 16 32 This directive selects the instruction set being generated The value 16 selects Thumb with the value 32 selecting ARM cpu name Select the target processor Valid values for name are the same as for the mcpu commandline option Specifying cpu clears any previously selected architecture extensions name dn register name type index name qn register name type index The dn and qn directives are used to create typed and or indexed register aliases for use in Advanced SIMD Extension Neon instructions The former should be used to create aliases of double precision registers and the latter to create aliases of quad precision registers If these directives are used to create typed aliases those aliases can be used in Neon instructions instead of writing types after the mnemonic or after each operand For example x dn d2 3
355. ine option ARM 97 mavxscalar option i386 146 mavxscalar option x86 64 146 mbarrel shift enabled command line option EI Acccihtaidtia pbRIIe eee pe AP URS 167 qmbig endyan 21 09 bebe rere Rb wd 228 mbreak enabled command line option LM32 DEE dE Ee cake Ud donati ye 167 AMIGIS3 E ie ef E reiege 219 mconstant gp command line option IA 64 163 mcpu command line option Alpha 84 mept option CDU voee ene Ry rbd EE 264 E cL 229 mcpu command line option ARM 95 mcpu command line option Blackfin 114 mcpu command line option M680x0 176 re 2n ego pede saws CRE eR RAN CERES 219 mdcache enabled command line option LM32 TM 167 mdebug command line option Alpha 84 mdivide enabled command line option LM32 TEE 167 mdsbt command line option TIC6X 274 me option stderr redirect 04 264 EE d os Se PGES Rh ees cow SP E sns 219 mepiphany command line option Epiphany 133 mepiphany16 command line option Epiphany aches dl hie daa sehen Seat obtains 133 merrors to file option stderr redirect 264 mesa option 8390 0 eee eee eee 231 mevexlig option 1280 146 mevexlig option x86 64 146 mevexwig option i386 146 mevexwig option x86 64 146
356. ings are not the same 7 63 incbin file skip count The incbin directive includes file verbatim at the current location You can control the search paths used with the I command line option see Chapter 2 Command Line Op tions page 21 Quotation marks are required around file The skip argument skips a number of bytes from the start of the file The count argument indicates the maximum number of bytes to read Note that the data is not aligned in any way so it is the user s responsibility to make sure that proper alignment is provided both before and after the incbin directive 7 64 include file This directive provides a way to include supporting files at specified points in your source program The code from file is assembled as if it followed the point of the include when the end of the included file is reached assembly of the original file continues You can control the search paths used with the I command line option see Chapter 2 Command Line Options page 21 Quotation marks are required around file 7 65 int expressions Expect zero or more expressions of any section separated by commas For each expression emit a number that at run time is the value of that expression The byte order and bit size of the number depends on what kind of target the assembly is for Chapter 7 Assembler Directives 59 7 66 internal names This is one of the ELF visibility directives The other two are hidde
357. inted as exits generate example The generate example option is similar to print opcodes but it gen erates an example for each instruction instead 9 24 2 Syntax In the M68HC11 syntax the instruction name comes first and it may be followed by one or several operands up to three Operands are separated by comma In the normal mode as will complain if too many operands are specified for a given instruction In the MRI mode turned on with M option it will treat them as comments Example inx lda 23 bset 2 x 4 brclr bot 8 foo The presence of a character or a character anywhere on a line indicates the start of a comment that extends to the end of that line A or a character at the start of a line also introduces a line comment but these characters do not work elsewhere on the line If the first character of the line is a then as well as starting a comment the line could also be logical line number directive see Section 3 3 Comments page 27 or a preprocessor control command see Section 3 1 Preprocessing page 27 The M68HC11 assembler does not currently support a line separator character The following addressing modes are understood for 68HC11 and 68HC12 186 Using as Immediate number Address Register number X number Y The number may be omitted in which case 0 is assumed Direct Addressing mode symbol or
358. ion NX negative of condition XX see full description below this expansion mode is disallowed by pcrel These are the simplest jump pseudo operations they always map to one partic ular machine instruction depending on the displacement to the branch target This instruction will be a byte or word branch is that is sufficient Otherwise a long branch will be emitted if available If no long branches are available and the pcrel option is not given an absolute long jump will be emitted instead If no long branches are available the pcrel option is given and a word branch cannot reach the target an error message is generated In addition to standard branch operands as allows these pseudo operations to have all operands that are allowed for jsr and jmp substituting these instruc tions if the operand given is not valid for a branch instruction Here jXX stands for an entire family of pseudo operations where XX is a conditional branch or condition code test The full list of pseudo ops in this family is jhi jls jcc jes jne jeq jvc jvs jpl jmi jge jlt jgt le Usually each of these pseudo operations expands to a single branch instruction However if a word branch is not sufficient no long branches are available and the pcrel option is not given as issues a longer code fragment in terms of NX the opposite condition to XX For example under these conditions jXX foo gives Chapte
359. ion is the machine s byte wide code for that character as assumes your character code is ASCII 4 means 65 B means 66 and so on 3 6 2 Number Constants as distinguishes three kinds of numbers according to how they are stored in the target machine Integers are numbers that would fit into an int in the C language Bignums are integers but they are stored in more than 32 bits Flonums are floating point numbers described below 3 6 2 1 Integers A binary integer is Ob or OB followed by zero or more of the binary digits 01 An octal integer is 0 followed by zero or more of the octal digits 01234567 A decimal integer starts with a non zero digit followed by zero or more digits 0123456789 A hexadecimal integer is Ox or 0X followed by one or more hexadecimal digits chosen from 0123456789abcdef ABCDEF Integers have the usual values To denote a negative integer use the prefix operator discussed under expressions see Section 6 2 3 Prefix Operators page 43 Chapter 3 Syntax 31 3 6 2 2 Bignums A bignum has the same syntax and semantics as an integer except that the number or its negative takes more than 32 bits to represent in binary The distinction is made because in some places integers are permitted while bignums are not 3 6 2 3 Flonums A flonum represents a floating point number The translation is indirect a decimal floating point number from the
360. ions Otherwise the constant will be placed into the nearest literal pool if it not already there and a PC relative LDR instruction will be generated adr register label This instruction will load the address of label into the indicated register The instruction will evaluate to a PC relative ADD or SUB instruction depending upon where the label is located If the label is out of range or if it is not defined in the same file and section as the ADR instruction then an error will be generated This instruction will not make use of the literal pool adrl register label This instruction will load the address of label into the indicated register The instruction will evaluate to one or two PC relative ADD or SUB instructions depending upon where the label is located If a second instruction is not needed a NOP instruction will be generated in its place so that this instruction is always 8 bytes long If the label is out of range or if it is not defined in the same file and section as the ADRL instruction then an error will be generated This instruction will not make use of the literal pool Chapter 9 Machine Dependent Features 105 For information on the ARM or Thumb instruction sets see ARM Software Development Toolkit Reference Manual Advanced RISC Machines Ltd 9 4 6 Mapping Symbols The ARM ELF specification requires that special symbols be inserted into object files to mark certain features a At the s
361. ions of the function perform a GP load One might use this directive instead of prologue if you are also using dwarf2 CFI directives gprel32 expression Computes the difference between the address in expression and the GP for the current object file and stores it in 4 bytes In addition to being smaller than a full 8 byte address this also does not require a dynamic relocation when used in a shared library t_floating expression Stores expression as an IEEE double precision value s_floating expression Stores expression as an IEEE single precision value f floating expression Stores expression as a VAX F format value g_floating expression Stores expression as a VAX G format value d floating expression Stores expression as a VAX D format value Set feature Enables or disables various assembler features Using the positive name of the feature enables while using nofeature disables at Indicates that macro expansions may clobber the assembler tem porary at or 28 register Some macros may not be expanded without this and will generate an error message if noat is in effect When at is in effect a warning will be generated if at is used by the programmer macro Enables the expansion of macro instructions Note that variants of real instructions such as br label vs br 31 1abel are considered alternate forms and not macros move reorder volatile These control whether and how the assembler may re order i
362. isters Bn and the index registers Xn of a storage operand can be skipped If Bn and Xn are skipped a zero will be stored to the operand field The notation changes as follows full notation short notation Dn 0 Bn Dn Bn Dn 0 0 Dn Chapter 9 Machine Dependent Features 235 Dn 0 Dn Dn Ln 0 Dn Ln 9 37 3 4 Instruction Formats The Principles of Operation manuals lists 26 instruction formats where some of the formats have multiple variants For the insn pseudo directive the assembler recognizes some of the formats Typically the most general variant of the instruction format is used by the insn directive The following table lists the abbreviations used in the table of instruction formats OpCode OpCd Part of the op code Bx Base register number for operand x Dx Displacement for operand x DLx Displacement lower 12 bits for operand x DHx Displacement higher 8 bits for operand x Rx Register number for operand x Xx Index register number for operand x Ix Signed immediate for operand x Ux Unsigned immediate for operand x An instruction is two four or six bytes in length and must be aligned on a 2 byte boundary The first two bits of the instruction specify the length of the instruction 00 indicates a two byte instruction 01 and 10 indicates a four byte instruction and 11 indicates a six byte instruction The following table lists the s390 instruction formats that are available with the insn ps
363. it computers permit a variety of branch instructions to do the same job Some of these instructions are short and fast but have a limited range others are long and slow but can branch anywhere in virtual memory Often there are 3 flavors of branch short medium and long Some other assemblers would emit short and medium branches unless told by this option to emit short and long branches t Temporary File Directory Some other assemblers may use a temporary file and this option takes a filename being the directory to site the temporary file Since as does not use a temporary disk file this option makes no difference t needs exactly one filename The Vax version of the assembler accepts additional options when compiled for VMS 292 Using as h n External symbol or section used for global variables names are not case sensi tive on VAX VMS and always mapped to upper case This is contrary to the C language definition which explicitly distinguishes upper and lower case To im plement a standard conforming C compiler names must be changed mapped to preserve the case information The default mapping is to convert all lower case characters to uppercase and adding an underscore followed by a 6 digit hex value representing a 24 digit binary value The one digits in the binary value represent which characters are uppercase in the original symbol name The h n option determines how we map names This takes several valu
364. ith pic will use PC relative rather than slightly faster absolute addresses in those expansions This option is only valid when generating ELF format object files The option march architecture specifies the recognized instruction set and recog nized register names It also controls the architecture type of the object file Valid values for architecture are vO_v10 All instructions and register names for any architecture variant in the set v0 v10 are recognized This is the default if the target is configured as cris v10 Only instructions and register names for CRIS v10 as found in ETRAX 100 LX are recognized This is the default if the target is configured as crisv10 v32 Only instructions and register names for CRIS v32 code name Guinness are recognized This is the default if the target is configured as crisv32 This value implies no mul bug abort A subsequent mul bug abort will turn it back on common vlt v32 Only instructions with register names and addressing modes with opcodes com mon to the v10 and v32 are recognized When N is specified as will emit a warning when a 16 bit branch instruction is expanded into a 32 bit multiple instruction construct see Section 9 8 2 CRIS Expand page 121 Some versions of the CRIS v10 for example in the Etrax 100 LX contain a bug that causes destabilizing memory accesses when a multiply instruction is executed with certain values in
365. ition Example LOCAL external_symbol LOCAL 42 local asymbol This directive operation generates a link time assertion that the operand does not correspond to a global register The operand is an expression that at link time resolves to a register symbol or a number A number is treated as the register having that number There is one restriction on the use of this directive the pseudo directive must be placed in a section with contents code or data The IS directive asymbol IS an expression sets the symbol asymbol to an_expression A symbol may not be set more than once using this directive Local labels may be set using this directive for example 5H IS 4 This directive reserves a global register gives it an initial value and optionally gives it a symbolic name Some examples 208 BYTE WYDE TETRA OCTA Using as areg GREG breg GREG data_value GREG data_buffer greg creg another data value The symbolic register name can be used in place of a non special register If a value isn t provided it defaults to zero Unless the option no merge gregs is specified non zero registers allocated with this directive may be eliminated by as another register with the same value used in its place Any of the in structions CSWAP GO LDA LDBU LDB LDHT LDOU LDO LDSF LDTU LDT LDUNC LDVTS LDWU LDW PR
366. kes the assembler accept instructions from the DSP Release 1 Application Specific Extension from that point on in the assembly The set nodsp directive prevents DSP Release 1 instructions from being accepted The directive set dspr2 makes the assembler accept instructions from the DSP Release 2 Application Specific Extension from that point on in the assembly This dirctive implies set dsp The set nodspr2 directive prevents DSP Release 2 instructions from being accepted The directive set mt makes the assembler accept instructions from the MT Application Specific Extension from that point on in the assembly The set nomt directive prevents MT instructions from being accepted The directive set mcu makes the assembler accept instructions from the MCU Appli cation Specific Extension from that point on in the assembly The set nomcu directive prevents MCU instructions from being accepted The directive set virt makes the assembler accept instructions from the Virtualiza tion Application Specific Extension from that point on in the assembly The set novirt directive prevents Virtualization instructions from being accepted Traditional MIPS assemblers do not support these directives 9 27 12 Directives to override floating point options The directives set softfloat and set hardfloat provide finer control of disabling and enabling float point instructions These directives always override the default that hard float instructions are
367. l relax section no relax EB EL Target PDP11 options mpic mno pic mall mno extensions mextension mno extension mcpu mmachine Target picoJava options mb me Target PowerPC options a32 a64 mpwrx mpwr2 mpwr m601 mppc mppc32 m603 m604 m403 m405 m440 m464 m476 m7400 m7410 m7450 m7455 m750cl mppc64 m620 me500 e500x2 me500mc me500mc64 me5500 me6500 mppc64bridge mbooke mpower4 mpwr4 mpower5 mpwr5 mpwr5x mpower6 mpwr6 mpower7 mpwr7 mpower8 mpwr8 ma2 mcell mspe mtitan me300 mcom many maltivec mvsx mhtm mvle mregnames mno regnames mrelocatable mrelocatable lib K PIC memb mlittle mlittle endian le mbig mbig endian be msolaris mno solaris nops count Target RX options mlittle endian mbig endian m32bit doubles m64bit doubles muse conventional section names msmall data limit mpid mrelax mint register number mgcc abi mrx abi Target s390 options m31 m64 mesa mzarch march CPU mregnames mno regnames mwarn areg zero Target SCORE options EB EL FIXDD NWARN SCORE5 SCORESU SCORE7 SCORE3 march score7 march score3 USE R1 KPIC O0 G num V Target SPARC options Av6 Av7 Av8 Asparclet Asparclite A
368. l of the placement of literal pools pool This is a synonym for ltorg name req register name This creates an alias for register name called name For example foo req wO unreq alias name This undefines a register alias which was previously defined using the req di rective For example foo req wO unreq foo An error occurs if the name is undefined Note this pseudo op can be used to delete builtin in register name aliases eg w0 This should only be done if it is really necessary 9 1 5 Opcodes as implements all the standard AArch64 opcodes It also implements several pseudo op codes including several synthetic load instructions LDR ldr register lt expression gt The constant expression will be placed into the nearest literal pool if it not already there and a PC relative LDR instruction will be generated For more information on the AArch64 instruction set and assembly language notation see ARMv8 Instruction Set Overview available at http infocenter arm com 9 1 6 Mapping Symbols The AArch64 ELF specification requires that special symbols be inserted into object files to mark certain features x At the start of a region of code containing AArch64 instructions d At the start of a region of data 84 Using as 9 2 Alpha Dependent Features 9 2 1 Notes The documentation here is primarily for the ELF object format as also supports the ECOFF and EVAX formats but feature
369. l override A_DIR 9 42 4 Constants Syntax The TIC54X version of as allows the following additional constant formats using a suffix to indicate the radix Binary 000000B 011000b Octal 10Q 224q Hexadecimal 45h OFH 9 42 5 String Substitution A subset of allowable symbols which we ll call subsyms may be assigned arbitrary string values This is roughly equivalent to C preprocessor define macros When as encounters one of these symbols the symbol is replaced in the input stream by its string value Subsym names must begin with a letter Subsyms may be defined using the asg and eval directives See Section 9 42 9 asg page 267 See Section 9 42 9 eval page 267 Expansion is recursive until a previously encountered symbol is seen at which point substitution stops In this example x is replaced with SYM2 SYM2 is replaced with SYM1 and SYMI is replaced with x At this point x has already been encountered and the substitution stops Chapter 9 Machine Dependent Features 265 asg x SYM1 asg SYM1 SYM2 asp SYM2 x add x a final code assembled is add x a Macro parameters are converted to subsyms a side effect of this is the normal as NARG dereferencing syntax is unnecessary Subsyms defined within a macro will have global scope unless the var directive is used to identify the subsym as a local macro variable see Section 9 42 9 var page 267 Substitution may be forced in situations where r
370. l sections sdata and sbss which are small counterparts of data and bss respectively The toolchain will treat such data as small regardless of the G setting On startup systems that support a small data area are expected to initialize register 28 also known as gp in such a way that small data can be accessed using a 16 bit offset from that register For example when addr is small data the dla 4 addr instruction above is equivalent to daddiu 4 28 gp_rel addr Small data is not supported for SVR4 style PIC 9 27 5 Directives to override the ISA level GNU as supports an additional directive to change the MIPS Instruction Set Architecture level on the fly set mipsn n should be a number from 0 to 5 or 32 3212 64 or 64r2 The values other than 0 make the assembler accept instructions for the corresponding ISA level from that point on in the assembly set mipsn affects not only which instructions are permitted but also how certain macros are expanded set mipsO restores the ISA level to 200 Using as its original level either the level you selected with command line options or the default for your configuration You can use this feature to permit specific MIPS III instructions while assembling in 32 bit mode Use this directive with care The set arch cpu directive provides even finer control It changes the effective CPU target and allows the assembler to use instructions specific to a particular
371. l with multiplication overflow and division by zero trap or no break which are synonyms take a trap exception and only work for Instruction Set Architecture level 2 and higher break or no trap also synonyms and the default take a break exception n When this option is used as will issue a warning every time it generates a nop instruction from a macro The following options are available when as is configured for an MCore processor jsri2bsr nojsri2bsr Enable or disable the JSRI to BSR transformation By default this is enabled The command line option nojsri2bsr can be used to disable it sifilter nosifilter Enable or disable the silicon filter behaviour By default this is disabled The default can be overridden by the sifilter command line option relax Alter jump instructions for long displacements mcpu 210 340 Select the cpu type on the target hardware This controls which instructions can be assembled EB Assemble for a big endian target EL Assemble for a little endian target See Section 9 25 1 Meta Options page 190 for the options available when as is config ured for a Meta processor See the info pages for documentation of the MMIX specific options See Section 9 34 1 PowerPC Opts page 224 for the options available when as is con figured for a PowerPC processor See the info pages for documentation of the RX specific options The following optio
372. lar instruction to fit within the bundle then the space at the end of that bundle is filled with no op instructions so the instruction starts in the next bundle As a corollary it s an error if any single instruction s encoding is longer than the bundle size 7 9 bundle lock and bundle unlock The bundle lock and directive bundle unlock directives allow explicit control over instruction bundle padding These directives are only valid when bundle align mode has been used to enable aligned instruction bundle mode It s an error if they appear when bundle align mode has not been used at all or when the last directive was bundle align mode O For some targets it s an ABI requirement that certain instructions may appear only as part of specified permissible sequences of multiple instructions all within the same bundle A pair of bundle lock and bundle unlock directives define a bundle locked instruc tion sequence For purposes of aligned instruction bundle mode a sequence starting with bundle lock and ending with bundle unlock is treated as a single instruction That is the entire sequence must fit into a single bundle and may not span a bundle boundary If necessary no op instructions will be inserted before the first instruction of the sequence so that the whole sequence starts on an aligned bundle boundary It s an error if the sequence is longer than the bundle size For convenience when using bundle lock and bundle
373. ld come first like this Section name flags MG Otype entsize GroupName linkage If flags contains the symbol then it may not also contain the G symbol and the Group Name or linkage fields should not be present Instead says to consider the section that s current before this directive If that section used G then the new section will use G with those same GroupName and linkage fields implicitly If not then the symbol has no effect If no flags are specified the default flags depend upon the section name If the section name is not recognized the default will be for the section to have none of the above flags it will not be allocated in memory nor writable nor executable The section will contain data For ELF targets the assembler supports another type of section directive for compat ibility with the Solaris assembler section name flags Note that the section name is quoted There may be a sequence of comma separated flags alloc section is allocatable write section is writable execinstr section is executable exclude section is excluded from executable and shared library tls section is used for thread local storage This directive replaces the current section and subsection See the contents of the gas testsuite directory gas testsuite gas elf for some examples of how this directive and the other section stack directives work 72 Using as 7 100 set symbol expression Set the value
374. ld is one bit and string is considered to be one word in size Only element descriptors structure union tags align and conditional assembly directives are allowed within struct endstruct align aligns member offsets to word boundaries only ssize if provided will always be assigned the size of the structure The tag directive in addition to being used to define a structure union ele ment within a structure may be used to apply a structure to a symbol Once applied to label the individual structure elements may be applied to label to produce the desired offsets using label as the structure base Set the tab size in the output listing Ignored utag union name 1 element count 1 name 2 element count 2 tname tag utagx tcount name n element count n usize endstruct label tag utag Similar to struct but the offset after each element is reset to zero and the usize is set to the maximum of all defined elements Starting offset for the union is always zero symbol usect section name size blocking flag alignment_flag Reserve space for variables in a named uninitialized section similar to bss usect allows definitions sections independent of bss symbol points to the first location reserved by this allocation The symbol may be used as a variable name size is the allocated size in words blocking flag indicates whether to block this section on a page boundary 128 words see Section
375. le when as is configured for an Altera Nios II processor For details about the PDP 11 machine dependent features options see Section 9 32 1 PDP 11 Options page 219 mpic mno pic Generate position independent or position dependent code The default is mpic mall mall extensions Enable all instruction set extensions This is the default mno extensions Disable all instruction set extensions mextension mno extension Enable or disable a particular instruction set extension mcpu Enable the instruction set extensions supported by a particular CPU and dis able all other extensions mmachine Enable the instruction set extensions supported by a particular machine model and disable all other extensions The following options are available when as is configured for a picoJava processor mb Generate big endian format output Chapter 1 Overview 11 ml Generate little endian format output The following options are available when as is configured for the Motorola 68HC11 or 68HC12 series m68hc11 m68hc12 m68hcs12 mm9s12x mm9s12xg Specify what processor is the target The default is defined by the configuration option when building the assembler xgate ramoffset Instruct the linker to offset RAM addresses from S12X address space into XGATE address space mshort Specify to use the 16 bit integer ABI mlong Specify to use the 32 bit integer ABI mshort double Specify to use t
376. loads the contents of the location pointed to by the label _a_variable into register 6 provided that the label is located somewhere within 256 bytes of the address held in the EP register Note the linker assumes that the EP register contains a fixed address set to the address of the label called __ep This can either be set up automatically by the linker or specifically set by using the defsym __ep lt value gt command line option Computes the offset of the named variable from address 0 and stores the result as a 16 bit signed value in the immediate operand field of the given instruction For example movea zdaoff a variable zero r6 puts the address of the label _a_variable into register 6 assuming that the label is somewhere within the first 32K of memory Strictly speaking it also possible to access the last 32K of memory as well as the offsets are signed Computes the offset of the named variable from the start of the Call Table Area whoes address is helg in system register 20 the CTBP register and stores the result a 6 or 16 bit unsigned value in the immediate field of then given instruction or piece of data For example callt ctoff table funci will put the call the function whoes address is held in the call table at the location labeled table funcl1 302 Using as longcall name Indicates that the following sequence of instructions is a long call to function name The linker will
377. local symbols the local symbols are translated into ordinary symbols using control characters are to hide the ordinal number of the symbol Unfortunately these symbols are not translated back in error messages Thus you may see confusing error messages when local symbols are used Control charac ters 003 control C and 004 control D are used for the MMIX specific local symbol syntax The symbol Main is handled specially it is always global By defining the symbols MMIX start text and __ MMIX start data the ad dress of respectively the text and data segments of the final program can be defined though when linking more than one object file the code or data in the object file containing the symbol is not guaranteed to be start at that position just the final executable See MMIX loc page 207 9 28 3 3 Register names Local and global registers are specified as 0 to 255 The recognized special register names are rJ TA rB rC rD rE rF rG rH rt rk rt rM rN r0 rP rQ rR rS rT rU rV rW rX rY rZ rBB rTT rWW rXX rYY and rZZ A leading is optional for special register names Local and global symbols can be equated to register names and used in place of ordinary registers
378. location counter but the align directive changes it and any label definition captures its current value The location counter of the section where statements are being assembled is said to be the active location counter 4 5 bss Section The bss section is used for local common variable storage You may allocate address space in the bss section but you may not dictate data to load into it before your program executes When your program starts running all the contents of the bss section are zeroed bytes The 1comm pseudo op defines a symbol in the bss section see Section 7 69 1comm page 60 The comm pseudo op may be used to declare a common symbol which is another form of uninitialized symbol see Section 7 32 comm page 52 Chapter 4 Sections and Relocation 37 When assembling for a target which supports multiple sections such as ELF or COFF you may switch into the bss section and define symbols as usual see Section 7 99 section page 69 You may only assemble zero values into the section Typically the section will only contain symbol definitions and skip directives see Section 7 104 skip page 72 Chapter 5 Symbols 39 5 Symbols Symbols are a central concept the programmer uses symbols to name things the linker uses symbols to link and the debugger uses symbols to debug Warning as does not place symbols in the object file in the same order they were declared This may break some debuggers 5 1
379. ls are used for symbols you are never intended to see If you use the L option then as retains these symbols in the object file If you also instruct 1d to retain these symbols you may use them in debugging number This is the number that was used in the local label definition So if the label is written 55 then the number is 55 C B This unusual character is included so you do not accidentally invent a symbol of the same name The character has ASCII value of 002 control B ordinal number This is a serial number to keep the labels distinct The first definition of 0 gets the number 1 The 15th definition of 0 gets the number 15 and so on Likewise the first definition of 1 gets the number 1 and its 15th definition gets 15 as well Chapter 5 Symbols Al So for example the first 1 may be named L1C B1 and the 44th 3 may be named L3C B44 Dollar Local Labels as also supports an even more local form of local labels called dollar labels These labels go out of scope i e they become undefined as soon as a non local label is defined Thus they remain valid for only a small region of the input source code Normal local labels by contrast remain in scope for the entire file or until they are redefined by another occurrence of the same local label Dollar labels are defined in exactly the same way as ordinary local labels except that they have a dollar sign su
380. ls ie hi 6 This modifier is used to load the high 16 bits of the offset of the GOT entry containing the offset of the symbol s address from the TCB to be used for initial exec TLS accesses tls_ie_ha16 tls_le This modifier is like tls_ie_hi16 but it adds one to the value if t1s ie 1016 of the input value is negative Chapter 9 Machine Dependent Features 285 This modifier is used to load the offset of the symbol s address from the TCB to be used for local exec TLS accesses tls le 1016 This modifier is used to load the low 16 bits of the offset of the symbol s address from the TCB to be used for local exec TLS accesses tls le hii16 This modifier is used to load the high 16 bits of the offset of the symbol s address from the TCB to be used for local exec TLS accesses tls le hai 6 This modifier is like tls_le_hi16 but it adds one to the value if t1s 1e 1016 of the input value is negative tls gd call This modifier is used to tag an instrution as the call part of a calling sequence for a TLS GD reference of its operand tls gd add This modifier is used to tag an instruction as the add part of a calling sequence for a TLS GD reference of its operand tls ie load This modifier is used to tag an instruction as the load part of a calling sequence for a TLS IE reference of its operand 9 45 3 TILEPro Directives align expression expression This is the generic align directive The fir
381. matic Instruction Alignment page 308 This optimization is enabled by default Note that the assembler will always align instructions like LOOP that have fixed alignment requirements longcalls no longcalls Enable or disable transformation of call instructions to allow calls across a greater range of addresses See Section 9 52 4 2 Function Call Relaxation page 310 This option should be used when call targets can potentially be out of range It may degrade both code size and performance but the linker can generally optimize away the unnecessary overhead when a call ends up within range The default is no longcalls transform no transform Enable or disable all assembler transformations of Xtensa instructions including both relaxation and optimization The default is transform no transform should only be used in the rare cases when the instructions must be exactly as specified in the assembly source Using no transform causes out of range instruction operands to be errors rename section oldname newname Rename the oldname section to newname This option can be used multiple times to rename multiple sections Chapter 9 Machine Dependent Features 307 9 52 2 Assembler Syntax Block comments are delimited by and End of line comments may be introduced with either or If a 4 appears as the first character of a line then the whole line is treated as a commen
382. mbler should be marked as position independent code PIC fix v4bx Allow BX instructions in ARMv4 code This is intended for use with the linker option of the same name mwarn deprecated mno warn deprecated Enable or disable warnings about using deprecated options or features The default is to warn 98 Using as 9 4 2 Syntax 9 4 2 1 Instruction Set Syntax Two slightly different syntaxes are support for ARM and THUMB instructions The default divided uses the old style where ARM and THUMB instructions had their own separate syntaxes The new unified syntax which can be selected via the syntax directive and has the following main features e Immediate operands do not require a prefix e The IT instruction may appear and if it does it is validated against subsequent condi tional affixes In ARM mode it does not generate machine code in THUMB mode it does e For ARM instructions the conditional affixes always appear at the end of the instruc tion For THUMB instructions conditional affixes can be used but only inside the scope of an IT instruction e All of the instructions new to the V6T2 architecture and later are available Only a few such instructions can be written in the divided syntax e The N and W suffixes are recognized and honored e All instructions set the flags if and only if they have an s affix 9 4 2 2 Special Characters H The presence of a anywhere on a line indicates the st
383. mbol and a jump slot for the symbol is added to the GOT For displacement fields and 16 bit immediate fields the symbol term is replaced with the offset from the start of the GOT to the jump slot for the symbol For a 32 bit pc relative field the pc relative offset to the jump slot from the current instruction address is used plt The plt modifier can be used for 16 bit and 32 bit pc relative immediate fields A procedure linkage table entry is generated for the symbol The symbol term is replaced with the relative offset from the current instruction to the PLT entry for the symbol pltoff The pltoff modifier can be used for 16 bit immediate fields The symbol term is replaced with the offset from the start of the PLT to the address of the symbol gotntpoff The gotntpoff modifier can be used for displacement fields The symbol is added to the static TLS block and the negated offset to the symbol in the static TLS block is added to the GOT The symbol term is replaced with the offset to the GOT slot from the start of the GOT indntpoff The indntpoff modifier can be used for 32 bit pc relative immediate fields The symbol is added to the static TLS block and the negated offset to the symbol in the static TLS block is added to the GOT The symbol term is replaced with the pc relative offset to the GOT slot from the current instruction address For more information about the thread local storage modifiers gotntpoff and indntpoff
384. mbolic debugging information 7 99 section name Use the section directive to assemble the following code into a section named name This directive is only supported for targets that actually support arbitrarily named sections on a out targets for example it is not accepted even with a standard a out section name COFF Version For COFF targets the section directive is used in one of the following ways section name flags section name subsection If the optional argument is quoted it is taken as flags to use for the section Each flag is a single character The following flags are recognized b bss section uninitialized data n section is not loaded writable section data section e exclude section from linking r read only section x executable section s shared section meaningful for PE targets a ignored For compatibility with the ELF version y section is not readable meaningful for PE targets 0 9 single digit power of two section alignment GNU extension If no flags are specified the default flags depend upon the section name If the section name is not recognized the default will be for the section to be loaded and writable Note the n and w flags remove attributes from the section rather than adding them so if they are used on their own it will be as if no flags had been specified at all If the optional argument to the section directive is not quoted it is taken as a sub section number
385. me number close to number Increasing this value can reduce the length of time it takes the assembler to perform its tasks at the expense of increasing the assembler s memory require ments Similarly reducing this value can reduce the memory requirements at the expense of speed reduce memory overheads This option reduces GAS s memory requirements at the expense of making the assembly processes slower Currently this switch is a synonym for hash size 4051 but in the future it may have other effects as well statistics Print the maximum space in bytes and total time in seconds used by assem bly strip local absolute Remove local absolute symbols from the outgoing symbol table v version Print the as version version Print the as version and exit W no warn Suppress warning messages 8 Using as fatal warnings Treat warnings as errors warn Don t suppress warning messages or treat them as errors W Ignored x Ignored Z Generate an object file even after errors files Standard input or source files to assemble See Section 9 1 1 AArch64 Options page 82 for the options available when as is con figured for the 64 bit mode of the ARM Architecture AArch64 See Section 9 2 2 Alpha Options page 84 for the options available when as is configured for an Alpha processor The following options are available when as is configured for an ARC processor marc 5161718 This o
386. men 282 TILEPro support 2 29 bnDR RIDE DR er 282 TILEPrIOSyntaExz ie YletereeReeNe RR E 282 time total for assembly ererecrirerininirorerss 25 title directive 1 2 l l esdc ek EGER De E ein 75 tls_gd directive Nios HU 216 tls ie directive Nos 216 tls_ldm directive Nios I 216 tls_ldo directive Nios I 216 tls le directive Nos 216 TMS320C6X support 274 tp register V 850 ioco ore ee ROI er eee 297 transform directive 0 0 c eee eee eee eee 312 trusted compiler 0 cece eee ass 22 turning preprocessing on and off 2T type directive COFF version 76 type directive ELF version 76 type of asvmbol 0 cece eee eee 41 U nalong directive BH occorre 250 u quad directive SH cessere NEE SN 250 uaword directive SH 250 ubyte directive DIOhAX 267 uchar directive TICh4X 267 uhalf directive TICh4AX 269 uint directive TIC54X 0 0006 269 ulebi28 directive cece ee eee 77 ulong directive TIC54X lt srirrsirsissiess seras 269 undefined section 35 union directive TICA4X 21 REESEN ee cou PUE ORBE RI S EE 290 usect directive TICE 211 ushort directive TTIORBAN 269 uword directive TICA4X 269 V V850 command line options 295 V850 floating point DEEFT 299 V850 line comment character 297 V850 line separator 06 c eee eee ee eee 297 V850 machine directives 0005 299
387. modifiers M 170 Motorola syntax for the 680x0 180 MOVI instructions relaxation esescscs 310 MOVN MOVZ and MOVK group relocations A ArCh64 cia eke ad Ee pee REIR RS 82 MOVW and MOVT relocations ARM 98 MRI compatibility mode 23 ee e tp DIR eRIPPEDII 65 MRI mode temporarily ssssssssrreere ne 65 MSP 430 floating point IEEE 213 MSP 430 1dent terg 20 eee eee eee 212 MSP 430 line comment character 211 MSP 430 line separator 211 MSP 430 machine directives 213 MSP 430 macros cv me Mesa pate ERE 211 MSP 430 opcodes Lsseeeeeesseeeese 213 MSP 430 options none 211 MSP 430 profiling capability 213 MSP 430 register namen 212 MSP 430 support RR Rr RIS 211 MSP430 Assembler Extensions 212 mul instruction OPE a e EEN SEA 155 mul instruction HDD 155 N Using as HAMED Secblon secas eene nre ste ate eee meng eased 69 named seeblong n seincrc gevi n fre Peasy dacs 34 names symbol a Eat ERENNERT 39 naming object Die 25 new page in listings lees 53 newblock directive TIC54X 270 E A EE 29 newline required at file end 28 Nios II line comment character 215 Nios II line separator character 215 Nios II machine directives 216 Nios II machine relocations 215 Nios opcodes 2 i2 ie RR 3g
388. mplex structures into symbol names using this field type An absolute expression The symbol s type is set to the low 8 bits of this expression Any bit pattern is permitted but 1d and debuggers choke on silly bit patterns other An absolute expression The symbol s other attribute is set to the low 8 bits of this expression desc An absolute expression The symbol s descriptor is set to the low 16 bits of this expression value An absolute expression which becomes the symbol s value If a warning is detected while reading a stabd stabn or stabs statement the symbol has probably already been created you get a half formed symbol in your object file This is compatible with earlier assemblers Stabd type other desc The name of the symbol generated is not even an empty string It is a null pointer for compatibility Older assemblers used a null pointer so they didn t waste space in object files with empty strings The symbol s value is set to the location counter relocatably When your program is linked the value of this symbol is the address of the location counter when the stabd was assembled Stabn type other desc value The name of the symbol is set to the empty string Stabs string type other desc value All five fields are specified 74 Using as 7 108 string str string8 str string16 str string32 str string64 str Copy the characters in str to the object fil
389. myl16 305 COMMENDS is secede es eae a REA RR RIGEN E REPE Dik comments Most 183 comments removed by preprocessor 27 common directive DARC 262 ee eent e 60 common variable storage csssrrererrree 36 compare and jump expansions 1960 161 compare branch instructions i960 161 comparison expressions 200 eee eee eee 44 conditional assembly sssri rirsrcitereeciinist as 57 constant single character 30 ESCH seriis paw arni rori baa N RR ERES 29 constants Benn deg ERES 31 constants character e s 29 constants converted by preprocessor 27 constants floating point ER constants INGESER EE 30 constants number v NEEN er nre 30 constants page 22 Nee SEA e ep EIE 258 constants SUnng ioionlelie bles me WERTE NUR 29 constants DICSAX ooi stade otote Renis 264 conversion instructions 1386 suus 148 conversion instructions x86 64 148 coprocessor wait i386 ee eee 150 copy directive TIC54X 0 268 cpu directive Monte 181 cpu directive MSP 430 0 0 213 CR16 line comment character 119 CR16 line separator 0 02 e eee eee 119 CR16 Operand Oualterz 118 CEUO SUDpOEPU 2i2e 02 RIbRR Pee ele e needa 118 crash of assembler ii ese cere ene 315 CRIS emulation crisaout command line EE TEE 120 CRIS emulation criself comma
390. n The two kinds of syntax are fully compatible In the following table apc stands for any of the address registers a0 through 4a7 the program counter Apc the zero address relative to the program counter Azpe or a suppressed address register 4za0 through ear The use of size means one of w or T and it may always be omitted along with the leading dot The use of scale means one of 1 2 4 or 8 and it may always be omitted along with the leading asterisk The following additional addressing modes are understood Address Register Indirect a0 through a7 hal is also known as hsp i e the Stack Pointer 4a6 is also known as fp the Frame Pointer Address Register Postincrement 4a0 through a7 Address Register Predecrement a0 through a7 Indirect Plus Offset number a0 through number fa7 or number 4pc The number may also appear within the parentheses as in number 4a0 When used with the pc the number may be omitted with an address register omitting the number produces Address Register Indirect mode Index number apc register size scale The number may be omitted or it may appear within the parentheses The apc may be omitted The register and the apc may appear in either order If both apc and register are address registers and the size and scale
391. n see Section 7 59 bidden page 56 and protected see Section 7 90 protected page 67 This directive overrides the named symbols default visibility which is set by their bind ing local global or weak The directive sets the visibility to internal which means that the symbols are considered to be hidden i e not visible to other components and that some extra processor specific processing must also be performed upon the symbols as well 7 67 irp symbol values Evaluate a sequence of statements assigning different values to symbol The sequence of statements starts at the irp directive and is terminated by an endr directive For each value symbol is set to value and the sequence of statements is assembled If no value is listed the sequence of statements is assembled once with symbol set to the null string To refer to symbol within the sequence of statements use Nsymbol For example assembling irp param 1 2 3 move dNparam spe endr is equivalent to assembling move di sp move d2 sp move d3 spQ For some caveats with the spelling of symbol see also Section 7 79 Macro page 62 7 68 irpc symbol values Evaluate a sequence of statements assigning different values to symbol The sequence of statements starts at the irpc directive and is terminated by an endr directive For each character in value symbol is set to the character and the sequence of statements is assembled If no value is li
392. n explicit parallel conflicts option ignore parallel conflicts This option tells the assembler s to stop checking parallel instructions for con straint violations This ability is provided for hardware vendors testing chip designs and should not be used under normal circumstances no ignore parallel conflicts This option restores the assembler s default behaviour of checking parallel in structions to detect constraint violations Ip This is a shorter synonym for the ignore parallel conflicts option nIp This is a shorter synonym for the no ignore parallel conflicts option warn unmatched high This option tells the assembler to produce a warning message if a high pseudo op is encountered without a matching low pseudo op The presence of such an unmatched pseudo op usually indicates a programming error no warn unmatched high Disables a previously enabled warn unmatched high option Wuh This is a shorter synonym for the warn unmatched high option Wnuh This is a shorter synonym for the no warn unmatched high option 9 22 2 M32R Directives The Renease M32R version of as has a few architecture specific directives low expression The low directive computes the value of its expression and places the lower 16 bits of the result into the immediate field of the instruction For example or3 r0 rO low 0x12345678 compute rO rO 0x5678 add3 rO rO low fred compute rO r0 low 16 bits of address of fred h
393. n go into a shared library The mno shared option tells gas to generate code which uses the calling convention but can not go into a shared library The resulting code is slightly more efficient This option only affects the handling of the cpload and cpsetup pseudo ops 9 27 2 High level assembly macros MIPS assemblers have traditionally provided a wider range of instructions than the MIPS architecture itself These extra instructions are usually referred to as macro instructions Some MIPS macro instructions extend an underlying architectural instruction while others are entirely new An example of the former type is and which allows the third operand to be either a register or an arbitrary immediate value Examples of the latter 1 The term macro is somewhat overloaded here since these macros have no relation to those defined by macro see Section 7 79 macro page 62 198 Using as type include bgt which branches to the third operand when the first operand is greater than the second operand and ulh which implements an unaligned 2 byte load One of the most common extensions provided by macros is to expand memory offsets to the full address range 32 or 64 bits and to allow symbolic offsets such as my_data 4 to be used in place of integer constants For example the architectural instruction lbu allows only a signed 16 bit offset whereas the macro Lu allows code such as lbu 4 arr
394. n selects little endian byte order default and mbe selects big endian byte order Note that LA 64 machine code always uses little endian byte order mtune itanium1 mtune itanium2 Tune for a particular A 64 CPU itaniuml or itanium2 The default is ita nium2 munwind check warning munwind check error These options control what the assembler will do when performing consistency checks on unwind directives munwind check warning will make the assem bler issue a warning when an unwind directive check fails This is the default munwind check error will make the assembler issue an error when an unwind directive check fails mhint b ok mhint b warning mhint b error These options control what the assembler will do when the hint b instruction is used mhint b ok will make the assembler accept hint b 164 Using as mint b warning will make the assembler issue a warning when hint b is used mhint b error will make the assembler treat hint b as an error which is the default y xexplicit These options turn on dependency violation checking xauto This option instructs the assembler to automatically insert stop bits where necessary to remove dependency violations This is the default mode xnone This option turns off dependency violation checking xdebug This turns on debug output intended to help tracking down bugs in the depen d
395. n the byte order of an integer on the computer as is assembling for Each size bytes in a repetition is taken from the lowest order size bytes of this number Again this bizarre behavior is compatible with other people s assemblers size and value are optional If the second comma and value are absent value is assumed zero If the first comma and following tokens are absent size is assumed to be 1 7 55 float flonums This directive assembles zero or more flonums separated by commas It has the same effect as single The exact kind of floating point numbers emitted depends on how as is configured See Chapter 9 Machine Dependencies page 81 7 56 func name label func emits debugging information to denote function name and is ignored unless the file is assembled with debugging enabled Only gstabs is currently supported label is the entry point of the function and if omitted name prepended with the leading char is used leading char is usually _ or nothing depending on the target All functions are currently defined to have void return type The function must be terminated with endfunc 7 57 global symbol globl symbol global makes the symbol visible to 1d If you define symbol in your partial program its value is made available to other partial programs that are linked with it Otherwise symbol takes its attributes from a symbol of the same name from another file linked into the same program
396. nches see Section 9 23 6 1 Branch Improvement page 182 m68000 as can assemble code for several different members of the Motorola 680x0 family The default depends upon how as was configured when it was built normally the default is to assemble code for the 68020 microprocessor The following options may be used to change the default These options control which in structions and addressing modes are permitted The members of the 680x0 family are very similar For detailed information about the differences see the Motorola manuals m68000 m68ec000 m68hc000 n68hc001 m68008 m68302 m68306 m68307 n68322 m68356 Assemble for the 68000 m68008 m68302 and so on are syn onyms for m68000 since the chips are the same from the point of view of the assembler 178 Using as m68010 Assemble for the 68010 m68020 m68ec020 Assemble for the 68020 This is normally the default m68030 m68ec030 Assemble for the 68030 m68040 m68ec040 Assemble for the 68040 m68060 m68ec060 Assemble for the 68060 mcpu32 m68330 n68331 n68332 m68333 n68334 m68336 n68340 n68341 n68349 m68360 Assemble for the CPU32 family of chips m5200 m5202 m5204 m5206 m5206e m521x m5249 m528x m5307 m5407 m54T7x m548x mc
397. ncrement reg reg regt Index Register plus Register Offset with Pre decrement reg reg reg The register can be either RO R1 RZ R3 R4 R5 RO or RT Convience macro opcodes to deal with 16 bit values have been added Immediate 16 Bit Wide number or symbol For example ldw R1 1024 ldw R3 timer ldw R1 R1 0 COM R1 stw R2 Ri 0 9 50 3 Assembler Directives The XGATE version of as have the following specific assembler directives 9 50 4 Floating Point Packed decimal P format floating literals are not supported yet The floating point formats generated by directives are these float Single precision floating point constants double Double precision floating point constants extend ldouble Extended precision long double floating point constants Using as Chapter 9 Machine Dependent Features 305 9 50 5 Opcodes 9 51 XStormy16 Dependent Features 9 51 1 Syntax 9 51 1 1 Special Characters is the line comment character If a appears as the first character of a line the whole line is treated as a comment but in this case the line can also be a logical line number directive see Section 3 3 Comments page 27 or a preprocessor control command see Section 3 1 Preprocessing page 27 A semicolon can be used to start a comment that extends from wherever the char acter appears on the line up to the end
398. nd line option O 120 CRIS march architecture command line EI EI EE 120 CRIS mul bug abort command line option is le EE Ee i sio ats 120 CRIS no mul bug abort command line option Te 120 CRIS no underscore command line option ade 120 CRIS pic command line option 120 CRIS underscore command line option 120 CRIS N command line option 120 CRIS architecture variant option 120 CRIS assembler directive arch 124 CRIS assembler directive dword 123 CRIS assembler directive syntax 123 CRIS assembler directives 204 123 CRIS built in symbols o erccsrsrsiiriniernsss 121 CRIS instruction expansion 121 CRIS line comment characters 122 337 CRIS Options oreet rre 120 CRIS position independent code 120 CRIS pseudo op arch 124 CRIS pseudo op dword e 0 eee 123 CRIS pseudo op Syntax 0 eee eee eee 123 CRIS pseudo OpS scssecsectp sete ene 123 CRIS register namen 123 CHRIS 8Uppotb rors i tese EEn ERR ce te sang ewes 120 CRIS symbols in position independent code 122 ctbp register V850 ciis ce er eR 299 ctoff pseudo op V850 ecssisirisssisiaissse 301 ctpc register VSbU 0 ee eee ee eee 299 ctpsw register VSbU eterisk 299 current address ANERE RENE EN SE EN 41
399. ndirect address register pointers for Data Space addressing One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory These added function registers are the 16 bit X Y and Z registers X r26 r27 Y r28 r29 Z r30 r31 9 5 2 3 Relocatable Expression Modifiers The assembler supports several modifiers when using relocatable addresses in AVR instruc tion operands The general syntax is the following modifier relocatable expression 108 This modifier allows you to use bits 0 through 7 of an address expression as 8 bit relocatable expression hi8 This modifier allows you to use bits 7 through 15 of an address expression as 8 bit relocatable expression This is useful with for example the AVR ldi instruction and 108 modifier For example ldi r26 1o8 sym 10 ldi r27 hi8 sym 10 hh8 This modifier allows you to use bits 16 through 23 of an address expression as 8 bit relocatable expression Also can be useful for loading 32 bit constants h1o8 Synonym of hh hhi8 This modifier allows you to use bits 24 through 31 of an expression as 8 bit expression This is useful with for example the AVR ldi instruction and 108 hi8 hlo8 hhi8 modifier For example ldi r26 108 285774925 ldi r27 hi8 285774925 ldi r28 hlo8 285774925 ldi r29 hhi8 285774925 r29 r28 r27 r26 285774925 pm_l
400. nerated by directives are these float Single precision 32 bit floating point constants double If the m64bit doubles command line option has been specified then then double directive generates double precision 64 bit floating point constants otherwise it generates single precision 32 bit floating point constants To force the generation of 64 bit floating point constants used the dc d directive instead 9 36 5 Syntax for the RX 9 36 5 1 Special Characters The presence of a appearing anywhere on a line indicates the start of a comment that extends to the end of that line If a 4 appears as the first character of a line then the whole line is treated as a com ment but in this case the line can also be a logical line number directive see Section 3 3 Comments page 27 or a preprocessor control command see Section 3 1 Preprocessing page 27 The character can be used to separate statements on the same line Chapter 9 Machine Dependent Features 231 9 37 IBM S 390 Dependent Features The s390 version of as supports two architectures modes and seven chip levels The archi tecture modes are the Enterprise System Architecture ESA and the newer z Architecture mode The chip levels are g5 g6 z900 z990 z9 109 z9 ec z10 z196 and zEC12 9 37 1 Options The following table lists all available s390 specific options m31 m64 Select 31 or 64 bit ABI implying a word size of 32 or 64 bit These o
401. nerating listings If you do not use psize listings use a default line count of 60 You may omit the comma and columns specification the default width is 200 columns as generates formfeeds whenever the specified number of lines is exceeded or whenever you explicitly request one using eject If you specify lines as 0 no formfeeds are generated save those explicitly specified with eject 68 Using as 7 92 purgem name Undefine the macro name so that later uses of the string will not be expanded See Section 7 79 Macro page 62 7 93 pushsection name subsection flags typeL arguments This is one of the ELF section stack manipulation directives The others are section see Section 7 99 Section page 69 subsection see Section 7 110 SubSection page 74 popsection see Section 7 87 PopSection page 66 and previous see Section 7 88 Previous page 66 This directive pushes the current section and subsection onto the top of the section stack and then replaces the current section and subsection with name and subsection The optional flags type and arguments are treated the same as in the section see Section 7 99 Section page 69 directive 1 94 quad bignums quad expects zero or more bignums separated by commas For each bignum it emits an 8 byte integer If the bignum won t fit in 8 bytes it prints a warning message and just takes the lowest order 8 bytes of the bignum The t
402. no longer support this directive it is recognized only for compatibility with existing assembler programs Even though this is a directive associated with the a out or b out object code formats as still recognizes it when producing COFF output and treats line as though it were the COFF 1n if it is found outside a def endef pair Inside a def line is instead one of the directives used by compilers to generate auxiliary symbol information for debugging 7 72 linkonce type Mark the current section so that the linker only includes a single copy of it This may be used to include the same section in several different object files but ensure that the linker will only include it once in the final output file The linkonce pseudo op must be used for each instance of the section Duplicate sections are detected based on the section name so it should be unique This directive is only supported by a few object file formats as of this writing the only object file format which supports it is the Portable Executable format used on Windows NT The type argument is optional If specified it must be one of the following strings For example linkonce same size Not all types may be supported on all object file formats discard Silently discard duplicate sections This is the default one only Warn if there are duplicate sections but still keep only one copy same size Warn if any of the duplicates have different
403. nored 9 9 2 6 eWORD Modifier Any symbol followed by word will be replaced by the symbol s value shifted right by 2 This is used in situations such as loading a register with the address of a function or any other code fragment For example if you want to load a register with the location of the function main then jump to that function you could do it as follows tai r2 main word jmp r2 9 9 3 Floating Point The D10V has no hardware floating point but the float and double directives generates IEEE floating point numbers for compatibility with other development tools 9 9 4 Opcodes For detailed information on the D10V machine instruction set see D10V Architecture A VLIW Microprocessor for Multimedia Applications Mitsubishi Electric Corp as imple ments all the standard D10V opcodes The only changes are those described in the section on size modifiers Chapter 9 Machine Dependent Features 129 9 10 D30V Dependent Features 9 10 1 D30V Options The Mitsubishi D30V version of as has a few machine dependent options Q The D30V can often execute two sub instructions in parallel When this option is used as will attempt to optimize its output by detecting when instructions can be executed in parallel lt n When this option is used as will issue a warning every time it adds a nop instruction CN When this option is used as will issue a warning if it needs to insert a nop after a 32 bit multiply bef
404. ns This chapter describes command line options available in all versions of the GNU assembler see Chapter 9 Machine Dependencies page 81 for options specific to particular machine architectures If you are invoking as via the GNU C compiler you can use the Wa option to pass arguments through to the assembler The assembler arguments must be separated from each other and the Wa by commas For example gcc c g O Wa alh L file c This passes two options to the assembler alh emit a listing to standard output with high level and assembly source and L retain local symbols in the symbol table Usually you do not need to use this Wa mechanism since many compiler command line options are automatically passed to the assembler by the compiler You can call the GNU compiler driver with the v option to see precisely what options it passes to each compilation pass including the assembler 2 1 Enable Listings alcdghlns These options enable listing output from the assembler By itself a requests high level assembly and symbols listing You can use other letters to select specific options for the list ah requests a high level language listing al requests an output program assembly listing and as requests a symbol table listing High level listings require that a compiler debugging option like g be used and that assembly listings al be re
405. ns for v7 A architecture implies idiv and xscale march architecture extension This option specifies the target architecture The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target architecture The following architecture names are recognized armvi armv2 armv2a armv2s armv3 armv3m armv4 armv4xm armv4t armv4txm armv5 armvoSt armvOtxm armvSte armv5texp armv6 armv6j armv6k armv6z armv6zk armv6 m armv6s m armv armv a armv7ve armv7 r armv7 m armv7e m armv8 a iwmmxt and xscale If both mcpu and march are specified the assembler will use the setting for mcpu The architecture option can be extended with the same instruction set extension options as the mcpu option mfpu floating point format mthumb This option specifies the floating point format to assemble for The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target floating point unit The following format options are recognized softfpa fpe fpe2 fpe3 fpa fpal0 fpaii arm7500fe softvfp softvfptvfp vfp vfp10 vfpi0 rO vfp9 vfpxd vfpv2 vfpv3 vfpv3 fp16 vfpv3 d16 vfpv3 di6 fp16 vfpv3xd vfpv3xd di6 vfpv4 vfpv4 di6 fpv4 sp di6 fp armv8 arm1020t arm1020e arm1136jf s maverick neon neon vfpv4 neon fp armv8 and crypto neon fp armv8 In addition to determining which instructions are as
406. ns are available when as is configured for the s390 processor family m31 m64 Select the word size either 31 32 bits or 64 bits mesa mzarch Select the architecture mode either the Enterprise System Architecture esa or the z Architecture mode zarch march processor Specify which s390 processor variant is the target g6 ep z900 z990 z9 109 z9 ec z10 z196 or zEC12 16 Using as mregnames mno regnames Allow or disallow symbolic names for registers mwarn areg zero Warn whenever the operand for a base or index register has been specified but evaluates to zero See Section 9 43 1 TIC6X Options page 274 for the options available when as is configured for a TMS320C6000 processor See Section 9 44 1 TILE Gx Options page 277 for the options available when as is configured for a TILE Gx processor See Section 9 52 1 Xtensa Options page 306 for the options available when as is configured for an Xtensa processor The following options are available when as is configured for a Z80 family processor z80 Assemble for Z80 processor r800 Assemble for R800 processor ignore undocumented instructions Wnud Assemble undocumented Z80 instructions that also work on R800 without warn ing ignore unportable instructions Wnup Assemble all undocumented Z80 instructions without warning warn undocumented instructions Wud Issue a warning for undocumented Z80
407. nse notice requires Cover Texts you must enclose the copies in covers that carry clearly and legibly all these Cover Texts Front Cover Texts on the front cover and Back Cover Texts on the back cover Both covers must also clearly and legibly identify you as the publisher of these copies The front cover must present the full title with all words of the title equally prominent and visible You may add other material on the covers in addition Copying with changes limited to the covers as long as they preserve the title of the Document and satisfy these conditions can be treated as verbatim copying in other respects If the required texts for either cover are too voluminous to fit legibly you should put the first ones listed as many as fit reasonably on the actual cover and continue the rest onto adjacent pages If you publish or distribute Opaque copies of the Document numbering more than 100 you must either include a machine readable Transparent copy along with each Opaque copy or state in or with each Opaque copy a computer network location from which the general network using public has access to download using public standard network protocols a complete Transparent copy of the Document free of added material If you use the latter option you must take reasonably prudent steps when you begin distribution of Opaque copies in quantity to ensure that this Transparent copy will remain thus accessible at the stated location until at least
408. nsions m11 03 Same as mkd11f Chapter 9 Machine Dependent Features 221 m11 04 Same as mkd11d m11 05 m11 10 Same as mkd11b m11 15 m11 20 Same as mka11 m11 21 Same as mti1 m11 23 m11 24 Same as mf11 m11 34 Same as mkdlle m11 34a Ame as mkdile mfpp m11 35 m11 40 Same as mkd11a m11 44 Same as mkd11z m11 45 m11 50 m11 55 m11 70 Same as mkb11 m11 53 m11 73 m11 83 m11 84 m11 93 m11 94 Same as mj11 m11 60 Same as mkd11k 9 32 2 Assembler Directives The PDP 11 version of as has a few machine dependent assembler directives bss Switch to the bss section even Align the location counter to an even number 9 32 3 PDP 11 Assembly Language Syntax as supports both DEC syntax and BSD syntax The only difference is that in DEC syntax a character is used to denote an immediate constants while in BSD syntax the character for this purpose is general purpose registers are named rO through r7 Mnemonic alternatives for r6 and r7 are sp and pc respectively Floating point registers are named ac through ac3 or alternatively frO through fr3 Comments are started with a or a character and extend to the end of the line FIXME clash with immediates Multiple statements on the same line can be separated by the character 9 32 4 Instruction Naming Some instructions have alternative names BCC BHIS BCS BLO 222 Using as
409. nstruc tions Accepted for compatibility with the OSF 1 assembler but as does not do instruction scheduling so these features are ignored The following directives are recognized for compatibility with the OSF 1 assembler but are ignored proc aproc reguse livereg option aent ugen eflag alias noalias 90 Using as 9 2 6 Opcodes For detailed information on the Alpha machine instruction set see the Alpha Architecture Handbook located at ftp ftp digital com pub Digital info semiconductor literature alphaahb pdf Chapter 9 Machine Dependent Features 91 9 3 ARC Dependent Features 9 3 1 Options marc 5 6 7 8 This option selects the core processor variant Using marc is the same as marc6 which is also the default arcb Base instruction set arc6 Jump and link jl instruction No requirement of an instruction between setting flags and conditional jump For example mov f rO r1 beq foo arc Break brk and sleep sleep instructions arc8 Software interrupt swi instruction Note the option directive can to be used to select a core variant from within assembly code EB This option specifies that the output generated by the assembler should be marked as being encoded for a big endian processor EL This option specifies that the output generated by the assembler should be marked as being encoded for a little endian processor this is the default 9 3 2 Syntax 9 3 2 1 Special Characters
410. ny261 attiny261a at tiny461 attiny461a attiny861 attiny86la attiny87 attiny43u attiny48 at tiny88 atS6rf401 Instruction set avr3 is for the classic AVR core with up to 128K program mem ory space MCU types at43usb355 at76c711 Instruction set avr3l is for the classic AVR core with exactly 128K program memory space MCU types atmegal03 at43usb320 Instruction set avr35 is for classic AVR core plus MOVW CALL and JMP instructions MCU types attinyl67 at90usb82 at90usb162 atmega8u2 at megal6u2 atmega32u2 Instruction set avr4 is for the enhanced AVR core with up to 8K program memory space MCU types atmega48 atmega48a atmega48p atmega8 atmega88 atmega88a atmega88p atmega88pa atmega8515 atmega8535 atmega8hva at90pwml at90pwm2 at90pwm2b at90pwm3 at90pwm3b at90pwm81 ata6289 Instruction set avr5 is for the enhanced AVR core with up to 128K program memory space MCU types atmegal6 atmegal6a atmegal61 atmegal62 atmegal63 atmegal64a atmegal64p atmegal65 atmegal65a atmegal65p atmegal68 atmegal68a atmegal68p atmegal69 atmegal69a atmegal69p atmegal69pa atmega32 atmega323 atmega324a atmega324p atmega325 atmega325a atmega325p atmega325pa atmega3250 atmega3250a at mega3250p atmega3250pa atmega328 atmega328p atmega329 atmega329a atmega329p atmega329pa atmega3290 atmega3290a atmega3290p atmega3290pa atmega406 atmega64 atmega640 atmega644 atmega644a atmega644p
411. o i e e o ni pe Kadaka ns 254 SparCvlSOf s ssieessme n bene eeu 254 AVG Pr 254 SNT eee ey eee ae erue SLM SE 254 Io op 254 zi p 254 E C DE 254 EE 254 e LC LARES BRL RM RNSRRRRRe 254 AVOG essi prertkud e e seul uber e stad Pares 254 e EE 254 b Option 1960 EE 159 big option MR obser bx hee tpa 172 LM 22 D ignored om VAX i coe edo er E el Ca 291 zd VAK OPON leese Se EE ans 291 eabi command line option ARM 97 EB command line option AArch64 82 EB command line option ARC 91 EB command line option ARM 97 EB option MIPS reel eee eee 192 EB option M32R sciite aieeaa eee es 172 EB option TILE Gx esee 211 EL command line option AArch64 82 EL command line option ARC 91 EL command line option ARM 97 EL option MIPS s cocer ir bre dosed eher 192 EL option M32 E seat RIED ER RES E 172 EL option TILE GX aere need ees nens 277 SE ee EE ach tein ada seas 22 F command line option Alpha 84 g command line option Alpha 84 G command line option Alpha 84 G option MIPS geriyor ocius e ee rex eesi 192 h option MAXZINVMS 292 H option VAXZIVMS 0c eee eee 292 SE path EE 22 ignore parallel conflicts option M32RX EE 173 Ip option M32RX EEN EINEN EEN eee 173 J ignored on VAX ee EEN NEEN cete ees 291 Epl
412. o seven RR RS ER OC re Renee gs 129 OOD OVI oats pam cries trae EN ades UE E 129 9 10 2 1 Size Moditers cece eee eee eens 129 9 10 2 2 Sub Instructions roteadores iti rusti ee 129 9 10 2 3 Special Character 129 9 10 2 4 Guarded Faecution eee eee eee 131 9 10 2 5 Register Names 0 cece ee cece T31 9 10 2 6 Addressing Modes eee e eee eee ees 132 9 10 3 Floating Point eec te Ree 132 9 10 4 Opeod6es scs se corre xr ime I ree mee RR d 132 9 11 Epiphany Dependent Features sseeeeeeesseeee 133 OTD Options EP 133 9 11 2 Epiphany Syntax cece eee ees 133 9 11 2 1 Special Characters eposi cece eee eee 133 9 12 H8 300 Dependent Features 134 9 12 1 Options iei Rr RE shuns ee ERE EN ER RR PCS 134 9 122 Synta eesriie sak kae depone dcc pra ede Eo reu suae 134 9 12 2 1 Special Characters 0 ccc eee eens 134 9 12 2 2 Register Name 134 9 12 2 3 Addressing Modes cece eee eee ees 134 9 12 3 Floating PO eR 135 9 12 4 H8 300 Machine Directives reise hr ERR Rene 136 9 12 5 Opcod6e8 ssii seis eed eret ERR SEENEN EE RE 136 9 13 HPPA Dependent Features 137 9 19 1 INOUGSU EE 137 9 13 2 OptlOHs iileelesbeerexrtePRIEE Ed NEE Se I DIAS 137 9 13 3 tte ue Ae hi tentrebrasa SEN E Erb Dei en 137 9 13 4 Floating Ponte oni eese eee pb Eo es 137 9 13 5 HPPA Assembler Directives ssssssesseeeeeeesse 137 9 13 6 OpPCOGeS eiua eise en hod we PED aT ek E Re Rs 141 9
413. o zero 66 Using as 7 86 p2align wl abs expr abs expr abs expr Pad the location counter in the current subsection to a particular storage boundary The first expression which must be absolute is the number of low order zero bits the location counter must have after advancement For example p2align 3 advances the location counter until it a multiple of 8 If the location counter is already a multiple of 8 no change is needed The second expression also absolute gives the fill value to be stored in the padding bytes It and the comma may be omitted If it is omitted the padding bytes are normally zero However on some systems if the section is marked as containing code and the fill value is omitted the space is filled with no op instructions The third expression is also absolute and is also optional If it is present it is the maximum number of bytes that should be skipped by this alignment directive If doing the alignment would require skipping more bytes than the specified maximum then the alignment is not done at all You can omit the fill value the second argument entirely by simply using two commas after the required alignment this can be useful if you want the alignment to be filled with no op instructions when appropriate The p2alignw and p2alignl directives are variants of the p2align directive The p2alignw directive treats the fill pattern as a two byte word value The p2alignl di rectives treats t
414. o8 This modifier allows you to use bits 0 through 7 of an address expression as 8 bit relocatable expression This modifier useful for addressing data or code from Flash Program memory The using of pm_108 similar to 108 Chapter 9 Machine Dependent Features 111 pm hi8 This modifier allows you to use bits 8 through 15 of an address expression as 8 bit relocatable expression This modifier useful for addressing data or code from Flash Program memory pm hh8 This modifier allows you to use bits 15 through 23 of an address expression as 8 bit relocatable expression This modifier useful for addressing data or code from Flash Program memory 9 5 3 Opcodes For detailed information on the AVR machine instruction set see www atmel com products AVR as implements all the standard AVR opcodes The following table summarizes the AVR opcodes and their arguments Legend r any register Idi register r16 r31 movw even register r0 r2 r28 r30 fmuP register r16 r23 adiw register r24 r26 r28 r30 pointer registers X Y Z base pointer register and displacement YZ disp Z pointer register for ellpm Rd Z immediate value from 0 to 255 immediate value from 0 to 255 n M Relocation impossible immediate value from 0 to 7 Port address value from 0 to 63 in out Port address value from 0 to 31 cbi sbi sbic sbis immediate value from 0 to 63 used in adiw sbiw imm
415. oBlaze sssucscesee 191 line separator MIPS sssesse 203 line separator MSP 430 211 line separator NS32K suusues 218 June separator PJ wisi ebore epe DEDE WR 223 line separator PowerPC susus 226 line separator RL 227 line separator RX ee eee ene ee 230 line separator S890 2 00 eee eee ee eee 231 line separator SCORE 247 line separator BP cese eee 248 line separator ODoi 2 0 eee eee 251 line separator Sparc eee eee eee eee 256 line separator TICE 273 line separator TIC6X uuesess 274 line separator V850 2 cece eee eee 297 line separator MAX 295 line separator SOATER nnne 303 line separator A tormelp ene 305 line separator A80 2 ec eee ee 286 line separator 28000 289 lines starting with 0 005 28 linkers nis oc nent ines ROS WP ee PPS ES EE 18 linker and assembler suusues 33 linkonce directive 0 eee eee eee eee 60 list direollVe iere l debe c iier oe dee cas 61 list directive TIC54X ege erg trm met 269 listing control turning off 65 listing control turning on 61 listing control new page rcrsrecreeres 53 listing control paper size 67 listing control subtitles sssr esesisirssrgric uai 69 listing control title ne 75 listings enabling ue EE EE EE 21 literal directive 24 ge see Re e
416. ocation 33 4 Sections and Relocation 4 1 Background Roughly a section is a range of addresses with no gaps all data in those addresses is treated the same for some particular purpose For example there may be a read only section The linker 1d reads many object files partial programs and combines their contents to form a runnable program When as emits an object file the partial program is assumed to start at address 0 1d assigns the final addresses for the partial program so that different partial programs do not overlap This is actually an oversimplification but it suffices to explain how as uses sections 1d moves blocks of bytes of your program to their run time addresses These blocks slide to their run time addresses as rigid units their length does not change and neither does the order of bytes within them Such a rigid unit is called a section Assigning run time addresses to sections is called relocation It includes the task of adjusting mentions of object file addresses so they refer to the proper run time addresses For the H8 300 and for the Renesas SuperH SH as pads sections if needed to ensure they end on a word sixteen bit boundary An object file written by as has at least three sections any of which may be empty These are named text data and bss sections When it generates COFF or ELF output as can also generate whatever other named sections you specify using the section directive see
417. odifiers when using symbol addresses in TILEPro instruc tion operands The general syntax is the following modifier symbol The following modifiers are supported 1016 hii6 hai6 got got 1016 got hii16 This modifier is used to load the low 16 bits of the symbol s address sign extended to a 32 bit value sign extension allows it to be range checked against signed 16 bit immediate operands without complaint This modifier is used to load the high 16 bits of the symbol s address also sign extended to a 32 bit value hai6 N is identical to hi16 N except if 1016 N is negative it adds one to the hi16 N value This way 1016 and ha16 can be added to create any 32 bit value using auli For example here is how you move an arbitrary 32 bit address into r3 moveli r3 1016 sym auli r3 r3 hai6 sym This modifier is used to load the offset of the GOT entry corresponding to the symbol This modifier is used to load the sign extended low 16 bits of the offset of the GOT entry corresponding to the symbol This modifier is used to load the sign extended high 16 bits of the offset of the GOT entry corresponding to the symbol 284 got hal6 pit tls gd Using as This modifier is like got hi6 but it adds one if got 1016 of the input value is negative This modifier is used for function symbols It causes a procedure linkage table an array of code stubs to be created at the time the shared object
418. oes not overflow A 48 bit symbolic value is constructed by using the following idiom Chapter 9 Machine Dependent Features 279 moveli r0 hw2 last sym shli6insli rO r0 hwi sym shli6insli rO r0 hwO sym bat got This modifier is used to load bits 0 15 of the symbol s offset in the GOT entry corresponding to the symbol bat last got This modifier yields the same value as ba got but it also checks that the value does not overflow hw1 last got This modifier is used to load bits 16 31 of the symbol s offset in the GOT entry corresponding to the symbol and it also checks that the value does not overflow pit This modifier is used for function symbols It causes a procedure linkage table an array of code stubs to be created at the time the shared object is created or linked against together with a global offset table entry The value is a pc relative offset to the corresponding stub code in the procedure linkage table This arrangement causes the run time symbol resolver to be called to look up and set the value of the symbol the first time the function is called at latest depending environment variables It is only safe to leave the symbol unresolved this way if all references are function calls hwO plt This modifier is used to load bits 0 15 of the pc relative address of a plt entry hwi plt This modifier is used to load bits 16 31 of the pc relative address of a plt entry hwi last plt This modifier
419. of size means one of w or 1 and it may be omitted along with the leading colon unless a scale is also specified The use of scale means one of 1 2 4 or 8 and it may always be omitted along with the leading colon The following addressing modes are understood Immediate number Data Register 720 through gr Address Register ap through ar hal is also known as Asp i e the Stack Pointer 4a6 is also known as fp the Frame Pointer Address Register Indirect 20 through a7 Address Register Postincrement 200 through a7 Address Register Predecrement h20 through a7 Indirect Plus Offset apc number Index apc number register size scale The number may be omitted 180 Using as Postindex apc number onumber register size scale The onumber or the register but not both may be omitted Preindex apc number register size scale onumber The number may be omitted Omitting the register produces the Postindex addressing mode Absolute symbol or digits optionally followed by b w or 1 9 23 3 Motorola Syntax The standard Motorola syntax for this chip differs from the syntax already discussed see Section 9 23 2 Syntax page 179 as can accept Motorola syntax for operands even if MIT syntax is used for other operands in the same instructio
420. of symbol to expression This changes symbol s value and type to conform to expression If symbol was flagged as external it remains flagged see Section 5 5 Symbol Attributes page 41 You may set a symbol many times in the same assembly If you set a global symbol the value stored in the object file is the last value stored into it On Z80 set is a real instruction use symbol defl expression instead 7 101 short expressions Short is normally the same as word See Section 7 124 word page 78 In some configurations however short and word generate numbers of different lengths See Chapter 9 Machine Dependencies page 81 7 102 single flonums This directive assembles zero or more flonums separated by commas It has the same effect as float The exact kind of floating point numbers emitted depends on how as is configured See Chapter 9 Machine Dependencies page 81 7 103 size This directive is used to set the size associated with a symbol COFF Version For COFF targets the size directive is only permitted inside def endef pairs It is used like this size expression ELF Version For ELF targets the size directive is used like this size name expression This directive sets the size associated with a symbol name The size in bytes is computed from expression which can make use of label arithmetic This directive is typically used to set the size of function symbols 7 104
421. oint operations Note that by de fault double precision floating point operations are always allowed even with CPU targets that don t have support for these operations construct floats no construct floats The no construct floats option disables the construction of double width floating point constants by loading the two halves of the value into the two single width floating point registers that make up the double width register This feature is useful if the processor support the FR bit in its status register and this bit is known by the programmer to be set This bit prevents the aliasing of the double width register by the single width registers By default construct floats is selected allowing construction of these floating point constants relax branch no relax branch The relax branch option enables the relaxation of out of range branches Any branches whose target cannot be reached directly are converted to a small instruction sequence including an inverse condition branch to the physically next instruction and a jump to the original target is inserted between the two instructions In PIC code the jump will involve further instructions for address calculation The BC1ANY2F BC1ANY2T BC1ANY4F BC1ANYAT BPOSGE32 and BPOSGE64 in structions are excluded from relaxation because they have no complementing Chapter 9 Machine Dependent Features 197 counterparts They could be relaxed with the use of a longer s
422. ol names Chapter 9 Machine Dependent Features 131 9 10 2 4 Guarded Execution as supports the full range of guarded execution directives for each instruction Just append the directive after the instruction proper The directives are T fgg TIR TR TE ee Execute the instruction if flag f0 is true Execute the instruction if flag f0 is false Execute the instruction if flag f1 is true Execute the instruction if flag f1 is false Execute the instruction if both flags f0 and f1 are true Execute the instruction if flag f0 is true and flag f1 is false 9 10 2 5 Register Names You can use the predefined symbols ro through r63 to refer to the D30V registers You can also use sp as an alias for r63 and link as an alias for r62 The accumulators are ad and at The D30V also has predefined symbols for these control registers and status bits psw bpsw pe bpc rpt_c rpt_s rpt_e mod_s mod_e iba f0 f1 f2 f3 f4 f5 f6 f7 S V Processor Status Word Backup Processor Status Word Program Counter Backup Program Counter Repeat Count Repeat Start address Repeat End address Modulo Start address Modulo End address Instruction Break Address Flag 0 Flag 1 Flag 2 Flag 3 Flag 4 Flag 5 Flag 6 Flag 7 Same as flag 4 saturation flag Same as flag 5 overflow flag 132 Using as va Same as flag 6 sticky overflow flag e Same as flag 7 carry borro
423. ompilers as part of jump tables Therefore when as assembles a directive of the form word symi sym2 and the difference between sym1 and sym2 does not fit in 16 bits as creates a secondary jump table immediately before the next label This secondary jump table is preceded by a short jump to the first byte after the secondary table This short jump prevents the flow of control from accidentally falling into the new table Inside the table is a long jump to sym2 The original word contains sym1 minus the address of the long jump to sym2 D If there were several occurrences of word symi sym2 before the secondary jump table all of them are adjusted If there was a word sym3 sym4 that also did not fit in sixteen bits a long jump to sym4 is included in the secondary jump table and the word directives are adjusted to contain sym3 minus the address of the long jump to sym4 and so on for as many entries in the original jump table as necessary 7 125 Deprecated Directives One day these directives won t work They are included for compatibility with older assem blers abort line Chapter 8 Object Attributes 79 8 Object Attributes as assembles source files written for a specific architecture into object files for that architec ture But not all object files are alike Many architectures support incompatible variations For instance floating point arguments might be passed in floating point registers if the
424. on defw expression expression For each expression the value is stored in two bytes ignoring overflow d24 expression expression def24 expression expression For each expression the value is stored in three bytes ignoring overflow d32 expression expression def32 expression expression For each expression the value is stored in four bytes ignoring overflow ds count value defs count value Fill count bytes in the object file with value if value is omitted it defaults to Zero symbol equ expression symbol defl expression These directives set the value of symbol to expression If equ is used it is an error if symbol is already defined Symbols defined with equ are not protected from redefinition 288 Using as set This is a normal instruction on Z80 and not an assembler directive psect name A synonym for See Section 7 99 Section page 69 no second argument should be given 9 46 5 Opcodes In line with common practice Z80 mnemonics are used for both the Z80 and the R800 In many instructions it is possible to use one of the half index registers ixl ixh iyl iyh in stead of an 8 bit general purpose register This yields instructions that are documented on the R800 and undocumented on the Z80 Similarly in f c is documented on the R800 and undocumented on the Z80 The assembler also supports the following undocumented Z80 instructions that have not been adopted
425. on E EE 200 MIPS architecture option 192 MIPS big endian output ssssecrereeres 192 MIPS CPU overide 0 cee eee eee 200 MIPS DSP Release 1 instruction generation OVEITIGG 03 nile rcx e e re Sane EE RATES 202 MIPS DSP Release 2 instruction generation E nescis eive R3 eingasu denen 202 MIPS endianness 0 00 eeeee eee eee 12 MIPS IEEE 754 NaN data encoding selection wv PET 201 MIBPSJISA co sack acts ws pedals psa t Rad 12 MIPS ISA override ssuusueusuesss 199 MIPS line comment character 202 MIPS line separator eseeseeeeeeee 203 MIPS little endian output esses 192 MIPS MCU instruction generation override 202 MIPS MDMX instruction generation override d doops 202 MIPS MIPS 3D instruction generation override Budbewddd tendi a pdt eo Ete tech oe Rok ene 202 MIPS MT instruction generation override 202 MIPS option SSES estes de 201 MIPS processOr 2 21 22 19 elfe EN REENEN Euh 192 IN WEEN 179 mlib directive EC Eed Sege d e ees 270 mlist directive TIOR4N 270 MMIX assembler directive BSPEC 209 MMIX assembler directive BYTE 208 MMIX assembler directive ESPEC 209 MMIX assembler directive GREG 207 MMIX assembler directive IS 207 MMIX assembler directive LOC 207 MMIX assembler directive LOCAL 207 MMIX assembler directive OCTA 208 MMIX assembler dir
426. on code for the instruction For example the lr mnemonic denotes the instruction format RR with the operation code 0x18 The definition of the various mnemonics follows a scheme where the first character usually hint at the type of the instruction a add instruction for example al for add logical 32 bit b branch instruction for example bc for branch on condition c compare or convert instruction for example cr for compare register 32 bit d divide instruction for example dlr devide logical register 64 bit to 32 bit i insert instruction for example ic insert character l load instruction for example Ltr load and test register mv move instruction for example mvc move character m multiply instruction for example mh multiply halfword Chapter 9 Machine Dependent Features 233 n and instruction for example ni and immediate o or instruction for example oc or character sla all shift left single instruction sra srl shift right single instruction st store instruction for example stm store multiple S subtract instruction for example slr subtract logical 32 bit t test or translate instruction of example tm test under mask x exclusive or instruction for example xc exclusive or character Certain characters at the end of the mnemonic may describe a property of the instruction c the instruction uses a 8 bit character operand
427. on 9 42 10 TIC54X Macros page 272 mlib filename filename Load the macro library filename filename must be an archived library BFD ar compatible of text files expected to contain only macro definitions The standard include search path is used mlist mnolist Control whether to include macro and loop block expansions in the listing output Ignored mmregs Define global symbolic names for the c54x registers Supposedly equivalent to executing set directives for each register with its memory mapped value but in reality is provided only for compatibility and does nothing newblock This directive resets any TIC54X local labels currently defined Normal as local labels are unaffected option option list Set listing options Ignored Sblock section name section name name n name n Designate section_name for blocking Blocking guarantees that a section will start on a page boundary 128 words if it would otherwise cross a page bound ary Only initialized sections may be designated with this directive See also See Section 9 42 2 TIC54X Block page 264 Sect section name Define a named initialized section and make it the current section symbol set value symbol equ value Equate a constant value to a symbol which is placed in the symbol table symbol may not be previously defined Space size in bits bes size in bits Reserve the given number of bits in the current section and zero fill t
428. on ere NES ses ERE ESE aeeai es aan ed 22 2 5 include Search Path path 22 2 6 Difference Tables KI 22 2 7 Include Local Symbols 7 22 2 8 Configuring listing output Listing 22 2 9 Assemble in MRI Compatibility Mode MI 24 2 10 Dependency Tracking MD rn eere nnn 25 2 11 Name the Object File Zeg us een ENN ANE repr m beg 25 2 12 Join Data and Text Sections RI 25 2 13 Display Assembly Statistics statistics 25 2 14 Compatible Output traditional format 25 2 15 Announce Version eu 25 2 16 Control Warnings W warn no warn Keier KE EE soc ebenrererer9 eese pede ehaaee ees 26 2 17 Generate Object File in Spite of Errors Z 26 3 Synta E iea eaaa a Ea aa aaa a a aa 27 Jel PreprocessIhg esedonk cece via sade RE ewes Dres aed ems 27 9 2 Whitespace uus s serene Rr A UA Fence ERE RA D UR Ra ern 27 2 9 lommoebhls 2 xx reis atone ien eux reste eA Ud aud eee 21 3A Surber ee eg dd ede be 28 3 5 Statements 29 448 hes eii dea cto nd EREN ER Rd 28 9 0 Constants saec eben end pude gna e RR ca nx ena ada 29 3 6 1 Character Constant 29 K EN WEE 29 3 0 1 2 Characters seed S neni Ee 30 3 6 2 Number Constants rss 0c cece e eee eee 30 3 0 2 1 Integers oec ker Dr eade o Ad REC EP RES 30 0 0 2 2 JBIEDUIIS 4c tou EE 31 3 0 2 3 PIONUMIS eene eterea e R ERE 31 ii Using as 4 Sections and Relocation
429. ong and quad A procedure linkage table entry us generated for the symbol The symbol term is replaced with the address of the PLT entry for the symbol pltoff The pltoff modifier can be used for short long and quad The symbol term is replaced with the offset from the start of the PLT to the address of the symbol tlsgd tlsldm The tlsgd and tlsldm modifier can be used for Jong and quad A tls_index structure for the symbol is added to the GOT The symbol term is replaced with the offset from the start of the GOT to the tls_index structure Chapter 9 Machine Dependent Features 245 Ogotntpoff indntpoff dtpoff Ontpoff The gotntpoff and Gindntpoff modifier can be used for Jong and quad The symbol is added to the static TLS block and the negated offset to the symbol in the static TLS block is added to the GOT For gotntpoff the symbol term is replaced with the offset from the start of the GOT to the GOT slot for indntpoff the symbol term is replaced with the address of the GOT slot The dtpoff modifier can be used for long and quad The symbol term is replaced with the offset of the symbol relative to the start of the TLS block it is contained in The ntpoff modifier can be used for long and quad The symbol term is replaced with the offset of the symbol relative to the TCB pointer For more information about the thread local storage modifiers see the ELF extension documentation ELF Handling For Thre
430. ons any such options will be processed recursively a cdghimns Turn on listings in any of a variety of ways ac omit false conditionals ad omit debugging directives ag include general information like as version and options passed ah include high level source al include assembly am include macro expansions an omit forms processing as include symbols file set the name of the listing file You may combine these options for example use aln for assembly listing without forms processing The file option if used must be the last one By itself a defaults to ahls alternate Begin in alternate macro mode See Section 7 4 a1tmacro page 48 compress debug sections Compress DWARF debug sections using zlib The debug sections are renamed to begin with zdebug and the resulting object file may not be compatible with older linkers and object file utilities nocompress debug sections Do not compress DWARF debug sections This is the default D Ignored This option is accepted for script compatibility with calls to other assemblers debug prefix map old new When assembling files in directory old record debugging information describ ing them as in new instead Using as defsym sym value 8 Define the symbol sym to be value before assembling the input file value must be an integer constant As in C a leading Ox indicates a hexadecimal value and a leading
431. onsequence Some of these may be supported in future releases EBCDIC strings EBCDIC strings are not supported packed binary coded decimal Packed binary coded decimal is not supported This means that the DC P and DCB P pseudo ops are not supported FEQU pseudo op The m68k FEQU pseudo op is not supported NOOBJ pseudo op The m68k NOOBJ pseudo op is not supported OPT branch control options The m68k OPT branch control options B BRS BRB BRL and BRW are ignored as automatically relaxes all branches whether forward or backward to an appropriate size so these options serve no purpose OPT list control options The following m68k OPT list control options are ignored C CEX CL CRE E G I M MEX MC MD X other OPT options The following m68k OPT options are ignored NEST 0 OLD OP P PCO PCR PCS R OPT D option is default The m68k OPT D option is the default unlike the MRI assembler OPT NOD may be used to turn it off XREF pseudo op The m68k XREF pseudo op is ignored debug pseudo op The i960 debug pseudo op is not supported extended pseudo op The i960 extended pseudo op is not supported List pseudo op The various options of the 1960 List pseudo op are not supported optimize pseudo op The 1960 optimize pseudo op is not supported output pseudo op The 1960 output pseudo op is not supported Chapter 2 Command Line Options 25 e setreal pseudo op The i960 setreal pseudo op
432. oo_example stab _page_switch jsr addr foo_example 9 24 4 Assembler Directives The 68HC11 and 68HC12 version of as have the following specific assembler directives relax The relax directive is used by the GNU Compiler to emit a specific relocation to mark a group of instructions for linker relaxation The sequence of instruc tions within the group must be known to the linker so that relaxation can be performed mode mshort nlong mshort double mlong double This directive specifies the ABI It overrides the mshort mlong mshort double and mlong double options far symbol This directive marks the symbol as a far symbol meaning that it uses a call rtc calling convention as opposed to jsr rts During a final link the linker will identify references to the far symbol and will verify the proper calling convention 188 Using as interrupt symbol This directive marks the symbol as an interrupt entry point This information is then used by the debugger to correctly unwind the frame across interrupts xrefb symbol This directive is defined for compatibility with the Specification for Motorola 8 and 16 Bit Assembly Language Input Standard and is ignored 9 24 5 Floating Point Packed decimal P format floating literals are not supported Feel free to add the code The floating point formats generated by directives are these float Single precision floating point con
433. ore a load or 16 bit multiply instruction 9 10 2 Syntax The D30V syntax is based on the syntax in Mitsubishi s D30V architecture manual The differences are detailed below 9 10 2 1 Size Modifiers The D30V version of as uses the instruction names in the D30V Architecture Manual However the names in the manual are sometimes ambiguous There are instruction names that can assemble to a short or long form opcode How does the assembler pick the correct form as will always pick the smallest form if it can When dealing with a symbol that is not defined yet when a line is being assembled it will always use the long form If you need to force the assembler to use either the short or long form of the instruction you can append either s short or 1 long to it For example if you are writing an assembly program and you want to do a branch to a symbol that is defined later in your program you can write bra s foo Objdump and GDB will always append s or 1 to instructions which have both short and long forms 9 10 2 2 Sub Instructions The D30V assembler takes as input a series of instructions either one per line or in the special two per line format described in the next section Some of these instructions will be short form or sub instructions These sub instructions can be packed into a single in struction The assembler will do this automatically It will also detect when it should not pack instructions For
434. orrect processing of interrupts By default generation of the NOP instruction happens automat ically but this command line option disables this behaviour It is then up to the programmer to ensure that interrupts are enabled and disabled correctly md mark the object file as one that requires data to copied from ROM to RAM at execution startup Disabled by default 9 29 2 Syntax 9 29 2 1 Macros The macro syntax used on the MSP 430 is like that described in the MSP 430 Family Assembler Specification Normal as macros should still work Additional built in macros are llo exp Extracts least significant word from 32 bit expression exp lhi exp Extracts most significant word from 32 bit expression exp hlo exp Extracts 3rd word from 64 bit expression exp hhi exp Extracts 4rd word from 64 bit expression exp They normally being used as an immediate source operand mov 1lo 1 r10 mov 1 r10 mov 1hi 1 r10 mov 0 r10 9 29 2 2 Special Characters Cu A semicolon appearing anywhere on a line starts a comment that extends to the end of that line If a 4 appears as the first character of a line then the whole line is treated as a comment but it can also be a logical line number directive see Section 3 3 Comments page 27 or a preprocessor control command see Section 3 1 Preprocessing page 27 212 Using as Multiple statements can appear on the same line provided that they are separat
435. ot want to do this report the bug anyway and send us the entire test case you used e A patch for the bug A patch for the bug does help us if it is a good one But do not omit the necessary information such as the test case on the assumption that a patch is all we need We might see problems with your patch and decide to fix the problem another way or we might not understand it at all Sometimes with a program as complicated as as it is very hard to construct an example that will make the program follow a certain path through the code If you do not send us the example we will not be able to construct one so we will not be able to verify that the bug is fixed And if we cannot understand what bug you are trying to fix or why your patch should be an improvement we will not install it A test case will help us to understand e A guess about what the bug is or what it depends on Such guesses are usually wrong Even we cannot guess right about such things without first using the debugger to find the facts Chapter 11 Acknowledgements 319 11 Acknowledgements If you have contributed to GAS and your name isn t listed here it is not meant as a slight We just don t know about it Send mail to the maintainer and we ll correct the situation Currently the maintainer is Nick Clifton email address nickc redhat com Dean Elsner wrote the original GNU assembler for the VAX Jay Fenlason maintained GAS for a while adding support for G
436. ote GAS and BFD support for the native HPPA object format SOM along with a fairly extensive HPPA testsuite for both SOM and ELF object formats This work was supported by both the Center for Software Science at the University of Utah and Cygnus Support Support for ELF format files has been worked on by Mark Eichin of Cygnus Support original incomplete implementation for SPARC Pete Hoogenboom and Jeff Law at the University of Utah HPPA mainly Michael Meissner of the Open Software Foundation i386 mainly and Ken Raeburn of Cygnus Support sparc and some initial 64 bit support Linas Vepstas added GAS support for the ESA 390 IBM 370 architecture Richard Henderson rewrote the Alpha assembler Klaus Kaempf wrote GAS and BFD support for openVMS Alpha Timothy Wall Michael Hayes and Greg Smart contributed to the various tic flavors David Heine Sterling Augustine Bob Wilson and John Ruttenberg from Tensilica Inc added support for Xtensa processors Several engineers at Cygnus Support have also provided many small bug fixes and con figuration enhancements Jon Beniston added support for the Lattice Mico32 architecture Many others have contributed large or small bugfixes and enhancements If you have contributed significant work and are not mentioned on this list and want to be let us know Some of the history has been lost we are not intentionally leaving anyone out Appendix A GNU Free Documentation License 321
437. ou may use the base size default 16 option to tell as to default to using the 16 bit value In this case a0 d0 is equivalent to 4a09 4d0 w You may use the base size default 32 option to restore the default behaviour disp size default 16 disp size default 32 If you use an addressing mode with a displacement and the value of the dis placement is not known as will normally assume that the value is 32 bits For example if the symbol disp has not been defined as will assemble the ad dressing mode Za0 disp d0 as though disp is a 32 bit value You may use the disp size default 16 option to tell as to instead assume that the displacement is 16 bits In this case as will assemble a0 disp d0 as though disp is a 16 bit value You may use the disp size default 32 option to restore the default behaviour pcrel Always keep branches PC relative In the M680x0 architecture all branches are defined as PC relative However on some processors they are limited to word displacements maximum When as needs a long branch that is not available it normally emits an absolute jump instead This option disables this substitu tion When this option is given and no long branches are available only word branches will be emitted An error message will be generated if a word branch cannot reach its target This option has no effect on 68020 and other processors that have long bra
438. ou use the size suffixes as issues a warning when the suffix and the register size do not match Chapter 9 Machine Dependent Features 137 9 13 HPPA Dependent Features 9 13 1 Notes As a back end for GNU CC as has been throughly tested and should work extremely well We have tested it only minimally on hand written assembly code and no one has tested it much on the assembly output from the HP compilers The format of the debugging sections has changed since the original as port version 1 3X was released therefore you must rebuild all HPPA objects and libraries with the new assembler so that you can debug the final executable The HPPA as port generates a small subset of the relocations available in the SOM and ELF object file formats Additional relocation support will be added as it becomes necessary 9 13 2 Options as has no machine dependent command line options for the HPPA 9 13 3 Syntax The assembler syntax closely follows the HPPA instruction set reference manual assembler directives and general syntax closely follow the HPPA assembly language reference manual with a few noteworthy differences First a colon may immediately follow a label definition This is simply for compatibility with how most assembly language programmers write code Some obscure expression parsing problems may affect hand written code which uses the spop instructions or code which makes significant use of the line separator as is much le
439. pecific applications replace noreplace Enables or disables the optimization of procedure calls both at assemblage and at link time These options are only available for VMS targets and replace is the default See section 1 4 1 of the OpenVMS Linker Utility Manual g This option is used when the compiler generates debug information When gcc is using mips tfile to generate debug information for ECOFF local labels must be passed through to the object file Otherwise this option has no effect Gsize A local common symbol larger than size is placed in bss while smaller symbols are placed in sbss F 32addr These options are ignored for backward compatibility Chapter 9 Machine Dependent Features 85 9 2 3 Syntax The assembler syntax closely follow the Alpha Reference Manual assembler directives and general syntax closely follow the OSF 1 and OpenVMS syntax with a few differences for ELF 9 2 3 1 Special Characters is the line comment character Note that if is the first character on a line then it can also be a logical line number directive see Section 3 3 Comments page 27 or a preprocessor control command see Section 3 1 Preprocessing page 27 can be used instead of a newline to separate statements 9 2 3 2 Register Names The 32 integer registers are referred to as n or rn In addition registers 15 28 29 and 30 may be referred to by the symbols fp at
440. pq store quad integer and pop stack instructions Register to register operations should not use instruction mnemonic suffixes fstl Ast st 1 will give a warning and be assembled as if you wrote fst 4st st 1 since all register to register operations use 80 bit floating point operands Contrast this with fstl 4st mem which converts ker from 80 bit to 64 bit floating point format then stores the result in the 4 byte location mem 9 15 11 Intel s MMX and AMD s 3DNow SIMD Operations as supports Intel s MMX instruction set SIMD instructions for integer data available on Intel s Pentium MMX processors and Pentium II processors AMD s K6 and K6 2 proces sors Cyrix M2 processor and probably others It also supports AMD s 3DNow instruction set SIMD instructions for 32 bit floating point data available on AMD s K6 2 processor and possibly others in the future Currently as does not support Intel s floating point SIMD Katmai KNI The eight 64 bit MMX operands also used by 3DNow are called mmO mm Amm They contain eight 8 bit integers four 16 bit integers two 32 bit integers one 64 bit integer or two 32 bit floating point values The MMX registers cannot be used at the same time as the floating point stack See Intel and AMD documentation keeping in mind that the operand order in instruc tions is reversed from the Intel syntax Chapter 9 Machine Dependent Feat
441. profiler This directive instructs assembler to add new profile entry to the object file 9 29 5 Opcodes as implements all the standard MSP 430 opcodes No additional pseudo instructions are needed on this family For information on the 430 machine instruction set see MSP430 User s Manual docu ment slau049d Texas Instrument Inc 9 29 6 Profiling Capability It is a performance hit to use gcc s profiling approach for this tiny target Even more jtag hardware facility does not perform any profiling functions However we ve got gdb s built in simulator where we can do anything We define new section profiler which holds all profiling information We define new pseudo operation profiler which will instruct assembler to add new profile entry to the object file Profile should take place at the present address Pseudo operation format profiler flags function to profile cycle corrector extra where flags is a combination of the following characters S function entry x function exit i function is in init section 214 Using as f function is in fini section 1 library call c libc standard call d stack value demand I interrupt service routine P prologue start p prologue end E epilogue start e epilogue end j long jump sjlj unwind a an arbitrary code fragment t extra parameter saved a constant value like frame size function_to_profile a function address cycle_corrector a valu
442. pter 9 Machine Dependent Features 257 In V9 there are 4 sets of floating point condition codes which are referred to as 4fccn Several special privileged and non privileged registers exist e The V9 address space identifier register is referred to as asi e The V9 restorable windows register is referred to as canrestore e The V9 savable windows register is referred to as 4cansave e The V9 clean windows register is referred to as Acleanwin e The V9 current window pointer register is referred to as Acwp e The floating point queue register is referred to as to e The V8 co processor queue register is referred to as Acq e The floating point status register is referred to as Afsr e The other windows register is referred to as hotherwin e The V9 program counter register is referred to as Apc e The V9 next program counter register is referred to as Anpc e The V9 processor interrupt level register is referred to as Apil e The V9 processor state register is referred to as 4pstate e The trap base address register is referred to as tba e The V9 tick register is referred to as tick e The V9 trap level is referred to as EL e The V9 trap program counter is referred to as htpc e The V9 trap next program counter is referred to as Atnpc e The V9 trap state is referred to as 4tstate e The V9 trap type is referred to as rt e The V9 condition codes is referred to as ccr e The
443. ptimization is done without adding instructions that could in crease the execution time of the program If there are density instructions in the code preceding a target the assembler can change the target alignment by widening some of those instructions to the equivalent 24 bit instructions Extra bytes of padding can be in serted immediately following unconditional jump and return instructions This approach is usually successful in aligning many but not all branch targets The LOOP family of instructions must be aligned such that the first instruction in the loop body does not cross an instruction fetch boundary e g with a 32 bit fetch width a LOOP instruction must be on either a 1 or 2 mod 4 byte boundary The assembler knows about this restriction and inserts the minimal number of 2 or 3 byte no op instructions to satisfy it When no op instructions are added any label immediately preceding the original loop will be moved in order to refer to the loop instruction not the newly generated no op instruction To preserve binary compatibility across processors with different fetch widths the assembler conservatively assumes a 32 bit fetch width when aligning LOOP instructions except if the first instruction in the loop is a 64 bit instruction Previous versions of the assembler automatically aligned ENTRY instructions to 4 byte boundaries but that alignment is now the programmer s responsibility 9 52 4 Xtensa Relaxation When an inst
444. ption selects the core processor variant EB EL Select either big endian EB or little endian EL output The following options are available when as is configured for the ARM processor family mcpu processor extension Specify which ARM processor variant is the target march architecture extension Specify which ARM architecture variant is used by the target mfpu floating point format Select which Floating Point architecture is the target mfloat abi abi Select which floating point ABI is in use mthumb Enable Thumb only instruction decoding mapcs 32 mapcs 26 mapcs float mapcs reentrant Select which procedure calling convention is in use EB EL Select either big endian EB or little endian EL output mthumb interwork Specify that the code has been generated with interworking between Thumb and ARM code in mind k Specify that PIC code has been generated See Section 9 6 1 Blackfin Options page 114 for the options available when as is configured for the Blackfin processor family See the info pages for documentation of the CRIS specific options The following options are available when as is configured for a D10V processor Chapter 1 Overview 9 0 Optimize output by parallelizing instructions The following options are available when as is configured for a D30V processor 0 Optimize output by parallelizing instructions n Warn when nops are generated N Warn when a
445. ptions are only available with the ELF object file format and require that the necessary BFD support has been included on a 31 bit platform you must add enable 64 bit bfd on the call to the configure script to enable 64 bit usage and use s390x as target platform mesa mzarch Select the architecture mode either the Enterprise System Architecture esa mode or the z Architecture mode zarch The 64 bit instructions are only available with the z Architecture mode The combination of m64 and mesa results in a warning message march CPU This option specifies the target processor The following processor names are recognized g5 g6 z900 z990 z9 109 z9 ec z10 and z196 Assembling an instruction that is not supported on the target processor results in an error message Do not specify g5 or g6 with mzarch mregnames Allow symbolic names for registers mno regnames Do not allow symbolic names for registers mwarn areg zero Warn whenever the operand for a base or index register has been specified but evaluates to zero This can indicate the misuse of general purpose register 0 as an address register 9 37 2 Special Characters is the line comment character If a appears as the first character of a line then the whole line is treated as a comment but in this case the line could also be a logical line number directive see Section 3 3 Comments page 27 or a preprocessor control command see S
446. quested also Use the ag option to print a first section with general assembly information like as version switches passed or time stamp Use the ac option to omit false conditionals from a listing Any lines which are not assembled because of a false if or ifdef or any other conditional or a true if followed by an else will be omitted from the listing Use the ad option to omit debugging directives from the listing Once you have specified one of these options you can further control listing output and its appearance using the directives list nolist psize eject title and sbttl The an option turns off all forms processing If you do not request listing output with one of the a options the listing control directives have no effect The letters after a may be combined into one option e g aln Note if the assembler source is coming from the standard input e g because it is being created by gcc and the pipe command line switch is being used then the listing will not contain any comments or preprocessor directives This is because the listing code buffers input source lines from stdin only after they have been preprocessed by the assembler This reduces memory usage and makes the code more efficient 2 2 alternate Begin in alternate macro mode see Section 7 4 altmacro page 48 22 Using as 2 3 D This option has no effect whatsoever b
447. r 9 Machine Dependent Features 183 dbXX fjXX bNXs oof jmp foo oof The full family of pseudo operations covered here is dbhi dbls dbcc dbcs dbne dbeq due dbvs dbpl dbmi dbge dblt dbgt dble dbf dbra dbt Motorola dbXX instructions allow word displacements only When a word displacement is sufficient each of these pseudo operations expands to the cor responding Motorola instruction When a word displacement is not sufficient and long branches are available when the source reads dbXX foo as emits dbXX ool bras oo2 ooi bral foo 002 If however long branches are not available and the pcrel option is not given as emits dbXX ooi bras oo2 ooi jmp foo 002 This family includes fjne fjeq fjge fjlt fjgt fjle fjf fjt fjgl fjgle fjnge fjngl fjngle fjngt fjnle fjnlt fjoge fjogl fjogt fjole fjolt fjor fjseq fjsf fjsne fjst fjueq fjuge fjugt fjule fjult fjun Each of these pseudo operations always expands to a single Motorola coproces sor branch instruction word or long All Motorola coprocessor branch instruc tions allow both word and long displacements 9 23 6 2 Special Characters Line comments are introduced by the character appearing anywhere on a line unless the bitwise or command line option has been specified An asterisk as the first character on a line marks the start of a line comment as well A hash character as the first character on a l
448. r has a slightly lower precedence than logical and In short it s only meaningful to add or subtract the offsets in an address you can only have a defined section in one of the two arguments Chapter 7 Assembler Directives 47 7 Assembler Directives All assembler directives have names that begin with a period The rest of the name is letters usually in lower case This chapter discusses directives that are available regardless of the target machine configuration for the GNU assembler Some machine configurations provide additional di rectives See Chapter 9 Machine Dependencies page 81 7 1 abort This directive stops the assembly immediately It is for compatibility with other assemblers The original idea was that the assembly language source would be piped into the assembler If the sender of the source quit it could use this directive tells as to quit also One day abort will not be supported 7 2 ABORT COFF When producing COFF output as accepts this directive as a synonym for abort 7 3 align abs expr abs expr abs expr Pad the location counter in the current subsection to a particular storage boundary The first expression which must be absolute is the alignment required as described below The second expression also absolute gives the fill value to be stored in the padding bytes It and the comma may be omitted If it is omitted the padding bytes are normally zero However on som
449. rand Modifiers The assembler supports several modifiers when using symbol addresses in 68HC11 and 68HC12 instruction operands The general syntax is the following modifier symbol addr This modifier indicates to the assembler and linker to use the 16 bit physical address corresponding to the symbol This is intended to be used on memory window systems to map a symbol in the memory bank window If the symbol is in a memory expansion part the physical address corresponds to the symbol address within the memory bank window If the symbol is not in a memory ex pansion part this is the symbol address using or not using the addr modifier has no effect in that case page This modifier indicates to use the memory page number corresponding to the symbol If the symbol is in a memory expansion part its page number is computed by the linker as a number used to map the page containing the symbol in the memory bank window If the symbol is not in a memory expansion part the page number is 0 Ahi This modifier indicates to use the 8 bit high part of the physical address of the symbol hlo This modifier indicates to use the 8 bit low part of the physical address of the symbol For example a 68HC12 call to a function foo_example stored in memory expansion part could be written as follows call Aaddr foo example page foo_example and this is equivalent to call foo_example And for 68HC11 it could be written as follows ldab page f
450. rce code m4byte align Marks the generated objecy file as supporting a maximum 32 bits of alignment for variables defined in the source code This is the default 9 49 2 Syntax Chapter 9 Machine Dependent Features 297 9 49 2 1 Special Characters is the line comment character If a appears as the first character of a line the whole line is treated as a comment but in this case the line can also be a logical line number directive see Section 3 3 Comments page 27 or a preprocessor control command see Section 3 1 Preprocessing page 27 Two dashes can also be used to start a line comment The character can be used to separate statements on the same line 9 49 2 2 Register Names as supports the following names for registers general register 0 r0 zero general register 1 rl general register 2 r2 hp general register 3 r3 sp general register 4 r4 gp general register 5 rd tp general register 6 r6 general register 7 rd general register 8 r8 general register 9 r9 general register 10 r10 general register 11 rll general register 12 r12 general register 13 r13 general register 14 r14 298 general register 15 r15 general register 16 r16 general register 17 r17 general register 18 r18 general register 19 r19 general register 20 r20 general register 21 r21 general register 22 r22 general register 23 r23 general register
451. re created automatically before ENTRY instructions and manually after literal position directives see Section 9 52 5 5 literal position page 313 If there are no preceding ENTRY instructions explicit literal position directives must be used to place the text section literal pools otherwise as will report an error When literals are placed in separate sections the literal section names are derived from the names of the sections where the literals are defined T he base literal section names are literal for PC relative mode L32R instructions and 1it4 for absolute mode L32R in structions see Section 9 52 5 7 absolute literals page 314 These base names are used for literals defined in the default text section For literals defined in other sections or within the scope of a literal prefix directive see Section 9 52 5 6 literal prefix page 314 the following rules determine the literal section name 1 If the current section is a member of a section group the literal section name includes the group name as a suffix to the base literal or lit4 name with a period to separate the base name and group name The literal section is also made a member of the group 2 If the current section name or literal prefix value begins with gnu linkonce kind the literal section name is formed by replacing kind with the base literal or lit4 name For example for literals defined in a section named gnu linkonce t func the literal
452. registers including lr which indicates the return address must be located in the same locations relative to the frame pointer The fnstart see fnstart pseudo op page 101 pseudo op appears immediately before the first instruction of the function while the fnend see fnend pseudo op page 101 pseudo op appears immediately after the last instruction of the function These pseudo ops specify the range of the function Only the order of the other pseudos ops e g setfp or pad matters their exact locations are irrelevant In the example above the compiler emits the pseudo ops with particular instructions That makes it easier to understand the code but it is not required for correctness It would work just as well to emit all of the pseudo ops other than fnend in the same order but immediately after fnstart The save see save pseudo op page 102 pseudo op indicates registers that have been saved to the stack so that they can be restored before the function returns The argument to the save pseudo op is a list of registers to save If a register is callee saved as specified by the ABI and is modified by the function you are writing then your code must save Chapter 9 Machine Dependent Features 107 the value before it is modified and restore the original value before the function returns If an exception is thrown the run time library restores the values of these registers from their locations on the stack before
453. requests that all operations including nonmemory reference operations ap pearing prior to the membar must have been performed and the effects of any excep tions become visible before any instructions after the membar may be initiated This corresponds to membar cmask field bit 2 MemIssue requests that all memory reference operations appearing prior to the membar must have been performed before any memory operation after the membar may be initiated This corresponds to membar cmask field bit 1 Lookaside requests that a store appearing prior to the membar must complete before any load following the membar referencing the same address can be initiated This corresponds to membar cmask field bit 0 StoreStore defines that the effects of all stores appearing prior to the membar in struction must be visible to all processors before the effect of any stores following the membar Equivalent to the deprecated stbar instruction This corresponds to membar mmask field bit 3 LoadStore defines all loads appearing prior to the membar instruction must have been performed before the effect of any stores following the membar is visible to any other processor This corresponds to membar mmask field bit 2 StoreLoad defines that the effects of all stores appearing prior to the membar in struction must be visible to all processors before loads following the membar may be performed This corresponds to membar mmask field bit 1
454. rights have been terminated and not permanently reinstated receipt of a copy of some or all of the same material does not give you any rights to use it Appendix A GNU Free Documentation License 327 10 FUTURE REVISIONS OF THIS LICENSE 11 The Free Software Foundation may publish new revised versions of the GNU Free Documentation License from time to time Such new versions will be similar in spirit to the present version but may differ in detail to address new problems or concerns See http www gnu org copyleft Each version of the License is given a distinguishing version number If the Document specifies that a particular numbered version of this License or any later version applies to it you have the option of following the terms and conditions either of that specified version or of any later version that has been published not as a draft by the Free Software Foundation If the Document does not specify a version number of this License you may choose any version ever published not as a draft by the Free Software Foundation If the Document specifies that a proxy can decide which future versions of this License can be used that proxy s public statement of acceptance of a version permanently authorizes you to choose that version for the Document RELICENSING Massive Multiauthor Collaboration Site or MMC Site means any World Wide Web server that publishes copyrightable works and also provides prominent fa
455. rmyl6 305 3byte directive AR 91 3DNOwWF 3380 s get iac PERENNI 152 3DNow x86 64 Li eitis eil p eit PE REA RR 152 4 430 Support 12 ee BEREIT Rn SI RR 211 4byte directive ARC eee eee eee 91 4byte directive Nios H 216 8 8byte directive Nios H 216 A SS OUb ide Leese leet eet eeee MPH IG E 18 a out symbol attributes 000 42 A_DIR environment variable TIC54X 264 AArch64 floating point IEEE suse 83 AArch64 immediate character 82 A Arch64 line comment character 82 A Arch64 line separator sssseesse esses 82 AArch64 machine directives sisuerenee 83 AArch64 opcodes 200 e cece eee eee ees 83 AArch64 options none 82 A Arch64 register namen 82 AArch64 relocations seen 82 AArch64 support 82 ABI options SH64 005 2511 abort directive iis see tek inii wed per 47 ABORT directe E AS Index absolute Sectlon seisererixm RR ERREUR absolute literals directive ADDI instructions relaxation addition permitted arguments lee EE addresses format of addressing modes DIN addressing modes DOUM addressing modes H8 200 addressing modes M tt addressing modes M68HC11 addressing modes SP addressing modes Sei addressing modes XGATE sssssss addressing modes 28000 ADR reg label pseudo op ARM
456. rns the floating point hyperbolic sine of expr sqrt expr Returns the floating point square root of expr tan expr Returns the floating point tangent of expr tanh expr Returns the floating point hyperbolic tangent of expr trunc expr Returns the integer value of expr truncated towards zero as floating point 9 42 8 Extended Addressing The LDX pseudo op is provided for loading the extended addressing bits of a label or address For example if an address _label resides in extended program memory the value of Label may be loaded as follows ldx label 16 a loads extended bits of label or label a loads lower 16 bits of label bacc a full address is in accumulator A 9 42 9 Directives align size even Align the section program counter on the next boundary based on size size may be any power of 2 even is equivalent to align with a size of 2 1 Align SPC to word boundary 2 Align SPC to longword boundary same as even 128 Align SPC to page boundary asg string name Assign name the string string String replacement is performed on string before assignment eval string name Evaluate the contents of string string and assign the result as a string to the subsym name String replacement is performed on string before assignment bes symbol size blocking flag alignment flagll Reserve space for symbol in the bss section size is in words If present block ing flag indicates the allocated
457. rocessor instructions TSTSET and WRTLCK mmxps mno mxps Enable or disable the use of the MFPS and MTPS instructions mspl mno spl Enable or disable the use of the SPL instruction Enable or disable the use of the microcode instructions LDUB MED and XFC 9 32 1 3 CPU Model Options These options enable the instruction set extensions supported by a particular CPU and disables all other extensions mka11 KA11 CPU Base line instruction set only mkb11 KB11 CPU Enable extended instruction set and SPL mkdita KD11 A CPU Enable limited extended instruction set mkdiib KD11 B CPU Base line instruction set only mkdiid KD11 D CPU Base line instruction set only mkdite KDI11 E CPU Enable extended instruction set MFPS and MTPS mkdiif mkdiih mkdiiq KD11 F KD11 H or KD11 Q CPU Enable limited extended instruction set MFPS and MTPS mkdiilk KD11 K CPU Enable extended instruction set LDUB MED MFPS MFPT MTPS and XFC mkdiiz KD11 Z CPU Enable extended instruction set CSM MFPS MFPT MTPS and SPL mf11 F11 CPU Enable extended instruction set MFPS MFPT and MTPS mjit J11 CPU Enable extended instruction set CSM MFPS MFPT MTPS SPL TSTSET and WRTLCK mti11 T11 CPU Enable limited extended instruction set MFPS and MTPS 9 32 1 4 Machine Model Options These options enable the instruction set extensions supported by a particular machine model and disables all other exte
458. rsonality routine and its encoding encoding must be a con stant determining how the personality should be encoded If it is 255 DW EH PE omit second argument is not present otherwise second argument should be a constant or a sym bol name When using indirect encodings the symbol provided should be the location where personality can be loaded from not the personality routine itself The default after cfi startproc is cfi personality Oxff no personality routine 7 15 cfi lsda encoding exp cfi_lsda defines LSDA and its encoding encoding must be a constant determining how the LSDA should be encoded If it is 255 DW ER PE omit second argument is not present otherwise second argument should be a constant or a symbol name The default after cfi_ startproc is cfi_lsda Oxff no LSDA 7 16 cfi def cfa register offset cfi def cfa defines a rule for computing CFA as take address from register and add offset to it Chapter 7 Assembler Directives 51 7 17 cfi def cfa register register cfi def cfa register modifies a rule for computing CFA From now on register will be used instead of the old one Offset remains the same 7 18 cfi def cfa offset offset cfi def cfa offset modifies a rule for computing CFA Register remains the same but offset is new Note that it is the absolute offset that will be added to a defined register to compute CFA address 7 19 cfi adjust cfa offset offset Same as cfi def cfa of
459. ruction operand is outside the range allowed for that particular instruction field as can transform the code to use a functionally equivalent instruction or sequence of instructions This process is known as relaxation This is typically done for branch instructions because the distance of the branch targets is not known until assembly time The Xtensa assembler offers branch relaxation and also extends this concept to function calls MOVI instructions and other instructions with immediate fields 9 52 4 1 Conditional Branch Relaxation When the target of a branch is too far away from the branch itself i e when the offset from the branch to the target is too large to fit in the immediate field of the branch instruction it may be necessary to replace the branch with a branch around a jump For example beqz a2 L may result in bnez n a2 M jL M The BNEZ N instruction would be used in this example only if the density option is available Otherwise BNEZ would be used This relaxation works well because the unconditional jump instruction has a much larger offset range than the various conditional branches However an error will occur if a branch target is beyond the range of a jump instruction as cannot relax unconditional jumps Similarly an error will occur if the original input contains an unconditional jump to a target that is out of range Branch relaxation is enabled by default It can be disabled by using underscore prefixes see
460. rve the Title of such a section when you modify the Document means that it remains a section Entitled XYZ according to this definition The Document may include Warranty Disclaimers next to the notice which states that this License applies to the Document These Warranty Disclaimers are considered to be included by reference in this License but only as regards disclaiming warranties any other implication that these Warranty Disclaimers may have is void and has no effect on the meaning of this License VERBATIM COPYING Appendix A GNU Free Documentation License 323 You may copy and distribute the Document in any medium either commercially or noncommercially provided that this License the copyright notices and the license notice saying this License applies to the Document are reproduced in all copies and that you add no other conditions whatsoever to those of this License You may not use technical measures to obstruct or control the reading or further copying of the copies you make or distribute However you may accept compensation in exchange for copies If you distribute a large enough number of copies you must also follow the conditions in section 3 You may also lend copies under the same conditions stated above and you may publicly display copies 3 COPYING IN QUANTITY If you publish printed copies or copies in media that commonly have printed covers of the Document numbering more than 100 and the Document s lice
461. s 110 9 5 3 Opcodes i isis EE EE 111 9 6 Blackfin Dependent Features 114 9 0 1 breng ENN EEN EE Reesen ENEE en e bte 114 ee ee ee ELI DIE an 114 9 6 3 Directives EE ke a e aset Pee ERR ehe cie kd 116 9 7 CRI16 Dependent Features 118 9 7 1 CR16 Operand QualifietS lt i srrereriieriiseree nian kasians 118 9 7 2 CRIG6 Syntax dccem heceonienandias RR RID 119 9 7 2 1 Special Character 119 9 8 CRIS Dependent Features 120 9 8 1 Command line Option 120 9 8 2 Instruction expansion 00 e eee eee eee eee eee 121 9 8 3 SYMONS eieae p a aoa EE EEEa SC 121 GSA SEN gie eiert ee Eden Poe Ea E REA 122 9 8 4 1 Special Characters ssssssseeeeeeeeeee 122 9 8 4 2 Symbols in position independent code 122 9 8 4 3 Register EE 123 9 8 4 4 Assembler Directive 123 9 9 D10V Dependent Features 0 0 cece eee eee ene 125 9 9 1 DIOV Options 22er a trice S Lewd nel Wace a 125 9 9 2 Synta ss ee EE NR AREE SPODEUE RP E 125 9 9 2 1 Size Modibers cece eee eee eee 125 9 9 2 2 Sub Instructions rara saagad eee 125 9 9 2 3 Special Characters 0 0 0 0 0 126 9 9 2 4 Register Name 127 Using as 9 9 2 5 Addressing Mode 127 9 9 26 eWORD Mode 128 9 9 3 Floating Point 2 cedet rr he E PER EPA at esed 128 9 94 Opcodes iiic eere RRRRRRUHEP ED DIDA RE ERG E 128 9 10 D30V Dependent Features 0 cece eee eee 129 9 10 D30V OptiolS s cense
462. s page 29 separated by commas It assembles each string with no automatic trailing zero byte into consecutive addresses 7 6 asciz string OTA asciz is just like ascii but each string is followed by a zero byte The z in asciz stands for zero 7 7 balign wl abs expr abs expr abs expr Pad the location counter in the current subsection to a particular storage boundary The first expression which must be absolute is the alignment request in bytes For example balign 8 advances the location counter until it is a multiple of 8 If the location counter is already a multiple of 8 no change is needed The second expression also absolute gives the fill value to be stored in the padding bytes It and the comma may be omitted If it is omitted the padding bytes are normally zero However on some systems if the section is marked as containing code and the fill value is omitted the space is filled with no op instructions The third expression is also absolute and is also optional If it is present it is the maximum number of bytes that should be skipped by this alignment directive If doing the alignment would require skipping more bytes than the specified maximum then the Chapter 7 Assembler Directives 49 alignment is not done at all You can omit the fill value the second argument entirely by simply using two commas after the required alignment this can be useful if you want the alignmen
463. s enabling 21 assigning values to symbols 39 54 at register MIR esce eR re hs 198 atmp directive 1800 cese erre eere 157 att syntax pseudo op i386 00 147 att syntax pseudo op HD D4 147 attributes symbol 2c onere we bales Fn 41 auxiliary attributes COFF symbols 42 auxiliary symbol information COFF 53 AVR line comment character 109 AVR line separator 200 cece eee eee 109 AVR modifters 000 cece eee eee eee 110 AVR opcode summar cess eee 111 AVR options none 108 AVR register games 110 AVR Support cheer erinit an ERR a 108 B backslash NX crees idn nea Gel ER 30 backspace Nb sere tegen D REPEAT 29 balign directive ss clic e e Re ek es 48 balignl directive cce rere ers pee 49 balignw directive eorr ener e eee geed 49 bes directive TICBAX 270 big endian output MIPS 0 12 big endian output BI 10 big endian output MS 192 big endian output los 274 BIGHUIMNS y 2 ts ease ad dawns EVER PUDE 31 binary constants TIC54X sssuesss 264 binary files including 0 58 binary EE 30 bit names A 64 0 0 cece eee eee eee 164 bitfields not supported on VAX 295 Blackfin directives 0 e cece ee ee 116 Blackfin options Done 114 Blackfin support e fas er RR pres 114 Blackfin Syr ax nce errem eee pe ER pees 114 gps pm 291 BM
464. s 32 bit SHcompact Note that the mode pseudo op is not permitted if the ISA is not specified on the command line abi 32 abi 64 Specify the default ABI If the ISA is specified and the ABI is not the default ABI depends on the ISA with SHmedia defaulting to 64 bit and SHcompact defaulting to 32 bit Note that the abi pseudo op is not permitted if the ABI is not specified on the command line When the ABI is specified on the command line any abi pseudo ops in the source must match it shcompact const crange Emit code range descriptors for constants in SHcompact code sections no mix Disallow SHmedia code in the same section as constants and SHcompact code no expand Do not expand MOVI PT PTA or PTB instructions expand pt32 With abi 64 expand PT PTA and PTB instructions to 32 bits only h tick hex Support H 00 style hex constants in addition to 0x00 style 9 40 2 Syntax 9 40 2 1 Special Characters 1 is the line comment character If a 4 appears as the first character of a line then the whole line is treated as a comment but in this case the line could also be a logical line number directive see Section 3 3 Comments page 27 or a preprocessor control command see Section 3 1 Preprocessing page 27 252 Using as You can use instead of a newline to separate statements Since has no special meaning you may use it in symbol names 9 40 2 2 Register Names You can use the prede
465. s for the H8 300H variant and also make int emit 32 bit numbers rather than the usual 16 bit for the H8 300 family h8300s Recognize and emit additional instructions for the H8S variant and also make int emit 32 bit numbers rather than the usual 16 bit for the H8 300 family h8300hn Recognize and emit additional instructions for the H8 300H variant in normal mode and also make int emit 32 bit numbers rather than the usual 16 bit for the H8 300 family h8300sn Recognize and emit additional instructions for the H8S variant in normal mode and also make int emit 32 bit numbers rather than the usual 16 bit for the H8 300 family On the H8 300 family including the H8 300H word directives generate 16 bit num bers 9 12 5 Opcodes For detailed information on the H8 300 machine instruction set see H8 300 Series Program ming Manual For information specific to the H8 300H see H8 300H Series Programming Manual Renesas as implements all the standard H8 300 opcodes No additional pseudo instructions are needed on this family Four H8 300 instructions add cmp mov sub are defined with variants using the suffixes b w and 1 to specify the size of a memory operand as supports these suffixes but does not require them since one of the operands is always a register as can deduce the correct size For example since rO refers to a 16 bit register mov r0 foo is equivalent to mov w r0 foo If y
466. s is the same as though the source code were inst O rl r2 You use OPI IMM IMPLIED by bitwise ORing it with SYNTAX 20P For example defining 64 bit multiplier with immediate operands extInstruction mp64 0x14 0xO0 SUFFIX COND SUFFIX FLAG SYNTAX 30P OP1 MUST BE IMM The above specifies an extension instruction called mp64 which has 3 operands sets the flags can be used with a condition code for which the first operand is an immediate Equivalent to discarding the result of the operation extInstruction mul164 0x14 0x00 SUFFIX COND SYNTAX 20P 0P1 IMM IMPLIED This describes a 2 operand instruction with an implicit first immediate operand The result of this operation would be discarded 94 Using as half expressions PODD long expressions TODO option arc arc5 arc6 arc7 arc8 The option directive must be followed by the desired core version Again arc is an alias for arc6 Note the option directive overrides the command line option marc a warn ing is emitted when the version is not consistent between the two even for the implicit default core version arc6 short expressions TODO word expressions TODO 9 3 5 Opcodes For information on the ARC instruction set see ARC Programmers Reference Manual ARC International www arc com Chapter 9 Machine Dependent Features 95 9 4 ARM Dependent Features 9 4 1 Options mcpu processor extension This option specifies the targ
467. s not include details on any machine s instruction set For details on that subject see the hardware manufacturer s manual 82 Using as 9 1 AArch64 Dependent Features 9 1 1 Options EB This option specifies that the output generated by the assembler should be marked as being encoded for a big endian processor EL This option specifies that the output generated by the assembler should be marked as being encoded for a little endian processor mabi abi Specify which ABI the source code uses The recognized arguments are ilp32 and 1p64 which decides the generated object file in ELF32 and ELF64 format respectively The default is 1p64 9 1 2 Syntax 9 1 2 1 Special Characters The presence of a on a line indicates the start of a comment that extends to the end of the current line If a appears as the first character of a line the whole line is treated as a comment The character can be used instead of a newline to separate statements The can be optionally used to indicate immediate operands 9 1 2 2 Register Names Please refer to the section 4 4 Register Names of ARMv8 Instruction Set Overview which is available at http infocenter arm com 9 1 2 3 Relocations Relocations for MOVZ and MOVK instructions can be generated by prefixing the label with abs_g2 etc For example to load the 48 bit absolute address of foo into x0 movz x0 abs_g2 foo bits 32
468. s specific to these formats are not yet documented 9 2 2 Options mcpu This option specifies the target processor If an attempt is made to assemble an instruction which will not execute on the target processor the assembler may either expand the instruction as a macro or issue an error message This option is equivalent to the arch directive The following processor names are recognized 21064 21064a 21066 21068 21164 21164a 21164pc 21264 21264a 21264b ev4 ev5 1ca45 ev5 ev56 pca56 ev6 ev67 ev68 The special name all may be used to allow the assembler to accept instructions valid for any Alpha processor In order to support existing practice in OSF 1 with respect to arch and exist ing practice within MILO the Linux ARC bootloader the numbered processor names e g 21064 enable the processor specific PALcode instructions while the electro vlasic names e g ev4 do not mdebug no mdebug Enables or disables the generation of mdebug encapsulation for stabs directives and procedure descriptors The default is to automatically enable mdebug when the first stabs directive is seen relax This option forces all relocations to be put into the object file instead of saving space and resolving some relocations at assembly time Note that this option does not propagate all symbol arithmetic into the object file because not all symbol arithmetic can be represented However the option can still be useful in s
469. s to expect a crash then when ours fails to crash we would know that the bug was not happening for us If you had not told us to expect a crash then we would not be able to draw any conclusion from our observations e If you wish to suggest changes to the as source send us context diffs as generated by diff with the u c or p option Always send diffs from the old file to the new file If you even discuss something in the as source refer to it by context not by line number The line numbers in our development sources will not match those in your sources Your line numbers would convey no useful information to us Here are some things that are not necessary e A description of the envelope of the bug Often people who encounter a bug spend a lot of time investigating which changes to the input file will make the bug go away and which changes will not affect it Chapter 10 Reporting Bugs 317 This is often time consuming and not very useful because the way we will find the bug is by running a single example under the debugger with breakpoints not by pure deduction from a series of examples We recommend that you save your time for something else Of course if you can find a simpler example to report instead of the original one that is a convenience for us Errors in the output will be easier to spot running under the debugger will take less time and so on However simplification is not vital if you do n
470. s version identifier in object code 9 13 6 Opcodes For detailed information on the HPPA machine instruction set see PA RISC Architecture and Instruction Set Reference Manual HP 09740 90039 142 Using as 9 14 ESA 390 Dependent Features 9 14 1 Notes The ESA 390 as port is currently intended to be a back end for the GNU CC compiler It is not HLASM compatible although it does support a subset of some of the HLASM directives The only supported binary file format is ELF none of the usual MVS VM OE USS object file formats such as ESD or XSD are supported When used with the GNU CC compiler the ESA 390 as will produce correct fully relo cated functional binaries and has been used to compile and execute large projects How ever many aspects should still be considered experimental these include shared library support dynamically loadable objects and any relocation other than the 31 bit relocation 9 14 2 Options as has no machine dependent command line options for the ESA 390 9 14 3 Syntax The opcode operand syntax follows the ESA 390 Principles of Operation manual assembler directives and general syntax are loosely based on the prevailing AT amp T SVR4 ELF Solaris style notation HLASM style directives are not supported for the most part with the exception of those described herein A leading dot in front of directives is optional and the case of directives is ignored thus for example using and USING have the s
471. se eere Rea x SE 264 9 42 6 Local Labels us DEE REES REDI ERIPUIT ss 265 9 42 7 Math B uilling iss rrr cente endian aia gates 265 9 42 8 Extended Addresetng 0 00 e cece e eee eens 267 9 42 9 Drees col neseee oa emeret yeu oem EE omens 267 9 42 10 MACOS as ies dr iae p ane tette qoe See DIA 9 42 11 Memory mapped Register 273 9 42 12 TIC5AX Synlax eiecti ee em emer evade ou 273 9 42 12 1 Special Character 273 9 43 TIC6X Dependent Features 274 9 43 1 TICOX OpD OnS i eraty ee vende tret es 274 9443 2 TICOX Syntax cete ru DD Ree E Ek Seed See En 2714 9 43 9 TICOX Directives setae cens Gana EEN dee 215 9 44 TILE Gx Dependent Features 0 cece eee ee eee 277 Q AAW gene Z t Q AAD Sybex hinds Heche cuneta oa sete og eot cete ded ee aon G 277 9 44 2 1 Opcode Name 277 9 44 2 2 Register Name SCT 9 44 2 3 Symbolic Operand Modifiers 0 278 9 44 38 TILE Gx Directive 280 9 45 TILEPro Dependent Features 000 e eee eee ee 282 Using as 9 45 1 OptlOUS ii dE EE de EEN 282 Ha SERA WEEN eher or P uot es 282 9 45 2 1 Opcode Names cece eee eee eee e eee 282 9 45 2 2 Register Name 282 9 45 2 3 Symbolic Operand Modifiers 000 283 9 45 3 TILEPro Directives Rr RR br Res 285 9 46 Z80 Dependent Features 286 940 1 OptlOnscs ge EE 286 ET E e EEN 286 9 46 2 1 Special Character 286 9 46 2 2 Register Names cece eee en 287 9 46 2 3 Case GBenativite 0 c cece eee eee
472. se of letters is significant foo is a different symbol name than Foo Multibyte characters are supported To generate a symbol name containing multibyte characters enclose it within double quotes and use escape codes cf See Section 3 6 1 1 Strings page 29 Generating a multibyte symbol name from a label is not currently supported Each symbol has exactly one name Each name in an assembly language program refers to exactly one symbol You may use that symbol name any number of times in a program Local Symbol Names A local symbol is any symbol beginning with certain local label prefixes By default the local label prefix is L for ELF systems or L for traditional a out systems but each target may have its own set of local label prefixes On the HPPA local symbols begin with L Local symbols are defined and used within the assembler but they are normally not saved in object files Thus they are not visible when debugging You may use the L 40 Using as option see Section 2 7 Include Local Symbols L page 22 to retain the local symbols in the object files Local Labels Local labels help compilers and programmers use names temporarily They create symbols which are guaranteed to be unique over the entire scope of the input source code and which can be referred to by a simple notation To define a local label write a label of the form N where N represents any positive integer To refer to t
473. sec a RENE ENTREE d 150 RL78 assembler directe 227 RL78 line comment character 227 RL78 linesepar tor i e re bI re eas 227 RL78 modifiers iss 2 ef SN AEN 4r UR 227 RR Options geed NEE e 227 LE e EE 227 PSEC edsr odei etn U qd eeefee bare geg 291 RX assembler directive 3byte Lus 229 RX assembler directive fetchalign 229 RX assembler directe 229 RX floating point 230 RX line comment character 230 AS Index RX line separator 00 eee ee eee eee 230 RX modiflers 2e iskon onn cake Sede d 229 RX ODUIOTIS ies pete tinte metre Hr see 228 EX SUDDOLPL ince edem enc me das e E 228 S s390 floating point ee RM bladed es 245 s390 instruction aliases 00006 238 s390 instruction formats sseessssss 235 s390 instruction marker 243 s390 instruction MNeMOnN CS s sssssrerres 232 s390 instruction operand modifier 241 s390 instruction operande 233 8390 instruction syntax ENEE 231 s390 line comment character 231 8390 line separator c itr 251 s390 literal pool entries eueneneusnenn 243 8390 OPllONS ws 0 0 don cek tee inte Gases E DERE bs 231 s390 register naming ilius e eere 232 390 SUDDOTU cach IE Ee eR ENNE 231 sblock directive TIC54X 00 270 Sbttl directive eee ner re bp EYES 69 schedule directe 312 Scl directivGus soe deci woven RR UIROS 69 SCORE archtectures eccrine ro tarosrenai 24
474. section unique by adding at the end of it in parentheses the name of the original author or publisher of that section if known or else a unique number Make the same adjustment to the section titles in the list of Invariant Sections in the license notice of the combined work In the combination you must combine any sections Entitled History in the vari ous original documents forming one section Entitled History likewise combine any sections Entitled Acknowledgements and any sections Entitled Dedications You must delete all sections Entitled Endorsements 6 COLLECTIONS OF DOCUMENTS You may make a collection consisting of the Document and other documents released under this License and replace the individual copies of this License in the various documents with a single copy that is included in the collection provided that you follow the rules of this License for verbatim copying of each of the documents in all other respects You may extract a single document from such a collection and distribute it individu ally under this License provided you insert a copy of this License into the extracted document and follow this License in all other respects regarding verbatim copying of that document 326 re Using as AGGREGATION WITH INDEPENDENT WORKS A compilation of the Document or its derivatives with other separate and independent documents or works in or on a volume of a storage or distribution m
475. section will be gnu linkonce literal func or gnu linkonce lit4 func 3 If the current section name or literal prefix value ends with test the literal section name is formed by replacing that suffix with the base literal or 1it4 name For example for literals defined in a section named iramO text the literal section will be iramO literal or iram0 1it4 4 If none of the preceding conditions apply the literal section name is formed by adding the base literal or 1it4 name as a suffix to the current section name or literal prefix value 9 52 5 5 literal_position When using text section literals to place literals inline in the section being as sembled the literal_position directive can be used to mark a potential location for a literal pool literal position The literal position directive is ignored when the text section literals op tion is not used or when L32R instructions use the absolute addressing mode The assembler will automatically place text section literal pools before ENTRY instruc tions so the literal position directive is only needed to specify some other location for a literal pool You may need to add an explicit jump instruction to skip over an inline literal pool l Literals for the init and fini sections are always placed in separate sections even when text section literals is enabled 314 Using as For example an interrupt vector does not begin with an ENTRY in
476. sed to be upward compatible with that described in Sections 1 3 and 1 4 of The Art of Computer Programming Volume 1 Draft versions of those chapters as well as other MMIX information is located at http www cs faculty stanford edu knuth mmix news html Most code examples from the mmixal package located there should work unmodified when assembled and linked as single files with a few noteworthy exceptions see Section 9 28 4 MMIX mmixal page 209 Before an instruction is emitted the current location is aligned to the next four byte boundary If a label is defined at the beginning of the line its value will be the aligned value In addition to the traditional hex prefix Ox a hexadecimal number can also be specified by the prefix character After all operands to an MMIX instruction or directive have been specified the rest of the line is ignored treated as a comment 9 28 3 1 Special Characters The characters and are line comment characters each start a comment at the begin ning of a line but only at the beginning of a line A prefixes a hexadecimal number if found elsewhere on a line If a appears at the start of a line the whole line is treated as a comment but the line can also act as a logical line number directive see Section 3 3 206 Using as Comments page 27 or a preprocessor control command see Section 3 1 Preprocessing page 27 Two other characters
477. sees pert RR 52 symbol making visible to linker 56 AS Index symbolic debuggers information for 73 SVMD OS sene icnn I OHPSRRERR ayaa arg aides leer 39 Symbols in position independent code CRIS 122 symbols with uppercase VAX VMS 291 symbols assigning values to 54 Symbols built in CRIS 0 121 Symbols CRIS built in suueee 121 symbols local common esseesssse 60 symver directive nisse ANERE AANER re RP 74 syntax compatibility 290 147 syntax compatibility x86 64 147 syntax AV Rig desit ker e Rip EIER 110 syntax Black cete REENEN tee m 114 syntax DIOV sli EE PR et RE per RR 125 Syntax D90V cust meret ROTG HPPLF IRE 129 syntax LM32 ioc Lec Rr netiis RARUS 168 Syntax M680X0 2 enescrehrpe S NEEN RORIS 179 syntax M68HC11 185 187 syntax machine independent 27 syntax RUB iore ete bk ease d 227 syntax RX EE sans teaver tes IRR XU ames 229 syntax SPARQ enee see reden 255 syntax ERC i23 eR Eres 277 syntax TILEPro 1 Rene 282 syntax XGATE ees les age enine Sie 303 syntax Xtensa assembler iuuceccseena 307 sysproc directive 1960 000 160 T bab Nb e creed ia eio POUR eS Re EOS E 29 tab directive TIC54X 0 eee eee SCH tag directives eire oe ra AE EE 75 tag directive TICBAX csse 271 TBM n Itu eter RES RIDERS
478. sembled this option also affects the way in which the double assembler directive behaves when assem bling little endian code The default is dependent on the processor selected For Architecture 5 or later the default is to assembler for VFP instructions for earlier architectures the default is to assemble for FPA instructions This option specifies that the assembler should start assembling Thumb in structions that is it should behave as though the file starts with a code 16 directive mthumb interwork This option specifies that the output generated by the assembler should be marked as supporting interworking mimplicit it never mimplicit it always mimplicit it arm mimplicit it thumb The mimplicit it option controls the behavior of the assembler when con ditional instructions are not enclosed in IT blocks There are four possible behaviors If never is specified such constructs cause a warning in ARM code and an error in Thumb 2 code If always is specified such constructs are ac cepted in both ARM and Thumb 2 code where the IT instruction is added Chapter 9 Machine Dependent Features 97 implicitly If arm is specified such constructs are accepted in ARM code and cause an error in Thumb 2 code If thumb is specified such constructs cause a warning in ARM code and are accepted in Thumb 2 code If you omit this option the behavior is equivalent to mimplicit it arm mapcs 26 mapcs 32 These options spec
479. sese 307 opcode summary AN KR opcode summary D10V 0 06 128 opcode summary D30V 000 eee 132 opcode summary HS 200 0 eee 136 opcode summary LM27 169 opcode summary SH 250 AS Index opcode summary DHG 253 opcode summary 28000 291 opcodes for A Arche 83 opcodes for ARC 94 opcodes for ARM 104 opcodes for MSP A20 0 0 e eee eee 213 opcodes for Nios D 217 opcodes for V850 cece eee eee eee 300 opcodes 1860 2 2 saved edad EES RM 157 opcodes 1960 dives cides see err a 161 opcodes M680x0 WENN SEN etes 182 opcodes MoSnHCHT eee eee 188 operand delimiters 22906 147 operand delimiters x86 64 00 147 operand notation MAX 294 operands in expressions eee 43 operator precedence 0 c cece es 44 operators in expressions resercre 43 operators permitted arguments 44 optimization MIO eco ce ctr rere 9 optimization DS il seems t her ER Re 9 optimizatiohs s 21 94 x ERE RXGRRENDENGREREGR 308 option directive ARC 94 option directive TIC54X 000 270 option SUMMALY 6 02652 itea a G4 bbR eee ewes x il options for AArch64 none sssssssrssuu 82 options for Alpha i i ler bid denied 84 options for ARC none 91 options for ARM none 95 options for AVR none 108 options for Blackfin none 114 Options EE 145 options for LA O4 cece eee eee 163 options for LM32 none
480. shifts compare and swap atomics and the clr synthetic instruction 262 Using as If generating 32 bit code as will generate the 32 bit opcode Whereas if 64 bit code is being generated the 64 bit opcode will be emitted For example 1dn will be transformed into ld for 32 bit code and 1dx for 64 bit code Here is an example meant to demonstrate all the supported opcode translations ldn 400 hol ldna 400 asi oi stn X 4oi 400 stna 02 400 4asi slin 03 3 03 srln 04 8 04 sran 05 12 od casn 00 01 02 casna 00 asi 01 o2 clrn Lei In 32 bit mode as will emit ld 00 01 lda 400 asi 02 st ol 400 sta 02 400 4asi sll 03 3 03 srl o4 8 o4 sra od5 12 ob cas 00 01 02 casa 400 asi 01 02 clr fet And in 64 bit mode as will emit ldx 00 01 ldxa 400 asi oi stx oi 00 stxa 02 400 asi sllx 03 3 03 srlx 04 8 04 srax job 12 05 casx 00 hoi 02 casxa 00 asi 01 02 clrx Zei Finally the nword translating directive is supported as well It is documented in the section on Sparc machine directives 9 41 4 Floating Point The Sparc uses IEEE floating point numbers 9 41 5 Sparc Machine Directives The Sparc version of as supports the following additional machine directives align This must be followed by the desired alignment in bytes Chapter 9 common half nword proc register res
481. some version of the 960 even if this means mix ing architectures In principle as attempts to deduce the minimal sufficient processor type if none is specified depending on the object code format the processor type may be recorded in the object file If it is critical that the as output match a specific architecture specify that architecture explicitly Add code to collect information about conditional branches taken for later optimization using branch prediction bits The conditional branch instructions have branch prediction bits in the CA CB and CC architectures If BR represents a conditional branch instruction the following represents the code generated by the assembler when b is specified call increment routine word 0 pre counter Label BR call increment routine word 0 post counter The counter following a branch records the number of times that branch was not taken the difference between the two counters is the number of times the branch was taken A table of every such Label is also generated so that the external postprocessor gbr960 supplied by Intel can locate all the counters This table is always labeled __BRANCH_TABLE__ this is a local symbol to permit collecting statistics for many separate object files The table is word aligned and begins with a two word header The first word initialized to 0 is used in maintaining linked lists of branch tables The second word is a count of the number
482. sponds to a prefetch function code of 21 n writes strong requests a strong prefetch for several writes and corresponds to a prefetch function code of 22 tone write strong requests a strong prefetch for one write and corresponds to a prefetch function code of 23 Onle one prefetch code may be specified Here are some examples prefetch 410 12 one_read prefetch Dei 8 n_writes prefetcha Agi 0x8 unified prefetcha 00 0x10 asi n_reads The actual behavior of a given prefetch function code is processor specific If a processor does not implement a given prefetch function code it will treat the prefetch instruction as a nop For instructions that accept an immediate address space identifier as provides many mnemonics corresponding to V9 defined as well as UltraSPARC and Niagara extended values For example ASI_P and ASI_BLK_INIT_QUAD_LDD_AIUS See the V9 and processor specific manuals for details 9 41 3 4 Relocations ELF relocations are available as defined in the 32 bit and 64 bit Sparc ELF specifications R_SPARC_HI22 is obtained using Ahi and R_SPARC_LO10 is obtained using io Like wise R_SPARC_HIX22 is obtained from hix and R_SPARC_LOX10 is obtained using los For example sethi hi symbol je or gi Alo symbol Ae sethi Zhix symbol gl xor f g1 4lox symbol Ae These high mnemonics extract bits 31 10 of their operand and the low mnemonics extra
483. ss forgiving about missing arguments and other similar oversights than the HP assembler as notifies you of missing arguments as syntax errors this is regarded as a feature not a bug Finally as allows you to use an external symbol without explicitly importing the symbol Warning in the future this will be an error for HPPA targets Special characters for HPPA targets include is the line comment character can be used instead of a newline to separate statements Since has no special meaning you may use it in symbol names 9 13 4 Floating Point The HPPA family uses IEEE floating point numbers 9 13 5 HPPA Assembler Directives as for the HPPA supports many additional directives for compatibility with the native assembler This section describes them only briefly For detailed information on HPPA specific assembler directives see HP9000 Series 800 Assembly Language Reference Manual HP 92432 90001 as does not support the following assembler directives described in the HP manual 138 Using as endm liston enter locct leave macro listoff Beyond those implemented for compatibility as supports one additional assembler di rective for the HPPA param It conveys register argument locations for static functions Its syntax closely follows the export directive These are the additional directives in as for the HPPA block n blockz n call callinfo code Reserve n bytes of
484. st argument is the requested align ment in bytes allow suspicious bundles Turns on error checking for combinations of instructions in a bundle that prob ably indicate a programming error This is on by default no allow suspicious bundles Turns off error checking for combinations of instructions in a bundle that prob ably indicate a programming error require canonical reg names Require that canonical register names be used and emit a warning if the nu meric names are used This is on by default no require canonical reg names Permit the use of numeric names for registers that have canonical names 286 Using as 9 46 Z80 Dependent Features 9 46 1 Options The Zilog Z80 and Ascii R800 version of as have a few machine dependent options z80 Produce code for the Z80 processor There are additional options to request warnings and error messages for undocumented instructions ignore undocumented instructions Wnud Silently assemble undocumented Z80 instructions that have been adopted as documented R800 instructions ignore unportable instructions Wnup Silently assemble all undocumented Z80 instructions warn undocumented instructions Wud Issue warnings for undocumented Z80 instructions that work on R800 do not assemble other undocumented instructions without warning warn unportable instructions Wup Issue warnings for other undocumented Z80 instructions do not treat
485. stack pointer personality name Sets the personality routine for the current function to name personalityindex index Sets the personality routine for the current function to the EABI standard routine number index pool This is a synonym for ltorg name req register name This creates an alias for register name called name For example foo req rO save reglist Generate unwinder annotations to restore the registers in reglist The format of reglist is the same as the corresponding store multiple instruction core registers save r4 r5 r6 lr stmfd sp r4 r5 r6 lr FPA registers save f4 2 sfmfd f4 2 sp VFP registers save d8 d9 d10 fstmdx sp d8 d9 d10 iWMMXt registers save wri0 wrii wstrd wri1 sp 8 wstrd wri0 sp 8 or Save wril wstrd wri1 sp 8 save wriO wstrd wri0 sp 8 Setfp fpreg spreg offset Make all unwinder annotations relative to a frame pointer Without this the unwinder will use offsets from the stack pointer The syntax of this directive is the same as the add or mov instruction used to set the frame pointer spreg must be either sp or mentioned in a previous movsp directive Chapter 9 Machine Dependent Features 103 movsp ip mov ip sp Setfp fp ip 4 add fp ip 4 Secrel32 expression expression This directive emits relocations that evaluate to the section relative offset of each expression s symbol
486. stants double Double precision floating point constants extend ldouble Extended precision long double floating point constants 9 24 6 Opcodes 9 24 6 1 Branch Improvement Certain pseudo opcodes are permitted for branch instructions They expand to the shortest branch instruction that reach the target Generally these mnemonics are made by prepend ing j to the start of Motorola mnemonic These pseudo opcodes are not affected by the short branches or force long branches options The following table summarizes the pseudo operations Displacement Width 4 Options short branches force long branches 4 4 Op BYTE WORD BYTE WORD 4 4 bsr bsr lt pc rel gt error jsr abs bra bra lt pc rel gt error jmp abs jbsr bsr lt pc rel gt jsr abs ber lt pc rel gt jsr abs jbra bra lt pc rel gt jmp lt abs gt bra lt pc rel gt jmp lt abs gt bXX bXX lt pc rel gt error bNX 3 jmp abs jbXX bXX lt pc rel gt bNX 3 bXX lt pc rel gt bNX 3 jmp abs jmp abs 4 4 XX condition NX negative of condition XX jbsr jbra These are the simplest jump pseudo operations they always map to one partic
487. sted the sequence of statements is assembled once with symbol set to the null string To refer to symbol within the sequence of statements use Nsymbol For example assembling irpc param 123 move dNparam sp endr is equivalent to assembling move di sp move d2 sp move d3 spQ For some caveats with the spelling of symbol see also the discussion at See Section 7 79 Macro page 62 60 Using as 7 69 lcomm symbol length Reserve length an absolute expression bytes for a local common denoted by symbol The section and value of symbol are those of the new local common The addresses are allocated in the bss section so that at run time the bytes start off zeroed Symbol is not declared global see Section 7 57 global page 56 so is normally not visible to 1d Some targets permit a third argument to be used with 1comm This argument specifies the desired alignment of the symbol in the bss section The syntax for 1comm differs slightly on the HPPA The syntax is symbol lcomm length symbol is optional 7 70 lflaks as accepts this directive for compatibility with other assemblers but ignores it 7 71 line line number Change the logical line number line number must be an absolute expression The next line has that logical line number Therefore any other statements on the current line after a statement separator character are reported as on logical line number line number 1 One day as will
488. struction operands The general syntax is the following gp symbol The modifier returns the offset from the _ gp symbol to the specified symbol as a 16 bit value The intent is that this offset should be used in a register offset move instruction when generating references to small data Ie like this mov W jent foo A4gpregl ri The assembler also supports two meta register names which can be used to refer to registers whose values may not be known to the programmer These meta register names are gpreg The small data address register Apidreg The PID base address register Both registers normally have the value r13 but this can change if some registers have been reserved for use by interrupt handlers or if both the small data limit and position independent data features are being used at the same time 9 36 3 Assembler Directives The RX version of as has the following specific assembler directives Sbyte Inserts a 3 byte value into the output file at the current location fetchalign If the next opcode following this directive spans a fetch line boundary 8 byte boundary the opcode is aligned to that boundary If the next opcode does not span a fetch line this directive has no effect Note that one or more labels may be between this directive and the opcode those labels are aligned as well Any inserted bytes due to alignment will form a NOP opcode 230 Using as 9 36 4 Floating Point The floating point formats ge
489. struction so the as sembler will be unable to automatically find a good place to put a literal pool Moreover the code for the interrupt vector must be at a specific starting address so the literal pool cannot come before the start of the code The literal pool for the vector must be explicitly positioned in the middle of the vector before any uses of the literals due to the nega tive offsets used by PC relative L32R instructions The literal_position directive can be used to do this In the following code the literal for M will automatically be aligned correctly and is placed after the unconditional jump global M code start j continue literal position align 4 continue movi a4 M 9 52 5 6 literal prefix The literal prefix directive allows you to override the default literal section names which are derived from the names of the sections where the literals are defined begin literal prefix name end literal prefix For literals defined within the delimited region the literal section names are derived from the name argument instead of the name of the current section The rules used to derive the literal section names do not change See Section 9 52 5 4 literal page 312 If the name argument is omitted the literal sections revert to the defaults This directive has no effect when using the text section literals option see Section 9 52 1 Command Line Options page 306 9 52 5 7 absolute literals
490. sym may require the widest displacement field 16 bits for m16c 24 bits for m32c These modifiers tell it to assume the address will fit in an 8 or 16 bit respectively unsigned displacement Note that of course if it doesn t actually fit you will get linker errors Example mov w 4dsp8 sym a0 r1 mov b 0 dsp8 sym a0 GE This modifier allows you to load bits 16 through 23 of a 24 bit address into an 8 bit register This is useful with for example the M16C smovf instruction which expects a 20 bit address in rih and a0 Example mov b hi8 sym rih mov w 1016 sym a0 smovf b 41016 Likewise this modifier allows you to load bits 0 through 15 of a 24 bit address into a 16 bit register 7ni16 This modifier allows you to load bits 16 through 31 of a 32 bit address into a 16 bit register While the M32C family only has 24 bits of address space Chapter 9 Machine Dependent Features 171 it does support addresses in pairs of 16 bit registers like a1a0 for the lde instruction This modifier is for loading the upper half in such cases Example mov w hil6 sym al mov w 1016 sym a0 lde w a1a0 r 9 21 2 2 Special Characters The presence of a character on a line indicates the start of a comment that extends to the end of that line If a 4 appears as the first character of a line the whole line is treated as a comment but in this case the line can also be
491. symbol name in parentheses register and functional unit names may not be enclosed in parentheses 9 43 3 TIC6X Directives Directives controlling the set of instructions accepted by the assembler have effect for in structions between the directive and any subsequent directive overriding it arch arch This has the same effect as march arch cantunwind Prevents unwinding through the current function No personality routine or exception table data is required or permitted If this is not specified then frame unwinding information will be constructed from CFI directives see Section 7 11 CFI directives page 50 c6xabi_attribute tag value Set the C6000 EABI build attribute tag to value The tag is either an attribute number or one of Tag_ISA Tag_ABI_wchar_t Tag_ABI_stack_align_needed Tag_ABI_stack_align_preserved Tag_ABI_ DSBT Tag_ABI_PID Tag_ABI_PIC TAG_ABI_array_object_alignment TAG_ ABI_array_object_align_expected Tag_ABI_compatibility and Tag_ABI_ conformance The value is either a number string or number string depending on the tag ehtype symbol Output an exception type table reference to symbol endp Marks the end of and exception table or function If preceeded by a handlerdata directive then this also switched back to the previous text section handlerdata Marks the end of the current function and the start of the exception table entry for that function Anything between this directive an
492. system procedure identified by index when calling procedures with the optimized call instruction callj Both arguments are required index must be between 0 and 31 inclusive Chapter 9 Machine Dependent Features 161 9 17 4 i960 Opcodes All Intel 960 machine instructions are supported see Section 9 17 1 i960 Command line Options page 159 for a discussion of selecting the instruction subset for a particular 960 architecture Some opcodes are processed beyond simply emitting a single corresponding instruction callj and Compare and Branch or Compare and Jump instructions with target displace ments larger than 13 bits 9 17 4 1 callj You can write callj to have the assembler or the linker determine the most appropriate form of subroutine call call bal or calls If the assembly source contains enough information a leafproc or sysproc directive defining the operand then as trans lates the ca11j if not it simply emits the ca11j leaving it for the linker to resolve 9 17 4 2 Compare and Branch The 960 architectures provide combined Compare and Branch instructions that permit you to store the branch target in the lower 13 bits of the instruction word itself However if you specify a branch target far enough away that its address won t fit in 13 bits the assembler can either issue an error or convert your Compare and Branch instruction into separate instructions to do the compare
493. t but in this case the line could also be a logical line number directive see Section 3 3 Comments page 27 or a preprocessor control command see Section 3 1 Preprocessing page 27 Instructions consist of a leading opcode or macro name followed by whitespace and an optional comma separated list of operands opcode operand Instructions must be separated by a newline or semicolon FLIX instructions which bundle multiple opcodes together in a single instruction are specified by enclosing the bundled opcodes inside braces format opcodeO operands opcode1 operands opcode2 operands Jy The opcodes in a FLIX instruction are listed in the same order as the corresponding instruction slots in the TIE format declaration Directives and labels are not allowed inside the braces of a FLIX instruction A particular TIE format name can optionally be specified immediately after the opening brace but this is usually unnecessary The assembler will automatically search for a format that can encode the specified opcodes so the format name need only be specified in rare cases where there is more than one applicable format and where it matters which of those formats is used A FLIX instruction can also be specified on a single line by separating the opcodes with semicolons format opcodeO operands opcode1 operands opcode2 operands If an opcode can only be encoded in a FLIX instruction but is not sp
494. t SOATE 305 instruction summary AND 111 instruction summary DIN 128 instruction summary D30V 132 instruction summary H8 300 136 instruction summary LM32 169 instruction summary SH 0 250 instruction summary Sol 253 instruction summary Z8000 291 instruction syntax a00 231 instructions and directives 6 28 int directive isl los fes elei urb Pew IER 58 int directive H8 3 Q0 rrcriseriuricirenirenssi 136 int directive 1380 ose e sensns ea i 152 int directive TICSAX ag eese re te n tea 269 int directive x86 64 0 0 eee eee eee 152 integer exXpreSSiONS n nnn 43 AS Index integer 16 byte cese eet eere aca cede 65 integer byle i ine e e RR REIR ERO 68 INGE BOTS ARENS 30 integers JEE Sen RTE REENEN 57 integers S2 Ditiss corset i deds xd SNE 58 integers binary a pere er Re RYE 30 integers decimal Lp RE DR REED 30 integers hexadecimal isesucseccrrrrren 30 integers Delta 2 Ae 8 eene RID REN aae ris 30 integers one byte eise rer erbe Sief 50 intel syntax pseudo op i886 4 147 intel syntax pseudo op x86 64 147 internal assembler sections 35 internal directe 59 invalid Input 4 EEN ENEE SN 315 IMVOCALION SUMMALY eccle ewe emer bed ee 1 IP2K architecture option 166 IP2K line comment character 166 IP2K line separator eca
495. t but in this case the line can also be a logical line number directive see Section 3 3 Comments page 27 or a preprocessor control command see Section 3 1 Preprocessing page 27 The IP2K assembler does not currently support a line separator character Chapter 9 Machine Dependent Features 9 20 LM32 Dependent Features 9 20 1 Options mmultiply enabled Enable multiply instructions mdivide enabled Enable divide instructions mbarrel shift enabled Enable barrel shift instructions msign extend enabled Enable sign extend instructions muser enabled Enable user defined instructions micache enabled Enable instruction cache related CSRs mdcache enabled Enable data cache related CSRs mbreak enabled Enable break instructions mall enabled Enable all instructions and CSRs 9 20 2 Syntax 9 20 2 1 Register Names LM32 has 32 x 32 bit general purpose registers r0 r1 r31 The following aliases are defined gp r26 fp r27 sp r30 ba r31 LM32 has the following Control and Status Registers CSRs IE Interrupt enable IM Interrupt mask IP Interrupt pending ICC Instruction cache control DCC Data cache control CC Cycle counter CFG Configuration EBA Exception base address DC Debug control 167 728 ra r29 ea 168 DEBA JTX JRX BPO BP1 BP2 BP3 WPO WP1 WP2 WP3
496. t currently possible but it can be done for the a out format The object file is meant for input to the linker 1d It contains assembled program code information to help 1d integrate the assembled program into a runnable file and optionally symbolic information for the debugger 1 7 Error and Warning Messages as may write warnings and error messages to the standard error file usually your termi nal This should not happen when a compiler runs as automatically Warnings report an assumption made so that as could keep assembling a flawed program errors report a grave problem that stops the assembly Warning messages have the format file name NNN Warning Message Text where NNN is a line number If a logical file name has been given see Section 7 53 file page 55 it is used for the filename otherwise the name of the current input file is used If a logical line number was given see Section 7 71 line page 60 then it is used to calculate the number printed otherwise the actual line in the current source file is printed The message text is intended to be self explanatory in the grand Unix tradition Error messages have the format Chapter 1 Overview 19 file_name NNN FATAL Error Message Text The file name and line number are derived as for warning messages The actual message text may be rather less explanatory because many of them aren t supposed to happen Chapter 2 Command Line Options 21 2 Command Line Optio
497. t does not emit anything for it When using COFF comments are emitted to the comment or rdata section depending on the target When using ELF comments are emitted to the comment section 7 62 if absolute expression if marks the beginning of a section of code which is only considered part of the source program being assembled if the argument which must be an absolute expression is non zero The end of the conditional section of code must be marked by endif see Section 7 44 endif page 54 optionally you may include code for the alternative condition flagged by else see Section 7 39 e1se page 53 If you have several conditions to check elseif may be used to avoid nesting blocks if else within each subsequent else block The following variants of if are also supported ifdef symbol Assembles the following section of code if the specified symbol has been defined Note a symbol which has been referenced but not yet defined is considered to be undefined ifb text Assembles the following section of code if the operand is blank empty ifc string1 string2 Assembles the following section of code if the two strings are the same The strings may be optionally quoted with single quotes If they are not quoted the first string stops at the first comma and the second string stops at the end of the line Strings which contain whitespace should be quoted The string comparison is case sensitive ifeq absolute expr
498. t file to be as small as possible and you know that the relevant symbols are always less than 17 bits away register prefix optional For some configurations especially those where the compiler normally does not prepend an underscore to the names of user variables the assembler requires a W before any use of a register name This is intended to let the assembler distinguish between C variables and functions named a0 through a7 and so on The is always accepted but is not required for certain configurations notably sun3 The register prefix optional option may be used to permit omitting the even for configurations for which it is normally required If this is done it will generally be impossible to refer to C variables and functions with the same names as register names bitwise or Normally the character is treated as a comment character which means that it can not be used in expressions The bitwise or option turns into a Chapter 9 Machine Dependent Features 177 normal character In this mode you must either use C style comments or start comments with a character at the beginning of a line base size default 16 base size default 32 If you use an addressing mode with a base register without specifying the size as will normally use the full 32 bit value For example the addressing mode a0 d0 is equivalent to Za0 d0 1 Y
499. t floats The no construct floats option disables the construction of double width floating point constants by loading the two halves of the value into the two single width floating point registers that make up the double width register By default construct floats is selected allowing construction of these floating point constants relax branch no relax branch The relax branch option enables the relaxation of out of range branches By default no relax branch is selected causing any out of range branches to produce an error mnan encoding Select between the IEEE 754 2008 mnan 2008 or the legacy mnan legacy NaN encoding format The latter is the default emulation name This option was formerly used to switch between ELF and ECOFF output on targets like IRIX 5 that supported both MIPS ECOFF support was removed in GAS 2 24 so the option now serves little purpose It is retained for backwards compatibility The available configuration names are mipself mipslelf and mipsbelf Choosing mipself now has no effect since the output is always ELF mipslelf and mipsbelf select little and big endian output respectively but EL and EB are now the preferred options instead nocpp as ignores this option It is accepted for compatibility with the native tools Chapter 1 Overview 15 trap no trap break no break Control how to dea
500. t to be filled with no op instructions when appropriate The balignw and balignl directives are variants of the balign directive The balignw directive treats the fill pattern as a two byte word value The balignl directives treats the fill pattern as a four byte longword value For example balignw 4 0x368d will align to a multiple of 4 If it skips two bytes they will be filled in with the value 0x368d the exact placement of the bytes depends upon the endianness of the processor If it skips 1 or 3 bytes the fill value is undefined 7 8 bundle align mode abs expr bundle align mode enables or disables aligned instruction bundle mode In this mode sequences of adjacent instructions are grouped into fixed sized bundles If the argument is zero this mode is disabled which is the default state If the argument it not zero it gives the size of an instruction bundle as a power of two as for the p2align directive see Section 7 86 P2align page 66 For some targets it s an ABI requirement that no instruction may span a certain aligned boundary A bundle is simply a sequence of instructions that starts on an aligned boundary For example if abs expr is 5 then the bundle size is 32 so each aligned chunk of 32 bytes is a bundle When aligned instruction bundle mode is in effect no single instruction may span a boundary between bundles If an instruction would start too close to the end of a bundle for the length of that particu
501. t values that are added and subtracted to one of the index registers Abbreviated as Mreg Length Registers The set of 32 bit registers LO L1 L2 L3 that normally contain the length in bytes of the circular buffer Abbreviated as Lreg Clear the Lreg to disable circular addressing for the corresponding breng Base Registers The set of 32 bit registers BO B1 B2 B3 that normally contain the base address in bytes of the circular buffer Abbreviated as Breg Floating Point The Blackfin family has no hardware floating point but the float directive gen erates ieee floating point numbers for use with software floating point libraries Blackfin Opcodes For detailed information on the Blackfin machine instruction set see the Black fin r Processor Instruction Set Reference 9 6 3 Directives The following directives are provided for compatibility with the VDSP assembler byte2 Initializes a two byte data object This maps to the short directive Chapter 9 byte4 db dw dd Var Machine Dependent Features 117 Initializes a four byte data object This maps to the int directive Initializes a single byte data object This directive is a synonym for byte Initializes a two byte data object This directive is a synonym for byte2 Initializes a four byte data object This directive is a synonym for byte4 Define and initialize a 32 bit data object 118 Using as 9 7 CR16 Dependent Features
502. takes an optional third argument This is the desired alignment of the symbol specified for ELF as a byte boundary for example an alignment of 16 means that the least significant 4 bits of the address should be zero and for PE as a power of two for example an alignment of 5 means aligned to a 32 byte boundary The alignment must be an absolute expression and it must be a power of two If 1d allocates uninitialized memory for the common symbol it will use the alignment when placing the symbol If no alignment is specified as will set the alignment to the largest power of two less than or equal to the size of the symbol up to a maximum of 16 on ELF or the default section alignment of 4 on DEI The syntax for comm differs slightly on the HPPA The syntax is symbol comm length symbol is optional Ya 1 This is not the same as the executable image file alignment controlled by 1d s section alignment option image file sections in PE are aligned to multiples of 4096 which is far too large an alignment for ordinary variables It is rather the default alignment for non debug sections within object 0 files which are less strictly aligned Chapter 7 Assembler Directives 53 7 33 data subsection data tells as to assemble the following statements onto the end of the data subsection numbered subsection which is an absolute expression If subsection is omitted it defaults to zero 7 34 def name Begin
503. tart of a region of code containing ARM instructions t At the start of a region of code containing THUMB instructions d At the start of a region of data The assembler will automatically insert these symbols for you there is no need to code them yourself Support for tagging symbols b f p and m which is also mentioned in the current ARM ELF specification is not implemented This is because they have been dropped from the new EABI and so tools cannot rely upon their presence 9 4 7 Unwinding The ABI for the ARM Architecture specifies a standard format for exception unwind infor mation This information is used when an exception is thrown to determine where control should be transferred In particular the unwind information is used to determine which function called the function that threw the exception and which function called that one and so forth This information is also used to restore the values of callee saved registers in the function catching the exception If you are writing functions in assembly code and those functions call other functions that throw exceptions you must use assembly pseudo ops to ensure that appropriate ex ception unwind information is generated Otherwise if one of the functions called by your assembly code throws an exception the run time library will be unable to unwind the stack through your assembly code and your program will not behave correctly To illustrate the use of these pseudo ops we
504. te 4 Bie xu et eKbRPRARSIdd ee 51 cfl return column register cccesese e ele NEE EEN 51 Gfi signal frame lcu ee boe n EY a beds 52 Cfi window gave EE EE ENEE eee EE 52 G i escape expression h gees ege rrr rre bes 52 cfi val encoded addr register encoding label 52 comm symbol length use ciet ee nace Re e EE 52 data subsection esses aeos de ebbe n c ed 53 def name i n p cas HESS ENNEN PR der 53 desc symbol abs expressiOn esee 53 dim iseers RR EDENE EETIKA ERTES DPGMRPYG PLease cR pedo 53 double flOonums v debe ees eset atri Dp sare geret 53 E EEN 53 CISC sic 6 be sega c e Rr ERREEN ERE uU RYE de sede nied cee 53 GlSOlf cu deserere De SI Seb e iid 53 cu PP H HMP 53 endet sede ne eL E Lx I td Le Ee t 54 endf nc scele breere er oe een bidder d repeat edd 54 endif eec vea aec e ki ee odes pate pa ei ete la 54 equ symbol erptessgion een een 54 equiv symbol expresslOn ce M RR E E pOUCO eS 54 Oqv symbol expresSsSlOnz ete eue eerte d Ree dk 54 EE 54 error string ois EE ge SES ore 54 roh pU 55 OKOT rer n dcaude ete del es pisc cb ua ERAqr eris Friede 55 tall SxpresSTOU ees cde EE nae delete 55 f llQ itoenst ek ctetu aorta a tte ee Pia op edle AEN 55 fill repeat Size value ing cna e PR Rp es 55 iloat flonumsc c ee Eni peru Rp n tma MEER EM 56 func name lt TADS EE 56 global symbol globl symbol cece eee 56 gnu attribute tag value
505. te this problem of correctly identifying string parameters to pseudo ops also applies to the identifiers used in irp see Section 7 67 Irp page 59 and irpc see Section 7 68 Irpc page 59 as well Mark the end of a macro definition Exit early from the current macro definition as maintains a counter of how many macros it has executed in this pseudo variable you can copy that number to your output with but only within a macro definition Bees A Warning LOCAL is only available if you select alternate macro syntax with alternate or altmacro See Section 7 4 altmacro page 48 Chapter 7 Assembler Directives 65 7 80 mri val If val is non zero this tells as to enter MRI mode If val is zero this tells as to exit MRI mode This change affects code assembled until the next mri directive or until the end of the file See Section 2 9 MRI mode page 23 7 81 noaltmacro Disable alternate macro mode See Section 7 4 Altmacro page 48 7 82 nolist Control in conjunction with the list directive whether or not assembly listings are generated These two directives maintain an internal counter which is zero initially list increments the counter and nolist decrements it Assembly listings are generated whenever the counter is greater than zero 7 83 octa bignums This directive expects zero or more bignums separated by commas For each bignum it emits a 16 byte integer The
506. tements on the same line 120 Using as 9 8 CRIS Dependent Features 9 8 1 Command line Options The CRIS version of as has these machine dependent command line options The format of the generated object files can be either ELF or a out specified by the command line options emulation crisaout and emulation criself The default is ELF criself unless as has been configured specifically for a out by using the configura tion name cris axis aout There are two different link incompatible ELF object file variants for CRIS for use in environments where symbols are expected to be prefixed by a leading _ character and for environments without such a symbol prefix The variant used for GNU Linux port has no symbol prefix Which variant to produce is specified by either of the options underscore and no underscore The default is underscore Since symbols in CRIS a out objects are expected to have a _ prefix specifying no underscore when generating a out objects is an error Besides the object format difference the effect of this option is to parse register names differently see crisnous page 123 The no underscore option makes a register prefix mandatory The option pic must be passed to as in order to recognize the symbol syntax used for ELF SVRA PIC position independent code see crispic page 122 This will also affect expansion of instructions The expansion w
507. tenance of as In order for a bug report to serve its purpose you must include the information that enables us to fix the bug 10 1 Have You Found a Bug If you are not sure whether you have found a bug here are some guidelines e If the assembler gets a fatal signal for any input whatever that is a as bug Reliable assemblers never crash e If as produces an error message for valid input that is a bug e If as does not produce an error message for invalid input that is a bug However you should note that your idea of invalid input might be our idea of an extension or support for traditional practice e If you are an experienced user of assemblers your suggestions for improvement of as are welcome in any case 10 2 How to Report Bugs A number of companies and individuals offer support for GNU products If you obtained as from a support organization we recommend you contact that organization first You can find contact information for many support companies and individuals in the file etc SERVICE in the GNU Emacs distribution In any event we also recommend that you send bug reports for as to http www sourceware org bugzilla The fundamental principle of reporting bugs usefully is this report all the facts If you are not sure whether to state a fact or leave it out state it Often people omit facts because they think they know what causes the problem and assume that some details do not matter
508. ter merging isn t yet implemented in 1d as will warn every time it expands an instruction to fit an operand unless the option x is specified It is believed that this behaviour is more useful than just mimicking mmixal s behaviour in which instructions are only expanded if the x option is specified and assembly fails otherwise when an instruction needs to be expanded It needs to be kept in mind that mmixal is both an assembler and linker while as will expand instructions that at link stage can be contracted Though linker relaxation isn t yet implemented in 1d The option x also imples linker allocated gregs If instruction expansion is enabled as can expand a PUSHJ instruction into a series of instructions The shortest expansion is to not expand it but just mark the call as redi rectable to a stub which 1d creates at link time but only if the original PUSHJ instruction is found not to reach the target The stub consists of the necessary instructions to form a jump to the target This happens if as can assert that the PUSHJ instruction can reach such a stub The option no pushj stubs disables this shorter expansion and the longer series of instructions is then created at assembly time The option no stubs is a syn onym intended for compatibility with future releases where generation of stubs for other instructions may be implemented Usually a two operand expression see G
509. term octa comes from contexts in which a word is two bytes hence octa word for 16 bytes 7 84 offset loc Set the location counter to loc in the absolute section Joc must be an absolute expression This directive may be useful for defining symbols with absolute values Do not confuse it with the org directive 7 85 org new lc fill Advance the location counter of the current section to new lc new lc is either an absolute expression or an expression with the same section as the current subsection That is you can t use org to cross sections if new lc has the wrong section the org directive is ignored To be compatible with former assemblers if the section of new lc is absolute as issues a warning then pretends the section of new lc is the same as the current subsection org may only increase the location counter or leave it unchanged you cannot use org to move the location counter backwards Because as tries to assemble programs in one pass new Ic may not be undefined If you really detest this restriction we eagerly await a chance to share your improved assembler Beware that the origin is relative to the start of the section not to the start of the subsection This is compatible with other people s assemblers When the location counter of the current subsection is advanced the intervening bytes are filled with fill which should be an absolute expression If the comma and fill are omitted fill defaults t
510. the first operand just before a cache miss When the mul bug abort command line option is active the default value as will refuse to assemble a file containing a multiply Chapter 9 Machine Dependent Features 121 instruction at a dangerous offset one that could be the last on a cache line or is in a section with insufficient alignment This placement checking does not catch any case where the multiply instruction is dangerously placed because it is located in a delay slot The mul bug abort command line option turns off the checking 9 8 2 Instruction expansion as will silently choose an instruction that fits the operand size for register constant operands For example the offset 127 in move d r3 127 r4 fits in an instruction using a signed byte offset Similarly move d r2 32767 r1 will generate an instruction using a 16 bit offset For symbolic expressions and constants that do not fit in 16 bits including the sign bit a 32 bit offset is generated For branches as will expand from a 16 bit branch instruction into a sequence of in structions that can reach a full 32 bit address Since this does not correspond to a single instruction such expansions can optionally be warned about See Section 9 8 1 CRIS Opts page 120 If the operand is found to fit the range a lapc mnemonic will translate to a lapcq instruction Use lapc d to force the 32 bit lapc instruction Similarly the addo mnemonic will translate
511. the name is undefined Note this pseudo op can be used to delete builtin in register name aliases eg r0 This should only be done if it is really necessary unwind raw offset bytel Insert one of more arbitary unwind opcode bytes which are known to adjust the stack pointer by offset bytes For example unwind raw 4 Oxb1 0x01 is equivalent to save r0 104 Using as vsave vfp reglist Generate unwinder annotations to restore the VFP registers in vfp reglist using FLDMD Also works for VFPv3 registers that are to be restored using VLDM The format of vfp reglist is the same as the corresponding store multiple in struction VFP registers vsave d8 d9 d10 fstmdd sp d8 d9 d10 VFPv8 registers vsave di5 di6 d17 vstm sp di5 d16 d17 Since FLDMX and FSTMX are now deprecated this directive should be used in favour of save for saving VFP registers for ARMv6 and above 9 4 5 Opcodes as implements all the standard ARM opcodes It also implements several pseudo opcodes including several synthetic load instructions NOP LDR ADR ADRL nop This pseudo op will always evaluate to a legal ARM instruction that does noth ing Currently it will evaluate to MOV r0 r0 ldr register expression If expression evaluates to a numeric constant then MOV or MVN instruction will be used in place of the LDR instruction if the constant can be generated by either of these instruct
512. ther targets use the default version Default Version This version of the file directive tells as that we are about to start a new logical file The syntax is file string string is the new file name In general the filename is recognized whether or not it is surrounded by quotes but if you wish to specify an empty file name you must give the quotes This statement may go away in future it is only recognized to be compatible with old as programs DWARF2 Version When emitting DWARF2 line number information file assigns filenames to the debug line file name table The syntax is file fileno filename The fileno operand should be a unique positive integer to use as the index of the entry in the table The filename operand is a C string literal The detail of filename indices is exposed to the user because the filename table is shared with the debug info section of the DWARF2 debugging information and thus the user must know the exact indices that table entries will have 7 04 fill repeat size value repeat size and value are absolute expressions This emits repeat copies of size bytes Repeat may be zero or more Size may be zero or more but if it is more than 8 then it is deemed to have the value 8 compatible with other people s assemblers The contents of 56 Using as each repeat bytes is taken from an 8 byte number The highest order 4 bytes are zero The lowest order 4 bytes are value rendered i
513. thout specified semantics Example BSPEC 42 TETRA 1 2 3 ESPEC The single operand to BSPEC must be number in the range 0 255 The BSPEC number 80 is used by the GNU binutils implementation 9 28 4 Differences to mmixal The binutils as and 1d combination has a few differences in function compared to mmixal see mmixsite page 205 The replacement of a symbol with a GREG allocated register see GREG base page 208 is not handled the exactly same way in as as in mnixal This is apparent in the mmixal example file inout mms where different registers with different offsets eventually yielding the same address are used in the first instruction This type of difference should however not affect the function of any program unless it has specific assumptions about the allocated register number Line numbers in the mmo object format are currently not supported Expression operator precedence is not that of mmixal operator precedence is that of the C programming language It s recommended to use parentheses to explicitly specify wanted operator precedence whenever more than one type of operators are used The serialize unary operator amp the fractional division operator the logical not operator and the modulus operator are not available Symbols are not global by default unless the option globalize symbols is passed Use the global directive to globalize symbols see Section 7 5
514. ting the current location counter Chapter 9 Machine Dependent Features 287 A backslash is an ordinary character for the Z80 assembler The single quote must be followed by a closing quote If there is one character in between it is a character constant otherwise it is a string constant 9 46 2 2 Register Names The registers are referred to with the letters assigned to them by Zilog In addition as recognizes ixl and ixh as the least and most significant octet in ix and similarly iyl and iyh as parts of iy 9 46 2 3 Case Sensitivity Upper and lower case are equivalent in register names opcodes condition codes and as sembler directives The case of letters is significant in labels and symbol names The case is also important to distinguish the suffix b for a backward reference to a local label from the suffix B for a number in binary notation 9 46 3 Floating Point Floating point numbers are not supported 9 46 4 Z80 Assembler Directives as for the Z80 supports some additional directives for compatibility with other assemblers These are the additional directives in as for the Z80 db expression stringl expression string defb expression string expression string For each string the characters are copied to the object file for each other expression the value is stored in one byte A warning is issued in case of an overflow dw expression expressi
515. tion 200 9 27 9 Directives to record which NaN encoding is being used 201 9 27 10 Directives to save and restore options 201 9 27 11 Directives to control generation of MIPS ASE instructions 202 9 27 12 Directives to override floating point options 202 9 27 13 Syntactical considerations for the MIPS assembler 202 9 27 13 1 Special Character 202 9 28 MMIX Dependent Features 0 0 c eee eens 204 9 28 1 Command line Option 204 9 28 2 Instruction expansion 0 eee eee ee 205 9 28 9 EE sesepi iie d nene dd ig dE ENER eae 205 9 28 3 1 Special Character 205 0 28 3 2 Symbols ces adedens svete e hee ene de ds 206 9 28 8 8 Register name 206 9 28 3 4 Assembler Directive 207 9 28 4 Differences to mmixal 0 ccc eee eee eee 209 9 29 MSP 430 Dependent Features 0 0 c cece cece 211 9201 E enee 211 9 20 2 Synla X ll see sares EE Sie EE E I RE sede R 211 9 20 2 1 Maerog e Ee NEE SEN RR eterna 211 9 29 2 2 Special Character SEL 9 29 2 3 Register Names 0 cece eee eee eee eee 212 9 29 2 4 Assembler Extensions lesse esses 212 9 29 3 Floating Pot asec eer s be Re 213 9 29 4 MSP 430 Machine Directive 213 9 20 5 geegent here rhe ie oud N E ak 213 9 29 6 Profiling Capability euge dE e Pave dee Reps 213 9 30 Nios II Dependent Features 215 9 30 1 Options 2 e die sawed PU
516. tion 3 6 1 1 Strings page 29 each character of that string is emitted as a byte Other operands must be constant expressions without forward references in the range 0 255 If you need operands hav ing expressions with forward references use byte see Section 7 10 Byte page 50 An operand can be omitted defaulting to a zero value The directives WYDE TETRA and OCTA emit constants of two four and eight bytes size respectively Before anything else happens for the directive the Chapter 9 Machine Dependent Features 209 current location is aligned to the respective constant size boundary If a label is defined at the beginning of the line its value will be that after the alignment A single operand can be omitted defaulting to a zero value emitted for the directive Operands can be expressed as strings see Section 3 6 1 1 Strings page 29 in which case each character in the string is emitted as a separate constant of the size indicated by the directive PREFIX The PREFIX directive sets a symbol name prefix to be prepended to all sym bols except local symbols see Section 9 28 3 2 MMIX Symbols page 206 that are not prefixed with until the next PREFIX directive Such prefixes accumulate For example PREFIX a PREFIX b c IS 0 defines a symbol abc with the value 0 BSPEC ESPEC A pair of BSPEC and ESPEC directives delimit a section of special contents wi
517. tion 7 87 PopSection page 66 and previous see Section 7 88 Previous page 66 This directive replaces the current subsection with name The current section is not changed The replaced subsection is put onto the section stack in place of the then current top of stack subsection 7 111 symver Use the symver directive to bind symbols to specific version nodes within a source file This is only supported on ELF platforms and is typically used when assembling files to be linked into a shared library There are cases where it may make sense to use this in objects to be bound into an application itself so as to override a versioned symbol from a shared library For ELF targets the symver directive can be used like this Chapter 7 Assembler Directives 75 symver name name2 nodename If the symbol name is defined within the file being assembled the symver directive effectively creates a symbol alias with the name name2 nodename and in fact the main reason that we just don t try and create a regular alias is that the character isn t permitted in symbol names The name2 part of the name is the actual name of the symbol by which it will be externally referenced The name name itself is merely a name of convenience that is used so that it is possible to have definitions for multiple versions of a function within a single source file and so that the compiler can unambiguously know which version of a function is being mentioned The
518. tion can obtained by enclosing an operand inside of Agdop hix22 The R_SPARC_GOTDATA_OP_LOX10 relocation can obtained by en closing an operand inside of 4gdop loxi0 Likewise RLSPARC_GOTDATA_OP can be ob tained by enclosing an operand inside of gdop For example assuming the GOT base is in register 417 sethi gdop hix22 symbol 11 xor 411 gdop loxiO symbol 11 ld 417 411 412 V4gdop symbol There are many relocations that can be requested for access to thread local storage variables All of the Sparc TLS mnemonics are supported e R SPARC TLS OD HI22 is requested using 4tgd hi22 e R SPARC TLS OD L010 is requested using 4tgd 1010 e R_SPARC_TLS_GD_ADD is requested using tgd_add e R SPARC TLS OD CALL is requested using red call e R SPARC TLS LDM HI22 is requested using t1ldm_hi22 e R_SPARC_TLS_LDM_LO10 is requested using tldm 1010 e R SPARC TLS LDM ADD is requested using 4tldm add e R SPARC TLS LDM CALL is requested using 4tldm call e R_SPARC_TLS_LDO_HIX22 is requested using t1ldo_hix22 e R_SPARC_TLS_LDO_LOX10 is requested using t1do_1lox10 e R_SPARC_TLS_LDO_ADD is requested using 4tldo add e R SPARC TLS IE HI22 is requested using Atie_hi22 e R SPARC TLS IE LO010 is requested using tie 1010 Chapter 9 Machine Dependent Features 261 R_SPARC_TLS_IE_LD is requested using rie Ld R_SPARC_TLS_IE_LDX is requested using tie_ldx R_SPARC_T
519. to the end of the current line Note that if a line starts with a character then it can also be a logical line number directive see Section 3 3 Comments page 27 or a preprocessor control command see Section 3 1 Preprocessing page 27 A semicolon can be used to separate multiple statements on the same line 9 20 3 Opcodes For detailed information on the LM32 machine instruction set see http www latticesemi com products i as implements all the standard LM32 opcodes 170 Using as 9 21 M32C Dependent Features as can assemble code for several different members of the Renesas M32C family Normally the default is to assemble code for the M16C microprocessor The m32c option may be used to change the default to the M32C microprocessor 9 21 1 M32C Options The Renesas M32C version of as has these machine dependent options m32c Assemble M32C instructions mi6c Assemble M16C instructions default relax Enable support for link time relaxations h tick hex Support H 00 style hex constants in addition to 0x00 style 9 21 2 M32C Syntax 9 21 2 1 Symbolic Operand Modifiers The assembler supports several modifiers when using symbol addresses in M32C instruction operands The general syntax is the following 4modifier symbol Adsp8 Adspi6 These modifiers override the assembler s assumptions about how big a sym bol s address is Normally when it sees an operand like sym a0 it assumes
520. to the shortest fitting instruction of addoq addo w and addo d when used with a operand that is a constant known at assembly time 9 8 3 Symbols Some symbols are defined by the assembler They re intended to be used in conditional assembly for example if asm arch cris v32 code for CRIS v32 elseif asm arch cris common_vi0_v32 code common to CRIS v32 and CRIS v10 elseif asm arch cris vi0O asm arch cris any vO vi10 code for v10 else error Code needs to be added here endif These symbols are defined in the assembler reflecting command line options either when specified or the default They are always defined to 0 or 1 asm arch cris any vO vi10 This symbol is non zero when march v0O_v10 is specified or the default asm arch cris common_vi0_v32 Set according to the option march common_v10_v32 asm arch cris vi0 Reflects the option march v10 asm arch cris v32 Corresponds to march v10 Speaking of symbols when a symbol is used in code it can have a suffix modifying its value for use in position independent code See Section 9 8 4 2 CRIS Pic page 122 122 Using as 9 8 4 Syntax There are different aspects of the CRIS assembly syntax 9 8 4 1 Special Characters The character is a line comment character It starts a comment if and only if it is placed at the beginning of a line A character starts a comment anywhere on the line causing
521. tors i etecec cce wae ses aa 248 SH machine directives 0 000 e eee 250 SH opcode summ are 250 SH Options 4 sairaana onai Aea S 248 SH TePisters ue rea aae ER D 249 SH SUPPO ees At pais e dees wees 248 SH64 ABI options erssicsceitis riar unn ena 251 SH64 addressing modes 252 SH64 ISA Options ciis erresa news ceeds 251 SH64 line comment character 251 SH64 line separator eese 251 SH64 machine directe 252 SH64 opcode summary 253 SHOA options suet EEE ENERE 251 SH64 registers eese rer pUR Rene YVES 252 SHOA SuppOEt Jenner rpm itte eee 251 shigh directive M32R eee R 173 shortditecive sre esinin ieni cde cies T2 short directive ARC 94 short directive TIOR4N 269 SIMD RE EELER REESEN EES des 152 SIMD X86 64 c eua e ekee Eh A 152 single character constant seresrecress 30 single directive cci imber e taisi 72 single directive i386 6000 eee e ees 152 single directive x86 64 006 152 single quote Z80 ios cete e perti 287 sixteen bit integers ee eee eee 5T sixteen byte jnteger r crcrererei aciri re nersini 65 size directive COFF version 72 size directive ELF version 72 size modifiers DIV 2000s eee 125 size modifiers D30V 20 ee eee ee 129 size modifiers Mot 179 size prefixes 1380 2 senec degi Eu I ANERE 150 size suffixes HS 200 136 size translations Sparc eee eee eee
522. ts in register 5 putting the result into register 6 Computes the lower 16 bits of the given expression and stores it into the im mediate operand field of the given instruction For example addi lo here there r5 r6 computes the difference between the address of labels here and there takes the lower 16 bits of this difference and adds it to register 5 putting the result into register 6 Computes the higher 16 bits of the given expression and then adds the value of the most significant bit of the lower 16 bits of the expression and stores the result into the immediate operand field of the given instruction For example the following code can be used to compute the address of the label here and store it into register 6 movhi hi here r0 r6 movea lo here r6 r6 The reason for this special behaviour is that movea performs a sign exten sion on its immediate operand So for example if the address of here was OxFFFFFFFF then without the special behaviour of the hi pseudo op the movhi instruction would put OxFFFF0000 into r6 then the movea instruc tion would takes its immediate operand OxFFFF sign extend it to 32 bits OxFFFFFFFF and then add it into r6 giving OXFFFEFFFF which is wrong the fifth nibble is E With the hi pseudo op adding in the top bit of the lo pseudo op the movhi instruction actually stores 0 into r6 OxFFFF 1 0x0000 so that the movea instruction stores 0xFFFFFFFF into r6
523. u do not see such symbols when debugging because they are intended for the use of programs like compilers that compose assembler programs not for your notice Normally both as and 1d discard such symbols so you do not normally debug with them This option tells as to retain those local symbols in the object file Usually if you do this you also tell the linker 1d to preserve those symbols 6 2 8 Configuring listing output listing The listing feature of the assembler can be enabled via the command line switch a see Section 2 1 a page 21 This feature combines the input source file s with a hex dump of the corresponding locations in the output object file and displays them as a listing file The format of this listing can be controlled by directives inside the assembler source i e List see Section 7 73 List page 61 title see Section 7 114 Title page 75 sbtt1 see Section 7 97 Sbttl page 69 psize see Section 7 91 Psize page 67 and eject see Section 7 38 Eject page 53 and also by the following switches Chapter 2 Command Line Options 23 listing lhs width number Sets the maximum width in words of the first line of the hex byte dump This dump appears on the left hand side of the listing output listing lhs width2 number Sets the maximum width in words of any further lines of the hex byte dump for a given input source line If this value is not specified it def
524. ubsequent RX RS and SS form instruc tions The expr will be evaluated to obtain the base address usually expr will merely be ai This assembler allows two using directives to be simultaneously outstanding one in the text section and one in another section typically the data section This feature allows dynamically loaded objects to be implemented in a relatively straightforward way A using directive must always be specified in the text section this will specify the base register that will be used for branches in the text section A second using may be specified in another section this will specify the base register that is used for non label address literals When a second using is specified then the subsequent 1torg must be put in the same section otherwise an error will result Thus for example the following code uses r3 to address branch targets and r4 to address the literal pool which has been written to the data section The 144 Using as is the constants A some_routine H 42 and E 3 1416 will all appear in the data section data using LITPOOL r4 text BASR r3 0 using r3 B START long LITPOOL START L r4 4 r3 L r 5 A some routine LTR r1i5 r1i5 BNE LABEL AH r0 H 42 LABEL ME r6 E 3 1416 data LITPOOL ltorg Note that this dual using directive semantics extends and is not compatible with HLASM semantics Note that this assembler directive does not support t
525. uction has an operand size prefix Instruc tion prefixes are best written on the same line as the instruction they act upon For example the scas scan string instruction is repeated with repne scas es edi al You may also place prefixes on the lines immediately preceding the instruction but this circumvents checks that as does with prefixes and will not work with all prefixes Here is a list of instruction prefixes e Section override prefixes cs ds ss es fs gs These are automatically added by specifying using the section memory operand form for memory references e Operand Address size prefixes data16 and addr16 change 32 bit operands addresses into 16 bit operands addresses while data32 and addr32 change 16 bit ones in a code16 section into 32 bit operands addresses These prefixes must appear on the same line of code as the instruction they modify For example in a 16 bit code16 section you might write addr32 jmpl ebx e The bus lock prefix lock inhibits interrupts during execution of the instruction it precedes This is only valid with certain instructions see a 80386 manual for details e The wait for coprocessor prefix wait waits for the coprocessor to complete the current instruction This should never be needed for the 80386 80387 combination e The rep repe and repne prefixes are added to string instr
526. uctions to make them repeat Zecx times es times if the current address size is 16 bits e The rex family of prefixes is used by x86 64 to encode extensions to 1386 instruction set The rex prefix has four bits an operand size overwrite 64 used to change operand size from 32 bit to 64 bit and X Y and Z extensions bits used to extend the register set You may write the rex prefixes directly The rex64xyz instruction emits rex prefix with all the bits set By omitting the 64 x y or z you may write other prefixes as well Normally there is no need to write the prefixes explicitly since gas will automatically generate them based on the instruction operands 9 15 8 Memory References An Intel syntax indirect memory reference of the form section base index scale disp is translated into the AT amp T syntax section disp base index scale where base and index are the optional 32 bit base and index registers disp is the optional displacement and scale taking the values 1 2 4 and 8 multiplies index to calculate the address of the operand If no scale is specified scale is taken to be 1 section specifies the optional section register for the memory operand and may override the default section register see a 80386 manual for section register defaults Note that section overrides in Chapter 9 Machine Dependent Features 151 AT amp T syntax must be preceded by a If you spec
527. uliprOCc 2we ke oe eee eed ERR RE RR 220 EUR dE RENE EELER RENE nen wens 220 mnaked reg option i386 146 mnaked reg option x86 64 146 mnan command line option MIPS 197 eh e 219 IDDO CSI ikea v 9 9 Cnr e ri ud e WEN 219 mno dsbt command line option TIC6X 274 MNO C1S 42524 dak ae Sees sees E tees ows 219 MNO ExteNSiONS esere cess pea wp ITI EES 219 mno fdpic command line option Blackfin 114 e EE 219 he We iru dee ait RR RR I eave PIERII 219 e EE 219 IDBOSIDU eos cated sGied paredh occ dag RERUM 219 mno keyll 2 24x 9 1 4 b RARE EELPRTGSR 219 mno limited eis cece eee eee eee eee 219 mno rafpl AUEREN Goa eek vee ee 220 MMo Microcode 1 eee 220 mno muliproC sai aci ek ect eee eee denne 220 ek le EE 220 HEI ce coos aa ede eee EEN 219 mno pic command line option TIC6X 274 mno regnames option s890 231 mno skip bug command line option AVR 109 SInhosspl zaras e eege dg 220 le EEN 196 mno wrap command line option AVR 109 mnopic command line option Blackfin 114 Geh EE 219 mpic command line option TIC6X 274 PMP UA fe 6 4 asserted pea asdiate nda A lend RES 228 mpid command line option TIC6X 274 Using as mregnames option s 00 231 mrelax command line option V850 296 mrh850 abi command line option V850
528. unsigned overflow command line option V850 EE 295 x command line option MMIX 204 z80 command line option Z80 286 z8001 command line option Z8000 289 z8002 command line option Z8000 289 Symbol cnet ame PEERS E RU BEES 41 2byte directive ARM 99 Abyte directive ARM 99 8byte directive ARM 99 align directive ARM 99 align directive TILE Gx 280 align directive TILEPro 285 allow suspicious bundles directive TILE Gx mu rr 280 allow suspicious bundles directive TILEPro EE EE 285 arch directive ARM 99 arch directive TIGCOX isi sorerescrisiinerias 275 arch extension directive ARM 99 arm directive ARM 99 big directive M32RX ENEE 174 bss directive AArch64 suusuunnnnnnnn 83 bss directive ARM 99 c6xabi attribute directive TIC6X 215 cantunwind directive ARM 99 cantunwind directive TIC6X 275 code directive ARM 100 cpu directive ARM 100 dn and on directives ARM 100 eabi attribute directive ARM 100 ehtype directive TIC6X ssueus 275 endp directive TICOX erosrcnirieiseurssisina 275 even directive ARM 101 extend directive ARM 101 fnend directive ARM 101 fnstart directive ARM 101 333 force thumb directive ARM 101 fpu directive ARM
529. ura 269 LOOP instructions alignment 308 low directive M32R 2 0 cece ee ate 173 lp register VSbn ii cesses tee ER RA 298 D roM 290 LWP 39802 eu ERE E CH pee ane bee E 153 UWP X80 cubus IR p REN RRSIEERA RA 153 M M16C architecture option 170 M32C architecture option 170 M32C line comment character Trd M320 line separator seen ee eee Nei M320 modifiers nous ape ere tempe EE 170 M320 le RE 170 M320 SEENEN 170 M32R architecture options sssesssse Te M32R directives uere tr Rte Ren 173 M32R E LEE 172 WIEN e EE 172 M32R warnihgs m ree erm m eene 174 M680x0 addressing modes T79 M680x0 architecture option IZT M680x0 branch improvement 182 M680x0 directives 0 cece eee eee 181 M680x0 floating point 00 181 M680x0 immediate character 183 M680x0 line comment character 183 M680x0 line separator 0 00 eee eee 183 M680x0 opcodes 22 c eee eee eee eee ee 182 M680x0 options nsn eR rh reg 176 M680x0 pseudo opcodes eee eee 182 AS Index M680x0 size modifiers 00 cee 179 M680x0 SUPPO t ie5 cree rire ad snes eas eee 176 MD680x syntax czetenn eter pREEC phe E pe oe 179 M68HC11 addressing modes 185 M68HC11 and M68HC12 support 184 M68HC11 assembler directive
530. ure independent attributes and clear for architecture dependent ones 8 1 1 Common GNU attributes These attributes are valid on all architectures Tag_compatibility 32 The compatibility attribute takes an integer flag value and a vendor name If the flag value is 0 the file is compatible with other toolchains If it is 1 then the file is only compatible with the named toolchain If it is greater than 1 the file can only be processed by other toolchains under some private arrangement indicated by the flag value and the vendor name 8 1 2 MIPS Attributes Tag GNU_MIPS_ABI_FP 4 The floating point ABI used by this object file The value will be e 0 for files not affected by the floating point ABI e 1 for files using the hardware floating point with a standard double precision FPU e 2 for files using the hardware floating point ABI with a single precision FPU 80 Using as e 3 for files using the software floating point ABI e 4 for files using the hardware floating point ABI with 64 bit wide double precision floating point registers and 32 bit wide general purpose registers 8 1 3 PowerPC Attributes Tag GNU Power ABI FP 4 The floating point ABI used by this object file The value will be e 0 for files not affected by the floating point ABI e 1 for files using double precision hardware floating point ABI e 2 for files using the software floating point ABI e 3 for files using single precision hardware floating point ABI
531. ures 153 9 15 12 AMD s Lightweight Profiling Instructions as supports AMD s Lightweight Profiling LWP instruction set available on AMD s Family 15h Orochi processors LWP enables applications to collect and manage performance data and react to per formance events The collection of performance data requires no context switches LWP runs in the context of a thread and so several counters can be used independently across multiple threads LWP can be used in both 64 bit and legacy 32 bit modes For detailed information on the LWP instruction set see the AMD Lightweight Profiling Specification available at Lightweight Profiling Specification 9 15 13 Bit Manipulation Instructions as supports the Bit Manipulation BMI instruction set BMI instructions provide several instructions implementing individual bit manipulation operations such as isolation masking setting or resetting 9 15 14 AMD s Trailing Bit Manipulation Instructions as supports AMD s Trailing Bit Manipulation TBM instruction set available on AMD s BDVERJ2 processors Trinity and Viperfish TBM instructions provide instructions implementing individual bit manipulation op erations such as isolating masking setting resetting complementing and operations on trailing zeros and ones 9 15 15 Writing 16 bit Code While as normally writes only pure 32 bit 1386 code or 64 bit x86 64 code depending on the default configuration it also supports writing
532. useful when splitting up a mmixal program into several files The gnu syntax turns off most syntax compatibility with mmixal Its usability is currently doubtful The relax option is not fully supported but will eventually make the object file prepared for linker relaxation If you want to avoid inadvertently calling a predefined symbol and would rather get an error for example when using as with a compiler or other machine generated code specify no predefined syms This turns off built in predefined definitions of all such symbols including rounding mode symbols segment symbols BIT symbols and TRAP symbols used in mmix system calls It also turns off predefined special register names except when used in PUT and GET instructions By default some instructions are expanded to fit the size of the operand or an external symbol see Section 9 28 2 MMIX Expand page 205 By passing no expand no such expansion will be done instead causing errors at link time if the operand does not fit The mmixal documentation see mmixsite page 205 specifies that global registers allocated with the GREG directive see MMIX greg page 207 and initialized to the same non zero value will refer to the same global register This isn t strictly enforceable in as since the final addresses aren t known until link time but it will do an effort unless the no merge gregs option is specified Regis
533. using curly braces add r3 r4 r5 add r7 r8 r9 lw r10 ri1 A bundle can span multiple lines If you want to put multiple instructions on a line whether in a bundle or not you need to separate them with semicolons as in this example A bundle may contain one or more instructions up to the limit specified by the ISA currently three If fewer instructions are specified than the hardware supports in a bundle the assembler inserts fnop instructions automatically The assembler will prefer to preserve the ordering of instructions within the bundle putting the first instruction in a lower numbered pipeline than the next one etc This fact combined with the optional use of explicit fnop or nop instructions allows precise control over which pipeline executes each instruction If the instructions cannot be bundled in the listed order the assembler will automatically try to find a valid pipeline assignment If there is no way to bundle the instructions together the assembler reports an error The assembler does not yet auto bundle automatically combine multiple instructions into one bundle but it reserves the right to do so in the future If you want to force an instruction to run by itself put it in a bundle explicitly with curly braces and use nop instructions not fnop to fill the remaining pipeline slots in that bundle 9 44 2 1 Opcode Names For a complete list of opcodes and descriptions of their semantics see TILE Gx Instruction
534. ust a shorthand so that multiplying eax by 69 for example can be done with imul 69 eax rather than imul 69 eax eax 156 Using as 9 16 Intel i860 Dependent Features 9 16 1 i860 Notes This is a fairly complete i860 assembler which is compatible with the UNIX System V 860 Release 4 assembler However it does not currently support SVR4 PIC De GOT GOTOFF PLT Like the SVR4 860 assembler the output object format is ELF32 Currently this is the only supported object format If there is sufficient interest other formats such as COFF may be implemented Both the Intel and AT amp T SVRA syntaxes are supported with the latter being the default One difference is that AT amp T syntax requires the prefix on register names while Intel syntax does not Another difference is in the specification of relocatable expressions The Intel syntax is haZexpression whereas the SVR4 syntax is expression ha and similarly for the 1 and h selectors 9 16 2 i860 Command line Options 9 16 2 1 SVR4 compatibility options V Print assembler version Qy Ignored Qn Ignored 9 16 2 2 Other options EL Select little endian output this is the default EB Select big endian output Note that the 1860 always reads instructions as little endian data so this option only effects data and not instructions mwarn expand Emit a warning message if any pseudo instruction expansions occurred For ex ample a
535. ut it is accepted to make it more likely that scripts written for other assemblers also work with as 2 4 Work Faster f should only be used when assembling programs written by a trusted compiler f stops the assembler from doing whitespace and comment preprocessing on the input file s before assembling them See Section 3 1 Preprocessing page 27 Warning if you use f when the files actually need to be preprocessed if they contain comments for example as does not work correctly 2 5 include Search Path I path Use this option to add a path to the list of directories as searches for files specified in include directives see Section 7 64 include page 58 You may use I as many times as necessary to include a variety of paths The current working directory is always searched first after that as searches any I directories in the same order as they were specified left to right on the command line 2 6 Difference Tables K as sometimes alters the code emitted for directives of the form word symi sym2 See Section 7 124 word page 78 You can use the K option if you want a warning issued when this is done 2 7 Include Local Symbols L Symbols beginning with system specific local label prefixes typically L for ELF systems or L for traditional a out systems are called local symbols See Section 5 3 Symbol Names page 39 Normally yo
536. v8plus Av8plusa Av9 Av9a xarch v8plus xarch v8plusa bump 32 1 64 Target TIC54X options mcpu 54 123589 mcpu 54 56 lp mfar mode mf merrors to file lt filename gt me lt filename gt Target TIC6X options march arch mbig endian mlittle endian mdsbt mno dsbt mpid no mpid near mpid far mpic mno pic Target TILE Gx options m32 m64 EB EL Target Xtensa options no text section literals no absolute literals no target align no longcalls no transform rename section oldname newname Target Z80 options 280 r800 ignore undocumented instructions Wnud ignore unportable instructions Wnup warn undocumented instructions Wud Using as Chapter 1 Overview 5 warn unportable instructions Wup forbid undocumented instructions Fud forbid unportable instructions Fup file Read command line options from file The options read are inserted in place of the original file option If file does not exist or cannot be read then the option will be treated literally and not removed Options in file are separated by whitespace A whitespace character may be included in an option by surrounding the entire option in either single or double quotes Any character including a backslash may be included by prefixing the character to be included with a backslash The file may itself contain additional file opti
537. ve Register require a register pair Register pairs are always data registers and are denoted using a colon eg R3 2 The larger number must be written firsts Note that the hardware only supports odd even pairs eg R7 6 R5 4 R3 2 and R1 0 Some instructions such as SP Push Multiple require a group of adjacent registers Adjacent registers are denoted in the syntax by the range enclosed in parentheses and separated by a colon eg R7 3 Again the larger number appears first Portions of a particular register may be individually specified This is written with a dot following the register name and then a letter denoting the desired portion For 32 bit registers H denotes the most significant High portion L denotes the least significant portion The subdivisions of the 40 bit registers are described later Accumulators The set of 40 bit registers Al and AO that normally contain data that is being manipulated Each accumulator can be accessed in four ways one 40 bit register The register will be referred to as Al or AO one 32 bit register The registers are designated as A1 W or A0 W two 16 bit registers The registers are designated as A1 H Al L A0 H or AO L one 8 bit register The registers are designated as Al X or AO X for the bits that extend beyond bit 31 Data Registers The set of 32 bit registers RO R1 R2 R3 RA R5 R6 and R7 that normally contain data for manipulation These are abbr
538. w flag b Same as flag 7 carry borrow flag 9 10 2 6 Addressing Modes as understands the following addressing modes for the D30V Rn in the following refers to any of the numbered registers but not the control registers Rn Register direct Rn Register indirect Rn Register indirect with post increment Rn Register indirect with post decrement SP Register indirect with pre decrement disp Rn Register indirect with displacement addr PC relative address for branch or rep imm Immediate data the is optional and ignored 9 10 3 Floating Point The D30V has no hardware floating point but the float and double directives generates IEEE floating point numbers for compatibility with other development tools 9 10 4 Opcodes For detailed information on the D30V machine instruction set see D30V Architecture A VLIW Microprocessor for Multimedia Applications Mitsubishi Electric Corp as imple ments all the standard D30V opcodes The only changes are those described in the section on size modifiers Chapter 9 Machine Dependent Features 133 9 11 Epiphany Dependent Features 9 11 1 Options as has two additional command line options for the Epiphany architecture mepiphany Specifies that the both 32 and 16 bit instructions are allowed This is the default behavior mepiphanyi6 Restricts the permitted instructions to just the 16 bit set 9 11 2 Epiphany Syntax 9 11 2 1 Special Characters The pres
539. w the assembler to accept instructions valid for any ARM processor In addition to the basic instruction set the assembler can be told to accept various extension mnemonics that extend the processor using the co processor instruction space For example mcpu arm920 maverick is equivalent to spec ifying mcpu ep9312 Multiple extensions may be specified separated by a The extensions should be specified in ascending alphabetical order Some extensions may be restricted to particular architectures this is docu mented in the list of extensions below Extension mnemonics may also be removed from those the assembler accepts This is done be prepending no to the option that adds the extension Extensions that are removed should be listed after all extensions which have been added again in ascending alphabetical order For example mcpu ep9312 nomaverick is equivalent to specifying mcpu arm920 The following extensions are currently supported crypto Cryptography Ex tensions for v8 A architecture implies fp simd fp Floating Point Extensions for v8 A architecture idiv Integer Divide Extensions for v7 A and v7 R ar chitectures iwmmxt iwmmxt2 maverick mp Multiprocessing Extensions for v7 A and v7 R architectures os Operating System for v6M architecture sec 96 Using as Security Extensions for v6K and v7 A architectures simd Advanced SIMD Extensions for v8 A architecture implies fp virt Virtualization Extensio
540. will issue a warning when a misaligned word long or quad directive is used You may use uaword ualong or uaquad to indicate that the value is intentionally misaligned 9 39 5 Opcodes For detailed information on the SH machine instruction set see SH Microcomputer User s Manual Renesas or SH 4 32 bit CPU Core Architecture SuperH and SuperH SH 64 Bit RISC Series SuperH as implements all the standard SH opcodes No additional pseudo instructions are needed on this family Note however that because as supports a simpler form of PC relative addressing you may simply write for example mov l bar r0O where other assemblers might require an explicit displacement to bar from the program counter mov l disp PC Chapter 9 Machine Dependent Features 251 9 40 SuperH SH64 Dependent Features 9 40 1 Options isa sh4 sh4a Specify the sh4 or sh4a instruction set isa dsp Enable sh dsp insns and disable sh3e sh4 insns isa fp Enable sh2e sh3e sh4 and sh4a insn sets isa all Enable sh1 sh2 sh2e sh3 sh3e sh4 sh4a and sh dsp insn sets isa shmedia isa shcompact Specify the default instruction set SHmedia specifies the 32 bit opcodes and SHcompact specifies the 16 bit opcodes compatible with previous SH families The default depends on the ABI selected the default for the 64 bit ABI is SHmedia and the default for the 32 bit ABI is SHcompact If neither the ABI nor the ISA is specified the default i
541. yields the same value as hw1 plt but it also checks that the value does not overflow hw2 last plt This modifier is used to load bits 32 47 of the pc relative address of a plt entry and it also checks that the value does not overflow hwO tls gd This modifier is used to load bits 0 15 of the offset of the GOT entry of the symbol s TLS descriptor to be used for general dynamic TLS accesses hwO last tls gd This modifier yields the same value as hwO Cla gd but it also checks that the value does not overflow hwi last tls gd This modifier is used to load bits 16 31 of the offset of the GOT entry of the symbol s TLS descriptor to be used for general dynamic TLS accesses It also checks that the value does not overflow 280 Using as hwO_tls_ie This modifier is used to load bits 0 15 of the offset of the GOT entry containing the offset of the symbol s address from the TCB to be used for initial exec TLS accesses hwO last tls ie This modifier yields the same value as hwO Cla ie but it also checks that the value does not overflow hwi last tls ie This modifier is used to load bits 16 31 of the offset of the GOT entry containing the offset of the symbol s address from the T CB to be used for initial exec TLS accesses It also checks that the value does not overflow hwO tls le This modifier is used to load bits 0 15 of the offset of the symbol s address from the TCB to be used for local exec TLS accesses hwO
542. ymbol aligned to the power of two specified by align length and align must be positive absolute expressions This directive differs from 1comm only in that it permits you to specify an alignment See Section 7 69 1comm page 60 extended flonums extended expects zero or more flonums separated by commas for each flonum extended emits an IEEE extended format 80 bit floating point number leafproc call lab bal lab You can use the leafproc directive in conjunction with the optimized call instruction to enable faster calls of leaf procedures If a procedure is known to call no other procedures you may define an entry point that skips procedure prolog code and that does not depend on system supplied saved context and declare it as the bal lab using leafproc If the procedure also has an entry point that goes through the normal prolog you can specify that entry point as call lab A leafproc declaration is meant for use in conjunction with the optimized call instruction callj the directive records the data needed later to choose between converting the callj into a bal or a call call lab is optional if only one argument is present or if the two arguments are identical the single argument is assumed to be the bal entry point Sysproc name index The sysproc directive defines a name for a system procedure After you define it using sysproc you can use name to refer to the
543. yntax the instruction name comes first and it may be followed by up to three operands Operands are separated by commas as will complain if too many operands are specified for a given instruction The same will happen if you specified too few operands nop ldl 23 CMP R1 R2 The presence of a character or a character anywhere on a line indicates the start of a comment that extends to the end of that line A or a t character at the start of a line also introduces a line comment but these characters do not work elsewhere on the line If the first character of the line is a then as well as starting a comment the line could also be logical line number directive see Section 3 3 Comments page 27 or a preprocessor control command see Section 3 1 Preprocessing page 27 The XGATE assembler does not currently support a line separator character The following addressing modes are understood for XGATE 6 Inherent Immediate 3 Bit Wide number Immediate 4 Bit Wide number 304 Immediate 8 Bit Wide number Monadic Addressing reg Dyadic Addressing reg reg Triadic Addressing reg reg reg Relative Addressing 9 Bit Wide symbol Relative Addressing 10 Bit Wide symbol Index Register plus Immediate Offset reg reg number Index Register plus Register Offset reg reg reg Index Register plus Register Offset with Post i

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