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S5N8947

1. 3 5 Example Code For lt Begin S gt 3 6 S5N8947 Table of Contents Continued Chapter 4 Exception Handling HNTOGUCTION P 4 1 Wa UP 4 2 Th Exception Vector Table ertet HU ERE ERE ER EO RUE BEEF EA 4 2 Entering amEXceptlohi cea x 4 3 Leaving anm EXCepltiODiss 4 4 Sample Exception Handler 1 erence eae neste eee nennen nns 4 4 Installing an Exception Handler 4 5 5 Controlling 55 8947 Modules S5N8947 Programmer s 5 1 Hardware YET 5 1 System Memory aaa 5 1 m 5 3 Example for System Manager Configuration Program 2 5 4 5 6 Example Code For Interrupt Handler 5 8 Example for Interrupt Setup Routine Header File Isr h a 5 9 Example Interrupt Setup R
2. 5 51 5 21 Concept Diagram for USB 5 53 5 22 Concept Diagram for USB Interrupt 5 54 5 23 Concept Diagram for USB Control Transfer 5 57 5 24 Concept Diagram for USB BulkOut 0 5 60 5 25 Concept Diagram for USB Bulkln Function 5 62 5 26 SAR cette erect 5 65 5 27 SAR Transmit 2 5 75 5 28 SAR RECEIVE Packet bei gb delata 5 79 5 29 SAR Interrupt Service 5 81 5 30 SAR Diagnosis EIOW iter eet t rm 5 84 5 31 Hyperterminal Window Display when Click the Send File in Pull down Menu 5 88 5 32 Hyperterminal Window Display when Xmodem File 5 89 5 33 Concept Diagram for Setting Up 5 91 5 34 PCMCIA Socket 5 98 S5N8947 vii Table Number 4 1 5 1 S5N8947 List of Tables Title Page Number General I O and the switch Configurations S5N8947 Evaluation 1 10 RJ45 Pin Configurations for Adapter
3. l mem Figure 1 4 System Clock Mode Selection and Functional Mode Selection System Clock Out MCLKO MCLKO is the same signal as internal system clock of S5N8947 This clock can be monitored at MCLKO pin If you want to use SDRAM with S5N8947 MCLKO should be used You can monitor it at MCLKO pin Ethernet Control Clock 25MHz crystal or oscillator have to be used for 10 100Mbps Ethernet PHY control clock In 55 8947 Board 25MHz oscillator is used External UART Clock S5N8947 support the External UART Clock input pin UCLK U12 But you can also use system clock source with internal PLL as a UART clock source 55 8947 Board the system clock source is used ELECTRONICS 1 7 ABOUT S5N8947 EVALUATION BOARD S5N8947 RESET LOGIC The nRESET System Reset Signal must be held to low level at least 540 master clock cycles to reset S5N8947 nRESET and nTRST JTAG Reset signal are anded logically But if you want to use circuit emulator ex Embedded ICE to dubug without BOOT ROM you should have the nTRST is floated If not whenever the ADW ARM Debug Window were invoked SW interrupt will be occurred S5N8947 System Configurations 55 8947 Board provides Big Little endian mode with S5N8947 and also contains a selectable resistor for the Byte Halfword Word size data bus access of ROM R176 R179 are used for the selection for the ROM access data bus size In S5N8947
4. RK SysInitVars Load up the linker defined values for the static data copy LDR r0 ImageSS ROSSLimit LDR rl ImageSSRWSSBase LDR r3 ImageSSZIS SBase p But first check whether we are trying to copy to the same address If so this means that the image was linked as an application image with the DATA section immediately following the CODE section Therefore there is nothing to copy since the data is already 1 r0 1 1 P Stop on CS ie Rl becomes gt R3 Carry has the same sense as 6502 i ie Carry NOT Borrow 0 CMP rl r3 LDRCC r2 r0 4 STRCC r2 r1 4 BCC 0 Clear remainder of data to ImageSSZISSLimit to 0 LDR rl ImageSSZISSLimit MOV r2 0 2 CMP rid STRCC r2 r3 4 BCC 2 MOV pc lr END ELECTRONICS 3 7 55 8947 NOTES 3 8 ELECTRONICS S5N8947 EXCEPTION HANDLING EXCEPTION HANDLING This chapter explains how exceptions are handled It also tells you how to set up an exception vector table and how to write an exception handler routine Information is presented according to the following Table of Contents INTRODUCTION An exceptions occurs when the normal flow of execution through a user program is diverted to allow the processor to handle events generated by internal or exter
5. eee eres nennen nennen nnn 5 91 Example Code for SPI Setup Function Routine lt gt 5 92 Example Code for SPI Write Function Routine lt gt 5 93 Example Code for SPI Read Function Routine spi C se e 5 95 PCMCIA Interface ate eee ea ua 5 97 Controlling the Power Switch 52214 5 99 Initialize PCMCIA Interface enne 5 99 Interrupt Service Routine for Card Detection enne 5 100 S5N8947 List of Figures Figure Title Page Number Number 1 1 S5N8947 Block Diagram 1 2 1 2 S5N8947 Block Diagram 2 sasay sayas 1 3 1 3 Detailed S5N8947 Board 1 6 1 4 System Clock Mode Selection and Functional Mode Selection 1 7 1 5 Boot Device Size Selection and Endian Mode Selection 1 8 1 6 Extended Device Chip Selection 1 9 1 7 ADSL Modem Clock Signal 1 10 2 1 S5N8947 Development Environment
6. 1 11 Ethernet Status 1 11 Exception Processing Modes and 4 2 MAC and BDMA Control Register Set 5 46 ix S5N8947 ABOUT S5N8947 EVALUATION BOARD ABOUT S5N8947 EVALUATION BOARD SYSTEM OVERVIEW S5N8947 Board supports a code development of SAMSUNG s S5N8947 16 32 bit RISC microcontroller for ADSL and Cable modem applications S5N8947 consists of 16 32 bit RISC ARM7TDMI CPU core 8 Kbyte unified cache 12 controller 2 channel 10 100 Mbps Ethernet controller SAR Segmentation and Reassembly UTOPIA the Universal Test amp Operations PHY Interface for ATM Interface Full rate USB controller 2 channel GDMA UART two 32 bit timers 18 programmable I O ports interrupt controller SPI interface PCMCIA interface and a system manager It also supports JTAG boundary scan for the application system testing S5N8947 Board consists of S5N8947 boot EEPROM Flash ROM DRAM module SDRAM UART serial communication port Ethernet interface with two external PHYs ATM25 PHY interface configuration switches and status LEDs The Ethernet interface has a complete IEEE802 3 physical layer interface with Ethernet hub router side RJ45 connector configuration ATM25 PHY interface chip is connected with S5N8947 with UTOPIA interface 55 8947 BOARD OVERVIEW S5N8947 Evaluation Board shows the basic system based hardware design which u
7. break case EPO_STATE_TRANSFER Print Transfer OK n endpointZeroState EPO_STATE_IDLE break case EPO_STATE_RECEIVER Print Receive OK n endpointZeroReceiver break ELECTRONICS 5 59 CONTROLLING S5N8947 MODULES S5N8947 USB BULKOUT TRANSFER ENDPOINT 1 3 USB BulkOut endpoint is endpoint that can receive endpoint 3 1 Check endpoint1 Interrupt 2 Store received data length in endpoint 3 3 Call endpoint BulkIn Function USB BulkOut Function When Endpoint 3 Interrupt occurs Call endpointBulkOutFunction Read E3RDS_REGISTER Call EndpointBulkInFunction USB BulkOut Function End Figure 5 24 Concept Diagram for USB BulkOut Function 5 60 ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES DIAGNOSTIC CODE USB BULKOUT TRANSFER ENDPOINT 1 3 endpointBulkOutFunction This is function for Endpoint Three Bulk Out function routine void endpointBulkOutFunction void ReadUsbRegister USB_E3RDS_REGISTER BulkOutCnt SetUsbRegister USB_E4SC_REGISTER 0x4000 Zero End Enable endpointBulkInFunction BulkOutdata BulkOutCnt ELECTRONICS 5 61 CONTROLLING S5N8947 MODULES S5N8947 USB BULKIN TRANSFER ENDPOINT 2 4 USB Bulkln endpoint is endpoint that can transmit endpoint2 4 1 Write the start address E4SA REGISTER 2 Write the size of data EATDS REGISTER
8. Entry point of RAM based project Hee ee AREA ROMBEGIN CODE READONLY ENTRY I EERE Ree ERRE KERERE ERER EEEE EREKE EREEREER CUR S Si EE REER E main Pseudo C entry point C compiler genereates reference to the symbol main to ensure that the object module containing the entry point gets pulled in This entry point is never actually called eee kuk S KUK EERE KERK RKE K EXPORT main main RomHdwInit Undefined Handler SWI Handler Prefetch Handler Abort Handler RomHdwInit IRO Handler FIQ Handler UJ UJ UJ UJ UJ UU UJ UJ Fr The Default Exception Handler Vector Entry Pointer Setup FIQ Handler SUB sp sp 4 STMFD sp r0 LDR r0 HandleFiq LDR rO r0 STR r0 sp 4 LDMFD sp xr0 pc IRO Handler SUB Sp sp 4 STMFD sp r0 LDR r0 HandleIrq LDR ro r0 STR rO sp 4 LDMFD sp r0 pc Prefetch Handler SUB Sp sp STMFD sp r0 LDR r0 HandlePrefetch LDR rO r0 STR r0 sp 4 LDMFD sp r0 pc 4 6 ELECTRONICS S5N8947 Abort_Handler STR LDMFD Sp sp 4 sp r0 r0 HandleAbort 150 50 rO sp 4 sp xr0 pc Undefined_Handler SUB TME D DR LDR STR LDMFD 9
9. con XIRQ_ENABLE Active Filtering Detect switch PortNum case IOPORT_8 break case IOPORT_9 con lt lt 5 break case IOPORT_10 con lt lt 10 break case IOPORT_11 con lt lt 15 break IOPCON con ZZ isr_XIrq_0 Interrupt Service Routine for External Interrupt Request 0 27 void 0 void Print xIRQ 0 Occurred ESC To EXIT Test n 12Print External IRQO ESC To EXIT isr XIrq 1 Interrupt Service Routine for External Interrupt Request 1 void isr 1 void Print n xIRQ_1 Occurred ESC To EXIT Test Nn 12Print External IRQ1 ESC To EXIT pm ELECTRONICS 5 39 CONTROLLING S5N8947 MODULES S5N8947 PORT TEST PROGRAM DESCRIPTION IN DIAGNOSTIC ROM S5N8947 Diagnostic program contains a program offers I O Port function test and shows the values of I O Port specific registers For the detail of these functions refer to I O Port diagnostic source code provided ioPort c Main Menu 47 66 1 0 Board Diagnostic Ver 1 0 Memory TEST UART TES Timer TEST TES I2C BUS TEST I O Port TEST Ethernet TEST USB Test SAR Test All Test User Program Download FLASH Memory Operation
10. if PktCnt 1 4 if strCFG SAR CHAN ChanNum PTI 4 strCFG SAR CHAN ChanNum PTI 5 strCFG SAR CHAN ChanNum PTI 6 OAM Cell pIxBufDesc PKT STATUS BD PKT 10 N strCFG SAR CHAN ChanNum PORT lt lt BD PHY SFT else if strCFG SAR CHAN ChanNum AAL AALCT PKT AALO AALO Cell pIxBufDesc PKT STATUS BD PKT AALO X strCFG SAR CHAN ChanNum PORT lt lt BD PHY SFT 15 if strCFG SAR CHAN ChanNum AAL AALCT PKT CRC10 CRC10 Cell pIxBufDesc PKT STATUS BD PKT 10 X strCFG SAR CHAN ChanNum PORT lt lt BD PHY SFT 1 Complete Packet pIxBufDesc PKT STATUS BD PKT AAL5 COMP N strCFG SAR CHAN ChanNum PORT lt lt BD PHY SFT else if i PktCnt 1 End Packet pIxBufDesc PKT STATUS BD PKT AAL5 END N strCFG SAR CHAN ChanNum PORT lt lt BD PHY SFT 1 Start or Middle Packet pIxBufDesc PKT STATUS BD PKT AAL5 STPMID N strCFG_SAR_CHAN ChanNum PORT lt lt BD PHY SFT LENGTH 1 switch 1 3 case 0 if PktCnt 1 if i 0 pTxBufDesc gt LENGTH 2048 strCFG SAR REG TRXALIGN else pIxBufDesc LENGTH 2048 1 pTxBufDesc LENGTH PktSize strCFG_SAR_REG TRXALIGN break case 1 if PktCnt 2 pTxBufDesc LENGTH 2048 else pTxBufDesc LENGTH PktSize 2048 break case 2 pTxBufDesc gt LENGTH PktSize 4096 break default ASSERT 0 break CELL HEAD pTIxBufDesc
11. LDR rl EXTHND BASE STR Fl CEL write to SDRAM base LDR r2 r1 read from SDRAM base CMP r2 rl compare above two data 5 if equal branch to SetSVC else set SDRAM environment rod EDO DRAM setting 27 EDO DRAM CONFIGURATION LDR r0 0x3FF0000 LDR rl 0x23FF0004 Start addr Ox3FF00000 STR rl r0 Cache OFF Write Buffer ON i Initialize Memory Configuration This operation must be done at a time f ADRL r0 SystemInitData_EDO LDMIA 0 1 10 LDR r0 0 3 0000 0x3010 ROMCON Offset 0x3010 STMIA rO rl r10 Additional code 5 4 UU NE i a S iT inc S5N8947 ELECTRONICS CONTROLLING S5N8947 MODULES S5N8947 77 System Memory Initialization Data For more refer to the S5N8947 User s Manual rf SystemInitData_EDO DCD OxOFFFFFFa 32bit data bus EXTDBWTH DCD 0x02000060 0x0000000 01 ROMCONO DCD 0x04008040 0x0200000 OxO3FFFFF ROMCON1 DCD 0x06010040 0 0400000 OxO5FFFFF ROMCON2 DCD 0 0 0 0600000 OxO7FFFFF PCMOFFSET DCD 0x9804039b 0 1000000 Ox17FFFFF DRAMCONO DCD 0 0 0 1800000 OxlBFFFFF DRAMCON1 DCD 0x9C0601AC 0x1800000 OxlBFFFFF DRAMCON2 DCD 0 00701 0 1 00000 DRAMCON3 DCD 0 9 398360 Refresh enabl REFEXTCON SystemInitData_SDRAM DCD OxOFFFFFFa 32bit data bus EX
12. OU S Q N P Select One 5 40 ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES Selecting 6 Port test at main menu shows sub menu of I O Port test below IO Port Test Menu Mn IO Port Read port 0 7 IO Port Write port 0 7 External Interrupt Test port 5 11 View Configuration IOPDATA Read Input mode Exit IO Port Test 03 ccc 1 2 3 4 5 Q Select One 1 IO Port Read port 0 7 2 IO Port Write port 0 7 In S5N8947 Evaluation board I O Ports 0 through 7 are connected to LEDs D12 D19 If you read I O Port 0 7 It reflects LEDs status If you write a value to I O Port 0 7 the LEDs reflect the value you wrote The LED is off when you write 1 to corresponding Port and the LED is on if you write 0 to the port With sub menu 1 and 2 you can read and write to I O Port and check the result from the LEDs status 3 External Interrupt Test port 5 11 Ports 5 11 are used for External Interrupt Request input ports In our 5538947 Evaluation board these are connected to 4 push button SWs With this SWs you can test External Interrupts In this function if you push one of the SWs S4 S7 you will see the message says external interrupts occurrence 4 View Configuration Shows the values of I O Port specific registers 5 IOPDATA Read Input mode You can configure the Por
13. 8 USB Test S SAR Test A All Test U User Program Download F FLASH Memory Operation Select One Select User Program Download with typing u at the cursor and you will see the message below SYSTEM INFORMATION ROMO BASE Ox 0 ROM1 BASE Ox 200000 DRAM BASE Ox 1000000 Input Download Area Address default 0x1000050 Ox Just press Enter If you want to change the download start address you have to re burn your ROM after changing HOMOPTS in make file DownLoad User s Program to DRAM x Using Xmodem s Using SFTP q Exit Select One ELECTRONICS 5 87 CONTROLLING S5N8947 MODULES S5N8947 x Using Xmodem Select Using Xmodem with typing x at the cursor and you will see the message below Waiting for User Program Please Select Menu on your Hyper Terminal gt Transfer Send file Browse File Choose protocol you selected Browse File Choose File name Click the send file in pull down menu of Hyperterminal and you will see the windows below And then search the ram bin User File file in your working directory At last select the Xmodem protocol Send Fie Folder C My Documents Filename Documents ram bin Protocol Xmodem Send Close Cancel Figure 5 31 Hyperterminal Window Display when Click the Send File in Pull down Menu 5 88 ELECTRONICS S5N8947 CONTRO
14. SPSR_ lt exception_mode gt CPSR Copy the contents of the Current Status Register CPSR into the Saved Program Status Register SPSR of the mode in which the execution is to be handled This saves the current mode interrupt masks and condition flags LR_ lt exception_mode gt PC 4 Store the return address pc 4 in Ir_ lt exception_mode gt PC Vector address_ lt exception_mode gt Set the PC to the appropriate vector address That is execution control is forced to an exception handler whose entry address is hard wired to the lower memory area The processor then sets the appropriate CPSR mode bits CPSR 5 0 Exception mode number To change to the appropriate mode also mapping in the appropriate banked registers for that mode CPSR 6 1 if the exception mode is RESET or FIQ or CPSR 7 1 to disable interrupts Note that IRQs are disabled when any other type of exception occurs and FIQs are disabled whenever an FIQ exception occurs ELECTRONICS 4 3 EXCEPTION HANDLING S5N8947 LEAVING AN EXCEPTION To return control of program execution to the place where the exception occurred the handler must perform the following steps These steps must be performed by a user program 1 CPSR SPSHR exception mode 2 exception mode The handler performs these two operations as an atomic instruction by performing a data processing instruction with the S flag set and with the PC as the desti
15. The data structure for IIC read amp write library function is defined at IIC header file i2c h ELECTRONICS 5 29 CONTROLLING S5N8947 MODULES EXAMPLE CODE FOR IIC WRITE FUNCTION ROUTINE lt i2c c gt S5N8947 IICWrite fy 7 The CAT24WC32 64 writes up to 32 bytes of data using the page write operation cycle in a single write void IICWrite UINT WriteAddr IICPageWrite UINT IIC_D char WriteData UINT SizeOfData EV O WriteAddr WriteData SizeOfData void IICPageWrite UINT SlaveAddr UINT WriteAddr char WriteData UINT SizeOfData UINT WriteDataCnt UINT ByteAddrMsb UINT ByteAddrLsb by ydy UINT wait ByteAddrMsb ByteAddrLsb Stepl Added 12 9 WriteAddr gt gt 8 WriteAddr amp Oxff Bytes Address Bytes Address IEN amp Oxff Setup IICCON Register START ACK ui time delay for ACK from slave Step2 Send Slave Address with read write Command SlaveAddr S_WRITE while IICDoneFlag wait 1000000 while IICDoneFlag 1 if wait Print IIC ERROR return wait IICDoneFlag 0 Step3 Send Bytes Address A15 A8 IICBUF ByteAddrMsb while IICDoneFlag wait 1000000 while IICDoneFlag 1 if wait Print Mn IIC ERROR return wait IICDoneFlag
16. define 0 000001 define 1 INT 0 000002 define EXT2 INI 0x000004 define EXT3 INI 0x000008 define EXTA INT 0x000010 define EXT5 INI 0x000020 define EXT6 INI 0x000040 define UARTO TX INT 0x000080 define UARTO RX ERR INT 0x000100 define TIMERO IN 0x000200 define 1 IN 0x000400 define TIMER2 IN 0x000800 define GDMAO INT 0x001000 define GDMA1 INT 0x002000 define USB INT 0x004000 define SAR ERROR INT 0x008000 define SAR DONE IN 0x010000 define MACO TX IN 0x020000 define BDMAO RX INT 0x040000 define MAC1 TX IN 0x080000 define BDMA1 RX INT 0x100000 define IIC INT 0x200000 define SPI INT 0x400000 define GLOBAL INT 0x800000 ELECTRONICS CONTROLLING S5N8947 MODULES CONTROLLING S5N8947 MODULES if Number of Interrupt sources define nEXTO INT 0 define nEXT1 IN 1 define nEXT2 INT 2 define nEXT3 INT 3 define nEXT4 IN 4 define nEXT5 IN 5 define nEXT6 INT 6 define nUARTO TX INT 7 define nUARTO RX ERR INT 8 define nTIMERO IN 9 define INT 10 define Ntimer2 INT 11 define nGDMAO INT 12 define nGDMA1 INT 13 define nUSB INT 14 define nSAR ERROR INT 15 define nSAR DONE INT 16 define nMACO TX INT 1 7
17. 2 If EndpointO interrupt occurs call function for Control transfer endpointzeroFunction 3 4 3 4 If Endpoint1 interrupt occurs call function for Interrupt Out transfer endpointInterruptOutFunction If Endpoint3 interrupt occurs call function for Control transfer endpointBulkOutFunction USB Interrupt Handler Read USB Interrupt Register 1 and Clear Suspend Interrupt Resume Interrupt Reset Interrupt Endpoint 0 Endpoint 1 Endpoint 2 Interrupt Interrupt Interrupt InterruptOut Control Transfer BulkOut Transfer USB Interrupt Handler Routine End Figure 5 22 Concept Diagram for USB Interrupt Handler 5 54 ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES DIAGNOSTIC CODE USB INTIALIZE lt Usb c gt InitISR This is function for enable USB Interrupt ZZ void InitISR void InitializationUSB Initialize USB Register SysSetInterrupt nUSB_INT USB_IntHandler Register USB Interrupt Enable_Intr nUSB_INT Enable USB Interrupt InitializationUSB This function Initialise the USB device Register and Global Variable void InitializationUSB void endpointZeroState EPO_STATE_IDLE Clear FA WriteUsbRegister USB_FA_REGISTER 0x00 Mode and Endian Setting WriteUsbRegister USB_PM_REGISTER 0x0300 Interrupt Enable WriteUsbRegister USB INT REGIST W
18. 200 2 2 3 1 S5N8947 Memory 9 3 2 5 1 S5N8947 System Memory for Sample 5 2 5 2 System Manager Concept 5 3 5 3 Interrupt Handler Setup Concept 5 6 5 4 Interrupt Handler Concept 5 7 5 5 Concept Diagram for UART Initialization_ 5 12 5 6 Concept Diagram for Using the 5 13 5 7 Concept Diagram for Setting a Timer I snt 5 17 5 8 Concept Diagram for Setting Up 5 20 5 9 Typical 5 25 5 10 Data Transmission 5 26 5 11 Acknowledge Response From 5 27 5 12 Device Addr SS EE 5 27 5 13 Page Write Operation 5 29 5 14 Random Address Byte Read 5 32 5 15 Sequential Read 5 33 5 16 Concept Diagram for the Configuring of I O 5 37 5 17 LAN Initialize I aa nnnm nnn nnne 5 43 5 18 BDMA Frame Descriptor nn 5 45 5 19 Ethernet Frame Transmit 5 48 5 20 Ethernet Frame Reception
19. BR BER RRB BRA BERR BERR BRB BR ERE BRK BER RRS EXTHND_BASE EQU 0x1000000 A EXTHND BASE HandleReset 4 HandleUndef 4 HandleSwi 4 HandlePrefetch 4 HandleAbort 4 HandleReserv 4 HandleIrq 4 HandleFiq 4 ELECTRONICS S5N8947 MEMORY MANAGEMENT ABOUT lt 5 gt C language programs often employ many variable of various types and scopes Auto variables use registers and the stack area and global variables are allocated to memory area When you link programs that use global variables you must then copy these variables from the read only area in the DRAM to the DRAM s read write area The ARM linker has several system variables that you can use to execute this operation Image RO Limit Defines the end address of the ROM code area which includes execution code and read only data Image RW Base Defines the RAM base address to be initialized RAM is used for the read write area The global variables are grouped into two categories Zero initialized area with variables initialized to zero by the compiler Initialized area which contains variables initialized by the program e 71 Defines the base address of the Zero initialized area of the RAM Image ZI Limit Defines an end address of the Zero initialized area of the RAM ELECTRONICS 3 5 EXAMPLE CODE FOR lt BEGIN S gt S5N8947 The example code shown below uses the system variables described above to
20. CELL HEAD strCFG SAR CHAN ChanNum VPI lt lt BD VPI SFT strCFG SAR CHAN ChanNum VCI BD VCI SFT strCFG SAR CHAN ChanNum PTI BD PTI SFT ELECTRONICS 5 77 CONTROLLING S5N8947 MODULES S5N8947 Enqueueing Load TxBufDesc address to Tx Ready registers for j 0 1 lt 100 if nSAR_TXREADY1 amp 0x80000000 nSAR TXREADY2 amp 0x80000000 continue break if nSAR_TXREADY1 amp 0x80000000 Print nTx Error TX R ASSERT 0 nSAR TXREADY2 amp 0x80000000 ADY READY DONE BAR TRUE Pi nSAR_TXREADY1 ULONG gWSarTxDesc SAR_ADRVALID nSAR TXREADY2 ULONG pTxBufDesc ADRVALID gWSarTxDesc pTxBufDesc NEXT DESC 5 78 ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES RECEIVE PACKET The S5N8947 SAR reassembles the received cells into packets And the payload data is placed receive buffer pool 0 or pool 1 at first Which pool is selected is determined by AAL connection table of the channel If the data being received overflows their buffer pool 0 or 1 the rest data is placed to pool 2 or pool 3 respectively After reassemble operation is done the address of first buffer descriptor from received packets is written to Rx Done queue and SAR requests Rx interrupt The SAR writes the address into Rx done queue in order setting th
21. Exit Timer Test returns to main menu ELECTRONICS 5 19 CONTROLLING S5N8947 MODULES S5N8947 GDMA The S5N8947 has a two channel general DMA controller After finishing setting up you can use GDMA as a communication method with memory To setup and using GDMAs you must control registers described in figure 5 8 below GDMA Setup Set the following values in the GDMACONO register Run disable Mode selection Transfer width Source Destination address attributes Data transfer modes Assign source address value to the GDMASRCO registers Assign destination address value to the GDMADSTO 1 registers Assign transfer count value to the GDMACNTO 1 registers Set Run enable bit in the GDMACONO 1 registers Figure 5 8 Concept Diagram for Setting Up GDMA 5 20 ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES EXAMPLE CODE FOR SETTING UP AND EXECUTING DMA lt GDMATest c gt RunGDMA Run GDMA function void RunGDMA int num if num 0 GDMACONO RUN ENABLE else GDMACON1 RUN ENABLE j void MemToMemGDMA int DmaNum int width transfer width GDMACON0 0 GDMACON1 0 mode initialization gSrcAddr unsigned int gSrcBuf NON CACHE FLAG gDstAddr unsigned int gDstBuf NON CACHE FLAG FillMemory gSrcAddr BUF SIZE 0 1234 Select Transfer Width 0 byte 1 half
22. Print nTimer2 Expired fendif User codes needs here 5 18 ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES TIMER TEST PROGRAM DESCRIPTION IN DIAGNOSTIC ROM 55 8947 Diagnostic program contains a test program for timers You can test basic functions of timers and check the values of timer specific registers For the details of these functions refer to timer diagnostic source code provided timer c lt Main Menu gt CM47 M66 V1 0 Board Diagnostic Ver 1 0 Memory TEST UART TEST Timer TEST GDMA TEST I2C BUS TEST I O Port TES Ethernet TES USB Test SAR Test All Test User Program Download FLASH Memory Operation Hj C 5 CO 1 Select One Selecting Timer test menu shows sub menu of timer test below Timer Test Menu 1 Run Timers 2 Test TOUTO 1 2 3 Test Watch dog Timer 4 View Timer Configuration Q Exit Timer Test Select One Descriptions of each menu are below Run Timers runs timers as pre defined timer duration values and executes timer interrupt service routine It s set for timerO interrupt to occur every 1 sec and 2 sec for timer1 Test TOUTO 1 2 test TOUTO 1 2 as outputs of timers through IO Port Test Watch dog Timer gets the counting values and test Watch dog timer View Timer Configuration shows values of timer specific registers
23. SWI_Handler SUB STMFD LDR IMPORT IMPORT IMPORT IMPORT ELECTRONICS sp sp 4 sp r0 r0 HandleUndef ro r0 rO sp 4 sp xr0 pc sp sp 4 sp r0 r0 HandleSwi FO r0 rO sp 4 sp r0 pc ImageSSZISSBase ImageSSZISSLimit ImageSSROSSLimit ImageSSRWSSBase EXCEPTION HANDLING 4 7 k k k x k k ck ck lt lt lt SysInitVar The DATA s EXCEPTION HANDLING S5N8947 XC k K k k k KKK K k Ck K k Ck k x lt x k x x k ck K k x x k K ck K x lt k KKK k lt x k K lt Sk ck x lt k x kx K lt ko s Initialise the DATA and BSS sections ection is initialised by copying data from the end of the ROM image given by ImageS ROSSLimit to the start of the RAM image given by ImageSSRWSSBase stopping when we reach ImageSSRWSSLimit All data from ImageSSRWSSLimit to ImageSSZISSLimit is then cleared to 0 BRAS DN IO RERE REKEREKE GENOA KEE KEREKERE SSS SysInitVars Load up the linker defined values for the static data copy LDR r0 Image RO Limit LDR rl ImageSSRWSSBase LDR r3 557155 But first check whether we are trying to copy to the same address If so this means that the image was linked as an application image with the DATA section immediately following the CODE section Therefore ther
24. 3 Run DMA USB Bulkln Function When device send data to host PC Call endpointBulkInfunction Write 45 REGISTER Write EATDS REGISTER DMA Run USB BulkOut Function End Figure 5 25 Concept Diagram for USB Bulkln Function 5 62 ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES DIAGNOSTIC CODE USB BULKIN TRANSFER ENDPOINT 2 4 endpointBulkInFunction This is function for Endpoint 4 Bulk In function routine ZZ void endpointBulkInFunction UCHAR BulkIndata ULONG BulkInLen ReadUsbRegister USB_E4SC_REGISTER tempReg if tempReg amp 0x08 WriteUsbRegister USB_E4SA_REGISTER BulkIndata WriteUsbRegister USB EATDS REGISTER BulkInLen Print nEP4 DMA Run SetUsbRegister USB_E4SC_REGISTER 0x01 1 Print DMA Not ready Print cannot set EP4SA EP4TDS EP4SC DMA_RUN n n lt UsbFunc C gt Continued Normal Condition Data Length 0 else if IterationCnt 0 amp amp RemainDataCnt 0 break Set In Packet Ready Bit InReadUsbRegister 4 ADDR_IN_CSR1_REGIST data 0x01 InWriteUsbRegister 4 ADDR IN CSR1 REGISTER data data IterationCnt ELECTRONICS 5 63 CONTROLLING S5N8947 MODULES S5N8947 SAR SEGMENT AND REASSEMBLY The S5N8947 SAR diagnostic code supports co
25. UART TEST Timer TEST TES I2C BUS TEST I O Port TES Ethernet TES USB Tes SAR Tes All Tes User Program Download FLASH Memory Operation Hj Ci 9 Q 1 ON Oi Cr EF ocv Select One Selecting 2 UART test menu shows sub menu of UART test below UART TEST MENU View Current UART Configuration Change UART Configuration Set Baud Rate UART UART Tx Interrupt Test Rx Interuupt Echo Test EXIT UART Test Select One Descriptions of each menu are below View Current UART Configuration shows values of UART specific registers e Change UART Configuration change the values of UART registers Set Baud Rate changes UART baud rate e UART Tx Interrupt Test tests UART Tx Interrupt e UART Rx Interrupt Echo Test UART echo test by Interrupt method e EXIT UART Test returns to main menu ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES TIMERS S5N8947 has three timers To setup and using timers you must control several registers described in figure 5 7 below To run timers you only have to set timer enable bit in the TMOD register Specify timer_duration Timer duration msec Timer Data Value Fucsk 1 Register TimerO Timer1 Timer2 Interrupt Service Routine Set count value in the TDATAO TDATA1 TDATA register Select Interval Toggle Mode To start the timer operati
26. for i 0 i PktCnt i Link payload address to Tx buffer descriptor pIxBufDesc strTxBufDescriptor NextBufDesc amp SAR_ADRVALID TxBufDescArea 0 First NextBufDesc ULONG pTxBufDesc NEXT DESC SAR ADRVALID NEXT DESC if i PktCnt 1 pTxBufDesc NEXT DESC strTxBufDescriptor ULONG NextBufDesc amp SAR_ADRVALID pIxBufDesc NEXT DESC strTxBufDescriptor ULONG NextBufDesc PAYLOAD ADDR 1 if PktPtn lt 0 100 If PktPtn gt 0 100 transmit TxPacket 1 2 3 contents as data switch i 3 case 0 if i 0 amp amp strCFG SAR REG TRXALIGN lt 4 pTxBufDesc gt PAYLOAD_ADDR ULONG N amp TxPacket 1 0 strCFG_SAR_REG TRXALIGN else pIxBufDesc PAYLOAD ADDR ULONG amp TxPacket 1 0 break case 1 pTxBufDesc gt PAYLOAD_ADDR ULONG amp STxPacket 2 0 break case 2 pTxBufDesc PAYLOAD ADDR ULONG amp TxPacket 3 0 break else If PktPtn is larger than 0 100 PktPtn is used as address of data pIxBufDesc PAYLOAD ADDR ULONG PktPtn strCFG_SAR_REG TRXALIGN ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES PKT STATUS 1
27. makefile S COPTS BSP DIR Nuart c o OBJ DIR Nuart o S OBJ DIR Diagnosis o BSP_DIR Diagnosis c BSP_DIR board h BSP DIR Nisr h N BSP_DIR NDiagnosis h N makefile S COPTS BSP_DIR Diagnosis c o S OBJ DIR Diagnosis o 7 DIR Mi2c o BSP_DIR i2c c BSP_DIR board h BSP DIR Misr h 5 DIR Mi2c h N makefile 5 5 BSP_DIR i2c c o OBJ_DIR i2c 0 S OBJ DIR NSPI o BSP_DIR SPI c BSP_DIR board h BSP_DIR isr h N S BSP_DIR SPI h N makefile 5 5 BSP_DIR SPI c o OBJ DIR NSPI o DIR NEMFlash o BSP DIR NEMFlash c BSP_DIR board h BSP_DIR isr h N S BSP_DIR EMFlash h N makefile 65 5 S BSP DIR NEMFlash c o OBJ_DIR EMFlash o 2 8 ELECTRONICS S5N8947 USING THE ARM SDT FOR S5N8947 PROJECTS Rules for application files S OBJ_DIR root o root c BSP_DIR board h N makefile S COPTS root c o OBJ_DIR root o Ck ck KKK k k k k k k k k K k k k KKK K k k lt K k KKK k k x k lt K lt k k k k k k k k amp k k k k k k k k k k k k amp k k KKK k k k k ko ko Rules for making some of the assembler compiler option files used to build applications These files are needed on in DOS Windows on Win98 NT due to command line length limitations Ck ck ck k kk Ck k Ck k k k k k K k Kk ck k kk k lt K Ck k Ck k k K lt k kk Ck k k k k kk C
28. message getch 2 16 ELECTRONICS S5N8947 MEMORY MANAGEMENT MEMORY MANAGEMENT This chapter describes the default 55 8947 memory and explains how to write programs to allocate memory areas Information is presented according to the following Table of Contents INTRODUCTION The S5N8947 MCU uses its System Manager block to manage memory Specifically the System Manager uses special registers to manage the control signals addresses and data those are required by external devices To control external memory operations the System Manager uses programmed settings in a dedicated set of special registers You can for example specify the memory type the external data bus width for each bank and the number of access cycles for each memory bank You can also define the memory map by specifying bank locations and sizes that correspond to address spacing assignments Using these special registers you can configure up to three ROM banks one PCMCIA bank four SRAM banks four DRAM banks and four external I O banks in a 32 Mbyte addressable system space The ordering of these banks with the system space is arbitrary For more information about the System Manager please refer to the S5N8947 32 Bit RISC Microcontroller User s Manual ELECTRONICS 3 1 55 8947 S5N8947 MEMORY MAP Figure 3 1 shows a typical memory map for a boot ROM program written for the 55 8947 evaluation board More
29. q Exit Select Test Item s S Now User program will be started Press s key and your program will start running 5 90 ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES SERIAL PERIPHERAL INTERFACE The S5N8947 provides a Serial Peripheral Interface SPI which is used for register access of other devices EEPROM and A D converter 55 8947 dedicate pin used for receive serial data SPIMISO transmit serial data SPIMOSI and clock SPICLK Set the I O port IOPCONO 1 IOPMOD IOPDATA Set the CLKFRQ value in SPICFG and Set the following values in SPICFG Interrupt enable Clock phase Clock invert GDMA sele SPI Interrupt enable Figure 5 33 Concept Diagram for Setting Up GDMA ELECTRONICS 5 91 CONTROLLING S5N8947 MODULES EXAMPLE CODE FOR SPI SETUP FUNCTION ROUTINE lt spi c gt SPISetup SPI Se tup Routine Initialize SPI control block to use SPI void SPISe tup void UINT len UINT ret Disable 1 0 Port setting PORTO SPI SPICLK OUTPUT PORT1 SPI SPIMOSI OUTPUT 2 SPI SPIMISO INPUT 5 92 IOPCON1 amp CS port mode IOPMOD CS port IOPDATA 5 port SPI is disable gSPICFG amp SPI ENABLE SPICFG gSPICFG Set CLKFRQ Value fSCL is SPI serial gSPICFG amp OxFFFFFF00 SPICFG gSPICFG gSPICFG ret SetC
30. Board byte size ROM BOSIZE1 low BOSIZEO high and halfword size ROM BOSIZE1 high BOSIZEO low is possible to use R180 and R187 are used for Big Little endian mode selection BOSIZEO Description low low Reserved low Half word high Big endian BIGEND Description low Little endian Figure 1 5 Boot Device Size Selection and Endian Mode Selection 1 8 ELECTRONICS S5N8947 ABOUT S5N8947 EVALUATION BOARD DRAM SDRAM Configurations S5N8947 Evaluation board has the 72 pin SIMM module on the board for one bank DRAM S5N8947 support Synchronous DRAM SDRAM In this case SDRAM or DRAM memory can be selected alternatively using by SYSCFG register Using these devices with 55 8947 Evaluation board RAS selection jumpers has to be set to select DRAM or SDRAM RAS SDRAMO RAS SDRAM1 SDRAMO SDRAM1 RAS_EDO DRAM 72pin SIMM Figure 1 6 Extended Device Chip Selection Bank select jumpers for DRAM SDRAM RAS selection jumpers on S5N8947 Evaluation board are provided just only for the purpose of each bank test So you want to use SDRAM you have to enable a SDRAM bank and remove same DRAM bank s jumper BOOT ROM code find out the type of memory which is installed on S5N8947 and then initialize the memory banks base end pointer and the timing of CAS RAS after the system power on reset or the reset key pressed and released If DRAM banks are found each bank can be configured as an EDO DRAM mode using th
31. DIAGNOSTIC ROM S5N8947 Diagnostic program contains a program offers GDMA function test and shows the values of GDMA specific registers For the detail of these functions refer to timer diagnostic source code provided GDMATest c Main Menu CMA7 M66 V1 0 Board Diagnostic Ver 1 0 1 Memory TEST 2 UART TES 3 Timer TES 4 GDMA TEST 5 I2C BUS TEST 6 I O Port TEST 7 Ethernet TEST 8 USB Test S SAR Test A All Test U User Program Download F FLASH Memory Operation Select One Selecting 4 GDMA test menu shows sub menu of GDMA test below GDMA Test Menu n Memory to Memory Memory to UART UART to Memory LoopBack GDMA0 2UART GDMA1 View GDMA Configuration Exit GDMA Test Select One ELECTRONICS 5 23 CONTROLLING S5N8947 MODULES S5N8947 Descriptions of each menu are below Memory to Memory Memory to Memory GDMA function test In this function there are two memory areas The one is the source memory area to be transferred and the other is the destination memory area The contents of memory is assigned in the code User s option is selecting transfer width byte half word word After transfer It compares the destination area with the source area and gives user a message whether the transfer is successful Memory to UART Memory to UART GDMA function test In this function there is a memory
32. NON CACHE FLAG 10 ptrAllocMem strCFG SAR REG RxPoolQ 0 BufSize pRxPoolQ UINT strCFG REG RxPoolO 1 Addr for i 0 i strCFG SAR REG RxPoolQ 1 Size i pRxPoolQ SwapWord ptrAllocMem SAR ADRVALID NON CACHE FLAG 10 ptrAllocMem strCFG SAR REG RxPoolQ 1 BufSize pRxPoolQ UINT strCFG_SAR_REG RxPoolQ_ 2 Addr for i 0 i strCFG SAR REG RxPoolQ 2 Size i pRxPoolQ SwapWord ptrAllocMem SAR ADRVALID NON CACHE FLAG 10 ptrAllocMem strCFG SAR REG RxPoolQ 2 BufSize pRxPoolQ UINT strCFG SAR REG RxPoolQ 3 Addr for i 0 i strCFG SAR REG RxPoolQ 3 Size i pRxPoolQ SwapWord ptrAllocMem SAR_ADRVALID NON CACHE FLAG 10 ptrAllocMem strCFG_SAR_REG RxPoolQ_3_BufSize Tx Buffer Descriptor Area for i 0 i lt TXBUFDESC NUM i gTxBufDescArea i ptrAllocMem ptrAllocMem BUFDESC_SIZE if ptrAllocMem gt S5N8947_DRAM_BASE S5N8947 DRAM SIZI return FAIL return SUCC 55 5 68 ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES CONTROL CONNECTION MEMORY The S5N8947 SAR connection memory is composed of followings e 1 Rate Lookup Table e VP Lookup Table e UBR Schedule Table e CBR Schedule Table Cell Buffers e Scheduler Connection
33. PCR_Cell SAR8947_MAX_BITRATE 1 6 de rate the PCR die to sonet 11 long double 11 260 0 270 0 compute ATM cells per second PCR_Cell PCR_Cell 53 0 8 0 power_p2 floor log PCR_Cell log 2 0 power_p2val pow 2 0 power_p2 mantissa PCR_Cell power_p2val Create the ABR rate format for the PCR MaxRate power_p2 pow 2 0 9 MaxRate mantissa 1 0 512 0 if PCR Cell MaxRate 1 0 pow 2 0 14 for n 0 0 i20 i DFLT RATE LKUPTBL SIZE i n 1 0 RateLookupTbl i UINT 16 0 mantissa 512 0 power p2val 512 0 n 5 70 ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES Open New Channel Whenever open new channel the CAM or VP lookup table and Connection tables have to be configured as VPI VCI PORT value and other conditions SAR CAM contents each table is 8 byte length Address CAM_VPIVCIx SAR BASE ADDRESS 0100h Connection count 8 CAM_CNx SAR BASE ADDRESS 0100h Connection count 8 4 Where x is connection count SAR refer for conversion between Scheduler AAL SAR connection number and VPI PORT Same function can be achieved by VP lookup table For full information about SAR CAM refer to user s manual Setup Scheduler Connection Table each table is 8 word length Address SCH_CONNTBL_BASE Scheduler con
34. Size DFLT QUE SIZE SCtrCFG SAR REG RxPoolQ 3 Size DFLT QUE SIZE StrCFG SAR REG RxPoolQ Offset DFLT QUE OFFSET StrCFG SAR REG RxPoolQ 0 Addr ptrAllocMem SAR ADRVALID NON CACHE FLAG ptrAllocMem strCFG SAR REG RxPoolQ 0 Size 4 StrCFG SAR REG RxPoolQ 1 Addr ptrAllocMem SAR ADRVALID N NON CACHE FLAG ptrAllocMem strCFG SAR REG RxPoolQ 1 Size 4 StrCFG SAR REG RxPoolQ 2 Addr ptrAllocMem SAR ADRVALID N NON CACHE FLAG ptrAllocMem strCFG SAR REG RxPoolQ 2 Size 4 ELECTRONICS 5 67 CONTROLLING S5N8947 MODULES S5N8947 m 10 3 Addr ptrAllocMem SAR_ADRVALID NON CACHE FLAG ptrAllocMem strCFG SAR REG RxPoolQ 3 Size 4 Init RxPool Buffer and Setup RxPool Queue StrCFG SAR REG RxPoolQ 0 BufSize DFLT RXPOOLBUFSIZE LOW StrCFG SAR REG RxPoolQ 1 BufSize DFLT RXPOOLBUFSIZE LOW StrCFG SAR REG RxPoolQ 2 BufSize DFLT RXPOOLBUFSIZE HIGH StrCFG SAR REG RxPoolQ 3 BufSize DFLT RXPOOLBUFSIZE HIGH Clear Tx Rx Done Queue Area ptrMem UINT SARmemStart for ptrMem UINT SARmemStart UINT ptrMem ptrAllocMem ptrMem ptrMem 0 Connect Rx Pool amp Buff pRxPoolQO UINT strCFG SAR REG RxPoolQ 0 Addr for i 0 i strCFG SAR REG RxPoolQ 0 Size i pRxPoolQ SwapWord ptrAllocMem SAR ADRVALID
35. Table e Connection Table e SAR Connection Table Initialize Connection Memory The S5N8947 SAR can use internal 8K bytes SRAM or external memory DRAM or SRAM as connection memory To use internal SRAM as connection memory set EXT_ONLY bit of CONFIGURATION register to 0 and to use external memory set this bit to 1 When using external memory the base address of connection memory has to be configured at EXT_CMBASE register If you use internal SRAM It s recommended the base address and size of each table to be set as default values In this case number of channels that can be opened is limited to 32 channels The number of channel is dependent on size of connection tables which are scheduler aal sar connection table After initializing location of connection memory SAR driver would setup CAM Contents or VP Lookup table Scheduler connection table AAL connection table SAR connection table when new channel is opened except 1 Rate Lookup table Setup 1 Rate Lookup Table The following code shows the setup of 1 Rate Lookup table In this code you would be change the SAR8947 MAX BITRATE value as your system ELECTRONICS 5 69 CONTROLLING S5N8947 MODULES S5N8947 DIAGNOSTIC CODE SETUP 1 RATE LOOKUP TABLE hed GenOneOfRateTbl Setup 1 rate look up table void GenOneOfRateTbl void ULONG PCR MaxRate double PCR_Cell power_p2 power_p2val mantissa int ip tiy
36. YES Print Nn SARisr Interrupt Rx Done Que 0 endif if ReadSARstatus amp INTSTAT_RXDONEQ1 CntSARRxDoneQuel_intr if DebugFlag_SAR_ISR YES Print Nn SARisr Interrupt Rx Done Que 1 endif 5 82 ELECTRONICS CONTROLLING S5N8947 MODULES Rx Done Interrupt if ReadSARstatus amp INTSTAT RXDONEO SARRXDONEOK PoolPat 0 if DebugFlag_SAR_ISR YES Print SARisr Interrupt Rx Done 0 fendif while 1 if RxDonePkt amp SAR ADRVALID break DefaultRxHook strRxBufDescriptor RxDonePkt RxDoneQue0O Index if RxDoneQueO Index DFLT RXDONEQ 0 5171 RxDoneQue0O Index 0 RxDonePkt ULONG strCFG REG RxDoneQ 0 Addr RxDoneQueO Index PoolPat Clear SAR address valid bit to release buffer descriptor of Rx done queue RxDonePkt amp SAR_ADRVALID Rx Pool 0 release RxPoolArea ULONG strCFG SAR REG RxPoolQ 0 Addr RxPoolQueO Index RxPoolArea SAR ADRVALID RxPoolQue0_Index if RxPoolQue0_Index DFLT RXPOOLOQ O0 SIZI RxPoolQueO Index 0 if ReadSARstatus amp INTSTAT_RXDONE1 SARRXDONEOK PoolPat 1 while 1 RxDonePkt ULONG strCFG SAR REG RxDoneQ 1 Addr RxDoneQuel Index if RxDonePkt amp SAR ADRVALID break DefaultRxHook strRxBufDescriptor RxDonePkt RxDoneQuel_Index if RxDoneQu
37. area which is going to be transferred to UART User fills this area with specific data and transfers this area to UART byte by byte User can see the byte data displayed in the console window UART to Memory UART to Memory GDMA function test After fill UART Rx buffer with specific data transfer to memory Loopback gt gt 1 Loopback test GDMAO UART Tx Buffer gt UART Rx Buffer gt GDMA1 View GDMA Configuration shows the values of GDMA specific registers Exit GDMA Test returns to main menu 5 24 ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES BUS CONTROLLER The S5N8947 device IIC bus controller supports only single master mode The 64K IIC serial EEPROM KS24L321 641 is used as the slave device for the usage of S5N8947 device IIC interface This IIC serial EEPROM used as the storage of the target system configuration parameters like as UART Baud Rate MAC address IIC serial prescaler clock etc FUNCTIONAL DESCRIPTIONS OF KS24L321 641 FC Bus Interface The KS24L321 641 supports the serial interface data transmission protocol The two wire bus consists of a serial data line SDA and a serial clock line SCL The SDA and the SCL lines must be connected to Vcc by a pull up resistor that is located somewhere on the bus Any device that puts data onto the bus is defined as a transmitter and any device that gets data from the bus is a receiver The
38. branch statement for each vector at the start of your program Example Handler Installation Routine S5N8947 boot ROM programs and standalone ROM programs must include an exception installation routine as part of the startup code In the example below only the program block related to FIQ exception handling is shown For more information and examples for boot ROM programs see Chapter 5 of this manual header file board a e amp Ck k Ck CK k k Ck k KKK k Ck Ck Ck k kk k Ck k k kk Ck k k k k k k k k k k k amp k k k k k k kk k ck k k amp k k k amp k k k k ko lt lt Align Exception Handler Area for 8 exception sources 0x1000000 0x1000020 e k ck ck k k ck k k Ck k k Ck k x lt k k ck K k K x k K lt x k K lt k K x x k x x k K ck x k x lt K K lt x k lt x K K lt x k kk ko K x x k x kx x lt lt lt EXTHND BASE EQU 0x1000000 EXTHND_BASE ndleReset 4 ndleUndef ndleSwi ndlePrefetch ndleAbort ndleReserv ndleIrq ndleFiq I 0 h HB PHP HB ELECTRONICS 4 5 EXCEPTION HANDLING S5N8947 S5N8947 Boot Program rombegin s 1 GET board a IMPORT RomHdwInit IMPORT SetVector EXPORT SysInitVars amp ck k k k k k k k k K x k k Ck k x lt k ck K k kk k K lt x k K lt k K x K k K x k k lt x k x K k k x lt k k k k k k k k k k k k k k k k k k k ko Fr
39. bus is controlled by a master device which generates the serial clock and start stop conditions controlling bus access Using the AO A1 and A2 input pins up to eight KS24L321 641 devices can be connected to the same C bus as slaves see Figure 5 9 Both the master and slaves can operate as a transmitter a receiver but the master device determines which bus operating mode would be active Bus Master Trasnmitter Receiver NetMCU KS24L321 641 KS24L321 641 KS24L321 641 KS24L321 641 TX RX TX RX TX RX TX RX AO 1 2 0 1 2 0 1 2 0 1 2 Vcc or Vss To Vcc or Vss To Vcc or Vss To Vcc or Vss Figure 5 9 Typical Configuration ELECTRONICS 5 25 CONTROLLING S5N8947 MODULES S5N8947 2 05 PROTOCOLS Here are several rules for I C bus transfers e new data transfer can be initiated only when the bus is currently not busy e is always transferred first in transmitting data e During a data transfer the data line SDA must remain stable whenever the clock line SCL is High The interface supports the following communication protocols Bus not busy The SDA and the SCL lines remain in High level when the bus is not active Start condition A start condition is initiated by a High to Low transition of the SDA line while SCL remains in High level All bus commands must be preceded by a start condition Stop condition A stop condition is initiated by a Low to High t
40. errors bspa err 5 VIA a opt ARM linker options LOPTS info interwork remov nozeropad MAP Symbols list ram map DEBUG Debug Command Macros LD armlink LIB armlib MKDIR md ECHO echo RM del Macros for various lists of object modules RAM_OBJ S OBJ_DIR begin o ROM_OBJ S OBJ_DIR rombegin o 2 6 S5N8947 ELECTRONICS S5N8947 USING THE ARM SDT FOR S5N8947 PROJECTS Ff I K K K KOK KOK K K K K K KOK K K K K K OK KOK KOK KOK K KOK KOK I I I I BSP OBJECT LIST These form the dependency list for everything in the BSP if KK KK KK K k K K KOK KOK K K Ck Ck Ck CK K K Ck Ck KOK KOK ck Ck Ck k KOK KOK kc kc KOK Ck k kck kc KKK kckckck kc kckck KK KOK BSP_OBJ1 OBJ_DIR init o OBJ_DIR except o OBJ_DIR sysinit o BSP OBJ2 OBJ_DIR intrhndl o OBJ_DIR timer o OBJ_DIR uart o BSP_OBJ3 OBJ_DIR Diagnosis o DIR Ni2c o OBJ_DIR MemoryTest o BSP_OBJ4 OBJ_DIR GDMATest o OBJ_DIR IOPort o OBJ_DIR down o BSP OBJ5 OBJ DIR NSPI o OBJ_DIR USBfunc o OBJ_DIR usb o BSP OBJ6 S OBJ DIR Nsramtest o OBJ_DIR EMFlash o OBJ_DIR AllTest o BSP_OBJS BSP_OBJ1 S BSP OBJ2 S BSP OBJ3 S BSP OBJA S BSP OBJ5 S BSP OBJ6 dE KCKCKCKCk CK k k Ck kk Ck Ck Ck K K KOK KOK K K K Ck K K Ck K K K K Ck Ck A Ck Ck kk kc k Ck ck k kck kc kc kc kc KOK KOK kckckck kc KK I APPLICATION OBJECT LIST These form the depend
41. if txIndex sarTxcount Print OverRun return E_NG Info2 Pti 0 Info2 Clp 0 Call SarPacketTx function returnValue Aal5PacketTx 0 VPI VCI U8 pFrame gt BrgHeaderAddr amp Info2 if returnValue SUCCESS Print Etherrx Sar Tx Error n return E_NG return 0 Packet Transmit Function need to check SAR Tx Linked List Done Aal5PacketTx USHORT USHORT vpi USHORT vci void PktChain OTHER_PKT_INFO Info SAR Linked List Done check not Tx Done Check 5 86 while rData Read_SARreg nSAR_TXREADY1 amp 0x80000000 SAR Resgiter Write to send packet Write SARreg nSAR TXREADY1 ULONG PktChain ADRVALID Write SARreg nSAR TXREADY2 ULONG LastPktDescPtr ADRVALID ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES HOW TO DOWNLOAD amp EXECUTING USER PROGRAM 55 8947 Diagnostic ROM program includes User Program Download function This be found Diagnostic ROM Program Main Menu shown below after booting the evaluation board system If you have coded a program and want to test it without burning another ROM you can make your program run on DRAM lt Main Menu gt 47 66 1 0 Board Diagnostic Ver 1 0 1 Memory TEST 2 UART TES 3 Timer TES 4 GDMA TES 5 I2C BUS TEST 6 I O Port TEST 7 Ethernet TEST
42. information about each area of the memory map is provided below System Space DRAMO Configuration Special Registers Ox3ff 0000 Not Used 0x1800000 Data Area 0x180 0000 Image RW Base 0x1000050 0x100_0000 Exception Handler Vector Not Used 0x1000000 0x020_0000 ROMO 2MB 0x000_0000 Figure 3 1 S5N8947 Memory 3 2 ELECTRONICS S5N8947 MEMORY MANAGEMENT MEMORY MAPPED AREAS SPECIAL REGISTERS The boot ROM program defines and initializes each function block according to specified values The special register area definition is controlled by the base address in the SYSCFG register which indicates the start address of the special registers The start address of individual special registers is defined as the special register base address SYSCFG value the register offset value DRAM The DRAM area contains a R W read write area a R O read only area and several user defined areas as follows e The exception handler vector table contains an exception handler vector address for each of the eight exception sources e The data area is used for global variables Memory in this space can be freely allocated or released by the user application e code area contains executable code which the user downloads from the host This area is therefore meaningful only for program debugging ROM The ROM area contains executable code and read only data You can use the ROM area for a boot ROM program t
43. locate the various sections CODE DATA BSS within the image Rt ROM Image 2 FL i i 55 055 CODE P H ImageS RO Limit Initialising LS data ii i i ak RAM Image n ImageSSRWS SBase Initialised 557155 gt 4 t lt Image SRWSSLimit Zero init BSS data H lt ImageSSZISSLimit P tS KEKER IMPORT IMPORT IMPORT IMPORT ImageSSZISSBase ImageSSZISSLimit ImageSSROSSLimit ImageS SRWSSBase e k ck k k KKK k k k k k k KKK KKK KKK k lt K k k k K k k K k k K lt k k lt k k k k k amp k k k k k k k k amp k k amp k k k k ko kx k ko ELECTRONICS S5N8947 MEMORY MANAGEMENT SysInitVars Initialise the DATA and BSS sections The DATA section is initialised by copying data from the end of the ROM image given by ImageSSROSSLimit to the start of the RAM image given by ImageSSRWSSBase stopping when we reach ImageSSRWSSLimit All data from ImageSSRWSSLimit to ImageSSZISSLimit is then cleared to 0 EUN
44. on the Options menu or the Context menu This command toggles between Displaying source only and Displaying source interleaved with disassembly When source code is shown interleaved with disassembly machine instructions appear in a lighter gray color For additional information about the ARM Debugger please refer to Chapter 3 of the ARM Software Development Toolkit User s Guide 2 14 ELECTRONICS S5N8947 USING THE ARM SDT FOR S5N8947 PROJECTS COMMUNICATING WITH THE HOST USING UART When debugging or executing a program it is useful to monitor communications between the S5N8947 MCU and the host Using UART and a communication terminal program you can view data or messages that are transferred from S5N8947 and you can transmit data or a command to S5N8947 Using the HyperTerminal program that is supported by Windows 95 98 or NT 2000 the host can communicate with the S5N8947 s UART module You can also use other communication terminal programs Guidelines for using the HyperTerminal and UART functions are described below USING HYPERTERMINAL To start the HyperTerminal program on Windows 95 98 or NT 2000 Select the Start Programs Accessories HyperTerminal group Double click on Hypertrm exe enter the Connection Name and select the Icon Click on OK In the Phone Number dialog box choose Direct to COM1 or COM2 as the Connect Using setting from the list of communication port templates for your system environment Click
45. to next process Check end of Receive Frame All received frame is processed Clear status and Ready Check receive frame Not owner status Not asserted Exit BDMA Rx Interrupt Service routine Figure 5 20 Ethernet Frame Reception Flow ELECTRONICS 5 51 CONTROLLING S5N8947 MODULES S5N8947 UNIVERSAL SERIAL BUS CONTROLLER USB DIAGNOSTIC CODE FUNCTION CAUTION 1 Endpoint 1 is used for loopback test with endpoint 2 Do not use it in your product 2 USB Controller in 55 8947 needs S W DMA arbitration If you want to use USB in your product request us a new sample code to prevent data from corruption Next version of Programmer s Guide will contain it The diagnostic code for the USB Universal Serial Bus is composed of five files USB H USBFUNC H USBDESC H USB C and USBFUNC C USB H Definition file for USB diagnostic code It defines USB register address and global variables USBFUNC H Definition file for USB diagnostic code It defines simple USB function USB request type global variables and register bit value USBDESC H Definition file for USB diagnostic code It defines USB configuration descriptor USB device descriptor and USB endpoint descriptor USB C Initialize USB controller for normal operating environment and Register interrupt service routine USBFUNC C The library functions for diagnostic code which are called by interrupt service routine It includes USB Tx Rx function and USB request
46. word 2 word switch getch case 0 byte transfer if DmaNum 0 GDMACONO MEM TO MEM GEN STOP INT else GDMACON1 MEM TO MEM GEN STOP INT gCount BUF SIZE 4 break case 1 half word transfer if DmaNum 0 GDMACONO MEM TO MEM GEN STOP INT HALF WORD else GDMACON1 MEM TO MEM GEN STOP INT HALF WORD gCount BUF SIZE 2 break case 2 word transfer if DmaNum 0 GDMACONO MEM TO MEM GEN STOP INT WORD else GDMACON1 MEM TO MEM GEN STOP INT WORD gCount BUF SIZE break default byte transferS Print Nn Wrong number set as default lbyte if DmaNum 0 GDMACONO MEM TO MEM GEN STOP INT else GDMACON1 MEM TO MEM GEN STOP INT gCount BUF SIZE 4 break ELECTRONICS 5 21 CONTROLLING S5N8947 MODULES 5 22 if DmaNum 0 else SysSetInterrupt nGDMAO_INT isr_TestGDMAO setting SrcAddr DstAddr Count GDMASRCO gSrcAddr GDMADSTO gDstAddr GDMACNTO gCount RunGDMA 0 Run GDMA SysSetInterrupt nGDMA1_INT isr TestGDMA1 setting SrcAddr DstAddr Count GDMASRC1 gSrcAddr GDMADST1 gDstAddr GDMACNT1 gCount RunGDMA 1 Run GDMA S5N8947 ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES GDMA TEST PROGRAM DESCRIPTION IN
47. 0 5 30 ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES Step4 Send Bytes Address 7 0 ByteAddrLsb while IICDoneFlag wait 1000000 while IICDoneFlag 1 if wait TIC ERROR return wait IICDoneFlag 0 Step5 Send Multiple Data for WriteDataCnt 0 WriteDataCnt lt SizeOfData WriteDataCntt IICBUF WriteData WriteDataCnt while IICDoneFlag wait 1000000 while IICDoneFlag 1 if wait Print TIC ERROR return wait IICDoneFlag 0 Step6 Stop IIC Controller IICCON STOP ELECTRONICS 5 31 CONTROLLING S5N8947 MODULES S5N8947 READ C FUNCTION LIBRARY read C library function IICReadlnt were implemented by using the following Random read byte and Sequential read operation Random Address Byte Read Operation Using random read operations the master can access any memory location at any time Before it issues the slave address with the R W bit set to 1 the master must first perform a dummy write operation This operation is performed in the following steps 1 The master first issues a start condition the slave address and the word address the first and the second addresses to be read This step sets the internal word address pointer of the KS24L321 641 to the desired address 2 When the master receives an ACK for the word address it immediately re issue
48. 0 endpointZeroState EPO STATE IDLE if EOSC value amp 0 00100000 1 SetUsbRegister USB 05 REGISTER 0x00200000 Print Setup End Nn endpointZeroState EPO STATE IDLE TRAN_END_Int if EOSC value amp 0 00000008 1 Print Tran End Mn WriteUsbRegister USB 5 REGISTER EpOInOutdata SetUsbRegister USB EOSC REGISTER 0x00000010 Tran End Clear endpointZeroState EPO STATE IDLE Device Request type check and Control Transfer Receiver switch endpointZeroState case EPO STATE IDLE 5 58 ELECTRONICS S5N8947 Read standard request if EOSC_value 6 0 00000002 CONTROLLING S5N8947 MODULES DeviceRequest bmRequestType NCA EpOInOutdata DeviceRequest bRequest EpOInOutdatat l1 DeviceRequest wValue L EpOInOutdatat2 DeviceRequest wValue EpOInOutdatat3 DeviceRequest wlIndex L EpOInOutdatat4 DeviceRequest wlIndex EpOInOutdatatS DeviceRequest wLength L EpOInOutdatat6 DeviceRequest wLength EpOInOutdatat7 switch DEVICE_bmREQUEST_TYPE DeviceRequest case STANDARD_TYPE Print Nn MCU gt gt Standard Type Interrupt Nn StandardDeviceRequest break case CLASS_TYPE Print MCU gt gt Class Type Interrupt n break case VENDOR_TYPE break case RESERVED_TYPE break
49. 0001 000 port 12 13 14 15 16 as output IOPMOD amp Oxfffffelf port 5 6 7 8 as input IOPCONO PORTO_PCMCIA_NCE1_OUTPUT PORT1_PCMCIA_NCE2_OUTPUT PORT2_PCMCIA_NIOIS16_INPUT P ORT3_PCMCIA_ALE_OUTPUT PORT4_PCMCIA_PCM_RW_OUTPUT I O port settings for PCMCIA XIRQ_ENABLE ACTIVE_LOW FILTERING_OFF FALLING_EDGE lt lt 8 xIRQO settings for PCMCIA port5 PCMCIA card interrupt XIRQ_ENABLE ACTIVE_LOW FILTERING_OFF FALLING_EDGE lt lt 13 xIRQl settings for PCMCIA port6 card detection interrupt IOPDATA PCMCIA BUFFER ENABLE buffer disable IOPDATA amp PCMCIA RESET reset signal set LOW PCMCIA reset polarity active high Interrupt settings SysSetInterrupt nEXT1 INT isr PCMCIA Detect Extl interrupt is used for PCMCIA card detection SysSetInterrupt nEXTO INT isr PCMCIA Card Int Ext0 interrupt is used for PCMCIA card interrupt Enable Intr 1 INT Enable Intr nEXTO INT ELECTRONICS 5 99 CONTROLLING S5N8947 MODULES INTERRUPT SERVICE ROUTINE FOR CARD DETECTION S5N8947 As described above S5N8947 has no PCMCIA host core When the card is inserted the card detection interrupt is generated In the service routine S5N8947 perform the operation First the power switching device TPS2214A is initialized Then S5N8947 reads the voltage sensing pins These two sense pins are rep
50. 100Mbps e Embedded ICE or Emulator can be interfaced with this for system debugging SYSTEM MEMORY MAP The CM47 M66 V 1 0 board has a ROM socket which be used to boot ROM For the code development 55 8947 Evaluation board supports SyncDRAM into component type and also DRAM SIMM sockets So you can select DRAM SIMM or SyncDRAM by jumper on the board The 55 8947 has a total 16M word memory space Each memory banks can be located anywhere within a this address range by setup the appropriate memory control registers The data bus size of each bank also can be configured by bus control registers The system configuration register SYSCFG also used to configure the start address of the special register and also control the write buffer cache The special register s address area is fixed at 64Kbytes It s initial value is Ox23FF0000 You can use the 8 Kbyte Cache memory Please refer to user s manual for more details For the Direct Memory Access you have to configure this area as non cachable region as set the bit 26 of memory access address ELECTRONICS 5 1 CONTROLLING S5N8947 MODULES S5N8947 SYSTEM MEMORY MAP Ox3ff_ffff Not Used Special Register Ox3ff_0000 Not Used DRAM BANK 0x180_0000 EXT I O BANK 1 3 EXT I O BANK 0 Not Used Data Area 0x360_0000 DRAM BANK 1 3 Code Area Application 0x180_0000 E Tm 0 100 0050 xception Handler Vector Table 0x100_0000
51. 100Mbps and Full Half duplex mode So you need to set the MAC and BDMA controller to work as your purpose LAN Initialize Start Reset PHY device 1 Reset PHY device and configure via MII station Management control function Get MAC H W address 2 Get MAC H W unique address Stored on EEPROM 3 Setup BDMA controller Disable MAG BUMA Vr pr 1 Disable MAC BDMA Tx Rx interrupt 2 Setup MAC BDMA interrupt vector Setup MAC BDMA Controller 3 Reset MAC BDMA controller 4 Set global MAC control register and BDMALSZ register 5 BDMA Tx Frame descriptor initialize 6 BDMA Rx Frame descriptor initialize Set global MAC controller register and 7 Set CAM memory and control register to BDMA register filtering incomming message 8 Enable MAC Tx BDMA Rx interrupt We use MAC Tx interrupt for transmit operation and BDMA Rx interrupt for receive operation BDMA Rx frame descriptor initialize 9 Set MAC BDMA Tx Rx control register Reset MAC BDMA Controller BDMA Tx frame descriptor initialize Set CAM memeory and CAM control register to filterling incoming message Enable MAC Tx BDMA Rx Interrupt Set MAC BDMA Tx Rx control register LAN Initialize Finished Figure 5 17 LAN Initialize Flow ELECTRONICS 5 43 CONTROLLING S5N8947 MODULES S5N8947 1 Reset and configure PHY device The station management operation is used to control PHY The PHY has many control and status registers MAC can control PHY and it ca
52. 55 8947 ADSL CABLE MODEM 32 BIT RISC MICROCONTROLLER PROGRAMMER S GUIDE Revision 1 0 ELECTRONICS Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication Samsung assumes no responsibility however for possible errors or omissions or for any consequences resulting from the use of the information contained herein Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others Samsung makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation any consequential or incidental damages S5N8947 32 Bit RISC Microcontrollers Programmer s Guide Revision 1 0 Publication Number 51 0 S5 N8947 032002 2002 Samsung Electronics Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application b
53. 7 MODULES CONTROLLING THE POWER SWITCH TPS2214A PCMCIA card operates at either 5V or 3 3V So power switching is required according to the card voltage In the reference board we use the TPS2214A power switching chip to provide the proper power To control this device three control signals are used clock data and latch In Figure 1 GPIO signals are used to control the power switching device But in the reference board we use data lines instead of GPIOs Used for the other devices attached to 55 8947 18 GPIO signals not many in number We assign the data 6 4 to latch data and clock each INITIALIZE PCMCIA INTERFACE For the PCMCIA we have to configure the I O port register I O port register settings are depicted in I O ports chapter S5N8947 has no PCMCIA host core but has an interface for PCMCIA We assign 2 interrupt sources for PCMCIA operation One for card detection and the other for card interrupt generated by targer card I O port 5 and 6 are used for that purpose These pins can be used as external interrupts The I O ports and interrupts initialization are described below void PCMCIA init void PCMCIA control register setting PCMCON 0x8007ffff PCMCIA little endian PCMCON 0 80011021 PCMCON 007 PCMCIA big endian I O port settings IOPMOD 0
54. 7 MODULES Using the UART This example shows how to transmit and receive data through UART using a polling method UART Setup Set ULCON Set UBRDIV Set UCON Transmit Receive Check UART 6 Check UART 5 Transmitter holding register Receive buffer register ontains valid data No UTXBUF TXdata RXdata URXBUF Figure 5 6 Concept Diagram for Using the UART ELECTRONICS 5 13 CONTROLLING S5N8947 MODULES EXAMPLE CODE FOR UART SETUP ROUTINE lt UART c gt UART_Setup Perform startup initialization of serial channels 77 ChanNum Indicates the serial channel to be opened Notice S5N8947 has only 1 UART Channel void UART_Setup int ChanNum unsigned int WordLength 0 unsigned int tDIV DivCnt0O DivCntl DivCntVal WordLength ULCON_WL8 Set Buad Rate Divisor value You should select UART clock defined in the file uart tDIV UARTCLK 16 BaudRate if tDIV 16 0 tDIV 1 gt 0Oxffff DivCntl 1 DivCntO tDIV 16 1 else DivCntl 0 DivCntO tDIV 1 DivCntVal DivCnt0 16 DivCnt1 h Initialize the UART registers if ChanNum chUART 0 if UARTCLK MAINCLK UARTLCONO WordLength Added 11 2 else UARTLCONO WordLength UCLK 11 2 endif UARTCONTO UCON RXM INTREQ UCON TXM INTREQ UCON RXSTAT INT UARTBRDO DivCntVal else 1 UARTLCON1 WordLength U
55. A0 ByteAddrLsb while IICDoneFlag wait 1000000 while IICDoneFlag 1 if wait 1 5 34 ELECTRONICS S5N8947 Print IIC ERROR return wait IICDoneFlag 0 Step5 Repeat Start RESTART START ACK IICBUF SlaveAddr S READ while IICDoneFlag wait 1000000 while IICDoneFlag 1 if wait Print n IIC ERROR return wait IICDoneFlag 0 Step6 Receive Multiple Data for Receive ReadCnt 0 ReadCnt ReadDataSize while wait while IICDoneFlag 1000000 IICDoneFlag return wait IICDoneFlag if wait Print n IIC ReadValue ReadCnt IICCON AckDisable while IICDoneFlag wait 1000000 while IICDoneFlag if wait Print n IIC return wait IICDoneFlag 0 ReadValue ReadCnt Step7 IICCON STOP ELECTRONICS Last Data and ACK Disable IEN IICBUF Stop Controller ERROR 1 CONTROLLING S5N8947 MODULES ReadCnt ERROR 5 35 CONTROLLING S5N8947 MODULES S5N8947 BUS TEST PROGRAM DESCRIPTION IN DIAGNOSTIC ROM 55 8947 Diagnositc program contains a program offers IIC bus controller function test and shows the values of IIC bus co
56. ByteAddr Bytes Address 7 0 Lsb lt lt 24 while SPICMD amp START TRANS SPICMD START T while SPIDoneF1 SPIDoneFlag 0 RANS ag ceiv Step3 4 R for ReadCnt Multiple data ReadCnt ReadDataSiz ReadCnt S5N8947 CS port Step4 Send write disabl IOPDATA amp CS_port TXCHR WRDI while SPICMD amp ST SPICMD START_T while SPIDoneFl1 SPIDoneFlag 0 IOPDATA CS port Step5 Disable SPI gSPICFG amp SPI ENABLE SPICFG gSPICFG gSPICFG amp SPI INT SPICFG gSPICFG while SPICMD amp START TRANS SPICMD while SPIDoneFlag PIDoneFlag 0 TEMP RXCHR ReadValue ReadCnt e command ART_TRANS RANS ag START TRANS char T t gt gt 24 ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES PCMCIA INTERFACE The S5N8947 s System Manager provides the control logic for a PCMCIA socket interface and requires only additional external analog power switching logic and buffering The control signals for PCMCIA are generated through external bus and general I O ports by configuring GPIO registers Additional address lines ADDR 25 22 for PCMCIA and analog power control signals are made by using one of the memory controller chip select pins ex PnRCS PnECS The PCMCIA controller provides common memory attri
57. CLK UARTCONT1 UCON RXM INTREQ UCON TXM INTREQ UCON RXSTAT INT UARTBRD1 DivCntVal Set Console registers if chCONSOLE 0 CNSL TxBuf amp UARTTXHO CNSL RxBuf amp UARTRXBO CNSL STAT amp UARTSTATO else CNSL_TxBuf amp UARTTXH1 CNSL RxBuf amp UARTRXB1 CNSL STAT amp UARTSTAT1 5 14 S5N8947 ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES General Function for Polling Transmit one byte through UART void putb char ch Wait until UARTO Transmit buffer register is empty and when empty tramsmit new data while ChkTxStatus 0 j UARTTxH ch Transmit string through UART void PutString char ptr while ptr Puto ptr Receive one byte through UART char getch void char ch Wait until UARTO Receive buffer register has valid data When data is valid receive new data while ChkRxStatus 0 ch UARTRxB return ch ELECTRONICS 5 15 CONTROLLING S5N8947 MODULES S5N8947 UART TEST PROGRAM DESCRIPTION IN DIAGNOSTIC ROM S5N8947 Diagnostic program contains a program offers UART function test and shows the values of UART specific registers For the detail of these functions refer to timer diagnostic source code provided uart c Main Menu CMA7 M66 V1 0 Board Diagnostic Ver 1 0 Memory TEST
58. CONN strCFG_SAR_CHAN ChanNum strCFG_SCH_CONNTBL PCR nPCR DFLT PCR StrCFG SAR CHAN ChanNum strCFG SCH CONNTBL SchType Qos 5 CBR StrCFG SAR CHAN ChanNum strCFG SCH CONNTBL MBS nMBS StrCFG SAR CHAN ChanNum strCFG SCH CONNTBL SCR nSCR StrCFG SAR CHAN ChanNum strCFG SCH CONNTBL AAL ConnNum ChanNum StrCFG SAR CHAN ChanNum strCFG SCH CONNTBL PHY INFO phy port ELECTRONICS 5 73 CONTROLLING S5N8947 MODULES S5N8947 Initialize AAL connection Table StrCFG SAR CHAN ChanNum strCFG AAL CONNTBL AAL CONN NUM ChanNum StrCFG SAR CHAN ChanNum strCFG AAL CONNTBL VP nVPI StrCFG SAR CHAN ChanNum strCFG AAL CONNTBL VC nVCI StrCFG SAR CHAN ChanNum strCFG AAL CONNTBL PHY PORT phy port AALO CRC10 Cell always use Buffer0 2 by H W if nAAL AALCT PKT AALO nAAL AALCT PKT CRC10 StrCFG SAR CHAN ChanNum strCFG AAL CONNTBL RxBuffType AALCT BUFF 0AND2 1 StrCFG SAR CHAN ChanNum strCFG AAL CONNTBL RxBuffType N amp 0 1 0 AALCT BUFF OAND2 AALCT BUFF 1AND3 StrCFG SAR CHAN ChanNum strCFG AAL CONNTBL RxPktType nAAL StrCFG SAR CHAN ChanNum strCFG AAL CONNTBL PayLoadOffset BUFDESC_SIZE StrCFG SAR REG TRXALIGN StrCFG SAR CHAN ChanNum strCFG AAL CONNTBL SCH ConnNum N StrCFG SAR CHAN ChanNum strCFG SCH CONNTBL SCH CONN NUM Initialize SAR connection Table StrCFG SAR CHAN ChanNum strC
59. DonePkt amp SAR_ADRVALID Rx Pool 0 release RxPoolArea ULONG strCFG SAR REG RxPoolQ 0 Addr RxPoolQue0_Index RxPoolArea SAR_ADRVALID RxPoolQue0_Index t if RxPoolQue0_Index DFLT RXPOOLQ 0 SIZE RxPoolQueO Index 0 mn SARRXDONEOK Pool lPat 1 whil 5 80 1 1 RxDonePkt ULONG strCFG_SAR_REG RxDoneQ_1 Addr RxDoneQuel_Index if RxDonePkt amp SAR ADRVALID break UserDefinedService strRxBufDescriptor RxDonePkt PoolPat RxDoneQuel_Indext if RxDoneQuel Index DFLT RXDONEQ 1 SIZE RxDoneQuel Index 0 Clear SAR address valid bit to release buffer descriptor of Rx done queue RxDonePkt amp SAR_ADRVALID Rx Pool 1 release RxPoolArea ULONG strCFG SAR REG RxPoolQ 1 Addr RxPoolQuel Index RxPoolArea 5 ADRVALID RxPoolQuel Index if RxPoolQuel Index DFLT RXPOOLQ 1 SIZE RxPoolQuel Index 0 ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES HANDLING INTERRUPT The S5N8947 has two types of SAR interrupt Done and Error that are requested by various source The full SAR interrupt sources are described in the User s manual The following flow chart shows the handling SAR interrupt Handling Interrupt SAR RX Done Error interrupt occurs Read the SAR_DONEINTSTATUS SAR_ERRINTSTATUS register If the status value is zero Check the in
60. E interface for boundary scan test and debugging channel for application ELECTRONICS 1 11 ABOUT S5N8947 EVALUATION BOARD S5N8947 NOTES 1 12 ELECTRONICS S5N8947 USING THE ARM SDT FOR S5N8947 PROJECTS USING THE ARM SDT FOR S5N8947 PROJECTS This chapter explains how to use the ARM Software Development Toolkit ARM SDT to set up a project for developing and debugging code for the S5N8947 microcontroller Information is presented according to the following Table of Contents INTRODUCTION The ARM Software Development Toolkit consists of two applications that let you to write and debug applications for the S5N8947 microcontroller with its embedded ARM7TDMI RISC core e Project Manager Write source code build the source code into image files or libraries e Debugger Debug your source files The ARM SDT is used mainly for software development This involves building either C or ARM assembler source code into ARM object code which can then be debugged using the ARM symbolic debugger The debugger software supports single stepping breakpoint and watch point settings and register viewing You can perform testing and debugging on code running under a emulation in the host system or on a S5N8947 target board system The following section reviews the specific SDT components as they relate to 55 8947 projects and provides a brief description of a typical application development working flow For complete documentation on
61. FG SAR CONNTBL SAR CONN NUM ChanNum StrCFG SAR CHAN ChanNum strCFG SAR CONNTBL SEG STATUS SARCT SEG EN return OK 5 74 ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES TRANSMIT PACKET To send a packet transmit buffer descriptor has to be configured as follows e If there are another packet descriptors in this chain load the address and set the valid bit to 1 e Select packet type e Write the length of buffer which links to this buffer descriptor e Write cell header information including GFC VPI VCI PTI and CLP e Link the address of payload data to transmit Transmit Packet Open Channel Configure Tx Buffer Descriptor acket chain has more than Packet Enqueing Tx buffer descriptor Enqueing Tx buffer descriptor TX READY 1 First of Packet Chain TX READY 1 2 Buffer descriptor to TX READY 2 Last of Packet Chain send Tx Rx Operation Figure 5 27 SAR Transmit Packet ELECTRONICS 5 75 CONTROLLING S5N8947 MODULES DIAGNOSTIC CODE SEND PACKET S5N8947 SendPacket Enqueing the Tx buf descriptor into the Tx Ready register void SendPacketSAR UINT ChanNum UINT PktSize ULONG PktPtn UINT PktCnt 5 76 strTxBufDescriptor pTxBufDesc ULONG NextBufDesc 0 int i 1 Cnt Make Tx Buffer Descriptor Link pIxBufDesc strTxBufDescriptor gWSarTxDesc NextBufDesc ULONG gWSarTxDesc
62. LLING S5N8947 MODULES Click Send button and then ram bin User File file send Sending C MyDocumentswambin 000 Packet Error checking RC Rietries Total retries Later Fil 30k of 259K Elapsed 00 00 15 Remaining 00 01 54 Throuahput 2033 cps Figure 5 32 Hyperterminal Window Display when Xmodem File Send After completing downloading and CRC checking following message appears at HyperTerminal window Waiting for User Program CCCCCCCCCCCCCCCCCCCCCOCCCCCCCOC 1 CRC Check Ok Start User s Program s Start Program q Exit Select Test Item s SS Now User program will be started Press s key and your program will start running ELECTRONICS 5 89 CONTROLLING S5N8947 MODULES S5N8947 s Using SFTP To download user s program you also need a DOS application offered by us This program is called sftp with file name SFTP EXE Open a DOS window and run Sftp as a format below sftp lt gt file name gt Ex sflp 1 ram bin Following message asks you if you want to change downloading baud rate Just press n The downloading procedure starts and the progress shown with mark After completing downloading and CRC checking following message appears at HyperTerminal window Waiting for User Program Ok CRC Check Ok Start User s Program s Start Program
63. Not Used PCMCIA BANK 0x060_0000 ROM BANK 1 2 0 020 0000 0 000 0000 0 100 0000 0 080 0000 Figure 5 1 S5N8947 System Memory for Sample Program 5 2 ELECTRONICS S5N8947 SYSTEM MANAGER ELECTRONICS CONTROLLING S5N8947 MODULES System Manager Configuration Define System Memory Map To initialize ROM SRAM Extra Bank DRAM PCMCIA DRAM refresh control register specify the following value Bank location and size Number of access cycles Memory type External data us width To initialize the System Register Address Configuration Register SYSCFG specify the following values Start address of SFRs Special Function Registers Cache enable If needed Write buffer enable If needed Write specified values simultaneously to System Manager Registers Figure 5 2 System Manager Concept Diagram 5 3 CONTROLLIN G S5N8947 MODULES EXAMPLE FOR SYSTEM MANAGER CONFIGURATION PROGRAM r SDRAM setting S5N8947 only KA SYNC DRAM CONFIGURATION LDR r0 0x3FF0000 LDR rl 0x83FF0004 Start addr Ox3FF00000 STR El r0 Cache OFF Write Buffer ON rZ Initialize Memory Configuration This operation must be done at a time 5 ADRL r0 SystemInitData_SDRAM LDMIA 0 rl r10 LDR r0 0 3 0000 0x3010 ROMCON Offset 0x3010 STMIA 0 rl r10 KA Test whether SDRAM is used or not
64. OBJS 85 ECHO S LOPTS 5 OBJ 5 5 OBJS S APP OBJS 5 LIB N lnkram opt VIA lnkram opt 85 RM opt ELECTRONICS S LD first rombegin o ROMBEGIN nodebug bin o rom bin ROMOPTS 2 7 USING THE ARM SDT FOR S5N8947 PROJECTS S5N8947 Rules for board specific files s S OBJ_DIR begin o BSP_DIR begin s BSP_DIR board a N makefile 5 S AOPTS BSP_DIR begin s o OBJ_DIR begin o S OBJ_DIR rombegin o BSP_DIR rombegin s BSP_DIR board a N makefile 5 S AOPTS BSP_DIR rombegin s OBJ_DIR rombegin o S OBJ_DIR init o BSP_DIR init s BSP_DIR board a N makefile S AOPTS BSP_DIR init s o OBJ_DIR init o S OBJ DIR Nexcept o BSP_DIR except s BSP_DIR board a N makefile 5 S AOPTS BSP_DIR except s o OBJ_DIR except o S OBJ_DIR intrhndl o BSP_DIR intrhndl c BSP_DIR isr h N makefile 6 5 S BSP DIR Mintrhndl c o OBJ_DIR intrhndl o S OBJ DIR Nsysinit o BSP_DIR sysinit c BSP DIR Nisr h N makefile 5 5 BSP_DIR sysinit c o OBJ_DIR sysinit o OBJ_DIR timer o BSP_DIR timer c BSP_DIR board h BSP_DIR isr h N S BSP_DIR timer h N makefile S COPTS BSP DIR Ntimer c o OBJ_DIR timer o S OBJ DIR Nuart o BSP_DIR uart c BSP_DIR board h BSP_DIR isr h N BSP DIR Nuart h N
65. OUTINE lt spi c gt SPIRead If The Sequential READ operation can be initiated by either the Immediate Address READ or Selective READ operation void SPIRead UINT ReadAddr UINT ReadDataSize char ReadValue SPISeqRead ReadAddr ReadValue ReadDataSize void SPISeqRead UINT ReadAddr char ReadValue UINT ReadDataSize UINT ReadCnt UINT ByteAddrMsb Bytes Address 15 8 UINT ByteAddrLsb Bytes Address 7 0 UINT wait U32 TEMP ByteAddrMsb ReadAddr gt gt 8 amp Oxff ByteAddrLsb ReadAddr amp Oxff prn Stepl Setup SPICFG Register gSPICFG EN SPI INT SPICFG gSPICFG gSPICFG SPI ENABLE SPICFG gSPICFG Step2 Send write enable command amp CS_port TXCHR WREN while SPICMD amp START TRANS SPICMD START TRANS while SPIDoneFlag SPIDoneFlag 0 IOPDATA CS_port Step3 1 Send Read command IOPDATA amp CS_port TXCHR READ while SPICMD amp START TRANS SPICMD START TRANS while SPIDoneFlag SPIDoneFlag 0 Step3 2 Send Bytes Address 15 8 TXCHR ByteAddrMsb lt lt 24 while SPICMD amp START_TRANS SPICMD START_TRANS while SPIDoneFlag ELECTRONICS 5 95 CONTROLLING S5N8947 MODULES 5 96 SPIDoneFlag 0 Step3 3 Send TXCHR
66. S SARAllocMem Allocate SAR Tx Rx PoolQ and DoneQ area These size of each queue are defined in the sar h UINT SARAllocMem void UINT ptrAllocMem pRxPoolQ i SARmemStart ptrMem if UserSarMemBase 0 Avoid S5N8947SAR limitiation ptrAllocMem SARmemStart HeapBase Oxf amp Oxf 8 else ptrAllocMem SARmemStart UserSarMemBase Init TxDONE Queue strCFG_SAR_REG TxDoneQ_Addr ptrAllocMem SAR_ADRVALID NON CACHE FLAG StrCFG SAR REG TxDoneQ Siz DFLT QUE SIZE StrCFG SAR REG TxDoneQ Offse DFLT QUE OFFSET ptrAllocMem strCFG SAR REG TxDoneQ Size 4 ct Init RxDone Queue strCFG_SAR_REG RxDoneQ_0_Size DFLT_QUE_SIZE strCFG_SAR_REG RxDoneQ_1_Size DFLT_QUE_SIZE StrCFG SAR REG RxDoneQ 0 Addr ptrAllocMem SAR ADRVALID NON CACHE FLAG ptrAllocMem strCFG SAR REG RxDoneQ 0 Size 4 StrCFG REG RxDoneO 1 Addr ptrAllocMem SAR ADRVALID NON CACHE FLAG ptrAllocMem strCFG SAR REG RxDoneQ 1 Size 4 StrCFG SAR REG RxDoneQ Offset DFLT QUE OFFSET Init RxPool Queue StrCFG SAR REG RxPoolQ 0 Size DFLT QUE SIZE StrCFG SAR REG RxPoolQ 1 Size DFLT QUE SIZE StrCFG SAR REG RxPoolQ 2
67. SB Bulkin Transfer Endpoint 2 4 nennen nennen nnne 5 62 Diagnostic Code USB Bulkin Transfer Endpoint 2 4 5 63 SAR Segment and 5 64 Gonfigure SAR Registers ediscere 5 65 Set p SARB QUGOUGS E 5 66 Diagnostic Code Setup Various SAR 5 67 Control Connection Memory 5 69 Diagnostic Code Setup 1 Rate Lookup 5 70 Diagnostic Code Setup VP Lookup Scheduler AAL SAR Connection Table 5 72 FANS Mit PACK iioii o eel nuin 5 75 Diagnostic Code Send 5 76 Receive Packet at 5 79 Diagnostic Code Receive Packet in The Interrupt Service 5 80 Handling Interruption eir 5 81 Diagnostic Code Receive Packet in the Interrupt Service Routine 5 82 Flow Chart of SAR 5 84 Appendix 5 85 How to Download amp Executing User 5 87 Serial Peripheral Interface
68. TDBWTH DCD 0x02000060 0x0000000 OxO1FFFFF ROMCONO DCD 0x04008040 0x0200000 OxO3FFFFF ROMCON1 DCD 0x06010040 0x0400000 OxO5FFFFF ROMCON2 DCD 0 0 0 0600000 OxO7FFFFF PCMOFFSET DCD 0x18040380 0 1000000 Ox17FFFFF DRAMCONO DCD 0 0x1800000 OxlBFFFFF DRAMCON1 DCD 0x1c060180 0x1800000 OxlBFFFFF DRAMCON2 DCD 0x20070180 0x1C00000 OxlFFFFFF DRAMCON3 DCD 0 278360 Refresh enabl REFEXTCON ELECTRONICS A SS CONTROLLING S5N8947 MODULES S5N8947 INTERRUPTS Interrupt Setup Initialize INTMOD Interrupt Mode Register FIQ IRQ Initialize INTMSK Interrupt Mask Register Disable Initialize INTPND Interrupt Pending Register ALL Clear Enable global mask bit in iterrupt Mask Register INTMSK 23 1 Setup interrupt vector address for each interrupt source Set interrupt vector with specified address of interrupt service routine Enable interrupt mask bit for each interrupt source When interrupt occurs Interrupt service routine E Figure 5 3 Interrupt Handler Setup Concept Diagram 5 6 ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES Example of Interrupt FIQ IRQ Handling Flow FIQ IRQ Exception Occurs Check INTOFFSET Register according to priority Branch to corresponding interrupt service routine Interrupt Service Routine Clear interrupt pending bit for the interrupt source 2 INTPND bit interrupt source 1 Execut
69. a Byte N Address Address Address N lt 31 Figure 5 13 Page Write Operation The KS24L321 641 automatically increments the word address pointer each time it receives a complete data byte When one byte is received the internal word address pointer increments to the next address so that the next data byte can be received If the master transmits more than 32 bytes before it generates a stop condition to end the page write operation the KS24L321 641 word address pointer value rolls over and the previously received data is overwritten If the master transmits less than 32 bytes and generates a stop condition the KS24L321 641 writes the received data to the corresponding EEPROM address During a page write operation all inputs are disabled and there would be no response to additional requests from the master until the internal write cycle is completed You can writes data to a Slave IIC Serial EEPROM using the IIC write library functions This write function divides the transfer data to page size and transmit it to Slave until all transfer data is sent S5N8947 device s IIC bus controller has the only one interrupt source for IIC So whenever the write operation or read operation is started IIC interrupt service routine have to be installed at vector table using SysSetlnterrupt
70. a payload data is received at Rx pool via valid channel SAR driver reads this address in the SAR Rx Done interrupt service routine Detailed operation of interrupt service routine will be described later in this chapter size of this queue is one of following values 256 1024 4096 16384 The DONEx SIZE register has this size value of each queue RX DONEx ADDR register has the each base address of these queues Receive Pool Queue The S5N8947 supports four receive pool queues and the pool 0 2 and pool 1 3 operate separately When a packet arrives at SAR the SAR starts copying data to pool 0 or pool1 Which pool is used is determined at AAL connection table of each channel If the size of payload data is longer than buffer size of poolO or pool1 the rest data is saved to pool 2 or pool 3 respectively Details of receive operation will be described later in this chapter The size of each pool queue is one of following values 256 1024 4096 16384 The POOLx SIZE register has this size value of each queue The buffer size of each pool queue is one of 128 2 bytes where n 0 9 Generally the buffer size of pool 0 and pool 1 is smaller than pool 2 and pool3 The RX POOLx SIZE register has this buffer size value of each queue The RX POOLx ADDR register has the each base address of these queues 5 66 ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES DIAGNOSTIC CODE SETUP VARIOUS SAR QUEUE
71. and to run the compiler 5 Command to run the assembler OBJ_DIR Name of the object dirtectory for this model note that it must end with 75 BSP_AOPTS Assembler options specific to this model BSP_COPTS Compiler options specific to this model INTERWORK Set to interwork to allow ARM THUMB interworking In these options you can set following modes Endian Big Little Processor modes ARM THUMB x amp K k KK KKK KK KK k k k k k KKK k K k k k k KKK k k k k k amp KKK k amp k k amp k KKK amp k k k k amp dio di amp k di dir k amp k didi k di di k dir did OBJ_DIR OBJ armcc Or tcc AS armasm tasm ENDIAN li INTERWORK or interwork 5 5 PD BSP LITTLE ENDIAN SETL FALSE PD THUMB SETL FALSE BSP COPTS ENDIAN DBSP LITTLE ENDIAN 0 ELECTRONICS 2 5 USING THE ARM SDT FOR S5N8947 PROJECTS DBGFLG g ARM C compiler options ui 51 DBGFLG zz 1 zal fy c COPTS2 IS BSP DIR W G IS ARMINC COPTS3 apcs 3 noswst nofpS INTERWORK cpu ARM7TM ARCH 4T 54 S BSP COPTS errors bspc err COPTS VIA c opt ARM assembler options 51 S DBGFLG DIR 5 52 cpu ARM7TM ARCH 4T 3 noswst nofp AOPTS3 5 AOPTS
72. ansmit burst size BTxMSL BDMA Tx to MAC Tx start level BTxSTSKO BDMA Tx stop when met not ownered frame BRxBRST BDMA Rx burst size BRxNLIE BDMA Rx null list interrupt enable BRxNOIE BDMA Rx not owner interrupt enable BRxSTSKO BDMA Rx stop when met not ownered frame BDMARXCON BDMA Receive control register BDMA receive enable BRxLittle Received data is stored in Little endian mode Used when Little endian is selected Received data is stored in Big endian mode Used when Big endian is selected BRxMAINC Received data is stored in memory address increment 5 46 ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES TRANSMIT ETHERNET FRAME After set all control register and BDMA transmit frame descriptor we are ready to transmit packet When transmit packet you can follow this step STEP 1 Get transmit frame descriptor and data pointer Get current frame descriptor and data pointer that will be used for prepare Ethernet frame data and transmit control function STEP 2 Check BDMA ownership Check BDMA owner is CPU or not when BDMA owner is CPU CPU can be write control bit and frame data If owner is BDMA then exit send packet function STEP 3 Prepare Tx frame data to frame buffer Copy Ethernet frame data to BDMA frame buffer this pointer is pointed by frame data field on frame descriptor STEP 4 Set Tx frame flag and length field After copy Ethernet frame to BDMA frame buffer CPU write control bit and the l
73. aster before returning to its stand by mode 5 26 ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES Master SCL Line Data from Transmitter ACK from Receiver Figure 5 11 Acknowledge Response From Receiver Slave Address After the master initiates a start condition it must output the address of the device to be accessed The most significant four bits of the slave address are called the device identifier The identifier for the KS24L321 641 is 1010 The next three bits comprise the address of a specific device The device address is defined by the state of the AO A1 and A2 pins Using this addressing scheme you can cascade up to eight KS24L321 641s on the bus Read Write The final eighth bit of the slave address defines the type of operation to be performed If the R W bit is 1 a read operation is executed If it is 0 a write operation is executed Device Identifier Device Select sese First High Address x Tx x nem no Second low Address ar De o T o NOTES 1 A12 is Don t care for the KS24L321 2 Xmeans Don care Figure 5 12 Device Address ELECTRONICS 5 27 CONTROLLING S5N8947 MODULES INITIALIZE THE IIC BUS CONTROLLER S5N8947 Before the use of IIC bus controller control status register IICCON and IIC prescaler register IICPS have to be initialized Code below shows the IIC initialize C r
74. atus amp 0x0001 EPO Print n USB_Diag_Log EPO Control Transfer Interrupt n endpointZeroFunction if status amp 0x0004 EP2 SetUsbRegister USB_E2SC_REGISTER 0x04 if status amp 0x0002 EP1 endpointInterruptOutFunction SetUsbRegister USB E1SC REGISTER 0x0a0002 if status amp 0x0010 EP4 SetUsbRegister USB_E4SC_REGISTER 0x04 if status amp 0x0008 EPS3 endpointBulkOutFunction SetUsbRegister USB E3SC REGISTER 0x0a0002 5 56 ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES USB CONTROL TRANSFER ENDPOINT 0 USB endpointO Control Transfer is special endpoint that can transmit and receive gt 2 Check EndpointO State If State is Transmit go back to idle state This state means that USB device send control data to host 5 If State is Receive endpointZeroReceiver This state means that USB device received control data from host 4 If State is IDLE Check Device Request Type of control data and change state of endpoint 0 This device request type is defined USB Spec1 1 After this run DMA USB Control Transfer When Endpoint 0 Interrupt pccurs Endpoint 0 StateCheck IDELE Transmitter Receiver Transmitter Receiver endpointZero Receiver Check Device Request Type of control data If type is transmit data If type is receive data Set EOSA 05 EOXDS Set EOSA 05 EOLDS Endpoint 0 State Endpoin
75. bute memory and I O function region by PRS bits PCMCON 31 30 The PCMCIA interface can be configured as big endian or little endian by PCMEND bit PCMCON 29 regardless of external big little selection pin BIGEND 16 When IOIS16 is not used by PCMCIA card I O function region PCMCIA function port size is depend on PPS bit POMCON 28 user can control PCMCIA access cycle by configuring PCMCON register PAST PSST PSL PSHT Figure 5 26 shows the PCMCIA socket interface guide The socket and external bus must be electrically isolated using external buffers and bus transceivers These buffers also provide voltage conversion required from the 3 3V to 5V cards ELECTRONICS 5 97 CONTROLLING S5N8947 MODULES 52214 RESET MODE STBY CLOCK LATCH pwrRESET DATA DATA 15 8 DATA 7 0 R W j nCE2 Core RESET 1 b1 150 P 14 R 15 P 16 DATA 15 8 DATA 7 0 Transceiver PI4 0 P 1 poet ae Buffer Buffer_En A 21 0 Transparent Latch nWBE 0 nOE nWBE 1 nWBE 2 P 12 nWE nOE jJ nlORD nQWR nlOWR P 13 ADDR 21 0 nRCS 3 PIS INPACK CD1 CD2 BVD1 BVD2 VS1 VS2 PI6 P 7 8 Figure 5 34 PCMCIA Socket Interface 5 98 S5N8947 PCMCIA socket Vcc Vcc D 15 8 D 7 0 A 21 0 REG WP IOIS16 READY IREQ INPACK CD1 CD2 BVD1 BVD2 51 VS2 ELECTRONICS S5N8947 CONTROLLING S5N894
76. cally The name of the executable target is the same as the project name When you have created a new project the information in the Project Window is displayed as a hierarchical flow diagram In the Project Window you can select one of two project variants These variants are automatically constructed from project templates supplied with the ARM Project Manager Debug For creating a target image that is suitable for debugging and which includes debugging information Release For creating a target images that is suitable for release but which includes no debugging information Adding Source Files to the Project 1 Select Add Files to Project from the Project menu 2 Choose the files you wish to add The project window is updated to reflect the change 3 Select Debug as the project variant Setting C Compiler Options 1 Select Tool Configuration for project name apj from the Project menu and choose cc armcc 2 Configure the compiler options as follows In Target page Processor ARM7TM Byte Format Big Endian 3 Forthe remaining options select the default values ELECTRONICS 2 3 USING THE ARM SDT FOR S5N8947 PROJECTS S5N8947 Setting Assembler Options 1 2 2 Select Tool Configuration for project names apj from the Project menu and choose lt asm gt armasm Configure the assembler options as follows Configure the compiler options as follows For the Target page Processor ARM7TM Byte Fo
77. cription in Diagnostic ROM 5 36 DP 5 97 Example I O Port Setup Routine as External Interrupt 5 38 I O Port Test Program Description in Diagnostic 5 40 iv S5N8947 Table of Contents Continued Chapter 5 Controlling S5N8947 Modules Ethernet Controller s L NA 5 42 MAC Diagnostic Code Function a 5 42 INE ananassa ATA r a r niaaa aqsu 5 43 Transmit Ethernet a 5 47 Control Frame Transmite eena rrr er eer Rd eene p ute RE REP ee RI 5 49 Receive Ethernet Frame 5 50 Universal Serial Bus Controller 5 52 USB Diagnostic Code 5 52 USB InitialiZ us 5 53 HJ SB nterr pt Handler 5 54 Diagnostic Code USB Intialize lt 05 gt 4 5 55 USB Control Transfer Endpoint 0 5 57 Diagnostic Code USB Control Transfer Endpoint 0 5 58 USB Bulkout Transfer 1 9 5 60 Diagnostic Code USB Bulkout Transfer Endpoint 1 3 5 61 U
78. define nBDMAO RX INT 18 define 1 TX INJ 19 define nBDMA1 RX INT 20 define nIIC INT 2L define nSPI_INT 22 define nGLOBAL INT 23 Interrupt Macro Funtions 77 define Enable Intr n INTMASK amp 1 lt lt define Disable Intr n INTMASK f een define Clear PendingBit n INTPEND 1 lt lt define SetPendingBit n INTPNDTST 1 lt lt n C funtion defines 7 extern void InitIntHandlerTable void extern void SysSetInterrupt unsigned long void extern void MainIntHandler int extern void MainUndefHandler void extern void MainPrefetchHandler void extern void MainAbortHandler void 5 10 5 00 S5N8947 ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES EXAMPLE INTERRUPT SETUP ROUTINE Intrhndl c include board h include isr h void InterruptHandlers MAXHNDLRS void static void DummyIsr ROR RR KKK k k K K K k K K K I K KOK K K KOK KOK KOK KOK KOK KOK KOK KOK KOK KOK KOK KOK KOK I RK R KOK O O KO InitIntHandlerTable Initialize the interrupt handler table NOTE S This should be called during system initialization by HdwInit K K K K KC K KOK K K KOK KOK KOK KOK KOK KOK KOK KOK KOK KOK KOK KOK KOK KOK KOK ck kokck ck ok KOK KOK ke ke e x void InitIntHandlerTable void int i Initialize interrupt handler table t
79. dom R W Test IIC Write one byte of data to a given address of EEPROM Loopback Test INT IIC read write Loopback test Configuration view Shows IIC related register value ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES PORTS The General I O ports PO P17 shared with a special function such as an external interrupt request an external DMA request amp acknowledge and timer signal outputs port mode can be configured by port mode register IOPMOD But the shared function will be configured by the IOPCON register not by IOPMOD Configure the I O port Set I O port mode register IOPMOD PO P17 can be configured input or outputs Disable interrupt Setup interrupt service functions for external interrupt external DMA interrupt and timer interrupt etc if needed Set I O port control register OPCON The P5 P17 have the shared with a special function such as a external interrupt input an external DMA request amp acknowledge timer signal output These shared function mode is determined by the IOPCON not IOPMOD Enable interrupt Read and Write I O data register IOPDATA Interrupt will be served if it is configured E Figure 5 16 Concept Diagram for the Configuring of I O Port ELECTRONICS 5 37 CONTROLLING S5N8947 MODULES EXAMPLE I O PORT SETUP ROUTINE AS EXTERNAL INTERRUPT SOURCE ExternallInterruptTest Test I O Ports as External Interrupt reques
80. e Breakpoint from the Execute menu The Set or Edit Breakpoint dialog box appears 4 Set the count to the required value or expression as required The program only halts when this expression is true ELECTRONICS 2 13 USING THE ARM SDT FOR 55 8947 PROJECTS S5N8947 SETTING A WATCHPOINT A watchpoint halts a program when a specified register or variable changes or becomes a specified value To set a watchpoint follow these steps 1 Display a list of registers variables and memory locations you wish to watch by selecting the Registers Variables and Memory options from the View menu 2 Click the register variable or memory area in which you wish to set the watchpoint Then choose Set or Edit Watchpoint from the Execute menu or the Context menu The Set or Edit Watchpoint dialog box appears 3 Enter a Target Value in the Set or Edit Watchpoint dialog box Program execution halts when the variable reaches the specified target value VIEWING VARIABLES REGISTERS AND MEMORY You can view and edit the value of variables registers and memory by choosing the respective heading from the View menu as follows Variables for global and local variables Registers for the current mode and for each of the six register view modes Memory for the memory area defined by the address you enter DISPLAYING THE CODE INTERLEAVED WITH THE DISASSEMBLY To display the source code interleaved with the disassembly choose Toggle Interleaving
81. e MAC Tx BDMA Rx interrupt to avoid abnormal branch STEP 2 BDMA and MAC interrupt vector setup Interrupt vector setup for MAC and BDMA interrupt after this statement MAC and BDMA interrupt can be used STEP 3 Set the initial condition of BDMA and Reset the MAC controller and BDMA controller And set the duplex mode and interface mode to MACCON register Ethernet interface can be configured as MII interface or old style 7 wire interface The 7 wire interface can be set by MII OFF bit STEP 4 Set the BDMA Tx Rx Frame Descriptor BDMA Frame descriptor is used for control BDMA automatically The transmit BDMA frame descriptor has frame buffer pointer control field length and status field and next frame descriptor field the BDMA receive frame descriptor is almost same as transmit frame descriptor except control field 5 44 ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES Frame Data Pointer 1 Frame Data Pointer 2 Frame Data Pointer N Next Frame Descriptor Next Frame Descriptor Next Frame Descriptor Figure 5 18 BDMA Frame Descriptor Structure The BDMA Tx Rx frame descriptor and frame buffer area should be non cacheable because BDMA can update the value so when we initialize frame descriptor add 0x4000000 for non cacheable access The default owner of transmit BDMA frame descriptor is CPU and the default owner of receive BDMA owner is BDMA after receive frame BDMA controller change the owner bit on BDMA f
82. e is n othing to copy since the data is already in place CMP r0 ri BEQ 1 Stop on CS ie Rl becomes gt R3 Carry has the same sense 6502 le Carry NOT Borrow CMP 3 LDRCC r2 r0 4 STRCC r2 r1 4 BCC 0 Clear rema inder of data to ImageSSZISSLimit to 0 1 LDR MOV 2 CMP STRC BCC MOV Mode_Mask IRQ Mask END 4 8 rl Image ZISSLimit r2 0 r2 r3 4 2 pe Ir EQU 3 EQU 2 ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES CONTROLLING S5N8947 MODULES This chapter presents concept diagrams and example programs for configuring various S5N8947 system control functions Information is presented according to the following Table of Contents S5N8947 PROGRAMMER S MODEL The diagnostic code routines have been written to give practical examples of writing code and evaluating S5N8947 evaluation board This is the target board of the S5N8947 which is embedded controller for network solutions based on ARM7TDMI This section will give you a brief descriptions about how to control the embedded functional blocks and also how to evaluate the S5N8947 Evaluation board HARDWARE OVERVIEW BOOT ROM 8bit data bus 4Mbit 512Kbytes EEPROM Located at ROM e DRAM Normal EDO DRAM 8Mbytes for 55 8947 DRAM Bank0 1 2 3 used CONSOLE UART SIO used e ETHERNET RJ45 connector 7 Wire interface or 2 channel 10
83. e rest interrupt service routine a Figure 5 4 Interrupt Handler Concept Diagram ELECTRONICS 5 7 CONTROLLING S5N8947 MODULES EXAMPLE CODE FOR INTERRUPT HANDLER ROUTINE IRQ FIQ Handler lt except s gt i Wrapper IRQ exception i IROWrapper STMFD sp r0 r12 lr LDR INTOFFSET LDR ro r1 BL MainIntHandler LDMFD sp r0 r12 lr SUBS lr 4 at Wrapper FIQ exception Z FIOWrapper STMFD sp r0 r7 lr LDR rl INTOFFSE LDR rO rl BL MainIntHandler LDMFD sp r0 r7 lr SUBS pc lr 4 Main Interrupt Handler lt Intrhndl c gt ROR KR KR KKK k k k KK RK K K K K KOK K K KOK KOK KOK KOK KOK KOK KOK KOK KOK KOK KOK KOK KOK KOK KK RK ke ke KK MainIntHandler main interrupt handler INPUTS vector vector offset of interrupt NOTES FIQ IRQ wrappers call this routine to handle all interrupts 7 ROK ROKK k k K k k Kk K K Sk K K K k K K K K KOK K K KOK KOK KOK KOK KOK O KO f void MainIntHandler int offset Clear pending bit in the INTPEND register Clear_PendingBit offset gt gt 2 Call interrupt service routine InterruptHandlers offset gt gt 2 0 5 8 S5N8947 ELECTRONICS S5N8947 EXAMPLE FOR INTERRUPT SETUP ROUTINE HEADER FILE lt gt include board h The Bit value of Interrupt registers
84. e system management block DRAM bank control register ELECTRONICS 1 9 ABOUT S5N8947 EVALUATION BOARD S5N8947 GENERAL PORTS S5N8947 s general I O ports are used for several purpose key interrupt input LED status display second Ethernet PHY interface and PCMCIA interface So the signal collision might be occurred when each interface is tested therefore you should set the collision protecting switch 51 52 68 59 511 on 55 8947 evaluation board before each function is operated GPIO and the switch configurations are shown in following Table 1 1 Table 1 1 General and the Switch Configurations on S5N8947 Evaluation Board Function Switch Setting Description 0 LED Status Display 1 ON J16 low PP 7 0 D3 D10 52 58 9 11 OFF Key Interrupt Input S2 ON J16 low PP5 8 10 53 57 1 S8 S9 S11 OFF Second Ethernet S8 S9 ON J16 high PP4 sTXDO PP5 sTXD1 PP6 sTXD2 PP7 sRX DV S1 S2 S11 OFF PP11 sCRS PP12 sRXD0 PP13 sRXD1 PP14 sRXD2 PP15 sRXD3 PP17 sRX ERR PCMCIA S11 ON J16 low PPO PnCE1 PP1 PnCE2 PP2 PIOISI6 PP3 ALE S1 S2 S8 S9 OFF PP5 PnIREQ PP6 PnCD PP7 VS1 PP8 VS2 P10 PBVD1 PP12 PRESET PP13 BufCon P14 DATA_P PP15 CLOCK_P PP17 LATCH_P The function of control switch and the status of LED can be defined by user software MODEM CLOCK S5N8947 Evaluation board has two method for modem clock input You should set the mode
85. e valid bit to 1 To fetch the received data in the Rx interrupt service routine SAR driver has to recognize the next valid queue location in the queue The S5N8947 SAR driver calculates this address as follows Rx buffer descriptor Base address of Rx Done Queue Received Packet Count For full receive operation refer to following flow chart Receive Packet SAR RX Done interrupt occurs Read the buffer descriptor address in the Rx Done queue Fetch the Payload data that Rx buffer descriptor points Clear valid bit of Rx Done Q and Set valid bit of Rx Pool Q If valid bit of next packet is set No il User receive operation f Figure 5 28 SAR Receive Packet ELECTRONICS 5 79 CONTROLLING S5N8947 MODULES S5N8947 DIAGNOSTIC CODE RECEIVE PACKET IN THE INTERRUPT SERVICE ROUTINE Rx Done Interrupt if ReadSARstatus amp INTSTAT RXDONEO SARRXDONEOK PoolPat 0 if DebugFlag_SAR_ISR YES Print n SARisr Interrupt Rx Done 0 endif while 1 1 RxDonePkt ULONG strCFG SAR REG RxDoneQ 0 Addr RxDoneQueO Index if RxDonePkt amp SAR ADRVALID if ReadSARstatus amp INTSTAT RXDON break UserDefinedService strRxBufDescriptor RxDonePkt PoolPat RxDoneQue0_Index if RxDoneQue0_Index DFLT_RXDONEQ_0_SIZI RxDoneQue0_Index 0 Gl Clear SAR address valid bit to release buffer descriptor of Rx done queue Rx
86. each ACK it receives from the master Start Slave Data Byte n Data Byte n 1 Data Byte n X Stop Address Figure 5 15 Sequential Read Operation ELECTRONICS 5 33 S5N8947 CONTROLLING S5N8947 MODULES EXAMPLE CODE FOR IIC READ FUNCTION ROUTINE lt i2c c gt IICRead Sequential READ operation can be initiated by either the Immediate Address READ or Selective READ operation void IICRead UINT ReadAddr UINT ReadDataSize char ReadValue IICSeqRead UINT IIC DEV 0 ReadAddr ReadValue ReadDataSize void IICSeqRead UINT SlaveAddr UINT ReadAddr char ReadValue UINT ReadDataSize UINT ReadCnt UINT ByteAddrMsb Bytes Address 15 8 UINT ByteAddrLsb Bytes Address 7 0 UINT wait ByteAddrMsb ReadAddr gt gt 8 amp Oxff ByteAddrLsb ReadAddr amp Oxff Stepl Setup IICCON Register IICCON START ACK Step2 Send Slave Address with read write Command IICBUF SlaveAddr S WRITE while IICDoneFlag wait 1000000 while IICDoneFlag 1 if wait Print IIC ERROR return wait IICDoneFlag 0 Step3 Send Bytes Address A15 A8 IICBUF ByteAddrMsb while IICDoneFlag wait 1000000 while IICDoneFlag 1 if wait Print n IIC ERROR return wait IICDoneFlag 0 Step4 Send Bytes Address A7
87. el Index DFLT RXDONEQ 1 SIZE RxDoneQuel Index 0 PoolPat Clear SAR address valid bit to release buffer descriptor of Rx done queue RxDonePkt amp SAR_ADRVALID Rx Pool 1 release RxPoolArea ULONG strCFG SAR REG RxPoolQ 1 Addr RxPoolQuel Index RxPoolArea SAR ADRVALID RxPoolQuel Index if RxPoolQuel Index DFLT RXPOOLOQ 1 SIZI RxPoolQuel Index 0 ELECTRONICS 5 83 CONTROLLING S5N8947 MODULES S5N8947 FLOW CHART OF SAR DIAGNOSIS KS8947 SAR Diagnosis Initialize and Setup SAR Tx Done Rx Done Rx pool queues Clear and Configure connection memeory and setup 1 Rate Lookup table Open new connection for default channel and initialize connection memory Execute the operation selected and update new configurations Internal Loop back Enable local loop back Send Packet SAR interrupt service routine Figure 5 30 SAR Diagnosis Flow 5 84 ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES APPENDIX OF SAR Packet Transmit 1 When SAR used with MAC MAC and SAR Buffering should be controlled So MAC Rx Descriptors must be allocated as many as an amount of the SAR Tx Descriptors If not it s possible to be occurred endless packet transmit operation Example define MAC_Rx_Desc_NUM 1024 define Tx_DoneQ_NUM 1024 2 When Packet Tx it can be used with interrupt mode or polling mode Above S5N8947 SAR S W guide
88. en transmit control frame follow this step STEP 1 Set Destination address to CAM 0 STEP 2 Set Source address to CAM 1 STEP 3 Set length or type field op code and operand to CAM 18 STEP 4 Set zero to double word that proceed 18 STEP 5 Enable CAM location by CAMEN register STEP 6 Enable transmit control frame by set the SendPause bit in MACTXCON register STEP 7 Wait control frame transmit is finished ELECTRONICS 5 49 CONTROLLING S5N8947 MODULES S5N8947 RECEIVE ETHERNET FRAME Receive operation of Ethernet frame is performed only on the BDMA Rx interrupt service routine A BDMA Rx interrupt is occurred when a frame reception is finished The detail Ethernet frame reception operation follow this step STEP 1 Get current frame descriptor pointer and BDMA status This step is used for get current frame descriptor s pointer from BDMARXPTR register The BDMARXPTR register value denotes the current processing frame descriptor point or the next frame descriptor pointer So this value is used for check last received frame or not STEP 2 Check Null list interrupt Null list interrupt means BDMARXPTR has 0x00000000 value this value is not accepted so when we met this interrupt we should initialize MAC and BDMA controller again STEP 3 Get Rx Frame Descriptor In this step we get receive frame descriptor s pointer to process data every receive process use BDMA receive frame descriptor pointer STEP 4 Chec
89. ency list for everything in the APPLICATION Add your applicaiton object file lists Ff I k K K K K K K K K K Ck Ck K K K K K kk Ck Ck CK kk ck ck APP_OBJ1 OBJ DIR root o APP OBJS S APP OBJ1 He Ak CKCKCKCKCk k kk kck kc k Ck Ck k ck kck kc k kc K K Ck K K K k k ck kc K KOK kc k Ck k kck kckckck ck k KK kckckck ck kk ck Rules for target image type 1 ram axf ARM executable image for embbedded ICE F 2 ram bin ARM plain binary image for downloading to RAM 3 rom bin ARM plain binary image for ROM Most of the linker command file is common so it is generated with common rule If a make is aborted the file lnkram cmd must be removed He Ak A k k k k k k K K A I K K KOK K K KOK K KOK kc KOK KOK K KOK kc k Ck k kck kckckck ck Ck I I IK ram axf c opt a opt dir N S RAM_OBJ S BSP_OBJS S APP OBJS 85 ECHO S LOPTS 5 OBJ 5 5 OBJS S APP OBJS S ARM LIB N gt lnkram opt S LD first DEBUG elf o ram axf RAMOPTS N VIA lnkram opt 85 opt ram bin c opt a opt dir S RAM_OBJ BSP_OBJS S APP OBJS 85 ECHO S LOPTS S RAM OBJ BSP_OBJS APP_OBJS LIB N gt lnkram opt S LD first begin o BEGIN nodebug o ram bin RAMOPTS N VIA lnkram opt 85 opt rom bin c opt a opt dir _ S BSP OBJS S APP
90. ength of frame data STEP 5 Change ownership to BDMA When ownership is BDMA BDMA can work so after prepare transmit frame descriptor and frame data ownership changed to BDMA owner STEP 6 Enable MAC and BDMA transmit control register to start transmit STEP 7 Change current frame descriptor to next frame descriptor ELECTRONICS 5 47 CONTROLLING S5N8947 MODULES S5N8947 The Ethernet frame transmit flow is depicted in Figure 5 19 Call SendPacket function to transmit packet Get Tx Frame descriptor pointer and Frame buffer pointer Exit SendPacket Check BDMA Ownership CPU owner Copy Frame data to frame buffer Set BDMA control field and frame length Change Ownership to BDMA Enable MAC and BDMA transmit Change the Tx frame descriptor to next frame descriptor MAC Tx interrupt Get Current Frame descriptor pointer from BDMATXPTR Compare gCTxFDPtr and Compare finished current frame descriptor Get Current Frame Buffer pointer Check Ownership Owneship is BDMA Process Error Status gCTxFDPtr Save Good frame status Get Next Frame Descriptor Exit MAC Tx interrupt service routine Figure 5 19 Ethernet Frame Transmit Flow 5 48 ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES CONTROL FRAME TRANSMIT You can transmit a control frame for a remote pause operation in full duplex mode operation 55 8947 Ethernet controller has a function of transmitting and receiving control frame Wh
91. guide POWER SUPPLY S5N8947 Board is designed to operate at 1 8V 3 3V 5V and 12V Therefore power to the S5N8947 is supplied through a DC jack power adapter which supports the voltage 5V and 12V and drives the current at least 1 5A And it is possible to control the power supply by power switch1 5V and switch2 12V ELECTRONICS 1 5 S5N8947 ABOUT S5N8947 EVALUATION BOARD AFE INTERFACE oneubeyy o Lzluaav 0 Le vL vax AHd NOH SeN LV TOUS WINIS NId2Z INVHas INVHas HSV 1J VOS68NSS 1 1 ueis S 21 YIdOLN Zv68NSS IdS NOW 1 1 5 IINQ LZINHV INOHd33 0 4 AEE A8 L oll AHd Joye nBay 19588001 01 ZEZXYN S Od VIOWOd AHd 19588001 01 9 sniels 40 q31 Qq31 5815 9 1euJeui3 OSO 2 152 71 180813 Figure 1 3 Detailed S5N8947 Board Diagram ELECTRONICS 1 6 S5N8947 ABOUT S5N8947 EVALUATION BOARD CLOCK SOURCE AND DISTRIBUTION The Following clock sources are supported at S5N8947 Board System Clock You can use 12 2 oscillator and direct input 50MHz 66MHz 72 2 oscillator XCLK 1 for system clock source by jumper setting The 12MHz clock source is also used for USB clock source with PLL enabled TMODE pin CLKSEL pin FMODE pin of S5N8947 of S5N8947 of S5N8947
92. hat initializes the system environment for application development as well as for standalone ROM code that contains complete execution codes and data ELECTRONICS 3 3 55 8947 EXAMPLE CODE FOR MEMORY AREA DEFINITION All of the user definable memory areas can be configured by the user program except for the code and data areas which are defined by linker option Several examples are provided below Define Data and Code Area Using the armlink Command or Windows Toolkit lt makefile gt Common rules for this BSP RAMOPTS Linker flags for location of ram axf ram bin image ROMOPTS Linker flags for location of rom bin image RAMOPTS 0x1000050 ROMOPTS RO 0x0 RW 0x1300000 Set Up the Special Register Area Using 0 3 0000 as Special Register Base Address lt init s gt LDR ro LDR rl STR rl 0x3FF0000 0x83FF004 r0 Default Address of SYSCFG 0x3FF0000 Base_addr 0x3FF00000 Cache OFF Write Buffer ON Define an Exception Handler Area From 0x1000000 0x1000020 lt board a gt KKK KKK KKK KKK KKK KK KKK KKK KKK KKK KK KKK k k amp k k k k k k k k k k k k k k k k k k k k k k k k k KK k k k ko k k Align Exception Handler Area for 8 exception sources PE 0x1000000 0x1000020 EKER BAAR ERR OR Ge SR IR KERR
93. he DEDUQGEL u uy 2 9 tro elena 2 10 2 2 11 Executing the Image 2 12 Stepping Through the 2 12 Setting Breakpoint aiaia emp MEC E 2 13 Setting a ilte RR 2 14 Viewing Variables Registers and 2 14 Displaying the Code Interleaved with the 2 14 Communicating with the Host Using 2 15 Using Hyperterminal meS ctetu deed aya ADNA SQA Saa RSS ha tear E D 2 15 Hyperterminal Setup for UART Communication 2 15 Using the S5N8947 UART with 2 16 Chapter 3 Memory Management aureo LUIN o 3 1 S5N8947 Memliory Maps fud EU 3 2 Memory ete tent N 3 3 Special Registels incierto LO RENTRER EAD ERTREATRR REDE EAYREATRERER RR RR 3 3 DRAM 3 3 3 3 Example Code For Memory Area 3 4 About Beglhnt
94. ically and breaks at the first line of the code Not Using the ARM Project Manager 1 Execute the ARM Debugger For Windows This software is included in the ARM Windows Toolkit 2 51 program group 2 Choose Load Image from the File menu or click the Open File button to select the ARM Image file project_name axf you want to load 2 10 ELECTRONICS S5N8947 USING THE ARM SDT FOR S5N8947 PROJECTS CONFIGURING THE DEBUGGER 1 Select Configure Debugger from the Options menu The Debugger Configuration dialog box is displayed There are two Target Environments as follows ARMulator Lets you execute ARM programs without physical ARM hardware by simulating ARM instructions in software Remote A Connects the ARM debugger directly to a target board or to an EmbeddedICE unit that is attached to a target board NOTE Please note the following requirements for using Remote A 1 a direct target board connection requires Angel debug monitor software 2 the EmbeddedICE software must be version 2 0 or greater and 3 application programs must be linked using the SDT 2 5 C language library Select the appropriate variants for your application and click the Configure button The ARMulator Configuration or Angel Remote Configuration dialog box is displayed For ARMulator configuration set the Processor Variant to ARM7TDMI and the Processor Clock Speed to 33 00 MHz For Angel Remote Configuration set the Remote Connection type Por
95. initialize the DRAM read write area IMPORT EXPORT AREA ALIGN ENTRY HdwInit SysInitVars BEGIN CODE READONLY Ck k Ck k k Ck k Ck Ck Ck k Ck k k lt k k Ck k Sk k k k K k lt K k k K lt k k k lt k Sk Ck k k k kk k ck k k Sk k k k k k k k ko ko F main Pseudo C entry point The C compiler genereates a reference to the symbol main to ensure that the object module containing the entry point gets pulled in P This entry point is never actually called CK K Ck k k k k k lt k k k K K k k K k lt k k k K K lt k x k K lt k k K K lt k k K K K lt k x K K lt k k K K lt k EXPORT main main k k k KKK k K x k k lt Ck k x lt k K lt x k x x k K lt x k x lt k K x x k x x k K lt x k K lt k K x x k K x K K lt x k x lt x K ko x k x x lt lt ko First instruction to be executed A Fr Branch to the HdwlInit entry point in the BSP 2 B lt k k k k Kk k k Ck k k lt x k x lt k K K k x x k K lt x k K lt k K x x k K lt k K lt x k K lt k K x x k x x k K lt x k kk ko K x x k x kx lt lt lt lt HdwInit Ck Ck ck k Kk k k k k Ck Ck k Ck k Kk ck k Ck k lt lt Ck k k K k k k lt k k k k ck k k k amp k k k k k amp k k ck k k k amp k k k Sk k k k k k ko ko The linker defines the following symbols which allow us to
96. k k k k k k k ck k k k kk k k k k k k k ko kx lt Cleanup and other rules Clean echo off 85 RM opt OBJ 85 RM err 85 RM axf S RM bin 85 map echo on c opt makefile echo COPTS1 gt c opt echo COPTS2 gt gt c opt echo COPTS3 gt gt c opt echo COPTS4 gt gt c opt a opt makefile echo S AOPTS1 gt a opt 5 52 gt gt a opt S AOPTS3 gt gt a opt dir S MKDIR OBJ_DIR ELECTRONICS 2 9 USING THE ARM SDT FOR S5N8947 PROJECTS S5N8947 DEBUGGING AND EXECUTING YOUR DEMO PROJECT When you build a project the Project Manager creates a new subdirectory called Debug or Release depending on the variant you select This subdirectory is located below the current working directory Several object files are placed in this variant subdirectory The executable ARM image code lt project_name gt axf is also generated in this subdirectory If you are using the ARM Project Manager you can then start the ARM Debugger for Windows and load the image of the application you are developing This procedure is described below STARTING THE DEBUGGER There are two ways to start the debugger and load the executable image Using the ARM Project Manager Click the Debug button of the Project Manager to open the ARM Debugger For Windows The Debugger loads your project image automat
97. k received frame is valid or not Check received frame descriptor status field to check received frame is valid or not STEP 5 1 Get received frame to memory buffer This step is main function that copy received frame to memory buffer to process So in the various RTOS can announce received frame in this step STEP 5 2 Process error status In this step check received frame descriptor status field to check this frame has error or not STEP 6 Change ownership to BDMA Change BDMA ownership to BDMA because BDMA can use this frame descriptor after receive operation STEP 7 Get next frame descriptor pointer to process When enter BDMA receive interrupt service routine we process all received frame before receive interrupt STEP 8 Check BDMA Not Owner status bit in the BDMASTAT register This Not Owner bit means all BDMA frame descriptor is used so we need set MAC and BDMA control register to receive frame normally 5 50 ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES The receive operation in the BDMA Rx interrupt service routine is described in Figure 5 20 BDMA Rx interrupt serviceroutine Get Current Frame Descriptor CRxPtr and BDMA status Clear status and MACInitialize Get Rx Frame Descriptor Check Received Process error status Frame Status No error Get received frame to memory buffer This function is main routine of process the received frame Change Ownership to BDMA Get Next frame Descriptor pointer
98. lag SPIDoneFlag 0 IOPDATA CS_port Step3 1 Send write command IOPDATA amp 5 port TXCHR WRITE while SPICMD amp START TRANS SPICMD START TRANS while SPIDoneFlag SPIDoneFlag 0 ELECTRONICS 5 93 CONTROLLING S5N8947 MODULES 5 94 Step3 2 Send Bytes Address 15 8 TXCHR ByteAddrMsb lt lt 24 while SPICMD amp START TRANS SPICMD START TRANS while SPIDoneFlag SPIDoneFlag 0 Step3 3 Send Bytes Address 7 0 TXCHR ByteAddrLsb 24 while SPICMD amp START TRANS SPICMD START_TRANS while SPIDoneFlag SPIDoneFlag 0 Step3 4 Send Multiple Data for WriteDataCnt 0 WriteDataCnt lt SizeOfData WriteDataCnt t TEMP WriteData WriteDataCnt TXCHR lt lt 24 while SPICMD amp START TRANS SPICMD START TRANS while SPIDoneFlag SPIDoneFlag 0 IOPDATA CS port Step4 Send write disable command amp 5 port TXCHR WRDI while SPICMD amp START TRANS SPICMD START TRANS while SPIDoneFlag SPIDoneFlag 0 IOPDATA CS port Step5 Disable SPI gSPICFG amp ENABLE SPICFG gSPICFG gSPICFG amp SPI INT SPICFG gSPICFG S5N8947 ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES EXAMPLE CODE FOR SPI READ FUNCTION R
99. lkfrq int fSPICLK SPICFG gSPICFG len 0x07 8 gSPICFG len amp 0x1f00 SPICFG gSPICFG gSPICFG amp SPI INT NORMAL ORD gSPICFG NORMAL ORDER SPICFG gSPICFG Enable SPI Interrupt SysSetInterrupt nSPI INT SPIisr Enable Intr nSPI INT disable TimerO interrupt clock frequency ER TOGGLING AT THE E S5N8947 support upto 5MHz GDMA ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES EXAMPLE CODE FOR SPI WRITE FUNCTION ROUTINE lt spi c gt SPIWrite The CAT24WC32 64 writes up to 32 bytes of data in a single write cycle using the page write operation void SPIWrite UINT WriteAddr char WriteData UINT SizeOfData SPIPageWrite WriteAddr WriteData SizeOfData void SPIPageWrite UINT WriteAddr char WriteData UINT SizeOfData UINT WriteDataCnt UINT ByteAddrMsb Bytes Address 15 8 UINT ByteAddrLsb Bytes Address 7 0 U32 TEMP ByteAddrMsb WriteAddr gt gt 8 amp Oxff ByteAddrLsb WriteAddr amp Oxff Stepl Setup SPICFG Register gSPICFG SPI INT SPICFG gSPICFG gSPICFG SPI ENABLE SPICFG gSPICFG Step2 Send write enable command IOPDATA amp CS_port TXCHR WREN while SPICMD amp START TRANS SPICMD START TRANS while SPIDoneF
100. m clock setting resistor R152 R153 STM from S5N8951 evaluation board Not used just for debug VCXO on S5N8947 board STM R153 OPEN Clock Input Figure 1 7 ADSL Modem Clock Signal Selection 1 10 ELECTRONICS S5N8947 ABOUT S5N8947 EVALUATION BOARD ETHERNET INTERFACE S5N8947 has two 10 100 Mbps Ethernet controller 5538947 Evaluation board supports two 10 100 Mbps Ethernet interface Two External PHY chips used in S5N8947 Board is able to operate 10 100 M bps 55 8947 Board s Ethernet connector RJ45 has Ethernet adapter side pin configuration which supports communication with the host PC s NIC You can also connect S5N8947 Evaluation board to hub or router direct without twisting cable Table 1 2 RJ45 Pin Configurations for Adapter Side External PHY interface J10 Pin Number Descriptions Pin Number Descriptions o e l s les 4 C J s Ethernet Status LED LED location 011 020 Table 1 3 Ethernet Status LED D11 D16 100Mbps Collision detection LED for External PHY D12 D17 Collision detection LED for External PHY D13 D18 100Mbps idle 10Mbps Link Link integrity LED for external PHY D14 D19 Transmit data LED for external PHY D15 D20 Receive data LED for external PHY Serial UART amp JTAG Interface S5N8947 Evaluation board supports a 9DIP SUB serial connector for UART S5N8947 MCU supports JTAG port JP2 It can be used as Circuit Emulator ex Embedded IC
101. n read the PHY status PHY has a unique address and there is many addresses for PHY internal control and status registers The operation of read and write to the station management register is described in below Mil Station Management Read Operation STEP 1 Specify the PHY address and a PHY internal register address in the STACON register STEP 2 Set busy bit in STACON then a PHY read operation is started STEP 3 Check Busy bit in STACON after read operation is finished this bit is cleared STEP 4 Read STADATA the STADATA register has the value of the PHY station register MII Station Management Write Operation STEP 1 Write the station management data to STADATA register STEP 2 Specify the PHY address and a PHY internal register address in STACON STEP 3 Set Write and Busy bit in STACON then PHY write operation is started STEP 4 Check Busy bit in STACON when the write operation is finished this bit is cleared 2 Get unique H W MAC address The every MAC has unique H W address this is used when filtering incoming message from network The CAM is used for filtering incoming message address In CM47 M66 V1 0 use IIC EEPROM for store MAC H W address for system 3 Setup MAC BDMA controller This function is used for setup MAC and BDMA controller register and Interrupt service routine for receive and transmit The each step of MAC initialize function is described in below STEP 1 Disable MAC and BDMA interrupt Disabl
102. nNum phy port StrCFG SAR CHAN ChanNum strCFG VPLOOKUP TBL AAL SARConnNum ChanNum else NC Scheduling StrCFG SAR CHAN ChanNum strCFG VPLOOKUP TBL SchConnNum ChanNum StrCFG SAR CHAN ChanNum strCFG VPLOOKUP TBL AAL SARConnNum ChanNum else switch strCFG_CONNMEM ChanSizePerVP case 16 VCMaskBit VPLT_VCBITMASK_4 break case 32 VCMaskBit VPLT_VCBITMASK_5 break case 64 VCMaskBit VPLT_VCBITMASK_6 break case 128 VCMaskBit VPLT_VCBITMASK_7 break case 512 VCMaskBit VPLT_VCBITMASK_9 break case 1024 VCMaskBit VPLT_VCBITMASK_10 break strCFG_SAR_CHAN ChanNum strCFG_VPLOOKUP_TBL VC_BitsMask VCMaskBit StrCFG SAR CHAN ChanNum strCFG VPLOOKUP TBL SchConnNum ChanNum nVCI StrCFG SAR CHAN ChanNum strCFG VPLOOKUP TBL AAL SARConnNum ChanNum nVCI OpenChanNum Initialize Scheduler connection Table if strCFG SAR CHAN ChanNum strCFG VPLOOKUP TBL SchConnType VPLT VCCONN StrCFG SAR CHAN ChanNum strCFG SCH CONNTBL SCH CONN NUM ChanNum StrCFG SAR CHAN ChanNum strCFG SCH CONNTBL ConnLevel SCHCT VCCONN else Add the VP connection algorithm here when 5171 StrCFG SAR CHAN ChanNum strCFG SCH CONNTBL SCH CONN NUM E lI ll Co strCFG_SAR_CHAN ChanNum strCFG_VPLOOKUP_TBL SchConnNum StrCFG SAR CHAN ChanNum strCFG SCH CONNTBL ConnLevel SCHCT VP
103. nal sources Two examples of such events are e Externally generated interrupts e An attempt by the processor to execute an undefined instruction When handling exceptions the previous processor status must be preserved so that the execution of the original user program can resume immediately after the appropriate execution routine is completed The ARM processor recognizes seven types of exceptions Reset Occurs when the CPU reset pin is asserted This exception normally occurs to signal a power up or to initiate a reset following CPU power up It is therefore useful for initiating a soft reset Undefined Instruction Occurs if neither the CPU nor any attached coprocessor recognizes the instruction currently being executed Software Interrupt A user defined synchronous interrupt instruction which allows a program running in User mode to request privileged operations that run in Supervisor mode Pre fetch Abort Occurs when the CPU attempts to execute an instruction which has been pre fetched from an illegal address In this case an illegal address is an address that the memory management subsystem has determined is inaccessible to the CPU in its current mode Data Abort Occurs when a data transfer instruction attempts to load or store data at an illegal address IRQ Occurs when the CPU s external interrupt request pin is asserted Low and the bit in the CPSR is clear FIQ Occurs when the CPU s external fast interrupt request pin i
104. nation register MOVS pc lr Each exception type requires the use of a different instruction The actual value that is stored in the PC is also dependent on the exception type as follows Undefined Instruction MOVS pc lr SWI MOVS pe ir Pre fetch Abort SUBS pc lr 4 Data Abort SUBS lr 8 IRQ SUBS lr SUBS pc lr 4 SAMPLE EXCEPTION HANDLER The basic form of an exception handler is as follows Default_HandleException lt Save value of registers to the stack area gt lt Exception service routine performed by user application gt lt Restore the values in the stack area to the corresponding registers gt lt Return the PC value according to exception type gt 4 4 ELECTRONICS S5N8947 EXCEPTION HANDLING INSTALLING AN EXCEPTION HANDLER You must install any new exception handler in the vector table Once the installation is complete the new handler executes wherever the corresponding exception occurs Installing the Handlers at Reset Exception handlers can be included in a boot program or they can be standalone programs Boot programs are used to initialize the system environment for application development Standalone programs on the other hand do not rely on the debugger or debug monitor to start program execution This makes it possible to load the vector table directly as part of your assembler reset or startup code If your ROM area starts at memory location 0 0 you can use a simple
105. nection number 8 Word Offset 4 For full information about Scheduler connection table refer to user s manual Setup AAL Connection Table each table is 8 word length Address CONNTBL BASE AAL connection number 8 Word Offset 4 With this table the buffer pool type and packet type is determined for reception For full information about AAL connection table refer to user s manual Setup SAR Connection Table each table is 8 word length Address CONNTBL BASE SAR connection number 8 Word Offset 4 For full information about SAR connection table refer to user s manual ELECTRONICS 5 71 CONTROLLING S5N8947 MODULES S5N8947 DIAGNOSTIC CODE SETUP VP LOOKUP SCHEDULER AAL SAR CONNECTION TABLE 4 SetNewConn Initialize New Connection with default setting 24 int SetNewConn UINT nVPI UINT nVCI UINT phy port UINT Qos UINT nPCR UINT nMBS UINT nSCR UINT nAAL UINT ChanNum i VCMaskBit 0 UINT if strCFG SAR REG CAM SAR CAM ENABLE Using Loockup Table if strCFG CONNMEM ChanSizePerVP lt nVCI return OVERSIZE if strCFG SAR REG UTO LEVEL UTOPIA MODE 11 if ChanNum strCFG CONNMEM ChanSizePerVP nVPI nVCI gt SIZE return OVERSIZE 1 if ChanNum strCFG CONNMEM ChanSizePerVP phy po
106. nfiguration and controlling SAR block It includes managing connection memory and buffer pool also The full contents are as follows e Configure SAR registers e Setup SAR queues Done queue Pool queue e Control connection memory e Transmit packet e Receive packet e Handle SAR interrupt e Flow chart of SAR Diagnosis This diagnostic code use a few data structures which provide effective solution for S5N8947 SAR control For example the structure C gSARChan is composed of channel information members and C gSARregTable contains the SAR register information including the clock values and constitution of queue For more these structures and other tables refer to the header file sar h With this diagnostic code you can understand and control the S5N8947 SAR more easily 5 64 ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES CONFIGURE SAR REGISTERS To open a connection and transmit or receive data through the S5N8947 SAR the following operation has to be performed SAR Register Initialization e Setup clock registers Set SAR clock and UTOPIA clock as your system e Setup connection memory registers Initialize the base address and size of SAR connection memory e Setup SAR queue registers Allocate the SAR Tx done queue Rx done queue Rx pool queues linitalize SAR Allocate SAR memory queue Tx Done Rx Done Rx Pool Setup clock values SAR clock UTOPIA clock Setup connection memory base address si
107. ntroller registers For the detail of these functions refer to bus diagnostic source code provided i2c c lt Main Menu gt CM47 M66 V1 0 Board Diagnostic Ver 1 0 Me UA Ti GD I2 I Et US SA Al Us FL c gt 10 Q gt Q N mory TEST RT TES mer TEST MA TES C BUS TEST O Port TES hernet TES B Tes R Tes l Tes er Program Download ASH Memory Operation oor ach cb ct Select One Selecting 5 12C BUS TEST at main menu shows sub menu of I2C bus test below 1 2 3 4 5 6 7 8 9 5 36 IIC Test Menu IIC IIC IIC IIC ITG IIC LIC IO Q N ES Page Write Sequentail Read Write Page Write Sequentail Read Write Byte random Loopback Te configurati Exit IIC Test Test INT Read Test INT Test INT Test POLL Read Test POLL Test POLL R W Test St INT on view Select One Page Write Test INT write test by interrupt Sequentail Read Test INT IIC read test by interrupt Read Write Test INT IIC Read Write test program by interrupt method Page Write Test POLL IIC Write test program by polling method Sequentail Read Test POLL IIC read test by polling Read Write Test POLL IIC Read Write test program by polling method Byte ran
108. o dummy function for i 0 i lt MAXHNDLRS i InterruptHandlers i DummyIsr ROR k KKK K k K I K K K I KOK K KOK KOK KOK KOK K KOK KOK KOK KOK KOK IA KOK KOK KO KOK KO KOK KOK KOK KO KOR KOK KE SysSetInterrupt Set the interrupt handler k K k k Kk K K k K K K k K K SK K K KOK K KOK KOK KOK KOK KOK K K KOK KOK KOK KOK KOK KOK KOK KOK KOK KOK KOK KOK KOK R KOK O O KO f void SysSetInterrupt unsigned long vector void handler Initialize each interrupt handler to user defined function InterruptHandlers vector handler ELECTRONICS 5 11 CONTROLLING S5N8947 MODULES UART S5N8947 S5N8947 has one UART Channel To setup the UART Channel follow the steps in figure 5 5 below After finishing setting up with the concept diagram for using UART in figure 5 6 you can use UART as a communication method between host and target system UART Setup Set the following value in the ULCON registers Word length Number of Stop bit Parity mode Serial clock infra red mode Write the baud rate divisor value to the UBRDIV registers Calculate this value as follows Divisor value int Source clock aud rate x 16 1 Set the following values in the UCON registers Receive mode Receive status interrupt enable Transmit mode Data set ready Send break Loop back enable Set console register Figure 5 5 Concept Diagram for UART Initialization ELECTRONICS S5N8947 CONTROLLING S5N894
109. on set timer enable bit in the TMOD register Figure 5 7 Concept Diagram for Setting a Timer ELECTRONICS 5 17 CONTROLLING S5N8947 MODULES S5N8947 EXAMPLE CODE FOR SETTING A TIMER lt Timer c gt RunTimers Sets timer registers values amp Interrupts and runs the timers Ti void RunTimers unsigned int msec t0 unsigned int msec tl unsigned int msec_t2 SysSetInterrupt nTIMERO INT isr TestTimer0 SysSetInterrupt nTIMER1 INT isr TestTimerl SysSetInterrupt nTIMER2 INT isr TestTimer2 nable Intr nTIMERO INT nable Intr nTIMERl INT nable Intr nTIMER2 INT p Ei TDATAO msec 0 50000 1 set timerO 1 msec 1 50000 1 set timerl msec t2 50000 1 set timer2 Run Timers interval mode TMOD TimerO Run Timerl Run Timer2 Run Timer0 1 2 Interrupt Service Routine void isr timer0 void if DebugFlag_L tm cnttt IOPDATA 1 lt lt tm cnt 8 gt l l Ea endif User codes needs here 77 void isr_timerl void if DebugFlag_Timer YES Print nTimerl Expired fendif User codes needs here void isr_timer2 void if DebugFlag_Timer YES
110. on OK The COM1 or COM2 Properties dialog box is displayed 4 Set Bits per Second to its proper value The other properties should be set to their default value You have now created a new empty terminal that is connected to the specified serial port The terminal window is displayed HYPERTERMINAL SETUP FOR UART COMMUNICATION Follow these steps to set up the HyperTerminal software for UART communication with the S5N8947 1 Select Properties from the File menu 2 When the lt gt Properties window is displayed click the Configure button 3 Click the ASCII Setup button and select the following check menus Baud Rate 38400 Data Bit 8 Parity None Stop Bit 1 Flow Control None NOTE These values are default values for 55 8947 Diagnostic ROM User can change these values when needed after change UART Configuration ELECTRONICS 2 15 USING THE ARM SDT FOR S5N8947 PROJECTS S5N8947 USING THE S5N8947 UART WITH HYPERTERMINAL For information about how to set up the UART please refer to the flowcharts and sample source code in Chapter 4 this manual To send and receive messages to from the host using the S5N8947 UART follow these steps Sending a Message to the Host When you have properly set up the UART you can send a message to the host by entering the following command Print Hello Receiving a Message from the Host To receive a message from the host enter the following command
111. outine Where the IIC prescaler frequency fSCL is defined at sysconf h which is the S5N8947 target system configuration header file EXAMPLE IIC BUS SETUP ROUTINE I2C C I ICSetup I2C Setup Routine Initialize IIC control block to use IIC EEPROM void IicSetup void Reset IIC Controller IICRESET Set Prescale Value fSCL is serial clock frequency SCL defined at sysconf h IIC PS SetPreScaler int fSCL support upto 100KHz Enable IIC Interrupt SysSetInterrupt nlIC INT IICisr Enable Intr nIIC INT SetPreScaler LJ AG alculat UINT 5 28 SetPreScaler UINT sclk return U INT MCLK sc1k 3 0 16 0 0 5 prescaler register value from Serial clock frequency sclk ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES WRITE C FUNCTION LIBRARY The KS24C321 641 writes up to 32 bytes of data page size A page write operation is initiated in the same way as byte write operation However instead of finishing the write operation after the first data byte is transferred the master can transmit up to 31 additional bytes The KS24L321 641 responds with an ACK each time it receives a complete byte of data See Figure 5 13 Slave First Word Second Word Data Byte 0 Dat
112. outine lt gt 5 11 Ni um 5 12 Example Code for UART Setup Routine lt gt 5 14 Uart Test Program Description in Diagnostic 00222444 0 5 16 REIN a m M E ER ES 5 17 Example Code for Setting a Timer lt Timer c gt nennen 5 18 Timer Test Program Description in Diagnostic 5 19 cia ue aa 5 20 Example Code for Setting Up and Executing lt gt 5 21 Test Program Description in Diagnostic 5 23 IC BUS CONTONE r cL 5 25 Functional Descriptions of 5241321 6 1 5 25 Senza efte EN E TT T 5 26 Initialize the Bus Controller u nennen nennen nnne nnn nnn nnns 5 28 Example for Bus Setup Routine lt 12 gt sss nne 5 28 IG Write C Function BIDraty terr rr 5 29 Example Code for IIC Write Function Routine lt 2 gt 5 30 IG Read G FE nction l ibrary itt retenta eter 5 32 Example Code for Read Function Routine lt 2 gt 5 34 lic Bus Test Program Des
113. presents Tx Done interrupt But we recommand to use Polling Mode Tx Done check operation Example First of all Don t use Tx Done interrupt service routine on ISR Then Need MAC Descriptor Buffer 1024 when Sar Tx Descriptor is 1024 ULONG sarTxcount 0 ULONG MacRx2SarTx ULONG SarFramePtr ULONG length OTHER_PKT_INFO Info2 MACFrame pFrame nt txIndex icnt 0 k LONG currentTxDoneA nextTxDoneA nt returnValue init Increment the Done Index and do a modulo to rap around the index to point to the the start of the circular queue if end of queue Aal5Gddb 0 pktmem gt TxDoneIdx Aal5Gddb 0 pktmem gt TxDonelIdx 5 txIndex Aal5Gddb 0 pktmem TxDoneIdx pFrame sMACFrame SarFramePtr SarFillHead U8 pFrame gt SarHeaderAddr length Packet Transmit Polling Mode currentTxDoneA ULONG Aal5Gddb 0 Config TxDoneAddr sarTxcount if currentTxDoneA amp ADRVALID while 1 Tx Done Check amp Tx Descriptor Refresh for Next cycle ULONG Aal5Gddb 0 Config TxDoneAddr sarTxcount amp ADRVALID ELECTRONICS 5 85 CONTROLLING S5N8947 MODULES S5N8947 SAR int sarTxcount sarTxcount TX_POOL_BUFS TX_POOL_BUFS 1024 nextTxDoneA ULONG Aal5Gddb 0 Config TxDoneAddr sarTxcount if nextTxDoneA amp ADRVALID continue else break while inner Sar Tx Over Run Check
114. project ELECTRONICS S5N8947 USING THE ARM SDT FOR S5N8947 PROJECTS USING COMMAND LINE TOOLS TO BUILD PROJECTS Three activities are required to build a project compilation assembly and linking You can perform these activities using the toolkit components or you can enter the commands directly on the command line Compile X armcc lt options gt lt C source gt Assemble armasm lt options gt lt assembly source file gt Link armlink lt options gt lt object files list gt When using the command line to build a project it is convenient to use the armmake utility Before you can execute armmake you must create a makefile in the working directory A sample makefile is included in the S5N8947 demo project armmake parameters not required Sample Makefile ARMINC c isiarm arm251 include ARM LIB c isiarm arm251 lib armlib_cn 32b BSP_DIR BSP Common rules for this BSP RAMOPTS Linker flags for location of ram axf ram bin image 5 Linker flags for location of rom bin image e RAMOPTS 0x1000050 ROMOPTS RO 0x0 RW 0x1300000 Ck ck ck ck k kk k k Ck k k Ck k Ck k k K k k Ck k k K Ck k k x k k lt k k k k k k k k k amp k k k k k kk k k k k k amp k k k amp k k kx k k ko ko A few important make options The following must be defined CC Comm
115. rame descriptor to CPU owner then it can be used by CPU STEP 5 Set the CAM Control register and the MAC address value CAM is used for filtering received frame from other frames The S5N8947 has 21 CAM but in the diagnostic code uses only 1 CAM In diagnostic code for CM47 M66 V1 0 use EEPROM for store H W address So before enable the receive operation We should load the MAC address to CAM and set the value of CAM enable control register The STEP 5 is doing this operation STEP 6 Enable interrupt BDMA Rx and MAC Tx interrupt In our diagnostic code we only use BDMA Rx interrupt for receive operation and MAC Tx interrupt for transmit operation You can refer transmit and receive operation of Ethernet controller for more detail of BDMA Rx and MAC Tx interrupt service routine STEP 7 Configure the BDMA and MAC control registers This step prepare all BDMA and MAC control register to operate After this set of BDMARXCON and MACRXCON Ethernet controller can receive incoming frame ELECTRONICS 5 45 CONTROLLING S5N8947 MODULES S5N8947 The value for MAC and BDMA basic operation is described in Table 5 1 Table 5 1 MAC and BDMA Control Register Set Value RegisterName Function Controlbit Description MACCON MAC global control register MACRXCON MAC Receive control register MAC Receive enable StripCRC Check the CRC but strip the from message BDMATXCON BDMA Transmit control register BTxBRST BDMA tr
116. ransition of the SDA line while SCL remains in High level All bus operations must be completed by a stop condition see Figure 5 10 1 1 lt lt Start Data ACK Stop Condition Valid Condition Figure 5 10 Data Transmission Sequence Data valid Following a start condition the data becomes valid if the data line remains stable for the duration of the High period of SCL New data must be put onto the bus while SCL is Low Bus timing is one clock pulse per data bit The number of data bytes to be transferred is determined by the master device The total number of bytes that can be transferred in one operation is theoretically unlimited ACK Acknowledge An ACK signal indicates that a data transfer is completed successfully The transmitter the master or the slave releases the bus after transmitting eight bits During the 9th clock which the master generates the receiver pulls the SDA line low to acknowledge that it has successfully received the eight bits of data see Figure 5 11 But the slave does not send an ACK if an internal write cycle is still in progress In data read operations the slave releases the SDA line after transmitting 8 bits of data and then monitors the line for an ACK signal during the 9th clock period If an ACK is detected but no stop condition the slave will continue to transmit data If an ACK is not detected the slave terminates data transmission and waits for a stop condition to be issued by the m
117. resenting the supply voltage After determining the supply voltage 55 8947 writes the 11 bit command to TPS2214A Finally the MCU sends the reset signal to the card The basic interrupt service routine is depiced below void isr PCMCIA Card Detect void U16 vs U32 wait card_detection 0 if INTPEND gt gt 1 amp 0 00000001 5 100 Clear PendingBit 1 for wait 0 wait 500000 wait 4 delay for PCMCIA card insertion initTPS2214A voltage sensing with VS1 VS2 vs IOPDATA amp 0x0180 if vs gt gt 7 0x03 5V operation configuring TPS2214A for 5V operation 52214 5V NCC 5V VPP 5V else if vs gt gt 7 0x01 3 3V operation configuring TPS2214A for 3 3V operation wrTPS2214A VCC_3V VCC 3 3V VPP OV else card_detection 1 Print Voltage Detection Fail return for wait 0 wait lt 10000 wait delay for PCMCIA card card reset PCMCIA Card Reset Print Detection End reset ELECTRONICS
118. riteUsbRegister USB INTE REGISTER 0x041F Reset Ep0 4 Enable Write Start Address of EPO 1 3 WriteUsbRegister USB 5 REGISTER EpOInOutdata R R iR 0 0000 T WriteUsbRegister USB_E1SA_REGISTER IntOutdata WriteUsbRegister USB E3SA REGISTER BulkOutdata USB_IntHandler This function is Service Routine for USB Interrupt USB Interrupts are Endpoint Interrupt and H W Status Interrupt ZZ ELECTRONICS 5 55 CONTROLLING S5N8947 MODULES void USB_IntHandler void ULONG status S5N8947 Read USB Interrupt Regsiter ReadUsbRegister USB INT REGISTER status WriteUsbRegister USB_INT_REGISTER 0x00 Interrupt Clear status amp 0x071f if status amp 0x0100 1 Print Nn USB Diag Log Suspend Mode n Disable ENABLE_SUSPEND bit in PM register ClearUsbRegister USB PM REGISTER 0x01 if status amp 0x0200 1 Print Nn USB Diag Log Resume Mode Nn Enable ENABLE SUSPEND bit in PM register SetUsbRegister USB_PM_REGISTER 0x01 if status amp 0x0400 Print Nn USB Diag Log Reset Mode Mn InitializationUSB if st
119. rmat Big Endian For the remaining options select the default values Setting Linker Options 1 2 Select Tool Configuration for project name apj from the Project menu and choose armlink Configure the linker options as follows For the Output page Output Formats Absolute ELF For the Entry and Base page Base of Image lt Read Only gt 0x1300000 start address of code area lt Read Write gt blank start address of data area NOTE When leaving Read Write base blank the Read Write area starts from the next address to the end of Read Only Area For the Image Layout page Place at start of image Object File Init o beginning object file name Area Name INIT beginning area name For the remaining options select the default values NOTE For additional options and for descriptions of the compiler assembler and linker please refer to chapters 1 2 and 3 of the ARM Software Development Toolkit Reference Guide Building Your Project When you have added the files you require and have set up the global options and parameters for specific files you are ready to build your project 1 2 4 Select Build project name Debug from the Project menu or click the Build button The Force Build option lets you rebuild all project files simultaneously The current build status is reflected in the Build Log which appears at the bottom of the Project Window when you build the
120. ronics Co Ltd San 24 Nongseo Ri Giheung Eup Yongin City Gyeonggi Do Korea C P O Box 37 Suwon 449 900 TEL 82 031 209 1946 FAX 82 031 209 6547 Home Page http www samsungsemi com Printed in the Republic of Korea Table of Contents Chapter 1 About S5N 8947 Evaluation Board CIBO NIME 1 1 55 8947 Board 000000 senes inn nas aaah n 1 1 2 1 4 5 o Eae E EI EM 1 5 55 E ATA E E EAEE EPE EE M 1 5 Clock Source And 1 7 n CL REOR 1 8 Gerieral l O Ports eet ee e a o nue 1 10 Modem ClO CK REESE 1 10 THERMO t ITSM ACS I sx 1 11 Chapter 2 Using the ARM SDT for S5N8947 Projects roe Mc 2 1 S5N8947 Development Environment a 2 2 Building a Demo Project Windows 95 98 2000 2 3 Using Command Line Tools to Build 2 5 Debugging and Executing Your Demo 2 10 Starting t
121. rt nVPI lt lt 3 nVCI gt CHAN SIZE return OVERSIZE for i 0 i OpenChanNum i if OpenChan i ChanNum return OPENCHAN 1 Using nVPI lt lt 15 nVCI lt lt 3 phy port 0 if Channel Number gt CHAN SIZE return OVERSIZE if OpenChanNum gt CHAN_SIZE return OVERSIZE for i 0 i OpenChanNum i ChanNum OpenChan i if strCFG SAR CHAN ChanNum CONNPATTERN CONNPATTERN return OPENCHAN E Add the Channel Number Searching Algorithm here ChanNum OpenChanNum Make New Connection Parameters OpenChan OpenChanNum ChanNum StrCFG SAR CHAN ChanNum VPI nVPI StrCFG CHAN ChanNum VCI nVCI StrCFG SAR CHAN ChanNum AAL nAAL StrCFG SAR CHAN ChanNum PTI DFLT PTI StrCFG SAR CHAN ChanNum PORT phy port StrCFG SAR CHAN ChanNum CONNPATTERN CONNPATTERN to Search Same Connection OpenChan OpenChanNum 1 Oxff 5 72 ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES When CHAN_SIZE 32 Initialize CAM Table Else Initialize VP Lookup Table StrCFG SAR CHAN ChanNum strCFG VPLOOKUP TBL SchConnType SCHCONNTYPE if strCFG SAR REG CAM 5 CAM ENABLE if SCHCONNTYPE VPLT_VPCONN VP Scheduling StrCFG SAR CHAN ChanNum strCFG VPLOOKUP TBL SchCon
122. s a start condition followed by another slave address with the R W bit set to 1 The KS24L321 641 then sends an ACK and the 8 bit data stored at the pointed address At this point the master does not acknowledge the transmission generating a stop condition The KS24L321 641 stops transmitting data and reverts to stand by mode Start Slave First Word Second Word Start Slave Data Byte n X Stop Address Address Address Address UU ULE PE EET Figure 5 14 Random Address Byte Read Operation 5 32 ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES Sequential Read Operation Sequential read operations can be performed in two ways current address sequential read operation and random address sequential read operation The first data is sent in either of the two ways current address byte read operation or random address byte read operation described earlier If the master responds with an ACK the KS24L321 641 continues transmitting data If the master does not issue an ACK generating a stop condition the slave stops transmission ending the sequential read operation Using this method data is output sequentially from address n followed by address n 1 The word address pointer for read operations increments to all word addresses allowing the entire EEPROM to be read sequentially in a single operation After the entire EEPROM is read the word address pointer rolls over and the KS24L321 641 continues to transmit data for
123. s asserted Low and the F bit in the CPSR is clear ELECTRONICS 4 1 EXCEPTION HANDLING S5N8947 EXCEPTION HANDLING THE EXCEPTION VECTOR TABLE The ARM processor supports seven types of exceptions Each type is assigned a privileged processor mode When an exception occurs program execution is forced from a fixed memory address corresponding to the exception type These fixed addresses are called hard vectors Exception handling is controlled by a vector table The vector table is a reserved 32 byte area at the bottom of the memory map with one word of space allocated to each exception type Because there is not enough space to contain the complete code for an exception handler the vector entry for each exception type typically contains a branch or load PC instruction that passes control to the appropriate handler routine Table 4 1 lists the exception types the corresponding processor modes and the hard vector addresses for each type Table 4 1 Exception Processing Modes and Vectors Exception Type Mode Vector Address Reset 0x00000000 Undefined Instruction 0x00000004 Software Interrupt SWI 0x00000008 Pre fetch Abort 0x0000000c Data Abort 0x00000010 IRQ 0x00000018 FIQ 0x0000001c 4 2 ELECTRONICS S5N8947 EXCEPTION HANDLING ENTERING AN EXCEPTION When an exception is generated the processor executes the following steps Again these operations are performed by the processor not by a user program 1
124. service function First USB sends descriptor s contents in USBDesc h to Host Host checks Product ID and Vendor ID of descriptor and transfers data packet All data transfer are same behavior method and each endpoint is assigned only transmitter or receiver But endpointO can transmit and receive Endpoint1 of S5N8947 s USB is BulkOut endpoints that can receive host s data Endpoint2 4 of S5N8947 s USB is Bulkln endpoints that can send data to host Host Application program contains Test Device Driver and DOS Application program To test the USB controller plug in the USB cable to the host and install Test Device Driver Bulkusb sys Bulkusb inf If USB device is installed well execute Dos application program Bulk34 w byte length byte length c loop count gt endpoint 3 4 loopback test 11112 w byte length r byte length c loop count gt endpoint 1 2 loopback test 5 52 ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES USB INITIALIZE 1 Initialize USB registers 2 Register USB interrupt service routine and enable interrupt Set EPO 1 3 LDS Limit Data Size and SA Start Address Register Register USB Interrupt Service Routine Enable KS8947 USB Interrupt USB linitalize End Figure 5 21 Concept Diagram for USB initialization ELECTRONICS 5 53 CONTROLLING S5N8947 MODULES S5N8947 USB INTERRUPT HANDLER 1 1 Read USB Interrupt Register and Clear it
125. ses the S5N8947 It can evaluate the basic operations of the S5N8947 and develop codes for it as well When the S5N8947 is contained in the 55 8947 Board you can use an in circuit emulator ICE This allows you to test and debug a system design at the processor level In addition the S5N8947 with embeddedICETM capability can be debugged directly using the EmbeddedICE Interface The S5N8947 function blocks are shown in Figure 1 1 ELECTRONICS 1 1 ABOUT S5N8947 EVALUATION BOARD Mode 1 1 SAR 1 MII 1 USB ARM7TDMI ICE 32bit RISC CPU Breaker 32 bit System Bus lt gt eee lt gt Memory Controller with Refresh Control 4 word Write Buffer Bus Router n Connection Memory 18 General Ports lt gt Interrupt Controller lt lt lt SAR UTOPIA 32bit Timer 0 1 2 b lt j Ethernet MAC Watchdog Timer 4 GDMA 0 1 lt gt USB Interface SPI Controller lt gt PLL USB UART gt PLL System Controller 4p TAP Controller for JTAG Figure 1 1 S5N8947 Block Diagram MODE1 1 2 S5N8947 External Device External lt Bus Master PCMCIA Up ELECTRONICS S5N8947 ABOUT S5N8947 EVALUATION BOARD Mode 2 1 SAR 2 1 USB ARM7TDMI ICE 32bit RISC CPU Breaker 32 bit System Bus Memory Controller d with Refresh Control Ext M Unified xema CACHE Device 4 word Write lt gt External Buffer System Bus B
126. t 0 State lt Transmitter Receiver USB Interrupt Handler Routine End Figure 5 23 Concept Diagram for USB Control Transfer ELECTRONICS 5 57 CONTROLLING S5N8947 MODULES 55 8947 DIAGNOSTIC CODE USB CONTROL TRANSFER ENDPOINT 0 Structure for Device Request Type USB Standard 5 1 1 static struct DEVICE_REQUEST UCHAR bmRequestType Device Request offset 0 UCHAR bRequest Device Request offset 1 UCHAR wValue_L Device Request offset 2 UCHAR wValue_H Device Request offset 3 UCHAR wIndex L Device Request offset 4 UCHAR wIndex H Device Request offset 5 UCHAR wLength L Device Request offset 6 UCHAR wLength H Device Request offset 7 DeviceRequest P endpointZeroFunction This is function for Control Transfer If it occurs endpointO interrupt this function is called This function check Device Request for Control Transfer type and call each other functions void endpointZeroFunction void int 1 ReadUsbRegister USB_EOSC_REGISTER EOSC_value EPO CSR register status check if EOSC_value amp 0 00400000 Print Sent Stall n Set sent stall ClearUsbRegister USB EOSC REGISTER 0x0040000
127. t Source void ExternallnterruptTest void IOPMOD amp Oxff01f set port5 11 into input ports IOPCONO 0 initialize IOPCONO register 1 0 initialize IOPCON1 register mapping the ISRs SysSetInterrupt nEXTO INT isr XIrq 0 SysSetInterrupt nEXT1 INT isr XIrq 1 Enables interrupts Enable Intr nEXTO INT Enable Intr 1 INT SetXIrqIOPCON Print n n gt gt xIRQn Enabled ESC To EXIT Nn To EXIT test while 1 if getch ESC break Disable Intr nEXTO INI Disable Intr nEXTl INI M SetXIrqIOPCON Set IOPCON register for xINTREQO xINTREQ6 IOPort 5 11 void SetXIrqIOPCON void ControlXIrq IOPORT 8 ACTIVE LOW FILTERING ON BOTH EDGE ControlXIrq IOPORT 9 ACTIVE LOW FILTERING ON FALLING EDGE 5 38 S5N8947 ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES ControlXIrq Set each IO Port as given parameters Af PortNum IO Port number Active active low high Filtering filtering on off Detect level rising edge falling edge both edge detection void ControlXIrq UINT PortNum UINT Active UINT Filtering UINT Detect unsigned int con
128. terrupt source and perform user interrupt service routine for each source i User receive operation Figure 5 29 SAR Interrupt Service Routine ELECTRONICS 5 81 CONTROLLING S5N8947 MODULES S5N8947 DIAGNOSTIC CODE RECEIVE PACKET IN THE INTERRUPT SERVICE ROUTINE 4 isr sar done SAR Done Interrupt service routine d void isr sar done void volatile ULONG ReadSARstatus 0 ULONG TxDoneQ TxIntCnt 0 RxIntCnt0 20 RxIntCnt1 0 ULONG TxDoneAddrValue PoolPat ULONG RxDoneOAddrValue RxDonelAddrValue RxDonePkt RxPoolArea while 1 Checkd SAR Interrupt source ReadSARstatus nSAR DONEINTSTATUS if ReadSARstatus 0 break Cnt SARintrDonett Clear SAR Interrupt Status register nSAR_DONEINTSTATUS ReadSARstatus Tx Done Interrupt if ReadSARstatus amp INTSTAT_TXDON a SARTXDONEOK SarTxOKFlagCheck 1 if DebugFlag_SAR_ISR YES Print n SARisr Interrupt Tx Done fendif Clear SAR address valid bit to release buffer descriptor TxDoneAddrValue ULONG nSAR_TXDONEADDR CntSARTxDoneintr TxDoneAddrValue amp SAR_ADRVALID Cnt SARTxDoneintrt if CntSARTxDoneintr DFLT TXDONEQ SIZE CntSARTxDoneintr 0 Rx Done Queue Interrupt if ReadSARstatus amp INTSTAT_RXDONEQO CntSARRxDoneQue0_intrt E if DebugFlag_SAR_ISR
129. the ARM SDT please refer to the Software Development Toolkit User s Guide ELECTRONICS 2 1 USING THE ARM SDT FOR S5N8947 PROJECTS S5N8947 55 8947 DEVELOPMENT ENVIRONMENT We recommend the following hardware environment for 55 8947 application development and debugging e Host computer An IBM compatible PC running Windows 95 98 or Windows NT 4 0 2000 with two serial ports and one parallel port One serial port is used to interface with Embedded ICE The other serial port can be used for UART communication if required e Evaluation board The type of board used depends on the target system e EmbeddedICE To support the debugging interface using the 55 8947 JTAG controller CM47 M66 V1 0 ROM Embedded ICE Interface PANGSA Embedded ICE Macrocell RAM Peripheral Figure 2 1 55 8947 Development Environment 2 2 ELECTRONICS S5N8947 USING THE ARM SDT FOR S5N8947 PROJECTS BUILDING A DEMO PROJECT WINDOWS 95 98 OR NT 2000 To build a 55 8947 demo project you must perform the following operations using the Project Manager Sample source files for a typical demo project can be found on the S5N8947 demo diskette Creating a New Project 1 Select New from the File menu 2 Choose Project from the New Dialog box 3 Choose ARM Executable Image as the project type from the list of project templates 4 Enter the Project Name and Project Directory The project filename extension apj is added automati
130. ts and Serial Line Speed to the proper values for your system environment 3 Select the Debugger page and set the Endian value to Big 4 Click OK If you are using Remote A the image file is downloaded to the DRAM ELECTRONICS 2 11 USING THE ARM SDT FOR 55 8947 PROJECTS S5N8947 EXECUTING THE IMAGE FILE 1 Initialize system variables After a download several windows are displayed such as the Execution window Console window and the Command window In the Command window you must initialize the system variables semihosting_enabled and vector_catch by entering the following commands let vector_catch 0x00 let semihosting_enabled 0x00 Or you can initialize these variables in the following way First create a text file called armsd ini that includes the above commands Then enter the following command in the command window ob c arm251 armsd ini For more information about this step please refer to chapter 6 of the ARM Software Development Toolkit User Guide Execute the program To do this select Go from Execute menu or click the Go button When you do this program execution starts When you execute the image the program is displayed in the Execution window as source The program halts at any breakpoints or watchpoints you have applied STEPPING THROUGH THE PROGRAM To step through the program execution flow you can select from the following three options Step Advances the program to the ne
131. ts as inputs or outputs with configuring the IOPMOD register In this menu function Port 0 17 set as input ELECTRONICS 5 41 CONTROLLING S5N8947 MODULES S5N8947 ETHERNET CONTROLLER MAC DIAGNOSTIC CODE FUNCTION The diagnostic source code for the MAC Medium Access Controller is composed of four files MAC H MAC C MACINIT C and MACLIB C e MACH Definition file for MAC diagnostic code Register bit value frame structure frame descriptor structure and function prototype e MAC C The main diagnostic code function call for MAC function test e MACINIT C Initialize and BDMA controller for normal operating environment PHY configuration and each interrupt service routine e The library functions for diagnostic code 5 42 ELECTRONICS S5N8947 CONTROLLING S5N8947 MODULES LAN INITIALIZE The Ethernet controller initialize function is composed of configure PHY device and initialize MAC BDMA controller The configuration of PHY device is performed by MII station management function This function is provided by MAC controller special function The configuration method of PHY device is something different between each vendor in this diagnostic code use only simple code for configure PHY and Full Half duplex mode The S5N8947 has MAC and BDMA controller for Ethernet interface The BDMA is used for transfer receive data to memory and transfer the transmit data to MAC The MAC can support 10
132. us Arbiter Master Connection Memory 5 General I O Ports b Interrupt Controller lt lt lt SAR UTOPIA 32bit Timer 0 1 2 lt gt Ethernet Watchdog Timer 4 GDMA 0 1 lt lt USB Interface SPI Controller I 3 GPIO Pins PLL USB UART Internal Clock Only lt gt PLL System Controller P Controller for JTAG Figure 1 2 S5N8947 Block Diagram MODE2 ELECTRONICS 1 3 ABOUT S5N8947 EVALUATION BOARD FEATURES 1 4 S5N8947 16 32 bit RISC microcontroller Boot ROM 512K bit 1M bit 4M bit support byte half word word size boot ROM Flash 8M bit support byte half word word size DRAM 72 pin SIMM module with two banks and EDO DRAM support SDRAM Two 4 16 with 2banks SDRAM support General I O Control switches and status display LED PCMCIA interface 10 100Mbp Expansion Ethernet interface One UART serial port 2 EEPROM SPI Interface Full rate USB controller ATM SAR block and UTOPIA interface 10 100Mbps Ethernet interface with two external PHYs EmbeddedICE M Interface S5N8947 ELECTRONICS S5N8947 ABOUT S5N8947 EVALUATION BOARD CIRCUIT DESCRIPTION S5N8947 Board consists of logic components several control status display block and a debug interface block S5N8947 Board s detailed block diagram and its components are shown in Figure 1 3 5538947 Board schematics are inserted at the end of this programmer s
133. xt line of code that is displayed in the Execution window Step Into Advances the program to the next line of code that follows all function calls If the code is ina called function the function source is displayed in the Execution window and the current code line is highlighted Step Out Advances the program from the current function to the point from which it was called immediately after the function call The appropriate line of code is displayed in the Execution window ELECTRONICS S5N8947 USING THE ARM SDT FOR S5N8947 PROJECTS SETTING A BREAKPOINT A breakpoint is a point you set in program code where the ARM debugger will halt program execution When you set a breakpoint it appears as a red marker in the left side of the window To set a simple breakpoint on a line of code follow these steps 1 Double click on the line where you want to place the break or choose Toggle Breakpoint from the Execute menu The Set or Edit Breakpoint dialog box appears 2 Set the count to the required value or expression as required The program only halts when this expression is true To set a breakpoint on a line of code within a particular program function Display a list of function names by selecting Function Names from the View menu 2 Double click on the Function Name you wish to open A new source window is displayed containing the function source 3 Double click on the line where the breakpoint is to be placed or choose Toggl
134. y the customer s technical experts Samsung products are not designed intended or authorized for use as components in systems intended for surgical implant into the body for other applications intended to support or sustain life or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application the Buyer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages expenses and reasonable attorney fees arising out of either directly or indirectly any claim of personal injury or death that may be associated with such unintended or unauthorized use even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electric or mechanical by photocopying recording or otherwise without the prior written consent of Samsung Electronics Samsung Electronics microcontroller business has been awarded full ISO 14001 certification BSI Certificate No FM24653 All semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives Samsung Elect
135. ze Open Channel Configure connection tables as channel Tx Rx Operation il Figure 5 26 SAR Initialization Allocation memory opening channel and Tx Rx operation will be described later in this chapter ELECTRONICS 5 65 CONTROLLING S5N8947 MODULES S5N8947 SETUP SAR QUEUES There are three types of queue in the 55 8947 SAR e Tx Done Queue has the addresses of Tx buffer descriptors that have been transmitted e Done Queue has the addresses of Rx buffer descriptors that have been received e Rx Pool Queue has the addresses of Rx buffer pools Transmit Done Queue The S5N8947 SAR writes the addresses of Tx buffer descriptors that have been transmitted in this queue At the same time the SAR requests Tx Done interrupt SAR driver reads this address in the SAR Done interrupt service routine Detailed operation of interrupt service routine will be described later in this chapter entry size of this queue is one of following values 256 1024 4096 16384 The TX DONE SIZE register has this size value The TX DONE ADDR register has the base address of this queue Receive Done Queue The S5N8947 supports two receive done queues and writes the addresses of Rx buffer descriptors that have been received in these queues The Rx done queue 0 and queue 1 indicates address of the received buffer descriptor through receive pool 0 and pool 1 respectively At the same time the SAR requests Rx Done interrupt if

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