User Manual ETE/ETX Module MSC ETE-A945GSE-1
Contents
1. 20 55 MSC ETE A945GSE 1 PRELIMINARY User Manual Signal Description UO Note VCC Power Supply 5VDC 5 jexternal supply GND Power Ground external supply N C Not connected n a Signal Description of IDE signals UO Note PIDE DO 15 Primary IDE Databus UO D7 Internal PD11k5 PIDE_AO 2 Primary IDE Addressbus O PIDE CS1 Primary IDE chip select channel O PIDE CS3 Primary IDE chip select channel O PIDE DRQ Primary IDE dma request Internal PD 11k5 PIDED_AK Primary IDE dma acknowledge O PIDE_RDY Primary IDE ready PU 4k7 3 3V PIDE_IOR Primary IDE IO read O PIDE IOW amp Primary IDE IO write O PIDE INTRO Primary IDE interrupt request IPU8BkK23 3V CBLID_P Cable ID primary PD 10k SIDE DO 15 Secondary IDE Databus UO Di Internal PD31k6 SIDE AO 2 Secondary IDE Addressbus O SIDE_CS1 Secondary IDE chip select O channel SIDE_CS3 Secondary IDE chip select O channel1 SIDE_DRQ Secondary IDE dma request PD 4k7 SIDED AK amp Secondary IDE dma acknowledge O SIDE RDY Secondary IDE ready PU 4k7 3 3V SIDE_IOR Secondary IDE IO read O SIDE_lIOW Secondary IDE IO write O SIDE_INTRQ Secondary IDE interrupt request PD 8k2 DASP_S SATA LED OC Function requires ext PU to 3V3 Do not pull down2. The integrated 32 bit 3D Intel Graphics Media Accelerator 950 supports a dual channel LVDS graphic interface On board features include a 10 100Base T RTL8103T Ethernet controller two EIDE ports audio parallel floppy serial keyboard and mouse interfaces six USB2 0 ports and two SATA ports 4 55 MSC ETE A945GSE 1 PRELIMINARY User Manual 2 Technical Description 2 1 Specifications Core CPU Intel Atom Processor N270 1 60GHz 533 MHz FCBGAS soldered ChipSet Mobile Intel 945GSE Intel 82801GBM ICH7 M L2 Cache 512KB 1 60GHz 533 MHz Memory 200 Pin SO DIMM socket for DDR2 max 2GByte ISA Bus Interface PCI Bus Interface Video Ethernet Audio USB EIDE Floppy Disk SATA Serial COM1 COM2 Parallel PCI to ISA Bridge ITE8888 ETX connector X2 Intel 82801 ICH7 ETX connector X1 Intel Gen 3 5 Integrated Graphics Engine CRT Interface Optional Flat Panel Interface LVDS 18bit single dual channel Chrontel CH7308 SDVO to LVDS converter LVDS 24bit single dual channel LAN controller RTL8103T 10 100Base T HDA decoder VT1708s integrated in Intel 82801GBM ICH7 M 6 USB 1 1 2 0 ports integrated in Intel 82801GBM ICH7 M 1 Port for up to 2 devices Ultra ATA 66 100 JMICRON JMB368 PCle to PATA controller 1 Port for up to 2 devices Ultra ATA 66 100 integrated in W83627 SIO pins shared with parallel port integrated in Intel 82801GBM ICH7 M 2 Port
3. PDIAG_S Secondary IDE Master Slave negotiation HDRST HardDrive reset O 3 3V signal level Signal Description of Ethernet signals I O Note TXD TXD Ethernet Twisted Pair transmit O signal pair RXD RXD Ethernet Twisted Pair receive signal pair ACTLED Ethernet activity LED O 3 3V 10mA sink LILED Ethernet link LED O 3 3V 10mA sink SPEEDLED Ethernet speed LED ON at O 3 3V 10mA sink 100Mb s 21 55 4 6 Connector X5 FAN Pin Signal 1 GND 2 PWM controlled VCC 5V 3 Fan speed Connector JST S3B ZR SM4A TF 4 7 SATA Connectors MSC ETE A945GSE 1 PRELIMINARY User Manual Signal Description of Misc signals UO Note SPEAKER Speaker output O Internal PD 20k 3 3V signal level BATT Battery supply 3 3V 3 6V max PWGIN Power good input PU 10k 3 3V PCLK DC Bus Clock UO PU 2k2 3 3V IDAT DC Bus Data UO IPU 2k2 3 3V SMBCLK SM Bus Clock UO IPU 6k8 DV SMBDAT SM Bus Data UO IPU 6k8 DV SMBALRT GM Bus Alert PU 10k 3 3V_SUS KBINH Keyboard inhibit PU 10k 5V 5V_SB Supply of internal suspend circuit PS ON Power Save ON O PU4k75V SB PWRBTN Power Button Internal PU 20k 3 3V_SUS OVCR Over current detect for USB PU 8k2 3 3V_SUS ROMKBCS n c n a EXT_PRG n C n a GPCS n c n a GPE1 n c n a GPE2 Ring Input PU 10k 3 3V_SUS BATLOW Batterie
4. 5 5 3 Memory Detection Postcodes Code Calistoga Memory Detection FFAOh Start memory detection FFOth Enable MCHBAR FFO2h Check for DRAM initialisation interrupt and reset fail FFO3h Verify all DIMMs are DDR2 and unbuffered FFO4h Detect an improper warm reset and handle FFO5h Detect if ECC SO DIMMs are present in the system FFO6h Verify all DIMMs are single or double sided and not asymmetric FFO7h Verify all DIMMs are x8 or x16 width FFO8h Find a common CAS latency between the DIMMS and the MCH FFO9h Determine the memory frequency and CAS latency to program FF10h Determine the smallest common TRAS for all DIMMs FF11h Determine the smallest common TRP for all DIMMs FF12h Determine the smallest common TRCD for all DIMMs FF13h Determine the smallest refresh period for all DIMMs FF14h Verify burst length of 8 is supported by all DIMMs FF15h Determine the smallest tWR supported by all DIMMs FF16h Determine DIMM size parameters FF17h Program Graphics frequency and PLL settings FF18h Program system memory frequency FF19h Determine and set the mode of operation for the memory channels FF20h Program clock crossing registers FF21h Disable Fast Dispatch FF22h Program the DRAM Row Attributes and DRAM Row Boundary registers FF23h Program the DRAM Bank Architecture register FF24h Program the DRAM Timing amp and DRAM Control registers FF25h Program O
5. User Manual 5 5 2 System Bios Postcodes Code Beeps POST Task Description 04h Get CPU type 03h Disable Non Maskable Interrupt NMI 06h Initialize system hardware 07h Disable shadow and execute code from the ROM 08h Initialize chipset with initial POST values 09h Set IN POST flag OAh Initialize CPU registers OBh Enable CPU cache OCh Initialize caches to initial POST values OEh Initialize I O component OFh Initialize fixed disk drives 10h Initialize Power Management 11h Load alternate registers with initial POST values 12h Restore CPU control word during warm boot 13h Initialize PCI Bus Mastering devices 14h Initialize keyboard controller 16h 1 2 2 3 BIOS ROM checksum 17h Initialize cache before memory Autosize 18h 8254 timer initialization 1Ah 8237 DMA controller initialization 1Ch Reset Programmable Interrupt Controller 20h 1 3 1 1 Test DRAM refresh 22h 1 3 1 3 Test 8742 Keyboard Controller 24h Set ES segment register to 4 GB 28h Autosize DRAM 29h Initialize POST Memory Manager 2Ah Clear 512 kB Base RAM 2Ch 1 3 4 1 RAM Address test 2Eh 1 3 4 3 Base RAM Test 2Fh Enable cache before system BIOS shadow 32h Compute CPU clock speed in MHz 33h Initialize Phoenix Dispatch Manager 36h Warm start shut down 38h Shadow system BIOS ROM 3Ah Autosize cache 3Ch Advanced configuration of chipset re
6. 60 ERR HDSEL 11 LCDDO16 12 LCDDO18 61 IRTX 62 PD6 RES 13 LCDDO17 14 LCDDO19 63 RXD2 64 INIT DIR 15 GND 16 GND 65 GND 66 GND 17 LCDDO13 18 LCDDO15 67 RTS2 68 PD5 RES 19 LCDDO12 20 LCDDO14 69 DTR2 70 SLIN STEP 21 GND 22 GND 71 DCD2 72 PD4 DSKCHG 23 LCDDO8 24 LCDDO11 73 DSR2 74 PD3 RDATA 25 LCDDO9 26 LCDDO10 75 CTS2 76 PD2 WP 27 GND 28 GND 77 TXD2 78 PD1 TRKO 29 LCDDO4 30 LCDDO7 79 RI2 80 PDO INDEX 31 LCDDO5 32 LCDDO6 81 VCC 82 VCC 33 GND 34 GND 83 RXD1 84 ACK DRV1 35 LCDDO1 36 LCDDO3 85 RTS1 86 BUSY MOT1 37 LCDDOO 38 LCDDO2 87 DTR1 88 PE WDATA 39 VCC 40 VCC 89 DCD1 90 SLCT WGATE 41 JILI DAT 42 LTGIOO 91 DSR1 92 MSCLK 43 JILI_CLK 44 BLON 93 CTS1 94 MSDAT 45 BIASON 46 DIGON 95 TXD1 96 KBCLK 47 COMP 48 Y 97 RI1 98 KBDAT 49 SYNC 50 C 99 GND 100 GND 15 55 MSC ETE A945GSE 1 PRELIMINARY User Manual Signal Description UO Note VCC Power Supply 5VDC 5 jexternal supply GND Power Ground external supply N C Not connected n a LTGIOO General Purpose IO O GPIO42 PU 4k7 5V DETECT Not connected n a Signal Description of analog CRT signals UO Note HSYNC Horizontal Sync O 3V3 signal level VSYNC _ Vertical Sync O 3V3 signal level R Red channel RGB Analog Video O Output G Green channel RGB Analog Video O Output B Blue channel RGB An
7. 79 C of the ACPI Passive Trip Point the 87 C 95 C 103 C 111 C point in which the OS will begin 119C throttling the CPU Note If the DTS is enabled only values below 97C are valid 37 55 MSC ETE A945GSE 1 PRELIMINARY User Manual E RR RO Passive TC1 Value This value sets the TC1 2 value for the ACPI Passive Cooling Formula Passive TC2 Value Passive TSP Value This item sets the TSP value for the ACPI Passive Cooling Formula It represents in tenths of a second how often the OS will read the temperature when Passive Cooling is Enabled Critical Trip Point POR This value controls the temperature 47 C 55 C 63 C 71 C 79 C of the ACPI Critical Trip Point the 87 C 95 C 103 C 111 C point in which the OS will shut the 119 C 127 C system off Notes 1 100C is POR for all Intels CPUs 2 If value is gt 100C and DTS is enabled the Out of Spec Bit will be used 3 The EC value will be set to 127 after ACPI initialation 5 2 3 7 Clock Control Sub Menu Feature Options Description CK 505 Clock Chip Program Control Programming of the CK 505 Clock Chip Program TBD PLL1 Spread Spectrum Off Down Spread Center Programming of PLL1 Spread Mode Spread Spectrum Clock Off PLL1 Spektrum is disabled Down Spread 0 5 Center Spread 0 25 PLL3 Spread Spectrum Off Software Programming of PLL3 Spread Spectrum Clock Off PLL1 Spektrum is disabled Software Spread Spectrum i
8. 8k2 5V SMEMR ISA memory read in lowest UO PU 1k0 5V 1MB address range MEMW ISA memory write UO PU 8k2 5V SMEMW amp ISA memory write in lowest UO PU 1k0 5V 1MB address range lOR ISA IO read UO PU 8k2 5V IOW ISA IO write UO PU 8k2 5V IOCHK ISA IO check PU 4k7 DV IOCHRDY ISA IO channel ready UO PU 1k0 5V M16 ISA 16Bit memory device UO PU 1k0 5V 016 ISA 16Bit IO device IPU 1k0 5V REFSH ISA memory refresh cycle UO PU 1k0 5V pending NOWS ISA No waitstates PU 1k0 5V MASTER ISA Master I PU 1k0 5V SYSCLK ISA System clock 8 MHz O OSC ISA Oscillator 14 31818 MHz O RSTDRV ISA Reset signal O DREQO 7 ISA DMA request PD 8k2 DACKO 7 ISA DMA acknowledge UO TC ISA DMA end UO PD 4k7 IRQ3 7 ISA Interrupt request IRQ table see 2 5 PU 8k2 5V IRQ9 12 ISA Interrupt request IRQ table see 2 5 PU 8k2 5V IRQ14 ISA Interrupt request UO IRQ table see 2 5 PU 8k2 5V IRQ15 ISA Interrupt request IRQ table see 2 5 PU 8k2 5V 14 55 MSC ETE A945GSE 1 PRELIMINARY User Manual 4 3 Connector X3 CRT Display TVout Serial Parallel Mouse Keyboard Standard pinout with LVDS and LPT Pin Signal Pin Signal Pin Signal Pin Signal 1 GND 2 GND 51 LPT FLPY 52 RESERVED 3 R 4 B 53 VCC 54 GND 5 HSY 6 G 55 STBHRES 56 AFD DENSEL 7 VSY 8 DDCK 57 RESERVED 58 PD7 RES 9 DETECTA 10 DDDA 59 IRRX
9. State Displays Current TPM Displays the current TPM status State Change TPM State No Change Changes TPM state Enable amp Activate Deactivate amp Disable Clear 41 55 MSC ETE A945GSE 1 PRELIMINARY User Manual 5 2 5 The Power Menu re om O mm After Power Failure Stay Off Sets the mode of operation if an AC power loss Power On occurs Power On will turn the power on as soon as the power supply is back on Stay Off will keep the power off until the power button is pressed Hardware Monitor Configure Hardware Monitor 5 2 5 1 Hardware Monitoring Menu Fees JL Sege CPU Vcore Displays the current CPU voltage Supply voltage 5V Displays the current voltage CPU Temperature Sensor Displays the current CPU temperature Board Temperature Sensor Displays the current board temperature FAN 1 speed Displays the current fan speed 42 55 MSC ETE A945GSE 1 PRELIMINARY User Manual 5 2 6 The Boot Menu After you turn on your computer it will attempt to load the operating system such as DOS Windows XP or Linux from a device listed in the boot priority order If it cannot find the operating system on that device it will attempt to load it from the next device in that list Boot devices i e with access to an operating system can include hard drives floppy drives CD ROMs removable devices e g USB sticks and network cards Note Specifying any device as a boot devic
10. comment C0000h CFFFFh VGA BIOS No 64 KB VGA BIOS D0000h D3FFFh SATA Yes No Shared with SATA OPROM D4000h DFFFFh Yes ISA bus or shadow RAM E0000h E3FFFh USB Buffer No E4000h FFFFFh System BIOS No free when SATA OPROM disabled 2 5 4 SMBus address map Device A6 A5 A4 A3 A2 A1 AO R W address SMBus host O IO O 1 0 1010 D 10 clock synthesizer ICOLPRS365 1 1 0 1 0 1 0 4 1 D D2 watchdog 1 0 1 1 0 1010 D DO HW monitor EMC2104 0 1 0 1 1 1 1 x BE SIO W83627HF default 0 O0 1 0 1 1 40 D 5An SIO W83627HF Temp3 default 1 0 0 1 0 0 4 0 D 90n SIO W83627HF Temp2 default 1 0 1 0 1 01 0 1 D 92 CMOS backup EEPROM 1 1 0 1 0 1 04 0 D A8 CMOS backup EEPROM amp 2 1lLO 1 0 1 0 1 D AA SPD EEPROM SO DIMM 110 1110 0 0 0 D AO 8 bit address with R W 7 bit address without RAW 9 55 MSC ETE A945GSE 1 PRELIMINARY User Manual 3 Mechanical Specification 3 1 Top view X10 X11 10 55 MSC ETE A945GSE 1 PRELIMINARY User Manual 4 ETX Connectors 4 1 Connector X1 PCI USB Audio Pin Signal Pin Signal Pin Signal Pin Signal 1 GND 2 GND 51 VCC 52 VCC 3 PCICLK3 4 PCICLK4 53 PAR 54 SERR 5 GND 6 GND 55 GPERR 56 RESERVED 7 PCICLK1 8 PCICLK2 57 PME 58 USB2 9 REQ3 10 GNT3 59 LOCK 60 DEVSEL 11 GNT2 12 3 3V 61 TRDY 62 USB3 13 REQ2 14 GNT1 63 IRDY 64
11. internal PU 20k 3 3Vsus LOCK PCI bus lock UO PU 8k2 3 3V DEVSEL PCI bus device select UO PU 8k2 3 3V TRDY PCI bus target ready UO PU 8k2 3 3V IRDY PCI bus initiator ready UO PU 8k2 3 3V STOP PCI bus stop UO PU 8k2 3 3V FRAME PCI bus frame UO PU 8k2 3 3V PCIRST PCI bus reset O 3 3V signal level INTA PCI bus interrupt A PU 8k2 3 3V INTB PCI bus interrupt B PU 8k2 3 3V INTC PCI bus interrupt C PU 8k2 3 3V INTD PCI bus interrupt D PU 8k2 3 3V SERIRQ Serial interrupt request UO PU 10k 3 3V Signal Description of USB Signals UO Note USBO USBO USB Port O UO 5V tolerant internal PD 15k USB1 USB1 USB Port 1 UO 15V tolerant internal PD 15k USB2 USB2 USB Port 2 O 5V tolerant internal PD 15k USB3 USB3 USB Port 3 UO 5V tolerant internal PD 15k USB4 USB4 USB Port 4 UO 5V tolerant internal PD 15k USB5 USB5 USB Port 5 UO 5V tolerant internal PD 15k Signal Description of Audio Signals UO Note SNDL Line Level stereo output left O 0 7VRMS SNDR Line Level stereo output right O 0 7VRMS AUXAL Auxiliary input A left AUXAR Auxiliary input A right MIC Microphone input ASGND Analog ground of sound controller ASVCC Analog supply of sound controller O 3 3V 12 55 MSC ETE A945GSE 1 PRELIMINARY User Manual 4 2 Connector X2 ISA Pin Signal Pin Signal Pin Signal Pin Signal 1 GND 2 GND 51 VCC 52 VC
12. low I PU 220k 3 3V_SUS EXTSMI External SMI PU 10k 3 3V_SUS RSMRST Resume Reset 3 3V signal level Pin Signal X7 Pin Signal X8 1 GND 1 GND 2 S1_TX 2 S2 TX 3 GI TX 3 S2 TX 4 GND 4 GND 5 GI RX 5 S2_RX 6 GI RX 6 S2_RX 7 GND 7 GND 22 55 MSC ETE A945GSE 1 PRELIMI NARY User Manual 4 8 Mini USB Connectors Pin Signal X10 Pin Signal X11 1 5V 1 5V 2 USB4 Data 2 USB5 Data 3 USB4 Data 3 USB5 Data 4 USB ID4 4 USB ID5 5 GND 5 GND 4 9 LVDS Connector X9 option Pin Signal 1 LVDS AO 2 LVDS_A0 3 LVDS_A1 4 LVDS_A1 5 LVDS _A2 6 LVDS _A2 7 LVDS_A CLK 8 LVDS A CLK 9 LVDS BO 10 LVDS BO 11 LVDS B1 12 LVDS B1 13 LVDS B2 14 LVDS B2 15 LVDS B CLK 16 LVDS B CLK 17 GND 18 LVDS VDD EN PD 100k 3 3V tolerant 19 LVDS_BKLEN PU 4k7 5V 20 LVDS BKLT CTRL PD 100k 3 3V tolerant Connector Hirose DF14 20P 1 25H 23 55 MSC ETE A945GSE 1 PRELIMINARY User Manual 5 BIOS 5 1 Introduction This guide describes the Phoenix TrustedCore Startup screen and contains information on how to access Phoenix TrustedCore setup to modify the settings which control Phoenix pre OS operating system functions 5 1 1 Startup Screen Overview The Phoenix TrustedCore Startup screen is a graphical user interface GUI
13. 14x 12mm 6 55 MSC ETE A945GSE 1 PRELIMINARY User Manual 2 2 Block diagram CPU MSC ETE A945GSE 1 Intel Atom N270 BGA Power IN 5V 5V Standby VBAT Power 3 30V 2 50V 1 80V 1 50V 1 35V 1 25V 1 05V 0 90V VCCCORE 3 3VSUS 1 5VSUS RT Northbridge PC5300 Intel 945GSE DDR2 LVDS 2x24Bit X3 SDRAM SO ES KR DIMM max 2GByte HW Monitor EMC2104 SPI LP Southbridge PCI PCI Intel ICH7M X1 TPM 1 2 Infineon EE Watch PCI ISA PROM dog ITE8888 LVDS 2x18Bit X9 Clock ICS9LPR3 2x mini USB X10 X11 Super UO Winbond W83627HF PCle to Audio PATA codec JMB368 VT1708s ISA UO PS2 Floppy LPT COM1 2 USB ISA IRDA USB 1 4 x2 X3 X1 Audio SMBus X1 X4 2 3 Installation 2 3 1 Jumpers and switches There are no jumpers or switches 2 3 2 Installing a DDR2 SO DIMM module The ETE A945GSE board has a standard 200 pin SO DIMM socket for 1 8V DDR2 SDRAM SO DIMM modules The chipset supports 256 Mbit 512 Mbit and 1 Gbit technologies providing maximum capacity of 2GB Note Module height should not exceed 1260 mil 32 mm 7 55 MSC ETE A945GSE 1 PRELIMINARY User Manual 2 4 Watchdog The ETE A945GSE board has a watchdog function implemented in a PIC Microcontroller Via SETUP the watchdog can be enabled and configured If the watchdog is enabled a counter is started which creates a reset if it is not retriggered within a program
14. 3 CTS1 94 MSDAT 93 CTS1 94 MSDAT 95 TXD1 96 KBCLK 95 TXD1 96 KBCLK 97 RI1 98 KBDAT 97 RH 98 KBDAT 99 GND 100 GND 99 GND 100 GND 19 55 MSC ETE A945GSE 1 PRELIMINARY User Manual 4 5 Connector X4 EIDE Ethernet Speaker Batterie DC SMBus etc Pin Signal Pin Signal Pin Signal Pin Signal 1 GND 2 GND 51 SIDE OWN 52 PIDE IORH 3 5V_SB 4 PWGIN 53 SIDE_DRQ 54 PIDE_lOW 5 PS_ON 6 SPEAKER 55 SIDE_D15 56 PIDE_DRQ 7 PWRBTN 8 BATT 57 SIDE_DO 58 PIDE_D15 9 KBINH 10 LILED 59 SIDE_D14 60 PIDE_DO 11 RSMRST 12 ACTLED 61 SIDE Di 62 PIDE D14 13 ROMKBCSH 14 SPEEDLED 63 SIDE D13 64 PIDE Di 15 EXT PRG 16 I2CLK 65 GND 66 GND 17 VCC 18 VCC 67 SIDE D2 68 PIDE D13 19 OVCR 20 GPCS 69 SIDE_D12 70 PIDE_D2 21 EXTSMI 22 I2DAT 71 SIDE_D3 72 PIDE D12 23 SMBCLK 24 SMBDATA 73 SIDE_D11 74 PIDE_D3 25 SIDE_CS3 26 SMBALRT 75 SIDE_D4 76 PIDE D11 27 SIDE_CS1 28 DASP S 77 SIDE_D10 78 PIDE D4 29 SIDE A2 30 PIDE CS3H 79 SIDE D5 80 PIDE D10 31 SIDE AO 32 PIDE_CS1 81 VCC 82 VCC 33 GND 34 GND 83 SIDE D9 84 PIDE D5 35 PDIAG S 36 PIDE A2 85 SIDE D6 86 PIDE D9 37 SIDE A 38 PIDE AO 87 SIDE D8 88 PIDE D6 39 SIDE INTRQ 40 PIDE A 89 GPE2 90 CBLID_P 41 BATLOW 42 GPE1 91 RXD 92 PIDE_D8 43 SIDE_AK 44 PIDE INTRQ 93 RXD 94 SIDE D7 45 SIDE RDY 46 PIDE AK amp 95 TXD 96 PIDE_D7 47 SIDE_IOR 48 PIDE RDY 97 TXD 98 HDRST 49 VCC 50 VCC 99 GND 100 GND
15. C 3 SD14 4 SD15 53 SA6 54 IRQ5 5 SD13 6 MASTER 55 SA7 56 IRQ6 7 SD12 8 DREQ7 57 SA8 58 IRQ7 9 SD11 10 DACK7 59 SA9 60 SYSCLK 11 SD10 12 DREQ6 61 SA10 62 REFSH 13 SD9 14 DACK6 63 SA11 64 DREQ1 15 SD8 16 DREQ5 65 SA12 66 DACK1 17 MEMW 18 DACK5 67 GND 68 GND 19 MEMR 20 DREQO 69 SA13 70 DREQ3 21 LA17 22 DACKO 71 SA14 72 DACK3 23 LA18 24 IRQ14 73 SA15 74 lOR 25 LA19 26 IRQ15 75 SA16 76 IOW 27 LA20 28 IRQ12 77 SA18 78 SA17 29 LA21 30 IRQ11 79 SA19 80 SMEMR 31 LA22 32 IRQ10 81 IOCHRDY 82 AEN 33 LA23 34 lO16 83 VCC 84 VCC 35 GND 36 GND 85 SDO 86 SMEMW 37 SBHE 38 M16 87 SD2 88 SD1 39 SAO 40 OSC 89 SD3 90 NOWS 41 SA1 42 BALE 91 DREQ2 92 SD4 43 SA2 44 TC 93 SD5 94 IRQ9 45 SA3 46 DACK2 95 SD6 96 SD7 47 SA4 48 IRQ3 97 lIOCHK 98 RSTDRV 49 SA5 50 IRQ4 99 GND 100 GND 13 55 MSC ETE A945GSE 1 PRELIMINARY User Manual Signal Description UO Note VCC Power Supply 5V 5 external supply GND Power Ground jexternal supply Signal ISA Bus Signals UO Note SDO 15 ISA Databus UO Jall ISA outputs 5V signal level PU 8k2 5V all ISA inputs 5V tolerant SAO 19 ISA Addressbus UO PU 8k2 5V LA17 23 ISA Addressbus UO PU 8k2 5V SBHE ISA Byte High Enable UO internal PU 50k 5V BALE ISA Address Latch Enable UO PD 4k7 AEN ISA Address Enable UO PD 4k7 MEMR ISA memory read UO PU
16. Ch Set up hardware interrupt vectors 7Dh Initialilze Intelligent System Monitoring 7Eh Initialize coprocessor if present 80h Disable onboard Super UO ports and IRQs 81h Late POST device initialisation 82h Detect and install external RS232 ports 83h Configure non MCD IDE controllers 84h Detect and install external parallel ports 85h Initialize PC compatible PnP ISA devices 86h Re initialize onboard I O ports 87h Configure Motheboard Configurable Devices optional 88h Initialize BIOS Data Area 89h Enable Non Maskable Interrupts NMIs 8Ah Initialize Extended BIOS Data Area 50 55 MSC ETE A945GSE 1 PRELIMINARY User Manual Code Beeps POST Task Description 8Bh Test and initialize PS 2 mouse 8Ch Initialize floppy controller 8Fh Determine number of ATA drives optional 90h Initialize hard disk controllers 91h Program timing registers according to PIO modes 92h Jump to UserPatch2 93h Build MPTABLE for multi processor boards 95h Install CD ROM for boot 96h Clear huge ES segment register 97h Fixup Multi Processor table 98h 1 2 Enable PCI devices and ROM Scan One long two short beeps on checksum failure 99h Check for SMART Drive 9Ah Shadow option ROMs 9Ch Set up Power Management 9Dh Initialize security engine optional 9Eh Enable hardware interrupts 9Fh Determine number of ATA and SC
17. DT FF26h Perform steps required before memory init FF27h Program the receive enable reference timing control register Program the DLL Timing Control Registers RCOMP settings FF28h Enable DRAM Channel I O Buffers FF29h Enable all clocks on populated rows FF30h Perform JEDEC memory initialization for all memory rows FF31h Program PM Settings FF32h Perform additional steps required after memory init FF33h Program DRAM throttling and throttling event registers FF34h Setup DRAM control register for normal operation and enable FF35h Setup DRAM control register for normal operation and enable FF36h Enable RCOMP FF37h Clear DRAM initialization bit in the ICH 53 55 MSC ETE A945GSE 1 PRELIMINARY User Manual 5 5 4 ACPI Postcodes Code ACPI Codes 03h Enter Suspend State S3 04h Enter Hibernate State S4 05h Enter Softoff State S5 ABh Enter Wakeup from Powerstate CDh End Wakeup from Powerstate 54 55 MSC ETE A945GSE 1 PRELIMINARY User Manual 6 Troubleshooting For additional help contact MSC Technical Support Phone 49 8165 906 200 Fax 49 8165 906 201 Email support msc technologies eu 55 55
18. INARY User Manual rm om rem DVMT Graphics Memory IN A Displays the Memory size of the Video device Onboard EDID EEPROM Disabled Enabled Enables or disables the Onboard GSE EEPROM for EDID Onboard EDID EEPROM Disabled Enabled Enables or disables the Onboard Chrontel EEPROM for EDID Chrontel 5 2 3 5 ICH Control Sub Menu C re IL zs JL Femme PCI Control Submenu Configure PCI Control ICH USB Contol Submenu Configure ICH USB Control AC97A Device 30 Disabled Auto Control Detection of the AC97 Audio Function 2 Device Disabled AC97 Audio will be unconditionally disabled regardless of presence Auto AC97 Audio will be enabled if present disabled otherwise AC97M Device 30 Disabled Auto Control Detection of the AC97 Modem Function 3 Device Disabled AC97 Modem will be unconditionally disabled regardless of presence Auto AC97 Modem will be enabled if present disabled otherwise AC97 Modem PNE Enable Disabled Enabled Control the ability to wake the System from an AC97 Modem Device SATA Device 31 Compatible Enhanced Compatible Function 2 SATA Drive Primary on SATA Controller in Legacy Mode PATA Drive Secondary on SATA Controller in Legacy Mode Enhanced SATA Drive Primary on SATA Controller in Native Mode PATA Drive Primary on PATA Controller in Legacy Mode AHCI Configuration Disabled Enabled Enhanced AHCI WinXP SP1 IAA driver supports AHCI
19. Intelligent Solutions Engineering Leadership User Manual ETE ETX Module MSC ETE A945GSE 1 Intel Atom N270 Rev 0 2 2014 09 19 MSC ETE A945GSE 1 PRELIMINARY User Manual Preface Copyright Notice Copyright O 2014 MSC Technologies GmbH All rights reserved Copying of this document and giving it to others and the use or communication of the contents thereof is forbidden without express authority Offenders are liable to the payment of damages All rights are reserved in the event of the grant of a patent or the registration of a utility model or design Important Information This documentation is intended for qualified audience only The product described herein is not an end user product It was developed and manufactured for further processing by trained personnel Disclaimer Although this document has been generated with the utmost care no warranty or liability for correctness or suitability for any particular purpose is implied The information in this document is provided as is and is subject to change without notice EMC Rules This unit has to be installed in a shielded housing If not installed in a properly shielded enclosure and used in accordance with the instruction manual this product may cause radio interference in which case the user may be required to take adequate measures at his or her owns expense Trademarks All used product names logos or trademarks are property of the
20. LVDS U 1 O LCDDO14 LVDS U 2 O LCDDO15 LVDS _U 2 O LCDDO16 LVDS _U CLK O LCDDO17 LVDS_U CLK O LCDDO18 LVDS_U3 O E LCDDO19 LVDS U3 O JILL DAT JILI DATA UO PU 4k7 3 3V JILI CLK JILI CLOCK UO PU 4k7 3 3V n a 18 55 MSC ETE A945GSE 1 PRELIMINARY User Manual 4 4 Connector X3 alternate pinout LPT Floppy LPT FLPY high LPT FLPY low Pin Signal Pin Signal Pin Signal Pin Signal 51 LPT FLPY 52 RESERVED 51 LPT FLPY 52 RESERVED 53 VCC 54 GND 53 VCC 54 GND 55 STB 56 AFD 55 RESERVED 56 DENSEL 57 RESERVED 58 PD7 57 RESERVED 58 RESERVED 59 IRRX 60 ERR 59 IRRX 60 HDSEL 61 IRTX 62 PD6 61 IRTX 62 RESERVED 63 RXD2 64 INT 63 RXD2 64 DIR 65 GND 66 GND 65 GND 66 GND 67 RTS2 68 PD5 67 RTS2 68 RESERVED 69 DTR2 70 SLIN 69 DTR2 70 STEP 71 DCD2 72 PD4 71 DCD2 72 DSKCHG 73 DSR2 74 PD3 73 DSR2 74 RDATA 75 CTS2 76 PD2 75 CTS2 76 WP 77 TXD2 78 PD1 77 TXD2 78 TRKO 79 RI2 80 PDO 79 RI2 80 INDEX 81 VCC 82 VCC 81 VCC 82 VCC 83 RXD1 84 ACK 83 RXD1 84 DRV 85 RTS1 86 BUSY 85 RTS1 86 MOT 87 DTR1 88 PE 87 DTR1 88 WDATA 89 DCD1 90 SLCT 89 DCD1 90 WGATE 91 DSR1 92 MSCLK 91 DSR1 92 MSCLK 9
21. OS To start the Phoenix TrustedCore Setup utility press F2 to launch Setup The Setup main menu appears The BIOS Menu Structure The BIOS Menu is structured in the following way Board Information IDE Channel 0 Master IDE Channel 0 Slave SATA Port 0 SATA Port 1 Boot Options Cache Memory CPU Control Sub Menu MCH Control Sub menu Video Intel IGD Control Sub menu ICH Control Sub menu PCI Control Sub menu ICH USB Control Sub menu ACPI Control Sub menu Clock Control Sub menu I O Device Configuration Watchdog Options Hardware Monitor 25 55 MSC ETE A945GSE 1 PRELIMINARY User Manual The Menu Bar The Menu Bar at the top of the window lists these selections D n o eee Use this menu for basic system configuration Advanced Use this menu to set the Advanced Features available on your system s chipset Security Use this menu to set User and Supervisor Passwords and the Backup and Virus Check reminders Exit Exits the current menu Use this menu to configure Power Management features Boot Use this menu to set the boot order in which the BIOS attempts to boot to OS Use the left and right arrow keys on your keyboard to make a menu selection The Legend Bar Use the keys listed in the legend bar on the bottom of the screen to make your selections or to exit the current menu The following table describes the legend keys and the
22. Pauses and displays Setup Entry or resume boot prompt if error occurs on boot If disabled system always attempts to boot Extended Memory Testing Normal Just zero it None Determines which type of test will be performed on extended memory during POST above 1 MB 30 55 MSC ETE A945GSE 1 PRELIMINARY User Manual 5 2 3 The Advanced Menu E oe lee Installed O S Reset configuration Data Large Disk Access Mode Small Disk Access Mode Port 80 Cycles Local Bus IDE adapter Secondary PATA OPROM Cache Memory CPU Control Sub Menu MCH Control Sub Menu Video Intel IGD Control Sub Menu ICH Control Sub Menu ACPI Control Sub Menu Clock Control Sub Menu I O Device Configuration Other DOS LPC Bus PCI Bus Disabled Enabled Disabled Enabled Submenu Submenu Submenu Submenu Submenu Submenu Submenu Submenu 31 55 Select the operating system installed on your system which you will use most commonly NOTE An incorrect setting can cause some operating systems to display unexpected behavior Select Yes if you want to clear the Extended System Configuration Data ESCD area Select Other for UNIX Novell NetWare Select DOS for all other operating systems Select if CHS translation should be made for a LBA capable harddisk with less than 1024 cylinders e g CompactFlash R If you have problems with booting from a CompactFlash R try to change this settin
23. SI drives AOh Set time of day A2h Check key lock A4h Initialize typematic rate A8h Erase F2 prompt AAh Scan for F2 key stroke ACh Enter SETUP AEh Clear Boot flag B0h Check for errors Bih Inform RomPilot about the end of POST B2h POST done prepare to boot operating system B3h store enhanced CMOS values in non volatile area B4h 1 One short beep before boot B5h Terminate QuietBoot optional B6h Check password optional B7h Initialize ACPI BIOS B9h Prepare Boot BAh Initialize DMI parameters BCh Clear parity checkers BDh Display MultiBoot menu BEh Clear screen optional BFh Check virus and backup reminders Coh Try to boot with INT 19 Cih Initialize POST PEM Error Manager C2h Initialize PEM error logging C3h Initialize error PEM display function C4h Initialize PEM system error handler 51 55 MSC ETE A945GSE 1 PRELIMINARY User Manual Code Beeps POST Task Description C5h PnPnd dual CMOS optional C6h Initialize note dock optional C7h Initialize note dock late C8h Force check optional C9h Extended checksum optional CAh Redirect Int 15h to enable remote keyboard CBh Redirect Int 13h to Memory Technologies CCh Redirect Int 10h to enable remote serial video CDh Remap I O and memory for PCMCIA CEh Initialize digitizer and display message D2h Unknown interrupt or exception 52 55 MSC ETE A945GSE 1 PRELIMINARY User Manual
24. STOP 15 REQ1 16 3 3V 65 FRAME 66 USB2 17 GNTO 18 RESERVED 67 GND 68 GND 19 VCC 20 VCC 69 AD16 70 CBE2 21 SERIRQ 22 REQO 71 AD17 72 USB3 23 ADO 24 3 3V 73 AD19 74 AD18 25 AD1 26 AD2 75 AD20 76 USBO 27 AD4 28 AD3 77 AD22 78 AD21 29 AD6 30 AD5 79 AD23 80 USB1 31 CBEO 32 AD7 81 AD24 82 CBE3 33 AD8 34 AD9 83 VCC 84 VCC 35 GND 36 GND 85 AD25 86 AD26 37 AD10 38 AUXAL 87 AD28 88 USBO 39 AD11 40 MIC 89 AD27 90 AD29 41 AD12 42 AUXAR 91 AD30 92 USB1 43 AD13 44 ASVCC 93 PCIRST 94 AD31 45 AD14 46 SNDL 95 INTC 96 INTD 47 AD15 48 ASGND 97 INTA 98 INTB 49 CBE1 50 SNDR 99 GND 100 GND 11 55 MSC ETE A945GSE 1 PRELIMINARY User Manual Signal Description UO Note VCC Power Supply 5V 5 jexternal supply GND Power Ground external supply 3V Power Supply 3 3V O Do not use externally RESERVED Not connected n a Do not connect Signal Description of PCI Bus Signals UO Note PCI outputs 3 3V signal level PCI inputs 5V tolerant PCICLK1 4 PCI clock output O REQO 3 PCI bus request IPU8BkK23 3V GNT0 3 PCI bus grant O ADO 31 PCI Adress Databus UO CBEO 3 PCI bus command byte enables UO PAR PCI bus parity UO SERR PCI bus system error UO PU 8k2 3 3V GPERR PCI bus grant parity error UO PU 8k2 3 3V PME PCI bus power management event UO
25. alog Video O Output DDCK Display Data Channel Clock UO PU 2k2 5V DDDA Display Data Channel Data UO PU 2k2 5V Signal Description of TV signals option UO Note SYNC n c n a Y n C n a C n c n a COMP n C n a Signal Description of COMx signals UO Note All TTL signal level DTR1 2 Data terminal ready of COM1 COM2 O HI 28 Ring indicator of COM1 COM2 PU 470k 5V TXD1 2 Data transmit of COM1 COM2 O RXD1 2 Data receive of COM1 COM2 PU 470k 5V CTS1 2 Clear to send of COM1 COM2 PU 470k 5V RTS1 2 Request to send of COM1 COM2 O DCD1 2 Data carrier detect of COM1 COM2 PU 470k 5V DSR1 2 Data set ready of COM1 COM2 PU 470k 5V Signal Description of keyboard and UO Note infrared signals KBDAT Keyboard Data UO PU 8k2 5V KBCLK Keyboard Clock O PU 8k2 5V MSDAT Mouse Data UO PU 8k2 5V MSCLK Mouse Clock O IPU 8k2 5V IRTX Infrared Transmit O IRRX Infrared Receive 16 55 MSC ETE A945GSE 1 PRELIMINARY User Manual Signal Description of FDC signals UO Note shared with LPT LPT FLPY LPT or Floppy Interface Connect to GND PU 10k 5V configuration input STB RES ne S AFD DENSEL density select O low 250 300Kb s high 500 1000Kb s PDO INDEX Index signal PD1 TRKO Track signal PD2 WP Write protect signal PD3 RDATA Raw data
26. ced C States disabled Enabled Enhanced C State enable Timestamp Counter Disabled Enabled Control TSC updates after C3 C4 Updates through this Setup Option 32 55 MSC ETE A945GSE 1 PRELIMINARY User Manual RD RR RR Thermal Control Circuit Disabled Setting this bit enables the thermal control circuit TCC portion of the Thermal Monitor feature of the CPU TM1 50 duty Cycle TM2 Geyserville III TM1 and TM2 DTS Enable Disabled Enabled Enabled the Atom DTS to be used for platform Thermal Management Note If DTS is disabled thermal throttling in ACPI will not work No Execute Mode Mem Enabled Disabled Protection Set Max Ext CPUID 3 Disabled Enabled Sets Max CPUID extended function value to 3 5 2 3 3 MCH Control Sub Menu Feature Options Description MDA Support Disabled Enabled Control MDA support for the PEG Device Memory Throttling Disabled Enabled Controls throttling and bandwidth limiting for the GMCH Delta Temperature in SPD Disabled Enabled Controls memory throttling based on thermal information present in the memory SPD 33 55 MSC ETE A945GSE 1 PRELIMINARY User Manual 5 2 3 4 Video Intel IGD Control Sub Menu CE RR f e IGD Device 2 Disabled Auto Enables or Disable the Internal Graphics Device by setting item to the desired value IGD Device 2 Function1 Disabled Auto Enables or Disable Function 1 of the Internal Graphics Device b
27. e on the Boot Menu requires the availability of an operating system on that device Selecting Boot ffom the Menu Bar displays the Boot menu which looks like this EE Boot priority order Boot priority order for next boot System tries to boot the 1 USB KEY first bootable device in this list USB FDC Use lt gt and lt gt to change order IDE 4 Use lt x gt to exclude or include device to boot priority list IDE 5 IDE O IDE 2 PCI LAN Exclude from boot order System does not try to boot a device from this list IDE 1 IDE 3 USB HDD USB CDROM USB ZIP USB LS120 PCI SCSI Pressing the F10 key during the bios boot phase will bring up the bios boot menu which will allow you to select a different boot device for the current boot process only In this boot menu only devices in the Boot priority list will selectable Devices excluded from boot order will not be shown 43 55 MSC ETE A945GSE 1 PRELIMINARY User Manual 5 2 7 The Exit Menu The following sections describe each of the options on this menu Note that lt Esc gt does not exit this menu You must select one of the items from the menu or menu bar to exit Exit Saving Changes After making your selections on the Setup menus always select Exit Saving Changes This procedures stores the selections displayed in the menus in CMOS short for battery backed CMOS RAM a special section of memory t
28. eeeenees 7 PA DNA elle o WEE 8 2 5 Interrupts DMA channels Upper memory iria eaaaaarerana aaa aaaaaanaranaa 8 2 5 1 POL DEVICOS sal siusciatetesa sos sis Eet heed ben Uso lin lit as Med act Med deg pes eet Dee EE E tee 8 2 5 2 DMA channels ecra a rn PR ED O errr eter a Para DU Ea a ta 9 25 05 Memonimap s rn an fate CARL Cae CARE CACL CARA naa CARL GARE 9 2 5 4 SMBuS address map 9 3 Mechanical Specification Saio cits eaves es aise ae eevee ee ei ee eee ere 10 SA TOPVIEW ee ER ER EE EE EE 10 3 2 ABottomVICW seas ne EE EE EE 10 4 ETX Connectorg eee ceraaareraaa aaa aanaaaa area anna aaa aaaaa area n anna anaaaa area EARE EEEE 11 4 1 Connector X1 PCI USB Audio 11 AD ConneciorX2 ISA rs ces pees tess teens E A cash asa tua dir ra nano E E E ATS 13 4 3 Connector X3 CRT Display TVout Serial Parallel Mouse Keyboard sssssessesnneeneeenena 15 4 4 Connector X3 alternate Gino 19 4 5 een e e tele tanita a ee ee ee eee 20 EIDE Ethernet Speaker Batterie 12C SMBUS etc 20 4 6 Connecior s FAN dica Dn eerie O 22 dm SATA el e 22 d Mini USB ConhectorS s s sssssissnisasasssnsasacnnnDA REESEN EES ER F NADA CANA ARES O NFL ANDA FARSA AS SSEA 23 4 9 LVDS Connector X9 option 23 NC e EEN 24 EN ALKOI 0 0 e EE 24 5 1 1 Startup Screen Overview irei aaa naaaaareea aaa aa naaaaaare aaa aaa aaaaaaneea ana aana 24 5 1 2 Activity Detection Background rir eaa
29. g No translate CHS only if HDD has gt 1024 cyls Yes translate CHS for all LBA capable disks Control where the Port 80h cycles are sent Enable the integrated local bus IDE adapter Enables or disables the OPROM of the onboard secondary PATA Controller Configure Cache Memory Configure CPU Control Configure MCH Control Configure Video Intel IGD Control MSC ETE A945GSE 1 PRELIMINARY User Manual RD RR RR Watchdog Options Configure Watchdog Options 5 2 3 1 Cache Memory Control Menu E oe ees Cache System BIOS area Uncached Enables caching of system BIOS area Write Protect Cache Video BIOS area Uncached Enables caching of video BIOS area Write Protect Cache D000 D3FF Disabled Disabled This block is not cached Cache D400 DY7FF Write Through Write through Writes are cached Cache D800 DBFF Write Protect and sent to main memory at once Write Back Write Protect Writes are ignored Write Back Writes are cached but not sent to main memory until necessary 5 2 3 2 Atom CPU Control Sub Menu CE RR Processor Power Disabled Selects the Processor Power Management GV3 Management desired C States Disabled C States and GV3 are Enabled disabled GV3 Only C States are disabled C States Only GV3 is disabled Enabled C States und GV3 are enabled Enhanced C States Disabled Enabled Enables Enhanced C State support Enable Disabled Enhan
30. gisters 3Dh Load alternate registers with CMOS values 4th Initialize RomPilot 42h Initialize interrupt vectors 45h POST device initialization 46h 2 1 2 3 Check ROM copyright notice 47h Initialize 120 support 49 55 MSC ETE A945GSE 1 PRELIMINARY User Manual Code Beeps POST Task Description 48h Check video configuration against CMOS 49h Initialize PCI bus and devices 4Ah Initialize all video adapters in system 4Bh QuietBoot start optional 4Ch Shadow video BIOS ROM 4Eh Display BIOS copyright notice 4Fh Initialize MultiBoot 50h Display CPU type and speed 51h Initialize EISA board 52h Test keyboard 54h Set key click if enabled 55h Configure USB devices 58h 2 2 3 1 Test for unexpected interrupts 59h Initialize POST display service 5Ah Display prompt Press F2 to enter SETUP 5Bh Disable CPU cache 5Ch Conventional memory test 60h Extended memory test 62h Address Test on Extended Memory 64h Jump to UserPatch1 66h Configure advanced cache registers 67h CPU feature MP and APIC initialization 68h Enable external and CPU caches 69h Setup System Management Mode SMM area 6Ah Display external L2 cache size 6Bh Load custom defaults optional 6Ch Display BIOS shadow status 70h Display error messages 72h Check for configuration errors 76h Check for keyboard errors 7
31. hat stays on after you turn your system off The next time you boot your computer the BIOS configures your system according to the Setup selections stored in CMOS If you attempt to exit without saving the program asks if you want to save before exiting During boot up PhoenixBlOS attempts to load the values saved in CMOS If those values cause the system boot to fail reboot and press lt F2 gt to enter Setup In Setup you can get the Default Values as described below or try to change the selections that caused the boot to fail Exit Discarding Changes Use this option to exit Setup without storing in CMOS any new selections you may have made The selections previously in effect remain in effect Load Setup Defaults To display the default values for all the Setup menus select Load Setup Defaults from the Main Menu If during boot up the BIOS program detects a problem in the integrity of values stored in CMOS it displays these messages System CMOS checksum bad run SETUP Press lt F1 gt to resume lt F2 gt to Setup The CMOS values have been corrupted or modified incorrectly perhaps by an application program that changes data stored in CMOS Press lt F1 gt to resume the boot or lt F2 gt to run Setup with the ROM default values already loaded into the menus You can make other changes before saving the values to CMOS Discard Changes If during a Setup Session you change your mind about changes you have made and
32. have not yet saved the values to CMOS you can restore the values you previously saved to CMOS Selecting Discard Changes on the Exit menu updates all the selections with their previous values Save Changes Selecting Save Changes saves all the selections without exiting Setup You can return to the other menus if you want to review and change your selections 44 55 MSC ETE A945GSE 1 PRELIMINARY User Manual 5 3 Bios Update If a System BIOS update is required please follow these instructions 1 Create a bootable DOS disk usb stick hdd 2 Copy PHLASH16 EXE BIOS WPH and UPDATE BAT to this device 3 Boot the system from this device 4 Type update bat to update the System BIOS 5 When the BIOS update has finished reboot the system Note After the system has been updated the CMOS has been changed to defaults and therefore it is necessary to enter Setup press F2 at boot time to configure the system settings 45 55 MSC ETE A945GSE 1 PRELIMINARY User Manual 5 4 Bios Crisis Recovery Note Contact your sales for information how to get the CRISDISK ZIP and an USB recovery dongle Please follow these simple steps to create a bootable crisis recovery medium Unzip CRISDISK ZIP and start the windows based program WINCRIS EXE on the host system A window will pop up as shown below Phoenix Crisis Disk Build 2 xl Project Path Driver Floppy Driver 1 44Mb ba
33. ict with SMBUS it is not possible to disable IRQ line 4 36 55 MSC ETE A945GSE 1 PRELIMINARY User Manual 5 2 3 5 2 ICH USB Control Sub Menu O re IL ze JL rem USB 1 1 Controllers Enable 1 Enable 2 Enable 3 Select the number of enabled USB1 1 Enable 4 Controllers USB 2 0 Controller Disabled Enabled Control USB 2 0 functionality through this Setup Item 5 2 3 6 ACPI Control Sub Menu ro IL e Le Enable ACPI No Yes En Disable ACPI BIOS Advanced Configuration and Power Interface Disable ACPI _Sx None S1 S2 S3 Select one of the ACPI power states S1 S2 or S3 If selected the corresponding power state will be disabled FACP RTC S4 Flag Disabled Enabled Valid only for ACPI Value Control the value for the RTC S4 flag in the FACP Table FACP PM Timer Flag Disabled Enabled Valid only for ACPI valve Controls the timer used by the OS through the FACP Tables Flags This is now possible with WINXP SP2 and beyond HPET Support Disabled Enabled This field is valid only in the WindowsXP OS Control the High Performance Event Timer through this setup option when enabled The HPET Table will then be pointed to by the RSDT and the proper enable bits will be set HPET Base Address OxFEDO0000 Select the Base Address for the High 0xFEDO1000 Performance Event Timer 0xFEDO2000 O0xFEDO3000 Passive Cooling Trip Point Disabled This value controls the temperature 47 C 55 C 63 C 71 C
34. ir alternates Dm Tab or Shift Tab Move cursor left and right i e at System Time System Date F9 Load the Default Configuration values for all menus a 26 55 MSC ETE A945GSE 1 PRELIMINARY User Manual Select an item To select an item use the arrow keys to move the cursor to the field you want Then use the plus and minus value keys to select a value for that field The Save Values commands in the Exit Menu save the values currently displayed in all the menus Display a submenu To display a submenu use the arrow keys to move the cursor to the sub menu you want Then press Enter A pointer marks all submenus 5 2 2 The Main Menu You can make the following selections on the Main Menu itself Use the sub menus for other selections Dee To come coma E System Time Enter Time HH MM SS System Date Enter Date DD MM YYYY 27 55 MSC ETE A945GSE 1 PRELIMINARY User Manual 5 2 2 1 Board Information ee Less Boot Counter Informative The number of times this board has booted up CPU Stepping Informative CPU ID Stepping CPU Cores Informative Number of CPU cores Northbridge Identification of the northbridge Southbridge Identification of the southbridge System Memory Amount of memory below 1MB Extended Memory Total amount of memory 28 55 MSC ETE A945GSE 1 PRELIMINARY User Manual 5 2 2 2 Master and Slaves The Master and Slave settings on the Main Menu control these t
35. ir respective owners Certification MSC Technologies GmbH is certified according to DIN EN ISO 9001 2000 standards Life Cycle Management MSC products are developed and manufactured according to high quality standards Our life cycle management assures long term availability through permanent product maintenance Technically necessary changes and improvements are introduced if applicable A product change notification and end of life management process assures early information of our customers Product Support MSC engineers and technicians are committed to provide support to our customers whenever needed Before contacting Technical Support of MSC Technologies GmbH please consult the respective pages on our web site at www msc technologies eu support boards for the latest documentation drivers and software downloads If the information provided there does not solve your problem please contact our Technical Support Email support msc technologies eu Phone 49 8165 906 200 2 55 MSC ETE A945GSE 1 PRELIMINARY User Manual Content 1 General Information rare aaa aaaaaa ane ea aa aaa naaaa ana aaa nana aaa aa nnr EEEn annn EEEE 4 1 1 Revision History raia aaanaaaaa arara nana anaaaaa nora aaa aa naaaaa area anna aannaaans 4 E nee re de EE 4 En le RE lee EE 5 CN Ee le EE 5 NR eeler H e E Le EE H 2 3 1 EE EA EE OE OO E A T E O seen 7 2 3 2 Installing a DDR2 SO DIMM mocdhule steer eeeeecaaeeeeeeeeeeeecaaaeeeee
36. ller Crisis recovery may take up to 5 minutes A long beep indicated successful recovery Crisis recovery does not include the bootblock 47 55 MSC ETE A945GSE 1 PRELIMINARY User Manual 5 5 Diagnostics Postcodes Postcodes can be seen on a special Postcode display either on the MSC mainboard or on an external Postcode PCI card There is an item in the bios setup to select the bus that should get the postcode data either PCI for external cards or LPC for onboard displays If a postcode display has only 2 digits only the lower byte of word value postcodes will be shown 5 5 1 Bootblock Bios Postcodes Code Bootblock Task Description BBH Bootblock Early Init after Reset 80h Chipset Init 81h Bridge Init 82h CPU Init 83h System Timer Init 84h System I O Init 85h Check forced Recovery Boot CMOS amp CMOS Backup Clear 86h Check BIOS Checksum 87h Goto BIOS start early BIOS initialzations 88h Init Multi Processor 89h Set Huge Segment 8Ah OEM Initializations 8Bh Init Interrupt and DMA Controller 8Ch Init Memory Type 8Dh Init Memory Size 8Eh Shadow Boot Block 8Fh Init SMM 90h System Memory Test 91h Init Interrupt Vectors 92h Init Realtime Clock 93h Init Standard Video 94h Init Beeper 95h Initialize USB Controller 95h Init Boot 96h Clear Huge Segment 97h Boot OS 99h Init Security 48 55 MSC ETE A945GSE 1 PRELIMINARY
37. m Disk Format Ge Removable Fired m Disk Options Create MINIDOS Crisis Disk Start C Create FULLDOS Crisis Disk C Format the Drive Diskette In the drop down box either select Floppy Drive A to create a recovery disk or select Removable Disk 0 xxxMb to create a recovery usb stick Disk options should be left at Create MINIDOS Crisis Disk Press the start button to generate the selected crisis recovery medium There are two possibilities to force the target system into crisis recovery mode either by USB crisis recovery dongle or by crisis recovery jumper 46 55 MSC ETE A945GSE 1 PRELIMINARY User Manual With the dongle you just have to plug it into a free USB port before switching the system on Please make sure that you use different USB controllers for USB dongle and USB crisis recovery medium After powerup crisis recovery mode should automatically start The crisis recovery jumper is located next to Com Express Board Connector the see picture below You have to shorten the two pins before applying power to the board As soon as crisis recovery is started you can remove the jumper The programming process is signalled by short beeps and terminated after successfull programming with one long beep After that the system is automatically rebooted Important Notes USB recovery dongle and USB crisis recovery device must not be plugged to the same USB contro
38. mable time window Possible watchdog delays Disabled default 1s 5s 10s 1min 5min 10min The time delay starts before the OS is loaded To retrigger the watchdog use the uebi exe tool 2 5 Interrupts DMA channels Upper memory IRQ used for available comment 0 Timer 0 No 1 Keyboard No 2 Slave 8259 No 3 COM2 COM1 No 1 4 COM1 COM2 No 1 5 LPT2 LPT1 Yes 1 2 6 Floppy Disk Controller No 1 7 LPT1 LPT2 No 1 2 8 Real Time Clock No 9 PCI Yes 1 10 PCI COM3 Yes 1 2 11 PCI COM4 Yes 1 2 12 PS 2 Mouse No 1 13 Floating Point Unit No 14 Primary IDE No 1 15 Secondary IDE No 1 1 If the device is disabled in SETUP the interrupt is available 2 Can be used by external Super I O controller FDC37C669 2 5 1 PCI Devices PCI Device PCI Interrupt REQ GNT 0 3 IDSEL PCI to ISA ITE8888 serial 4 45 5 AD29 Sound MODEM not used INTA INTB USB 0 3 Southbridge INTC 8 55 MSC ETE A945GSE 1 PRELIMINARY User Manual 2 5 2 DMA channels DMA used for available comment 0 Yes 1 ECP if enabled No LPT ECP mode if enabled 2 Floppy Disk Controller No 3 ECP if enabled No LPT ECP mode default 4 Cascade No 5 7 Yes 2 5 3 Memory map Upper Memory used for available
39. mode 35 55 MSC ETE A945GSE 1 PRELIMINARY User Manual O re IL zm JL Femme Disable Vacant Ports Disabled Enabled Controls automatic disabling if vacant SATA ports On board LAN Disabled Enabled Setting item to Disabled will remove the LAN from PCI Config Space Setting item to Enabled will allow the LAN to operate correctly PXE OPROM Disabled Enabled Enable PXE Option ROM Pop Up Mode Enable Disabled Enabled Select the proper mode If disabled bus master traffic is a break event and it will return from C3 C4 to CO based on break events If enabled ICH will observe a bus master request and it will take the system from a C3 C4 state to a C2 state and auto enable bus masters Pop Down Mode Enable Disabled Enabled Should be enabled only if Pop up is enabled If disabled ICH will NOT attempt to automatically return If enabled ICH will observe a NO bus master request and it can return to a previous C3 or C4 state DMI Link ASPM Support Enabled Disabled Control ASPM support for DMI link between GMCH and ICH 5 2 3 5 1 PCI Control Sub Menu EC oe e PCI IRQ line 1 8 Disabled Select the IRQ number that should Auto Select be used for this PCI interrupt line BD Os AO te Disabled PCI INT not functional Auto Select Let Bios decide which IRQ should be assigned 3 4 5 6 7 10 12 Use this IRQ number for the PCI interrupt Note To avoid a critical confl
40. naaaaareraaaaaaaaaaaaaneranaaaaana 24 bio Trusi dcore SelUb HOENEN 25 5 2 1 Configuring the System BIO 25 522 gt Shes Malin Men this eerste 27 5 2 3 The Advanced Men 31 Geh TheiSecuritya MED 41 520 JIhePowornMEN EE 42 5 2 6 The Boot Menu A 43 5 2 7 The Exit Mem 44 53 s_ BIOS Update Ee 45 5 4 Bios Crisis e VE 46 5 5 DiaGnOSticS POStCOES sett a r a est choked aa a aa aa a T aaa araa a ar aaraa a aaan aarian bennie biii 48 5 5 1 Bootblock Bios POSICOdES 1 eesti eee nie een eee eee 48 5 5 2 System Bios Postcodes eee eeeeeeeee eee eee e eee aaeee sete eeeecaaaeeeeeeeeeteccaaaeeeeeeeeneeeaaaes 49 5 5 3 Memory Detection Postcodes AAA 53 de GI ere e 54 G Ree eet e E 55 3 55 MSC ETE A945GSE 1 PRELIMINARY User Manual 1 General Information 1 1 Revision History Rev bate spon SEIN 2014 09 19 New covering page 1 2 Introduction The ETe A945GSE is an all in one Atom N270 CPU module It is fully compliant with the ETX 3 0 standard The module is based on Intel Atom N270 CPU and the Intel 945GSE chipset The Intel Atom N270 CPU is on the embedded roadmap of Intel which means that the processors are long term available The Intel Atom N270 CPU supports 533MHz CPU bus The Intel 945GSE supports 400 533MHz memory bus The ETE A945GSE supports DDR2 memory modules It provides a 200 pin SO DIMM socket giving you the flexibility to configure your system up to 2GB of DDR2 DRAM
41. read PD4 DSKCHG Disc changed PD5 RES nc PD6 RES nc PD7 RES nc ERR HDSEL Head select O INIT DIR Direction O SLIN STEP Motor step O ACK DRV1 Drive 1 select O BUSY MOT1 Motor 1 select O PE WDATA Raw write data O SLCT WGATE Write enable O Signal Description of LPT signals UO Note shared with FDC LPT FLPY LPT or Floppy Interface Connect to VCC resistor configuration input 4K7 PU 10k 5V STB RES Strobe signal O AFD DENSEL Automatic feed O PDO INDEX Databus DO UC PD1 TRKO Databus D1 UO PD2 WP Databus D2 UO PD3 RDATA Databus D3 UC PD4 DSKCHG Databus D4 UC PD5 RES Databus D5 UC PD6 RES Databus D6 UC PD7 RES Databus D7 UC ERR HDSEL LPT error INIT DIR Initiate O SLIN STEP Select O ACK DRV1 Acknowledge BUSY MOT1 Busy PE WDATA Paper empty SLCT Power ON WGATE 17 55 MSC ETE A945GSE 1 PRELIMINARY User Manual Signal Description of LVDS Flatpanel UO Note signals BIASON n C Display contrast voltage ON O DIGON Display Power ON O 3 3V tolerant BLON Display Backlight ON O PU 4k7 5V LCDDOO LVDS LO O LCDDO1 LVDS LO O LCDDO2 LVDS L1 O LCDDOS LVDS L1 O LCDDO4 LVDS L2 O LCDDO5 LVDS L2 O LCDDO6 LVDS LCLK O LCDDO7 LVDS_LCLK O LCDDO8 LVDS _L3 O LCDDO9 LVDS L3 O LCDDO10 LVDS UO O LCDDO11 LVDS U 0 O LCDDO12 LVDS U 1 O LCDDO13
42. rupt for more than one port the menu displays an asterisk at the conflicting settings 39 55 MSC ETE A945GSE 1 PRELIMINARY User Manual 5 2 3 9 Watchdog Options E RR Lee Watchdog delay second After watchdog is activated he waits seconds selected delay time before he starts seconds counting the timeout period seconds minutes minutes Watchdog timeout second Select the maximum watchdog second trigger period seconds If the watchdog will not be triggered seconds during selected period system reset seconds will be generated minute minutes 10 minutes Watchdog start on boot No Yes Select if the watchdog should be started at the end of POST 40 55 MSC ETE A945GSE 1 PRELIMINARY User Manual 5 2 4 The Security Menu me om om Supervisor Password Is Displays Supervisor Displays the current status of the Password Is Supervisor password Clear or Set User Password Is Displays User Password Is Displays the current status of the User password Clear or Gei Set Supervisor Press return to enter Supervisor Password controls access to Password supervisor password the setup utility Set User Password Press return to enter user User Password controls access to the password system at boot Password on boot Disabled Enables password entry on boot Enabled TPM Support Disabled Enable Trusted Platform Module support Enabled Current TPM
43. s integrated in W83627 SIO 2x TTL IrDA on COM2 integrated in W83627 SIO 1 Parallel Port PS 2 compatible ECP EPP via SETUP configurable pins shared with floppy port 5 55 MSC ETE A945GSE 1 PRELIMINARY User Manual Keyboard Mouse Realtime Clock Watchdog TPM optional EDID EEPROM BIOS EEPROM System Monitoring Power supply Typical supply current DOS prompt Typical CMOS battery power consumption Environment Dimensions integrated in W83627 SIO MFIl Keyboard Interface PS 2 Mouse Interface integrated in 82801GBM ICH7 M external battery required Microcontroller PIC12F509A Start delay and timeout configurable via SETUP creates hardware reset Trusted Plattform Module TPM 1 2 SLB 9635 TT 1 2 on Board EDID EEPROM enable disable via SETUP Phoenix Trusted SecureCore in SPI Flash device EEPROM for CMOS Setup backup 1 fan with speed input valid only if optional fan connector is used 3 temperatures CPU GSE and board EMC2104 6 voltages Vcore CPU 2 5V 3 3V 1 5V 1 05V Vbat W83627 SIO 5V 45 1 6A 1 8 A RTC CMOS integrated in Intel 82801GBM ICH7 M Temperature O 60C operating 25 85 C non operating Humidity rel O 95 operating 5 95 non operating Note A heat spreader plate is available from MSC providing a standard thermal interface for the module The heat spreader is not a heat sink 95x 1
44. s Bios Controlled with following supported ranges Down Spread 05 2 Center Spread 0 25 0 5 Spread Percentage Down 0 5 Down 1 Down If controlled by Software select 1 5 Center 0 25 Center Percentage of PLL3 Spread 0 5 Spectrum 38 55 MSC ETE A945GSE 1 PRELIMINARY User Manual 5 2 3 8 I O Device Configuration Menu o ee Serial Port A Disabled Enabled Auto Disabled Disabled the device Enabled User configuration Auto BIOS or OS chooses configuration Base O address 3F8 2F8 3E8 2E8 Set the base I O address for Serial Port A Interrupt Set the interrupt for Serial Port A Serial Port B Disabled Enabled Auto Disabled Disabled the device Enabled User configuration Auto BIOS or OS chooses configuration Mode Normal IR ASK IR Set the mode for Serial Port B wired infrared Base O address 3F8 2F8 3E8 2E8 Set the base I O address for Serial Port B Interrupt 3 4 Set the interrupt for Serial Port B Parallel Port Disabled Enabled Auto Disabled Disabled the device Enabled User configuration Auto BIOS or OS chooses configuration Output Set the mode for Parallel Port Bi directional ECP Base O address 378 278 3BC Set the base I O address for Parallel Port Interrupt Set the interrupt for Parallel Port 7 DMA channel 1 3 Set the DMA channel for Parallel Port only available if mode was set to ECP Warning If you choose the same UO address or Inter
45. that is included in Phoenix TrustedCore products The default bios behavior is to show an informational text screen during bios POST phase but the graphical boot screen can be enabled in the bios setup The standard boot screen is a black screen including a progress bar at the bottom of the screen This bar indicates the progress of the Startup Screen functions and provides user prompting and POST status The following figure shows the various parts of a generic Startup Screen at 1024x768 resolution 5 1 2 Activity Detection Background While the TrustedCore Startup screen is displayed press the Setup Entry key F2 TrustedCore default The TrustedCore Startup Status Bar acknowledges the input and at the end of POST the screen clears and setup launches An example of the Startup Status Bar displaying changing state is shown in the following figure The Please Wait text is displayed after the F2 key is pressed to acknowledge user input Active status bar Please Wait a 24 55 MSC ETE A945GSE 1 PRELIMINARY User Manual 5 2 TrustedCore Setup Utility With the Phoenix TrustedCore Setup program you can modify TrustedCore settings and control the special features of your computer The Setup program uses a number of menus for making changes and turning the special features on or off This chapter provides an overview of the Setup utility and describes at a high level how to use it 5 2 1 Configuring the System BI
46. vice CD ROM CD ROM drive Cylinders 1 to 65536 Number of Cylinders 1 to 16 Number of read write heads 1 to 63 Number of sectors per track Multi Sector Transfers Disabled 2 sectors Any selection except Disabled 4 sectors 8 sectors determines the number of sectors 16 sectors transferred per block 29 55 MSC ETE A945GSE 1 PRELIMINARY User Manual E RR o e LBA Mode Control Disabled Enabled Enabling LBA causes Logical Block Addressing to be used in place of Cylinders Heads amp Sectors 32 Bit I O Disabled Enabled Enables 32 bit communication between CPU and IDE card Requires PCI or local bus Transfer Mode Standard Selects the method for transferring the Fast PIO data between the hard disk and Fast PIO system memory Fast PIO The Setup menu only lists those Fast PIO options supported by the drive and FPIO 3 DMA platform FPIO 4 DMA 2 Ultra DMA Mode Disabled Ultra DMA Mode supports 33 66 100 Mode MB sec transfer rate for fixed disk Mode drives Mode Mode Mode Mode 5 SMART Monitoring Disabled Enabled Displays the status of SMART Monitoring if supported by the used drive WARNING Incorrect settings can cause your system to malfunction 5 2 2 3 Boot Options Disabled Enabled Enabled displays system configuration on boot Boot time Diagnostic Disabled Enabled Enabled displays the diagnostic Screen screen during boot Disabled displays the Boot Logo Post Errors Disabled Enabled
47. y setting item to the desired value IGD Boot Type VBIOS default Select the Video Device that will be CRT activated during POST LFP EFP EFP2 CRT LFP CRT EFP 1024x768 1 PPC 18b Select the LCD panel used by the 1600x1200 2 PPC 24b Internal Graphics Device by selecting 1280x1024 2 PPC 24b the appropriate setup item 1024x768 1 PPC 24b The first item is Panel 1 the last item is Panel 16 Some Panels are not numbered due to size constraints IGD LCD Panel Type Note Due to size constrains not all Panels are exactly numbered The first item is Panel 1 the last one Panel 16 IGD Panel Scaling Auto Force Scaling Off Selects the LCD panel scaling option used by the Internal Graphics Device 1 Auto 2 Force Scaling 3 Off IGD Backlight 0 10 20 30 40 Select the starting brightness for the Brightness 50 60 70 80 90 LVDS backlight signal 100 DVMT 3 0 Mode Fixed DVMT Combo Select the configuration of DVMT 3 0 Graphics Memory that Driver will allocate for use by the Internal Graphics Device 1 Fixed 2 DVMT 3 Combo Pre Allocated Memory 1 MB 8 MB Select the amount of Pre Allocated Size Graphics Memory for use by the Internal Graphics Device Total graphics Memory 64MB 128 MB MaxDVMT Select the amount of Total Graphics Memory Pre Allocated Fixed DVMT for use by the Internal for use by the Internal Graphics Device 34 55 MSC ETE A945GSE 1 PRELIM
48. ypes of devices e Hard disk drives IDE and SATA e Removable disk drives e CD ROM drives There is one IDE connector on your motherboard usually labeled Primary IDE There are usually two connectors on each ribbon cable attached to IDE connector When you have connected two drives to this connector the one on the end of the cable is the Master When you enter Setup the Main Menu displays the results of Autotyping information each drive provides about its own size and other characteristics and how they are arranged as Masters or Slaves on your machine Note Do not attempt to change these settings unless you have an installed drive that does not autotype properly such as an older hard disk drive that does not support autotyping H you need to change your drive settings select one of the Master or Slave drives on the Main Menu This will display a menu like this Note The capacity is displayed in real Mbytes 1MB 1024 1024 Bytes Drives with a total capacity greater than 8Gbyte operate in LBA format only E O ees None Autotyping is not able to Removable supply the drive type or end user has selected None disabling any drive that Removable may be installed ATAPI Auto Autotyping the drive itself supplies the information User You supply the hard disk drive information in the following fields IDE Removable Removable Disk Drive ATAPI Removable Removable Disk Drive Other ATAPI non specific ATAPI De
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