MPC5668EVB User`s Manual - Freescale Semiconductor
Contents
1. FITTED TXEN MCU PKS is connected to FlexRay A transceiver TXEN 2 FITTED MCU is connected to A transceiver RXEN YA FITTED WAKE Transceiver WAKE is connected to GND 20 A pier STB CAN Transceiver STB is connected to 5v Posn 3 4 20 A ewe EN CAN Transceiver is Enabled Posn 3 4 FITTED WAKE CAN Transceiver WAKE is connected to GND 421 eren STB CAN Transceiver STB is connected to 5v Posn 3 4 J21 erred EN CAN Transceiver is Enabled Posn 3 4 J22 MLB Monitor No Jumpers J23 SCI B FITTED TXD MCU TXD B is routed MAX3223 J24 SCI B FITTED MCU is routed via MAX3223 J25 Flex PWR UN Posn 1 2 FITTED 12V 12V Flexray circuitry is powered from main 12V input 5V 5V Flexray circuitry is powered from 5 0V switching reg deo Flex PA VIO VIO Flexray circuitry is powered from VDDE2 Posn 5 6 MPC5668bEVBUM D Page 25 of 29 MPC5668EVB Users Manual Rev 0 1 J26 Flex A FITTED BGE Flexray A interface BGE signal is pulled to VIO Posn 1 2 J26 Flex A FITTED EN Flexray A interface EN signal is pulled to VIO Posn 3 4 J26 Flex A FITTED STBEN Flexray A interface STBN signal is pulled to VIO Posn 5 6 J26 Flex A FITTED WAKE Flexray A in2. I E LL zl E acena e m TE GAN ECT ET 5685 7 1 a 8 T wo Place near MOST OPTICAL MPC5568EVBUM D Page A 14 May 2009 MPC5668EVB Users Manual Rev 0 1 MPC5568EVBUM D All RESET Pullup Resistors are shown on Reset Circuitry page TERMINATION RESISTORS Page A 15 May 2009 MPC5668EVB Users Manual Rev 0 1 May 2009 PHANTOM PORT CIRCUITRY ERRABAL MPC5568EVBUM D Page A 16 5668 Users Manual Rev 0 1 May 2009 exi mpe ran PortC ADC FlexRay 120 BA PortD CAH 12C rpe PortE 9MIOS 12C Portc ENICS Tp an FESD Port EMIOS FEC Kepa PortJ EMIOS DSPI Reset Connectors are 0 1 through hole headers lt x x USER CONNECTORS ptm Phantom Dort A 0 Phantom Dort 1 MPC5568EVBUM D Page A 17 MPC5668EVB Users Manual Rev 0 1 MPC5568EVBUM D Lnd E 28 DN Om ROV IR User Peripherals Inc Prototyping Page A 18 May 2009
3. LOW GND Figure 3 9 CAN Physical Interface Connector Each of the MCU signals to the CAN transceivers is jumpered allowing the transceiver to be isolated if that MCU pin is not configured or used for CAN operation There is a 2x2 jumper for each CAN channel one for Rx one for Tx There are also two power jumpers J30 to physically remove power 12v and 5v from both of the CAN transceivers Jumpers J20 CAN B and J21 CAN A are configuration jumpers for each of the Transceivers to control Wake Standby and Enable Jumpers can be fitted to select default values or wires can be used to connect these pins to the MCU Table 3 14 CAN Control Jumpers 430 J31 J7 J30 FITTED D 5v is applied to both CAN transceivers VCC Posn 1 2 REMOVED No 5v power is applied to CAN transceivers J30 FITTED D 12v Power is applied to both CAN transceivers VBAT Posn 3 4 REMOVED No 12v power is applied to CAN transceivers J31 CAN A FITTED D TX is connected to CAN controller Posn 1 2 REMOVED MCU CNTX A is NOT routed to CAN controller J31 CAN A FITTED D RX CNRX A is connected to CAN controller Posn 3 4 REMOVED MCU CNRX A is NOT routed to CAN controller J29 CAN B FITTED D TX is connected to CAN controller Posn 1 2 REMOVED MCU CNTX B is NOT routed to CAN controller J29 CAN B FITTED D RX MCU CNRX B is connec
4. wazaa iieis 3 3 1 POWER SUPPLY CONFIGURATION enne tentent nnt tenent nette 4 21 1 Power Supply Connectors eot etie elio a PR ERR 4 3 52 Power Switch SW6 cs eere Na Qa Ya O Saa 4 3 1 8 Regulator Power Jumpers J42 J44 J45 and 46 5 3 1 4 Power Status LED s and FUSE s sua eene ete ethernet eher 5 3 1 5 MCU Supply Routing and Jumpers J41 J42 J43 J44 J45 J46 J47 448 J49 J50 6 3 1 6 Regulator Power Domains mmama 8 3 2 MCU CLOCK GON TROL ocn ono dro db ast ae d RH E d s das 9 3 2 1 Main Clock Selection J85 J87 J61 and 66 9 3 22 32Khz External Clock Selection J67 and 471 sse 10 3 3 RESET CONTROL J MBER 75 rore stt reb Pte eR tee t idonee 11 Reset EEDS 11 3 3 2 Reset Buffering Schemes 12 3 3 3 Reset Boot Configuration J69 n nennen nennen nene 13 3 4 ONCE AND NEXUS CONFIGURATION J32 J70 13 3 4 1 Debug Connector Pinouls 14 3 5 CAN CONFIGURATION 20 21 29 30 31 2 1 1 412 24 421 4 101002060060000000000000005000 15 3 6 RS232 C
5. LVI circuitry is located 3 3 Reset Control Jumper J75 to the t left of the MCU in the area titled HESET The EVB incorporates an LVI Low Voltage Inhibit device to provide under voltage protection for the two main switching regulators and 3 3v When either of these regulator voltages drops below a certain threshold level the LVI will assert the MCU reset line to prevent incorrect operation of the MCU or EVB circuitry The table below shows the approximate threshold voltages for each regulator Table 3 7 LVI Monitor Threshold Voltages 5 0V Switcher 1 47 3 3V Switcher 1 47 is powered from the 5 0V switching regulator and monitors the 3 3V regulator using a pM power fail monitor circuit The LVI also provides a de bounced input for EVB reset switch SW5 Jumpers are provided to disable either the main LVI reset out which affects the reset from the 5 0V switching regulator and from the reset switch or the power fail out circuit which only affects the reset from the 3 3V regulator If the 5v regulator LVI is disabled the reset switch will not function Table 3 8 LVI Control Jumpers FITTED D 5 0V switching regulator is monitored Reset switch J75 active Posn 1 2 REMOVED 5 0V switching regulator is not monitored Reset switch inactive J75 FITTED D 3 3V switching regulator is monitored Posn 3 4 REMOVED 3 3V switching regulator is not monitored Notes Ifthe 5 0
6. MPC5668EVBUM D Page 3 of 29 5668 Users Manual Rev 0 1 3 1 Power Supply Configuration the bottom left area of the EVB EVB requires an external power supply voltage of 12V DC minimum 14A This allows the EVB to be easily used in a vehicle if required The single input voltage is regulated on board using 3 switching and 1 linear regulators to provide the necessary EVB and MCU operating voltages of 5 0V 3 3V and 2 5V For flexibility there are two different power supply input connectors on the EVB as detailed below 3 1 1 Power Supply Connectors 2 1mm Barrel Connector P22 This connector should be used to connect the supplied wall plug mains adapter Note if a replacement or alternative adapter is used care must be taken to ensure the 2 1mm plug uses the correct polarisation as shown below GND Figure 3 2 2 1mm Power Connector 2 Way Lever Connector P23 This can be used to connect a bare wire lead to the EVB typically from a laboratory power supply The polarisation of the connectors is clearly marked on the EVB Care must be taken to ensure correct connection V 12V Figure 3 3 2 Power Connector 3 1 2 Power Switch SW6 Slide switch SW6 can be used to isolate the power supply input from the EVB voltage regulators if required Moving the slide switch to the right away from connector P23 will turn the EVB on Mov
7. 29 So 2 freescale semiconductor MPC5668EVB Users Manual Revision 0 1 May 2009 MPC5668EVB Users Manual Rev 0 1 May 2009 Revision History D McMenamin Initial Release PCB s only Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not des
8. normal I O port J86 RV1 are located next to P17 To allow the EVB core voltages to be monitors by the ATD J74 allows the 2 5v 3 3v and 5v Switcher and Linear regulator outputs to be connected to the ATD inputs J73 allows the 12v EVB supply to be monitored via resister ladder to reduce the voltage to a level that is in spec of the ATD s range 65 of the 12v supply is applied to the ADC via the resistor ladder Table 6 2 RV1 Connection Jumper J8 Jumper J86 FITTED Output from variable resistor RV1 is applied to PAO RV1 REMOVED D Output from RV1 is not connected to MCU disabled J73 FITTED 65 of the output from 12v Reg is applied to PA14 VSUP REMOVED D 12v Reg Output is not connected to 14 J74 FITTED Output from 2 5v Reg is connected to PA10 1 2 REMOVED D Output from 2 5v Reg is NOT connected to PA10 J74 FITTED Output from 3 3v Reg is connected to PA10 POSN3 4 REMOVED D Output from 3 3v Reg is NOT connected to PA10 J74 FITTED Output from 5v Switching Reg is connected to PA10 POSN 5 6 REMOVED D 2 from 5v Switching Reg is NOT connected to J74 FITTED Output from 5v Linear Reg is connected to PATO POSN7 8 REMOVED D Output from 5v Linear Reg is NOT connected to PA10 Note PA14 and 15 can also be used for the EXTAL32 and XTAL32 32Khz reference clock If these pins are used for this purpose they will not be available for GPIO
9. r Power supply Input and filter cuan 5 Test and reference points TEM Tem TID Te Power 1 Switching Regulators Input Linear and Switchers 25V 025A Switching Regulator 1124 10 rA MPC5568EVBUM D Page A 3 May 2009 MPC5668EVB Users Manual Rev 0 1 May 2009 x lt x x x Power 2 MCU and Routing MLB 2 5V 3 3V VRC 3 3V OR 5V Marzus 3 3V PLL 3 37 MPC5568EVBUM D Page A 4 5668 Users Manual Rev 0 1 ID VUKE pen M Clock Circuitry MPC5568EVBUM D Page A 5 May 2009 MPC5668EVB Users Manual Rev 0 1 IVI Circuit RESET and Boot Configuration MPC5568EVBUM D Page A 6 May 2009 5668 Users Manual Rev 0 1 MPC5568EVBUM D May 2009 SS x JTAG and Nexus Connectors WS TOR T ew masan AA bes E nar amp mennan wun ms 2 4 i z u x a Hr z x 2H E x E x x E a E 7 5668 Users Manual Rev 0 1 CAN PHYSICAL INTERFACE 1 MPC5568EVBUM D Page A 8 May 2009 MPC5668EVB Users Manual Rev 0 1
10. 10 Port J Connector Pinout P29 1 PJO eMIOS 15 2 PJ1 eMIOS 14 3 PJ2 eMIOS 13 4 PJ3 eMIOS 12 5 eMIOS 1 1 6 PJ5 eMIOS 10 7 PJ6 eMIOS 9 8 PJ7 eMIOS 8 9 PJ8 eMIOS 7 10 PJ9 eMIOS 6 11 PJ10 eMIOS 5 12 PJ11 eMIOS 4 13 PJ12 eMIOS 3 14 PJ13 eMIOS 2 15 PJ14 eMIOS 1 16 PJ15 eMIOS 0 17 GND 18 GND 6 1 10 Port K RESET MLB Connector P30 Table 6 11 Port K Connector Pinout P30 1 PKO MLBCLK 2 PK1 MLBSIG 3 PK2 MLBDAT 4 PK3 FR A RX FR A TX 5 4 TX 6 5 EN 7 PK6 FR B RX 8 PK7 FR B TX FR B TX E 11 PK10 Pcs 12 GND 18 RST OUT 14 TST RST 15 GND 16 GND MPC5668EVBUM D Page 31 of 29 6 2 Prototyping Area User LED s Switches There is a rectangular prototype area on the EVB consisting of a 0 1inch pitch array of through hole plated pads Power from all three voltage regulators is readily accessible along with GND This area is ideal for the addition of any custom circuitry Adapters are available to convert SMD devices to 0 1inch pitch through hole Some of the pads in the prototyping area are connected to the CAN C F pins of the MCU as well as power and the DB9 connectors This allows an additional 4 CAN physical interfaces to be added to the EVB for evaluation with the MCU The layout of this is shown in Figure X below Note The power supply lines to the prototype area are connected directl
11. 2 D EVB INT is Routed to the EVB INIC 2 3 INIC150 INT is Routed to the MOST150 header J59 SCL 1 2 D EVB SCL is Routed to the EVB INIC 2 3 INIC150 SCL is Routed to the MOST150 header 1 2 D EVB MLBSIG is Routed to the EVB INIC Je MEBSIG 2 3 INIC150 MLBSIG is Routed to the MOST150 header The status and reset lines can also be isolated via J56 and J64 If required the standard fit INIC can be removed and replaced with the ROM memory alternate Please observe the power supply requirements of the device MPC5668EVBUM D Page 22 of 29 5668 Users Manual Rev 0 1 3 11 Phantom Ports J76 J77 J78 J79 J80 To support the de serialisation feature of the MPC5668 module the EVB features 4 chained SIPO shift registers interfaced to DSPI A This allows a 32 bit phantom port to be created The port can operate at either 5V or 3 3V depending on the VDDE2 supply voltage J42 This is outputted on P24 and P25 Please refer to the MPC5668 Reference manual for guideline on how to create software to interface to the phantom part Five jumpers are used to allow the signals and power to be isolated from the phantom port circuitry These are detailed in table x below Table 3 24 Phantom Port Control J35 J36 J55 FITTED D PFO DSPI A CLK is connected to the phantom port J76 CLK circuitry REMOVED PFO DSPI A CLK is disconnected from the phantom port circuitry FITTED
12. 3V J42 1 2 D 5 0v MCU VDDE2 is powered from 5v VDDE2 2 3 3 3V MCU VDDE2 is powered from 3 3V J44 1 2 D 5 0v MCU VDDE3 is powered from 5v VDDE3 2 3 3 3V MCU VDDES is powered from 3 3V J41 1 2 D 5 0v MCU VDDE4 is powered from 5v VDDE4 2 3 3 3V MCU VDDE4 is powered from 3 3V 3 3V J48 FITTED MCU VDD33 pin is powered from switching regulator VDD33 REMOVED MCU VDD33 pin is not powered externally D J50 FITTED VDDSYN pin is powered from switching VDDSYN regulator REMOVED MCU VDDSYN pin is not powered externally D 3 3v J45 1 2 D 2 5V MCU VDD pin is powered from 1 5v switching 2 5V VDDEMLB regulator 2 3 3 3V MCU VDD pin is not powered externally The jumper configuration shown in Table 3 2 details the default state of the EVB In this configuration all power is supplied from the Linear and Switching regulators VDDA is connected to the 5 0V Linear regulator VRC is connected to the 5 0V switching regulator VRCSEL is connected to logic 1 enabling the internal 3 3V regulator J48 and J50 are removed VDDE 1 4 are connected to the 5 0V switching regulator CAUTION When jumper J47 VRCSEL is in position 1 2 INT the MCU s 3 3V internal voltage regulators are enabled and supply power to the 3 3V power domains In this case jumpers J48 VDD33 and J50 VDDSYN must be removed Similarly when jumper J47 is removed no power is supplied to the MCU internal voltage regulators and jumpers
13. D VDDE2 Domain power is applied to the 4 shift registers U15 U16 U21 U22 dr REMOVED SREG PWR power is applied to the 4 shift registers 015 U16 U21 U22 FITTED D PF1 DSPI A Serial Data Out is connected to the phantom port circuitry J78 REMOVED IN PF1 DSPI A Serial Data Out is disconnected from the phantom port circuitry FITTED D PF11 is connected to the phantom port circuitry J79 CLR Allows for software to reset the Shift registers REMOVED PF11 is disconnected from the phantom port circuitry FITTED D PF3 DSPI A PCS is connected to the phantom port circuitry Jan REMOVED OUT PF3pSPIA PCS is disconnected from the phantom port circuitry MPC5668EVBUM D Page 23 of 29 4 Pin Usage The table below provides a useful cross reference to see what MCU port pins used by the various EVB peripherals and functions Note that there are some overlapping functions for example the Nexus and External bus as shown by the shaded boxes in the table below Table 4 1 EVB MCU Pin Usage FlexRay A PK 3 5 Enabled By Default CANA PDJ O 1 CANB PD 2 3 SCIA PD 12 13 SCIB PD 14 15 LINC 0 11 LIND PE 2 3 FlexRay B PK 6 8 Reset PK 9 Config Ethernet PG 6 9 0 11 PG 12 15 PH S 7 MOST MLB PB 0 1 PG 0 PK O 2 PG 2 5 User RVAR PA 0 Phantom PF 0 1 3 11 Port MPC56
14. DB9 female connector PC RS 232 compliant via a Maxim physical interface SCI channels C and D can be routed to LIN interface header 0 1 and molex connectors both will full physical transceivers FlexCAN channels A and B can be routed to 0 1 headers and DB9 connector via a Philips high speed CAN transceiver which supports both 3 3V and 5V inputs FlexCAN channels C D E and F are routed to the prototyping area with DB9 connectors to allow additions CAN physical interfaces to be easily integrated User prototyping area consisting of a 0 1 grid of through hole pads with easy access to the EVB ground and power supply rails Ethernet signals routed to a National Semiconductor physical interface and Pulsejack RJ45 connector with integrated magnetics MLB signals routed to SMSC MOST INIC with Tyco Optical Transceiver INIC JTAG and MLB monitor ports Support for optional ROM INIC or MLB150 daughter card from SMSC 4 active low LED s and 4 pushbutton switches for development purposes Jumper selectable variable resistor connected to ADC channel 0 driving between VRH and VRL Liberal scattering of GND test points surface mount loops placed throughout the EVB To alleviate confusion between jumpers and headers all EVB jumpers are implemented as 2mm pitch whereas headers are 0 1 2 54 This prevents inadvertently fitting a jumper to a header IMPORTANT Before the EVB is used or power is applied please fully read the followin
15. J85 U20 PWR REMOVED EVB oscillator module U20 is not powered 1 2 D MOD Daughter card EXT CLK is routed from U20 dor OSG SEL 2 3 SMA Daughter card EXT CLK is routed from P32 SMA Connector J66 1 2 D y2 MCU Clock is Y2 Must Match J61 2 3 GND MCU Clock is Selected by J87 J61 1 2 D Y2 MCU Clock is Y2 Must Match J66 2 3 EVB MCU Clock is Selected by J87 Note that the 3 3V regulator must be enabled when using oscillator module Y1 CAUTION The MPC5668 clock circuitry is all 3 3v based Any external clock signal driven into the SMA connector must have a maximum voltage of 3 3V MPC5668EVBUM D Page 9 of 29 3 2 2 32Khz External Clock Selection 467 and 471 The EVB also supports an external 32KHz watch crystal that can be used as a timing source within the MCU The 32Khz crystal can be optionally connected to PA 14 and PA 15 of the MCU When using the 32KHz crystal PA 14 and PA 15 will not be visible on P17 Port A header 32KHz EVB Clock Circuitry J67 MCU PA 14 EXTAL32 PA 14 PA 15 e BAL TEENS Figure 3 6 EVB Clock Selection Table 3 6 32Khz Crystal Jumper Selection J67 1 2 D 32Khz Crystal 2 is connected to Must Match J71 2 3 PA 14 Pin functions as Normal I O J71 1 2 D Y3 32Khz Crystal Y2 is connected to MCU Must Match J67 2 3 PA 15 Pin functions as Normal MPC5668EVBUM D Page 10 of 29 switch RED
16. PHY PWR The DP4348C Ethernet Physical Interface is powered from the 3 3v SR J63 RJ45 No Jumpers J64 MOST FOT 1 2 STATUS MOST FOT is Status is connected to PB1 J65 MLBSIG 1 2 EVB MLBSIG is Routed to the EVB INIC J66 MCU CLK 1 2 Y2 MCU Clock is Y2 J67 32KHz CLK 1 2 32Khz Crystal 2 is connected to _ External reset source LVI Debug or Target will be able Jeg BS TAN to assert MCU reset J69 BOOT CFG 1 2 FLASH MCU boots from internal flash J70 TCLK PULL 1 2 VDDE2 Pec NEXUS TCLK signal is pulled to VDDE2 via J71 32KHz CLK 1 2 Y3 32Khz Crystal Y2 is connected to MCU J72 Not Implemented J73 ADC VSUP REMOVED Output from variable resistor RV1 is applied to MCU 474 REMOVED On board Voltage levels not connected to EVB J75 1 2 FITTED Enables 3 3v board level LVI J75 3 4 FITTED Enables 5v board level LVI J76 FITTED CLK de A CLK is connected to the phantom port SREG VDDE2 Domain power is applied to the 4 shift registers era PWR 015 U16 021 U22 J78 FITTED PFi DSPI_A Serial Data Out is connected to the phantom port circuitry PF11 is connected to the phantom port circuitry Allows ure for software to reset the Shift registers J80 FITTED OUT iesu A PCS is connected to the phantom port J81 5 0v LINEAR FITTED DISABLE 5 0v linear regu
17. PINOUT P18 sss 29 TABLE 6 4 PORT C CONNECTOR PINOUT P19 n n nnne nnne nnns 29 TABLE 6 5 PORT D CONNECTOR PINOUT 20 29 TABLE 6 6 PORT E CONNECTOR PINOUT P21 u tee e RIO RR OR ORTOS SIT aes 30 TABLE 6 7 PORT F CONNECTOR PINOUT P26 nnne nennen tenentes 30 TABLE 6 8 PORT F CONNECTOR PINOUT 27 30 TABLE 6 9 PORTH CONNECTOR PINOUT P28 u ai AI kane 30 TABLE 6 10 PORT J CONNECTOR PINOUT P29 0 ccccecesseseseseesesesceseseeeescseesesesesacaesesaeseeesaesecaeseeeseeeeseaeeeecaeeesaeeeatas 31 TABLE 6 11 PORT K CONNECTOR PINOUT P30 31 MPC5668EVBUM D iii 1 Introduction This user s manual details the setup and configuration of the Freescale Semiconductor MPC5668 Evaluation Board hereafter referred to as the EVB The EVB is intended to provide a mechanism for easy customer evaluation of the MPC5668 family of microprocessors and to facilitate hardware and software development At the time of writing this document the MPC5668 family is offered 208 package 256MAPBGA package supporting Nexus debug is also available for development purposes For the latest product information please speak to your Freescale representative or consult the MPC5668 web pages at www freescale com The EVB is intended for bench laboratory use and has been designed using
18. RMCK SCK and FSY are brought out to the header J22 to allow for monitoring and control if required J88 provides the MLB monitor header that is compatible with the SMSC MLB Monitor hardware The Pin out of this is shown in Figure x below MLBCLK 1 2 VSS MLBSIG 3 4 VSS MLBDAT 5 6 VSS MLBSI 7 8 VSS MLBDI 9 10 VSS Figure 3 13 MLB Monitor Connector MPC5668EVBUM D Page 21 of 29 MPC5668EVB Users Manual Rev 0 1 May 2009 Port J11 is placed on the edge of the EVB to allow the SMSC MOST 150 EVB to be interfaced to the MPC5668EVB This allows for evaluation of the MOST150 INIC with the MPC5668 To use this connector the signals must be routed from the on chip INIC to this connector using the Jumpers detailed in table x below Removing these Jumpers also allow the signals between the INIC and the MCU to be isolated Table 3 23 Signal Control 1 2 D EVB is Routed to the EVB INIC JS7 MEBCLK 2 3 INIC150 MLBCLK is Routed to the MOST150 header J38 PSO 1 2 D EVB PSO is Routed to the EVB INIC 2 3 INIC150 PSO is Routed to the MOST150 header 1 2 D EVB MLBDAT is Routed to the EVB INIC 2 3 INIC150 MLBDAT is Routed to the MOST150 header J40 SDA 1 2 D EVB SDA is Routed to the EVB INIC 2 3 INIC150 SDA is Routed to the MOST150 header J57 PS1 1 2 D EVB 51 is Routed to the EVB INIC 2 3 INIC150 PS1 is Routed to the MOST150 header J58 INT 1
19. of isolation Pullups are also also present on some of these signals These are detailed in the table below Please be aware of this when using I O on ports and H Table 3 20 Pull up Pull down resistors on Ports G and H for Ethernet Physical PG 9 Down GND 2 2kQ PGI7 Up 3 3v SR 1 5kQ PG 12 Down GND 2 2kQ PG 13 Down GND 2 2kQ PG 14 Down GND 2 2kQ PG 15 Down GND 2 2kQ PH 1 Down GND 2 2kQ PH 2 Down GND 2 2kQ PH 3 Down GND 2 2kQ PH 4 Down GND 2 2kQ PH 5 Down GND 2 2kQ PH 6 Down GND 2 2kQ PH 7 Down GND 2 2kQ The VDDES voltage domain that is used by ports and should be set to 3 3v J44 Pos 2 3 when power is applied to the physical interface Power can be removed from the physical interface via J62 Table 3 21 Ehternet Physical Interface Power Supply Enabled J26 The DP4348C Ethernet Physical Interface is powered J62 FITTED D PHY PWR PHY PWR from the 3 3v SR OE REMOVED The DP4348C Ethernet Physical Interface is not powered MPC5668EVBUM D Page 20 of 29 3 10 Most is fitted with range of hardware to support the MOST communication protocol These include SMSC 0581050 U6 INIC interfaced to the MPC5668 pin Media Local Bus MLB interface INIC JTAG port P12 and MLB monitor port J88 Tyco Physical optical transceiver U8 interfaced to the SMSC OS81050 Dual footprint la
20. power is applied to the EVB four green power LED s adjacent to the voltage regulators show the presence of the supply voltages as follows LED 058 Indicates that the 5 0V linear regulator is enabled and working correctly LED 059 Indicates that the 1 5V switching regulator is enabled and working correctly LED DS10 Indicates that the 3 3V switching regulator is enabled and working correctly LED DS11 Indicates that the 5 0V switching regulator is enabled and working correctly If no LED s are illuminated when power is applied to the EVB and the regulators are correctly enabled using the appropriate jumpers it is possible that either power switch SW6 is in the OFF position or that the fuse F1 has blown The fuse will blow if power is applied to the EVB in reverse bias where a protection diode ensures that the main fuse blows rather than causing damage to the EVB circuitry If the fuse has blown check the bias of your power supply connection then replace fuse F1 with a 20mm 500 fast blow fuse MPC5668EVBUM D Page 5 of 29 power supply jumpers are located in the 3 1 5 MCU Supply Routing and Jumpers centre of the EVB ina box J41 442 443 444 445 446 447 448 449 MCU Supply 450 MCU can be operated in 5v and 3 3v modes changing J46 When in 5v mode has internal regulators that can generate the 3 3V supplies for VDDSYN and VDD33 Whilst this is the intended mode of operation for the MCU whe
21. signal is pulled to VIO Posn 1 2 REMOVED Flexray B interface BGE signal is unterminated J28 Flex B FITTED D EN Flexray B interface EN signal is pulled to VIO Posn 3 4 REMOVED Flexray B interface EN signal is unterminated J28 Flex B FITTED D STBEN Flexray B interface STBN signal is pulled to VIO Posn 5 6 REMOVED Flexray B interface STBN signal is unterminated J28 Flex B FITTED D WAKE Flexray B interface WAKE signal is pulled to GND Posn 7 8 REMOVED Flexray B interface WAKE signal is unterminated Notes The flexray physical interfaces are connected to 2 pin molex connectors FlexRAY A 1 25 shrouded 2 pin connectors to connect to the flexray bus as are standard fit on many Freescale development platforms using flexray Important A 40Mhz oscillator is required for the correct operation of the flexray controller Please ensure that the 40Mhz crystal is selected as the system clock or use a 40Mhz external clock source MPC5668EVBUM D Page 19 of 29 MPC5668EVB Users Manual Rev 0 1 The Ethernet circuitry is located in the right edge of 3 9 Ethernet the EVB in an area titled Ethernet The EVB is fitted with a National Semiconductor DP8348C Ethernet physical interface U9 and a Pulse Jack J1011F21PNL RJ45 connector with integrated activity LED s and magnetics J63 The National Semiconductor DP8348C physical interface is connected to the on the MPC5668 This is a fixed connection with no means
22. 1 8 Port H eMIOSZFEG P28 mennan ativan oai dete tese 30 6 1 9 gt Port J eMIOS FEC P29 aet x e ts EEG YN 31 6 1 10 Port RESET MLB Connector 0 3l 6 2 PROTOTYPING AREA AND USER LED S eene 32 APPENDIX A SCHEMATICS MPC5668EVBUM D ii MPC5668EVB Users Manual Rev 0 1 May 2009 Index of Figures and Tables FIGURE 3 1 EVB FUNCTIONAL BLOCKS crt eee ite tette tate ettet i 3 FIGURE 3 2 2 IMM POWER GONNEGTOR rette rtt eret eene TCR 4 FIGURE 3 3 2 LEVER POWER 00 0 4 FIGURE 3 4 POWER SUPPLY ROUTING aa iet ee t Rn eO 6 FIGURE 3 5 EVB GLOCK SELECTION ERE T nene EATA 9 FIGURE 3 6 EVB GEOCK SELECTIONS 10 FIGURE 3 7 EVB RESET BUFFERING SCHEME n nn nn nn 12 FIGURE 3 8 MPC5668 JTAG ONCE CONNECTOR 02 200000 0000 000000000000000 n tn ete etn eee een eene 14 FIGURE 3 9 CAN PHYSICAL INTERFACE CONNECTOR nn nn 15 FIGURE 3 10 RS232 PHYSICAL INTERFACE 2 0400 16 FIGURE 3 11 LIN PHYSICAL INTERFACE CONNECTORS 17 FIGURE 3 12 I
23. 68EVBUM D Page 24 of 29 5 Default Jumper Summary Table The following table details the DEFAULT jumper configuration of the EVB as explained in detail in section 3 Table 5 1 Default Jumper Positions J1 LIN MOLEX No Jumpers J2 LIN MOLEX No Jumpers J3 LIN D FITTED MASTER LIN D Bus Master Mode Enabled J4 LIN D FITTED LIN D RX LIN D RX from MCU Connected to LIN Interface J5 LIN C FITTED MASTER LIN C Bus Master Mode Enabled J6 SCI PWR FITTED Power is applied to the SCI transceiver J7 FlexRAY FITTED CAP A DIS FlexRAY Decoupling CAP Disable J8 FlexRAY FITTED CAP A 015 FlexRAY Decoupling CAP Disable J9 FlexRAY FITTED CAP B DIS FlexRAY Decoupling CAP Disable J10 FlexRAY FITTED CAP B DIS FlexRAY Decoupling CAP Disable J11 External Port No Jumpers Ji2 LIN D FITTED LIND EN LIN D Bus Enable Physical Interface J13 LIND FITTED LIND TX LIN D TX from Connected to LIN Interface J14 LINC FITTED LING TX C TX from Connected to LIN Interface JIB LINC FITTED LIN C RX LIN C RX from MCU Connected to LIN Interface J16 LINC FITTED LINC EN LIN D Bus Enable Physical Interface J17 SCIA FITTED SCIARX MCU RXD A is routed to MAX3223 J18 5 FITTED SCIA TX MCU TXD A is routed to MAX3223 4 FITTED MCU PKA is connected to FlexRay A transceiver TX 19
24. ABLE 3 13 NEXUS DEBUG CONNECTOR PINOUT nentes etn ete esee nne 14 TABLE 3 14 CAN CONTROL JUMPERS J30 J31 J7 nn 15 TABLE 3 15 RS232 GONTROL JUMPERS wits oerte i bete eee 16 TABLE 3 46 LIN GONTROLEJUMPERS 342 n l eee IR AA u 17 TABLE 3 17 FLEXRAY MCU SIGNAL ROUTING JUMPERS J19 J27 sss 18 TABLE 3 18 FLEXRAY POWER CONTROL JUMPERS J25 18 TABLE 3 19 FLEXRAY CONTROL JUMPERS 426 J28 19 TABLE 3 20 PULL UP PULL DOWN RESISTORS ON PORTS G AND H FOR ETHERNET 20 TABLE 3 21 EHTERNET PHYSICAL INTERFACE POWER SUPPLY ENABLED 26 20 TABLE 3 22 POWER SUPPLY CONTROL J35 J36 J55 nnne nenne 21 TABLE 3 23 PHANTOM PORT CONTROL J35 J36 J55 terere tnnt rennen nennen 23 TABLE 421 EVB MGU PIN USAGE etri eer erret n ee onte 24 TABLE 5 1 DEFAULT JUMPER POSITIONS ete esed igne 25 TABLE 6 1 PORT A CONNECTOR PINOUT 17 sse ener 28 TABLE 6 2 RV1 CONNECTION JUMPER_OJ8 n eere etse rises inei sesta eite eate etna etn ese eene 28 TABLE 6 3 PORT B CONNECTOR
25. ADC input MPC5668EVBUM D Page 28 of 29 6 1 2 Port B ADC SPI P18 Table 6 3 Port B Connector Pinout P18 1 PBO AN16 2 PB1 AN17 3 PB2 AN18 4 19 5 PB4 AN20 6 PB5 AN21 7 PB6 AN22 8 PB7 AN23 9 8 AN24 10 PB9 AN25 11 PB10 AN26 12 PB11 AN27 13 PB12 AN28 14 13 29 15 14 AN30 16 PB15 AN31 17 GND 18 GND 6 1 3 Port C ADC FLEXRAY 2 P19 Table 6 4 Port C Connector Pinout P19 2 PC1 4 5 6 PC5 AN37 8 PC7 AN39 10 9 41 12 11 AN43 14 PC13 AN45 16 PC15 AN47 18 GND 6 1 4 Port D CAN 2 SCI P20 Table 6 5 Port D Connector Pinout P20 1 CNTX_A 2 CNRX_A 3 PD2 CNTX_B 4 PD3 CNRX_B 5 PD4 CNTX_C 6 PD5 CNRX_C 7 PD6 CNTX_D 8 PD7 CNRX_D 9 PD8 CNTX_E 10 PD9 CNRX E 11 PD10 CNTX F 12 PD11 CNRX F 13 PD12 TXD A 14 PD13 RXD A 15 PD14 TXD B 16 PD15 TXD B 17 GND 18 GND MPC5668EVBUM D Page 29 of 29 _ 5668 Users Manual Rev 0 1 6 1 5 Port E SCI eMIOS I2C P21 Table 6 6 Port E Connector Pinout P21 1 PEO TXD C 2 PE1 RXD C 3 PE2 TXD D 4 D 5 PE4 TXD_E 6 PE5 RXD_E 7 PE6 TXD_F 8 PE7 RXD
26. BUM D Page 16 of 29 LIN circuitry is located in the top edge of the EVB in an area titled LIN 3 7 LIN Configuration J3 J4 J5 J12 J13 J14 J15 J16 The EVB is fitted with two Freescale MCZ33661EF LIN transceivers The eSCI module incorporates a hardware controlled LIN master and as such the LIN transceivers are connected to the TX and RX signals of SCI C and D For flexibility the LIN transceivers are connected to a standard 0 1 connector P7 for LIN C and P6 for LIN D and a 4 pin molex connector J2 for LIN C and J1 for LIN D at the top edge of the PCB as shown in the figure below For ease of use the 12V EVB supply is fed to pin1 of the connectors and the LIN transceiver power input to pin 2 This allows the LIN transceiver to be powered directly from the EVB supply by simply linking pins 1 and 2 of connector P7 P6 using a 0 1 jumper shunt P7 P8 VDD UNREG LIN VSUP LIN GND Figure 3 11 LIN Physical Interface Connectors Along with the MCU signal routing jumpers J10 J11 there is are jumpers J5 J6 to enable or disable the LIN transceiver and jumpers J1 and J2 which determines if the LIN transceiver is operating in master or slave mode as defined in the table below Table 3 16 LIN Control Jumpers J5 FITTED D LIN C transceiver is configured for LIN Master mode LIN C M REMOVED LIN C transceiver is configured for LIN Slave mode J3 FITTED D LIN D t
27. J48 VDD33 and J50 VDDSYN must be fitted to power the respective MCU pins 3 3V regulator must also be enabled in this case MPC5668EVBUM D Page 7 of 29 3 1 5 1 Changing VDDE 1 4 Voltage Before changing the VDDEx voltage from the default 5 0V setting you need to ensure that this will not impact any of the EVB peripherals that you are using The table below details what EVB peripherals are tied to a particular VDDEx grouping and also the MCU pin operating voltage suitable for that peripheral Table 3 3 VDDE 1 3 Pad Groupings Ethernet Port G and H VDDE3 3 3V CANA and CANB Port D VDDE2 5 0V or 3 3V SCI A and B Port D VDDE2 5 0V or 3 3v LIN C and D Port E VDDE2 5 0V or 3 3v FlexRay Port K VDDE2 5 0V or 3 3V JTAG Dedicated JTAG VDDE2 5 0V or 3 3V Nexus Custom Domain VDDENEX 3 3V 3 1 6 Regulator Power Domains Before disabling any of the EVB regulators it is worthwhile considering if any of the EVB components or peripherals you require will be affected Table 3 4 details a list of the various EVB components and peripherals powered by the regulators Table 3 4 Power Supply Distribution 2 5V MCU VDDEMLB pins Switcher MLB INIC 1 5V Power section of Prototype area 3 3V MCU VDD33 and VDDSYN pins ONLY use when on chip MCU regulator is Switcher disabled MCU VDDEx pins when run in 3 3v mode Oscillator Module U20 MLB INIC RS 232 Transceiver VDDE2 dependant LIN tran
28. LK should be pulled to GND Table 3 12 ONCE NEXUS TCLK Termination Control 1 2 D VDDE JTAG NEXUS TCLK signal is pulled to VDDE2 via J70 10KO PULL 2 3 GND JTAG NEXUS TCLK signal is pulled to GND via 10KQ Note J70 is located to the right of the reset LED s out with the ONCE Nexus connector area MPC5668EVBUM D Page 13 of 29 3 4 1 Debug Connector Pinouts The EVB is fitted with 14 pin JTAG ONCE and 38 pin Nexus debug connectors The following diagram shows the 14 pin JTAG ONCE connector pinout 0 1 keyed header The Nexus module used on the 5668 family uses the JTAG pins for control of the Nexus block along with additional Nexus pins for trace messages Nexus mode is entered by a JTAG sequence whereby the Nexus EVTI pin is sampled on the rising edge of the JTAG TRST pin If the EVTI is asserted on TRST Nexus is enabled TDI 1 TDO3 TCLK 5 7 9 VDDE2 11 RDY 13 2 VSS 4 VSS 6 VSS 8 N C 10 TMS 12 VSS 14 JCOMP Figure 3 8 MPC5668 JTAG ONCE Connector The table below shows the pinout of the 38 pin MICTOR Nexus connector for the MPC5668 Table 3 13 NEXUS Debug Connector Pinout 1 Reserved 2 Reserved 3 Reserved 4 Reserved 5 MDO 9 MCU M5 6 CLKOUT MCU PK9 7 Vendor 2 TP25 8 MDO 8 MCU L5 9 Reset In Reset CCT 10 EVTI MCU M11 11 TDO
29. MCU M3 12 VREF 3 3V Reg 13 MDO 10 MCU M6 14 RDY TP29 15 TCLK 16 MDO 7 MCU K5 17 TMS MCU L3 18 MDOJ6 MCU J5 19 TDI MCU J3 20 MDO 5 MCU J6 21 TRST JCOMP 22 4 MCU H6 23 MDO 11 MCU M7 24 MDO 3 MCU H5 25 Tool l O 3 TP26 26 MDO 2 MCU G5 27 Tool l O 2 TP27 28 MDO 1 MCU F5 29 Tool l O 1 TP28 30 MDO O MCU E5 31 UBATT 12V Vin 32 EVTO MCU M12 33 UBATT 12V Vin 34 MCKO M10 35 Tool l O 0 TP30 36 MSE1 MCU M9 37 VALTREF 3 3V Reg 38 MSEO MCU M8 Note In order to preserve the ability to accurately measure power consumption on the MCU pins the JTAG and Nexus connector reference voltages will be sourced directly from the 5V regulator or from the 12V unregulated input MPC5668EVBUM D Page 14 of 29 MPC5668EVB Users Manual Rev 0 1 May 2009 3 5 CAN Configuration J20 J21 J29 J30 J31 CAN section is located in the top right corner of the EVB in an area marked CAN The EVB has 2x NXP TJA1041T high speed CAN transceiver on the MCU CAN A and CAN B channels These can operate with 5v or 3 3v I O from the MCU This is determined by VDDE2 domain For flexibility the CAN transceiver I O is connected to a standard 0 1 connector and DB9 connector at the top edge of the PCB Connectors P11 and P3A provides the CAN bus level signal interface for CAN A and connector P10 and for CAN B The pinout for these connectors is shown below
30. MCU is diving the reset signal and also to allow connection of non open drain reset inputs a reset in and reset out buffering scheme is implemented as shown in Figure 3 7 Reset In There are possible external sources of reset JTAG Nexus connector reset User reset from user connectors LVI reset circuitry including the reset switch Each of these reset sources is fed into the input of an AND gate and then converted to an open drain output which is directly connected to the MCU reset pin Reset Out The MCU reset pin is buffered to provide a reset out signal capable of driving the reset LED and also multiple devices requiring a reset input The reset buffering scheme is detailed below From JTAG Nexus From TGT MCU RESET From LVI 5v From LVI 3 3v Reset OUT Reset OUT To RED Reset LED BDM Reset In external device reset Figure 3 7 EVB Reset Buffering Scheme Jumper J17 is used to completely disconnect the reset in buffering if desired This is for debug purposes only and should normally be left connected Disconnecting this jumper will mean no external MCU reset can be achieved Table 3 9 Reset Out Control Jumper J68 FITTED D External reset source LVI Debug or Target will be RST IN able to assert MCU reset REMOVED External reset is disabled Not recommended MPC5668EVBUM D Page 12 of 29 3 3 3 Reset Boot Configuration J69 The MPC5668 has a si
31. MPC5568EVBUM D lutum paran CAN PHYSICAL INTERFACE 2 Page A 9 May 2009 MPC5668EVB Users Manual Rev 0 1 SCI and LIN PHYSICAL INTERFACES MPC5568EVBUM D Page A 10 May 2009 MPC5668EVB Users Manual Rev 0 1 MPC5568EVBUM D passa mam Bote Plexray is Alternate function of Portk 3 8 Pins E ogi AE 1 FLEXRAY PHYSICAL INTERFACE Page A 11 May 2009 MPC5668EVB Users Manual Rev 0 1 MPC5568EVBUM D May 2009 sapan lt x x ETHERNET PHYSICAL INTERFACE AND RJ45 DE Page A 12 MPC5668EVB Users Manual Rev 0 1 MPC5568EVBUM D POWER SUPPLY DECOUPLING as per KANIS ksr SXYVLSOOWASDAT TS munus MSAK PINETE m TAGAN 3 4 pen pred om we uy LEO i 13 2009 MPC5668EVB Users Manual Rev 0 1 Tear TEAANECT Place near 0581050 twm MOST PHYSICAL INTERFACE Layout Guidelines per MPCSS10ADAPMLB LAY 23554 MOST Optical should be c Place R68 next to OS81050 se to OS81050 Place R75 next to MOST Optical
32. NC5668 JTAG CONNECTOR nsn 21 FIGURE 3 13 MLB MONITOR CONNECTOR n nn 21 TABLE 3 1 REGULATOR POWER 5 0 0 5 TABLE 3 2 POWER SUPPLY 2 0 50 7 TABEE 9 3 VDDE 1 3 PAD GROUPINGS neret EO 8 TABLE 3 4 POWER SUPPLY DISTRIBUTION c cccccccccsccssccssecssccsssccsscssscessccsscesesessccssscsssesssessscssscesscsssccssecssscsscesecesssensenes 8 TABLE 3 5 CLOCK SOURCE JUMPER SELECTION n ete ete en ensi n 9 TABLE 3 6 32KHz CRYSTAL JUMPER 10 TABLE 3 7 LVI MONITOR THRESHOLD VOLTAGES 11 TABLE 358 EVI GONTROEJUMPERS nee tite Greta te eti eri etel un Le a ed te etes 11 TABLE 3 9 RESET OUT CONTROL JUMPPFR n anna 12 TABLE S 10 BOOTGEG GONTROLD z 5 5 att aT tete SG edet 13 TABLE 3 11 JTAG NEXUS TARGET RESET ROUTING nn 13 TABLE 3 12 ONCE NEXUS TCLK TERMINATION trennen ete erede nee 13 T
33. ONFIGURATION J6 J17 18 J23 424 16 3 7 LIN CONFIGURATION 17 J19 TG i o ret ERE HE waa 17 3 8 FLEXRAY CONFIGURATION J19 J27 J25 J26 428 18 3 9 ETHERNET ero E NR DATO medendi ERE A OE tI e UI 20 3 10 MEB AND MOST zB ERROR Em d ER UR Red 21 3 11 PHANTOM PORTS J76 J77 478 79 J80Y tn ete e ah PE RERO sed 23 MCU PIN USAGE MAP u 24 DEFAULT JUMPER SUMMARY TABLE 25 USER CONNECTOR DESCRIPTIONS siccsevccscdcccsnscscectucecesscesotecessacestcacevecscadeasnentucesesededessaonsasteetebscecdbessasasicesstes 28 6 1 1 Port A ADC Connector 486 J73 and J74 U n nn 28 6 2 PoItBLADG io ute t p RESERVE EGER US SEIEN EVE RE 29 6 1 3 Pot CZADC FEEXRAY I2G PI Ni s eie e ie rito 29 6 1 4 Port DZ CAN S126 2 iss ee d eee eere 29 6 1 5 Port E SCI7eMIOS7T2G P21 eor e Pd ONE xe Ee EE eR 30 6 56 Pot EZ DSPh P26 s ded e OGGI AAA E ER 30 6 1 7 Port G DSPI eMIOS FEC P27 a aa nalaman nnne rennen trennt netten 30 6
34. PSO is Routed to the EVB INIC J39 MLBDAT 1 2 EVB MLBDAT is Routed to the EVB INIC J40 SDA 1 2 EVB SDA is Routed to the EVB INIC J41 VDDE4 1 2 5 0v MCU VDDE4 is powered from 5v J42 VDDE2 1 2 5 0v MCU VDDE2 is powered from 5v 443 VDDE1 1 2 5 0v MCU VDDE1 is powered from 5v 444 VDDE3 1 2 5 0v MCU VDDE3 is powered from 5v J45 VDDEMLB 1 2 2 5V MCU VDD pin is powered from 1 5v switching regulator J46 VRC 1 2 5V VRC is supplied from the 5V switching regulator J47 VRCSEL 1 2 INT 3 3 V internal voltage regulator enabled 5 V mode J48 VDD33 REMOVED MCU VDD33 pin is powered from switching regulator J49 VDDA FITTED MCU VDDA is powered from 5V linear regulator J50 VDDSYN REMOVED MCU VDDSYN pin is powered from switching regulator MPC5668EVBUM D Page 26 of 29 451 REMOVED Do not route CAN F to Prototype Area J52 CAN D REMOVED Do not route CAN D to Prototype Area J53 CAN E REMOVED Do not route CAN E to Prototype Area J54 CAN C REMOVED Do not route CAN C to Prototype Area J55 INIC PWR FITTED 2 5v PWR 2 5v is applied to VDDC1 and VDDC2 J56 INIC RST FITTED RST INIC Reset is connected to PBO J57 INIC PS1 1 2 EVB MLB PS1 is Routed to the EVB INIC J58 INIC INT 1 2 EVB INT is Routed to the EVB INIC J59 INIC SCL 1 2 EVB SCL is Routed to the EVB INIC J60 INIC BOOT 1 2 EVB INIC Boot pin is pulled up to 2 5v Rail 461 MCU CLK 1 2 Clock is 2 62 PWR FITTED
35. V switching regulator is disabled for any reason the LVI circuit will attempt to assert MCU Reset signal Jumper shunts on jumper J20 position 1 2 and 3 4 must be removed in this situation This will also leave the reset switch SW5 inoperative Ifthe 3 3V regulator is disabled the shunt on jumper J20 position 3 4 must be removed to prevent the LVI asserting reset 3 3 1 Reset LEDs There are two reset LED s DS2 AMBER and DS3 RED placed adjacent to the EVB RESET switch to indicate the RESET status of the EVB and MCU LED DS3 titled RST will illuminate if the MCU itself issues a reset In this condition LED DS2 will not illuminate LED 052 titled USR will illuminate when one of the following external hardware devices issues a reset to the MCU LVI circuitry either an under voltage detection or the reset switch is being pressed There is a reset being asserted from the user connectors or from the daughter card There is a reset being driven from the Nexus or JTAG debug probe Note that LED DS3 MCU Reset will also illuminate during an external user reset MPC5668EVBUM D Page 11 of 29 3 3 2 Reset Buffering Scheme The MPC5668 family has a single reset pin This single pin functions as a dual purpose input output signal providing Reset In and Reset Out functionality There is a lot of circuitry on the EVB that has access to the reset pin In order to reduce the loading on the pin when the
36. _F 9 PE8 TXD_G 10 RXD G 11 10 TXD H 12 PE11 RXD H 13 PE12 TXD J 14 PE13 RXD J 15 PE14 SCL A 16 PE15 SDA A 17 GND 18 GND 6 1 6 Port F DSPI P26 Table 6 7 Port F Connector Pinout P26 1 PFO SCK A 2 PF1 SOUT A 3 PF2 SIN A 4 PCS A 0 5 4 SCK 6 SOUT B 7 PF6 SIN B 8 PF7 PCS 0 9 PF8 SCK C 10 PF9 SOUT C 11 PF10 SIN C 12 11 PCS C 0 13 PF12 SCK D 14 PF13 SOUT D 15 14 SIN D 16 PF15 PCS 00 17 GND 18 GND 6 1 7 Port G eMIOS FEC P27 Table 6 8 Port F Connector Pinout P27 1 2 PCS A 5 3 4 PCS D 2 5 PCS D 3 6 PG5 PCS D 4 7 PG6 PCS C 1 8 PG7 PCS C 2 9 PG8 eMIOS 7 10 PG9 eMIOS 6 11 PG10 eMIOS 5 12 PG11 eMIOS 4 13 PG12 eMIOS 3 14 PG13 eMIOS 2 15 PG14 eMIOS 1 16 PG15 eMIOS 0 17 GND 18 GND 6 1 8 Port H eMIOS FEC P28 Table 6 9 Port Connector Pinout P28 1 PHO eMIOS 31 2 PH1 eMIOS 30 3 PH2 eMIOS 29 4 PH3 eMIOS 28 5 PH4 eMIOS 7 6 PH5 eMIOS 26 6 eMIOS 25 8 PH7 eMIOS 24 9 PH8 eMIOS 23 10 PH9 eMIOS 22 11 PH10 eMIOS 21 12 11 eMIOS 20 13 PH12 eMIOS 19 14 PH13 eMIOS 18 15 PH14 eMIOS 17 16 PH15 eMIOS 16 17 GND 18 GND MPC5668EVBUM D Page 30 of 29 6 1 9 J eMIOS 29 Table 6
37. g sections on how to correctly configure the board Failure to correctly configure the board may cause irreparable component MCU or EVB damage MPC5668EVBUM D Page 2 of 29 3 Configuration This section details the configuration of each of the EVB functional blocks Throughout this document all of the default jumper and switch settings are clearly marked with D and are shown in blue text This should allow a more rapid return to the default state of the EVB if required Note that the default configuration for 3 way jumpers is a header fitted between pins 1 and 2 On the EVB 2 way and 3 way jumpers have been aligned such that Pin 1 is either to the top or to the left of the jumper On 2 way jumpers the source of the signal is connected to Pin 1 The EVB has been designed with ease of use in mind and has been segmented into functional blocks as shown below Detailed silkscreen legend has been used throughout the board to identify all switches jumpers and user connectors MOST and MLB Serial SCI CAN Prototype Area Ethernet S aa m aCpn Xxxrx REV ACH XEXXX REV X KOSA YA B 2009 FREEELALE 4 Pamei Routing 1 i User LEDs n H i onnectors Power LVI Voltage umpers i switches MN eee Regulators Circuitry and NEKUS SMA In Out User Potentiometer Figure 3 1 EVB Functional Blocks
38. igned intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part Learn More For more information about Freescale products please visit www freescale com Freescale and the Freescale logo are trademarks of Freescale Semiconductor All other product or service names are the property of their respective owners Freescale Semiconductor 2009 All Rights Reserved MPC5668EVBUM D i MPC5668EVB Users Manual Rev 0 1 May 2009 4 5 6 INDEX INERODUCTION mm N 1 EVB FEATURES 2 EE
39. ing the slide switch to the left towards connector P23 will turn the EVB off MPC5668EVBUM D Page 4 of 29 3 1 3 Regulator Power Jumpers 442 J44 445 and 446 The Power supply control jumpers are located adjacent to the respective regulators As mentioned above the EVB has four voltage regulators on board 2 5V switching regulator 017 to supply the MCU MLB Pads voltage and the SMSC 06 8 8V switching regulator U18 for EVB peripherals and MCU regulator logic and 5 0V switching regulator U19 for the MCU regulator and I O and EVB peripherals 5 0V linear regulator U14 for the MCU ADC power supply All of the regulators have the option of being disabled if they are not required The table below details the jumper configurations for enabling and disabling the regulators By default all of the regulators are enabled Table 3 1 Regulator Power Jumpers FITTED DISABLE 2 5V switching regulator output is J81 2 5V REMOVED D 2 5V switching regulator output is Enabled FITTED DISABLE B UM regulator output is J82 3 3V is REMOVED 0 3 3V switching regulator output is Enabled FITTED DISABLE M d regulator output is J83 5 0V Pra m REMOVED 0 5 0V switching regulator output is Enabled FITTED D ENABLE 5 0V linear regulator output is Enabled REMOVED 5 0V linear regulator output is Disabled 3 1 4 Power Status LED s and Fuse When
40. lator output is Enabled J82 2 5v REMOVED DISABLE 2 5v switching regulator output is Enabled J83 3 3v REMOVED DISABLE 3 3v switching regulator output is Enabled J84 5 0v REMOVED DISABLE 5 0v switching regulator output is Enabled J85 U20 PWR FITTED EVB oscillator module U20 is powered 286 RV1 FITTED from variable resistor RV1 is applied to J87 OSC SEL 1 2 MOD Daughter card EXT CLK is routed from U20 MPC5668EVBUM D Page 27 of 29 6 User Connector Descriptions This section details the pinout of the EVB user connectors The connectors are 0 1 inch pitch turned pin headers and are located to the right hand side of the EVB Pins are grouped by port functionality and the PCB legend shows the respective port number adjacent to each pin 6 1 1 Port A ADC Connector J86 RV1 J73 and J74 Table 6 1 Port A Connector Pinout P17 1 PAO ANO 2 PA1 AN1 3 PA2 AN2 4 5 4 AN4 6 PAS AN5 7 AN6 8 AN7 9 PA8 AN8 10 PA9 AN9 11 PA10 AN10 12 PA11 AN11 13 PA12 AN12 14 PA13 AN13 15 PA14 AN14 16 PA15 AN15 17 GND 18 GND To provide a quick means of supplying input to the ATD Analogue To Digital converter a 2KQ variable resistor RV1 will is connected between P5V and GND with the output centre tap connected to PAO ANO via jumper J86 By removing jumper J86 PAO is disconnected from the variable resistor and can function as a
41. n VRC 5v the EVB allows the internal MCU regulators to be disabled by changing VRCSEL to EXT and applying external voltages to the VDDSYN and VDD33 inputs When in 3 3v mode VDDSYN and VDD33 inputs must always be supplied externally The VDDE 1 4 pins control the pad voltages over 4 groupings of pads see the MCU reference manual for details Jumpers J41 J34 allow the VDDEx pins to be connected to the 5 0v or 3 3V switching regulators The VDDEMLB domain can be 3 3 or 2 5v selectable by J45 MCU Power 12V J49 5V Linear 1 o e VDDA J46 5V Switcher VRC 33V J43 Switcher VDDE1 2 5V J42 Switcher VDDE2 J44 VDDES3 J41 VDDE4 J45 VDDEMLB VRCSEL 4 J50 1 INTernal VDDSYN 0 MEG VDD33 J48 VRCSEL Figure 3 4 Power Supply Routing MPC5668EVBUM D Page 6 of 29 Table 3 2 Power Supply 5 0V J49 VDDA FITTED D MCU VDDA is powered from 5V linear regulator REMOVED MCU VDDA User powered from J49 Pin 2 5 0V J46 1 2 D 5V VRC is supplied from the 5V switching regulator 3 3V VRC 2 3 3 3v VRC is supplied from the 3 3V switching regulator J47 1 2 D INT 3 3 V internal voltage regulator enabled 5 V mode VRCSEL 2 3 EKT 3 3 V supplied erternal 3 3 V mode J43 1 2 0 5 0 MCU VDDE1 is powered from 5v VDDE1 2 3 3 3V VDDE 1 is powered from 3
42. ngle boot configuration pin BOOTCFG which determines the boot location of the MCU based on the state of the pin at POR Power On Reset This is shown in the table below Table 3 10 BOOTCFG Control FLASH MCU boots from internal flash 1 2 D 8 SERIAL MCU boots from external serial source J69 BOOT CFG 2 ONCE and NEXUS 3 4 ONCE and Nexus Configuration 432 J70 connectors are located at the left hand edge of the EVB The EVB supports a standard ONCE cable with a 14 pin 0 1 walled header footprint There is also a 38 pin MICTOR connector for Nexus debug Nexus debug is only supported when using a 256 MPC5668 There are two generic jumpers associated with both the ONCE and Nexus as detailed below Some debug probes have the ability to assert and also monitor the state of the MCU reset line This is not possible when the reset signal is buffered so a jumper J32 is included to allow routing the debug reset signal direct to the MCU reset pin or via the EVB Reset In buffering Table 3 11 JTAG NEXUS Target Reset Routing 1 2 D BUF JTAG reset signal is buffered to MCU RESET pin J32 JRST connected to the MCU circuitry 2 3 DIR JTAG reset signal is connected direct to MCU RESET pin Some debug manufacturers specify whether the debug TCLK signal is pulled low or high Jumper J70 provides the ability to select whether is pulled to GND or VDDE2 For low power operation TC
43. normal temperature specified components 70 MPC5668EVBUM D Page 1 of 29 _ 5668 Users Manual Rev 0 1 2 EVB Features The EVB provides the following key features Note MCU Socket supporting the 208BGA production package and the 256BGA development package Single 12 14V external power supply input with on board regulators to provide all of the necessary EVB and MCU voltages Power may be supplied to the EVB via a 2 1mm barrel style power jack or a 2 way level connector 12V operation allows in car use if desired Flexible on board power supply configuration with the option to bypass the internal MCU regulators if desired Master power switch and regulator status LED s Regulators connected to the ADC to allow monitoring User reset switch with reset status LED s User configurable Low Voltage Inhibit to monitor the status of the 3 3V and 5V regulators Control of the BOOTCFG status via a dedicated jumper Flexible MCU clocking options 40MHz Oscillator Crystal 32Khz Watch Crystal connector to allow external clock support 8Mhz Oscillator circuit SMA connector on MCU CLKOUT signal for easy access Standard 14 pin ONCE debug connector and 38 pin MICTOR Nexus connectors All MCU signals are accessible on port ordered groups of 0 1 pitch headers DSPI A signals can be routed to a set of shift registers to allow a 32 bit phantom port to be created SCI channels A and B can be routed to a standard
44. ntation Figure 3 10 RS232 Physical Interface Connector The MPC5668 eSCI also provides hardware LIN master capability which is supported on the EVB via LIN transceivers Jumpers J17 J18 J23 and J24 are provided to isolate the MCU SCI signals from the RS232 interface as described below There is also a global power jumper J9 controlling the power to the RS232 transceiver Table 3 15 RS232 Control Jumpers J6 FITTED D Power is applied to the MAX3223 transceiver SCI PWR REMOVED No power is applied to the MAX3223 transceiver FITTED D MCU TXD A is routed to MAX3223 de BCEA REMOVED TXD A signal is disconnected from CAN LIN I FITTED D MCU RXD A is routed via MAX3223 J17 SCI A REMOVED RAD MCU RXD A signal is disconnected from CAN LIN FITTED D MCU TXD B is routed via MAX3223 423 SCI B REMOVED TXD MCU TXD B signal is disconnected from CAN LIN wA FITTED D EXD MCU RXD B is routed via MAX3223 J24 SC B REMOVED MCU RXD B signal is disconnected from CAN LIN The default configuration enables SCI A and SCI B channels RS232 compliant interfaces with no hardware flow control are available at DB9 connector P1 If the MCU is configured such that SCI A or SCI B is set as a normal I O port then the relevant jumpers must be removed to avoid any conflicts occurring If required jumper J6 can be used to completely disable the SCI transceiver MPC5668EV
45. ransceiver is configured for LIN Master mode LIN D M REMOVED LIN D transceiver is configured for LIN Slave mode J16 FITTED D The LIN C transceiver is enabled LIN C EN REMOVED The LIN C transceiver is disabled J12 FITTED D The LIN D transceiver is enabled LIN D EN REMOVED The LIN D transceiver is disabled FITTED D MCU TXD C is routed to LIN Physical J14 SCI C REMOVED TAD MCU TXD C signal is disconnected LIN Physical FITTED D MCU RXD C is routed to LIN Physical J15 SCI C REMOVED RAD MCU RXD C signal is disconnected LIN Physical FITTED D MCU TXD D is routed to LIN Physical J14 SC D REMOVED MCU TXD D signal is disconnected LIN Physical FITTED D MCU RXD D is routed to LIN Physical J15 SCFD REMOVED MCU RXD D signal is disconnected LIN Physical Note Jumpers J3 J5 do NOT route power to LIN transceivers they only control an enable line on the LIN device Power to the LIN transceiver is supplied via connectors P7 P8 Pin 2 The Default LIN configuration is with the module enabled in master mode LIN slave mode can be enabled by removing jumpers J3 J5 MPC5668EVBUM D Page 17 of 29 MPC5668EVB Users Manual Rev 0 1 The Flexray circuitry is 3 8 FlexRAY Configuration located in the top edge of J19 J27 J25 J26 J28 EVB is fitted with 2 FlexRAY physical interfaces connected to MCU FlexRAY channels and B Jumpers J19 and J27 are provided to route the
46. respective MCU signals to the physical interfaces as described below Table 3 17 Flexray MCU Signal Routing Jumpers 419 J27 J19 Flex A FITTED D TX MCU PK4 is connected to Flexray A transceiver TX Posn 1 2 REMOVED MCU PK4 is not connected to Flexray A transceiver TX J19 Flex A FITTED D TXEN MCU PKB is connected to Flexray A transceiver TXEN Posn 3 4 REMOVED MCU PKS is not connected to Flexray A transceiver TXEN J19 Flex A FITTED D MCU is connected to Flexray A transceiver RX Posn 5 6 REMOVED is not connected to Flexray A transceiver RXEN J27 Flex B FITTED D TX MCU 7 is connected to Flexray B transceiver TX Posn 1 2 REMOVED MCU is not connected to Flexray B transceiver TX J27 Flex B FITTED D TXEN MCU 8 is connected to Flexray B transceiver TXEN Posn 3 4 REMOVED MCU 8 is not connected to Flexray transceiver TXEN J27 Flex B FITTED D RX MCU PK6 is connected to Flexray transceiver RX Posn 5 6 REMOVED MCU PK6 is not connected to Flexray transceiver RXEN The power to the Flexray physical interface is controlled via jumper J25 to allow disconnection if required The Flexray physical interface is capable of interfacing with MCU voltages of 3 3V or 5 0V as defined by the voltage supplied VDDE2 via jumper J42 Table 3 18 Flexray Power Control Jumpers J25 J25 Flex PWR FITTED D 12V 12V Flexray circuit
47. ry is powered from main 12V input Posn 1 2 REMOVED 12V Flexray circuitry is not powered J25 Flex PWR FITTED D 5 5V Flexray circuitry is powered from 5 0V switching reg Posn 3 4 REMOVED 5V Flexray circuitry is not powered J25 Flex PWR FITTED D VIO VIO Flexray circuitry is powered from VDDE2 Posn 5 6 REMOVED VIO Flexray circuitry is not powered The flexray interface has 4 pins which are used for configuration and are pulled high or low controlled by a jumper as described in the table below By default all of the jumper headers are fitted Please consult the Flexray physical interface specification before changing any of these jumpers MPC5668EVBUM D Page 18 of 29 _ 5668 Users Manual Rev 0 1 J26 Flex A Table 3 19 Flexray Control Jumpers J26 J28 FITTED D Flexray A interface BGE signal is pulled to VIO Posn 1 2 REMOVED BGE Flexray A interface signal is unterminated J26 Flex A FITTED D EN Flexray A interface EN signal is pulled to VIO Posn 3 4 REMOVED Flexray A interface EN signal is unterminated J26 Flex A FITTED D STBEN Flexray A interface STBN signal is pulled to VIO Posn 5 6 REMOVED Flexray A interface STBN signal is unterminated J26 Flex A FITTED D WAKE Flexray A interface WAKE signal is pulled to GND Posn 7 8 REMOVED Flexray A interface WAKE signal is unterminated J28 Flex B FITTED D BGE Flexray B interface BGE
48. sceiver VDDE2 dependant supply for Flexray interface when VIO is 3 3V LVI circuitry 3 3V Power section of Prototype area 5 0V MCU VDDEx 5v mode VPP and VDDR pins Switcher LVI circuit main power affecting Reset Switch Reset In Reset Out logic Reset configuration circuitry User LED s and Switches RS 232 Transceiver VDDE2 dependant LIN transceiver VDDE2 dependant CAN transceivers FlexRay transceivers 5 0V Power section of Prototype area JTAG and Nexus connectors 5 0V MCU VDDA pin Linear LVI circuit monitor MPC5668EVBUM D Page 8 of 29 MCU clock control jumpers are located close to 3 2 MCU Clock Control crystal oscillator modules 3 2 1 Main Clock Selection J85 J87 J61 and J66 The EVB supports three possible MCU clock sources 1 The local 40MHz ALC pierce oscillator circuit 2 An oscillator module on the EVB U20 driving the MCU EXTAL signal 3 An external clock input to the EVB via the SMA connector P32 driving the MCU EXTAL signal The clock circuitry is shown in the diagram below Please refer to the appropriate daughter card user manual for specific jumper numbers and circuitry 3 3V SR EVB Clock Circuitry Oscillator Module 820 Local Crystal Circuit Y2 Figure 3 5 EVB Clock Selection Table 3 5 Clock Source Jumper Selection FITTED D EVB oscillator module U20 is powered
49. ted to CAN controller Posn 3 4 REMOVED MCU CNRX B is NOT routed to CAN controller J20 amp J21 FITTED D WAKE CAN Transceiver WAKE is connected to GND Posn 1 2 REMOVED WAKE is not connected and available on Pin 2 J20 amp J21 FITTED D CAN Transceiver STB is connected to 5v Posn3 4 REMOVED STB STB is not connected and available on Pin 4 420 amp 421 FITTED D ER CAN Transceiver is Enabled Posn 3 4 REMOVED EN is not connected and available on Pin 6 Access to the Error and inhibit signals from the transceivers is provided on J33 and J34 The prototyping area provides features that allow for additional CAN interfaces to be added to the EVB Please see Section 6 2 for details Notes Care should be taken when fitting the jumper headers as they can easily be fitted in the incorrect orientation MPC5668EVBUM D Page 15 of 29 RS232 circuitry 3 6 RS232 Configuration 46 417 J18 423 J24 214 titled 5 EVB has single MAX3223 RS232 transceiver device providing RS232 signal translation for the SCI channels and B Each of the two RS232 outputs from the MAX232 device is connected to a DB9 connector allowing a direct RS232 connection to a PC or terminal Connector P1A provides the RS232 level interface for MCU SCI A and P1B for MCU SCI B The pinout of these connectors is detailed below Note that hardware flow control is not supported on this impleme
50. terface WAKE signal is pulled to GND Posn 7 8 J27 Flex B FITTED TX MCU is connected to Flexray B transceiver TX Posn 1 2 J27 Flex B FITTED TXEN MCU 8 is connected to Flexray transceiver TXEN Posn 3 4 J27 Flex B FITTED RX MCU PK6 is connected to Flexray B transceiver RX Posn 5 6 J28 Flex B FITTED BGE Flexray B interface BGE signal is pulled to VIO Posn 1 2 J28 Flex B FITTED EN Flexray B interface EN signal is pulled to VIO Posn 3 4 J28 Flex B FITTED STBEN Flexray B interface STBN signal is pulled to VIO Posn 5 6 J28 Flex B FITTED WAKE Flexray B interface WAKE signal is pulled to GND Posn 7 8 J29 CAN B FITTED TX is connected to CAN controller C Posn 1 2 J29 CAN B FITTED RX MCU is connected to CAN controller C Posn 3 4 J30 CAN FITTED VCC is applied to both CAN transceivers Posn 1 2 J30 CAN FITTED VIO Power is applied to both CAN transceivers VIO Posn 3 4 J31 CAN A FITTED TX is connected to CAN controller A Posn 1 2 J31 CAN A FITTED RX MCU CNRX A is connected to CAN controller A Posn 3 4 1 2 JTAG reset signal is buffered to MCU RESET pin J32 JRST BUF connected to the MCU Reset In circuitry J33 CAN Status No Jumpers J34 CAN Status No Jumpers J35 FITTED 3 3v PWR 3 3v is applied to VDDP1 and VDDP2 of the INIC J36 FITTED 2 5v PWR 2 5v is applied to VDDA1 and VDDA2 J37 MLBCLK 1 2 EVB MLBCLK is Routed to the EVB INIC J38 PSO 1 2 EVB
51. y to the regulator outputs and not connected to the jumpered MCU supply There are 4 active low user LED s DS4 DS5 DS6 and DS7 These are driven by connecting a logic 0 signal to the corresponding pin on 0 1 header P15 user LED s There are 4 active high pushbutton switches SW2 SW3 SW4 and SW5 which will drive 5V onto the respective pins on 0 1 connector P16 when pressed The switch outputs are pulled to GND with a 10K resistor network MPC5668bEVBUM D Page 32 of 29 MPC5668EVB Users Manual Rev 0 1 May 2009 Appendix A EVB Schematics MPC5668 Evaluation Board Table of Contents Revisions MCU Signals 2 4 ut Linear and Switchers 3 and Routing Sheet 4 Circuitry Sheet 5 and Boot Configuration Sheet 6 JIAG and Nexus Connectors 7 8 CAL INTERFACE HIGH SPEED CAL INTERFACE 2 MODULES SCI and LIN PHYSICAL INTERFACES FLEXRAY PHYSICAL INTERFACE Sheet 11 ETHERNET PHYSICAL INTERFACE AND 45 MLB INIC Sheet 13 MOST PHYSICAL INTERFACE IERMINATION RESISTORS PORT CIRCUITRY USER CONNECTORS User Peripherals Inc Prototyping MPC5568EVBUM D Page A 1 MPC5668EVB Users Manual Rev 0 1 May 2009 mpe Suca yrsc 5668 256 SIGNALS ERSTE SE DILE x MPC5568EVBUM D Page A 2 MPC5668EVB Users Manual Rev 0 1
52. yout to allow the SMSC OS81050 to be replaced with the smaller ROM alternative 40 Pin header to allow the EVB to be interfaced to the MOST 150 EVB from SMSC Power Jumpers on the EVB are configured to allow the EVB to supply power to both the ROM and Flash versions of the SMSC OS81050 INIC that are supported by the dual footprint on the EVB By default the Flash version of the OS81050 is fitted to the EVB The jumpers also allow power to be removed from the INIC The power supply jumpers are detailed below All Power supplies domains referred to in this table are for the Flash based INIC Please refer to the schematics to see how this affects the supply domains of the ROM INIC if it has been fitted Table 3 22 INIC Power Supply Control J35 J36 J55 PE FITTED D 33vis applied to VDDP1 and VDDP2 of the INIC REMOVED No 3 3v power is applied to VDDP1 VDDP2 FITTED D 2 5v is applied to VDDA1 and VDDA2 498 REMOVED 29 No power is applied to VDDAT and VDDA2 FITTED D 2 5v is applied to VDDC1 and VDDC2 s REMOVED 5VPWR power is applied to VDDC1 and VDDC2 The Pin out for the INIC JTAG connector filled to the EVB is show in Figure x below e e 2vss N C3 4INIC BOOT VSS5 e 63 3v TDI7 e 8TCK 3 3V9 e e 10 VSS 11 12 RST N C 13 14 TMS Figure 3 12 INC5668 JTAG Connector The INIC pins MLBDI MLBSI
Download Pdf Manuals
Related Search