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78K/II SERIES 8-BIT SINGLE-CHIP UM

1. Mnemonic Operands Bytes Internal ROM high speed fetch External ROM fetch Internal Ram SFR 72781 PRAM SFR ROM ROM SUBC A byte 2 2 6 saddr byte 3 4 8 9 11 sfr byte 4 10 10 14 18 nr 2 T 3 A saddr 2 5 6 7 A sfr 3 7 7 10 11 saddr saddr 3 4Note 1 QNote 2 QNote 1 11 2 A mem 2 4 See Table 7 6 4 4 for details A amp mem 3 5 AND A byte 2 2 6 saddr byte 3 4 8 9 11 sfr byte 4 10 10 14 18 nr 2 7 3 A saddr 2 5 6 7 A sfr 3 7 7 10 11 saddr saddr 3 4Note 1 QNote 2 QNote 1 118062 A mem 2 4 See Table 7 6 4 4 for details A amp mem 3 5 OR A byte 2 2 6 saddr byte 3 4 8 9 11 sfr byte 4 10 10 14 18 nr 2 7 3 EM A saddr 2 5 6 7 A sfr 3 7 7 10 11 saddr saddr 3 4Note 1 QNote 2 QNote 1 11 2 A mem 2 4 See Table 7 6 4 4 for details A amp mem 3 5 Continued Notes 1 IRAM for both saddr and saddr 2 SFR for both saddr and saddr 127 78K ll SERIES USER S MANUAL Clock cycles
2. Mnemonic Operands Bytes Internal ROM high speed fetch External ROM fetch Internal Internal ROM IRAM SFR ROM SFR XOR A byte 2 2 6 saddr byte 3 4 8 9 11 sfr byte 4 10 10 14 18 nr 2 7 3 A saddr 2 5 6 7 A sfr 3 7 7 10 11 saddr saddr 3 4Note 1 QNote 2 QNote 1 11 1 2 A mem 2 4 See Table 7 6 4 4 for details A amp mem 3 5 CMP A byte 2 2 6 sadar byte 3 3 5 9 11 sfr byte 4 7 7 14 15 nr 2 7 3 A saddr 2 5 6 T A sfr 3 7 7 10 11 saddr saddr 3 3Note 1 7Note 2 QNote 1 Note 2 A mem 2 4 See Table 7 6 4 4 for details A amp mem 3 5 Notes 1 IRAM for both saddr and 2 128 SFR for both saddr and CHAPTER 7 INSTRUCTION SET 4 16 bit operation instructions ADDW SUBW CMPW Clock cycles Mnemonic Operands Bytes Internal ROM high speed fetch External ROM fetch py IRAM PRAM SFR IRAM PRAM SFR EMEM ADDW AX word 3 4 9 AX rp 2 6 B 8 saddrp 2 7 11 B 9 13 lt 3 13 16 SUBW AX word 3 4 9 AX rp 2 6 8 u AX saddrp 2 7 11 9 13
3. 186 XORT ER 187 188 CERT 189 CE 190 CALL 055 192 193 CALL 194 BRK 195 ale 196 197 198 249 78K ll SERIES USER S MANUAL Stack manipulation instructions SIG qaya ataqa uya na uapa MOVW SP eee DEGW SP Unconditional branch instructions CPU control instructions MOV yt SEL aquya aqha amana aid 250 APPENDIX INDEX OF INSTRUCTIONS MNEMONICS IN ALPHABETICAL ORDER A ae 149 ERE 165 150 167 158 INCW SP 203 ADIBA 181 ADJBS u 182 153 ANT a 185 MEN EON 144 MOV STBC byte oinn 217 B BN EO 184 147 208 MOVW SP 202 210 MOVW SP 202 213 162 208 NV 209 BNE 211 209
4. 94 CHAPTER 1 78K ll SERIES FEATURES 1 2 OUTLINE OF uPD78214 SUB SERIES PRODUCTS uPD78212 78213 78214 78P214 78212 A 78213 A 78214 A 78P214 A 1 2 1 Features Instruction cycle 333 ns uPD78212 78214 78P214 500 ns uPD78213 On chip memory ROM Mask ROM 16K bytes uPD78214 8K bytes uPD78212 Not incorporated uPD78213 PROM 16K bytes uPD78P214 RAM 512 bytes 384 bytes uPD78212 only O pins 54 36 uPD78213 only On chip 8 bit converter 8 analog inputs Timer counters 16 bits x 1 8 bits x 3 Serial interface Independent on chip UART and CSI e wPD78212 A 78213 A 78214 A 78P214 A Special quality grade products of 78212 78213 78214 78P214 1 2 2 Applications Standard products OA equipment including printers typewriters PPCs facsimile etc electronic musical instruments inverters cameras etc Special products Automotive electronic equipment combustion control disaster crime preven tion unit 78K ll SERIES USER S MANUAL 1 2 3 Ordering Information and Quality Grade 1 Ordering information Ordering code uPD78212CW xxx uPD78212GC xxx AB8 uPD78212GJ xxx 5BJ uPD78213CW uPD78213GC AB8 uPD78213GJ uPD78213GQ 36 uPD78213L uPD78214CW xxx uPD78214GC xxx AB8 uPD78214GJ xxx 5BJ uPD78214GQ xxx 36 uPD78214L xxx uPD78P214CW uPD78P214GC AB8 uPD78P214GJ uPD78P214GQ 36 uPD78P214L
5. sua 8 Sd z jeuueuo 4o unoo J8uul Jejunoo9 19UJ siia 91 L SFR address data bus eoepelul eues pexoo o ayes pneg Cz GdLNI Od LNI e qeuuueJ60Jg E INN CHAPTER 1 78K ll SERIES FEATURES 1 3 OUTLINE OF uPD78218A SUB SERIES PRODUCTS uPD78217A 78218A 78P218A 78218A A 1 3 4 Features Instruction cycle 333 ns uPD78218A 78P218A 500 ns uPD78217A On chip memory ROM Mask ROM 32K bytes uPD78218A Not incorporated uPD78217A PROM 32 bytes uPD78P218A RAM 1024 bytes Upward compatible with uPD78214 series Enhanced macro service amp timer counters increased on chip memory size O pins 54 36 uPD78217A only e On chip 8 bit A D converter 8 analog inputs Timer counters 16 bits x 1 8 bits x 3 Serial interface Independent on chip UART and CSI e wPD78218A A Special quality grade product of uPD78218A 1 3 2 Applications Standard products OA equipment including printers typewriters PPCs facsimile etc electronic musical instruments inverters cameras etc Special products Automotive electrical equipment combustion control disaster crime preven tion unit 78K ll SERIES USER S MANUAL 1 3 3 Ordering Information and Quality Grade 1 Ordering information Ordering code uPD78217ACW uPD78217AGC AB8
6. 192 193 194 195 196 197 198 191 78K ll SERIES USER S MANUAL Call CALL Subroutine Call 16 Bit Direct Register Indirect Specification Instruction format CALL target Operation SP 1 lt SP 2 lt PC SP lt SP 2 PC lt target n Number of instruction bytes Operands Mnemonic Operands target CALL laddr16 rp Flags Description Makes a subroutine call using a 16 bit absolute address or register indirect address The start address of the nextinstruction PC n is saved to the stack and a branch is made to the address specified by the target operand target Coding example CALL 3059H Makes a subroutine call to 03059H 192 CHAPTER 8 INSTRUCTION DESCRIPTIONS Call Flag CALLF Subroutine Call 11 Bit Direct Specification Instruction format CALLF target Operation SP 1 lt PC 2 SP 2 lt PC 2 L SP lt SP 2 PC lt target Operands Mnemonic Operands target CALLF laddr11 Flags Description This subroutine call can branch only to an address in the range 00800H to 00FFFH The start address of the next instruction 2 is saved to the stack anda branch is made to an address in the range 00800H to OOFFFH Only the low order 11 address bits are specified the high order 5 bits are fixed at 00001B e Locating subroutine in the area fr
7. 102 7 2 16 Bit Instructions for Each Addressing 103 7 3 Bit Manipulation Instructions for Each Addressing Type 104 7 4 Call Instructions and Branch Instructions for Each Addressing Type 105 7 5 Operation Codes for mem a a 108 7 6 Table of Instruction Execution 136 9 1 Development Tools for Screen 226 9 2 Development Tools for In Circuit Emulator Control Program 228 vi CHAPTER 1 78K ll SERIES FEATURES The 78K series consists of the 5 series shown in Figure 1 1 The 78K ll series is one of these 5 series and comprises general purpose type products with an on chip 8 bits CPU These products have an instruction system and high performance interrupt controller suited to control applications and also incorporate a high performance CPU provided with a 1M byte data memory space 78K ll series further comprises 5 sub series the uPD78214 sub series 78218 sub series uPD78224 sub series uPD78234 sub series and uPD78244 sub series allowing the most suitable sub series to be selected for the particular application Each sub series has the same CPU with differences in the peripheral hardware only consequently the entire instruction set is shared by a
8. Mnemonic Operands B1 B2 B3 B4 B5 INC r 1100 0 R2 Ri Ro saddr 00 10 0110 Saddr offset DEC r 11 00 1 Re Ri Ro 0010 0111 Saddr offset INCW rp 0100 0 1 P Po DECW rp 0100 1 1 Pi Po 7 Shift rotate instructions ROR ROL RORC ROLC SHR SHL SHRW SHLW ROR4 ROL4 Operation code Mnemonic Operands 1 2 B3 B4 B5 ROR rn 00 1 1 000 0 0 R2 R ROL rn 00 1 1 000 1 0 No R2 R RORC rn 00 1 1 0000 00 2 1 R2 ROLC rn 00 1 1 00010 0 NeNi No R2 SHR rn 00 1 1 0000 0 2 R2 SHL 0011 0001 0 2 R2 SHRW 0011 0000 P2 P1 0 SHLW 0011 0001 1 1 No P2 P1 0 ROR4Note mem1 00 00 0101 000 1 1R 0 amp 1 0000 0001 000 010 1 1 Ri 0 ROLANote 00 00 0101 001 1 1R amp mem1 0000 0001 000 0101 1 1R 0 Note Cannot be used on 78244 sub series EEPROM area 117 78K ll SERIES USER S MANUAL 8 BCD adjustment instructions ADJBA ADJBS Operation code Mnemonic Operands B1 B2 B3 B4 B5 ADJBA 0000 1110 ADJBS 0000 11 1 1 9 Bit manipulation instructions MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 Operation code Mnemonic Operands B1 B2 B3 B4 B5 MOV1 CY saddr bit 00 00 1000 0000 0 B2 lt Saddr offset gt sfr bit 0000 1000 0000 1 B2 1 lt Sfr offset A bit 0000
9. RR 219 211 190 rc 206 BAK HN 195 212 BICER 214 154 FZ IMMER PPP 210 NR EM CNRC 186 C P GALE 192 POP e 201 14 193 PUSH sm 200 194 189 MERE ss 156 160 777 196 198 197 ROLA a 171 DENZ a i asss 215 ROLA esses y e 179 DEC n s sss 166 MR 173 168 170 DECW SP 204 4 178 au alias 00 PORC 172 163 E 220 251 78K ll SERIES USER S MANUAL S 252 APPENDIX C REVISION HISTORY A revision history is shown below Chapters described in the revised chapter column indicate those for the corresponding edition Edition Major changes Revised chapter Fifth The 68 pin PLCC has been changed to the 68 plastic QFJ Throughout The 64 pin ceramic LCC with window has been changed to the 64 pin ceramic WQFN The PC series has been changed to the PC AT Cautions and remarks have been added to Section 4 1 3 Chapter 4 The instruction code of BT has been modified in Section 7 2 3 Cha
10. JSOY pesn uguM Jejdepe Jeiquiesse INOHd 5 0061 94 2 2 5 eoejelul 106 L 2 oly Bngap wilV Od Wal 59195 0086 SoH eqoJd uogejnu3 JojejnuJe SO 3l 2 22 89 N N N 2 05 00 lu uido j A G 71 6 224 CHAPTER 9 DEVELOPMENT TOOLS MEMO 225 78K ll SERIES USER S MANUAL Table 9 1 Development Tools for Screen Debugger Target device Package In circuit emulator uPD78214 sub 64SDIP IE 78240 R A Pe 64QUIP uPD782192Note 1 uPD78213 64QFP uPD78214 14 x 14 mm body 68QFJ 74QFP 20 x 20 mm body uPD78218A sub 64SDIP IE 78240R A series uPD78217A uPD78218A 64QFP uPD78224 sub 84QFJ IE 78230 R A series uPD78220 uPD78224 64QFP uPD78P224 20 x 20 mm body uPD78234 sub 80QFP IE 78230 R A series 14 x 14 mm body uPD78233 uPD78234 84QFJ uPD78237 94QFP uPD78238 20 x 20 mm body uPD78P238 94WQFNNote 2 uPD78244 sub 64SDIP IE 78240 R A series uPD78243 64QFP uPD78244 14 x 14 mm body Screen debugger SD78K II Device file DF78210 Emulation p
11. PG 1500 This program provides the serial and parallel interfaces between PG 1500 and the host controller machine enabling the host machine to control the PG 1500 Host machine OS Distribution medium Part number PC 9800 series MS DOS Ver 3 10 to 5 25 inch 2HD uS5A10PG1500 3 5 inch 2HD uS5A13PG1500 IBM PC AT or See 4 5 25 inch 2DNote 2 uS7B11PG1500 compalhles 5 25 inch 2HC uS7B10PG1500 3 5 inch 2HC uS7B13PG1500 Notes1 Versions 5 00 and 5 00A feature a task swap function However the task swap function cannot be used with this software 2 The 5 25 inch 2D model is no longer available Those users who have already purchased a 5 25 inch 2D model will be supplied with a 5 25 inch 2HC or 3 5 inch 2HD model when the product is next upgraded 4 OS for the IBM PC The following OSs are supported for the IBM PC OS Version DOSTM Ver 3 1 to Ver 6 3 J6 1 VNote 2 to J6 3 VNote 2 Windows TMNote 1 Ver 3 1 MS DOS Ver 5 0 to Ver 6 2 5 0 VNote 2 to 6 2 VNote 2 IBM DOSTM J5 02 VNote 2 Notes 1 PC DOS and Windows are used together for the fuzzy knowledge data creation tool 2 Only English version systems are supported Caution Versions 5 00 and later feature a task swap function However the task swap function cannot be used with this software 239 78K ll SERIES USER S MANUAL 9 3 UPGRADING OTHER IN CIRCUIT EMULATORS TO 78K II SERIES LEVEL The 78K series and
12. 179 78K ll SERIES USER S MANUAL 8 8 BCD ADJUSTMENT INSTRUCTIONS BCD adjustment instructions are as follows ADJBA 181 ADJBS 182 180 CHAPTER 8 INSTRUCTION DESCRIPTIONS Decimal Adjust Register for Addition ADJBA Decimal Adjustment of Addition Result Instruction format ADJBA Operation Decimal Adjust Accumulator for Addition Operands None Flags Description Performs A register CY flag and flag decimal adjustment from the contents of the A register CY flag and AC flag The operation of this instruction is meaningful only when the result is stored in the A register after addition of BCD binary coded decimal format data In other case a meaningless operation is performed The adjustment method is shown in the table below f the contents of the A register are 0 as a result of the adjustment the Z flag is set 1 otherwise the Z flag is cleared 0 Condition Operation A3 0 lt 9 4 lt 9 and CY 0 lt A CY lt 0 AC lt 0 0 4 gt 10 CY 1 A lt 01100000B lt 1 lt 0 gt 10 4 lt 9 and CY 0 lt 000001108 CY lt 0 lt 1 0 A7 4 gt 9 1 lt 011001108 lt 1 lt 1 1 4 lt 9 and CY 0 lt 000001108 CY lt 0 lt 1 A7 4 gt 10 CY 1 lt 011001108 lt 1
13. 2 7 ee 24 Fear u u umu uy 24 1 6 2 e 24 1 6 3 Ordering Information and Quality 25 1 6 4 Function u una u au qaa 26 126 55 Block Diagrairi er 28 SERIESPRODUCTS uu I aqsu asa 29 CHAPTER3 MEMORY SPACE U U U U 37 CHAPTER 4 CHAPTER 5 CHAPTER 6 34 MEMORY SPAGE wate De eee a eee 37 3 1 1 wPD78214 Sub Series Memory Space 38 3 1 2 uPD78218A Sub Series Memory 38 3 1 3 uPD78224 Sub Series Memory Space 39 3 1 4 uPD78234 Sub Series Memory Space 39 3 1 5 uPD78244 Sub Series Memory Space 40 3 2 INTERNAL PROGRAM MEMORY AREA INTERNAL ROM 41 3 3 VECTOR TABLE AREA pere 42 3 4 INSTRUCTION TABLE 43 3 5 INSTRUCTION ENTRY 43 3 6 44 3 7 EEPROM AREA uPD78244 SUB SERIES ONLY 46 3 8 SPECI
14. 97 78K ll SERIES USER S MANUAL 10 Call return instructions CALL CALLF CALLT RET RETI RETB Mnemonic Operand No of Operation Flags bytes 2 CY CALL laddr16 3 SP 1 lt PC 3 u SP 2 lt PC 3 lt addr16 SP SP 2 rp 2 SP 1 2 SP 2 lt PC 2 PCH lt PCL lt SP lt SP 2 CALLF laddr11 2 SP 1 PC 2 SP 2 lt PC 2 PC15 11 00001 lt 11 SP lt SP 2 CALLT addr5 1 SP 1 1 SP 2 PC 1 lt 0000000001 addr5 1 PC lt 0000000001 addr5 SP lt SP 2 BRK 1 SP 1 PSW SP 2 1 SP 3 PC 1 L PCL lt 003EH PCH lt 003FH SP lt SP 3 IE 0 RET 1 PCL lt SP PCH lt SP 1 SP SP 2 RETI 1 PCL SP PCH SP 1 PSW SP 2 R R R SP SP 3 NMIS 0 RETB 1 PCL SP PCH SP 1 PSW SP 2 R R R SP SP 3 11 Stack manipulation instructions PUSH POP MOVW INCW DECW Mnemonic Operand No of Operation Flags bytes 2 CY PUSH PSW 1 SP 1 PSW SP SP 1 sfr 2 SP 1 lt sfr SP SP 1 rp 1 SP 1 lt SP 2 lt SP lt SP 2 POP PSW 1 PSW lt SP SP SP 1 R R R sfr 2 sfr
15. Ord 054 Old 004 s OST ASSES A A Hod 1l Wi 5 e lt G 214 014 va 45 lt gt 8 18534 snq eq zx v a jauueyo E pod indino IX SI E d m 952 Sua 8 5 Jejunoo Jeuul e ES JosseooJud 5 WN eo 39 WOH ueojoog 2 alsv cc ds is Ex 51915 691 5 5 1 aon NOH 5 a Zq od C gt Jejoujuoo VERUM 4 ZQqv oav lt gt SIV 8V snq sseJppv uoisuedxe 6 7 91 17 78K ll SERIES USER S MANUAL 1 5 OUTLINE OF uPD78234 SUB SERIES PRODUCTS UPD78233 78234 78237 78238 78P238 78234 A 78238 A 1 5 1 Features Instruction cycle 333 ns uPD78234 78238 78P238 500 ns uPD78233 78237 On chip memory ROM Mask ROM 16K bytes uPD78234 32K bytes uPD78238 Not incorporated uPD78233 78237 PROM 32K bytes uPD78P238 RAM 640 bytes uPD78233 78234 1024 bytes uPD78237 78238 78P238 I O pins 64 uPD78234 78238 78P238 46 uPD78233 78237 On chip 8 bit A D converter 8 analog inputs On chip 8 bit D A converter 2 analog outputs 12 bit PWM outputs 2 outputs T
16. amp 1 7 4 lt 1 lt amp mem1 7 4 ROL4Note mem1 2 lt 1 7 4 mem1 3 0 lt 1 7 4 lt mem1 3 o 1 3 lt amp mem1 7 4 amp mem1 s o lt amp mem1 7 4 Note Cannot be used on 78244 sub series EEPROM area lt amp 1 95 78K ll SERIES USER S MANUAL 8 BCD conversion instructions ADJBA ADJBS Mnemonic Operand No of Operation Flags bytes ADJBA 1 Use the decimal adjust accumulator after addition x x ADJBS 1 Use the decimal adjust accumulator after subtraction x x 9 Bit manipulation instructions MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 Mnemonic Operand No of Operation Flags bytes MOV1 CY saddr bit 3 CY lt saddr bit x CY sfr bit 3 CY sfr bit x CY A bit 2 CY lt A bit x CY X bit 2 CY lt X bit x CY PSW bit 2 CY lt PSW bit x saddr bit CY 3 saddr bit lt CY sfr bit CY 3 sfr bit lt CY A bit CY 2 A bit CY X bit CY 2 X bit CY PSW bit CY 2 PSW bit CY X AND1 CY saddr bit 3 CY lt CY saddr bit x CY saddr bit 3 CY lt A saddr bit x CY sfr bit 3 CY lt A sfr bit x CY sfr bit 3 CY lt CY sfr bit x CY A bit 2 lt CY A bit x CY A bit 2 CY lt CY A A bit x CY X bit 2 CY lt CY A X
17. dst 3 o lt dst 7 4 Operands Mnemonic Operands dst RORANoete mem1 amp mem1 Note Cannot be used on uPD78244 sub series EEPROM area Flags Description Rotates the low order 4 bits of the A register and the destination operand dst 2 digit digit data 4 bit data to the right The high order 4 bits of the A register are not changed Coding example ROR4 HL Performs digit rotation to the right of the memory contents specified by the A and HL registers HL 7 4 3 0 7 4 3 0 Before execution 1010 0011 1100 0101 After execution 1010 0101 0011 1100 178 CHAPTER 8 INSTRUCTION DESCRIPTIONS Rotate Left Digit ROL4 Digit Left Rotation Instruction format ROL4 dst Operation lt dst 7 4 dst 3 0 lt A3 0 dst 7 4 lt dst 3 0 Operands Mnemonic Operands dst ROLANote mem1 amp mem1 Note Cannot be used on uPD78244 sub series EEPROM area Flags Description Rotates the low order 4 bits of the A register and the destination operand dst 2 digit data 4 bit data to the left The high order 4 bits of the A register are not changed Coding example ROL4 DE 54H Performs digit rotation to the left of the A register and the memory contents of address DE register contents 54H A DE 54H 7 4 3 0 7 4 3 0 Before execution 0001 0010 0100 1000 After execution 0001 0100 1000 0010
18. jauueyo 99IAJ8S OIJEN interface 201 992 8 8 9 201 S lt Zd LNI lt lt l d1NI JosseooJd zs ue loog D lt 0d1NI LOL amp m 001 7 d LNI Bus control SLV 8v uoisuedxe 6 7 91 1 aon NOH sels IS 08S OS Jejoquoo b sseappy 13 78K ll SERIES USER S MANUAL 1 4 OUTLINE OF uPD78224 SUB SERIES PRODUCTS uPD78220 78224 78P224 1 4 4 Features Instruction cycle 333 ns uPD78224 78P224 500 ns uPD78220 On chip memory ROM Mask ROM 16K bytes uPD78224 Not incorporated uPD78220 PROM 16K bytes uPD78P224 RAM 640 bytes O pins 71 53 uPD78220 only Comparator 4 bit resolution x 8 Timer counters 16 bits x 1 8 bits x 2 Serial interface Independent on chip UART and CSI 1 4 2 Applications Areas handling a large amount of data such as kanji character generators typewriters hand held word processors ECRs etc 14 CHAPTER 1 78K ll SERIES FEATURES 1 4 3 Ordering Information and Quality Grade 1 Ordering information Ordering code Package On chip ROM uPD78220GJ 5BG 94
19. 20 x 20 mm body Standard uPD78P238LQ 84 pin plastic QFJ 111150 mil Standard uPD78P238KF 94 pin ceramic WQFN Standard uPD78234GC A xxx 3B9 80 pin plastic 14 x 14 mm body Special uPD78234GJ A xxx 5BG 94 pin plastic 20 x 20 mm body Special uPD78238GC A xxx 3B9 80 pin plastic 14 x 14 mm body Special uPD78238GJ A xxx 5BG 94 pin plastic 20 x 20 mm body Special Remark xxx is the ROM code number Please refer to Quality grade on NEC Semiconductor Devices Document number IEI 1209 published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications 20 CHAPTER 1 78 SERIES FEATURES 1 5 4 Function Outline Product name T uPD78234 uPD78238 uPD78P238 uPD78233 uPD78237 Number of basic instructions mnemonics 65 Minimum instruction execution time 333 ns 500 ns at 12 MHz operation On chip memory capacity ROM 16K bytes 32K bytes 32 16K ROM less Mask ROM Mask ROM bytesNote 1 PROM RAM 640 bytes 1024 bytes pyrosNotet 640 bytes 1024 bytes Memory space Program 64K bytes data 1M byte pins Input 16 Output 12 Input output 36 18 Total 64 46 Additional Pins with pull up resistor 42 24 function pinsNote 2 LED direct drive outputs 24 8 Transistor direct drive outputs 8 ROM less mode setting MODE pin Not possible ROM less product high level
20. Transfers the contents of the source operand src specified by the 2nd operand to the destination operand dst specified by the 1st operand Coding example MOVW AX HL Transfers the memory contents indicated by the HL register to the AX register 147 SERIES USER S MANUAL 8 3 8 BIT OPERATION INSTRUCTIONS 8 bit operation instructions are as follows ADD 149 ADDC 150 SUB 151 SUBC 152 AND 153 OR 154 XOR 155 156 148 CHAPTER 8 INSTRUCTION DESCRIPTIONS Add ADD Byte Data Addition Instruction format ADD dst src Operation dst CY lt dst src Operands Mnemonic Operands dst src ADD A byte saddr byte sfr byte r r A saddr A sfr saddr saddr A mem A amp mem Flags Description Adds the source operand src specified by the 2nd operand to the destination operand dst specified by the 1st operand and stores the result in the CY flag and the destination operand dst If dst is 0 as a result of the addition the Z flag is set 1 otherwise the Z flag is cleared 0 carry is generated out of bit 7 as a result of the addition the flag is set 1 otherwise the CY flag is cleared 0 is generated out of bit into bit 4 as a result of the addition the AC flag is set 1 otherwise the AC flag is cleared 0 Coding example
21. 64 6 1 3 Table Indirect Addressing LIL 65 CHAPTER 7 CHAPTER 8 6 1 4 Register Addressing 65 6 2 OPERAND ADDRESS ADDRESSING sese 66 6 2 1 Implied Addressing 1 U U U 66 6 2 2 Register Addressing u ll S 67 6 2 3 Immediate Addressing ai decet ig i 69 6 2 4 Short Direct aaa eene 70 6 2 5 Special Function Register SFR Addressing 72 6 2 6 Stack Addressing eine ae ede 73 6 3 1M BYTE EXPANSION SPACE ADDRESSING 74 6 3 1 Direct Addressing eene enne nnne nnns 74 6 3 2 Register Indirect Addressing 77 6 9 9 Based rer toad eee ec ity e rue duds 80 6 3 4 Indexed Addressing certae toner tt ret pert td 83 INSTRUCTION SE RR 87 FA OPERATIONS EE 87 7 1 1 Operand Representation Format and Description Method 87 7 42 88 TAG 89 7 1 4 List of Basic Instruction Operations 90 7 1 5 Instructi
22. A mem A amp mem Flags Description Subtracts the source operand src specified by the 2nd operand and the CY flag from the destination operand dst specified by the 1st operand and stores the result in the destination operand dst The CY flag is subtracted from the LSB This instruction is mainly used in multiple byte subtractions f dst is O as a result of the subtraction the Z flag is set 1 otherwise the Z flag is cleared 0 f a borrow is generated in bit 7 as a result of the subtraction the CY flag is set 1 otherwise the CY flag is cleared 0 If aborrow is generated out of bit 4 into bit 3 as a result of the subtraction the AC flag is set 1 otherwise the AC flag is cleared 0 Coding example SUBC A DE Subtracts the contents of DE register address and the CY flag from the A register and stores the result in the A register The DE register is incremented after the operation 152 CHAPTER 8 INSTRUCTION DESCRIPTIONS And AND Byte Data Logical Product Instruction format AND dst src Operation dst lt dst src Operands Mnemonic Operands dst src AND A byte saddr byte sfr byte A saddr A sfr saddr saddr A mem A amp mem Flags Description Obtains the bit by bit logical product of the destination operand dst specified by the 1st operand and the source op
23. A saddr 10 0 1 11 1 Saddr offset gt sfr 0000 0001 1001 11 10 Sfr offset gt saddr saddr 0111 111 0 Saddr offset lt Saddr offset gt 00 0 0 mem 11 lt Low Offset gt lt High Offset gt amp 00 00 0001 00 0 0 111 O lt Low Offset gt lt High Offset gt Continued 114 CHAPTER 7 INSTRUCTION SET Operation code Mnemonic Operands B1 B2 B3 B4 B5 XOR A byte 10 10 110 1 lt Data gt saddr byte 0110 110 1 lt Saddr offset gt lt Data gt sfr byte 0000 00010110 110 1 lt Sfr offset gt lt Data gt nr 1000 11 0 1 0 Re Rs 0 R2 R1Ro A saddr 10 0 1 110 1 Saddr offset gt sfr 0000 000 1 10 0 1 1 1 0 1 Sfr offset gt saddr saddr 0111 110 1 Saddr offset gt lt Saddr offset gt 00 0 0 110 1 lt Low Offset gt lt High Offset gt amp mem 0000 0001000 0 110 1 lt Low Offset lt High Offset gt byte 10 10 111 1 Data gt saddr byte 0110 111 1 Saddr offset gt lt Data gt sfr byte 0000 00010110 111 1 Saddr offset gt lt Data gt nr 1000 11 1 1 0 Re Rs 0 R2 R1Ro A saddr 10 0 1 11 1 1 Saddr offset gt sfr 0000 000 1 10 0 1 111 1 lt Sfr offset gt saddr sad
24. SFR RON IRAM PRAM SFR 4 4 nr i 3 6 EU See Table 7 6 3 4 for details A amp mem A saddr 4 8 6 A sfr 10 10 13 saddr saddr 6Note 1 14Note 2 10Note 1 IRAM for both saddr and saddr 2 SFR for both saddr and saddr 2 16 bit data transfer instructions MOVW Clock cycles Operands Bytes Internal ROM high speed fetch External ROM fetch 2 IRAM PRAM SFR oe IRAM PRAM SFR EMEM rp word 3 3 9 saddrp word 4 4 12 12 word 4 rp rp 2 4 6 saddrp 2 6 10 8 saddrp 2 5 9 7 ie AX sfrp 2 10 sfrp AX 2 i 9 i 2 11 9 13 13 13 14 12 16 10 16 AX amp mem1 3 13 11 15 15 15 17 15 19 19 19 mem1 AXNote 2 8 12 12 12 11 15 15 15 amp mem1 AXNote 3 10 14 14 14 14 18 18 18 Note Cannot be used uPD78244 sub series EEPROM area 125 78K ll SERIES USER S MANUAL 3 8 bit operation instructions ADD ADDC SUB SUBC AND OR XOR Clock cycles Mne
25. 11 12 15 15 14 15 18 A amp DE A amp HL A amp DE A amp HL 13 14 17 17 17 18 21 21 21 A DE byte A HL byte 9 10 13 13 13 14 17 A amp DE byte A amp HL byte 11 12 15 15 16 17 20 20 20 A SP byte 10 11 14 14 14 15 18 18 18 gt amp SP byte 12 13 16 16 17 18 21 21 21 word A word B word DE word HL 9 10 13 13 20 20 20 gt gt gt gt gt amp word A A amp word B A amp word DE A amp word HL 11 12 15 15 23 23 23 CHAPTER 7 INSTRUCTION SET Instruction group 8 bit data arithmetic amp logical operation instruc tions Mnemonic ADD ADDC SUB SUBC AND XOR CMP Table 7 6 Table of Instruction Execution Cycles 4 4 Internal ROM high speed fetch External ROM fetch Operands Bytes IRAM PRAM SFR EMEM ja IRAM PRAM SFR EMEM EE 2 9 8 10 10 12 11 13 13 13 A RUE 11 10 12 12 12 15 14 16 16 16 DE P 2 11 0 11 12 12 12 14 13 15 15 15 HL amp DE 13 12 13 14 14 14 17 18 18 18 amp HL 3 9 8 91 101 110 10 13 12 14 14 14 4 11 4041 12 12 12
26. A v mem A amp mem 3 5 A A v amp mem XOR A byte 2 A v byte saddr byte 3 saddr lt saddr byte str byte 4 sfr sfr byte rr 2 r lt r r A saddr 2 A lt saddr A sfr 3 A v sfr saddr saddr 3 saddr saddr saddr A mem 2 4 A mem A amp mem 3 5 A lt amp mem Continued 93 78K ll SERIES USER S MANUAL Mnemonic Operand No of Operation Flags bytes A byte 2 A byte X x saddr byte 3 saddr byte x x sfr byte 4 sfr byte x x rr 2 r r X x A saddr 2 A saddr x x A sfr 3 A sfr x x saddr saddr 3 saddr saddr x x A mem 2 4 A mem x x A amp mem 3 5 A amp mem x x 4 16 bit arithmetic logical instructions ADDW SUBW CMPW Mnemonic Operand No of Operation Flags bytes ADDW AX word 3 AX CY lt word x x AX rp 2 CY lt AX X x AX saddrp 2 AX CY lt AX saddrp x x AX sfrp 3 CY lt sfrp x x SUBW AX word 3 AX CY lt AX word x x AX rp 2 CY lt AX rp X X AX saddrp 2 AX CY lt AX saddrp x x AX sfrp 3 CY lt AX sfrp x x CMPW AX word 3 AX word x x AX rp 2 AX rp x x AX saddrp 2 AX saddrp x x AX sfrp 3 AX sfrp x x 94 CHAPTER 7 INSTRUCTION SET 5 Multiply divi
27. Instruction format INCW dst Operation dst lt dst 1 Operands Mnemonic Operands dst INCW rp Flags Description Increments the contents of the destination operand dst by 1 Since this instruction is often used to increment the register pointer in addressing which uses a register the contents of the Z AC and CY flags are not changed Coding example INCW HL Increments the HL register 167 78K ll SERIES USER S MANUAL Decrement Word Word Data Decrement DECW Instruction format DECW dst Operation dst lt dst 1 Operands Mnemonic Operands dst DECW rp Flags Description Decrements the contents of the destination operand dst by 1 Sincethis instruction is often used to decrement the register pointer in addressing which uses a register the contents of the Z AC and CY flags are not changed Coding example DECW DE Decrements the DE register 168 CHAPTER 8 INSTRUCTION DESCRIPTIONS 8 7 SHIFT ROTATE INSTRUCTIONS Shift rotate instructions are as follows ROR ROL RORC ROLG SHR SHL SHRW SHLW ROR4 ROL4 170 171 172 173 174 175 176 177 178 179 169 78K ll SERIES USER S MANUAL Rotate Right ROR Byte Data Right Rotation Instruction format ROR dst cnt Operation CY dst lt dsto dstm 1 lt cnt times cnt 0 to 7 Operands Mnemonic Operands dst cnt ROR rn Flag
28. LED direct drive outputs 16 pinsNote Transistor direct drive outputs 8 ROM less mode setting EA pin low level ROM less product Real time output ports 4 bits x 2 or 8 bits x 1 General registers 8 bits x 8 x 4 banks memory mapped Timer counters 16 bit timer counters Timer register x 1 Pulse output Capture register x 1 capability Compare register x 2 Toggle output PWM PPG output 8 bit timer counter 1 Timer register x 1 Pulse output Capture compare capability register x 1 Real time Compare register 1 ouput 4 bits 2 8 bit timer counter 2 Timer register x 1 Pulse output Capture register x 1 capability Compare register x 2 G PWM PPG output 8 bit timer counter 3 Timer register x 1 Compare register x 1 Serial interface UART CSI 3 wire serial SBI Note Additional function pins are included in the I O pins 1 channel incorporating dedicated baud rate generator 1 channel Continued CHAPTER 1 78K ll SERIES FEATURES uPD78212 uPD78214 uPD78P214 8 bit resolution x 8 channels uPD78213 Product name em A D converter Interrupts 19 sources 7 external 12 internal BRK instruction 2 level priority programmable 2 servicing modes vectored interrupts macro service Instruction set 16 bit operation Multiply divide 8 bits x 8 bits 16 bits 8 bits Bit manipulation
29. SP lt SP 1 rp 1 rp lt SP lt SP 1 SP SP 2 MOVW SP word 4 SP word SP AX 2 SP AX AX SP 2 AX SP INCW SP 2 SP lt SP 1 DECW SP 2 SP lt SP 1 98 CHAPTER 7 INSTRUCTION SET 12 Unconditional branch instruction BR Mnemonic BR Operand No of Operation Flags bytes 2 laddr16 3 PC lt addr16 2 PCH lt PCL addr16 2 PC lt PC 2 jdisp8 99 78K ll SERIES USER S MANUAL 13 Conditional branch instructions BC BL BNC BNL BZ BE BNZ BNE BT BF BTCLR DBNZ Mnemonic Operand No of Operation Flags Wes 7 BC addr16 2 PC PC 2 jdisp8 if CY 1 BL BNC addr16 2 lt PC 2 jdisp8 if CY 0 BNL BZ addr16 2 PC PC 2 jdisp8 if Z 1 BE BNZ addr16 2 PC PC 2 jdisp8 if Z 0 BNE BT saddr bit addr16 3 PC lt PC 3 jdisp8 if saddr bit 1 sfr bit addr16 4 PC lt PC 4 jdisp8 if sfr bit 1 A bit addr16 3 PC lt PC 3 jdisp8 if A bit 1 X bit addr16 3 PC lt PC 3 jdisp8 if X bit 1 PSW bit addr16 3 PC PC 3 jdisp8 if PSW bit 1 BF saddr bit addr16 4 PC lt PC 4 jdisp8 if saddr bit 0 sfr bit addr16 4 PC lt PC 4 jdisp8 if sfr bit 0 A bit addr16 3 PC PC 3 jdisp8 if A bit 0 X bit addr16 3 PC PC 3 jdisp8 if
30. lt 3 13 16 CMPW AX word 3 3 9 AX rp 2 5 7 saddrp 2 6 10 8 12 sfrp 3 12 15 5 Multiplication division instructions MULU DIVUW Clock cycles Mnemonic Operands Bytes Internal ROM high speed fetch External ROM fetch Lu IRAM SFR EMEM deis IRAM PRAM SFR EMEM MULU r 2 22 24 DIVUW r 2 74 76 129 78K ll SERIES USER S MANUAL 6 Increment decrement instructions INC DEC INCW DECW Clock cycles Mnemonic Operands Bytes Internal ROM high speed fetch External ROM fetch Internal Internal Rom IRAM PRAM SFR IRAM PRAM SFR INC r 1 2 3 saddr 2 3 7 6 7 DEC r 1 2 3 2 3 7 6 7 INCW rp 1 3 3 DECW rp 1 3 3 7 Shift rotate instructions ROL RORC ROLC SHR SHL SHRW SHLW ROR4 ROL4 Clock cycles Mnemonic Operands Bytes Internal ROM high speed fetch External ROM fetch IRAM SFR EMEM IRAM PRAM SFR ROR rn 2 2 542n ROL rn 2 3 2n 5 2 RORC rn 2 342n 542n ROLC rn 2 3 2 5
31. 200 CHAPTER 8 INSTRUCTION DESCRIPTIONS Pop POP Pop Instruction format POP dst Operation When dst rp When dst PSW or sfr dst lt SP dst lt SP dstu lt SP 1 SP lt SP 1 SP lt SP 2 Operands Mnemonic Operands src POP PSW sfr rp Flags src PSW Other than cases at left 2 2 R R R Description Restores data from the stack to the register specified by the destination operand dst If the operand is the PSW each flag is replaced with stack data No interrupts or macro services are acknowledged between the POP PSW instruction and the next instruction Coding example POP IMKOL Restores stack data to the IMKOL register 201 78K ll SERIES USER S MANUAL MOVW SP src Move Word MOVW AX SP Stack Pointer Word Data Transfer Instruction format MOVW dst src Operation dst lt src Operands Mnemonic Operands dst src MOVW SP word SP AX AX SP Flags Description These instructions are used to manipulate the contents of the stack pointer Stores the source operand src specified by the 2nd operand in the destination operand dst specified by the 1st operand Coding example MOVW PS 0FE1FH Stores OFE1FH in the stack pointer 202 CHAPTER 8 INSTRUCTION DESCRIPTIONS INCW SP Increment Word Stack Pointer Increment Instruction format INCW SP Operation SP
32. nstruction code format The CPU checks the data obtained by logical negation of the immediate data to be written and if correct performs the write If the data is incorrect the write is not performed and the next instruction is executed Coding example MOV STBC 2 Writes 2 to STBC sets STOP mode 217 78K ll SERIES USER S MANUAL Select Register Bank Register Bank Selection SEL RBn Instruction format SEL RBn Operation RBS0 RBS1 lt n 0 to 3 Operands Mnemonic Operands RBn SEL RBn Flags Description Selects the register bank specified by the operand RBn as the register bank to be used by the next and subsequent instructions RBn comprises RBO to RB3 Coding example SEL RB2 Selects register bank 2 as the register bank to be used from the next instruction onward 218 CHAPTER 8 INSTRUCTION DESCRIPTIONS NOP No Operation No Operation Instruction format NOP Operation no operation Operands None Flags Description Expends time without performing any processing 219 78K ll SERIES USER S MANUAL Enable interrupt El Interrupt Enabling Instruction format EI Operation IE 1 Operands None Flags Description Sets the acknowledgment enabled state for maskable interrupts sets 1 the interrupt enable flag IE No interrupts or macro service requests
33. port 8 bit port P5 8 bit port 8 bit I O port 8 bit port 8 bit port P6 4 bit output 4 bit output 4 bit output 4 bit output 4 bit output 4 bit output 4 bit output port 4 bit port 2 bit port 4 bit port 2 bit port 4 bit port 2 bit port 4 bit port port port port port port port P7 6 bit input port 7 bit port Note Additional function pins are included in I O pins 30 CHAPTER 2 78 SERIES PRODUCTS 1 3 uPD78244 sub series uPD78234 sub series uPD78233 uPD78234 uPD78237 uPD78238 wPD78243 uPD78244 uPD78P238 65 Common to 78K II series 500 ns 333 ns 500 ns 333 ns 500 ns 333 ns When the stack area is internal dual port RAM 6 Other than above 8 40 to 85 C 5 V 10 Ta 10 to 70 C Voo 5 V 10 8 bits x 8 x 4 banks P6 and PM6 None 16K bytes None 32K bytes None 16K bytes 32K 16K bytesNote None 512 bytes 640 bytes 1024 bytes 1024 bytes 512 bytes 1024 640 bytesNote Program memory space 64K bytes Data memory space 1M byte 16 14 12 18 36 18 36 10 28 46 64 46 64 36 54 24 42 24 42 16 34 8 24 8 24 0 16 8 8 bit input output port 8 bit input output port 8 bit input port 8 bit input output port 8 bit port 8 bit port
34. uPD78218ACW xxx uPD78218AGC xxx AB8 uPD78P218ACW uPD78P218AGC AB8 uPD78P218ADW uPD78218ACW A xxx uPD78218AGC A xxx AB8 Package 64 pin plastic shrink DIP 750 mil 64 pin plastic QFP 14 x 14 mm body 64 pin plastic shrink DIP 750 mil 64 pin plastic QFP 14 x 14 mm body 64 pin plastic shrink DIP 750 mil 64 pin plastic QFP 14 x 14 mm body 64 pin ceramic shrink DIP with window 750 mil 64 pin plastic shrink DIP 750 mil 64 pin plastic QFP 14 x 14 mm body Remark xxx is the ROM code number 2 Quality grade Ordering code uPD78217ACW uPD78217AGC AB8 uPD78218ACW xxx uPD78218AGC xxx AB8 uPD78P218ACW uPD78P218AGC AB8 uPD78P218ADW uPD78218ACW A xxx 78218 8 64 plastic shrink DIP 750 mil 64 pin plastic QFP 14 x 14 mm body 64 pin plastic shrink DIP 750 mil 64 pin plastic QFP 14 x 14 mm body 64 pin plastic shrink DIP 750 mil 64 pin plastic QFP 14 x 14 mm body 64 pin ceramic shrink DIP with window 750 mil 64 pin plastic shrink DIP 750 mil 64 pin plastic QFP 14 x 14 mm body Remark xxx is the ROM code number On chip ROM None None Mask ROM Mask ROM One time PROM One time PROM EPROM Mask ROM Mask ROM Quality grade Standard Standard Standard Standard Standard Standard Standard Special Special Please refer to Quality grade NEC Semiconductor Devices Document number IEI 1209 published
35. 16 15 17 17 17 SP byte 10 lool 11 11 14 13 15 15 15 A amp SP byte 4 12 11 12 13 13 13 17 16 18 18 18 A word A 4 9 8 9 10 10 10 14 15 17 17 17 A word HL A amp word A NOR 5 11 10 11 12 12 12 17 18 20 20 20 A amp word DE A amp word HL 139 78K ll SERIES USER S MANUAL MEMO 140 CHAPTER 8 INSTRUCTION DESCRIPTIONS This chapter describes the instructions of the 78K ll series products Instructions with different operands are grouped by mnemonic The basic organization of the instruction descriptions is shown on the next page Please refer to Chapter 7 Instruction Set for the number of bytes and operation codes of the instructions The same instructions are used on all 78 series products 141 78K ll SERIES USER S MANUAL Description Example Mnemonic Full name Move MOV Byte Data Transfer Meaning of instruction Instruction format MOV dst src Shows the basic coding format of the instruction Operation dst lt src Shows the instruction operation using symbols Operands Shows the operands which can be specified with this instruction See Chapter 7 for the symbols used for the various operands r byte A amp mem saddr byte L A laddr16 A saddr A amp laddr16 saddr A L PSW A mem A
36. 8 bit I O port 8 bit port 8 bit port 8 bit I O port 4 bit output 4 bit output 4 bit output 4 bit output 4 bit output 4 bit output port 2 bit port 4 bit port 2 bit port 4 bit port 2 bit port 4 bit port port port port port port 8 bit input port 6 bit input port Note Set by software 31 78K ll SERIES USER S MANUAL Sub series name uPD78214 sub series uPD78218A sub series uPD78224 sub series Product name 78212 uPD78213 uPD78214 wPD78217A uPD78218A uPD78220 uPD78224 Item uPD78P214 uPD78P218A uPD78P224 PWM outputs None Comparators None 4 bits x 8 A D converter 8 bits x 8 None Conversion time Select according to the operating frequency selection input 3 4 V to 3 6 V to voltage range Input voltage Always pin voltage from 0 V to AVrer Pin voltage from 0 V to related restriction for pins selected by bits ANI0 to ANI2 AVrer for pins subject of ADM register only to A D conversion only during A D conversion D A converter None Timer 16 bit timer 1 count counter ters 8 bit timer 3 2 counter Toggle 4 outputs PWM PPG Yes No output One shot No Yes No pulse Interrupt 7 5 sources External SFR area 16 bytes OFFDOH to OFFDFH None Serial UART 1 channel inter face CSI 1 channel for SBI BRG timer Yes Dual fun
37. lt High Offset gt ADDC A byte 1010 100 1 lt Data gt saddr byte 0110 100 1 Saddr offset gt lt Data gt sfr byte 0000 00010110 1001 lt Sfr offset gt lt Data gt nr 1000 100 1 0 Res Rs 0 RzRiRo A saddr 1001 100 1 lt Saddr offset gt sfr 0000 000 1 100 1 1001 lt Sfr offset gt saddr saddr 0111 1001 lt Saddr offset gt lt Saddr offset gt 00 0 0 1 0 0 1 Low Offset gt lt High Offset gt A amp 0000 0001000 0 100 1 lt Low Offset gt lt High Offset gt Continued 112 CHAPTER 7 INSTRUCTION SET Operation code Mnemonic Operands B1 B2 B3 B4 B5 SUB A byte 10 10 10 1 0 Data gt saddr byte 0110 101 0 lt Saddr offset gt lt Data gt sfr byte 0000 0001 0110 1 0 10 lt Sfr offset gt lt Data gt nr 1000 10 1 0 0 Re Rs 0 R2 R1Ro A saddr 10 0 1 101 04 Saddr offset gt sfr 0000 000 1 1 0 1 101 0 lt Sfr offset gt saddr saddr 0111 101 0 lt Saddr offset gt lt Saddr offset gt 00 0 0 10 1 0 lt Low Offset gt lt High Offset gt amp mem 0000 0001000 0 101 0 lt Low Offset lt High Offset gt SUBC A byte 1010 101 1 lt Data gt saddr byte 0110 101 1 Saddr offset gt
38. o 13538 8 lt 9 E snq g 2 a Jeuueuo E LX us a ze S91 q 952 Jeouenbes JosseooJd WOH ueajoog 915 MSd ds 5 15 t aon NOH Bus control SLV 8V uoisuedxe 61 91 1 sseJppy SFR address data bus Hod jenp 72 JON p28 ddl Se1oN seva sts wouda3 Q v aauAV v pod jndjno 8 Sd AJA lunoo i uu 8 Sd 4ejunoo 18uul 8 Sd 4ejunoo 48ull sug 91 L eues pneg 28 CHAPTER 2 78K ll SERIES PRODUCTS This chapter shows the functions of the 78K ll series products in tabular form For further details please refer to the relevant User s Manual 29 78K ll SERIES USER S MANUAL Sub series name uPD78214 sub series uPD78218A sub series uPD78224 sub series Product 78212 uPD78213 uPD78214 wPD78217A uPD78218A wPD78220 uPD78224 Item 1 078 214 uPD78P218A 78 224 Number of basic 65
39. Common to 78K ll series instructions Minimum instruction 333 ns 500 ns 333 ns 500 ns 333 ns 500 ns 333 ns execution time PUSH and PSW instruction execution When the stack area is internal dual port 5 or 7 internal dual When the stack area is port RAM 6 When the stack area is internal dual port RAM 5 time number of Other than above 7 or 9 Other than above 8 or7 clocks Operating ambient Other than uPD78P218A 40 to 85 C 5 V 10 Ta 40 to 85 C temperature and uPD78P218A Ta 40 to 85 C 5 V 0 3V 5 V 5 supply voltage range Ta 10 to 70 C 5 V 10 General registers 8 bits x 8 x 4 banks Bank registers P6 and PM6 P6 only On chip ROM 8K bytes None 16K bytes None 32K bytes None 16K bytes memory EEPROM None RAM 384 bytes 512 bytes 1024 bytes 640 bytes Memory space Program memory space 64K bytes Data memory space 1M byte Input 14 pins Output 12 12 20 Input output 28 10 28 10 28 25 35 Total 54 36 54 36 54 45 63 Addi Pins with 34 16 34 16 34 None tional pull up func resistor tion pins LED direct 16 0 16 0 16 Note drive outputs Transistor 8 None direct drive outputs PO 8 bit output port P1 8 bit port P2 8 bit input port P3 8 bit port P4 8 bit port 8 bit I O port 8 bit
40. Divide Unsigned Word DIVUW Unsigned Word Data Division Instruction format DIVUW dst Operation AX quotient dst remainder lt AX dst Operands Mnemonic Operands dst DIVUW r Flags Description Divides the AX register contents by the destination operand dst contents and stores the quotient in the AX register and the remainder in the destination operand dst The division treats the contents of the AX register and the destination operand dst as unsigned data Dividing the contents by 0 dst 0 results in AX quotient FFFFH dst remainder Original value of the X register Coding example DIVUW E Divides the AX register contents by the E register contents and stores the quotient in the AX register and the remainder in the E register 163 78K ll SERIES USER S MANUAL 8 6 INCREMENT DECREMENT INSTRUCTIONS Increment decrement instructions are as follows ING 165 DEC 166 INCW 167 DECW 168 164 CHAPTER 8 INSTRUCTION DESCRIPTIONS Increment INC Byte Data Increment Instruction format INC dst Operation dst lt dst 1 Operands Mnemonic Operands dst INC r saddr Flags Description Increments the contents of the destination operand dst by 1 If the result of the increment is 0 the Z flag is set 1 otherwise the 7 flag is cleared 0 Ifacarry is generated out of bit 3 into bit 4 as a result of the increment the
41. Real time output ports 4 bits x 2 or 8 bits x 1 General registers 8 bits x 8 x 4 banks memory mapped Timer counters Notes 1 Set by software 16 bit timer counters Timer register x 1 Pulse output Capture register x 1 capability Compare register x 2 Toggle output PWM PPG output One shot pulse output 8 bit timer counter 1 Timer register x 1 Pulse output Capture compare capability register x 1 Real time Compare register x 1 output 4 bits x 2 Timer register x 1 Pulse output Capture register x 1 capability Compare register x 2 Po 8 bit timer counter 2 PWM PPG output 8 bit timer counter 3 Timer register 1 Compare register x 1 Continued 2 Additional function pins are included in the pins 21 78K ll SERIES USER S MANUAL Product name iem uPD78234 uPD78238 uPD78P238 uPD78233 uPD78237 PWM output function 12 bit resolution x 2 channels PWM frequency 23 4 kHz Serial interface UART 1 channel incorporating dedicated baud rate generator CSI 3 wire serial SBI 1 channel A D converter 8 bit resolution x 8 channels D A converter 8 bit resolution x 2 channels Interrupts 19 sources 7 external 12 internal BRK instruction 2 level priority programmable 2 servicing modes vectored interrupts macro service Instruction set 16 bit operation Multiply divide 8 bits x 8 bits 16 bits 8 bits Bit manip
42. amp mem1 lt AX Note Cannot be used on 78244 sub series EEPROM area 3 8 bit arithmetic logical instructions ADD ADDC SUB SUBC AND OR XOR CMP Operand No of Operation Flags LA 2 A byte 2 A CY lt byte x x x saddr byte 3 saddr CY lt saddr byte x X X sfr byte 4 sfr CY lt sfr byte x x x rr 2 r CY lt r r x X X A saddr 2 A CY lt saddr x x x sfr 3 A CY A sfr x x X saddr saddr 3 saddr CY lt saddr saddr x x x A mem 2 4 A lt mem x x x A amp mem 3 5 A CY lt amp mem x x x Continued 91 78K ll SERIES USER S MANUAL Mnemonic Operand No of Operation Flags bytes AC ADDC A byte 2 A CY lt byte x x saddr byte 3 saddr CY lt saddr byte CY x x sfr byte 4 sfr CY lt sfr byte x x nr 2 r lt x x A saddr 2 A CY lt A saddr CY x x A sfr 3 A lt A sfr CY x x saddr saddr 3 saddr CY lt saddr saddr CY x x A mem 2 4 A CY lt mem x x A amp mem 3 5 A CY lt amp mem CY x x SUB A byte 2 A CY lt byte x x saddr byte 3 saddr CY lt saddr byte x x sfr byte 4 sfr CY lt sfr byte
43. 0 0 lt Saddr offset gt lt Low Byte gt lt High Byte gt sfrp word 0000 10 1 1 Sfr offset lt Low Byte gt lt High Byte gt rp 0010 010 0 0 5 0 1 2 P10 AX saddrp 00 01 11 0 0 lt Saddr offset gt 0001 101 04 Saddr offset gt sfrp 0001 00 0 1 lt Sfr offset gt sfrp 0001 00 1 1 Sfr offset gt 1 0000 01 0 11 110 0 0 1Ro mem1 AX 0000 010 111110 0 1 1Ro AX amp mem1Note 0000 00010000 010111110 0 0 1 Ro amp mem1 AXNote 00 00 00010000 010111110 0 1 1 Ro Note Cannot be used on 78244 sub series EEPROM area 111 78K ll SERIES USER S MANUAL 3 8 bit operation instructions Operation code ADD ADDC SUB SUBC AND OR XOR CMP Mnemonic Operands B1 B2 B3 B4 B5 ADD A byte 10 10 100 0 Data gt saddr byte 0110 100 0 lt Saddr offset gt lt Data gt sfr byte 0000 0001 0110 1 0 0 0 lt Sfr offset gt lt Data gt nr 1000 10 0 0 0 RsRsR4 0 R2 A saddr 10 0 1 10 0 0 lt Saddr offset gt sfr 0000 0001 1001 1 0 0 0 lt Sfr offset gt saddr saddr 0111 100 0 lt Saddr offset gt lt Saddr offset gt 00 0 0 1 0 004 Low Offset gt lt High Offset gt amp 0000 0001000 0 100 0 lt Low Offset gt
44. 7007 HP UXT rel 9 01 DAT uS3P16RA78K2 SPAROstationTM SunOS rel 4 1 1 Cartridge tape uS3K15RA78K2 EWS 4800 series RISC EWS UX V rel 4 0 20 24 uS3M15RA78K2 78 series compiler CC78K Ill CC78K II Notes 1 This C compiler can be used with all 78 series products Its language specifications conform to ANSI standards and compiled programs can be written into ROM The compiler offers such features as special function register manipulation bit manipulation variables using short direct addressing and interrupt control The use of these features ensures It also has a start up routine sample program and a standard function object library To use this compiler the 78K ll series effective programming and high object efficiency relocatable assembler RA78K II is necessary Host machine OS Distribution medium Part number PC 9800 series MS DOS Ver 3 30 to 5 25 inch 2HD uS5A10CC78K2 3 5 inch 2HD uS5A13CC78K2 IBM PC AT or See 4 5 25 inch 2DNote 2 uS7B11CC78K2 compatibles 5 25 inch 2HC uS7B10CC78K2 3 5 inch 2HC uS7B13CC78K2 HP9000 series 700 HP UX rel 9 01 DAT uS3P16CC78K2 SPARCstation SunOS rel 4 1 1 Cartridge tape uS3K15CC78K2 EWS 4800 series RISC EWS UX V rel 4 0 ies uS3M15CC78K2 The 8 inch 2D model has been superseded by the 5 25 inch 2HD and 3 5 inch 2HD models Those users who have already purchased an 8 in
45. 75X series in circuit emulators can be upgraded to the level of the 78K ll series by replacing their internal boards with an optional board Note that the upgraded in circuit emulator requires an appropriate new control program 9 3 1 Upgrading to IE 78240 R A Level Emulator IE group number Required board Remarks IE 78230 R A 1 IE 78240 R EM IE 78140 R IE 78240 RNote 1 2 IE 78200 R BK IE 78112 RNote 1 3 IE 78200 R BK The high speed download function is not IE 78210 RNote 1 IE 78240 R EMNote 2 supported Those users who are also using IE 78220 RNote 1 an in circuit emulator of IE group 1 2 or 4 IE 78310 RNote 1 are recommended to upgrade these emulators IE 78310A R also Those users with an in circuit emulator of IE group 1 do not need to purchase the IE 78200 R BK the IE 78200 R BK board is built into the IE group 1 in circuit emulator IE 75000 R 4 IE 78200 R BK Those users with an in circuit emulator of IE IE 75001 R IE 78240 R EM group 1 do not need to purchase the IE 78000 R IE 78200 R BK the IE 78200 R BK board is IE 78130 R built into the IE group 1 in circuit emulator IE 78230 RNote 1 IE 78320 RNote 1 IE 78327 R IE 78330 R IE 78350 R IE 78600 R Notes1 This product is no longer produced and is not available from NEC 2 This board is used for emulation for the uPD78214 sub series Those users who already have the IE 78210 R EMNote 1 do not have to purchase this board 240 CHA
46. A Store data in bank 1 PM6 register contents added as maximum address information DBNZ B LOOP Repeat processing Figure 3 4 Example of Inter Bank Data Transfer Bank 1 Bank 5 main data bank subsidiary data bank 1FFFFH 5FFFFH 10000H 50000H MOV DE4 A MOV A amp HL A register Remark Both banks of MOV DE A and MOV A amp HL are stored in 0 50 CHAPTER 4 REGISTERS 4 4 CONTROL REGISTERS Control registers comprise the program counter PC program status word PSW and stack pointer SP 4 1 1 Program Counter PC The program counter is a 16 bit binary counter which holds program memory address information see Figure 4 1 The program counter is normally incremented automatically by the number of instruction bytes fetched When an instruction associated with a branch is executed immediate data or register contents are set in the PC When a RESET signal is input the contents of address 00000H of internal ROM or external memory in the uPD78213 78217A 78220 78233 78237 78243 are set in the low order 8 bits of the PC and the contents of address 00001H in the high order 8 bits Figure 4 1 Program Counter Configuration 14 13 11 10 15 12 9 8 7 6 5 4 3 2 1 0 otsPoposporsponpor eos po cr res res ea eer eoo 4 1 2 Program Status Word PSW The program status word PSW is an 8 bit register consisting of various flags which are set or reset dependi
47. AC flag is set 1 otherwise the AC flag is cleared 0 Since this instruction is often used to increment a counter for repeated processing or the offset register in indexed addressing the contents of the CY flag are not changed in order to retain the CY flag contents in a multiple byte operation Coding example INC B Increments the B register 165 78K ll SERIES USER S MANUAL Decrement DEC Byte Data Decrement Instruction format DEC dst Operation dst lt dst 1 Operands Mnemonic Operands dst DEC r Flags Description Decrements the contents of the destination operand dst by 1 f the result of the decrement is 0 the Z flag is set 1 otherwise the Z flag is cleared 0 is generated out of bit 4 into bit as a result of the decrement the AC flag is set 1 otherwise the AC flag is cleared 0 Since this instruction is often used to decrement a counter for repeated processing or the offset register in indexed addressing the contents of the CY flag are not changed in order to retain the CY flag contents in a multiple byte operation Ifitis not wished to change the AC and CY flags when dst is the B register C register or saddr the DBNZ instruction can be used Coding example DEC OFE92H Decrements the contents of address OFE92H 166 CHAPTER 8 INSTRUCTION DESCRIPTIONS INCW Increment Word Word Data Increment
48. BCD adjustment etc Package 64 pin plastic shrink DIP 750 mil 64 pin plastic QUIP except uPD78212 68 pin plastic QFJ 950 mil except 78212 64 pin plastic QFP 14 x 14 mm body 74 pin plastic QFP 20 x 20 mm body 64 pin ceramic shrink DIP with window 750 mil uPD78P214 only 78K ll SERIES USER S MANUAL 1 2 5 Block Diagram 1 s B 1 YO 2 10 ul suoluod pepeus ss ddA 15534 ex 5 2 wn gt LX s l q 992 vLedg adrl vLzg ddrl e 1 2820 1 s l q 821 S d 94 694 ZSd 4 LEd ZZd LOd 044 Ord 004 2288888 H aoNN VH y zLegzadr AVud uod penp 72 Y9 28 2 48 212820 1 JON 212820 1 Salon 52 ejeq 99IAJ8S z aon S944q 962 Bus interface Jeouenbes OJOI A WOH OJIN JosseooJud ueojoog Data bus 8 Bus control V 8V uoisuedxe 61 v 91v 519151691 Aresodwia snq 5 1 C V exsug pod 1ndino 8 Sd jeuueuo
49. NOH z m LLA riv ovL_ gt ZW 5 lt 21 0 1dnuejul SIV 8V Sng ss ppV lqeuutue16o1d uoisuedxe 619 919 23 78K ll SERIES USER S MANUAL 1 6 OUTLINE OF uPD78244 SUB SERIES PRODUCTS uPD78243 78244 1 6 1 Features Instruction cycle 333 ns uPD78244 500 ns uPD78243 On chip memory ROM Mask ROM 16K bytes uPD78244 Not incorporated uPD78243 RAM 512 bytes On chip EEPROMNote 512 bytes Note Electrically erasable programmable read only memory Unlike ordinary data memory RAM EEPROM can retain data in the event of a power failure O pins 54 uPD78244 36 uPD78243 On chip 8 bit A D converter 8 analog inputs Timer counters 16 bits x 1 8 bits x 3 Serial interface Independent on chip UART and CSI 1 6 2 Applications OA equipment including printers typewriters cameras PPOs facsimile etc adjustment data storage in application set assembly data retention in case of power failure etc 24 CHAPTER 1 78K ll SERIES FEATURES 1 6 3 Ordering Information and Quality Grade 1 Ordering information Ordering code Package uPD78243CW 64 pin plastic shrink DIP 750 mil uPD78243GC AB8 64 pin plastic QFP 14 x 14 mm body uPD78243CW xxx 64 pin plastic shrink DIP 750 mil uy PD78243GC xxx AB8 64 pin plastic QFP 14 x 14 mm body Remark xxx is the ROM code number 2 Quality grade Ordering code P
50. O pins Input 8 Output 20 12 LED drive capability 8 LED drive capability 8 Input output 35 25 63 45 ROM less mode setting EA pin low level ROM less product Real time output ports 4 bits x 2 or 8 bits x 1 General registers 8 bits x 8 x 4 banks memory mapped Timer counters 16 bit timer counters Timer register x 1 Pulse output Capture register x 1 capability Compare register x 2 Toggle output 8 bit timer counter 1 Timer register x 1 Pulse output Capture compare capability register x 1 Real time Compare register x 1 output 4 bits x 2 8 bit timer counter 2 Timer register x 1 Pulse output Capture register x 1 capability Compare register x 2 Toggle output Serial interface UART 1 channel CSI 3 wire serial SBI 1 channel Comparator 4 bit resolution x 8 Interrupts 17 sources 8 external 9 internal BRK instruction 2 level priority programmable 2 servicing modes vectored interrupts macro service Instruction set 16 bit operation Multiply divide 8 bits x 8 bits 16 bits 8 bits Bit manipulation BCD adjustment etc Package 94 pin plastic QFP 20 x 20 mm body 84 pin plastic QFJ 1150 mil 16 CHAPTER 1 78K II SERIES FEATURES 1 4 5 Block Diagram INV H Hod jenp 72 vzedgZadrl vzzaz adr JON 0228 L ta 9 4 94 594 Sd LEd 4Zd Ld LOd p2zd8Zadn 104 044
51. Operands Mnemonic Operands dst cnt RORC ron Flags Description Rotates to the right the contents of the destination operand dst specified by the 1st operand including the CY flag cnt times as specified by the 2nd operand f the 2nd operand cnt is 0 no processing is performed Z AC and CY flags also do not change Coding example RORC B 1 Rotates the contents of the B register 1 bit to the right including the CY flag 172 CHAPTER 8 INSTRUCTION DESCRIPTIONS Rotate Left with Carry ROLC Byte Data Left Rotation including Carry Instruction format ROLC dst cnt Operation CY lt dst7 dsto lt dstm 1 lt dstm x cnt times cnt 0 to 7 Operands Mnemonic Operands dst cnt ROLC rn Flags Description Rotates to the left the contents of the destination operand dst specified by the 1st operand including the CY flag cnt times as specified by the 2nd operand f the 2nd operand cnt is 0 no processing is performed Z AC and CY flags also do not change To perform a one bit left rotation execution time can be reduced by using ADDC 7 0 Coding example ROLC A 3 Rotates the contents of the A register 3 bits to the left including the CY flag 173 SERIES USER S MANUAL Shift Right Logical SHR Byte Data Logical Right Shift Instruction format dst cnt Operation
52. PSW Flags Shows the operation of flags which are changed by execution of the instruction The symbols used for flag operations are shown below Z AC CY Legend Symbol Meaning Blank No change 0 Cleared to 0 1 Set to 1 x Set or cleared depending on result R Previously saved value is restored Description Describes the operation of the instruction in detail Transfers the contents of the source operand src specified by the 2nd operand to the destination operand dst specified by the 1st operand Coding example MOV A 4DH Transfers 4DH to the A register 142 CHAPTER 8 INSTRUCTION DESCRIPTIONS 8 1 8 BIT DATA TRANSFER INSTRUCTIONS 8 bit data transfer instructions are as follows MOV 144 145 143 78K ll SERIES USER S MANUAL Move Byte Data Transfer MOV Instruction format MOV dst src Operation dst lt src Operands Mnemonic Operands dst src Mnemonic MOV r byte MOV saddr byte sfr byte A saddr saddr A saddr saddr A sfr sfr A A mem Flags In case of PSW byte and PSW A operands Z AC CY x x x Description Operands dst src A amp mem mem A amp mem A laddri16 A amp addr16 laddr16 amp laddr16 PSW byte PSW A A PSW Other than cases at left AC CY Transfers the contents of the source operand src specif
53. SP 3 SP 3 Cautions 1 In stack addressing the entire 64K byte space can be accessed but no stack area can be secured in the SFR area and internal ROM area 2 RESET input makes the SP undefined Anon maskable interrupt is also acknowledgeable immediately after reset release Therefore if a non maskable interrupt request is generated with the unstable SP immediately after reset release it may perform unexpected operation In order to minimize this risk be sure to perform the SP initialization immediately after reset release 53 78K ll SERIES USER S MANUAL 4 2 GENERAL REGISTERS 4 2 1 Configuration General registers are configured as four banks each containing eight 8 bit registers X A C B E D L H mapped onto a specific address area OFEEOH to 0FEFFH see Figure 4 6 Figure 4 6 General Register Configuration 8 bit processing 16 bit processing OFEEOH t Register bank 3 RBS1 0 11 4 T Register bank 2 RBS1 0 10 t Register bank 1 RBS1 0 01 t Register bank 0 RBS1 0 00 The register bank used when an instruction is executed is specified by a CPU control instruction SEL RBn When RESET is input register bank 0 is specified The register bank in use during instruction execution can be checked by reading the register bank selection flag RBSO 1 in the PSW The area O
54. X bit 0 PSW bit addr16 3 PC PC 3 jdisp8 if PSW bit 0 BTCLR saddr bit addr16 4 PC lt PC 4 jdisp8 if saddr bit 1 then reset saddr bit sfr bit addr16 4 PC lt PC 4 jdisp8 if sfr bit 1 then reset sfr bit A bit addr16 3 PC PC 3 jdisp8 if A bit 1 then reset A bit X bit addr16 3 PC PC 3 jdisp8 if X bit 1 then reset X bit PSW bit addr16 3 PC PC 3 jdisp8 if PSW bit 1 x x x then reset PSW bit DBNZ r1 addr16 2 r1 lt r1 1 then PC lt 2 jdisp8 if r1 z 0 saddr addr16 3 saddr lt saddr 1 100 then PC lt PC 3 jdisp8 if saddr 0 CHAPTER 7 INSTRUCTION SET 14 CPU control instructions MOV SEL NOP El DI Mnemonic Operand No of Operation Flags bytes 2 AC MOV STBC byte 4 STBC lt byte SEL RBn 2 RBS1 0 n n20 3 NOP 1 No operation EI 1 IE lt 1 Enable interrupts DI 1 IE lt 0 Disable interrupts 101 78K ll SERIES USER S MANUAL 7 1 5 Instruction Lists for Each Addressing 1 8 bit instructions MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MULU DIVUW INC DEC ROR ROL RORC ROLC SHR SHL ROR4 ROL4 DBNZ PUSH and POP Table 7 1 8 Bit Instructions for Each Addressing Type Second byte A r saddr sfr mem amp mem 16 amp 16 PSW n NoneNote 2 First operand d saddr operand A ADDNo
55. by NEC Corporation to know the specification of quality grade on the devices and its recommended applications 10 CHAPTER 1 78K II SERIES FEATURES 1 3 4 Function Outline Product name I uPD78218A uPD78P218A uPD78217A em Number of basic instructions mnemonics 65 Minimum instruction execution time 333 ns 500 ns at 12 MHz operation On chip memory capacity ROM 32K bytes 32K bytes PROM ROM less Mask ROM RAM 1024 byte Memory space Program 64K bytes data 1M byte pins Input 14 Output 12 Input output 28 10 Total 54 36 Additional Pins with pull up resistor 34 16 junction LED direct drive outputs 16 pinsNote Transistor direct drive outputs 8 ROM less mode setting EA pin low level ROM less product Real time output ports 4 bits x 2 or 8 bits x 1 General registers 8 bits x 8 x 4 banks memory mapped Timer counters 16 bit timer counters Timer register x 1 Pulse output Capture register x 1 capability Compare register x 2 Toggle output PWM PPG output One shot pulse output 8 bit timer counter 1 Timer register x 1 Pulse output Capture compare capability register x 1 Real time Compare register x 1 output 4 bits x 2 8 bit timer counter 2 Timer register x 1 Pulse output Capture register x 1 capability Compare register x 2 Toggle output PWM PPG output 8 bit timer counter 3 Timer register x 1 Compare register x 1 Serial inter
56. edge as specified by bit 0 ESNMI of external interrupt mode register 0 INTMO is input to the NMI pin nonmaskable interrupt request is unconditionally acknowledged even in the interrupt disable 01 state This kind of interrupt requestis not subjectto interrupt priority control and takes priority over all other interrupts 5 1 3 Maskable Interrupt Requests Maskable interrupt requests are controlled by the setting of the interrupt mask register In addition acknowledgment can be specified as enabled disabled for maskable interrupts as a whole by means of the IE flag in the PSW The order of priority when multiple maskable interrupt requests with the same priority are generated simultaneously is fixed default priority It is also possible to perform multiprocessing control by dividing interrupt priorities into a high priority group and a low priority group by means of the priority specification flag register PRO However macro servicing acknowledgment is performed without regard to priority control to the IE flag 60 CHAPTER 5 INTERRUPT FUNCTIONS 5 2 MACRO SERVICE FUNCTION In macro service when an interrupt is acknowledged CPU execution is temporarily suspended and the service set by firmware is executed As macro service is performed without CPU intervention it is not necessary to save restore CPU status information such as that held the PC and PSW This method is thus effective in improving the CPU service
57. fuzzy knowledge data converted by the translator Host machine OS Distribution medium Part number PC 9800 series MS DOS 5 25 inch 2HD uS5A10FI78K2 Ver 3 30 to 3 5 inch 2HD uS5A13FI78K2 Ver 5 00ANote IBM PC AT or See Section 9 2 2 4 5 25 inch 2HC uS7B10FI78K2 3 5 inch 2 uS7B13FI78K2 Fuzzy inference debugger FD78K lI This program performs fuzzy inference by linking with the fuzzy knowledge data at the hardware level using the in circuit emulator Host machine OS Distribution medium Part number PC 9800 series MS DOS 5 25 inch 2HD uS5A10FD78K2 Ver 3 30 to 3 5 inch 2HD uS5A13FD78K2 Ver 5 00ANote IBM PC AT or See Section 9 2 2 4 5 25 inch 2HC uS7B10FD78K2 compatibles 3 5 inch 2HC uS7B13FD78K2 Note Versions 5 00 and 5 00A feature a task swap function However the task swap function cannot be used with this software 248 APPENDIX INDEX OF INSTRUCTIONS MNEMONICS CLASSIFIED BY FUNCTION 8 bit data transfer instructions Shift rotate instructions 170 ROL 171 Qislcc 172 su 173 OH 174 175 176 iB 177 RBROR4222 178 s 179 MOWA pc 184 IND eee ee 185
58. incremented high order increment unchanged Macro service Macro service execution time of the uPD78214 series is the same as that of the uPD78224 series execution time Macro service execution time of the uPD78218A series is the same as that of the uPD78234 series or that of the uPD78244 series The execution time varies depending on the mode Compare these products by referencing their User s Manuals Restriction when Generated when transfer data is DOH to Generated when transfer Generated when transfer data is transferred DFH source buffer memory data is DOH to DFH from macro service address is OFEDOH to type A memory to OFEDFH SFR Standby function HALT STOP mode Oscillation stabi Fixed Choice of two times Fixed lization time after STOP mode release Pseudo SRAM Yes Refresh pulse width 1 Yes Refresh pulse refresh function width 1 5 Memory access None FC80H to FDFFH not restrictions accessible when refresh function is used ROM less mode EA pin EA pin setting low level low level low level low level Package e 64 pin plastic shrink DIP 750 mil 64 pin plastic shrink 84 pin plastic e 68 pin plastic QFJ 1950 mil DIP 750 mil 11150 mil uPD78212 64 pin plastic 94 pin plastic 64 pin plastic 14 x 14 mm body 14 x 14 mm body 20 x 20 mm body 74 pin plastic 20 x 20 mm bod
59. of shift bits 3 bit immediate data 0 7 Register bank RBO RB3 7 1 2 Operation Field 88 gt RO R7 AX BC DE HL RPO RP3 PC SP PSW CY AC Z RBS1 RBS0 IE Register A 8 bit accumulator Register X Register B Register Register D Register E Register Register L Register 0 to register 7 absolute name Register pair AX 16 bit accumulator Register pair BC Register pair DE Register pair HL Register pair 0 to register pair 3 absolute name Program counter Stack pointer Program status word Carry flag Auxiliary carry flag Zero flag Register bank selection flag Interrupt request enable flag CHAPTER 7 INSTRUCTION SET STBC Standby control register jdisp8 Signed 8 bit data displacement 128 to 127 Contents at address enclosed in parentheses or at address indicated in register enclosed in parentheses xxH Hexadecimal number XH xL Eight high order bits and eight low order bits of 16 bit register pair 7 1 3 Flag Field Blank No change 0 Cleared to zero 1 Set to 1 X Set or cleared according to the result R Saved values are restored 89 78K ll SERIES USER S MANUAL 7 1 4 List of Basic Instruction Operations 1 8 bit data transfer instructions MOV XCH Mnemonic
60. performed This is performed when a BR rp or CALL rp instruction is executed Illustration 65 78K ll SERIES USER S MANUAL 6 2 OPERAND ADDRESS ADDRESSING There are a number of methods addressing methods as described below for specifying the registers memory etc to be manipulated when an instruction is executed 6 2 1 Implied Addressing Function This addressing automatically addresses a register functioning as an accumulator A AX in the general register area 78K II series instructions which use implied addressing in the instruction word are shown below Instruction Register specified by implied addressing MULU A register as multiplicand AX register as register storing product DIVUW AX register as register storing dividend and quotient ADJBA ADJBS A register as register storing number subject to decimal adjustment ROR4 ROL4 A register as register storing digit data subject to digit rotation only low order 4 bits used Operand format As use is determined automatically according to the instruction there is no specific operand format Coding example MULU r lInan8 bitx8 bit multiplication instruction the product of the A register and r register is stored in AX The A and AX registers are specified by implied addressing 66 CHAPTER 6 ADDRESSING 6 2 2 Register Addressing Function This addressing method accesses as an operand the general register specified by the register specificati
61. the BR addr16 instruction or a conditional branch instruction is executed Illustration bytes of this instruction N jdisp8 2 bits 0 When 1 X all bits 1 63 78K ll SERIES USER S MANUAL 6 1 2 Immediate Addressing Function The immediate data in the instruction word is transferred to the program counter PC and a branch is performed This is performed when the CALL addr16 BR addr16 CALLF addr11 instruction is executed In the case of the CALLF addr11 instruction the high order 5 bit address is fixed at 00001 Illustration CALL or BR Low Addr High Adar 64 CHAPTER 6 ADDRESSING 6 1 3 Table Indirect Addressing Function The contents branch destination address ofthe table in the specific location addressed by the immediate data in the low order 5 bits of the operation code are transferred to the program counter and a branch is performed This is performed when the CALLT addr5 instruction is executed Illustration 7 54 0 Operation code 1 1 15 8 765 0 Effective address 00000000 m Memory Table Effective address Low Addr Effective address 1 High Addr 6 1 4 Register Addressing Function The contents of the register pair RPO to RP3 specified by the instruction word are transferred to the program counter PC and a branch is
62. the register bank selection flag RBS1 RBSO The addition is performed as addition of two 16 bit positive numbers if the register is 8 bits in length the contents of that register are extended to 16 bits as a positive number before the addition A carry out of the 16th bit is ignored The entire memory space including the 1M byte expansion data memory area can be addressed The kind of addressing is used for reading table data etc TABLE 4 TABLE 3 TABLE A 2 When 3H 1 TABLE Manipulate 4th data in the table using TABLE A Operand format Indexed addressing is used when executing an instruction with the operand formats shown below Identifier Description mem word A word B word DE word HL amp mem amp word A amp word B amp word DE amp word HL 83 78K ll SERIES USER S MANUAL Coding example General example 1 ADDC A mem Operation code 0000 1010 0 1001 Low Offset High Offset General example 2 SUBC A amp mem Operation code 0000 0001 0000 1010 0 mem Low Offset High Offset Specific example ADDC A 4010H DE When indexed addressing using the sum of register pair DE and 04010H as mem is selected Operation code 0000 1010 0000 1001 0001 0000 0100 0000 84 CHAPTER 6 ADDRESSING Illustrations 1 1M byte addressing without amp symbol In
63. uPD78P214GQ 36 used in combination with PG 1500 etc PA 78P214L PROM programmer adapter for uPD78P214L used in combination with PG 1500 etc PA 78P224GJ PROM programmer adapter for u PD78P224GJ 5BG used in combination with PG 1500 etc PA 78P224L PROM programmer adapter for uPD78P224L used in combination with PG 1500 etc PA 78P238GC PROM programmer adapter for u PD78P238GC 3B89 used in combination with PG 1500 etc PA78P238GJ PROM programmer adapter for u PD78P238GJ 5BG used in combination with PG 1500 etc PA 78P238KF PROM programmer adapter for u PD78P238KF used in combination with PG 1500 etc PA 78P238LQ PROM programmer adapter for uPD78P238LQ used in combination with PG 1500 etc 233 78K ll SERIES USER S MANUAL 9 2 2 Software 1 Language processing software 1 3 78 series relocatable This relocatable assembler can be used for all the 78K ll series products Its macro functions enhance efficiency in software development It also includes structured assembler which makes the program control structure more comprehensive thus improving software productivity and maintainability The relocatable assembler consists of the following programs assembler RA78K II 234 Structured assembler preprocessor program name ST78K2 Converts a source program written in the structured assembler language into a form that can be input to the relocatable a
64. 00110000 1 B2 Bo CY X bit 0000 00110000 0 B2 PSW bit 0000 00100000 0 Bz Bi saddr bit CY 0000 100 0 0 00 1 0 B2 lt Saddr offset gt sfr bit 0000 1000 0001 1 B2 1 lt Sfr offset gt A bit 0000 00110001 1 B2 X bit 0000 0011 0001 0 Be Bo PSW bit CY 0000 0010000 1 0 Bz AND1 CY saddr bit 0000 10000010 0 B2 lt Saddr offset gt saddr bit 0000 10000011 0 B2 lt Saddr offset gt sfr bit 0000 1000 0010 1 B2 1 lt Sfr offset gt sfr bit 0000 1000 0 01 1 1 B2 1 lt Sfr offset gt A bit 0000 00110010 1 B2 CY A bit 0000 00 1 1 00 1 1 1 B2 CY X bit 0000 001 10010 0 Be Bo CY X bit 0000 001 1 00 1 1 0 Be Bo CY PSW bit 0000 00100010 0 Be CY PSW bit 0000 0010 00 1 1 0 Be Bo Continued 118 CHAPTER 7 INSTRUCTION SET Operation code Mnemonic Operands B1 B2 B3 B4 B5 OR1 CY saddr bit 0000 1000 0100 0 B2 Bi lt Saddr offset gt saddr bit 0000 100 0 0 10 1 0 B2 Bi lt Saddr offset gt sfr bit 0000 1000 0100 1 B2 B Bo Sfr offset gt sfr bit 0000 10 00 01 01 1 B2 1 lt Sfr offset gt CY A bit 0000 001 10100 1 B2 B1Bo CY A bit 0000 00 11 01 0 1 1 B2 B1Bo CY X bit 0000 0
65. 0014H 00016H 00018H 0001AH 0001CH 00020H 00022H 00024H 00026H 00028H 0002AH 0003EH Notes 1 Except uPD78224 sub series 2 uPD78224 sub series only 3 uPD78244 sub series only 42 Interrupts Reset RESET input NMI INTP0 INTP1 INTP2 INTP3 INTP4 INTC30Note 1 INTP5 INTADNOote 1 INTC20Note 1 INTP6Note 2 INTC00 INTC01 INTC10 INTC11 INTC21 INTSER INTSR INTST INTCSI INTEERNote 3 INTEPWNote 3 BRK CHAPTER 3 MEMORY SPACE 3 4 CALLT INSTRUCTION TABLE AREA The 64 byte area from 00040H to 0007FH is used to store 1 byte call instruction CALLT subroutine entry addresses In the CALLT instruction this table is referenced and a branch is made to the address written in the table as a subroutine As the CALLT instruction is one byte in length the program object size can be compressed by using the CALLT instruction for subroutine calls which appear numerous times within a program As a maximum of 32 subroutine entry addresses can be written in the table it is recommended that they be registered in order to frequency of use If this area is not used as the CALLT instruction table it can be used as ordinary program memory or data memory 3 5 CALLF INSTRUCTION ENTRY TABLE The area from 00800H to 00FFFH can be accessed by a direct subroutine call by means of a 2 byte call instruction CALLF Since CALLF is a 2 byte call instruction the object size can be compressed compared with use of the direct subrouti
66. 00H to FFFFFH 078212 8 bytes 56704 bytes 00000H to 01FFFH 02000H to OFD7FH 078213 64768 bytes 512 bytes L 00000H to OFCFFH OFDOOH to OFEFFH uPD78214 78 214 EA L uPD78214 16K bytes 48384 bytes uPD78P214 00000H to O3FFFH 04000H to OFCFFH EA H Notes 1 Access in external memory expansion mode Common use with data memory is possible 2 Access in 1M byte expansion mode 3 1 2 uPD78218A Sub Series Memory Space Program memory Data memory Product name Internal ROM External memoryNote 1 Internal RAM External memoryNote 2 uPD78217A 64256 bytes 1024 bytes 960K bytes EA L 00000H to OFAFFH OFBOOH to OFEFFH 10000H to FFFFFH uPD78218A uPD78P218A EA L uPD78218A 32K bytes 31488 bytes uPD78P218 00000H to 07FFFH 08000H to OFAFFH EA H Notes1 Access in external memory expansion mode Common use with data memory is possible 2 Access in 1M byte expansion mode 38 CHAPTER 3 MEMORY SPACE 3 1 3 uPD78224 Sub Series Memory Space Program memory Data memory Product name Internal ROM External memoryNote 1 Internal RAM External memoryNote 2 uPD78220 64640 bytes 640 bytes 960K bytes EA L 00000H to OFC7FH OFC80H to OFC7FH 10000H to FFFFFH uPD78224 yu PD78P224 EA L uPD78224 16K bytes 48256 bytes uPD78P224 00000H to 03FFFH 04000H to 0FC7FH EA H Notes 1 Access in external memory expansion mode Common use with data memo
67. 01 1 0100 0 B2 B1Bo CY X bit 0000 00 11 01 0 1 0 Bz CY PSW bit 0000 0010 0100 0 B2 B1Bo CY PSW bit 0000 0010 0101 0 B2 XOR1 CY saddr bit 0000 1000 0110 0 B2 lt Saddr offset gt sfr bit 0000 100 0 0 110 1 B2 1 lt Sfr offset gt A bit 0000 00110110 1 B2 CY X bit 0000 001 1 01 10 0 Bz B1Bo CY PSW bit 0000 0010 0 11 0 0 B2 SET1 saddr bit 1011 0 B2 lt Saddr offset gt sfr bit 0000 1000 1000 1 B2 B Bo Sfr offset gt A bit 0000 001 11000 1 B2 B1Bo X bit 0000 001111000 0 B2 PSW bit 00 00 0010 1000 0 B2 B1Bo 01 00 0001 CLR1 saddr bit 10 10 0 B2 B Bo Saddr offset gt sfr bit 0000 100011001 1 B2 1 lt Sfr offset gt A bit 0000 00 1 1 100 1 1 B2 B1Bo X bit 0000 00 1 1 100 1 0 Bz PSW bit 0000 0010 1001 0 B2 CY 0100 0000 NOT1 sadar bit 0000 1000 0 11 1 0 Bi lt Saddr offset gt sfr bit 0000 10000111 1 B2 lt Sfr offset gt 0000 00110111 1 B2 X bit 0000 00110111 0 B2 PSW bit 00 00 0010 0 11 1 0 Bz 01 00 0010 119 78K ll SERIES USER S MANUAL 10 Call return instructions CALL CALLF CALLT RET RETI RETB Operation code Mnemonic Operands B1 B2 B3 B4 5 CALL laddr16 0010 10 0 0 lt Low Adar gt lt H
68. 14 15 20 21 20 21 14 151 20 21 20 21 14 15 20 21 20 21 11 Stack manipulation instructions PUSH POP MOVW INCW DECW Clock cycles Mnemonic Operands Bytes Internal ROM high speed fetch External ROM fetch IRAM PRAM EMEM IRAM PRAM EMEM PUSH PSW 1 Note Note Note Note Note Note sfr 2 7 9 9 9 12 12 1 8 9 12 13 12 13 8 9 12 13 12 13 PSW 1 6 8 8 6 8 8 sfr 2 9 11 11 9 12 12 1 11 12 15 16 15 16 11 12 15 16 15 16 MOVW SP word 4 8 8 8 12 12 12 SP 2 9 9 9 11 11 11 5 2 10 10 10 12 12 12 INCW SP 2 5 5 5 7 7 7 DECW SP 2 5 5 5 7 7 7 Note uPD78214 sub series and 78224 sub series 5 7 7 9 7 9 5 7 7 9 7 9 uPD78218A sub series 78234 sub series and 78244 sub series 6 8 8 6 8 8 133 SERIES USER S MANUAL 12 Unconditional branch instructions BR Mnemonic BR Clock cycles Internal ROM high speed fetch External ROM fetch Operands Bytes laddr16 3 rp 2 addr16 2 No branch Branch Internal ROM gt Internal ROM Internal ROM gt External ROM No branch Branch External ROM gt External ROM m Internal ROM External ROM 9 11 8 10 7 9 13 Conditional branch instructions BC BL BNC BNL BZ BE BNZ BNE BT BF BTCLR DBNZ Clock cycles Internal ROM high speed fetch External ROM fetch Mnemonic Operands Byte
69. 14 SUB SERIES PRODUCTS eee 3 12 17 Tp EE 3 1 2 2 ciii 3 1 2 3 Ordering Information and Quality Grade 4 1 2 4 Function Outline 6 1 2 5 Block Diagram uiii a 8 1 3 OUTLINE OF uPD78218A SUB SERIES PRODUCTS 9 ccc 9 1 9 2 ee e terit ooa are bet s bas 9 1 8 8 Ordering Information and Quality 2 10 1 9 4 OUTING pada eeu 11 1 85 Block u iere eo bat eee eee 13 1 4 OUTLINE OF uPD78224 SUB SERIES PRODUCTS 14 kat Irun 14 1 4 2 AD PIICATIONS uuu c 14 1 4 8 Ordering Information and Quality 15 T4 Function 16 14 5 Diagrami 17 1 5 OUTLINE OF uPD78234 SUB SERIES PRODUCTS 18 IET uc ne hee 18 ES MEN eene anes 18 1 5 8 Ordering Information and Quality 19 1 5 4 Function Obtling 21 15 5 Block uu e ts cd eed dined oe nodu 23 1 6 OUTLINE OF uPD78244 SUB SERIES PRODUCTS
70. 14 x 14 mm body 94 pin plastic QFP 20 x 20 mm body 84 pin plastic 1150 mil 94 pin ceramic WQFN 80 pin plastic 14 x 14 mm body 94 pin plastic 20 x 20 mm body 80 pin plastic 14 x 14 mm body 94 pin plastic 20 x 20 mm body Remark xxx is the ROM code number On chip ROM None None None Mask ROM Mask ROM Mask ROM None None None Mask ROM Mask ROM Mask ROM One time PROM One time PROM One time PROM EPROM Mask ROM Mask ROM Mask ROM Mask ROM 19 78K ll SERIES USER S MANUAL 2 Quality grade Ordering code Package Quality grade uPD78233GC 3B9 80 pin plastic QFP 14 x 14 mm body Standard uPD78233GJ 5BG 94 pin plastic QFP 20 x 20 mm body Standard uPD78233LQ 84 pin plastic QFJ 711150 mil Standard uPD78234GC xxx 3B9 80 pin plastic QFP 14 x 14 mm body Standard uPD78234GJ xxx 5BG 94 pin plastic QFP 20 x 20 mm body Standard uPD78234LQ xxx 84 pin plastic 711150 mil Standard uPD78237GC 3B9 80 pin plastic 14 x 14 mm body Standard uPD78237GJ 5BG 94 pin plastic QFP 20 x 20 mm body Standard uy PD78237LQ 84 pin plastic QFJ 111150 mil Standard uPD78238GC xxx 3B9 80 pin plastic QFP 14 x 14 mm body Standard uPD78238GJ xxx 5BG 94 pin plastic 20 x 20 mm body Standard u PD78238LQ xxx 84 pin plastic QFJ 111150 mil Standard uPD78P238GC 3B9 80 pin plastic 14 x 14 mm body Standard uPD78P238GJ 5BG 94 pin plastic
71. 2 of IE group 1 do not need to purchase the IE 78200 R EM the IE 78200 R EM board is built into the IE group 1 in circuit emulator IE 75000 R 3 Upgrading to IE 78220 R level is not allowed IE 75001 R Upgrading to IE 78230 R A is recommended IE 78000 R IE 78130 R IE 78140 R IE 78230 RNote 1 IE 78230 R A IE 78240 RNote 1 IE 78240 R A IE 78320 RNote 1 IE 78327 R IE 78330 R IE 78350 R IE 78600 R Notes 1 This product is no longer produced and is not available from NEC 2 This board is no longer produced and is not available from NEC Those users who do not have the IE 78220 R EM are recommended to upgrade to the IE 78230 R A level which includes the functions of IE 78230 R 244 CHAPTER 9 DEVELOPMENT TOOLS 9 3 6 Upgrading to IE 78210 RNote 1 Emulator IE 78112 RNote 1 IE 78220 RNote 1 IE group number 1 Level Required board IE 78210 R EMNote 2 Remarks IE 78310 RNote 1 IE 78310A R IE 78200 R EMNote 1 IE 78210 R EMNote 2 Those users who have an in circuit emulator of IE group 1 do not need to purchase the IE 78200 R EM the IE 78200 R EM board is built into the IE group 1 in circuit emulator IE 75000 R IE 75001 R IE 78000 R IE 78130 R IE 78140 R IE 78230 RNote 1 IE 78230 R A IE 78240 RNote 1 IE 78240 R A IE 78320 RNote 1 IE 78327 R IE 78330 R IE 78350 R IE 78600 R Upgrading to IE 78210 R level is not allowed Upgrading to IE 78240 R A is recommen
72. 210CWNote 1 series IE 78240 R IE 78240Note 4 EP 78240CW R PD78212Note 2 LPD78213 64QUIP EP 78210GQNote 1 uPD78214 EP 78240GQ R uPD78P214 64QFP EP 78210GCNote 1 14 x 14 mm body EP 78240GC R 68QFJ EP 78210L Note 1 EP 78240LP R 74QFP EP 78210GJNotes 1 6 20 x 20 mm body EP 78240GJ R uPD78218A sub 64SDIP IE 78240 R 1 78240 EP 78210CWNote 1 series EP 78240CW R uPD78217A uPD78218A 64QFP EP 78210GCNote 1 uPD78P218A 14 x 14 mm body EP 78240GC R uPD78224 sub 84QFJ IE 78220 R IE 78220Note 5 EP 78220LNote 1 series IE 78230 R IE 78230Note 5 EP 78230LQ R uPD78220 uPD78224 64QFP EP 78220GJNotes 1 7 uPD78P224 20 x 20 mm body EP 78230GJ R uPD78234 sub 80QFP IE 78230 R IE 78230 EP 78230GC R series 14 x 14 mm body uPD78233 uPD78234 84QFJ EP 78230LQ R 94 EP 78230GJ R uPD78P238 20 x 20 mm body 94WQFNNote 3 uPD78244 sub 64SDIP IE 78240 R 1 78240 EP 78210CWNote 1 series EP 78240CW R uPD78243 uPD78244 64QFP EP 78210GCNote 1 14 x 14 mm body EP 78240GC R Notes 1 No longer manufactured and not available for purchase 2 The uPD78212 package range comprises 64 pin SDIP 64 pin QFP and 74 pin QFP only 3 uPD78P2368 only 4 E 78210 R and IE 78240 R require IE 78210 and IE 78240 respectively 5 E 78220 R and IE 78230 R require IE 78220 and IE 78230 respectively 6 Requires EP 78210L or EP 78240LP R 7 Requires EP 78220L or EP 78230LQ R 228 CHAPTER 9 DEVELOPMENT TOOLS Conversion socketNote PROM programme
73. 42n SHR rn 2 3 2n 5 2 SHL rn 2 3 2n 5 2 SHRW rp n 2 3 3n 5 3 SHLW 2 3 3n 543n RORANote 2 24 32 32 32 26 34 34 34 amp 1 3 26 34 34 34 29 37 37 37 ROL4Note 2 25 33 33 33 27 35 35 35 amp 1 3 27 35 35 35 i 30 38 38 38 Note Cannot be used on uPD78244 sub series EEPROM area 130 CHAPTER 7 INSTRUCTION SET 8 BCD adjustment instructions ADJBA ADJBS Clock cycles Mnemonic Operands Internal ROM high speed fetch External ROM fetch Internal IRAM PRAM SFR 912 IRAM PRAM SFR ADJBA 3 3 ADJBS 3 3 Caution Internal ROM 9 Bit manipulation instructions MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 Clock cycles Mnemonic Operands Bytes Internal ROM high speed fetch External ROM fetch Internal Internal PRAM SFR PRAM SFR IEMEM MOV1 CY saddr bit 3 5 7 9 g CY sfr bit 3 7 11 A bit 2 5 7 CY X bit 2 CY P
74. 5 1 Interrupt Request Servicing Modes Interrupt request Servicing by PC PSW contents Servicing mode servicing mode Vectored interrupts Software According to save restore Executed after branching operation to desired service program Macro service Hardware Retained Execution of preset processing Firmware such data transfer etc Remark There are some interrupt request sources for which macro service cannot be used Please refer to individual product documentation for details 59 78K ll SERIES USER S MANUAL 5 1 INTERRUPT REQUESTS There are three kinds of interrupt request Software interrupt requests Nonmaskable interrupt requests Maskable interrupt requests 5 1 1 Software Interrupt Requests An interrupt request by software is generated by execution of a BRK instruction vectored interrupt An interrupt request generated by the BRK instruction can be acknowledged even in the interrupt disabled DI state These interrupts are not subject to interrupt priority control Therefore when the BRK instruction is executed the vector table contents are placed in the PC and a branch is performed unconditionally Nesting in its own routine is also possible by executing the BRK instruction in a BRK instruction service routine An RETB instruction is executed to return from the BRK instruction service routine 5 1 2 Nonmaskable Interrupt Requests A nonmaskable interrupt request is generated when a valid
75. 5 inch 2HD uS5A10DF78230 Not 3 5 inch 2HD uS5A13DF78230 IBM PC AT or See 4 5 25 inch 2HC uS7B10DF78230 compatibles 3 5 inch 2 uS7B13DF78230 PC 9800 series MS DOS Ver 3 30 to 5 25 inch 2HD uS5A10DF78240 Not SL ML 3 5 inch 2HD uS5A13DF78240 IBM PC AT or See 4 5 25 inch 2HC uS7B10DF78240 compatibles 3 5 inch 2 uS7B13DF78240 Note Versions 5 00 and 5 00A feature a task swap function However the task swap function cannot be used with this software 237 78K ll SERIES USER S MANUAL 2 Software for the in circuit emulator 2 2 In circuit emulator control program IE78210 IE78220 IE78234 IE78240 Notes 1 This program enables control of the in circuit emulator for the 78K ll series from the host machine It can automatically execute commands thus enhancing efficiency in debugging The following programs are available depending on the type of in circuit emulator Emulator Host machine OS Distribution medium Part number IE 78210 R PC 9800 series MS DOS 8 inch 2DNote 1 185 11 78210 01 Wer 31040 p op inch 3HD uS5A101E78210 P01 Ver 5 00ANote 2 3 5 inch 2HD uS5A131E78210 IBM PC AT See 4 5 25 inch 2DNote3 uS7B11IE78210 P02 compatibles 5 25 inch 2 187 101 78210 3 5 inch 2HC uS7B131E78210 IE 78220 R PC 9800 series MS DOS 8 inch 2DNote 1 185 11 78220 01 IF 8220 R EM wel S101 525
76. 6 8 X bit 2 PSW bit 2 5 7 CY 1 2 3 NOT1 saddr bit 2 6 10 10 14 sfr bit 3 10 16 A bit 2 6 8 X bit 2 PSW bit 2 5 7 CY 1 2 3 132 CHAPTER 7 INSTRUCTION SET 10 Call return instructions CALL CALLF CALLT RET RETI RETB Clock cycles Internal ROM high speed fetch External ROM fetch Mnemonic Operands Bytes Internal ROM Internal ROM External ROM External ROM Internal ROM External ROM Internal ROM External ROM IRAM IRAM PRAM EMEM IRAM PRAM PRAM EMEM CALL laddr16 3 11 12 15 16 15 16 12 13 16 17 16 17 15 16 19 20 19 20 17 18 21 22 21 22 rp 2 12 13 16 17 16 17 14 15 18 19 18 19 13 14 17 18 17 18 15 16 19 20 19 20 CALLF laddr11 2 11 12 15 16 15 16 12 13 16 17 16 17 14 15 18 19 18 19 CALLT addr5 1 14 15 18 19 18 19 16 17 20 21 20 21 14 15 18 18 120 21 24 25 24 25 1 16 17 22 23 22 23 18 19 24 25 24 25 17 18 23 24 23 24 22 24 28 30 28 30 18 24 124 20 26 26 19 25 25 1 10 11114 15 1415 11 12 15 16 15 16 10 11114 15 14 15 11 12 15 16 15 16 1 15 16 21 22 21 22 15 16 21 22 21 22 15 16 21 22 21 22 15 16 21 22 21 22 1 14 15 20 21 20 21
77. 78210 R EMNote IE 78230 R EM IE 78220 R EKMNote IE 78200 R EMKNote IE 782K00 R BK Boards enabling a 75X series or 78K series in circuit emulator to upgrade to another 78 series in circuit emulator For details see Section 9 3 Emulation board Target devices IE 78210 R EMNote uPD78214 sub series IE 78220 R EMNote uPD78224 sub series IE 78230 R EM uPD78224 sub series uPD78234 sub series IE 78240 R EM uPD78214 sub series uPD78218A sub series uPD78244 sub series EP 78210CWNote EP 78240CW R Emulation probes for uPD78214 sub series uPD78218A sub series and uPD78244 sub series 64 pin shrink DIP The EP 78240CW R is a long cabled version of the EP 78210CW EP 78210GCNote EP 78240GC R Emulation probes for uPD78214 sub series 78218 sub series and uPD78244 sub series for 64 pin QFP Used together with the EV 9200GC 64 The EP 78240GC R is a long cabled version of the EP 78210GC EP 78210GJNote Socket adapter for 78214 sub series 74 pin QFP Used together with the EP 78210L or EP 78240LP R and the EV 9200G 74 EP 78240GJ R Emulation probe for 1PD78214 sub series 74 pin QFP Used together with the EV 9200G 74 Unlike the 782100 this is a stand alone probe and is easy to handle EP 78210GQNote EP 78240GQ R Emulation probes for 78214 sub series 64 QUIP The EP 78240GQ R is a long cabled version of the EP 78210GQ EP 78210LNote EP 78240LP R
78. 8 2 Versions 5 00 and 5 00A feature a task swap function However the task swap function cannot be used with this software Caution To purchase the RX78K II you need to fill in a purchase form and enter into a use authorization contract in advance Remark When the RX78K II real time OS is used the RA78K Il assembler package available separately is necessary 247 78K ll SERIES USER S MANUAL 10 2 FUZZY INFERENCE DEVELOPMENT SUPPORT SYSTEM Fuzzy know ledge data creation tool Supports input and editing as well as the evaluation simulation of fuzzy knowledge data fuzzy rules and membership functions Host machine OS Distribution medium Part number PC 9800 series MS DOS 5 25 inch 2HD uS5A10FE9000 Ver 3 30 to 3 5 inch 2HD uS5A13FE9000 Ver 5 00ANote IBM PC AT or See Section 9 2 2 4 5 25 inch 2HC uS7B10FE9200 compatibies 3 5 inch 2HC uS7B13FE9200 Translator This program converts fuzzy knowledge data obtained with the fuzzy knowledge data creation tool into an assembler source program for the RA78K II Host machine OS Distribution medium Part number PC 9800 series MS DOS 5 25 inch 2HD uS5A10FT9080 Ver 3 30 to 3 5 inch 2HD uwS5A13FT9080 Ver 5 00ANote IBM PC AT or See Section 9 2 2 4 5 25 inch 2HC uS7B10FT9085 compatibles 3 5 inch 2HC uS7B13FT9085 Fuzzy inference module This program performs fuzzy inference by linking with the
79. AC lt 1 181 78K ll SERIES USER S MANUAL Decimal Adjust Register for Subtraction ADJBS Decimal Adjustment of Subtraction Result Instruction format ADJBS Operation Decimal Adjust Accumulator for Subtraction Operands None Flags Description Performs A register CY flag and AC flag decimal adjustment from the contents of the A register CY flag and AC flag The operation of this instruction is meaningful only when the result is stored the A register after subtraction of BCD binary coded decimal format data In other cases a meaningless operation is performed The adjustment method is shown in the table below f the contents of the A register are 0 as a result of the adjustment the Z is set 1 otherwise the Z flag is cleared 0 Condition Operation AC 0 0 lt A CY lt 0 lt 0 CY 1 lt 011000008 CY lt 1 AC lt 0 1 CY 0 A lt A 00000110B CY lt 0 AC lt 1 1 A lt A 01100110B CY lt 1 AC lt 1 182 CHAPTER 8 INSTRUCTION DESCRIPTIONS 8 9 BIT MANIPULATION INSTRUCTIONS Bit manipulation instructions are as follows MOV1 AND1 OR1 XOR1 SET1 NOT1 184 185 186 187 188 189 190 183 78K ll SERIES USER S MANUAL Move Single Bit MOV1 1 Bit Data Transfer Instruction format MOV1 dst src Operation dst l
80. ACE 3 1 MEMORY SPACE In the 78K ll series a 1M byte memory space can be accessed Program memory mapping differs according to the on chip memory capacity and pinNote statuses Therefore see Section 3 1 1 through Section 3 1 5 for details of memory map address areas Note uPD78214 sub series 78218A sub series 78224 sub series 78224 sub series 78244 sub series EA pin uPD78234 sub series MODE pin Notes 1 2 3 Figure 3 1 Memory Map o 7 o 5 o o m 5 2 External memoryNete 1 2 S 960K bytes S Y 10000H OFFFFH Special function registers SFR External SFR areaNete 2 gt gt gt 4 Internal RAM wo at o o T 3 F MEE gt _ gt 9 2 External memory gt JE 5 og _ Internal ROMNete 3 og as Y Y y 00000H Access in 1M byte expansion mode Internal memory Access in external memory expansion mode except uPD78224 sub series External data memory in uPD78213 78217A 78220 78233 78237 and 78243 ROM less products 37 78K ll SERIES USER S MANUAL 3 1 1 uPD78214 Sub Series Memory Space Program memory Data memory Product name Internal ROM External memoryNote 1 Internal RAM External memoryNote 2 078212 64896 bytes 384 bytes 960K bytes EA L 00000 to OFD7FH OFD80H to OFEFFH 100
81. ADD CR11 56H Adds 56H to the CR11 register and stores the result in the CR11 register 149 78K ll SERIES USER S MANUAL ADDC Add with Carry Byte Data Addition including Carry Instruction format ADDC dst src Operation dst CY lt dst src CY Operands Mnemonic Operands dst src ADDC A byte saddr byte sfr byte rr A saddr A sfr saddr saddr A mem A amp mem Flags Description Adds the source operand src specified by the 2nd operand and the CY flag to the destination operand dst specified by the 1st operand and stores the result in the destination operand dst and the CY flag The CY flag is added to the LSB This instruction is mainly used in multiple byte additions f dst is 0 as a result of the addition the Z flag is set 1 otherwise the Z flag is cleared 0 is generated out of bit 7 as a result of the addition the CY flag is set 1 otherwise the CY flag is cleared 0 is generated out of bit 3 into bit 4 as a result of the addition the AC flag is set 1 otherwise the AC flag is cleared 0 Coding example ADDC A 1234H B Adds the A register the contents of address 1234H B register and the CY flag and stores the result in the A register 150 CHAPTER 8 INSTRUCTION DESCRIPTIONS SUB Subtract Byte Data Subtraction Instruction f
82. AL FUNCTION REGISTER SFR sees 46 3 9 EXTERNAL SFR AREA EXCEPT uPD78224 SUB SERIES 46 3 10 EXTERNAL MEMORY SPAGE uu uuu aku devo gu 47 3 11 EXTERNAL EXPANSION DATA MEMORY 48 REGISTERS 51 4 1 CONTROL REGISIERS UN a M uui Pk a 51 4 1 1 Program Counter na 51 4 1 2 Program Status Word PSW uuu uuu 51 4 1 3 Stack Pointer SP eene eene nnns nnne 53 4 2 GENERAL REGISTERS retire bet exeo ashpa 54 421 GConflgukatlomiisi nr 54 42 2 FUMCUONS uuu 56 4 3 SPECIAL FUNCTION REGISTERS SER 22 57 INTERRUPT FUNCTIONS o terre 59 51 INTERRUPT REQUESTS 60 5 1 1 Software Interrupt 60 5 1 2 Nonmaskable Interrupt Requests 60 5 1 3 Maskable Interrupt Requests 60 5 2 MACRO SERVICE 00 assaka dua 61 ADDRESSING 63 6 1 INSTRUCTION ADDRESS 5 63 Relative u ete ret de rent 63 6 1 2 Immediate Addressing
83. Addr gt lt High Adar gt lt A amp laddr16 0000 00010000 10011 11 000 0 lt Low Addr gt lt High Addr gt Continued Note When DE HL DE DE HL or HL is written in mem or amp this comprises a special 1 byte code or 2 byte code respectively 109 78K ll SERIES USER S MANUAL Operation code Mnemonic Operands B1 B2 B3 B4 B5 MOV laddr16 0000 100 111111 000 1 lt Low gt lt High gt amp laddr16 0000 0001 0000 100111 11 000 1 lt Low Addr gt lt High Addr gt PSW byte 0010 1071 1711 1 1 11 10 lt Data gt PSW 00 01 00101111 1110 PSW 00 01 00001111 1110 0010 01 0 1 0 Re Rs Ra 0 RzRiRo 1101 1 R2 Ri Ro A saddr 0010 00 0 11 Saddr offset gt sfr 0000 0001 0010 00 01 lt Sfr offset gt saddr saddr 00 1 1 100 1 Saddr offset gt lt Saddr offset gt 00 0 0 mem 0 1 0 lt Low Offset gt lt High Offset gt A amp mem 0000 0001000 0 mod 010 0 lt Low Offset lt High Offset gt 110 CHAPTER 7 INSTRUCTION SET 2 16 bit data transfer instructions MOVW Operation code Mnemonic Operands B1 B2 B3 B4 B5 MOVW rp word 0110 P2 Pi 0 lt Low Byte gt lt High Byte gt saddrp word 00 00 11
84. Based addressing is used when executing an instruction with the operand formats shown below Identifier Description mem DE byte HL byte SP byte amp mem amp DE byte amp HL byte amp SP byte 80 CHAPTER 6 ADDRESSING Coding examples General example 1 AND A mem Operation code 0000 011 0 1100 Offset General example 2 CMP A amp mem Operation code 0000 0001 0000 011 0 Offset Specific example AND A DE 10H When based addressing using the sum of register pair DE and 10H as mem is o pu 2 Operation code 0000 0 1 1 0000 1100 0001 0000 81 78K ll SERIES USER S MANUAL Illustrations 1 1M byte addressing without amp symbol Register pair contents T 8 bit offset Remark n the uPD78224 sub series the low order 4 bits of the PM6 register are fixed at 0 Therefore only bank 0 can be accessed when the amp symbol is not used 2 1M byte addressing with amp symbol Register pair n 8 bit offset data Y Register pair contents 8 bit offset 82 CHAPTER 6 ADDRESSING 6 3 4 Indexed Addressing Function This addressing method addresses memory by using the 16 bit address data specified by the operand in the instruction word as the index and adding to this value the contents of the register specified in the instruction word in the register bank specified by
85. CY lt dsto 4517 lt 0 dstm 1 lt dstm x cnt times cnt 0 to 7 Operands Mnemonic Operands dst cnt SHR rn Flags Description Shifts to the right the contents of the destination operand dst specified by the 1st operand cnt times as specified by the 2nd operand 0 is shifted into the MSB bit 7 each time 1 bit is shifted fthe result of the shift operation is O the Z flag is set 1 otherwise the Z flag is cleared 0 The AC flag is always 0 regardless of the result of the shift operation The final data shifted out of the LSB bit 0 as a result of the shift operation is set in the CY flag fthe second operand cnt is 0 no processing is performed Z AC and CY flags also do not change This instruction gives the same result as dividing the destination operand dst by 2cnt CY 7 0 J Coding example SHR H 2 Shifts the contents of the H register 2 bits to the right 174 CHAPTER 8 INSTRUCTION DESCRIPTIONS Shift Left Logical SHL Byte Data Logical Left Shift Instruction format dst cnt Operation CY lt dst7 dsto lt 0 dstm 1 lt dstm x cnt times cnt 0 to 7 Operands Mnemonic Operands dst cnt SHL ron Flags Description Shifts to the left the contents of the destination operand dst specified by the 1st operand cnt times as specified by the 2nd operand 0 is shifted into the LSB bit 0 each time 1 bit is shifted
86. Description fthe contents of the 1st operand bit are set 1 branches to the address specified by the 2nd operand addr16 If the contents of the 1st operand bit are not set 1 no processing is performed and the next instruction is executed Coding example OFE47H 3 55CH Branches to 0055CH if bit 3 of address OFE47H is 1 the start of this instruction is in the address range from 004DAH to 005D9H 212 CHAPTER 8 INSTRUCTION DESCRIPTIONS Branch if False BF Conditional Branch depending on Bit Test Byte Data Bit 0 Instruction format BF bit addr16 Operation PC PC b jdisp8 if bit 0 Operands Mnemonic Operands bit addr16 b Number of bytes BF saddr bit addr16 sfr bit addr16 A bit addr16 X bit addr16 PSW bit addr16 A Flags Description f the contents of the 1st operand bit are cleared 0 branches to the address specified by the 2nd operand addr16 If the contents of the 1st operand bit are not cleared 0 no processing is performed and the next instruction is executed Coding example BF P2 2 1549H Branches to 01549H if bit 2 of port 2 is 0 the start of this instruction is in the address range from 014C6H to 015C5H 213 78K ll SERIES USER S MANUAL Branch if True and Clear BTCLR Conditional Branch and Clear depending on Bit Test Byte Data Bit 1 Instruction format BTCL
87. Emulation probes for 1PD78214 sub series 64 pin plastic QFJ The EP 78240LP R is a long cabled version of the EP 78210L EP 78220GJ Socket adapter for uPD78224 sub series 94 pin Used together with the EP 78220L or EP 78230LQ R and the EV 9200G 94 EP 78230GJ R Emulation probe for uPD78224 sub series and uPD78234 sub series 94 Used together with the EV 9200G 94 Unlike the EP 78220GJ this is a stand alone probe and is easy to handle EP 78220LNote Emulation probe for uPD78224 sub series and uPD78234 sub series 84 pin plastic QFJ No new orders are currently being accepted The EP 78230LQ R should be ordered instead Continued Note No longer manufactured and not available for purchase 231 78K ll SERIES USER S MANUAL 1 Relevant to in circuit emulator 3 3 EP 78230LQ R Emulation probe for uPD78224 sub series and uPD78234 sub series 84 pin plastic QFJ The EP 78230LQ R is a long cabled version of the EP 78220L for use with the uPD78234 sub series EP 78230GC R Emulation probe for uPD78234 sub series 80 pin Use together with the EV 9200GC 80 EV 9200GC 74 Socket mounted on user system board for 74 pin QFP use Used together with EP 78210GJ or EP 78240GJ R EV 9200GC 80 Socket mounted on user system board for 80 pin QFP use Used together with EP 78230GC R EV 9200G 94 Socket mounted on user system board for 94 pin QFP use Used together with E
88. FEEOH to OFEFFH can be addressed or accessed as a normal data memory irrespective of whether or not it is used as a general register 54 CHAPTER 4 REGISTERS Remark If it is necessary to return to the original register bank when the register bank is changed the SEL RBninstruction should be executed after saving the PSW to the stack usingthe PUSH PSW instruction If the stack location has not changed the POP PSW instruction can be used to return to the original register bank When the register bank is changed by an interrupt service program the PSW is saved to the stack automatically when the interrupt is acknowledged and is restored by the or RETB instruction Therefore when only one register bank is used by the interrupt service routine only the SEL RBn instruction need be executed and execution of the PUSH PSW and PSW instructions is not necessary Example 1 When register bank is changed by a normal program register Specifying register bank 2 PUSH PSW SEL RB2 Operated by register bank 2 POP PSW Operated by original register bank 2 When register bank is changed by an interrupt servicing program Specifying register bank 1 SEL 1 Operated by register bank 1 Restored automatically to original register bank when restoring to interrupt service program RETI 55 78K ll SERIES USER S MANUAL 4 2 2 Functions In addition to being manipulated as 8 bit units general registers can als
89. ION SET Example MOV r r Operation code 00100100 0 Re Rs Ra 0 Re Ri Ro When the A register is specified as the 1st operand and the L register as the 2nd operand the instruction is written as follows MOV A L Transfer L register contents to A register The operation code for this instruction is as follows Operation code 00100100 00010110 L register specification code A register specification code 107 78K ll SERIES USER S MANUAL 7 2 2 Operation Code When mem amp mem mem1 or amp mem1 1 Specified as Operand 1 Operation codes when mem or amp is written in operand field The codes assigned to mod and mem in the operation code field fixed for the contents written in mem or amp mem in the operand field are shown in Table 7 5 Table 7 5 Operation Codes for mem amp mem mem amp mem addressing mode Operation mode Addressing mode name Description mod mem Register indirect mode DE 1 0 1 1 0 0 HL 1 1 1 01 0 1 1 1 1 010 1 1 01 1 0 01 1 1 1 1 0 1 HL 1 0 1 Base mode DE byte 0 0 1 1 0 SP byte 0 1 1 01 0 0 1 HL byte 0 1 1 010 1 Indexed mode word DE 0 1 0 1 0 O word 0 1 1 01 0 1 word HL 0 1 0 1 010 1 O word B 0 1 1 01 0 1 1 2 Operation codes when or amp 1 is written in operand field The table below shows Ro or R1 in t
90. Inch PHD uS5A101E78220 P01 Ver 5 00ANote 2 3 5 inch 2HD uS5A131E78220 IBM PC AT See 4 5 25 inch 2DNote3 57811 278220 2 compatinies 5 25 inch 2HC 157 101 78220 02 3 5 inch 2HC uS7B13IE78220 P02 IE 78230 R PC 9800 series MS DOS 8 inch 2DNote 1 uS5A11E78230 ele S101 PHD uS5A101E78230 Ver 5 00ANote 2 3 5 inch 2HD uS5A131E78230 IBM PC AT See 4 5 25 inch 2DNote3 157 111 78230 compatibles 5 25 inch 2HC 187 101 78230 3 5 inch 2HC uS7B131E78230 IE 78240 R PC 9800 series MS DOS 8 inch 2DNote 1 uS5A11E78240 Wet 31019 BHD uS5A101E78240 Ver 5 00ANote 2 3 5 inch 2HD uS5A131E78240 IBM PC AT or compatibles See 4 5 25 inch 2DNote 3 uS7B111E78240 5 25 inch 2HC uS7B101IE78240 3 5 inch 2HC uS7B131E78240 The 8 inch 2D model has been superseded by the 5 25 inch 2HD and 3 5 inch 2HD models Those users who have already purchased an 8 inch 2D model will be supplied with a 5 25 inch 2HD or 3 5 inch 2HD model when the product is next upgraded 2 Versions 5 00 and 5 00A feature a task swap function However the task swap function cannot be used with this software 3 5 25 inch 2D model is no longer available Those users who have already purchased a 5 25 inch 2D model will be supplied with a 5 25 inch 2HC or 3 5 inch 2HC model when the product is next upgraded 238 CHAPTER 9 DEVELOPMENT TOOLS 3 Software for the PROM Programmer
91. K Series and 78K ll Series Composition 1 3 1 Memory u nsn aus E a 37 3 2 Internal RAM Mapping 45 3 3 Example of Inter Bank Data 49 3 4 Example of Inter Bank Data Transfer 50 4 1 Program Counter Configuration sse eene nennen nnne 51 4 2 Program Status Word Configuration 4222 0424 51 4 3 Stack Pointer 53 4 4 Data Saved to Stack 53 4 5 Data Restored from Stack Area insets nine 53 4 6 General Register Configuratio Misiista qalas 54 9 1 Development Tool Configuration nennen nnne 224 LIST OF TABLES Table No Title Page 3 1 Wall s n EP 42 3 2 Internal RAM Area in 78K ll Series Products 44 3 3 External Memory Space in 78K ll Series 47 4 1 Register Bank Selection uin a 52 4 2 Correspondence Between Function Names and Absolute Names 57 5 1 Interrupt Request Servicing Modes nnns 59 7 1 8 Bit Instructions for Each Addressing uu
92. Operand No of Operation Flags 7 MOV r byte 2 r lt byte saddr byte 3 saddr lt byte sfr byte 3 sfr byte pr 2 r lt r 1 lt 2 lt 2 saddr lt saddr saddr 3 saddr lt saddr A sfr 2 A lt sfr sfr A 2 sfr lt A A mem 1 4 A mem A amp mem 2 5 A amp mem mem A 1 4 mem A amp mem A 2 5 amp mem lt A A laddr16 4 A lt laddr16 A amp laddr16 5 A lt amp laddr16 laddr16 4 laddri6 A amp laddr16 5 amp laddr16 A PSW byte 3 PSW lt byte x x x PSW A 2 PSW lt x x x A PSW 2 A lt PSW XCH A r 1 lt r pr 2 r lt gt 2 4 lt amp 3 5 lt gt amp A saddr 2 lt gt saddr sfr 3 A lt gt sfr saddr saddr 3 saddr lt gt saddr 90 CHAPTER 7 INSTRUCTION SET 2 16 bit data transfer instructions MOVW Mnemonic MOVW Mnemonic ADD Operand No of Operation Flags 2 word 3 rp lt word saddrp word 4 saddrp lt word sfrp word 4 sfrp lt word rp rp 2 rp lt rp AX saddrp 2 AX lt saddrp saddrp AX 2 saddrp lt AX AX sfrp 2 AX lt sfrp sfrp AX 2 sfrp lt 2 lt 1 amp mem1 3 AX lt amp mem1 mem1 AXNote 2 mem1 lt AX amp mem1 AXNote 3
93. P 78220GJ or EP 78230GJ R EV 9200GC 64 Socket mounted on user system board for 64 pin QFP use Used together with EP 78210GC or EP 78240GC R EV 9900 Remarks 1 232 A jig used to remove the 78 238 from the EV 9200G 94 A pincer may be a substitute The use of the EV 9900 facilitates the work The use of two EV 9900 facilitates the work even more One EV 9200G 74 and EV 9200GC 64 are provided with the EP 78210GJ EP 78210GC EP 78240GC R and EP 78240GJ R One EV 9200G 94 and EV 9200GC 80 are provided with the EP 78220GJ EP 78230GJ R and EP 78230GC R The EV 9200G 74 EV 9200GC 64 EV 9200G 94 and EV 9200GC 80 are sold in sets of five ordered in units of a set CHAPTER 9 DEVELOPMENT TOOLS 2 PROM write tools PG 1500 PROM programmer which enables an on chip PROM single chip microcomputer to be programmed by stand alone or manipulation from the host machine connecting with an optional board and a programmer adapter separately sold And typical PROMs of 256K bits to 4M bits are programmable PA 78P214CW PROM adapter for LPD78P214CW 78P214DW 78P218ACW 78P218ADW used combination with PG 1500 etc PA 78P214GC PROM programmer adapter for uPD78P214GC AB8 and 78P218AGC ABE used in combination with PG 1500 etc PA 78P214GJ PROM programmer adapter for uPD78P214GJ 5BJ used in combination with PG 1500 etc PA 78P214GQ PROM programmer adapter for
94. PTER 9 DEVELOPMENT TOOLS 9 3 2 Upgrading to IE 78240 RNote 1 Level Emulator IE group number Required board Remarks IE 78112 RNote 1 1 IE 78240 R EMNote 2 The high speed download function is not IE 78210 RNote 1 supported Those users who are also using IE 78220 RNote 1 an in circuit emulator of IE group 4 are recommended to upgrade to IE group 4 level IE 78130 R 2 IE 78240 R EM IE 78230 RNote 1 IE 78310 RNote 1 3 IE 78200 R EMNote 1 The high speed download function is not IE 78310A R IE 78240 R EMNote 2 supported Those users who an in circuit emulator of IE group 1 do not need to purchase the IE 78200 R EM the IE 78200 R EM board is built into the IE group 1 in circuit emulator 1 75000 4 IE 78200 R EMNote 1 Those users who have emulator IE 75001 R IE 78240 R EM of IE group 1 do not need to purchase the IE 78000 R IE 78200 R EM the IE 78200 R EM board is IE 78320 RNote 1 built into the IE group 1 in circuit emulator IE 78327 R IE 78330 R IE 78350 R IE 78600 R IE 78140 R 5 IE 78200 R EMNote 1 Upgrading to IE 78240 R A level is IE 78230 R A IE 78240 R EM recommended Notes1 This product is no longer produced and is not available from NEC 2 This board is used for emulation for the uPD78214 sub series Those users who already have the IE 78210 R EMNote 1 do not have to purchase this board 241 78K ll SERIES USER S MANUAL 9 3 3 Upgrading
95. R area is mapped as the external SFR area In the case of a ROM less product or use of external memory expansion mode set by the memory expansion mode register MM in a product with on chip ROM externally connected peripheral I Os etc can be accessed using the address bus and address data bus As the external SFR area can be accessed by SFR addressing it has special characteristics such as allowing easy peripheral I O manipulation etc enabling the object size to be reduced and so forth Bus operations when accessing the external SFR area are the same as for ordinary memory accesses Caution There is no external SFR area in the uPD78224 sub series 46 CHAPTER 3 MEMORY SPACE 3 10 EXTERNAL MEMORY SPACE External memory space is memory space which can be accessed in accordance with the setting of the memory expansion mode register MM Itcan be used for storage of programs table data etc and allocation of peripheral devices Table 3 3 External Memory Space in 78K ll Series Products Product name uPD78212 External memory space 64896 bytes 02000H to OFD7FH uPD78213Note 64768 bytes 00000 to OFCFFH uPD78214 uPD78P214 48384 bytes 04000H to OFCFFH yu PD78217ANote 64256 bytes 00000H to OFAFFH uPD78218A uPD78P218A 31488 bytes 08000H to OFAFFH uPD78220Note 64640 bytes 00000H to OFC7FH uPD78224 uPD78P224 48256 bytes 04000H to OFC7FH uPD78233N
96. R bit addr16 Operation PC lt PC b jdisp8 if bit 1 then bit lt 0 Operands Mnemonic Operands bit addr16 b Number of bytes BTCLR saddr bit addr16 4 sfr bit addr16 4 A bit addr16 X bit addr16 3 PSW bit addr16 3 Flags bit PSW bit Other than cases at left 2 2 CY x x X Description e f the contents of the 1st operand bit are set 1 clears 0 the contents of the 1st operand bit and branches to the address specified by the 2nd operand If the contents of the 1st operand bit are not set 1 no processing is performed and the next instruction is executed f the 1st operand bit is PSW bit only the contents of the relevant flag are cleared 0 Coding example BTCLR PSW 0 356H If PSW bit 0 CY flag is 1 clears the CY flag and branches to address 00356H the start of this instruction is in the address range 002D4H to 003D3H 214 CHAPTER 8 INSTRUCTION DESCRIPTIONS Decrement and Branch if Not Zero DBNZ Conditional Loop R1 z 0 Instruction format DBNZ dst addr16 Operation dst dst 1 then PC lt PC b jdisp16 if dst R1 0 Operands Mnemonic Operands bit addr16 b Number of bytes DBNZ r1 lt addr16 2 saddr addr16 3 Flags Description Decrements by 1 the contents of the destination operand dst specified by the 1st operand and branches to the destination operand dst fthe resul
97. RETURN INSTRUCTIONS 191 8 11 STACK MANIPULATION 5 199 8 12 UNCONDITIONAL BRANCH INSTRUCTIONS esee 205 8 13 CONDITIONAL BRANCH INSTRUCTIONS sese 207 8 14 CPU CONTROL INSTRUCTIONS esses eene nennen nnne 216 DEVELOPMENT TOOLS I a 223 971 DEVELOPMENT TOOLS rae 223 9 2 OUTLINE OF TOOLS Ee 230 SEE 230 9 2 2 Software y u aa aaa STOAR Eia 234 9 33 UPGRADING OTHER IN CIRCUIT EMULATORS TO 78K ll SERIES LEVEL 240 9 3 1 Upgrading to IE 78240 R A Level 0 040 240 9 3 2 Upgrading to IE 78240 R 241 9 3 3 Upgrading to IE 78240 R A Level 242 9 3 4 Upgrading to IE 78230 R Level 243 9 3 5 Upgrading to E 78220 R Level tiie tect certet rie rete eere 244 9 3 6 Upgrading to IE 78210 R 245 BUILT IN SOFTWARE 247 10 1 REAL TIME ccm 247 10 2 FUZZY INFERENCE DEVELOPMENT SUPPORT SYSTEM 248 INDEX OF INSTRUCTIONS MNEMONICS CLASSIFIED BY FUNCTION 249 INDEX OF INSTRUCTIONS MNEMONICS IN ALPHABETICAL ORDER 251 REVISION HISTOR Y aare u u 253 LIST OF FIGURES Figure No Title Page 1 1 78
98. ROM One time PROM One time PROM One time PROM EPROM Mask ROM Mask ROM None None Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM One time PROM One time PROM CHAPTER 1 78K ll SERIES FEATURES 2 Quality grade Ordering code uPD78212CW xxx uPD78212GC xo AB8 uPD78212GJ xxx 5BJ uPD78213CW uPD78213GC AB8 uPD78213GJ uPD78213GQ 36 uPD78213L uPD78214CW xxx uPD78214GC xo AB8 uPD78214GJ xxx 5BJ 78214 0 36 782141 uPD78P214CW uPD78P214GC AB8 uPD78P214GJ uPD78P214GQ 36 uPD78P214L uPD78P214DW uPD78212CW A xxx uPD78212GC A o AB8 uPD78213CW A uPD78213GQ A 36 uPD78214CW A xxx 78214 8 uPD78214GJ A xxx 5BJ uPD78214GQ A xxx 36 uPD78214L A xxx uPD78P214CW A uPD78P214GC A AB8 Package 64 pin plastic shrink DIP 750 mil 64 pin plastic 14 x 14 mm body 74 pin plastic 20 x 20 mm body 64 pin plastic shrink DIP 750 mil 64 pin plastic 14 x 14 mm body 74 pin plastic 20 x 20 mm body 64 pin plastic QUIP 68 pin plastic QFJ 1950 mil 64 pin plastic shrink DIP 750 mil 64 pin plastic QFP 14 x 14 mm body 74 pin plastic QFP 20 x 20 mm body 64 pin plastic QUIP 68 pin plastic 950 mil 64 pin plastic shrink DIP 750 mil 64 pin plastic QFP 14 x 14 mm body 74 pin plastic QFP 20 x 20 mm body 64 pin plastic QUIP 68 pin plastic 7 950 mil 64 pin ceramic shrink DIP with window 750 mil 64 pin plastic shrin
99. SP This is a 16 bit register which holds the start address of the stack area LIFO method 00000H to 0FFFFH see Figure 4 3 The SP is used for addressing the stack area during subroutine or interrupt servicing SP contents are decremented before being written to the stack area and incremented after being read from the stack area see Figures 4 4 and 4 5 The SP is accessed by dedicated instructions Since SP contents are undefined after RESET input the SP should always be initialized by an initialization program immediately after reset release before issuing a subroutine call or acknowledging an interrupt Example initialization MOVW SP SP lt OFEEOH when used from FEDFH Figure 4 3 Stack Pointer Configuration 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Figure 4 4 Data Saved to Stack Area PUSH rp instruction CALL CALLF and CALLT instructions Interrupt Stack Stack Stack SP lt SP 2 SP SP 2 SP lt SP 3 SES 2 Register pair Low it 2 PC7 PCO ud 3 PC7 PCO Register pair Upper ud 1 PC15 PC8 ES 2 PC15 PC8 SP SP gt SRT 1 PSW SP Figure 4 5 Data Restored from Stack Area POP rp instruction RET instruction RETI instruction Stack Stack Stack SP Register pair Low SP 7 SP PC7 PCO SP 1 Register pair Upper 1 15 8 1 15 8 2 SP 2 one PSW SP SP 2 SP SP 2
100. SW bit 2 5 7 saddr bit 3 8 12 12 14 sfr bit CY 3 12 14 A bit CY 2 8 10 EET X bit CY 2 PSW bit CY 2 7 9 AND1 CY saddr bit 3 5 9 CY saddr bit 3 7 11 CY sfr bit 3 7 12 sfr bit 3 CY A bit 2 CY A bit 2 5 7 CY X bit 2 CY X bit 2 CY PSW bit 2 5 7 CY PSW bit 2 Continued 131 78K ll SERIES USER S MANUAL Clock cycles Mnemonic Operands Bytes Internal ROM high speed fetch External ROM fetch Internal Internal ROM IRAM PRAM SFR ROM IRAM PRAM SFR EMEM OR1 CY saddr bit 3 5 9 CY saddr bit 3 7 11 L sfr bit 3 7 12 CY sfr bit 3 CY A bit 2 CY A bit 2 5 7 CY X bit 2 CY X bit 2 CY PSW bit 2 5 7 CY PSW bit 2 XOR1 CY saddr bit 3 5 9 CY sfr bit 3 7 12 CY A bit 2 5 7 CY X bit 2 CY PSW bit 2 5 7 SET1 sadar bit 2 3 7 6 11 sfr bit 3 10 10 14 16 A bit 2 6 8 X bit 2 PSW bit 2 5 7 1 2 3 CLR1 saddr bit 2 3 7 6 11 sfr bit 3 10 10 14 16 A bit 2
101. To our customers Old Company Name in Catalogs and Other Documents On April 1 2010 NEC Electronics Corporation merged with Renesas Technology Corporation and Renesas Electronics Corporation took over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electronics website http www renesas com April 17 2010 Renesas Electronics Corporation Issued by Renesas Electronics Corporation http www renesas com Send any inquiries to http www renesas com inquiry 24 NC S AS 10 11 12 Notice All information included in this document 1 current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is gr
102. Z flag is cleared 0 f a borrow is generated in bit 7 as a result of the subtraction the CY flag is set 1 otherwise the CY flag is cleared 0 If aborrow is generated out of bit 4 into bit 3 as a result of the subtraction the AC flag is set 1 otherwise the AC flag is cleared 0 Coding example OFE38H OFEDOH Subtracts the contents of address OFEDOH from the contents of address OFE38H and performs flag modification only comparison of address OFE38H contents and address OFEDOH contents 156 CHAPTER 8 INSTRUCTION DESCRIPTIONS 8 4 16 BIT OPERATION INSTRUCTIONS 16 bit operation instructions are as follows ADDW 158 SUBW 159 CMPW 160 157 78K ll SERIES USER S MANUAL ADDW Add Word Word Data Addition Instruction format ADDW dst src Operation dst CY lt dst src Operands Mnemonic Operands dst src ADDW AX word AX rp AX saddrp AX sfrp Flags Description Adds the source operand src specified by the 2nd operand to the destination operand dst specified by the 1st operand and stores the result in the destination operand dst If dst is 0 as a result of the addition the Z flag is set 1 otherwise the Z flag is cleared 0 carry is generated out of bit 15 as a result of the addition the CY flag is set 1 otherwise the CY flag is cleared 0 The AC flag is undefined as a result of the addition Codin
103. a 74 CHAPTER 6 ADDRESSING Coding example General example 1 MOV A addr16 Operation code 0001 1001 1111 0000 Low Addr Low order 16 bit address High Addr General example 2 MOV A amp addr16 Operation code 0000 0001 0000 1001 1 0000 Low Addr Low order 16 bit address High Adar e Specific example MOV A 0FE00H When 0FE00H is used as addr16 Operation code 0000 1001 1 0000 0000 0000 a e A eu n 75 78K ll SERIES USER S MANUAL Illustrations 1 1M byte addressing without amp symbol 16 bit address data n w 16 bit address Remark n the uPD78224 sub series the low order 4 bits of the PM6 register are fixed at 0 Therefore only bank 0 can be accessed when the amp symbol is not used 2 1M byte addressing with amp symbol 16 bit address data n gt A 16 bit address 76 CHAPTER 6 ADDRESSING 6 3 2 Register Indirect Addressing Function This addressing method addresses the memory subject to manipulation whose output address is the register pair specified by the register pair specification code in the instruction word in the register bank specified by the register bank selection flag RBS1 RBSO This addressing method can be used on the entire memory space including the 1M byte expansion data memory area In addition register indirect addressing with auto increm
104. ackage uPD78243CW 64 pin plastic shrink DIP 750 mil uPD78243GC AB8 64 pin plastic QFP 14 x 14 mm body uPD78243CW xxx 64 pin plastic shrink DIP 750 mil uPD78243GC AB8 64 pin plastic QFP 14 x 14 mm body Remark xxx is the ROM code number On chip ROM None None Mask ROM Mask ROM Quality grade Standard Standard Standard Standard Please refer to Quality grade on NEC Semiconductor Devices Document number IEI 1209 published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications 25 78K ll SERIES USER S MANUAL 1 6 4 Function Outline Product name Item Number of basic instructions mnemonics uPD78244 uPD78243 Minimum instruction execution time 333 ns 500 ns at 12 MHz operation On chip memory capacity ROM 16K bytes ROM less EEPROM 512 bytes RAM 512 bytes Memory space Program 64K bytes data 1M byte I O pins Input 14 Output 12 Input output 28 10 Total 54 36 Additional Pins with pull up resistor 34 16 nciion LED direct drive outputs 16 pinsNote Transistor direct drive outputs 8 ROM less mode setting EA pin low level ROM less product Real time output ports 4 bits x 2 or 8 bits x 1 General registers 8 bits x 8 x 4 banks memory mapped Timer counters 16 bit timer counters Timer register x 1 Pulse output Capture register x 1 capability Compar
105. al ROM high speed fetch Instruction group Mnemonic Operands Bytes External ROM fetch Internal ROM IRAM PRAM SFR EMEM Internal ROM IRAM PRAM SFR EMEM 8 bit data transfer instruc tions Note A DE A HL A amp DE A amp HL 10 11 A DE A HL A DE A HL 8 9 10 10 10 9 10 11 amp DE A amp HL A amp A amp HL 10 11 12 12 13 12 13 14 A DE byte A HL byte 7 8 12 11 12 13 A amp DE byte A amp HL byte 9 10 11 11 15 14 15 16 A SP byte 8 9 10 10 10 13 12 13 14 gt amp SP byte 10 11 12 12 12 16 15 16 17 word A word B word DE word HL 7 8 15 16 gt gt gt gt gt amp word A A amp word B A amp word DE 9 10 11 11 18 19 A amp word HL Note The above figures apply when instructions with a short word length are used 136 When one byte word length is long Internal ROM fetch 1 cycle External ROM fetch 3 cycles CHAPTER 7 INSTRUCTION SET Instruction group 8 bit data transfer instruc tions Mnemonic Mov Note Table 7 6 Table of Instruction Execution Cycles 2 4 Operands DE HL Bytes Interna
106. also do not change This instruction gives the same result is dividing the destination operand dst by 2cnt CY 7 0 Coding example SHRW AX 3 Shifts the contents of the AX register 3 bits to the right divides the AX register contents by 8 176 CHAPTER 8 INSTRUCTION DESCRIPTIONS Shift Left Logical Word SHLW Word Data Logical Left Shift Instruction format dst cnt Operation CY lt dstis dsto lt 0 dstm 1 lt dstm x cnt times cnt 0 to 7 Operands Mnemonic Operands dst cnt SHLW rp n Flags Description Shifts to the left the contents of the destination operand dst specified by the 1st operand cnt times as specified by the 2nd operand 0 is shifted into the LSB bit 0 each time 1 bit is shifted f the result of the shift operation is 0 the Z flag is set 1 otherwise the Z flag is cleared 0 The flag is always 0 regardless of the result of the shift operation The final data shifted out of the MSB bit 15 as a result of the shift operation is set in the CY flag fthe second operand cnt is 0 no processing is performed Z AC and CY flags also do not change Coding example SHLW E 1 Shifts the contents of the E register 1 bit to the left 177 78K ll SERIES USER S MANUAL Rotate Right Digit ROR4 Digit Right Rotation Instruction format ROR4 dst Operation lt dst 3 o dst 7 4 lt
107. anted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this document b
108. are acknowledged between this instruction and the next instruction Acknowledgment of vectored interrupts from other sources can be disabled even when this instruction is executed Refer to individual documentation for details 220 CHAPTER 8 INSTRUCTION DESCRIPTIONS Disable interrupt DI Interrupt Disabling Instruction format DI Operation IE lt 0 Operands None Flags Description Disables acknowledgment of vectored maskable interrupts clears 0 the interrupt enable flag IE No interrupts or macro service requests are acknowledged between this instruction and the next instruction Refer to individual documentation for details of interrupt servicing 221 78K ll SERIES USER S MANUAL MEMO 222 CHAPTER 9 DEVELOPMENT TOOLS 9 1 DEVELOPMENT TOOLS The tools required for 78K ll series product development are shown in Figure 9 1 and Tables 9 1 and 9 2 223 78K ll SERIES USER S MANUAL Jojejnuje ue pejoeuuoo eq jouueo SMI SAS 00Z 008r SAA3 0065 7 004 seues 0006dH eui SMI v H 0F282 3l 10 02282 31 ueuw 440 10 uonoeuuoo 10 194908 2 H 02284 3l 10 H 0128 3l pesn eq 10 L 5910 0 euo e puejs se pesn SI d u9uM
109. area can be accessed at a higher speed than the rest of the memory space from an overall viewpoint its use is recommended in the applications mentioned above Note uPD78224 sub series 45 78K ll SERIES USER S MANUAL 3 7 EEPROM AREA uPD78244 SUB SERIES ONLY The 512 byte area from OFBOOH to OFCFFH has EEPROM mapped onto it EEPROM is memory which can be written to or read by a program and which unlike internal RAM retains data in the event of a power failure Caution The following instructions cannot be used on this area MOVW MOVW amp meml AX ROR4 ROR4 amp meml ROL4 ROL4 amp 3 8 SPECIAL FUNCTION REGISTER SFR AREA The area from 0FF00H to 0FFFFH has on chip peripheral hardware special function registers SFRs mapped onto it see documentation for individual products With the exception of uPD78224 sub series products the area from 0FFD0H to 0FFDFH is mapped as the external SFR area and allows access to externally connected peripheral I Os etc in a ROM less product or in external memory expansion mode set by the memory expansion mode register MM in a product with on chip ROM Caution Addresses in this area which are not mapped as SFRs should not be accessed An illegal access may result in CPU deadlock A deadlock state can be released by reset input only 3 9 EXTERNAL SFR AREA EXCEPT uPD78224 SUB SERIES The 16 byte area from OFFDOH to OFFDFH within the SF
110. ator for the 78K ll series when used together with SD78K II the device file It can be used when the in circuit emulator has been upgraded to IE 78230 R A or IE 78240 R A class and a PC 9800 series or IBM PC AT computer is being used as a host computer This debugger can debug source programs written in C structured assembly language and assembly language Its split screen function by which the screen is split into sections to enable the simultaneous display of different information makes debugging more efficient Host machine OS Distribution medium Part number PC 9800 series MS DOS Ver 3 30 5 25 inch 2HD uS5A10SD78K2 Not Mar 3 5 inch 2HD uS5A13SD78K2 IBM PC AT or See 4 5 25 inch 2HC uS7B10SD78K2 3 5 inch 2 uS7B13SD78K2 Device file This is used together with the screen debugger SD78K II to debug programs of the DF78210 uPD78214 sub series DF78220 Host machine 05 Distribution medium Part number DF78230 DF78240 PC 9800 series MS DOS Ver 3 30 to 5 25 inch 2HD uS5A10DF78210 Not 3 5 inch 2HD uS5A13DF78210 IBM PC AT or See 4 5 25 inch 2HC uS7B10DF78210 compatioles 3 5 inch 2 uS7B13DF78210 PC 9800 series MS DOS Ver 3 30 to 5 25 inch 2HD uS5A10DF78220 Not VERUM 3 5 inch 2HD uS5A13DF78220 IBM PC AT or See 4 5 25 inch 2HC uS7B10DF78220 compatioles 3 5 inch 2 uS7B13DF78220 PC 9800 series MS DOS Ver 3 30 5 2
111. ay as IE 78230 R A by purchasing the board separately sold IE In circuit emulator Target devices IE 78240 R A uPD78214 sub series 1PD78218A sub series uPD78244 sub series 1 78230 uPD78224 sub series uPD78234 sub series IE 78240 RNote IE 78210 RNote IE 78230 RNote IE 78220 RNote In circuit emulators for the 78K ll series The target devices of each emulator are shown below Purchase of the separately available emulation board allows conversion to a different 78K II series in circuit emulator The in circuit emulator is connected to a host machine or console to perform debugging Connecting the in circuit emulator to a host machine allows symbolic debugging and object file exchange with the host machine enabling highly efficient debugging to be performed Two RS 232 C serial interface channels are incorporated allowing the connection of a PG 1500 PROM programmer The IE 78230 R and IE 78240 R also incorporate a Centronics interface allowing high speed object file and symbol file downloading In circuit emulator Target devices IE 78210 RNote uPD78214 sub series IE78220 RNote uPD78224 sub series IE 78230 RNote uPD78224 sub series uPD78234 sub series IE 78240 RNote uPD78214 sub series uPD78218A sub series uPD78244 sub series Continued Note No longer manufactured and not available for purchase 230 CHAPTER 9 DEVELOPMENT TOOLS 1 Relevant to in circuit emulator 2 3 IE 78240 R EM IE
112. bility of its semiconductor devices the possibility of defects cannot be eliminated entirely To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device customer must incorporate sufficient safety measures in its design such as redundancy fire containment and anti failure features NEC devices are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to devices developed based on customer designated quality assurance program for a specific application The recommended applications of a device depend on its quality grade as indicated below Customers must check the quality grade of each device before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircrafts aerospace equipment submersible repeaters nuclear reactor control systems life support systems or medical equipment for life support etc The quality grade of NEC devices in Standard unless otherwise
113. bit x CY X bit 2 CY CY A X bit x CY PSW bit 2 CY lt CY PSW bit X CY PSW bit 2 CY CY PSW bit x Continued 96 CHAPTER 7 INSTRUCTION SET Mnemonic Operand No of Operation Flags Z 1 CY saddr bit 3 CY lt CY v saddr bit x CY saddr bit 3 CY lt CY saddr bit sfr bit 3 CY lt CY v sfr bit x CY sfr bit 3 CY lt CY v sfr bit A bit 2 CY CY v Abit x CY A bit 2 CY CY v A bit x CY X bit 2 CY lt CY v x CY X bit 2 CY lt CY v X bit x CY PSW bit 2 CY CY v PSW bit x CY PSW bit 2 CY CY v PSW bit x XOR1 CY saddr bit 3 lt CY saddr bit sfr bit 3 CY lt CY sfr bit x CY A bit 2 CY CY lt A bit x CY X bit 2 CY CY lt X bit x CY PSW bit 2 CY CY PSW bit x SET1 saddr bit 2 saddr bit lt 1 sfr bit 3 sfr bit lt 1 A bit 2 A bit lt 1 X bit 2 X bit lt 1 PSW bit 2 PSW bit lt 1 x x 1 lt 1 1 CLR1 saddr bit 2 saddr bit lt 0 sfr bit 3 sfr bit 0 A bit 2 A bit 0 X bit 2 X bit lt 0 PSW bit 2 PSW bit 0 x x x 1 lt 0 0 NOT1 saddr bit 3 saddr bit lt saddr bit sfr bit 3 sfr bit sfr bit A bit 2 A bit A bit X bit 2 X bit X bit PSW bit 2 PSW bit PSW bit x x x CY 1 CY lt CY x
114. bling Do not allow MOS devices to stand on plastic plates or do not touch pins Also handle boards on which MOS devices are mounted in the same way 2 CMOS specific handling of unused input pins Caution Hold CMOS devices at a fixed input level Unlike bipolar or NMOS devices if a CMOS device is operated with no input an intermediate level input may be caused by noise This allows current to flow in the CMOS device resulting in a malfunction Use a pull up or pull down resistor to hold a fixed input level Since unused pins may function as output pins at unexpected times each unused pin should be separately connected to the Vpp or GND pin through a resistor If handling of unused pins is documented follow the instructions in the document 8 Statuses of all MOS devices at initialization Caution The initial status of a MOS device is unpredictable when power is turned on Since characteristics of a MOS device are determined by the amount of ions implanted in molecules the initial status cannot be determined in the manufacture process NEC has no responsibility for the output statuses of pins input and output settings and the contents of registers at power on However NEC assures operation after reset and items for mode setting if they are defined When you turn on a device having a reset function be sure to reset the device first MS DOS and Windows are trademarks of Microsoft Corporation IBM DOS PC AT and PC DOS are
115. cannot be performed by an in circuit emulator if 0 is not set 48 CHAPTER 3 MEMORY SPACE Example 1 HuPD78224 sub series inter bank data transfer To select bank 5 as the expansion bank and transfer bank 5 data to bank 0 MOV MM 47 Set memory expansion mode MOV PM6 0H Low order 4 bits of PM6 always set to 0 MOV P6 5H Subsidiary bank register P6 setting MOV Loop counter setting LOOP MOV A amp HL Read from bank 5 P6 register contents added as maximum address information MOV DE Store data in bank 0 instruction without amp accesses bank 0 DBNZ B LOOP Repeat processing Figure 3 3 Example of Inter Bank Data Transfer Bank 0 Bank 5 main data bank subsidiary data bank 00000H 50000H MOV DE MOV A amp HL A register Remark Both banks of MOV DE and MOV A amp HL are stored 0 49 78K ll SERIES USER S MANUAL Example 2 Inter bank data transfer in non uPD78224 sub series product Toselectbank 1 as the main bank and bank 5 as the subsidiary bank and transfer bank 5 data to bank 1 MOV 47H Set memory expansion mode MOV PM6 1H Main bank register PM6 setting MOV P6 5H Subsidiary bank register P6 setting MOV B Loop counter setting LOOP MOV A amp HL Read from bank 5 P6 register contents added as maximum address information MOV DE
116. ce equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under
117. certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electr
118. ch 2D model will be supplied with a 5 25 inch 2HD or 3 5 inch 2HD model when the product is next upgraded 2 The 5 25 inch 2D model is no longer available Those users who have already purchased a 5 25 inch 2D model will be supplied with a 5 25 inch 2HC or 3 5 inch 2HC model when the product is next upgraded 3 Versions 5 00 and 5 00A feature a task swap function However the task swap function cannot be used with this software 235 78K ll SERIES USER S MANUAL 1 Language processing software 3 3 This source program is used to modify the libraries supplied with CC78K ll to satisfy user 78K II series C compiler library source file CC78K II L EWS 4800 series RISC Note Versions 5 00 and 5 00A feature a task swap function However the task swap function cannot be specifications Host machine OS Distribution medium Part number PC 9800 series MS DOS Ver 3 30 5 25 inch 2HD uS5A10CC78K2 L 3 5 inch 2HD uS5A13CC78K2 L IBM PC AT or See 4 5 25 inch 2HC uS7B10CC78K2 L compatibles 3 5 inch 2HC uS7B13CC78K2 L HP9000 series 700 HP UX rel 9 01 DAT uS3P16CC78K2 L SPARCstation SunOS rel 4 1 1 used with this software 236 EWS UX V rel 4 0 Cartridge tape QIC 24 uS3K15CC78K2 L uS3M15CC78K2 L CHAPTER 9 DEVELOPMENT TOOLS 2 Software for the in circuit emulator 1 2 Screen debugger This program controls the in circuit emul
119. ction as timer counter 3 Yes Dedicated Yes No baud rate generator External Yes No baud rate clock input Real time output ports 32 4 bits x 2 or 8 bits x 1 CHAPTER 2 78 SERIES PRODUCTS 2 3 uPD78234 sub series uPD78244 sub series uPD78233 uPD78234 uPD78237 uPD78238 uPD78P238 uPD78243 uPD78244 12 bits x 2 None 8 bits x 8 Can be selected arbitrarily Select according to the operating frequency 3 4 V to 3 6 V to Pin voltage from 0 V to AVrer for pins subject to A D conversion only during A D conversion 8 bits x 2 None Yes Yes 16 bytes OFFDOH to OFFDFH 1 channel 1 channel for SBI Yes Dual function as timer counter 3 Yes Yes 4 bits x 2 or 8 bits x 1 33 78K ll SERIES USER S MANUAL Sub series name uPD78214 sub series uPD78218A sub series uPD78224 sub series Product 78212 uPD78213 uPD78214 wPD78217A uPD78218A wPD78220 uPD78224 Item uPD78P214 uPD78P218A uPD78P224 Interrupts 2 levels programmable vectored macro service External 7 8 Internal 12 9 Interrupts permitted 15 6 use of macro service Macro service 8 bits only 8 16 bits selectable 8 bits only counter bits except Type A Macro service Only low order 8 bits incremented 16 bits incremented Only low order 8 bits type C MPD MPT high order unchanged
120. de instructions MULU DIVUW Mnemonic Operand No of Operation Flags bytes 2 MULU r 2 AX Axr DIVUW r 2 AX quotient r remainder AX r When r 0 r X AX lt OFFFFH 6 Increment decrement instructions INC DEC INCW DECW Mnemonic Operand No of Operation Flags bytes 7 INC r 1 r lt r 1 x x saddr 2 saddr lt saddr 1 x x DEC r 1 r lt r 1 X x saddr 2 saddr lt saddr 1 x x INCW rp 1 rp lt rp 1 DECW rp 1 rp lt rp 1 7 Shift rotate instructions ROR ROL RORC ROLC SHR SHL SHRW SHLW ROR4 ROL4 Mnemonic Operand No of Operation Flags bytes Z AC CY ROR rn 2 CY r7 lt ro rm 1 rm x n times n 0 to 7 x ROL rn 2 CY ro rz 1 rm x n times n 0 to 7 x RORC rn 2 CY lt ro rz lt CY 1 lt rm x n times n 0 to 7 X ROLC rn 2 CY lt 17 10 CY 1 lt rm x n times n 0 to 7 X SHR rn 2 CY lt 10 17 lt 0 rm 1 lt rm x n times n 0 to 7 x 0 X SHL rn 2 CY lt 17 10 0 1 lt rm x n times 0 to 7 x 0 x SHRW rp n 2 lt 15 lt 0 rpm 1 lt rpm n times 0 to 7 x 0 X SHLW rp n 2 CY lt 15 rpo lt 0 rpm 1 lt rpm x n times n 0 to 7 x 0 x ROR4Note mem1 2 lt 1 mem1 7 4 lt mem1 3 o mem1 7 4 amp mem1 3 lt amp 1
121. ded Notes 1 This product is no longer produced and is not available from NEC 2 This board is no longer produced and is not available from NEC Those users who do not have the IE 78210 R EM are recommended to upgrade to the IE 78240 R A level which includes the functions of IE 78240 R 245 78K ll SERIES USER S MANUAL MEMO 246 CHAPTER 10 BUILT IN SOFTWARE 10 1 REAL TIME OS Real time OS The RX78K II is intended to achieve a multitask environment for control fields which require RX78K II real time control CPU idle time can be assigned to other processing allowing overall system performance to be improved The RX78K II offers 31 system calls compliant with the specifications The RX78K II package provides a tool configurator to create the RX78K II nucleus and multiple information tables However the use of this requires RAM of 1K byte or moreNote 1 Host machine OS Distribution medium Part number PC 9800 series MS DOS 5 25 inch 2HD uS5A10RX78217 Ver 3 30 to 3 5 inch 2HD uS5A13RX78217 Ver 5 00ANote 2 IBM PC AT or See Section 9 2 2 4 5 25 inch 2HC uS7B10RX78217 3 5 2HC uS7B13RX78217 HP9000 series 700 HP UX rel 9 01 DAT uS3P16RX78217 SPARCstation SunOS rel 4 1 1 Cartridge tape uS3K15RX78217 Bc series EWS UX V rel 4 0 uS3M15RX78217 Notes1 Target devices uPD78217A 78218A 78P218A 78237 78238 78P23
122. dex address n RegisterNote Index address Register contents Remark In the 78224 sub series the low order 4 bits of the PM6 register are fixed at 0 Therefore only bank 0 can be accessed when the amp symbol is not used 2 1M byte addressing with amp symbol Index address n RegisterNote r Index address Register contents Note 8 bit register or 16 bit register 8 bit register pair 85 78K ll SERIES USER S MANUAL MEMO 86 CHAPTER 7 INSTRUCTION SET This chapter lists the 78K ll series instruction set The same instructions are used on all 78K ll series products 7 1 OPERATIONS 7 1 1 Representation Format and Description Method Code operands in the operand field for each instruction using the specified operand representation format for details refer to the relevant assembler specifications When several coding forms are presented any one can be used Since uppercase letters and symbols and amp are keywords write any symbols as is Do not omit symbols amp when writing immediate data with labels r and rp can be written with any functional and absolute names rp sfr sfrp mem mem1 Auto increment Auto decrement Immediate data Absolute addressing Relative addressing Bit inversion Indirect addressing Sub bank specification Reg
123. dr 0111 111 11 lt Saddr offset gt lt Saddr offset gt 000 0 11 1 1 lt Low Offset gt lt High Offset gt amp mem 0000 0001000 mod 0 mem 1 11 1 Low Offset gt lt High Offset gt Continued 115 78K ll SERIES USER S MANUAL 4 16 bit operation instructions ADDW SUBW CMPW Operation code Mnemonic Operands B1 B2 B3 B4 B5 ADDW AX word 0010 110 1 Low Byte gt lt High Byte gt 1000 1000 0000 1 2 Pi 0 AX saddrp 00 01 110 1 lt Saddr offset gt sfrp 0000 0001 0001 1 1 0 1 lt Sfr offset gt SUBW AX word 00 10 11 1 0 Low Byte lt High Byte gt 1000 1010 0000 1 PeP10 AX saddrp 00 01 11 1 O lt Saddr offset gt sfrp 0000 0001 0001 1110 Sfr offset gt CMPW AX word 0010 111 1 Low Byte gt lt High Byte gt 1000 1111 0000 1 P2P10 AX saddrp 00 01 11 1 1 lt Saddr offset gt sfrp 0000 0001 0001 111 1 lt Sfr offset gt 5 Multiplication division instructions MULU DIVUW Operation code Mnemonic Operands B1 B2 B3 B4 B5 MULU r 0000 010110000 1 R2RiRo DIVUW r 0000 01 0 1 00 0 1 1 R2 Ro 116 CHAPTER 7 INSTRUCTION SET 6 Increment decrement instructions INC DEC INCW DECW Operation code
124. dthe address of the next instruction PC 1 are saved to the stack then the IE flag is cleared 0 and a branch is made to the address indicated by the vector address 0003EH word data As the IE flag is cleared 0 subsequent maskable vectored interrupts are disabled Return from a software vectored interrupt generated by this instruction is performed by the RETB instruction 195 78K ll SERIES USER S MANUAL Return RET Return from Subroutine Instruction format RET Operation PCL lt SP PCH lt SP 1 SP lt SP 2 Operands None Flags Description This instruction is used to return from a subroutine called by the CALL CALLF or CALLT instruction The word data saved to the stack is restored to the PC and a return is made from the subroutine 196 CHAPTER 8 INSTRUCTION DESCRIPTIONS Return from Interrupt RETI Return from Hardware Vectored Interrupt Instruction format RETI Operation PCL lt SP PCH lt SP 1 PSW lt SP 2 SP lt Operands None Flags Description This instruction is used to return from a vectored interrupt The data saved to the stack is restored to the PC and PSW the NMIS flag in the IST register is cleared 0 and a return is made from the interrupt service routine This instruction cannot be used to return from a software interrupt generated by the BRK instruction Nointerrupts or macro ser
125. e register x 2 Toggle output PWM PPG output One shot pulse output 8 bit timer counter 1 Timer register x 1 Pulse output Capture compare capability register x 1 Real time Compare register x 1 output 4 bits x 2 8 bit timer counter 2 Timer register x 1 Pulse output Capture register x 1 capability Compare register x 2 Toggle output PWM PPG output 8 bit timer counter 3 Timer register x 1 Compare register x 1 Continued Note Additional function pins are included in the I O pins 26 CHAPTER 1 78K ll SERIES FEATURES Product name uPD78244 em Serial interface UART 1 channel incorporating dedicated baud rate generator CSI 3 wire serial SBI 1 channel uPD78243 A D converter 8 bit resolution x 8 channels Interrupts 21 sources 7 external 14 internal BRK instruction 2 level priority programmable 2 servicing modes vectored interrupts macro service Instruction set 16 bit operation Multiply divide 8 bits x 8 bits 16 bits 8 bits Bit manipulation BCD adjustment etc Package 64 pin plastic shrink DIP 750 mil 64 pin plastic QFP 14 x 14 mm body 27 78K ll SERIES USER S MANUAL 1 6 5 Block Diagram 1 992 SZd Z9d 8 9d ZSd Zvd Z d 0 4 OSd Otd 05 41419395 Z d Z0d 004 18 11 va
126. e result in the CY flag 186 Obtains the logical sum of the logical negation of bit 0 of the X register and the CY flag CHAPTER 8 INSTRUCTION DESCRIPTIONS Exclusive Or Single Bit XOR1 1 Bit Data Exclusive Logical Sum Instruction format XOR1 dst src Operation dst lt dst v src Operands Mnemonic Operands dst src XOR1 CY saddr bit CY sfr bit CY A bit CY X bit CY PSW bit Flags Description Obtains the exclusive logical sum of the bit data of the destination operand dst specified by the 1st operand and the source operand src specified by the 2nd operand and stores the result in the destination operand dst The result of the operation is stored in the CY flag since it is the destination operand dst Coding example XOR1 CY A 7 Obtains the exclusive logical sum of bit 7 of the A register and the CY flag and stores the result in the CY flag 187 78K ll SERIES USER S MANUAL Set Single Bit Carry Flag SET1 1 Bit Data Setting Instruction format 5 1 dst Operation dst lt 1 Operands Mnemonic Operands dst src SET1 saddr bit sfr bit A bit X bit PSW bit CY Flags dst PSW bit dst CY Other than cases at left Z AC CY 2 CY 7 x x x 1 Description Sets 1 the destination operand dst If the destination operand dst is CY or PSW bit only the relevant flag is set 1 Codin
127. ent and register indirect addressing with auto decrement are provided The former increments and the latter decrements the addressed register pair DE HL by 1 after execution of the instruction These addressing methods are ideal for processing of multiple consecutive data items as in block data transfers etc The entire memory space including the 1M byte expansion data memory area can be addressed Operand format Register indirect addressing is used when executing instructions with the operand formats shown below Identifier Description mem DE HL DE HL DE HL amp mem amp DE amp HL amp DE amp HL amp DE amp HL DE HL amp mem1 amp DE amp HL Remark after the register name indicates auto increment and indicates auto decrement 77 78K ll SERIES USER S MANUAL Coding example General example 1 MOV A mem When DE HL DE HL DE or HL is specified for mem in register indirect mode Operation code 0 10 1 1 mem Specific example 1 ADD A mem When register indirect mode is specified Operation code 0001 0110 0 1000 General example 2 XOR A amp mem Operation code 0000 0001 0001 0110 0 1101 Specific example 2 MOV A DE When DE is specified for mem Operation code 0101 1100 Specific example 3 ADD amp HL When amp HL is specified for mem O
128. er s Manual IEU 1313 wPD78224 Sub Series User s Manual IEM 1215 uPD78234 Sub Series Use s Manual IEU 1290 e yPD78244 Sub Series User s Manual IEU 1316 To learn about the electrical specifications of the 78K ll series gt Refer to the relevant separate Data Sheet To learn about application examples of the various functions of the 78K ll series products gt Refer to the relevant separate Application Note Weighting in data notation High order digit on the left low order digit on the right Active low notation line over pin signal name Note Explanation of text marked Note Caution Information to be noted carefully Remarks Supplementary information Numeric notations Binary or Decimal Hexadecimal xxxxH Related documentation Documents for entire 78K ll series Document Document number User s Manual Instruction This manual SBI User s Manual EEU 1303 Application Note Basic IEA 1220 Application IEA 1282 Floating Point Arthmetic Operation Program IEA 1273 Selection Guide IF 1160 Instruction Application Table Instruction Set T Development Tools Selection Guide EF 1114 individual documents pPD78214 sub series Brochure Product name PD78212 PD78213 PD78214 Document uPD78P214 Data Sheet 2526 2481 User s Manual Hardware IEM 1236 Mode Register Appl
129. erand src specified by the 2nd operand and stores the result in the destination operand dst If all bits are 0 as a result of obtaining the logical product the Z flag is set 1 otherwise the Z flag is cleared 0 Coding example AND OFEBAH 11011100B Obtains the bit by bit logical product of the contents of OFEBAH and 11011100B and stores the result in OFEBAH 153 78K ll SERIES USER S MANUAL Or OR Byte Data Logical Sum Instruction format OR dst src Operation dst lt dst o src Operands Mnemonic Operands dst src OR A byte saddr byte sfr byte 94 saddr A sfr saddr saddr A mem A amp mem Flags Description Obtains the bit by bit logical sum of the destination operand dst specified by the 1st operand and the source operand src specified by the 2nd operand and stores the result in the destination operand dst Ifall bits are 0 as a result of obtaining the logical sum the Z flag is set 1 otherwise the Z flag is cleared 0 Coding example OR OFE98H Obtains the bit by bit logical sum of the A register and OFE98H and stores the result in the A register 154 CHAPTER 8 INSTRUCTION DESCRIPTIONS Exclusive Or XOR Byte Data Exclusive Logical Sum Instruction format dst src Operation dst lt dst src Operands Mnemonic Operands dst src XOR A byte saddr b
130. ess in external memory expansion mode Common use with data memory is possible 2 Access in 1M byte expansion mode 40 CHAPTER 3 MEMORY SPACE 3 2 INTERNAL PROGRAM MEMORY AREA INTERNAL ROM ROM is incorporated in 78K ll series products in the address spaces shown below and be used to store programs table data etc This area is usually addressed by the program counter PC Remark Product uPD78212 00000H to 01FFFH Address space Internal ROM 8K x 8 bits uPD78214 00000H to O3FFFH uPD78P214 uPD78224 uPD78P224 uPD78234 uPD78244 16K x 8 bits uPD78218A 00000H to 07FFFH uPD78P218A uPD78238 uPD78P238 32K x 8 bits In ROM less products or ROM less operation in a product with on chip ROM this address space functions as external memory 41 78K ll SERIES USER S MANUAL 3 3 VECTOR TABLE AREA The 64 byte area from 00000H to 0003FH is reserved as a vector table area The vector table area holds the program start addresses used when a branch is made due to RESET input or generation of an interrupt request The low order 8 bits of a 16 bit address are stored in an even address and the high order 8 bits in an odd address Any part of the area which is not used as a vector table can be used as program memory or data memory Table 3 1 Vector Table Vector table address 00000H 00002H 00006H 00008H 0000AH 0000CH 0000EH 00010H 00012H 0
131. f the result of the shift operation is 0 the Z flag is set 1 otherwise the Z flag is cleared 0 The AC flag is always 0 regardless of the result of the shift operation The final data shifted out of the MSB bit 7 as a result of the shift operation is set in the CY flag fthe second operand cnt is 0 no processing is performed Z AC and CY flags also do not change To perform a one bit left shift execution time can be reduced by using ADD r r 7 0 C Coding example SHL E 1 Shifts the contents of the E register 1 bit to the left 175 78K ll SERIES USER S MANUAL Shift Right Logical Word SHRW Word Data Logical Right Shift Instruction format SHRW dst cnt Operation CY lt dsto dstis lt 0 dstm 1 dstm x cnt times cnt 0 to 7 Operands Mnemonic Operands dst cnt SHRW rp n Flags Description Shifts to the right the contents of the destination operand dst specified by the 1st operand cnt times as specified by the 2nd operand 0 is shifted into the MSB bit 15 each time 1 bit is shifted f the result of the shift operation is O the Z flag is set 1 otherwise the Z flag is cleared 0 The AC flag is always 0 regardless of the result of the shift operation The final data shifted out of the LSB bit 0 as a result of the shift operation is set in the CY flag fthe second operand cnt is 0 no processing is performed Z AC and CY flags
132. face UART 1 channel incorporating dedicated baud rate generator CSI 3 wire serial SBI 1 channel Continued Note Additional function pins are included in the I O pins 11 78K ll SERIES USER S MANUAL uPD78217A Product name uPD78218A uPD78P218A em A D converter 8 bit resolution x 8 channels Interrupts 19 sources 7 external 12 internal BRK instruction 2 level priority programmable 2 servicing modes vectored interrupts macro service Instruction set 16 bit operation Multiply divide 8 bits x 8 bits 16 bits 8 bits Bit manipulation BCD adjustment etc Package 64 pin plastic shrink DIP 750 mil 64 pin plastic QFP 14 x 14 mm body 64 pin ceramic shrink DIP with window 750 mil uPD78P218A only 12 CHAPTER 1 78K II SERIES FEATURES 1 3 5 Block Diagram JeisiDoJ veLzdgzadr 10 ul pepeus SSA va 48538 ex System control sexa 897 1 WV 72 seq v8LzdgZadr velegz adr pereJ0djooul JON 4128 1 SZd 94 694 ZSd Zvd LEd Zed LOd OSd Otd 00 uod 0 Y Q v G NV 0NV Jeouenbes OJ9IN WOH ODI exsuq r pod euun eed ir snq
133. ffset gt lt jdisp gt sfr bit addr16 0000 100 011011 1 B2 lt Sfr offset gt lt jdisp gt A bit addr16 0000 00111011 1 B2 lt jdisp gt X bit addr16 0000 00111011 0 B2 1 lt jdisp gt PSW bit addr16 0000 00101011 0 B2 1 lt jdisp gt saddr bit 16 0 0 0 100011010 0 B2 1 lt Saddr offset gt jdisp gt sfr bit addr16 0000 100011010 1 B2 1 lt Sfr offset gt lt jdisp gt A bit addr16 0000 001 11010 1 B2 B Bo jdisp gt X bit addr16 0000 001 1101 0 0 B2 1 lt jdisp gt PSW bit addri6 0000 0010 1010 0 B2 1 lt jdisp gt Continued 121 78K ll SERIES USER S MANUAL Operation code Mnemonic Operands B1 B2 B3 B4 B5 BTCLR saddr bit addr16 0 0 0 10 011101 0 B2 1 lt Saddr offset lt jdisp gt sfr bit addr16 0 0 0 10 01101 1 Be Bi lt Sfr offset gt lt jdisp gt A bit addr16 0 0 0 0 0 1 1 101 1 B2 1 lt jdisp gt X bit addr16 0 0 0 0 0 1 1 101 0 B2 1 lt jdisp gt PSW bit addr16 0 0 0 00 011101 0 Bz 1 lt jdisp gt DBNZ r1 addr16 00 1 00 1 lt jdisp gt saddr addr16 00 1 10 1 lt Saddr offset gt lt jdisp gt 14 CPU control instructions SEL El DI Operation code Mnemonic Opera
134. g example ADDW 0AB0DH Adds OABCDH to the AX register and stores the result in the AX register 158 CHAPTER 8 INSTRUCTION DESCRIPTIONS Subtract Word SUBW Word Data Subtraction Instruction format SUBW dst src Operation dst CY lt dst src Operands Mnemonic Operands dst src SUBW AX word AX rp AX saddrp AX sfrp Flags Description Subtracts the source operand src specified by the 2nd operand from the destination operand dst specified by the 1st operand and stores the result in the destination operand dst and the CY flag The destination operand can be cleared to 0 by making the source operand src and the destination operand dst the same If dst is 0 as a result of the subtraction the Z flag is set 1 otherwise the Z flag is cleared 0 If a borrow is generated bit 15 as a result of the subtraction the CY flag is set 1 otherwise the flag is cleared 0 The AC flag is undefined as a result of the subtraction Coding example SUBW 01 Subtracts the contents of the register from the contents of the AX register and stores the result in the AX register 159 78K ll SERIES USER S MANUAL CMPW Compare Word Word Data Comparison Instruction format CMPW dst src Operation dst src Operands Mnemonic Operands dst src CMPW AX word AX rp AX saddrp AX sfrp Flags Descri
135. g example SET1 OFE55H 1 Sets 1 bit 1 of OFE55H 188 CHAPTER 8 INSTRUCTION DESCRIPTIONS Not Single Bit Carry Flag CLR1 1 Bit Data Clear Instruction format dst Operation dst lt 0 Operands Mnemonic Operands dst CLR1 saddr bit sfr bit A bit X bit PSW bit CY Flags dst PSW bit dst CY Other than cases at left Z AC CY Z AC CY Z AC x x x 0 Description Clears 0 the destination operand dst If the destination operand dst is CY or PSW bit only the relevant flag is cleared 0 Coding example CLR1 P3 7 Clears 0 bit 7 of port 3 189 78K ll SERIES USER S MANUAL Clear Single Bit Carry Flag NOT1 1 Bit Data Clear Instruction format NOT1 dst Operation dst lt dst Operands Mnemonic Operands dst NOT1 saddr bit sfr bit A bit X bit PSW bit CY Flags dst PSW bit dst CY Other than cases at left Z AC CY 2 Z AC CY x x x x Description Obtains the logical negation of the bit specified by the destination operand dst and stores the result in the destination operand dst e If the destination operand dst is CY or PSW bit only the relevant flag is changed Coding example NOT1 A 2 Inverts bit 2 of the register 190 CHAPTER 8 INSTRUCTION DESCRIPTIONS 8 10 CALL RETURN INSTRUCTIONS Call return instructions are as follows CALL CALLF CALLT BRK
136. he operation code field determined according to the contents written for mem1 or amp mem1 in the operand field Operand field Operation code field amp 1 Ro or 1 DE 0 HL 1 108 CHAPTER 7 INSTRUCTION SET 7 2 3 List of Operation Codes Mnemonic MOV 1 8 bit data transfer instructions MOV XCH Operation code Operands B1 B2 B3 B4 B5 r byte 1011 1 R2 Ri Ro lt Data gt saddr byte 0011 101 0 lt Saddr offset gt lt Data gt sfr byte 0010 10 1 1 lt Sfr offset gt lt Data gt nr 00 1 0 010 0 0 Re R5 R4 0 R2 Ro A r 11 0 1 0 R2 R1 Ro A saddr 00 10 0000 Saddr offset gt saddr 0010 001 0 Saddr offset gt sfr 00 0 1 00 0 0 Sfr offset gt sfr A 00 0 1 001 0 lt Sfr offset gt saddr saddr 00 1 1 10 0 04 Saddr offset gt lt Saddr offset gt 01 01 1 00 0 mod 0 mem 0 0 0 0 lt Low Offset gt lt High Offset gt Note 00 0001 0101 1 mem A amp mem 00 00 0001000 0 000 0 lt Low Offset gt lt High Offset gt 0 1 0 1 0 mem mem A 00 0 mod 1 mem 0 0 00 lt Low Offset gt lt High Offset gt 0001 0101 0 mem amp mem A 00 00 000 31 0 0 0 mod 1 mem 000 0 lt Low Offset gt lt High Offset gt laddr16 0000 100111111 0000 Low
137. ication Table Brochure uPD78P214 A Data Sheet 2831 3095 User s Manual Hardware IEU 1236 Mode Register Application Table HPD78218A sub series Product name uPD78217A uPD78218A Document Brochure IC 2748 IC 2722 IC 3188 uPD78P218A uPD78P218A A Data Sheet User s Manual Hardware IEU 1313 Special Function Register Application Table e uPD78224 sub series Product name PD78220 Document uPD78224 uPD78P224 Data Sheet 2374 2475 User s Manual Hardware IEU 1215 Special Function Register Application Table e uPD78234A sub series Ai PD78233 uPD78234 PD78237 uPD78238 uPD78P238 wPD78234 A Document n n n u A Brochure uPD78238 A Data Sheet IC 2476 2607 2984 User s Manual Hardware IEU 1290 Special Function Register Application Table HPD78244 sub series Product name Document BPD 78244 uPD78243 Brochure Data Sheet IC 2774 User s Manual Hardware IEU 1316 Special Function Register Application Table 1 2 CONTENTS 78K II SERIES FEATURES uuu uuu asss 1 1 1 78K l SERIES PRODUCT EXPANSION DIAGRAM 2 1 2 OUTLINE OF uPD782
138. ied by the 2nd operand to the destination operand dst specified by the 1st operand No interrupts or macro services are acknowledged between MOV PSW byie instruction PSW A instruction and the next instruction Coding example MOV A 4DH Transfer 4DH to the A register 144 CHAPTER 8 INSTRUCTION DESCRIPTIONS XCH Exchange Byte Data Exchange Instruction format dst src Operation dst lt gt src Operands Mnemonic Operands dst src XCH nr A mem A amp mem A saddr A sfr saddr saddr Flags Description Exchanges the contents of the 1st operand with contents of the 2nd operand Coding example XCH A OFEBCH Exchanges the contents of register A with the contents of address OFEBCH 145 78K ll SERIES USER S MANUAL 8 2 16 BIT DATA TRANSFER INSTRUCTIONS 16 bit data transfer instructions are as follows MOVW 147 146 CHAPTER 8 INSTRUCTION DESCRIPTIONS MOVW Move Word Word Data Transfer Instruction format MOVW dst src Operation dst lt drc Operands Mnemonic Operands dst src MOVW rp word saddrp word sfrp word rp rp AX saddrp saddrp AX AX sfrp sfrp AX mem1 AX amp mem1 mem1 AXNote amp mem1 AXNote Note Cannot be used for the EEPROM area of the uPD78244 sub series Flags Description
139. igh Addr gt 0000 01 0 1 0 1 O 1 1 P2P10 CALLF laddr11 1001 0 fa gt CALLT addr5 11 1 ta gt BRK 01 0 1 1110 RET 01 0 1 01 10 RETI 01 0 1 01 1 1 RETB 01 0 1 1111 11 Stack manipulation instructions POP MOVW INCW DECW Operation code Mnemonic Operands B1 B2 B3 B4 B5 PUSH rp 0011 1 1 P PSW 0100 1001 sfr 0010 100 1 lt Sfr offset gt POP rp 0011 0 1 P Po PSW 0100 1000 sfr 01 00 00 1 1 Sfr offset gt MOVW SP word 0000 101111111 1 1 0 0 lt Low Byte gt lt High Byte gt SP 00 01 00111111 1100 5 00 01 00011111 1100 INCW SP 0000 010111100 1000 DECW SP 0000 010111100 1001 120 CHAPTER 7 INSTRUCTION SET 12 Unconditional branch instructions BR Mnemonic BR 13 Conditional branch instructions Operation code Operands B1 B2 B3 B4 B5 laddr16 0010 110 014 Low gt lt High gt 0000 01010100 1 P2 P10 addr16 00 0 1 0100 jdisp gt BL BNC BNL BZ BNZ BNE BF BTCLR DBNZ Operation code Mnemonic Operands B1 B2 B3 B4 B5 BC addr16 1000 00 1 1 lt jdisp gt addr16 10 00 001 0 lt jdisp gt BNL BZ addr16 10 00 00 0 1 jdisp gt BNZ addr16 1000 00 0 0 jdisp gt BT saddr bit addr16 0 1 1 1 0 B2 B lt Saddr o
140. imer counters 16 bits x 1 8 bits x 3 Serial interface Independent on chip UART and CSI e uPD78234 A 78238 Special quality grade products of 78234 78238 1 5 2 Applications 18 Standard products OA equipment including LBP printers typewriters HDDs FDDs PPCs facsimile etc electronic musical instruments inverters cameras air conditioners etc Special products Automotive electronic equipment combustion control disaster crime preven tion unit CHAPTER 1 78K II SERIES FEATURES 1 5 3 Ordering Information and Quality Grade 1 Ordering information Ordering code uPD78233GC 3B9 uPD78233GJ 5BG uPD78233LQ uPD78234GC xxx 3B9 uPD78234GJ xxx 5BG uPD78234LQ xxx uPD78237GC 3B9 uPD78237GJ 5BG uPD78237LQ uPD78238GC 3B9 uPD78238GJ 5BG uPD78238LQ uPD78P238GC 3B9 uPD78P238GJ 5BG uPD78P238LQ uPD78P238KF uPD78234GC A xxx 3B9 uPD78234GJ A xxx 5BG uPD78238GC A xxx 3B9 uPD78238GJ A xxx 5BG Package 80 pin plastic QFP 14 x 14 mm body 94 pin plastic QFP 20 x 20 mm body 84 pin plastic QFJ 1150 mil 80 pin plastic 14 x 14 mm body 94 pin plastic 20 x 20 mm body 84 pin plastic 71150 mil 80 pin plastic QFP 14 x 14 mm body 94 pin plastic QFP 20 x 20 mm body 84 pin plastic 71150 mil 80 pin plastic QFP 14 x 14 mm body 94 pin plastic QFP 20 x 20 mm body 84 pin plastic 71150 mil 80 pin plastic QFP
141. ion Checks whether a carry has been generated after an addition instruction Determines the result of bit manipulation BNL instruction Checks whether a borrow has been generated after a subtraction instruction After a compare instruction checks whether or not the 1st operand of the compare instruction is smaller Coding examples CMP A B Compares the size of the A register contents and B register contents BNL 1500 Branches to 01500H if the contents of the A register are not smaller than the contents of the B register the start of this instruction is in the address range from 0147FH to 0157EH 209 78K ll SERIES USER S MANUAL BZ Branch if Zero Equal BE Conditional Branch depending on Zero Flag Z 1 Instruction format BZ addr16 BE addr16 Operation PC lt 2 jdisp8 if Z 1 Operands Mnemonic Operands addr16 BZ addr16 BE Flags Description When Z 1 branches to the address specified by the operand When Z 0 no processing is performed and the next instruction is executed The operation of the BZ instruction and the BE instruction is the same Differences in their use are as follows BZ instruction Checks whether the result of an addition subtraction or increment decrement instruc tion or an 8 bit logical operation is O BE instruction Checks for a match after a compare instruction Coding example DEC B BZ 3C5H Branches to 003C5H if the B regi
142. isters Functional name X A C B E D L H Absolute name 7 Register group 1 Register pairs Functional name BC DE HL Absolute name RP0 RP3 Special function registers A special function register name is specified Refer to User s Manual Hardware of relevant product for details Special function register pairs A special function register pair name is specified Refer to User s Manual Hardware of relevant product for details Memory address indicated in indirect addressing mode Register indirect mode DE HL DE HL DE HL Base mode DE byte HL byte SP byte Indexed mode word A word B word DE word HL Memory address indicated in indirect addressing group 1 mode DE HL 87 78K ll SERIES USER S MANUAL saddr saddr saddrp addr16 addr11 addr5 word byte bit RBn Memory address indicated in short direct addressing mode FE20H FF1FH immediate data or label Memory address indicated in short direct addressing pair mode FE20H FF1EH immediate data or label 16 bit address 0000 immediate data or label 11 bit address 800H FFFH immediate data or label 5 bit address 40H 7EH immediate data or label even number only 16 bit data 16 bit immediate data or label 8 bit data 8 bit immediate data or label 3 bit data 3 bit immediate data or label Number
143. it data transfer instructions MOV XCH Mnemonic MOV Notes 1 124 Clock cycles Operands Bytes Internal ROM high speed fetch External ROM fetch Internal Internal ROM IRAM SFR ROM IRAM SFR r byte 2 2 6 sadar byte 3 3 9 5 9 sfr byte 3 5 12 rr 2 6 A r 1 2 3 A saddr 2 4 6 saddr A 2 3 5 8 saddr saddr 3 3Note 1 7 2 QNote1 A sfr 2 4 4 6 9 sfr A 2 5 5 A mem 1 4 A amp mem 2 5 See Table 7 6 1 4 2 4 for details mem A 1 4 amp mem A 2 5 A laddr16 4 7 6 8 8 8 15 14 16 16 A amp laddr16 5 9 8 10 10 10 18 17 19 19 laddr16 A 4 6 8 8 8 14 16 17 amp laddr16 A 5 8 10 10 10 17 19 20 PSW byte 3 5 9 PSW A 2 6 A PSW 2 4 Continued IRAM for both saddr and saddr SFR for both saddr and saddr CHAPTER 7 INSTRUCTION SET Mnemonic XCH Notes 1 Mnemonic MOVW Clock cycles Operands Internal ROM high speed fetch External ROM fetch temal IRAM
144. k DIP 750 mil 64 pin plastic QFP 14 x 14 mm body 64 pin plastic shrink DIP 750 mil 64 pin plastic QUIP 64 pin plastic shrink DIP 750 mil 64 pin plastic QFP 14 x 14 mm body 74 pin plastic QFP 20 x 20 mm body 64 pin plastic QUIP 68 pin plastic QFJ 1950 mil 64 pin plastic shrink DIP 750 mil 64 pin plastic QFP 14 x 14 mm body Remark xxx is the ROM code number Please refer to Quality grade on NEC Semiconductor Devices Document number IEI 1209 published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications Quality grade Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Special Special Special Special Special Special Special Special Special Special Special 78K ll SERIES USER S MANUAL 1 2 4 Function Outline Product name uPD78212 uPD78214 uPD78P214 uPD78213 Number of basic instructions mnemonics 65 Minimum instruction execution time 333 ns 500 ns at 12 MHz operation On chip memory capacity ROM 8K bytes 16K bytes 16K bytes ROM less Mask ROM Mask ROM PROM RAM 384 bytes 512 byte Memory space Program 64K bytes data 1M byte pins Input 14 Output 12 Input output 28 10 Total 54 36 Additional Pins with pull up resistor 34 16
145. l ROM high speed fetch External ROM fetch Internal ROM IRAM PRAM SFR EMEM Internal ROM IRAM PRAM SFR EMEM amp DE A amp HL A 11 DE A HL A DE A HL 8 9 9 10 11 amp DE4 amp HL amp DE amp HL A 10 11 12 13 14 DE byte A HL byte A 7 8 11 12 13 amp DE byte A amp HL byte A 9 10 14 15 16 SP byte A 8 9 10 10 10 12 13 14 amp SP byte A 10 11 12 12 12 15 16 17 word A A word B A word DE A word HL A 7 8 16 amp word A A amp word B A amp word DE A word HL A 9 10 17 Note The above figures apply when instructions with a short word length are used When one byte word length is long Internal ROM fetch 1 cycle External ROM fetch 3 cycles 19 137 78K ll SERIES USER S MANUAL Instruction group 8 bit data transfer instruc tions 138 Mnemonic Table 7 6 Table of Instruction Execution Cycles 3 4 Operands A DE A HL Bytes Internal ROM high speed fetch External ROM fetch Internal ROM IRAM PRAM 13 SFR 13 EMEM 13 Internal ROM IRAM 12 PRAM 16 SFR 16 EMEM A amp DE A amp HL 15 15 15 19 A DE HL A DE A HL
146. ll sub series The only difference between products within the same sub series moreover is the size of memory Figure 1 1 78K Series and 78K ll Series Composition 78 Series 78K 0 Series 78 Series 8 bit single chip microcomputers uPD78214 Sub Series uPD78218A Sub Series 78 Series uPD78224 Sub Series uPD78234 Sub Series 78244 Sub Series 7 Series 16 bit single chip microcomputers 78K IV Series 78K ll SERIES USER S MANUAL 78 SERIES PRODUCT EXPANSION DIAGRAM 1 1 seues qns 8128 0 1 5 oew U L p puedx s 941 peoueuue sas 991 seues qns ryeg poppe I NOud33 seues qns rL2g Qd peoueuue Jejunoo 1euJn pue 99 4 941 peppe si yndyno 1 peurejuoo 1 JeueAuoo 941 seues qns s eu peoueuue uonouni Joje1eueb pneq pue 941 peurejuoo s q V eur s u s qns pzzg adn D 1 p s eu Jejunoo pue eu 1 pappe si 3nd3no WMd 941 y q q V
147. lt Data gt sfr byte 0000 0001 0110 101 11 lt Sfr offset gt lt Data gt nr 1000 10 1 1 0 Re Rs R4 0 R2 R1Ro A saddr 10 0 1 10 1 Tss Saddr offset gt sfr 0000 000 1 100 1 101 1 lt Sfr offset gt saddr saddr 0111 101 1 lt Saddr offset gt lt Saddr offset gt 000 0 10 11 Low Offset gt lt High Offset gt amp mem 0000 00 0 1 00 0 mod 0 mem 101 1 lt Low Offset lt High Offset gt Continued 113 78K ll SERIES USER S MANUAL Operation code Mnemonic Operands B1 B2 B3 B4 B5 AND A byte 1010 11 0 0 lt Data gt saddr byte 0110 11 0 01 Saddr offset gt lt Data gt sfr byte 0000 0001 0110 1100 lt Sfr offset gt lt Data gt nr 1000 11 0 010 Rs 0 R2 A saddr 10 0 1 110 0 Saddr offset gt sfr 0000 0001 1001 1 1 0 O lt Sfr offset gt saddr saddr 0111 110 Saddr offset gt lt Saddr offset gt 00 0 0 mem 1 1 0 O lt Low Offset gt lt High Offset gt amp 0000 0001000 0 1100 lt Low Offset lt High Offset gt OR A byte 10 10 11 1 Data gt saddr byte 0110 111 0 lt Saddr offset gt lt Data gt sfr byte 0000 0001 0110 1110 lt Sfr offset gt lt Data gt nr 1000 11 1 0 0 Res Rs 0 R2
148. lt SP 1 Operands None Flags Description Increments the contents of the SP stack pointer by 1 203 78K ll SERIES USER S MANUAL DECW SP Decrement Word Stack Pointer Decrement Instruction format DECW SP Operation SP lt SP 1 Operands None Flags Description Decrements the contents of the SP stack pointer by 1 204 CHAPTER 8 INSTRUCTION DESCRIPTIONS 8 12 UNCONDITIONAL BRANCH INSTRUCTIONS The unconditional branch instruction is as follows 206 205 78K ll SERIES USER S MANUAL BR Branch Unconditional Branch Instruction format BR target Operation PC lt target Operands Mnemonic Operands target BR laddr16 rp addr16 Flags Description Performs an unconditional branch Transfers the target address operand target word data to the PC then branches Coding example BR AX Branches using the contents of the AX register as the branch address 206 CHAPTER 8 INSTRUCTION DESCRIPTIONS 8 13 CONDITIONAL BRANCH INSTRUCTIONS Conditional branch instructions are as follows BC BL BNC BNL BZ BE BNZ BNE BT BF BTCLR DBNZ 208 208 209 209 210 210 211 211 212 213 214 215 207 78K ll SERIES USER S MANUAL BC Branch if Carry Less than BL Conditional Branch depending on Carry Flag CY 1 Instruction format BC addr16 BL addr16 Ope
149. monic Operands Bytes Internal ROM high speed fetch External ROM fetch Internal Internal Rom IRAM PRAM SFR IRAM SFR EMEM ADD A byte 2 2 6 saddr byte 3 4 8 9 11 sfr byte 4 10 10 14 18 nr 2 7 3 2 5 6 7 3 7 7 10 11 saddr saddr 3 4Note 1 QNote 2 QNote 1 11 1 2 2 4 Table 7 6 4 4 for details amp 3 5 ADDC A byte 2 2 6 saddr byte 3 4 8 9 11 sfr byte 4 10 10 14 18 Eb 2 7 3 A saddr 2 5 6 7 A sfr 3 7 7 10 11 saddr saddr 3 4Note 1 QNote 2 QNote 1 1iNote2 A mem 2 4 See Table 7 6 4 4 for details A amp mem 3 5 SUB A byte 2 2 6 sadar byte 3 4 8 9 11 sfr byte 4 10 10 14 18 rar 2 7 3 Z A saddr 2 5 6 7 A sfr 3 7 7 10 11 saddr saddr 3 4Note 1 QNote 2 QNote 1 11 1 2 A mem 2 4 See Table 7 6 4 4 for details A amp mem 3 5 Continued Notes 1 IRAM for both saddr and saddr 2 SFR for both saddr and saddr 126 CHAPTER 7 INSTRUCTION SET Clock cycles
150. n data memory area Direct addressing Register indirect addressing Based addressing Indexed addressing Data manipulation on the 1M byte expansion data memory area is executed after first loading the bank register PM6 or P6 with 4 bit bank data which specifies the memory bank on which the operation is to be performed Bank data set in bank register PM6 is output as the extension address A16 to A19 only during execution of a memory manipulation instruction using one of the four addressing modes above Bank data set in bank register P6 is output as the extension address A16 to A19 only during execution of a memory manipulation instruction with the symbol amp affixed Once bank data is set it is retained until next overwritten by the program Cautions 1 Whenthe 1M byte expansion space is not used the low order 4 bits ofthe PM6 register must be set to 0 2 Inthe uPD78224 sub series the low order 4 bits of the PM6 register must be set to 0 6 3 1 Direct Addressing Function This addressing method addresses memory directly by means of the 16 bit address data in the instruction word This addressing method can be used on the entire memory space including the 1M byte expansion data memory area Operand format Direct addressing is used when executing instructions with the operand formats shown below Identifier Description laddr16 Label or 16 bit immediate data amp laddr16 Label or 16 bit immediate dat
151. nds B1 B2 B3 B4 B5 MOV STBC byte 00 0 10 11100 0000 lt Data gt lt Data gt SEL RBn 0 0 0 0 1 111010 1 0 NiNo NOP 00 0 00 0 El 01 0 10 1 DI 01 0 10 0 122 CHAPTER 7 INSTRUCTION SET 7 3 INSTRUCTION CLOCK CYCLES 7 3 4 Clock Cycles Column This column outlines the number of clock cycles in instruction execution One clock cycle is 1 fcLk 167 ns when 6 MHz 1 Clock field classification The number of instruction clock cycles varies according to the instruction fetch method and the memory accessed or branched to by the instruction 1 Instruction fetch method For internal ROM high speed fetch Shows the number of clock cycles when an internal ROM program is executed with MM register IFCH 1 When IFCH 0 same as for external ROM fetch For external ROM fetch Shows the number of clock cycles in execution using exter nal programmable memory 2 Memory area accessed or branched to by instruction nternal ROM Internal ROM fetch IRAM Access to internal dual port RAM 0FE00H to OFEFFH SFR Special function register access PRAM Access to non IRAM area of internal RAM EMEM External memory access 2 Use of n in clock cycles column n in the clock cycles column of a shift rotate instruction indicates the number of bits shifted 3 Use of in clock cycles column alb aorb 123 78K ll SERIES USER S MANUAL 7 3 2 List of Clock Cycles 1 8 b
152. ne call instruction CALL 3 bytes Speed is also increased when operating with external ROM When high speed is required writing direct subroutines in this area is an effective solution When it is wished to reduce the object size this can be achieved by writing an unconditional branch BR instruction in this area and locating the subroutine itself outside this area for subroutines which are called from 4 or more places In this case only the 3 bytes of the BR instruction take up space in the CALLF entry area and thus the object size can be reduced with many subroutines 43 SERIES USER S MANUAL 3 6 INTERNAL RAM AREA 78K ll series products incorporate general purpose static RAM This area is configured as follows Internal RAM area Internal RAM Product name Peripheral RAM PRAM Internal dual port RAM IRAM Table 3 2 Internal RAM Area in 78K ll Series Products Internal RAM area Peripheral RAM PRAM uPD78212 384 bytes 128 bytes OFD80H to OFEFFH OFD80H to OFDFFH uPD78213 512 bytes 256 bytes uPD78214 OFDOOH to OFEFFH OFDOOH to OFDFFH uPD78P214 uPD78217A 1024 bytes 768 bytes uPD78218A OFBOOH to OFEFFH OFBOOH to OFDFFH uPD78P218A uPD78220 640 bytes 384 bytes uPD78224 OFC80H to OFEFFH OFC80H to OFDFFH uPD78P224 uPD78233 uPD78234 uPD78237 1024 bytes 768 bytes uPD78238 OFBOOH to OFEFFH OFBOOH to OFDFFH uPD78P238 uPD78243 512 bytes 256 by
153. ng on the result of executing an instruction see Figure 4 2 In addition to being written to or read as an 8 bit unit flags can be manipulated individually by means of bit manipulation instructions The PSW is saved to the stack when a vectored interrupt request is acknowledged or when a BRK or PUSH PSW instruction is executed and restored when a RETI RETB or POP PSW instruction is executed The PSW is set to 02H by RESET input interrupt acknowledgment disabled state PC Figure 4 2 Program Status Word Configuration 7 6 5 4 3 2 1 0 e Tz esi ac Fes o ee sv PSW 51 78K ll SERIES USER S MANUAL 1 Carry flag CY 2 3 4 5 6 52 The stores overflow underflow during execution of addition subtraction instruction This flag also stores the shifted out value when a shift rotate instruction is executed and functions as a one bit accumulator when a bit manipulation instruction is executed Interrupt priority status flag ISP This flag controls the priority of currently acknowledgeable maskable vectored interrupts When this flag is 0 low order vectored interrupts specified by the priority specification flag register PR0 are acknowl edgment disabled and when 1 acknowledgment is enabled regardless of priority Actual acknowledg ment is controlled by the status of the IE flag ISP contents are updated each time a maskable vectored in
154. not amp is affixed to the instruction operand The P6 register is selected as the bank register when amp is used and the PM6 register is selected when amp is not used This function facilitates processing in which for example data read from data ROM e g kanji data for printing is expanded or compressed and stored in RAM if a RAM area is specified with one of the two banks used as the main data bank while a data ROM area is specified with the other bank used as the subsidiary bank Remark Theoperation code and execution time of instructions which use PM6 register as the bank register are shorter than those of instructions which use the P6 register Also instructions which manipulate the P6 register are shorter and have a shorter execution time than instructions which manipulate the PM6 register Itis therefore efficient to use the PM6 register as the main bank register which specifies frequently accessed banks and to use the P6 register as the subsidiary bank register for which the specified bank frequently changes Cautions 1 In the uPD78224 sub series the low order 4 bits PM60 to PM63 of the PM6 register should always be set to 0 before use Since the low order 4 bits of the PM6 register are used as 0 bank 0 is always accessed in an addressing mode without amp 2 When the external expansion data memory space is not used ensure to set 0 to the low order 4 bits of the PM6 register PM60 to PM63 A normal emulation
155. o be manipulated as 16 bit units by pairing two 8 bit registers AX BC DE HL These registers can be used for general purposes such as temporary storage of operation results or as operands in inter register operation instructions The area from OFEEOH to OFEFFH can be addressed and accessed as ordinary data memory regardless of whether or not it is used as a general register area As 78K ll series is provided with 4 register banks efficient programs can be written by using different register banks for normal processing and interrupt servicing The individual registers have the specific functions described below 1 Mainly used for 8 bit data transfers and operation processing Can also be used for bit data storage In addition this register can also be used to hold the offset value when indexed addressing is used AX RPO Mainly used for 16 bit data transfers and operation processing X RO Can store bit data Has a loop counter function and can be used by the DBNZ instruction In addition this register can also be used to hold the offset value when indexed addressing is used C R2 Has a loop counter function and can be used by the DBNZ instruction DE RP2 HL RP3 These register pairs have a pointer function and operate as the register which specifies the base address when register indirect addressing or based addressing is used In addition these register pairs also operate as the register which h
156. olds the offset value in indexed addressing The registers can be described by their absolute names R0 to R7 RP0 to RP3 as well as by their functional names X A C B E D L H AX BC DE HL which indicate their specified functions The correspondence between these names is shown in Table 4 2 56 CHAPTER 4 REGISTERS Table 4 2 Correspondence Between Function Names and Absolute Names 1 8 bit operations Functional name Absolute name r O gt gt lt 2 16 bit opeations Functional name Absolute name AX RPO BC RP1 DE RP2 HL RP3 4 33 SPECIAL FUNCTION REGISTERS SFR These are registers to which special functions are allocated such as on chip peripheral hardware mode registers control registers etc and are mapped onto the 256 byte space from OFFOOH to OFFFFH Please refer to individual product documentation for details of the special function registers Caution Addresses in this area which are not allocated to SFRs should not be accessed An illegal access may result in CPU deadlock A deadlock state can be released by reset input only 57 78K ll SERIES USER S MANUAL MEMO 58 CHAPTER 5 INTERRUPT FUNCTIONS The 78K ll series is provided with two modes for servicing interrupt requests These two servicing modes can be set as required by the program In addition multiprocessing control using two priority levels can easily be performed for maskable vectored interrupts Table
157. om 00800H to OOFFFH and using this instruction enables the program size to be reduced The execution time is also reduced when there is a program in external memory Coding example 0C2AH 00C2AH subroutine call 193 78K ll SERIES USER S MANUAL Call Table Subroutine Call Call Table Reference CALLT Instruction format CALLT addr5 Operation SP 1 lt 1 SP 2 lt PC 1 L SP lt SP 2 PCH lt 00000000001 addr5 1 PCL lt 00000000001 addr5 Operands Mnemonic Operands addr5 CALLT addr5 Flags Description This is a call table reference subroutine call The start address of the next instruction PC 1 saved to the stack and a branch is made to the address indicated by the word data in the call table the high order 10 bits of the address are fixed at 0000000001B the next 5 bits are specified by addr5 and the LSB is fixed at 0 Coding example CALLT 60H Subroutine call to the address indicated by the word data in addresses 00060 and 00061H 194 CHAPTER 8 INSTRUCTION DESCRIPTIONS Break Software Vectored Interrupt BRK Instruction format BRK Operation SP 1 lt PSW SP 2 lt PC 1 SP 3 lt PC 1 L IE lt 0 SP lt SP 4 PCH lt 3FH PCL lt Operands None Flags Description The software interrupt instruction The PSW an
158. on code Rn Pn in the instruction word in the register bank specified by the register bank selection flag RBS1 50 Register addressing is performed when an instruction with the operand format shown below is executed when an 8 bit register is specified one of eight registers is specified by 3 bits in the operation code or one of two registers by 1 bit When a 16 bit register pair is specified one of four register pairs is specified by 2 bits in the operation code Operand format Identifier Description r X A C B E D L H rl C rp AX BC DE HL In addition to the functional names X A C B E D L H AX BC DE HL absolute names to R7 RP0 to RP3 can be specified for r r1 and rp Coding example 1 General example MOV Operation code 1101 Ro Specific example MOV A When C register is selected as Operation code 1101 0010 67 78K ll SERIES USER S MANUAL Coding example 2 68 General example INCW rp Operation code 0100 01 Pi Po Specific example INCW DE When DE register pair is selected as rp Operation code 0100 0110 CHAPTER 6 ADDRESSING 6 2 3 Immediate Addressing Function Inthis addressing method 8 bit data and 16 bit data to be manipulated are included in the operation code Operand format Immediate addressing is used when executing instructions with the operands shown below Identifier Description byte Label or 8 bi
159. on Lists for Each Addressing Type 102 7 2 OPERATION CODES ection edades 106 7 2 1 Operation Code Symbols u UU 106 7 2 2 Operation Code When mem amp mem amp mem1 15 5 5 ux tpe reet i 108 7 2 3 List of Operation nennen 109 7 3 INSTRUCTION CLOCK CYCLES lu 123 73 1 Clock Cycles Columns tote e eret und eei eiie 123 7922 Listo Clock Gycles soi ettet nete e x Foe EN 124 INSTRUCTION DESCRIPTIONS i UU IILI ansia nn 141 8 1 8 BIT DATA TRANSFER 143 8 2 16 DATA TRANSFER 146 8 3 8 BIT OPERATION INSTRUCTIONS 148 8 4 16 OPERATION INSTRUCTIONS sees 157 8 5 MULTIPLICATION DIVISION INSTRUCTIONS 161 8 6 INCREMENT DECREMENT INSTRUCTIONS 164 8 7 SHIFT ROTATE INSTRUCTIONS 169 8 8 BCD ADJUSTMENT INSTRUCTIONS sss nennen nnne 180 8 9 BIT MANIPULATION INSTRUCTIONS esses 183 CHAPTER 9 CHAPTER 10 APPENDIX A APPENDIX B APPENDIX C 8 10 CALL
160. onics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics lt 1 USER S MANUAL 78K ll SERIES 8 BIT SINGLE CHIP MICROCOMPUTER INSTRUCTIONS uPD78214 SUB SERIES uPD78218A SUB SERIES uPD78224 SUB SERIES uPD78234 SUB SERIES uPD78244 SUB SERIES Document 010228 6 00 00 edition Previous No IEU 1311 Date Published December 1995 P NEC Corporation 1990 Printed in Japan 78K ll SERIES FEATURES 78 SERIES PRODUCTS MEMORY SPACE REGISTERS INTERRUPT FUNCTIONS ADDRESSING INSTRUCTION SET INSTRUCTION DESCRIPTIONS DEVELOPMENT TOOLS BUILT IN SOFTWARE INDEX OF INSTRUCTIONS MNEMONICS CLASSIFIED BY FUNCTION INDEX OF INSTRUCTIONS MNEMONICS IN ALPHABETICAL ORDER REVISION HISTORY Cautions on CMOS Devices D Countermeasures against static electricity for all MOSs Caution When handling MOS devices take care so that they are not electrostatically charged Strong static electricity may cause dielectric breakdown in gates When transporting or storing MOS devices use conductive trays magazine cases shock absorbers or metal cases that NEC uses for packaging and shipping Be sure to ground MOS devices during assem
161. ormat Operation Operands Mnemonic SUB Flags Z AC x x Description SUB dst src dst CY lt dst src Operands dst src A byte saddr byte sfr byte nr A saddr A sfr saddr saddr A mem A amp mem CY Subtracts the source operand src specified by the 2nd operand from the destination operand dst specified by the 1st operand and stores the result in the destination operand dst and the CY flag The destination operand can be cleared to 0 by making the source operand src and the destination operand dst the same If dst is 0 as a result of the subtraction the Z flag is set 1 otherwise the Z flag is cleared 0 If a borrow is generated in bit 7 as a result of the subtraction the CY flag is set 1 otherwise the flag is cleared 0 If aborrow is generated out of bit 4 into bit 3 as a result of the subtraction the AC flag is set 1 otherwise the AC flag is cleared 0 Coding example SUB D L Subtracts the L register from the D register and stores the result in the D register 151 78K ll SERIES USER S MANUAL SUBC Subtract with Carry Byte Data Subtraction including Carry Instruction format SUBC dst src Operation dst CY lt dst src CY Operands Mnemonic Operands dst src SUBC A byte saddr byte sfr byte rr A saddr A sfr saddr saddr
162. ote 64640 bytes 00000H to 0FC7FH uPD78234 48256 bytes 04000H to OFC7FH uPD78237Note 64256 bytes 00000 to OFAFFH uPD78238 uPD78P238 31488 bytes 08000H to OFAFFH uPD78243Note 64256 bytes 00000H to OFAFFH uPD78244 Note ROM less product 47872 bytes 04000H to OFAFFH 47 78K ll SERIES USER S MANUAL 311 EXTERNAL EXPANSION DATA MEMORY SPACE The area from 10000H to FFFFFH is space which can be accessed when the 1M byte expansion mode has been specified by means of the memory expansion mode register MM In this case pins P60 to P63 of port 6 function as the 4 bit expansion address bus A16 to A19 The data memory space is handled as sixteen 64K byte banks with the P6 register and the low order 4 bits of the PM6 register functioning as the bank registers used to select the bank This space is useful when handling large amounts of data as in the case of a kanji character generator for example This space can only be accessed when the bank to be used 4 bit address information on pins A16 to A19 has been set beforehand in the bank register P60 to P63 of the P6 register or PM60 to PM63 of the PM6 register and during execution of an instruction which has extended addressing capability Asthere are two bank registers P6 and PM6 two banks can normally be used as banks on which operations are to be performed One or other of the bank registers is selected according to whether or
163. p 16 bit manipulable special function register name Coding example General example MOV sfr A Operation code 0001 0010 Sfr offset Specific example MOV A When is specified as sfr Operation code 0001 0010 0010 0000 72 CHAPTER 6 ADDRESSING Illustration Op code Sfr offset 15 87 0 SFR Effective address 1 1 1 1 1 1 1 FL 6 2 0 Stack Addressing Function In this addressing method the 64K byte stack area is indirectly addressed by the contents of the stack pointer SP This type of addressing is used automatically when a PUSH or POP instruction is executed when registers are saved restored due to generation of an interrupt request and when a subroutine call or return instruction is executed Coding example PUSH DE Executing this instruction when the contents of the DE register are saved to the stack area using a PUSH instruction automatically decrements 2 the SP before storing the DE register contents in the stack area Illustration Stack area sp 2 register contents T 1 D register contents SP Caution Stack addressing can be used for the entire 64K byte space but the SFR area and internal ROM area cannot be reserved as a stack area 73 78K ll SERIES USER S MANUAL 6 3 1M BYTE EXPANSION SPACE ADDRESSING In 78K ll series products the following addressing modes can be used to access the 1M byte expansio
164. peration code 0000 0001 0001 0110 0001 1000 78 CHAPTER 6 ADDRESSING Illustrations 1 1M byte addressing without amp symbol Register pair n x Bank n Register pair contents as Remark n the uPD78224 sub series the low order 4 bits of the PM6 register are fixed at 0 Therefore only bank 0 can be accessed when the amp symbol is not used 2 1M byte addressing with amp symbol Register pair n lt 79 78K ll SERIES USER S MANUAL 6 3 3 Based Addressing Function This addressing method addresses memory by using as the base register the register pair specified by the register pair specification code in the instruction word in the register bank specified by the register bank selection flag RBS1 RBS0 and adding 8 bit immediate data to these contents as offset data The addition is performed with the offset data extended to 16 bits as a positive number A carry out of the 16 the bit is ignored The entire memory space including the 1M byte expansion data memory area can be addressed This kind of addressing is used for specifying data in an array of records which are composed of multiple bytes of data MOV A HL 2H Record start address HL is specified as the start address and HL 2 is manipulated HL 2 HL 1 record in array Record start address Data specified in individual records Operand format
165. pin plastic 20 x 20mm body None uPD78220L 84 pin plastic QFJ 1150 mil None uPD78224GJ xxx 5BG 94 pin plastic QFJ 20 x 20 mm body Mask ROM uPD78224L xxx 84 pin plastic QFJ 1150 mil Mask ROM uPD78P224GJ 5BG 94 pin plastic QFP 20 x 20 mm body One time PROM uPD78P224L 84 pin plastic QFJ 1150 mil One time PROM Remark xxx is the ROM code number 2 Quality grade Ordering code Package Quality grade uPD78220GJ 5BG 94 pin plastic 20 x 20 mm body Standard uPD78220L 84 pin plastic QFJ 1150 mil Standard uPD78224GJ xxx 5BG 94 pin plastic 20 x 20 mm body Standard uPD78224L xxx 84 pin plastic QFJ 1150 mil Standard uPD78P224GJ 5BG 94 pin plastic 20 x 20 mm body Standard uPD78P224L 84 pin plastic QFJ 0 1150 mil Standard Remark xxx is the ROM code number Please refer to Quality grade on NEC Semiconductor Devices Document number IEI 1209 published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications 15 78K ll SERIES USER S MANUAL 1 4 4 Function Outline Product name I uPD78224 uPD78P224 uPD78220 em Number of basic instructions mnemonics 65 Minimum instruction execution time 333 ns 500 ns at 12 MHz operation On chip memory capacity ROM 16K bytes 16K bytes PROM ROM less Mask ROM RAM 640 bytes Memory space Program 64K bytes data 1M byte I
166. pter 7 Table 9 1 has been divided into a table for the screen debugger and Chapter 9 table for the in circuit emulator control program Descriptions related to the EV 9900 HP9000 series 300 SPARCstation and EWS 4800 series have been added Description related to IBM PC AT has been added to the screen debugger and device file Chapter 10 has been added Chapter 10 Sixth A disaster crime prevention unit has been added as a special product in Chapter 1 applications of the LPD78214 sub series uPD782184A sub series and uPD78234 sub series Z AC and CY flags also do not change has been added to the sentence Chapter 8 If the second operand cnt is 0 no processing is performed in Description of ROR ROL RORC ROLC SHR SHL SHRW and SHLW Description related to the 3 5 inch 2HC has been added to the Chapter 9 IBM PC AT The HP9000 series 300 has been changed to the HP9000 series 700 The screen debugger of IBM PC AT and the 5 25 inch 2HC of the device file have been already developed 4 OS for the IBM PC has been added The Fuzzy inference debugger FD78K II has been already developed Appendix C has been added Appendix G 253 78K ll SERIES USER S MANUAL MEMO 254
167. ption Subtracts the source operand src specified by the 2nd operand from the destination operand dst specified by the 1st operand The result of the subtraction is not stored anywhere only the Z AC and CY flags are changed f a result of the subtraction is 0 the Z flag is set 1 otherwise the Z flag is cleared 0 If a borrow is generated bit 15 as a result of the subtraction the CY flag is set 1 otherwise the flag is cleared 0 The AC flag is undefined as a result of the subtraction Coding example CMPW OFE43H Subtracts the word data in address OFE43H from the AX register and performs flag modification only comparison of the AX register and address OFE43H word data 160 CHAPTER 8 INSTRUCTION DESCRIPTIONS 8 5 MULTIPLICATION DIVISION INSTRUCTIONS Multiplication division instructions are as follows MULU 162 DIVUW 163 161 78K ll SERIES USER S MANUAL Multiply Unsigned MULU Unsigned Data Multiplication Instruction format MULU src Operation AX lt AX x src Operands Mnemonic Operands src MULU r Flags Description Multipliesthe A register contents by the source operand src data as unsigned data and stores the result in the AX register Coding example MULU H Multiplies the A register contents by the H register contents and stores the result in the AX register 162 CHAPTER 8 INSTRUCTION DESCRIPTIONS
168. r adapter PA 78P214CW PA 78P214GQ EV 9200GC 64 PA 78P214GC PA 78P214L EV 9200G 74 PA 78P214GJ PA 78P214CW EV 9200GC 64 PA 78P214GC PA 78P224L EV 9200G 94 PA 78P224GJ EV 9200GC 80 PA 78P238GC PA78P238LQ EV 9200G 94 PA 78P238GJ PA 78P238KF EV 9200GC 64 Assembler RA78K II C compiler CC78K II C compiler library source file CC78K II L Note Socket for connecting emulation probe to the user system Mounted on the user system board for use 229 78K ll SERIES USER S MANUAL 9 2 OUTLINE OF TOOLS 9 2 1 Hardware 1 Relevant to in circuit emulator 1 3 IE 78240 R A IE 78230 R A used in 78200 R Bk These are function enhanced versions of the previous 78K II series in circuit emulator The target device of each emulator is shown below When PC 9800 series or IBM PC AT is used as a host machine these can be used These require the screen debugger and device file separately sold and allow debugging in the level of source program such as C language or structured assembly language by use in combination with them Simultaneous trace of data access and program fetch and CO coverage function enables efficient debugging and program test IE 78210 R or IE 78240 R can be used the same way as IE 78240 R A by purchasing the board separately sold IE 78200 R BK and IE 78220 R or IE 78230 R can be the same w
169. ration PC lt 2 jdisp8 if CY 1 Operands Mnemonic Operands addr16 BC addr16 BL Flags Description When CY 1 branches to the address specified by the operand When CY 0 no processing is performed and the next instruction is executed The operation of the BC instruction and the BL instruction is the same Differences in their use are as follows BC instruction Checks whether a carry has been generated after an addition instruction Determines the result of bit manipulation BL instruction Checks whether a borrow has been generated after a subtraction instruction After a compare instruction checks whether or not the 1st operand of the compare instruction is smaller Coding example BC 300H Branches to 00300H if CY 1 the start of this instruction is in the address range from 0027FH to 0037EH 208 CHAPTER 8 INSTRUCTION DESCRIPTIONS BNC Branch if Not Carry Less than BNL Conditional Branch depending on Carry Flag CY 0 Instruction format BNC addr16 BNL addr16 Operation PC lt PC 2 jdisp8 if CY 0 Operands Mnemonic Operands addr16 BNC addr16 BNL Flags Description When CY 0 branches to the address specified by the operand When CY 1 no processing is performed and the next instruction is executed The operation of the BNC instruction and the BNL instruction is the same Differences in their use are as follows BNC instruct
170. reg Pi rp Re Rs r 0 C rp 0 0 0 RO X 1 B Pe Ps rp 0 0 1 1 A 0 0 IPR0 0 1 0 2 0 1 PR1 BC 0 1 1 B 1 0 IPR2 DE 1 0 1 1 PR3 HL 1 0 1 5 1 1 0 R6 L 1 1 1 R7 H Bn Immediate data corresponding to bit Nn Immediate data corresponding to n Data 8 bit immediate data corresponding to byte Low High Byte Saddr offset Saddr offset Sfr offset Low High Offset Low High Addr jdisp8 fa ta 16 bit immediate data corresponding to word Low order 8 bit offset data of 16 bit address corresponding to saddr or saddrp Low order 8 bit offset data of 16 bit address corresponding to saddr Special function register sfr sfrp 16 bit address low order 8 bit offset data 16 bit offset data corresponding to word in indexed addressing 16 bit immediate data corresponding to addr16 Signed two s complement data 8 bit for relative address distance between start address of next instruction and branch address Low order 11 bits of immediate data corresponding to addr11 Low order 5 bits of immediate data corresponding to addr5 x dis Caution The code when the 1st and 2nd operands in the operand field are both registers a register pair is as described below The high order 4 bits of the register specification byte comprise the 1st operand specification code and the low order 4 bits comprise the 2nd operand specification code 106 CHAPTER 7 INSTRUCT
171. robe EP 78240CW R EP 78240GQ R EP 78240GC R EP 78240LP R EP 78240GJ R DF78210 EP 78240CW R EP 78240GC R DF78220 EP 78230LQ R EP 78230GJ R DF78230 EP 78230GC R EP 78230LQ R EP 78230GJ R DF78240 EP 78240CW R EP 78240GC R Notes 1 The 078212 package range comprises 64 SDIP 64 pin QFP 74 pin only 2 uPD78P238 only 226 CHAPTER 9 DEVELOPMENT TOOLS Conversion socketNote PROM programmer adapter PA 78P214CW PA 78P214GQ EV 9200GC 64 PA 78P214GC PA 78P214L EV 9200G 74 PA 78P214GJ PA 78P214CW EV 9200GC 64 PA 78P214GC PA 78P224L EV 9200G 94 PA 78P224GJ EV 9200GC 80 PA 78P238GC PA 78P238LQ EV 9200G 94 PA 78P238GJ PA 78P238KF EV 9200GC 64 Assembler RA78K II C compiler CC78K II C compiler library source file CC78K II L Note Socket for connecting emulation probe to the user system Mounted on the user system board for use 227 78K ll SERIES USER S MANUAL Table 9 2 Development Tools for In Circuit Emulator Control ProgramNote 1 In circuit emulator i circui Note 1 i Target device Package In circuit emulatorNote control programNote 1 Emulation probe uPD78214 sub 64SDIP IE 78210 R IE 78210Note 4 EP 78
172. ry is possible 2 Access in 1M byte expansion mode 3 1 4 nPD78234 Sub Series Memory Space Program memory Data memory Product name Internal ROM External memoryNote 1 Internal RAM External memoryNote 2 uPD78233 64640 bytes 640 bytes 960K bytes MODE H 00000H to OFC7FH OFC80H to OFEFFH 10000H to FFFFFH uPD78234 MODE H uPD78234 16K bytes 48256 bytes MODE L 00000 to 04000 to 0FC7FH uPD78237 64256 bytes 1024 bytes MODE H 00000H to OFAFFH OFBOOH to OFEFFH uPD78238 MODE H uPD78238 32K bytes 31488 bytes MODE L 00000H to 07FFFH 08000H to OFAFFH uPD78P238 uPD78234 78238 memory mapping can be selected by the memory MODE L Note 3 size switchover register IMS Notes 1 Access in external memory expansion mode Common use with data memory is possible 2 Access in 1M byte expansion mode 3 Cannot be used as MODE H ROM less operation specification in the uPD78P238 39 78K ll SERIES USER S MANUAL 3 1 5 HuPD78244 Sub Series Memory Space Product name Program memory Data memory Internal ROM External memoryNote 1 uPD78243 64256 bytes EA L 00000H to OFAFFH 078244 L 78244 16 bytes 47872 bytes 00000 to 04000 to 03FFFH OFAFFH EEPROM 512 bytes OFBOOH to OFCFFH Internal RAM 512 bytes OFDOOH to OFEFFH External memoryNote 2 960K bytes 10000H to FFFFFH Notes 1 Acc
173. s Description Rotates to the right the contents of the destination operand dst specified by the 1st operand cnt times as specified by the 2nd operand The contents of the LSB bit 0 are rotated into the MSB bit 7 and at the same time transferred to the CY flag f the 2nd operand cnt is 0 no processing is performed Z AC and CY flags also do not change 7 0 Es Coding example 4 Rotates the contents of the C register 4 bits to the right 170 CHAPTER 8 INSTRUCTION DESCRIPTIONS Rotate Left ROL Byte Data Left Rotation Instruction format ROL dst cnt Operation CY dsto lt dst7 dstm 1 lt x cnt times cnt 0 to 7 Operands Mnemonic Operands dst cnt ROL rn Flags Description Rotates to the left the contents of the destination operand dst specified by the 1st operand cnt times as specified by the 2nd operand The contents of the MSB bit 7 are rotated into the LSB bit 0 and at the same time transferred to the CY flag f the 2nd operand cnt is 0 no processing is performed 7 0 Coding example ROL L 2 Rotates the contents of the L register 2 bits to the left 171 78K ll SERIES USER S MANUAL Rotate Right with Carry RORC Byte Data Right Rotation including Carry Instruction format RORC dst cnt Operation CY lt dsto 4517 lt CY dstm 1 lt dstm x cnt times cnt 0 to 7
174. s uPD78214 sub series uPD78212 78213 78214 78P214 78212 A 78213 A 78214 A 78P214 A uPD78218A sub series 1PD78217A 78218 78P218A 78218A A uPD78224 sub series uPD78220 78224 78 224 uPD78234 sub series uPD78233 78234 78237 78238 78 238 78234 A 78238 A uPD78244 sub series uPD78243 78244 The purpose of this manual is to give users an understanding of the various instruction functions of the 78K II series products This manual is broadly organized as follows e 78K ll series features 78K ll series products CPU functions Instruction set Description of instructions Development tools Built in Software Using the manual Legend When reading this manual a general knowledge of electrical and logic circuits and microcomputers is necessary To check details of the function of an instruction when the mnemonic is known gt Use the instruction indexes in Appendix A and B To check an instruction when the function is generally known but the mnemonic is not known gt Find the mnemonic from Chapter 7 then check the function of the instruction in Chapter 8 To get an overview of the function s of the 78K II series instructions gt Read the manual in accordance with the table of contents To learn about the hardware functions of the 78K II series gt Refer to the relevant separate User s Manual wPD78214 Sub Series User s Manual IEM 1236 e yPD78218A Sub Series Us
175. s Branch Branch NO Internal ROM Internal ROM NO External ROM External ROM branch a 2 branch Internal ROM External ROM Internal ROM External ROM BC addr16 2 2 4 6 6 7 9 BL BNC addr16 2 2 4 6 6 7 9 BNL BZ addr16 2 2 4 6 6 7 9 BE BNZ addr16 2 2 4 6 6 7 9 BNE BT saddr bit Saddr16 3 4 6 8 9 10 12 sfr bit adddr16 4 7 9 11 13 15 16 A bit 3 addr16 X bit Saddr16 3 5 7 8 9 10 12 PSW bit 3 addr16 Continued 134 CHAPTER 7 INSTRUCTION SET Clock cycles Internal ROM high speed fetch External ROM fetch Mnemonic Operands Bytes Branch Branch NO jnternal ROM Internal External External ROM branch branch ud Internal ROM External ROM Internal ROM External ROM BF saddr bit addr16 4 5 7 9 12 13 15 sfr bit adddr16 4 7 9 11 13 15 16 A bit 3 addr16 X bit Saddr16 3 5 7 8 9 10 12 PSW bit 3 addr16 BTCLR saddr bit addr16 4 5 9 9 12 15 15 sfr bit addr16 4 7 13 13 13 18 18 A bit 3 addr16 9 12 X bit addr16 3 5 9 9 15 PSW bit addr16 3 8 ti DBNZ r1 addr16 2 3 5 Y 6 7 9 saddr Saddr16 3 4 6 8 9 10 12 Clock cycles Mnemonic Operands Internal ROM high speed fetch External ROM fetch MOV STBC byte 9 15 SEL RBn 2 6 NOP 2 3 El 2 3 DI 2 3 135 78K ll SERIES USER S MANUAL Table 7 6 Table of Instruction Execution Cycles 1 4 Intern
176. s for Each Addressing Type Second First operand A bit A bit X bit X bit saddr bit saddr bit sfr bit sfr bit PSW bit PSW bit NoneNote operand CY MOV1 AND1 MOV1 AND1 MOV1 AND1 MOV1 AND MOV1 AND1 SET1 AND1 OR1 AND1 OR1 AND1 OR1 AND1 OR1 AND1 OR1 CLR1 OR1 OR1 OR1 OR1 OR1 NOT1 XOR1 XOR1 XOR1 XOR1 XOR1 A bit MOV1 SET1 CLR1 NOT1 BT BF BTCLR X bit MOV1 SET1 CLR1 NOT1 BT BF BTCLR saddr bit MOV1 SET1 CLR1 NOT1 BT BF BTCLR sfr bit MOV1 SET1 CLR1 NOT1 BT BF BTCLR PSW bit MOV1 1 CLR1 NOT1 BT BF BTCLR Note The second operand does not exist or is not an operand address 104 CHAPTER 7 INSTRUCTION SET 4 Call instructions and branch instructions CALL CALLF CALLT BR BC BT BF BTCLR DBNZ BL BNC BNL BZ BE BNZ and BNE Table 7 4 Call Instructions and Branch Instructions for Each Addressing Type Instruction addressing operand Basic instruction addr16 BR BCNote laddr16 CALL BR CALL BR laddr11 CALLF addr5 CALLT Composite instruction BT BF BTCLR DBNZ Note BL BNC BNL BZ BE BNZ and BNE are the same as BC 5 Other instructions ADJBA ADJBS BRK RET RETI RETB NOP El DI and SEL 105 78K ll SERIES USER S MANUAL 7 2 OPERATION CODES 7 2 1 Operation Code Symbols rir rl rp rp Re Ro GT Ro
177. sers who are also using IE 78220 RNote 1 an in circuit emulator of IE group 4 are recommended to upgrade to IE group 4 level IE 78130 R 2 IE 78230 R EM IE 78240 RNote 1 IE 78310 RNote 1 3 IE 78200 R EMNote 1 The high speed download function is not IE 78310A R IE 78230 R EMNote 2 supported Those users who an in circuit emulator of IE group 1 do not need to purchase the IE 78200 R EM the IE 78200 R EM board is built into the IE group 1 in circuit emulator 1 75000 4 IE 78200 R EMNote 1 Those users who have emulator 1 75001 IE 78230 R EM of IE group 1 do not need to purchase the IE 78000 R IE 78200 R EM the IE 78200 R EM board is IE 78320 RNote 1 built into the IE group 1 in circuit emulator IE 78327 R IE 78330 R IE 78350 R IE 78600 R IE 78140 R 5 IE 78200 R EMNote 1 Upgrading to IE 78230 R A level is IE 78240 R A IE 78230 R EM recommended Notes 1 This product is no longer produced and is not available from NEC 2 This board is used for emulation for the uPD78224 sub series Those users who already have the IE 78220 R EMNote 1 do not have to purchase this board 243 78K ll SERIES USER S MANUAL 9 3 5 Upgrading to IE 78220 RNote 1 Level Emulator IE group number Required board Remarks IE 78112 RNote 1 1 IE 78220 R EMNete 2 IE 78210 RNote 1 IE 78310 RNote 1 2 IE 78200 R EM Those users who have an in circuit emulator IE 78310A R IE 78220 R EMNote
178. specified in NEC s Data Sheets or Data Books If customers intend to use NEC devices for applications other than those specified for Standard quality grade they should contact NEC Sales Representative in advance Anti radioactive design is not implemented in this product M7 94 11 Major Changes Page p 3 9 18 Description A disaster crime prevention unit has been added as a special product in applications of the uPD78214 sub series uPD78218A sub series and uPD78234 sub series p 170 to p 177 Z AC and CY flags also do not change has been added to the sentence If the second operand cnt is 0 no processing is performed in Description of ROR ROL RORC ROLC SHR SHL SHRW and SHLW p 223 Chapter 9 Description related to the 3 5 inch 2HC has been added to IBM PC AT The HP9000 series 300 has been changed to the HP9000 series 700 p 237 The screen debugger of IBM PC AT and the 5 25 inch 2HC of the device file have been already developed p 239 4 OS for the IBM PC has been added p 248 e The Fuzzy inference debugger FD78K II has been already developed p 253 Appendix C has been added The mark shows major revised points Intended readership Purpose Organization PREFACE This manual is intended for engineers who wish to gain an understanding of the functions of the 78 seriesNote and design application systems using a device in this series Note 78K ll series product
179. ssembler Relocatable assembler program name RA78K2 Converts a source program written in assembly language into a machine language program enabling the generation of a relocatable object module file Linker program name LK78K2 Links an object module file generated by the relocatable assembler with a library file to determine the absolute address of the program and to generate a load module file Object converter program name OC78K2 Converts a load module file generated by the linker into a suitable form for downloading to the in circuit emulator and PROM programmer Librarian program name LB78K2 Links object module files generated by the relocatable assembler to create a single library file It also updates the library files List converter program name LCNV78K2 Creates an assemble list from the assemble list file output by the relocatable assembler using the object and load module files The assemble list contains absolute values CHAPTER 9 DEVELOPMENT TOOLS 1 Language processing software 2 3 78K ll series relocatable assembler RA78K II Host machine OS Distribution medium Part number PC 9800 series MS DOSTM 8 inch 2DNote 1 uS5A1RA78K2 2 r 5 25 inch 2HD uS5A10RA78K2 3 5 inch 2HD uS5A13RA78K2 IBM PC AT or See 4 5 25 inch 2DNote2 uS7B11RA78K2 companies 5 25 inch 2HC uS7B10RA78K2 3 5 inch 2HC uS7B13RA78K2 HP9000 series
180. st the type C macro service can be used with the addition of output data ring control a function for repeated transfers of a series of data and a function for automatic addition of the compare register and data etc The type C macro service can only be used with INTC10 and INTC11 interrupts and only certain SFRs can be used in the transfers The 64K byte memory space from 00000 to OFEFFH can be used Type C is suitable for stepping motor control etc by means of real time output port macro service 61 78K ll SERIES USER S MANUAL MEMO 62 CHAPTER 6 ADDRESSING 6 1 INSTRUCTION ADDRESS ADDRESSING The instruction address is determined by the contents of the program counter PC and is normally incremented automatically 1 for each byte in accordance with the number of instruction bytes fetched each time an instruction is executed However when an instruction involving a branch is executed the branch destination address is set in the PC in accordance with the addressing methods shown below and then the program branches to that address 6 1 1 Relative Addressing Function The value obtained by adding the 8 bit immediate data displacement value jdisp8 of the operation code to the start address of the next instruction is transferred to the program counter PC then a branch is performed The displacement value is treated as signed two s complement data 128 to 127 with bit 7 as the sign bit This is performed when
181. ster contents are 0 the start of this instruction is in the address range from 00344H to 00443H 210 CHAPTER 8 INSTRUCTION DESCRIPTIONS BNZ Branch if Not Zero Not Equal BNE Conditional Branch depending on Zero Flag Z 0 Instruction format BNZ addr16 BNE addr16 Operation PC lt PC 2 jdisp8 if Z 0 Operands Mnemonic Operands addr16 BNZ addr16 BNE Flags Description When Z 0 branches to the address specified by the operand When Z 1 no processing is performed and the next instruction is executed The operation of the BNZ instruction is the same Differences in their use are as follows BNZ instruction Checks whether the result of an addition subtraction or increment decrement instruction or an 8 bit logical operation is O BNE instruction Checks for a match after a compare instruction Coding example CMP A 55 BNE 0A39H Branches to 00A39H if the A register contents are not 0055H the start of this instruction is in the address range from 009B8H to 00AB7H 211 78K ll SERIES USER S MANUAL Branch if True BT Conditional Branch depending on Bit Test Byte Data Bit 1 Instruction format BT bit addr16 Operation PC lt PC b jdisp8 if bit 1 Operands Mnemonic Operands bit addr16 b Number of bytes BT saddr bit addr16 3 sfr bit addr16 4 A bit addr16 3 X bit addr16 3 PSW bit addr16 3 Flags
182. t src Operands Mnemonic Operands dst src MOV1 CY saddr bit CY sfr bit CY A bit CY X bit CY PSW bit saddr bit CY sfr bit CY A bit CY X bit PSW bit CY Flags dst CY PSW bit Other than cases at left Z AC CY Z AC CY Z AC CY x X X X Description Transfers the bit data of the source operand src specified by the 2nd operand to the destination operand dst specified by the 1st operand If the destination operand dst is CY or PSW bit only the relevant flag is changed Coding example MOV1 P3 4 CY Transfers the contents of the CY flag to bit 4 of port 3 184 CHAPTER 8 INSTRUCTION DESCRIPTIONS AND1 And Single Bit 1 Bit Data Logical Product Instruction format AND1 dst src Operation dst lt dst src Operands Mnemonic Operands dst src AND1 CY saddr bit CY sfr bit CY A bit CY X bit CY PSW bit Flags Description AND1 dst src dst lt dst src Mnemonic Operands dst src AND1 CY saddr bit CY sfr bit CY A bit CY X bit CY PSW bit Obtains the logical product of the bit data of the destination operand dst specified by the 1st operand and the source operand src specified by the 2nd operand and stores the result in the destination operand dst f the 2nd operand is prefixed with the logical product after logical negation of the source operand src is obtained The result of
183. t immediate data word Label or 16 bit immediate data Coding example General example ADD A byte Operation code 1010 1001 Data Specific example ADD A 77 When 77H is used for byte Operation code 1010 1000 0111 0111 69 78K ll SERIES USER S MANUAL 6 2 4 Short Direct Addressing Function This addressing method uses 8 bit immediate data in the instruction word to directly address the memory to be manipulated in a fixed space This kind of addressing can be used with most instructions and allows various kinds of data to be manipulated using a small number of bytes and clock cycles This addressing method is used on the 256 byte space from OFE20H to OFF1FH Internal RAM is mapped onto addresses OFE20H to OFEFFH and special function registers SFR onto addresses FFOOH to FF1FH The SFR area OFFOOH to OFF1FH on which short direct addressing is used has mapped onto it the ports timer counter unit compare registers and capture registers frequently used by the program These SFRs can be manipulated using a small number of bytes and clock cycles Bit 8 of the effective address is 0 when the 8 bit immediate data is 20H to FFH and 1 when OOH to 1FH Operand format This type of addressing is used when executing instructions which include saddr or saddrp in their operands In an instruction using saddrp two bytes of data can be accessed The memory addressed by the effective address as the lower byte and the memor
184. t of decrementing the destination operand dst by 1 is not 0 the instruction branches to the address indicated by the 2nd operand addr16 If the result of decrementing the destination operand dst by 1 is 0 no processing is performed and the next instruction is executed Flags are not changed Coding example DBNZ B 1215H Decrements the contents of the B register and if the result is not 0 branches to 001215H the start of this instruction is in the address range from 001194H to 001293H 215 78K ll SERIES USER S MANUAL 8 14 CPU CONTROL INSTRUCTIONS CPU control instructions are as follows MOV STBC byte 217 SEL RBn 218 we 219 El 220 DI 221 216 CHAPTER 8 INSTRUCTION DESCRIPTIONS MOV STBC byte Move Standby Mode Setting Instruction format MOV STBC byte Operation STBC lt byte Operands Mnemonic Operands MOV STBC byte Flags Description This is a dedicated write instruction for the standby control register STBC This instruction writes the immediate data specified by the 2nd operand to STBC Only this instruction can be used to write to the STBC register This instruction has a special format and in addition to the immediate data used in performing the write the operation code must also provide data resulting from the logical negation of that value see figure below This is generated automatically by NEC assemblers
185. te 1 MOV MOV MOV MOV MOV MOV MOV MOV XCH XCH XCH XCH XCH ADDNote 1 ADDNote 1 ADDNote 1 ADDNote 1 r MOV MOV ROL MULU XCH ROLC DIVUW ADDNote 1 ROR INC RORC DEC SHR SHL DBNZ saddr MOV MOV MOV INC ADDNote 1 DBNZ ADDNote 1 DEC sfr MOV MOV PUSH ADDNote 1 POP mem MOV amp mem mem1 ROR4Note 3 amp mem1 ROL4Note 3 laddr16 MOV amp laddr16 MOV PSW MOV MOV PUSH POP STBC MOV Notes 1 ADDC SUB SUBC AND and CMP are the same as ADD 2 The second operand does not exist or is not an operand address 3 Cannot be used for EEPROM area of the 78244 sub series 102 CHAPTER 7 INSTRUCTION SET 2 16 bit instructions MOVW ADDW SUBW CMPW INCW DECW SHRW SHLW PUSH and POP Table 7 2 16 Bit Instructions for Each Addressing Type Second word AX rp saddrp sfrp mem1 amp mem1 SP n None First operand ADDW ADDW MOVW MOVW MOVW MOW MOVW SUBW SUBW ADDW ADDW CMPW CMPW SUBW SUBW CMPW CMPW rp MOVW MOVW SHLW INCW SHRW DECW PUSH POP saddrp MOVW MOVW sfrp MOVW MOVW 1 MOVWNote amp 1 SP MOVW MOVW INCW DECW Note Cannot be used for EEPROM area of the u PD78244 sub series 103 78K ll SERIES USER S MANUAL 3 Bit manipulation instructions MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 BT BF and BTCLR Table 7 3 Bit Manipulation Instruction
186. terrupt is acknowledged Register bank selection flag RBS0 RBS1 This is a 2 bit flag which selects one of four register banks see Table 4 1 2 bit information indicating the selected register bank is stored by execution of the SEL RBn instruction Table 4 1 Register Bank Selection RBS1 RBS0 Specified Register Bank 0 0 Register bank 0 0 1 Register bank 1 1 0 Register bank 2 1 1 Register bank 3 Auxiliary carry flag AC This flag is set 1 in the event of a carry out of bit 3 or a borrow into bit 3 as the result of an operation and reset 0 otherwise The AC is used when a BCD adjustment instruction is executed Zero Z This flag is set 1 when the result of an operation is zero and reset 0 otherwise Interrupt request enable flag IE This flag controls CPU interrupt request acknowledgment operations When 0 the interrupt disabled state is set and only acknowledgment of nonmaskable interrupts and macro service with masking released is possible other interrupts are disabled When 1 the interrupt enabled state is set and enabling of interrupt request acknowledgment is controlled by the ISP flag the interrupt mask flag corresponding to the particular interrupt request and the priority specification flag The IE flag is set 1 by execution of the El instruction and reset 0 by execution of the DI instruction or interrupt acknowledgment CHAPTER 4 REGISTERS 4 1 3 Stack Pointer
187. tes uPD78244 OFDOOH to OFEFFH OFDOOH to OFDFFH Internal dual port RAM IRAM 256 bytes to OFEFFH Internal dual port RAM IRAM allows high speed access In particular the area from OFE20H to OFEFFH can be used in short direct addressing mode for high speed access This area is mapped as shown below General register OFEEOH to OFEFFH Macro service control word OFEC2H OFED4HNote to OFEDFH Peripheral RAM PRAM is used as ordinary data memory Note 1 PD78224 sub series 44 8 registers x 8 bits x 4 banks 30 12Note x 8 bits CHAPTER 3 MEMORY SPACE Internal RAM mapping is shown in Figure 3 2 Figure 3 2 Internal RAM Mapping General registers control registers permissible area Address depends on the product Cautions 1 Program fetching is not possible from the internal RAM area 2 Inthe uPD78224 sub series peripheral RAM PRAM cannot be used when the refresh function is used Remark It is effective to locate frequency accessed data work areas status flags etc in the area OFE20H to OFEC1H OFED3HNote Also using the area from to OFE1FH for the stack areaorthe areafor macro service channel and macro service datatransfers allows fast accesses and is thus effective in improving system throughput Short direct addressing cannot be used on this area Itis manipulated in the same way as the rest of the memory space However since this
188. the operation is stores in the CY flag since it is the destination operand dst Coding example AND1 CY OFE7FH 3 Obtains the logical product of bit 3 of OFE7FH and the CY flag and stores the result in the CY flag AND1 PSW 6 Obtains the logical product of the logical negation of PSW bit 6 the Z flag and the CY flag and stores the result in the CY flag 185 78K ll SERIES USER S MANUAL OR1 Or Single Bit 1 Bit Data Logical Sum Instruction format OR1 dst src Operation dst dst v src Operands Mnemonic Operands dst src OR1 CY saddr bit CY sfr bit CY A bit CY X bit CY PSW bit Flags Description OR1 dst src dst dst v src Mnemonic Operands dst src OR1 CY saddr bit CY sfr bit CY A bit CY X bit CY PSW bit Obtains the logical sum of the bit data of the destination operand dst specified by the 1st operand and the source operand src specified by the 2nd operand and stores the result in the destination operand dst Ifthe 2nd operand is prefixed with the logical sum after logical negation of the source operand src is obtained The result of the operation is stored in the CY flag since it is the destination operand dst Coding example OR1 CY P2 5 Obtains the logical sum of bit 5 of port 2 and the CY flag and stores the result in the CY flag OR1 X 0 and stores th
189. time There are three types of macro service A B and C 1 Type A One byte of data is transferred between a special function register SFR and memory each time an interrupt request is generated and when the specified number of data transfers have been performed a vectored interrupt request is generated The SFR involved in the transfer is fixed for each interrupt request and memory is limited to addresses OFE00H through 0FEFFH in internal RAM The specification method is simple making this type suitable for small volume high speed data transfers 2 Type B As with type A one byte of data is transferred between a special function register SFR and memory each time an interrupt request is generated and when the specified number of data transfers have been performed a vectored interrupt request is generated The SFR and memory involved in the transfer are specified by the macro service channel memory is limited to the 64K byte space from 00000H to OFEFFH This is a general purpose version of type A suitable for use with a large volume of transfer data 3 Type C Each time an interrupt request is generated data is transferred one byte at a time from memory to the real time output port and the 8 bit timer counter 1 compare register When the specified number of data transfers have been performed a vectored interrupt is generated In addition to performing data transfers to two locations in response to a single interrupt reque
190. to IE 78230 R A Level Emulator IE group number Required board Remarks IE 78240 R A 1 IE 78230 R EM IE 78140 R IE 78230 RNote 1 2 IE 78200 R BK IE 78112 RNote 1 3 IE 78200 R BK The high speed download function is not IE 78210 RNote 1 IE 78230 R EMNote 2 supported Those users who are also using IE 78220 RNote 1 an in circuit emulator of IE group 1 2 or 4 IE 78310 RNote 1 are recommended to upgrade these emulators IE 78310A R also Those users with an in circuit emulator of IE group 1 do not need to purchase the IE 78200 R BK the IE 78200 R BK board is built into the IE group 1 in circuit emulator IE 75000 R 4 IE 78200 R BK Those users with an in circuit emulator of IE IE 75001 R IE 78230 R EM group 1 do not need to purchase the IE 78000 R IE 78200 R BK the IE 78200 R BK board is IE 78130 R built into the IE group 1 in circuit emulator IE 78240 R IE 78320 RNote 1 IE 78327 R IE 78330 R IE 78350 R IE 78600 R Notes 1 This product is no longer produced and is not available from NEC 2 This board is used for emulation for the LPD78224 sub series Those users who already have the IE 78220 R EMNote 1 go not have to purchase this board 242 CHAPTER 9 DEVELOPMENT TOOLS 9 3 4 Upgrading to IE 78230 RNote 1 Level Emulator IE group number Required board Remarks IE 78112 RNote 1 1 IE 78230 R EMNote 2 The high speed download function is not IE 78210 RNote 1 supported Those u
191. trademarks of IBM Corporation SPARCstation is a trademark of SPARC International Inc SunOS is a trademark of Sun Microsystems Corporation HP9000 series 700 and HP UX are trademarks of Hewlett Packard Company TRON is an abbreviation of The Realtime Operating system Nucleus ITRON is an abbreviation of Industrial TRON The export of these products from Japan is regulated by the Japanese government The export of some or all of these products may be prohibited without governmental license To export or re export some or all of these products from a country other than Japan may also be prohibited without a license from that country Please call an NEC sales representative The information in this document is subject to change without notice No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation NEC Corporation assumes no responsibility for any errors which may appear in this document NEC Corporation does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device No license either express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Corporation or others While NEC Corporation has been making continuous effort to enhance the relia
192. uPD78P214DW uPD78212CW A xxx uPD78212GC A x AB8 uPD78213CW A uPD78213GQ A 36 uPD78214CW A xxx uPD78214GC A xxx AB8 uPD78214GJ A xxx 5BJ uPD78214GQ A xxx 36 uPD78214L A xxx uPD78P214CW A uPD78P214GC A AB8 Package 64 pin plastic shrink DIP 750 mil 64 pin plastic 14 x 14 mm body 74 pin plastic QFP 20 x 20 mm body 64 pin plastic shrink DIP 750 mil 64 pin plastic 14 x 14 mm body 74 pin plastic QFP 20 x 20 mm body 64 pin plastic QUIP 68 pin plastic 950 mil 64 pin plastic shrink DIP 750 mil 64 pin plastic 14 x 14 mm body 74 pin plastic QFP 20 x 20 mm body 64 pin plastic QUIP 68 pin plastic 950 mil 64 pin plastic shrink DIP 750 mil 64 pin plastic QFP 14 x 14 mm body 74 pin plastic QFP 20 x 20 mm body 64 pin plastic QUIP 68 pin plastic 0950 mil 64 pin ceramic shrink DIP with window 750 mil 64 pin plastic shrink DIP 750 mil 64 pin plastic QFP 14 x 14 mm body 64 pin plastic shrink DIP 750 mil 64 pin plastic QUIP 64 pin plastic shrink DIP 750 mil 64 pin plastic QFP 14 x 14 mm body 74 pin plastic QFP 20 x 20 mm body 64 pin plastic QUIP 68 pin plastic L1 950 mil 64 pin plastic shrink DIP 750 mil 64 pin plastic QFP 14 x 14 mm body Remark xxx is the ROM code number On chip ROM Mask ROM Mask ROM Mask ROM None None None None None Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM One time PROM One time P
193. ulation BCD adjustment etc Package 22 80 pin plastic QFP 14 x 14 mm body 94 pin plastic QFP 20 x 20 mm body 84 pin plastic QFJ 11150 mil 94 pin ceramic WQFN uPD78P238 only CHAPTER 1 78K II SERIES FEATURES 1 5 5 Block Diagram 89 2 peegzadrl eezg adr WWHd reJeudueg WV 2 YZE 91 vezg adr JON 6 8 adrl eezgZ adr 1 19481694 BJGUBE gt LLd L9d 9d Sd Led LEd Zd Ld LOd 8 eui 10 044 OSd Old 00 luo ML 438AV pepe Ul pepeus 4 ON 0ONV 8 SSAV ddA VV JeueAuo9 Lau AY E INV 0INV ldsau 8 lt gt snq eyeq ex o Jeuueuo 9 Lx 99IAJ8S d zao S 1 q 962 5 Jeouenbes 5 105590010 9 sia 8 Sd z Jeuueuo 39 WOH B ue loog 8 oO gisv 5 M 08434 e sJejsiDoJ LIVM Ayesodwa 5 Laon
194. ut Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products are classified according to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers offi
195. vices are acknowledged between this instruction and the next instruction to be executed 197 78K ll SERIES USER S MANUAL Return from Break RETB Return from Software Vectored Interrupt Instruction format RETB Operation PCL lt SP PCH lt SP 1 PSW lt SP 2 SP lt SP 3 Operands None Flags Description This instruction is used to return from a software interrupt generated by the instruction The PC and PSW saved to the stack are restored and a return is made from the interrupt service routine No interrupts or macro services are acknowledged between this instruction and the next instruction to be executed 198 CHAPTER 8 INSTRUCTION DESCRIPTIONS 8 11 STACK MANIPULATION INSTRUCTIONS Stack manipulation instructions are as follows PUSH POP MOVW SP src MOVW AX SP INCW SP DECW SP 200 201 202 202 203 204 199 78K ll SERIES USER S MANUAL PUSH Push Push Instruction format Operation Operands Mnemonic PUSH Flags Description Saves the data in the register specified by the source operand src to the stack Coding example PUSH src When src rp SP 1 lt SP 2 srci SP lt SP 2 Operands src PSW sfr rp CY When src PSW or sfr SP 1 src SP SP 1 PUSH AX Saves the contents of the AX register to the stack
196. x x nr 2 r CY lt r r x x A saddr 2 A CY lt A saddr x x A sfr 3 A CY lt A sfr x x saddr saddr 3 saddr CY lt saddr x x A mem 2 4 A CY lt mem x x A amp mem 3 5 A CY lt amp mem x x SUBC A byte 2 A CY lt A byte CY x x saddr byte 3 saddr CY lt saddr byte CY X x sfr byte 4 sfr CY lt sfr byte CY x X nr 2 lt x x A saddr 2 A CY lt A saddr X X A sfr 3 A CY lt A sfr CY x x saddr saddr 3 saddr CY lt saddr saddr CY x x A mem 2 4 A CY lt A mem x x A amp mem 3 5 A CY lt A amp mem x X Continued 92 CHAPTER 7 INSTRUCTION SET Mnemonic Operand No of Operation Flags bytes AND A byte 2 byte saddr byte 3 saddr saddr byte str byte 4 sfr sfr byte rr 2 r A r A saddr 2 A A saddr A sfr 3 sfr saddr saddr 3 saddr lt saddr saddr A mem 2 4 A A mem A amp mem 3 5 A A amp mem OR A byte 2 A A v byte saddr byte 3 saddr saddr v byte str byte 4 sfr sfr v byte rr 2 r lt r v r A saddr 2 A v saddr A sfr 3 A A v sfr saddr saddr 3 saddr saddr v saddr A mem 2 4 A
197. y 64 pin ceramic shrink 64 pin plastic QUIP Except uPD78212 DIP with window 64 pin ceramic shrink uPD78P218A only DIP with window uPD78P214 only 34 CHAPTER 2 78K ll SERIES PRODUCTS 3 3 uPD78234 sub series uPD78244 sub series uPD78233 uPD78234 uPD78237 uPD78238 uPD78P238 uPD78243 uPD78244 2 levels programmable vectored macro service 7 12 14 8 16 bits selectable except Type A 16 bits incremented Macro service execution time of the uPD78214 series is the same as that of the uPD78224 series Macro service execution time of the uPD78218A series is the same as that of the uPD78234 series or that of the uPD78244 series The execution time varies depending on the mode Compare these products by referencing their User s Manuals Generated when transfer data is DOH to DFH Generated when transfer source buffer memory address is OFEDOH to OFEDFH HALT STOP mode Choice of two times Yes Refresh pulse width 1 None MODE pin MODE pin EA pin high level high level low level not settable e 84 pin plastic QFJ 111150 mil 64 pin plastic shrink 80 pin plastic QFP 14 x 14 mm body DIP 750 mil 94 pin plastic QFP 20 x 20 mm body 64 pin plastic QFP 94 pin ceramic WQFN uPD78P238 only 14 x 14 mm body 35 78K ll SERIES USER S MANUAL MEMO 36 CHAPTER 3 MEMORY SP
198. y in the next address as the higher byte Identifier Description saddr Label or immediate data between FE20H and FF1FH saddrp Label or immediate data between FE20H and FF1EH Coding example General example MOV saddr saddr Operation code 00 1 1 1000 Saddr offset 2nd operand source Saddr offset 1st operand destination 70 CHAPTER 6 ADDRESSING Specific example MOV OFE30H OFE50H Operation code 0 0 0101 Illustration Effective address 1 1 1000 2nd operand source 0000 1st operand destination 1 1 0000 OP code Saddr offset Short direct memory i 5 15 987654 0 71 78K ll SERIES USER S MANUAL 6 2 5 Special Function Register SFR Addressing Function This addressing method uses 8 bit immediate data in the instruction word to address a memory mapped special function register SFR The SFR mapped space on which this type of addressing is used is the 256 byte space from OFFOOH to OFFFFH However SFRs mapped onto addresses OFFOOH to OFF1FH can be also accessed by short direct addressing Remark With NEC s assembler package RA78K II instructions on SFRs mapped onto addresses to OFF1FH use short direct addressing automatically forcibly Operand format SFR addressing is used when executing instructions with the operand formats shown below Identifier Description sfr Special function register name sfr
199. yte sfr byte rr A saddr A sfr saddr saddr A mem A amp mem Flags Description Obtains the bit by bit exclusive logical sum of the destination operand dst specified by the 1st operand and the source operand src specified by the 2nd operand and stores the result in the destination operand dst The logical negation of all bits of the destination operand dst can be obtained by selecting as the source operand src of this instruction Ifall bits are 0 as a result of obtaining the exclusive logical sum the Z flag is set 1 otherwise the Z flag is cleared 0 Coding example XOR A P2 Obtains the bit by bit exclusive logical sum of the A register and the P2 register and stores the result in the A register 155 78K ll SERIES USER S MANUAL Compare Byte Data Comparison CMP Instruction format dst src Operation dst src Operands Mnemonic Operands dst src CMP A byte saddr byte sfr byte nr A saddr A sfr saddr saddr A mem A amp mem Flags Description Subtracts the source operand src specified by the 2nd operand from the destination operand dst specified by the 1st operand The result of the subtraction is not stored anywhere only the Z AC and CY flags are changed f the result of the subtraction is O the Z flag is set 1 otherwise the

78K/II SERIES 8-BIT SINGLE-CHIP UM

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