Module A9M9360_2 - Digi International
Contents
1. 14 3 8 Chip Selects Memory Map nen 14 3 9 NAND Fl sh neces dee divae loe ud evt ne orden iode else 15 3 10 1 2 16 64 MBytes SDRAM ns utn dee aee get 16 3 11 Usage of 2 SDRAM bark cn ect tet erobert im en 16 3 12 73 GPIO Pins multiplexed with other Functions 17 3 13 External 23 3 14 10 100Mbps Ethernet 23 3 15 USB 2 0 full and low speed Host and Device Controller 24 3 16 UART Channels eeen er rrt aeea aerea Eee REEE ENEE PERTE 24 3 17 SPI Channel S iicet ata 24 3 18 Usage UART and SPI on A9M9360 24 3 19 Bauidrate Table ians ire RR ET ERR REA TERR RR 26 3 20 FG BUS 27 3 21 LCD Controller STN 27 3 22 Serial EEPROM for storing Configuration Parameters 28 2 22 ecp rc 28 3 24 JTAG Boundary Scan 900000000000000000000 28 3 25 Single 3 3V Power Supply Power Sequencing 29 EEE 5101011 01 0 C1 MA CAE die A T ties Mie 30 Module 9 9360 22. hate eae 5 1 Software Hifits vee Dev eo o 64 MGCHARl6S ree eet Sete 6 1 Extended 7 Known Faults and 7 1 SDRAM Clocks Clockout1 3 not switchable 7 2 2 Setup Time Data always half low time of Clock 7 3 SPI Boot System needs Hardware Workaround 2 01 8 Appendix sec E eaten t ag ab Heb ea t Pinning Mod ler eniti e Gea ee 8 2 Pinning Description Module rette 8 3 Pinning Module on A9MVali Validation Board 8 4 Pinning Module on Development Module 9 9360 2 1 Revision History 2005 03 09 V1 00 KR Initial Version derived from 9 9360 1 spec 2005 04 05 V1 00 KR Transfer to standard document format 2005 05 30 V1 00 KR Migration to 9 9360 2 Module 9 9360 2 2 General A9M9360 Module is a member of the ModARM9 family with a NetSilicon NS9360 CPU The ModARM9 family includes several modules with the same size connectors and a set of common pins and functions see Arm9 module pinning table xls with CPUs
3. 3 23 RTC MAXIM DALLAS 051337 in uSOP8 case on the module is connected to the bus device address OxDO OxD1 It has its own 32 768KHz clock crystal Power is taken from 3 3V when provided otherwise from fed by an external battery An interrupt line GPIO13 configured as IRQO is connected to the RTC pin AINT open drain default disabled the connection can be opened by depopulating resistor R2 3 24 JTAG Boundary Scan NS9360 support JTAG and boundary scan with the signals TCK TMS TDI TDO and TRST The signal RTCK is not connected to external Selection between normal mode and debug mode is done with the external signal DEBUG_EN HCONFO Selection between ARM debug mode and boundary scan mode is done with the signal OCD_EN HCONF2 See table below normal not recommended Sn SE Scan possible here too but TRST is connected with SRST system may hang 0 11 CLARM debug CEE L 0 0 BoundayScan 28 Module 9 9360 2 3 25 Single 3 3V Power Supply Power Sequencing The module has 3 3V_IN and VLIO 3 3V too for A9M9360 supply pins Internal voltages 1 5V core voltage with up to 400mA will be converted by a switching regulator from VLIO to keep losses small Power up and power down behaviour recommended by NetSilicon for the NS9360 see 9360 power sequencing doc from NetSilicon will be ensured by hardware Due to generation of 1 5V from 3 3V IN or
4. SDA 1284D4 LCDD11 LCD 19 Module 9 9360 2 Port Alternate Alternate Alternate Alternate Module on Function Function Function Function Function DEV Board 03 default 00 UART 00 misc 01 02 default usage at power up 1 PWMO 128405 LCDD12 LCD 1 128406 LCDD13 LCD PWM2 128407 LCDD14 LCD GPIO39 PWMS 128408 LCDD15 LCD GPIO42 RTSC Reserved USB_PHY USB_EXTPH _D Y D 44 TXDD SPID_DO 1284 USB _ PH USB EXTPH SELECT TXOUT Y_OE EN STRB _RXD Y_RXD E iiie INIT USB PHY acad _RXD drives DEBUG LED _SUSP P SEL REQ Y SUSP 8 USB_PHY 1284 DMA R B NAND _SPEED P_LOG DONE Flash GPIO control on module _D LIE _D dupe secl BIN on d d son TXOUT Module 9 9360 2 Port Alternate Alternate Alternate Alternate Module on Function Function Function Function Function DEV Board 03 default 00 UART 00 misc 01 02 default usage at power up RXDO Reserved 05 RXDO _RXD dupe x e _SUSP dupe MII RXD2 Reserved USB PHY RXD2 mm ES dupe MII RXD3 Reserved USB PHY m mmm dupe GPIO57 Reserved USB PHY MII TXEN dE and dupe GPIO58 MII TXER Reserved Reserved MII TXER GPIO59 MII T
5. Dedicated 2 pins IIC_SDA and IIC_SCK on A9M9750 can be GPIO70 71 or A26 A27 on 9 9360 also 8 timers A9M9360 16 on 9 9750 4 PWM channels added on A9M9360 each uses 2 timers Additional USB device modul on A9M9360 needs external USB PHY connected to GPIO42 48 Module 9 9360 2 2 3 Existing Variants of 9 9360 1 Current state 02 2005 1 0381 CPU speed 177MHz 16MByte SDRAM 32MByte NAND flash 8KByte SPI boot EEPROM 8KByte I2C EEPROM RTC 0 70 0382 CPU speed 177MHz 32MByte SDRAM 32MByte NAND flash 8KByte SPI boot EEPROM 8KByte I2C EEPROM RTC 0 70 0383 CPU speed 177MHz 64MByte SDRAM 64MByte NAND flash 8KByte SPI boot EEPROM 8KByte I2C EEPROM RTC 0 70 Due to a bug in the NS9360 CPU the module generation A9M9360_1 is stopped A safe start in SPI boot mode needs a hardware workaround realised A9M9360 2 2 4 Existing Variants of 9 9360 2 Current state 05 2005 4 0381 CPU speed 177MHz 16MByte SDRAM 32MByte NAND flash 8KByte SPI boot EEPROM 8KByte I2C EEPROM RTC 0 70 0382 CPU speed 177MHz 32MByte SDRAM 32MByte NAND flash 8KByte SPI boot EEPROM 8KByte I2C EEPROM RTC 0 70 0383 CPU speed 177MHz 64MByte SDRAM 64MByte NAND flash 8KByte SPI boot EEPROM 8KByte I2C EEPROM RTC 0 70 Module 9 9360 2 3 Detailed Description 3 1 Size 60 x 44 mm 9 9360 module has a size of 60 44 mm 3 2 2x 120 pin Con
6. independant USB device channel is provided when an external unidirectional or bidirectional PHY is connected to the USB device control signals GPIO42 45 48 In this case the internal PHY has to be used in host mode 3 16 UART Channels Up to 4 UART channels with all handshake signals are provided channels 8 15 0 7 C GPIO20 23 amp GPIO40 43 D GPIO24 27 amp 44 47 They be used in asynchronous mode as UART Baud rates are supported up to 1 8MHz in asynchronous mode 3 17 SPI Channels Four SPI channels are provided by the NS9360 Usage in master or slave mode is possible SPI channel B GPIOO 1 6 7 is connected to the serial 8Kx8 SPI EEPROM containing the boot program and the initial SDRAM parameters for booting via SPI when RESET is asserted External usage of this channel after boot at runtime is provided with additional hardware The other SPI channels can be used free if not used in UART or LCD or USB mode or blocked by other GPIO usage 3 18 Usage UART and SPI on A9M9360 Module ARMSO9 modules have 2 serial ports A B wired with at least TXD RXD RTS and CTS as common port lines 24 Module 9 9360 2 NS9360 chip allows only the usage of UART channels A B for UART and or SPI function if the LCD function is used too If all signals of the LCD function realised on the module are used channel C for UART and or SPI function is blocked Usage USB with externa
7. 15 Module 9 9360 2 3 10 1 2 16 64 MBytes SDRAM Two SDRAM banks are available on the module They are connected to CS4 D_CSO and CS5 D_CS1 CS6 D_CS2 and CS7 D_CS3 are lost The module does not provide external SDRAM connection A9M9360 has one or two 1X4MX32 2X4MX32 or 4X4MX32 SDRAM onboard The highest address connected is A12 Range of chip select is 256M BAO 1 are connected to A13 14 The SDRAM controller connects the right address line to allow a gapless memory space at different SDRAM sizes 3 11 Usage of 2 SDRAM bank SPI loader used on 9 9360 module initializes only SDRAM bank 0 with SD 50 When the system is running from SDRAM the 274 bank cannot be initialized because it uses the same registers for different parameters as the running bank Especially the Dynamic Memory Control Register has to be changed from normal to set mode command while starting the 274 bank So the initialization routine has to be run either from NOR flash if booting with flash or from another memory place A good choice may be the ethernet TX buffer descriptor RAM starting at address 0 0601000 with a space of 256 32bit words Before using this RAM it must be enabled by setting bit 23 of the Ethernet General Control register 1 to high 16 Module 9 9360 2 3 12 73 Pins multiplexed with other Functions NS9360 has 73 GPIO pins 23 more than NS9750 All pins are multiplexed with
8. Extended Module For further modules the ModARMO family it might be necessary to have some additional hardware placed on the module which will need more signal lines connected between module and base board than currently available To meet these future requirements an extended board was defined which has two additional board to board connectors with 60 pins each The size of the extended module is defined as 92 x 44mm Two holes for M2 screws catercornered are provided to enable fixing of the module on the base board Board to Board Distance h Module Connector X3 X4 Base Board Connector X3 X4 33 Module 9 9360 2 No of Pins Qty Supplier Order No No Of Supplier Order No Pins 5mm 60 AMP 177984 2 Berg 61083 061009 6mm 60 AMP 179029 2 60 2 AMP 177983 2 Berg 61083 062009 7mm Berg 61082 061009 60 AMP 179030 2 Berg 61083 063009 8mm 60 AMP 179031 2 Berg 61083 064009 34 Module 9 9360 2 T Known Faults and Limitations T 1 SDRAM Clocks Clockout1 3 not switchable Only SDM CLKOUTO can be switched off by software Switching SDM CLKOUT 1 3 does not work CPU fault can be fixed only by NetSilicon Workaround None all 4 signals used on module with 2 SDRAM banks equipped 7 2 2 Setup Time Data always half low time of Clock I2C_SDA from NS9360 changes after half low time of I2C_SCL instead of short time afte
9. LCD D8 and SPIB_CE dupe DMAOACK dupe EIRQ2 GPIO32 _LCDD8 1284 DO GPIO11 CTSA 0 dupe EIRQ3 GPIO40 TXDC SPIC DO GPIO18 LCD PWREN LCDD16 ETH CAMREJ EIRQO and EIRQ1 have a third position on the NS9360 EIRQO dupe GPIO68 also A24 EIRQ1 dupe GPIO69 also A25 Both address lines are routed to the modules connectors If not used on the base board or application the interrupts are available by changing the GPIO configuration 3 14 10 100Mbps Ethernet Port The 10 100Mbps Ethernet port of the NS9360 allows a glueless connection of a 3 3V MII or RMII PHY chip that generates the physical Ethernet signals The module has a MII PHY chip LXT972 in a LQFP 64 case on board No transformer or Ethernet connector is on the module these parts have to be 23 Module 9 9360 2 provided by the base board PHY clock of 25MHz is generated the PHY chip with a 25MHz crystal 3 15 USB 2 0 full and low speed Host and Device Controller The USB section of the NS9360 CPU provides USB signals for a host and device channel All external configuration for a USB host and or a USB device interface has to be made on the base board 48MHz USB clock is generated on the CPU with a 48MHz crystal in fundamental configuration The internal USB PHY in the NS9360 CPU can be used for the USB host or device channel USB INTPHY DP USB INTPHY DN These signals are not 5V tolerant and have to be protected on the base board A 2
10. GPIO70 and muxed signal A26 lost and SDA GPIO71 and muxed signal A27 lost is connected on the module to a serial EEPROM with interface on device address OxAO OxA1 Device address 0 0 OxD1 connects to an RTC on board All other addresses can be used externally Due to a timing bug in the I C state machine the maximum clock frequency in slow mode should be 50KHz and 200KHz in fast mode Otherwise minimum setup time for the target can be violated SDA changes after half low time of SCK instead of shortly after falling edge so setup time for data is 2 5us 100KHz and 612 5ns 400KHz Important Use only 3 3V devices 3 21 LCD Controller STN amp TFT An LCD interface for STN or TFT LCD s is provided with up to 18 data lines and 6 control lines Usage for LCD disables serial ports C D and most GPIOs The module provides the full LCD interface 18 data lines LCCDO 17 GPIO24 41 and 6 control lines GPIO18 23 This interface allows connection of most TFT and STN monchrome and color LCDs Details see NS9360 hardware user manual 27 Module 9 9360 2 3 22 Serial EEPROM for storing Configuration Parameters The nonvolatile storage of parameters like MAC address etc is supported with a serial 8Kx8 EEPROM 24LC64 or similar in TSSOP8 case connected to the lC bus at device address 0 OxA1 Write protect WP and optional address lines 0 A1 A2 are grounded some manufacturers leave these pins n
11. at power up GPIO7 DCDB SPI Boot DMAO Ack EIRQ1 DCDB CE dupe SPI Boot CE SPIB_CE or external ext SPIB_CE TXCLK_A GPIO8 TXDA SPIA DO TXDA SPI A GPIO9 RXDA SPIA DI RXDB SPI A 6 0 dupe dupe dupe ere over dupe EIRQO PWM2 EIRQO dupe dupe connected to RTC_INT on module GPIO13 DSRA GPIO14 SPIA Timer 1 ext RXCLK B GPIO15 DCDA Timer2 LCD CLKI SPIA ext N TXCLK_B GPIO16 USB 1284 Reserved USB OVCUR mM UE t dupe GPIO17 USB Reserved Reserved USB PREL m Bree Rela GPIO18 Ethernet LCD EIRQ3 LCD mI E Reject 18 Module 9 9360 2 Port Alternate Alternate Alternate Alternate Module on Function Function Function Function Function DEV Board 03 default 00 UART 00 misc 01 02 default usage at power up GPIO19 Ethernet LCD DMA1 ACK LCD CAM HSYNC dupe Request 20 LCD CLK Reserved VFSYNC GPIO22 Bod SPIC CLK LCD Reserved RXCLK C GPIO23 DCDC SPIC_ ie Reserved LCD ud a XCL a TXCLK_C GPIO24 DTRD LCDDO GPIO25 DSRD LCDDf GPIO26 RID SPID_CLK LCDD2 Timer 3 LCD al RXCLK_D 27 DCDD SPID_ LCDD3 Timer 4 eiu TXCLK_D dupe dupe Fees pte DE dupe e DM T dupe ae dupe 2 EIRQ2 128401 LCDD8 LCD GPIO33 Reserved 128402 LCDD9 LCD GPIO34 INC SCL 128403 LCDD10 LCD 610535
12. be read in GEN ID register bit 31 default high Recommended Combinations of DEBUG EN ON not recommended may hang avoid OFF Module 9 9360 2 3 6 Clock Generation Summary Clock Frequencies on 177MHz Module Clock Tape Settings Result Crystal 29 4912MHz PLL_ND 4 0 PLL Multiplier b10010 d24 CPU PLL active PLL_FS 1 0 PLL divider b11 d2 CPU PLL active PLL IS 1 0 value b11 ND16 31 CPU PLL active resulting PLL clock 353 8944 MHz CPU clock 176 9472 MHz AHB SDRAM and external clock 88 4736 MHz BCLK clock 44 2368 MHz UART Baud Rate Clock BBus 44 2368 MHz LCD clock 88 4736MHz 44 2368MHz 22 1184MHz or 11 0592MHz By writing in the NDSW CPCC FSEL and PLLSW fields of the SCON PLLCR register the CPU speed can be changed IMPORTANT Changing PLL parameters ends with a 4 ms RESET to allow changed PLL to stabilize Applications using this feature have to discriminate between cold start and warm start 13 Module 9 9360 2 3 7 Boot Process A9M9360 modules are preconfigured to boot with SPI channel B from a serial SPI EEPROM containing memory controller setup for SDRAM bank 0 and an initial boot program that moves the boot loading program from NAND flash to SDRAM bank 0 and starts it The serial SPI EEPROM has a size of 8KByte 3 8 Chip Selects Memory Map NS9360 CPU provides 8 chip selects
13. from different manufacturers There are two modules with Netsilicon CPUs in this family available A9M9750 and A9M9360 2 1 Common Features Below are the common features of this module which will be covered in further detail later in the document ARM core with MMU Size 60mm x 44mm with 240 pin connectors e SDRAM 16MB 256MB e NAND Flash 32MB 256MB e 4 Serial RS232 interfaces e Host and device USB interface USB2 0 compliant e 10 100Mbps Ethernet interface 2 interface 100KHz 400KHz e SPI interfaces JTAG interface Module 9 9360 2 2 2 Differences between 9 9750 9 9360 Modules Netsilicon CPU 59360 is low cost version of the NS9750 It has many features from the NS9750 including CPU core and most peripherals Differences 1 2 CPU clock is 100 177MHz NS9750 up to 200MHz Two SDRAM banks allowing up to 2 256MByte memory No PCI CardBus A9M9360 All pins used by PCI on 9 9750 unconnected on A9M9360 NS9360 has 73 GPIOs multiplexed with other functions NS9750 has 50 The same number of GPIOs are available on the A9M9360 connectors as the A9M9750 provides GPIOO 48 Additional GPIO66 72 are available too but have non GPIO function names 22 25 2 SCL 2 SDA WAIT and will be used normally in this function LCD function limited to 18bit LCD data LCD adapters with 18bit TFT LCD used for A9M9750 will run with A9M9360 too
14. LL bypassed not allowed e PLL_FS divider set to 2 e PLL_ND multiplier set to 24 177 2 21 154MHz or 14 103MHz Boot from SPI EEPROM spi bin 10 Module 9 9360 2 3 5 Configuration Pins Module Module configuration pins change either hardware configurations on the module HCONFO 3 or they are user specific and can be read in the GEN_ID register SCONFO 3 Signal name external Comment pin name DEBUG EN CPU Mode Select PU 10K HCONFO 0 Disconnects TRST and PWRGOOD for JTAG and Boundary scan debug mode 1 TRST PWRGOOD connected for normal mode default internal NAND flash HCONF 1 write protect 0 7 write protect active 1 no write protect OCD_EN JTAG Boundary Scan HCONF2 Select JTAG mode function selection DEBUG_EN has to 0 ARM Debug Mode be low too BISTEN set to high 1 Boundary Scan Mode BISTEN set to low default unused GPIO38 User defined software SCONFO read Bit 28 GEN ID configuration pin can be read in GEN ID register bit 28 default high 9 User defined software SCONF1 read Bit 29 GEN ID configuration pin can be read in GEN ID register bit 29 default high GPIO40 User defined software SCONF2 read Bit 30 GEN ID 11 Module 9 9360 2 configuration can be read in GEN ID register bit 30 default high GPIO41 User defined software SCONF3 Bit 31 GEN ID configuration pin can
15. Module 9 9360 2 Users Manual Module 9 9360 2 Copyright 2005 FS Forth Systeme GmbH Postfach 1103 79200 Breisach Germany Release of Document May 30 2005 Filename UM Module A9M9360 2 doc Author Karl Rudolf Program Version All rights reserved No part of this document may be copied or reproduced in any form or by any means without the prior written consent of FS Forth Systeme GmbH Module 9 9360 2 Table of Contents Ts Revision 5 2 General iicet Teide b e eee bes Prae 6 2 1 COMMON Feat res ceteri ee e assesses ed dg dud 6 2 2 Differences between A9M9750 and A9M9360 Modules 7 2 3 Existing Variants of A9M9360 1 8 2 4 Existing Variants of ASMSSOU0 2 gat studied ate MR uad 8 3 Detailed Description 4 mmn 9 3 1 Size 60 x 44 9 3 2 22 120 eoo teu e cete e Pee d REN ERE 9 2 9 7 NS9360 CPU pmo etn ctae n n tains onn od cda 9 3 4 Configuration Pins CPU 9 3 5 Configuration Pins Module rtr tee eben etate ede 11 3 6 Clock 13 Qu BOOEPIOCOSS xoi fateri
16. VLIO with a step down switching regulator the core voltage will rise later than the I O voltage 3 3V IN A FET switch controls the switching of the I O voltage 3 3V into the module Important Every base board has to switch its 3 3V supply according to the module Otherwise power sequencing on the module is influenced by backfeeding the module with 3 3V from the base board The signal PWREN is provided for this purpose 29 Module 9 9360 2 4 Bootloader Every module is delivered with a bootloader UBOOT pre installed in NAND Flash The bootloader is capable of booting the Operating System from NAND Flash via a serial port or via Ethernet Parameters can be passed to the kernel from the bootloader 5 Software 926 core in the NS9360 contains an MMU thus allowing Operating Systems such as Linux and Windows CE to be supported Board Support Packages for Windows CE net 4 2 and Linux using kernel 2 6 x are in development Other Operating Systems can be supported on request 5 1 Software Hints This chapter just lists some problems which occurred while bringing a NS9360 FORTH into life UARTs all four channels have their RESET bit set Reset bits SCON_MRES other wise system hangs at access to UART registers 12C Reset bit in SCON MRES Same effect as mentioned for UARTs System Memory Chip Select X Memory Mask register Bit 0 has to be 1 otherwise chip select is blocked Is undocumented chip
17. XDO Reserved Reserved MII TXDO GPIOG0 MII TXD1 Reserved Reserved TXD1 GPIOG1 MII TXD2 Reserved Reserved MII TXD2 GPIOG2 MII TXD3 Reserved Reserved MII TXD3 GPIO63 MI COL Reserved Reserved COL GPIOG4 MIL CRS Reserved Reserved CRS N T GPIO 6 A22 Reserved Reserved A22 GPIO67 A23 Reserved Reserved A23 GPIO68 A24 MCKE 0 IRQO dupe A24 GPIO69 A25 MCKE 1 lRQ1dupe A25 GPIO70 2 SCL SCL dupe GPIO71 A27 MCKE 3 IIC SDA SDA 21 Module 9 9360 2 Port Alternate Alternate Function Function Function 03 default 00 UART 00 misc at power up Alternate Function 01 Alternate Function 02 Module on DEV Board default usage ___ _ ___ due 02 GPIO72 TA STB ext WAIT 22 Module 9 9360 2 3 13 External Interrupts 4 external interrupts are multiplexed with other functions on the GPIO pins Every interrupt is routed to two or three different GPIOs to increase the chance of using them without giving up another vital function External 1 Pos other functions 15 Pos 274 Pos other functions 27 Interr dupe Pos EIRQO GPIO1 RXDB SPIBoot_DI GPIO13 DSRA PWM2 dupe SPIB_DI DMAO REQ used on module for dupe RTC interrupt EIRQ1 GPIO7 DCDB SPIBoot CEZ GPIO28 LCD D4
18. divided in 4 channels for dynamic RAMs and 4 static chip selects Every chip select has a 256MB range Below the whole memory map of the NS9360 chip Address Size Comments Range Mbyte OxOFFFFFFF Ox1FFFFFFF module P eme Ox2FFFFFFF PM Garret Ox3FFFFFFF d Ed R RR RN OxAFFFFFFF EXT_CS1 0x50000000 NAND Flash Program Memory Ox5FFFFFFF EXT CS2 ec EC cd 71 Ox6FFFFFFF EXT_CS3 Sed bli EI Ox7FFFFFFF e eee Ox8FFFFFFF VENE NE RN Ox9FFFFFFF GEM e OxAO3FFFFF Bridge 0 0400000 BBustoAHB 14 Module 9 9360 2 Address Size Comments Range Mbyte OxAOAFFFFF reserved 0xA0500000 OxAOBFFFFF Ethernet 0xA0600000 OxAOGFFFFF reserved Ethernet Communication Module 0xA0700000 1 Memory momor Corot LCD 0xA0800000 1 LCD Controller _ a UN 9 OxAO9FFFFF Module OxFFFFFFFF 3 9 NAND Flash A9M9360 has 32Mx8 64Mx8 or 128Mx8 NAND Flash onboard Optionally greater sizes can be populated depending on availability The NS9360 limits the address range of a single chip select to 256MByte but this is not relevant for NAND Flash as the interface to the NAND flash needs always 32 kByte here due to usage of A13 14 for address and command control The NAND flash is accessed with EXT 51 The chip can be write protected externally with the signal FWP
19. in the specification of the Development board Spec Devkit A9M9750 A9M9360 or 1 Erste Fu note 36
20. l PHY needs GPIOs providing SPI channel D 25 Module 9 9360 2 3 19 Baudrate Table Baud rate generators in the NS9360 have different clock sources selectable 1 X1_SYS_OSC M It is the frequency of the input crystal divided by M M depends on the multiplier settings PLL_ND of the PLL M 2 at PLL_ND gt 8 decimal 14 7456MHz with 29 4912MHz quartz unusable for PLL_ND lt 8 baud clock instable and or wrong frequency at CPU speeds lt 58 9824 2 Cannot be used with PLL bypassed 2 BCLK For 176 9472MHz CPU clock is BCLK AHBCLK 2 44 2368MHz Only internal source when PLL bypassed 3 External receive clock from GPIO6 14 22 26 pins 4 External transmit clock from GPIO7 15 23 27 pins Count values vs Baud Rate Clock Baud Rate X1 SYS 2 N BCLK N BCLK N BCLK 44 236800 2 38 707200MHZ 25 804800 2 14 745600 Error Error Error 2 Error 275 12287 _ 32255 21503 4607 2687 127 Module 9 9360 2 Baud Rate X1 SYS 2 N BCLK N BCLK N BCLK 44 236800 2 38 707200MHZ 25 804800 2 14 745600 Error Error Error 2 Error 91600 0 1843200 9 9360 module is using PLL so modules with 177MHz 155MHz and 103MHz will use the values from column 1 allowing baud rates from 75 921600Bd 3 20 PC Bus This bus with the signals SCL
21. nectors Two 120 pin connectors on the long side of the module allow accessing most signals of the NetSilicon NS9360 CPU An optional extension with another two 60 pin connectors is planned This will extend the length of the module from 60mm to approximately 95mm Pin compatible in power supply and main port functions to other ModARM9 modules 3 3 NS9360 CPU For details see 9360 HardwareReferenceManual pdf from NetSilicon The CPU is offered in three speed and temperature variants e 177MHz 0 70 C 155MHz 40 85 C 103MHz 0 70 C 3 4 Configuration Pins CPU Several pins allow configuration of the CPU before booting CPU pins have weak pull ups value range is 15 300K for a default configuration Most pins do not have configuration options some are connected for internal configuration on the module 32 of the 73 GPIO pins allow user specific configurations They are latched in the GEN_ID register address 0xA0900210 5 clock cycles after the rising edge of RESET Important configuration pins are protected i e not accessible externally until strapping information configured on module is latched For details see Spec 9 9360 2 pdf Module 9 9360 2 Normally the hardware module configuration needs never to be changed by the client wrong configuration can make the module unbootable Module configuration details see specification 9 9360 2 e little endian mode selected e PLL active P
22. other functions UART SPI USB Ethernet DMA parallel port IEEE1284 IIC port LCD port timers interrupt inputs some memory bus address and control pins Using a pin as GPIO means always to give up another functionality 0 48 GPIO66 72 are accessible on the connectors GPIO13 is used for RTC interrupt on module allows sharing with open drain ORing GPIO49 65 are used on the module and not external accessible All GPIOs are set to GPIO input function after RESET Usage in another function needs configuring the GPIO registers at start up Port Name Alternate Alternate Alternate Alternate Module on Function Function Function Function Function DEV Board 03 default 01 02 default usage at power up GPIOO TXDB SPI Boot DMAO Timer 1 TXDB DONE dupe SPI Boot DO M dupe or external SPIB DO GPIO1 RXDB SPI Boot DMAO EIRQO RXDB DI REQ Dupe SPI Boot DI SPIB DI or external SPIB DI GPIO2 RTSB 1 ACK RTSB DMA GPIO3 CTSB HEN s DMAO CTSBZ DMA REQ GPIO4 DTRB 1284 DMAO DTRB BUSY DONE Nive pt Soe 5 DSRB 1284 ERR DMAO ACK DSRB DMA GPIO6 RIB SPI Boot 1284 Timer 7 RIB CLK P_JAM dupe SPI Boot CL SPIB CLK K or external ext SPIB CLK RXCLK A 17 Module 9 9360 2 Port Alternate Alternate Alternate Alternate Module on Function Function Function Function Function DEV Board 03 default 00 UART 00 misc 01 02 default usage
23. r high to low edge of clock as other I2C devices do CPU fault can be fixed only by NetSilicon Workaround Use half clock speed i e 50KHz in slow mode and 200KHz in fast mode 7 3 SPI Boot System needs Hardware Workaround The SPI EEPROM boot engine has a fault that prevents sometimes a proper setup of the SDRAM controller A hardware workaround is necessary that watches via a spare SDRAM chip select the successful initialization of the SDRAM controller chip select toggling for refresh Otherwise 274 reset is necessary which will always result in a proper setup and the system will start This workaround is implemented in the 9 9360 2 module 35 Module 9 9360 2 8 8 1 Pinning Module The pinning for all currently planned and realised modules are defined in the file Arm9 Module Pinning Table XLS 8 2 Pinning Description Module A detailed pin description is available as Pin Description A9M9360 or doc 8 3 Pinning Module on A9MVali Validation Board This pinning is included in the specification of the validation board A9MVali X doc or pdf Important If possible avoid usage of A9M9360 modules on A9MVALI X boards due to missing power sequencing on this base board Module powerup and powerdown may be disturbed by backfeeding 3 3V signals from base board Prefered base board is 9 97500 1 8 4 Pinning Module on Development Board This pinning is included
24. select enable now documented SDRAM bank 1 can be used if initilization is running not from SDRAM bank 0 see chapter SDRAM 30 Module 9 9360 2 6 Mechanics The module size is defined to 60 x 44mm Two holes for M2 screws catercornered are provided to enable fixing of the module on the base board Two board to board connectors are used on the module Depending on the counterpart on the base board different distances between module and base board can be realized The minimum distance is 5mm Therefore the height of the parts mounted on the bottom side of the module should not exceed 2 5mm The height of the parts mounted at the top side should not exceed 4 1mm Board to Board Module Connector X1 X2 Base Board Connector X1 X2 Distance h No of Pins Qty Supplier Order No No Of Pins Supplier Order No 5mm 120 AMP 177984 5 Berg 61083 121000 6 mm 120 2 AMP 177983 5 120 AMP 179029 5 Berg 61082 121000 Berg 61083 122000 7 mm 120 AMP 179030 5 Berg 61083 123000 8mm 120 AMP 179031 5 Berg 61083 124000 31 Module 9 9360 2 Mechanical Drawing from TOP View 2 2 2x 32 Module 9 9360 2 Mechanical Drawing from Side View The size of h depends on the board to board connectors The size between the board to board connectors is measured from pad to pad 6 1
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