AT91SAM7S Microcontroller Series Schematic Check List
Contents
1. AT91SAM 7S Microcontroller Series Schematic Check List 1 Introduction This application note is a schematic review check list for systems embedding Atmel s AT91SAM7S series of ARM Thumb based microcontrollers It gives requirements concerning the different pin connections that must be consid ered before starting any new board design and describes the minimum hardware resources required to quickly develop an application with the AT91SAM7S Series It does not consider PCB layout constraints It also gives advice regarding low power design constraints to minimize power consumption This application note is not intended to be exhaustive Its objective is to cover as many configurations of use as possible The Check List table has a column reserved for reviewing designers to verify the line item has been checked AIMEL T AT91 ARM Thumb based Microcontrollers Application Note 6258D ATARM 18 Dec 07 AMEL 2 Associated Documentation Before going further into this application note it is strongly recommended to check the latest documents for the AT91SAM7S Series Microcontrollers on Atmel s Web site Table 2 1 gives the associated documentation needed to support full understanding of this appli cation note Table 2 1 Associated Documentation Information Document Title User Manual Electrical Mechanical Characteristi AE ancala Ka gi AT91SAM7S Series Product Datasheet Ordering Information Errat2. Web Site www atmel com www atmel com AT91SAM Literature Requests www atmel com literature for use as components in applications intended to support or sustain life POWERED ARMs 2007 Atmel Corporation All rights reserved Atmel logo and combinations thereof and others are registered trademarks SAM BA and others are trademarks of Atmel Corporation or its subsidiaries ARM the ARM Powered logo Thumb and ARM7TDMI are registered trademarks of ARM Limited Other terms and product names may be the trademarks of others Atmel Europe Le Krebs 8 Rue Jean Pierre Timbaud BP 309 78054 Saint Quentin en Yvelines Cedex France Tel 33 1 30 60 70 00 Fax 33 1 30 60 71 11 Technical Support AT91SAM Support Atmel techincal support Atmel Japan 9F Tonetsu Shinkawa Bldg 1 24 8 Shinkawa Chuo ku Tokyo 104 0033 Japan Tel 81 3 3523 3551 Fax 81 3 3523 7581 Sales Contacts www atmel com contacts 6258D ATARM 18 Dec 07
3. a Internal architecture of processor ARM Thumb instruction sets Embedded in circuit emulator Evaluation Kit User Guide AT91SAM7S EK Evaluation Board User Guide ARM7TDM Datasheet 2 Application Note memm 6258D ATARM 18 Dec 07 Application Note 3 Schematic Check List 3 3V Single Power Supply Strategy On chip Voltage Regulator Used To reduce power consumption voltage regulator can be put in standby mode DC DC Converter GND 4 7uF 100nF GND Voltage Regulator 2 2UF 100nF i VDDOUT H VDDCORE VDDPLL GND 3 3V Single Power Supply Schematic Example On chip Voltage regulator is used Power Supply on VDDIO 3 3V M Signal Name Recommended Pin Connection Description Powers on chip voltage regulator and ADC o Decoupling Filtering capacitors must be added to improve VDDIN Decoupling Filtering capacitors startup stability and reduce source voltage drop 100 nF and 4 7 pF Vvppin store Tstope Must be superior or equal to 6V ms Decoupling Filtering capacitors Output of the on chip 1 8V voltage regulator VDDOUT i ilteri i OU 100 nF and 2 2 pry Decoupling Filtering capacitors must be added to guarantee 1 8V stability Powers I O lines and USB transceivers 3 0V to 3 6V VDDIO or Dual voltage range supported 1 65 to 1 95V Decoupling capacitor 100 nF Note that supplying less than 3 0V to VDDIO prevents any use of the USB transceiv
4. and ADC NOT Used 100nF DC DC Converter GND 100nF r a VDDPLL DC DC Converter GND VDDCORE 2 ee Cy wen 3 3V and 1 8V Dual Power Supply Schematic BE On chip Voltage regulator is not used ADC is not used Power Supply on VDDIO 3 3V Mw Signal Name Recommended Pin Connection Description VDDIN Connected to GND VDDOUT Can be left unconnected Powers I O lines and USB transceivers 3 0V to 3 6V Dual voltage range supported or VDDIO 1 65 to 1 95V Decoupling Filtering capacitors must be added to improve Decoupling Filtering capacitors startup stability and reduce source voltage drop 100 nF and 4 7pF Note that supplying less than 3 0V to VDDIO prevents any use of the USB transceivers veer 3 0V to 3 6V y Rene i Decoupling capacitor 100 nF vppFLasH MUS a pau che as a VDDCORE 6258D ATARM 18 Dec 07 AMEL AIMEL Signal Name Recommended Pin Connection Description Powers device logic on chip RC and Flash 1 65 to 1 95V Decoupling Filtering capacitors must be added to improve VDDCORE Decoupling Filtering capacitors startup stability and reduce source voltage drop 100 nF and 2 2 pF 0 Vvppcore store Tstope Must be superior or equal to 6V ms 1 65 to 1 95V VDDPLL i 1 2 Powers the main oscillator and the PLL Decoupling capacitor 100 nF No separate ground pins are provided for the different GND Sound power supplies O
5. er filter e o PLL PLLRC Can be left unconnected if PLL not used h C2 Ci e GND R C1 and C2 must be placed as close as possible to the pins 10 Application Note memm 6258D ATARM 18 Dec 07 es caton Note My Signal Name Recommended Pin Connection Description ICE and JTAG TCK Pull up 100 kOhm No internal pull up resistor TMS Pull up 100 kOhm No internal pull up resistor TDI Pull up 100 kOhm No internal pull up resistor TDO Floating JTAGSEL In harsh environments It is strongly recommended to tie this pin to GND if not used or to add an external low value resistor such as 1 kOhm Must be tied to Vyppig to enter JTAG Boundary Scan Internal pull down resistor 15 kOhm Flash Memory ERASE In harsh environments It is strongly recommended to tie this pin to GND if not used or to add an external low value resistor such as 1 kOhm Must be tied to Vyppio to erase the General Purpose NVM bits GPNVMx the whole Flash content and the security bit SECURITY Internal pull down resistor 15 kOhm Reset Test NRST Can be left unconnected NRST is configured as an output at power up NRST is controlled by the Reset Controller RSTC An internal pull up resistor to Vyppio 10 kOhm is available for User Reset and External Reset control 6 TST In harsh environments It is str
6. ers AMEL s 6258D ATARM 18 Dec 07 AMEL Signal Name Recommended Pin Connection Description 3 0V to 3 6V VDDFLASH Powers Flash charge pump Decoupling capacitor 100 nF 1 65 to 1 95V VDDCORE Can be connected directly to VDDOUT pin Powers device and Flash logic on chip RC Decoupling capacitor 100 nF 1 65 to 1 95V VDDPLL Can be connected directly to VDDOUT pin Powers the main oscillator and the PLL Decoupling capacitor 100 nF No separate ground pins are provided for the different power supplies Only GND pins are provided and should be connected as shortly as possible to the system ground plane GND Ground Application Note m 6258D ATARM 18 Dec 07 Application Note 3 3V and 1 8V Dual Power Supply Strategy On chip Voltage Regulator NOT Used and ADC Used To reduce power consumption voltage regulator can be put in standby mode 100nF H VDDFLASH 100nF VDDIO DC DC Converter 7 GND i tT VDDIN 4 7UF T 100nF I GND 2 2uF GND 100nF r VDDPLL DC DC Converter GND VDDCORE 2 edad i L iak aot 3 3V and 1 8V Dual Power Supply Schematic Example On chip Voltage regulator is not used ADC is used Power Supply on VDDIO 3 3V T Signal Name Recommended Pin Connection Description 3 0V to 3 6V Powers ADC VDDIN Decoupling Filtering capacitors Decoupling Filtering capacitors must be added to improve 100 nF and 4 7
7. intellectual property right is granted by this document or in connection with the sale of Atmel products EXCEPT AS SET FORTH IN ATMEL S TERMS AND CONDI TIONS OF SALE LOCATED ON ATMEL S WEB SITE ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT INDIRECT CONSEQUENTIAL PUNITIVE SPECIAL OR INCIDEN TAL DAMAGES INCLUDING WITHOUT LIMITATION DAMAGES FOR LOSS OF PROFITS BUSINESS INTERRUPTION OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifica tions and product descriptions at any time without notice Atmel does not make any commitment to update the information contained herein Unless specifically pro vided otherwise Atmel products are not suitable for and shall not be used in automotive applications Atmel s products are not intended authorized or warranted International Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel 852 2721 9778 Fax 852 2722 1369 Product Contact
8. nly GND pins are provided and should be connected as shortly as possible to the system ground plane Application Note m 6258D ATARM 18 Dec 07 es caton Note i Signal Name Recommended Pin Connection Description Clock Oscillator and PLL Internal Equivalent Load Capacitance C CL 20 pF Crystal Load Capacitance to check Corystat AT91SAM7S XIN Crystals between 3 and 20 MHz XOUT ae Capacitors on XIN and XOUT crystal load capacitance dependant IK S Mhz Main Oscillator CerystaL 1 in ARRA Normal Mode 1 kOhm resistor on XOUT only required for e e crystals with frequencies lower than 8 MHz hs Crex CLexT Example for an 18 432MHz crystal with a load capacitance of Corystat 20 pF no external capacitors C gxr are required Copystar C1 Refer to the electrical specifications of the AT91SAM7S datasheet XIN XOUT ay 1 8V Square wave signal VDDPLL XIN external clock source Main Oscillator XOUT can be left unconnected SAET E A in f Duty Cycle 40 to 60 Bypass Mode AMEL o 6258D ATARM 18 Dec 07 AIMEL i Signal Name Recommended Pin Connection Description See the Excel spreadsheet ATMEL_PLL_LFT_Filter_CALCULATOR_AT91_xxx zip available in the software files on the Atmel Web site allowing calculation of the best R C1 C2 component values for the PLL Loop Back Filter PLLRC Second ord
9. ongly recommended to tie this pin to GND if not used or to add an external low value resistor such as 1 kOhm Must be tied to Vyppio to enter Fast Flash Programming FFPI mode or SAM BA Boot recovery mode Internal pull down resistor 15 kOhm 6258D ATARM 18 Dec 07 AMEL 11 AMEL Signal Name Recommended Pin Connection Description PIO All PIOs are pulled up inputs at reset and are 5V tolerant To reduce power consumption if not used the concerned PIO can be configured as an output driven at 0 with internal pull up disabled PAX Application Dependant ADC ADVREF is a pure analog input Decoupling capacitor s To reduce power consumption if ADC is not used connect ADVREF to GND ADVREF ADO to AD3 are digital pulled up inputs at reset AD4 to AD7 are pure analog inputs ADO to AD7 OV to Vapvrer To reduce power consumption if ADC is not used connect AD4 AD5 AD6 and AD7 to GND USB Device UDP To reduce power consumption USB Device Built in Transceivers can be disabled enabled by default No internal pull up pull down resistors Application Dependant Typically 1 5 kOhm resistor to Vyppjio To reduce power consumption if USB Device is not used connect DDP to Vyppio DDP No internal pull down resistor DDM Application Dependant a To reduce power consumption if USB Device is not used connect DDM to GND No
10. pF startup stability and reduce source voltage drop Decoupling Filtering capacitors Output of the on chip 1 8V voltage regulator VDDOUT 100 nF and 2 2 pF 2 Decoupling Filtering capacitors must be added to prevent H on chip voltage regulator oscillations Powers I O lines and USB transceivers 3 0V to 3 6V or Dual voltage range supported VDDI a 1 65 to 1 95V Decoupling capacitor 100 nF Note that supplying less than 3 0V to VDDIO prevents any use of the USB transceivers AMEL s 6258D ATARM 18 Dec 07 AMEL Signal Name Recommended Pin Connection Description aa 3 0V to 3 6V kn net l A Decoupling capacitor 100 nF 2 vppFLasH Must always be superior or equal to Vvppcore Powers device logic on chip RC and Flash 1 65 to 1 95V Decoupling Filtering capacitors must be added to improve VDDCORE Decoupling Filtering capacitors startup stability and reduce source voltage drop 100 nF and 2 2 pF Vvppcore store Tstope Must be superior or equal to 6V ms 1 65 to 1 95V VDDPLL P th i illat the PLL Decoupling capacitor 100 nF 0 Cele ane MAN RENO annie No separate ground pins are provided for the different power supplies GND Ground Only GND pins are provided and should be connected as shortly as possible to the system ground plane Application Note memm 6258D ATARM 18 Dec 07 Application Note 3 3V and 1 8V Dual Power Supply Strategy On chip Voltage Regulator
11. ram Hardware Constraints See the AT91SAM Boot Program section of the AT91SAM7S datasheet for more details on the boot program 4 1 SAM BA Boot The SAM BA Boot Assistant supports serial communication via the DBGU or the USB Device Port e DBGU Hardware Requirements 3 to 20 MHz crystal or 1 to 50 MHz external clock e USB Device Hardware Requirements 18 432 MHz crystal PA16 dedicated to USB DDP Pull up When this PIO is driven low by SAM BA Boot the pull up must be enabled 14 Application Note mmm 6258D ATARM 18 Dec 07 es A 1iCation Note Revision History 6258D ATARM 18 Dec 07 AMEL Change Request Doc Rev Comments Ref 6258A First issue 6258B disclaimer added to Introduction on page 1 3254 Section 3 Schematic Check List Precisions added to schematics of power supply 6258C strategies Note added for use in harsh environments Precisions added to ADC and descriptions PA16 use definition in Section 4 1 SAM BA Boot 3922 Clock Oscillator and PLL on page 9 schematic updated 6258D Updated Recommended Pin Connection for JTAGSEL ERASE and TST 5071 15 AIMEL T O Headquarters Atmel Corporation 2325 Orchard Parkway San Jose CA 95131 USA Tel 1 408 441 0311 Fax 1 408 487 2600 Disclaimer The information in this document is provided in connection with Atmel products No license express or implied by estoppel or otherwise to any
12. tes 12 1 These values are given only as a typical example 2 Decoupling capacitors must be connected as close as possible to the microcontroller and on each concerned pin 100nF VDDCORE 100nF B VDDCORE 100nF VDDCORE GND 3 It is recommended to establish accessibility to a JTAG connector for debug in any case 4 Ina well shielded environment subject to low magnetic and electric field interference the pin may be left unconnected In noisy environments a connection to ground is recommended 5 See Test Pin description in I O Lines Considerations section of the corresponding AT91SAM7S datasheet for more details on the different conditions to enter FFPI or SAM BA Boot recovery modes 6 Example of USB Device connection As there is no embedded pull up an external circuitry can be added to enable and disable the pull up To prevent over consumption when the host is disconnected an external pull down can be added to DDP and DDM Application Note memm 6258D ATARM 18 Dec 07 Application Note A termination serial resistor Rey must be connected to DDP and DDM A recommended resistor value is defined in the electrical specifications of the AT91SAM7S datasheet itori 27K PIO 5V Bus Monitoring 47K 3V3 PIO zz Pullup Control 10 Enable 11 Disable 1 5K Rext 2 1 a DDP E Oo R 3 TypeB 4 EXT Connector 330K 330K AMEL 13 6258D ATARM 18 Dec 07 T AMEL 4 AT91SAM Boot Prog
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