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1. THALES MTITI THALESM TA 00104e7e3ac 2662 VMPC62a 450 512 F32 PC62a 45 62601H m Ge Ge Ge Ge E m1 T I I Id CA DT 129 5e 12 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 4 Hardware Configuration To ensure proper operation of the VMPC6a board you may need to check its links Figure 4 1 illustrates the placement of the links on the board F e e SRAM Legend PPC750 PPC750 cid VZLA Link CPUO CPUI FR e o P1 AVIGNON Ce 07A LU Host Bridge ALMA_V64 VME PCI INTERFACE Pee EUSEB ERES Elbe 9 OO 33 9 Interrupt and I O Controller
2. USER FLASH ii ERA mo ji O 100BASE O Controller E E H 10 100BASE HE Transformer L d E IH e 10 100BASE T a 0 Transceiver 8 Figure 4 1 VMPC6a Link Positions Thales Computers 13 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Hardware Configuration 4 1 Manufacturing Self Test Link LK1 This link is only used for the manufacturing self tests Do not fit this link for normal operation CA DT 129 5e 14 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Hardware Configuration 4 2 System Flash EPROM Link LK2 This link enables or disables writes to the System Flash EPROM To copy a new VMPCBug firmware version follow the explanations given in the section Upgrading the VMPCBug version in the VMPCBug User s Manual To save the NVRAM contents into the first system flash EPROM use the ENV S command For further information about saving and restoring the NVRAM contents refer to section 10 2 4 ENV Command page 87 and the VMPCBug User s Manual Fitting Meaning IN Enables writes to the System Flash EPROM
3. Figure 5 1 Connector Positions and Numbering Thales Computers 17 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Connectors 5 1 1 PO Connector Pin Assignment Optional The PO connector is optional on VMPC6a boards The PCI signals from the PMC slot are connected to the PO connector 32 bit PCI subset in order to connect a Thales Computers dual PMC carrier card through its PO overlay backplane Connecting multiple SBC through PO is not supported by the VMPC6a PO Connector Pin Number l Row e Signal Row d Signal Row c Signal Row b Signal Row a Signal 1 N C N C N C 2 m N C N C N C E 3 Pon N C N C N C o 4 CLKOUT N C N C N C V I O 5 on REQ1 GNT1 REQ2 GNT2 6 REQ3 GNT3 N C N C C BE1 7 C BEO C BE3 C BE2 FRAME RST 8 DEVSEL IRDY TRDY PAR 9 Pon N C N C N C N C 10 on N C N C N C N C 11 on N C N C N C N C 12 STOP N C N C AD 01 AD 00 13 INTB INTA amp AD 03 AD 02 AD 05 14 AD 04 AD 07 AD 06 AD 09 AD 08 15 AD 11 AD 10 AD 13 AD 12 AD 15 16 AD 14 AD 17 AD 16 AD 19 AD 18 17 AD 21 AD 20 AD 23 AD 22 AD 25 18 AD 24 AD 27 AD 26 INTC INTD 19 AD 29 AD 28 AD 31 AD 30 N C PCI signals active when low For more information about PCI signal
4. 8 3 LEDs Eleven LEDs are mounted on the front panel Three of these can be software programmable LEDs Refer to the Programmer s Reference Guide for more details PCI MEZZANINE CARD RST KBD MS SERIAL SCSI ETHERNET EE N SN CO cy tl AS m m FLTI FLT2 CPUBUS Sue O eun VME SCSI JEPCI era STOP LED This yellow LED indicates that the board is in RESET phase or that one of the power supplies CPU core 3 3V 5V is out of range FAULT1 LED This red LED indicates a checkstop condition for CPUO It is connected to CKSTPOUT_ signal of the CPUO FAULT2 LED This red LED indicates a checkstop condition for CPUI It is connected to CKSTPOUT signal of the CPUI CPU BUS LED This green LED connected to both processor output signals DBB indicates an activity on the CPU bus from either of CPUs CPU1 LED This green LED indicates an activity on the CPUO bus or address bus parked to the CPUO without activity It is active when the CPUO bus has gained address bus mastership CPU2 LED This red LED indicates an activity on the CPU1 bus or address bus parked to the CPUI without activity It is active when the CPUI bus has gained address bus mastership VME LED This yellow LED indicates that the board is the VME bus master SCSI LED This yellow LED indicates an activity on the SCSI bus This LED can be programmed by software EPCI LED
5. Guaranteed 888 88 SOURCE www artisantg com Connectors Signal Description Mnemonic Description ACK SCSI bus Acknowledge ATN SCSI bus Attention BSY SCSI bus Busy C D SCSI bus Command Data phase DBO to DB15 SCSI bus data DBPO to DBP1 SCSI bus data parity 1 0 SCSI bus l O phase MSG SCSI bus Message phase N C This pin is not connected REQ SCSI bus Request RST SCSI bus Reset SEL SCSI bus Select SCSI bus terminator power Supplies power for external SCSI bus terminators Fused at 2 Amp TERMPWR GND Logical Ground Thales Computers 41 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Connectors 5 2 4 P6 ETHERNET 10BASE T 100BASE T Connector ETHERNET In standard 10BASE T or 100BASE T Ethernet interface is available on this 8 way RJ45 socket connector The pin assignment is as follows 1 Transmit 2 Transmit 3 Receive 4 GND 5 GND 6 Receive 7 GND 8 GND Shell Chassis Ground Pin 8 Pin 1 gt ETHERNET 1 Pin 8 Signal Description Description Receive 10BASE T 100BASE T receive data Transmit 10BASE T 100BASE T transmit data With the Ethernet routed to backplane manufacturing option 10 100BASE T Ethernet interface is only NOTE available on the P2 connector In th
6. 7013 No communication reproduction or use without prior written approval from Thales Computers Your comments on this manual will be welcome A sheet is appended for you to submit your remarks Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Table Of Contents Chapter 1 Introduction oicorinasan a m rh eee mers ern We vege ema Ye epi e 1 LL Opjectives voii A Ut We AR E IA A ITA aia Att 2 1 2 Audience a aia 2 MEE Corr 2 14 Structile a mU pes sus Dod A a Marec fes 2 1 5 Conventions 2g a ed ere E TE we e RR e MR ee dues eee Sees 3 L6 Related Documents uer lI a Era PR Deas ra S aes s RE E TEES 4 Chapter 2 General Information ooooooooococrcrcrcrrorororrorcrorcrcoroso 5 2l Introducti n ii ia A 5 22 RR 7 2 3 Tnputs Outputs 5e eo as m Rai di EE E AURI E EE RENTUR 8 2 4 Operating System Support cc ccc ccc ccc ee rere ee eee ee ee ee hh hh nnn tnn 9 Chapter 3 Unpacking and Identification 0 ccc cece ce cette cee cece eee nne 11 3l Unpackie iii AA A A 11 3 2 Inspection 2000 ieee ede 328 92949 9300093 Ue DRE Ee UR Ad sare o na d Ec aci se 11 3 3 Board Identification s scope carers e tI RA REEL EGG eevee s acegre EG RR RR ERR E 12 Chapter 4 Hardware Configuration o oooooooocoooororcrcorororrorororcrconoso 13 41 Manufacturing Self Test Link LK1 eeeeeeeeeeeeeee Hh hh nn nn 14 4 2 System Flash
7. A rtisan Artisan Technology Group is your source for quality Technology Group new and certified used pre owned equipment FAST SHIPPING AND SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT DELIVERY Experienced engineers and technicians on staff Sell your excess underutilized and idle used equipment TENS OF THOUSANDS OF at our full service in house repair center We also offer credit for buy backs and trade ins IN STOCK ITEMS www artisantg com WeBuyEquipment 7 EQUIPMENT DEMOS HUNDREDS OF InstraV ea REMOTE INSPECTION LOOKING FOR MORE INFORMATION MANUFACTURERS Remotely inspect equipment before purchasing with Visit us on the web at www artisantg com 7 for more our interactive website at www instraview com 7 information on price quotations drivers technical LEASING MONTHLY specifications manuals and documentation RENTALS ITAR CERTIFIED CEP BAD tia Contact us 888 88 SOURCE sales artisantg com www artisantg com G kontron Since March 6th 2008 Thales Computers has become Kontron Modular Computers S A This documentation was created with Thales graphics rules The Kontron Corporate Design will be implemented in the next version of this document Each occurence of Thales Computers shall be understood as Kontron Modular Computers S A For all questions related to this document please contact support kom sa kontron com or visit www kontron com G kontron OURCE www artisantg com www ko
8. Address lines that are used in conjunction with A01 A15 to PISO AES broadcast a standard or extended address Address Bus bits 24 to 31 Address lines that are used in conjunction with A01 A23 to noie broadcast an extended address AC Failure This signal indicates when the AC input to the power supply is no longer being AGEAIL provided or that the required AC input voltage levels are not being met Address Modifier bits 0 to 5 These signals are used to broadcast information such as AMOTO AMS the address size cycle type master identification or any combination of these Address Strobe This signal indicates when a valid address has been placed on the address bus Bus Busy This signal is driven low by the requester associated with the current bus master to indicate that its master is using the bus Bus Clear This signal is generated by an arbiter to indicate that there is a higher priority request for the bus than the one being processed This signal requests the current master to release the bus Bus Error This signal is generated by a slave or bus timer to tell the master that the data transfer was not completed Bus Grant 0 to 3 In These signals are generated by the arbiter to tell the board receiving it that if it is requesting the bus on that level then it has been granted use of the BGOIN to BG3IN bus Otherwise the board should pass the signal down the daisy chain The BGxIN BGxO
9. BUSMODE 2 to BUSMODE 4 Bus Mode Driven by the host to indicate the bus mode Always set to PCI mode on VMPC6a C BEO to C BE7 Command Byte Enables During the address phase these signals specify the type of cycle to carry out on the PCI bus During the data phase the signals are byte enables that specify the active bytes on the bus C BE4 to C BE7 are specifics to 64 bit bus extension CLK Clock All PCI bus signals except RST are synchronous to this 33 MHz clock DEVSEL Device Select Driven low by a PCI agent to signal that it has decoded its address as the target of the current access FRAME FRAME Driven low by the current master to signal the start and duration of an access GNT Grant Driven low by the arbiter to grant PCI bus ownership to a PCI agent IDSEL Initialization Device Select Device chip select during configuration cycles INTA and INTD Interrupt lines Level sensitive active low interrupt requests IRDY Initiator Ready Driven low by the initiator to signal its ability to complete the current data phase LOCK Driven low to indicate an atomic operation that may require multiple transactions to complete N C This pin is not connected PAR Parity Parity protection bit for ADO to AD31 and C BEO to C BE3 PAR64 Parity Upper DWORD Parity protection bit for AD32 to AD63 and C BE4 to C BE7 PERR Parity Error Dri
10. o ooooooororrrr e e 17 Figure 5 2 VMPC6a Front Panel o reidet irens eee i Ee ee I 36 Figure 9 1 VMPCoa Block Diagram cir rr A RA RARE Ra EE RARE EES Ns 64 Figure 9 2 PCI Interconnectivity generic use o ooooooooor I ee 66 Figure 9 3 PCI to VME Bridge Block Diagram o o oooooooocorr III 69 Figure 9 4 I O Controller Block Diagram o o oooooooorrrrr RII et 71 Figure 9 5 PCI 10 100 Mb s Ethernet LAN Controller Block Diagram 0 0 00 0c e eee eee 72 Figure 9 6 SCSI Controller Block Diagram 0 0 eee e eens 74 Fig re Al VME Dimensions ssr eser erintene iv epee tone eb Hey ened eT bee by RE YE Ces 93 Thales Computers V CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Table Of Contents List Of Tables Table 2 1 VMPC6a Order Code cue do 5 Table 6 1 PMC Site Information o 43 Table 8 1 External Interrupts INTEXTS 0 0 0 ccc Rh m 9 rh 58 Table 8 2 Devices connected to the 32 bit PCI DUS ooooooocoocr n 60 Table 8 3 Devices connected to the 64 bit PCI bus 0 2 I 61 Table 10 1 Usual Commands ne ERREUR ROC E US RES EN IR NER ROE EM IM REE Ree pe 81 CA DT 129 5e vi Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 1 Introduction The VMPC6a board with its associated peripherals and software is the latest g
11. 8 24 51 57 60 66 72 90 See also Connectors 100BASE T 72 73 10BASE T 72 73 LED 73 P2 connector 90 105 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com F Flammability 91 Front Panel 8 36 47 56 76 Serial Ports 8 Serial Software Option 39 G Geographical address pin 19 21 H Host Bridge See AVIGNON Chip Humidity 92 I VO Controller See COBRA Chip IDSEL See Device Number Inspection 11 Installation Board 47 PMC Boards 43 Interrupts 23 31 55 76 Acknowledge 23 External 55 57 Handling 22 69 89 INT 57 Interrupter 22 89 PCI 59 SMI 55 57 Sources 55 VMEbus 70 K Keyboard Mouse 1 5 7 8 24 58 66 90 See also Connectors Controller 77 L L2 Cache See Memory LEDs 50 90 100Base T Activity 50 73 10Base T Activity 50 73 CPU Activity 50 Master VME 50 PCI 64 Activity 50 Reset Phase 50 SCSI Activity 50 75 CA DT 129 5e Index Links 13 Manufacturing self tests 14 Memory System Flash 15 67 68 88 User Flash 16 68 Settings Default 16 M Manufacturing Option 90 Ethernet 7 8 PO 7 18 Master Operation 69 Memory 67 L2 Cache 5 7 65 82 87 90 Maps 51 53 54 NVRAMIRTC 7 68 71 87 88 90 SDRAM 5 7 65 67 70 82 86 90 Space 54 NVRAM 54 SDRAM 54 System Flash 54 User Flash 54 System Flash 5 7 67 84 90 User Flash
12. A quick visual inspection should reveal any obviously loose components Any defects detected should be reported to Thales Computers Thales Computers 11 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Unpacking and Identification 3 3 Board Identification Thales Computers VMPC6a boards are identified by labels fitted on the bottom side Labels fitted to the bottom side of the VMPC6a Commercial Reference label of the mother board Refer to Chapter 2 General Information section 2 1 Introduction Table 2 1 VMPC6a Order Code on page 5 for a complete description of this label Board Idenditification label of the mother board Variant label and Engineering Change Level E C Level label The Variant label is used with the Self Tests and manufacturing self tests In the above example the Variant label is 700104e7e3ac and the E C Level is 2662 Chronological serial number label Ethernet Number label This number is always EVEN and in hexadecimal O0 9 9 9 m D DE46007E THALESI IATA S N 1102411080775 E
13. ACK SCSI bus Acknowledge ATN SCSI bus Attention BSY SCSI bus Busy C D SCSI bus Command Data phase COBRA output signal 1 through 6 e g CO GPIO 1 COBRA GPIO 1 COBRA GPIO FLAG register 5C should not be modified this will render your board inoperative COBRA GPIOs are common with the counter divider CO GPIOBT For this reason you must read before the COBRA Reference Manual CI DT 405 and ensure that the counter divider are not used by your operating system check COBRA registers DATA Differential data pair DBO to DB15 SCSI bus data DBPO to DBP1 SCSI bus data parity 1 0 SCSI bus l O phase MSG SCSI bus Message phase N C This pin is not connected PMC IO x PMC IO signals from PMC Used to transmit I O signals from PMC board connected to the VMPC6a PWRFLT2 This signal is used to handle the power failure on the USB controller Receiver Ethernet receive data available with Ethernet routed to backplane manufacturing option REQ SCSI bus Request RST SCSI bus Reset SEL SCSI bus Select S1_TXD Channel 1 Transmit Data S1_RXD Channel 1 Receive Data S1 RTS Channel 1 Request To Send not available in Two simplified lines on front panel mode Page 1 of 2 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 25 CA DT 129 5e Connectors Mnemonic Description Channel 1 C
14. By using the ENV debugging monitor command the GEO ID environment variable can be read Refer to the section 10 2 4 ENV Command page 87 9 2 6 4 DMA Channels Two DMA channels are available to the user The priority between channels is programmable and blocks may be interlaced or not DMA completion can be signalled via an interrupt to the PCI bus 9 2 6 5 Interrupt Management The VME PCI bridge Interrupt Controller can handle different interrupt sources Q 7 VME interrupts IRQ7 IRQI Q 8 mail box interrupts they occur when a specific 8 bit register is addressed in write mode from the PCI or the VME Q ACFAIL and SYSFAIL on VMEbus Q internal exceptions end of DMA error acknowledges on PCI bus or VME bus VMEbus arbitration timeout All these interrupts can be masked and can drive either the INTA PCI bus interrupt which is the dedicated PCI interrupt pin or any of the three programmable interrupt pins INTI to INT3 For more information about these interrupts refer to the Programmer s Reference Guide CA DT 129 5e 70 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Functional Description 9 2 7 Utility I O and Auxiliary Function Bus The COBRA I O Controller is an ASIC developed by Thales Computers The COBRA chip provides a number of capabilities including an interrupt controller compliant with the CHRP standard and a bridge from the
15. C FORTRAN ADA Wind River VxWorks BSP and associated development environments Other OSs available through Third Parties due to PReP compliance The VMPC6a supports several environment condition severity from the standard S class build up 0 to 55 degrees air cooled to the Ruggedized RC build up 40 to 55 degrees conduction cooled Typical applications for such a highly attractive product in terms of performance price and flexible I O are military communications image and signal processing medical industrial process control C3I scientific research and many others Thales Computers 1 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Introduction 1 1 Objectives This guide provides general information hardware preparation and installation instructions operating instructions and a functional description of the VMPC6a board The onboard programming onboard firmware and other firmware e g drivers and BSPs are described in detail in separate guides see section 1 6 Related Documents 1 2 Audience This guide is written to cover as far as possible the range of people who will handle or use the VMPC6a from unpackers inspectors through system managers and installation technicians to hardware and software engineers Most chapters assume a certain amount of knowledge on the subjects of single board computer architecture interfac
16. OUT Disables writes to the System Flash EPROM Default configuration Thales Computers 15 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Hardware Configuration 4 3 User Flash EPROM Link LK3 This link enables or disables writes to the User Flash EPROM To read write or erase the User Flash contents follow the explanations given in the section VMPC4b VMPC5 and VMPC6 User Flash EPROM in the VMPCBug User s Manual Fitting Meaning IN Enables writes to the User Flash EPROM Disables writes to the User Flash EPROM ou Default configuration 4 4 Table Of Default Link Settings Link Setting Action LK1 OUT Manufacturing self tests disabled LK2 OUT Writes to the System Flash EPROM disabled LK3 OUT Writes to the User Flash EPROM disabled CA DT 129 5e 16 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 5 Connectors This chapter gives the pin assignment and signal descriptions for the VMPC6a connectors The first section describes the pin assignments for the onboard connectors PO P1 P2 J11 J14 P7 P8 The second section gives the pin assignments and a description of the front panel connectors P3 to P6 5 1 Onboard Connectors
17. Use VMPC6a RA Ruggedized Air Cooled or VMPC6a RC Ruggedized Conduction Cooled models with their dedicated documentations A 6 2 Storage Environment The VMPC6a may be stored or transported without damage within the following limits Temperature range Relative humidity Altitude Random Vibration Acceleration 40 to 85 C Up to 9096 without condensation from 1640 to 33000 feet 500 to 10000 meters approximatively Hz 10 15 25 40 100 1000 2000 g Hz 0 04 0 15 0 15 0 04 0 005 0 005 0 001 2g during 5mn 6 directions For storage environment exceeding the above specification ruggedized versions of VMPC6a board are NOTE available Use VMPC6a RA Ruggedized Air Cooled or VMPC6a RC Ruggedized Conduction Cooled models with their dedicated documentations CA DT 129 5e 92 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Specifications A 7 Mechanical Construction The VMPC6a is build on a multi layer double Eurocard and conforms to the dimensions specified in the ANSI VITA VME64 1 1994 The dimensions shown below are in millimetres with inches in parentheses for general guidance only 233 35 261 85 10 309 9 187 mu 160 6 29 lt gt ic 20 02 0 79 2 54 0 1 Figure A 1 VME Dimensions e Length 233 35 mm e Depth 160 mm without connectors e Height 1 VME slot
18. VME PCI INTERFACE 10 100BASE E Controller NOTE Onboard SDRAM and the second System Flash are on the bottom side Figure 2 1 Top View of the VMPC6a CA DT 129 5e Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com General Information 2 2 Features e PowerPC one 750L processor from 450 MHz and upwards for VMPC6a two 750L processors from 450 MHz and upwards for VMPC6a Dual Extensive operating system support including AIX LynxOS and VxWorks Wide range of shrink wrapped application software available 1 MByte of 2 way set associative secondary cache per processor One 64 bit 66 33 MHz PCI PMC expansion slot onboard with optional carrier ICPMC 6 providing a maximum of three PCI PMC slots Up to 512 MBytes of SDRAM with ECC onboard 1 5 MBytes of System Flash EPROM e 8Kx8 of user NVRAM and Real Time Clock TOD calendar with a replaceable battery crystal package e Standard features include Onboard PCI Ethernet LAN controller with 10 100BASE T Ethernet on front panel Up to 32 MBytes of User Flash EPROM Ultra or Wide Ultra SCSI I O processor Two RS232 serial I O channels up to 115 2 Kbaud Keyboard mouse interface VME64 interface with PCI to VME64 bridge using ALMA V64 PCI to VME interface chip Local I Os and PMC I Os routed to P2 connector e VME64 inte
19. 32 bit PCI 2 1 interface to a reduced slave only ISA Bus Facilities provided on the Reduced ISA include Q interrupt handling for 32 external interrupt sources Q interrupt outputs for up to four processors O general purpose I O Q timer counter facilities Q fast internal FIFO or SRAM for real time applications Q ISA master interface PCI Bus PCI Bus Interface General GPIOs Purpose Internal Slave only IOs Registers External ITs CPU ITs 4 Interrupt Message Passing FIFOs Reduced ISA i Interface Timers nd Master Only Controller Reduced ISA Bus Figure 9 4 I O Controller Block Diagram The COBRA I O Controller handles via the RISA bus the following peripherals Q serial lines Q NVRAM RTC Q User Flash Thales Computers 71 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Functional Description 9 2 8 PCI 10 100 Mb s Ethernet LAN Controller The DEC DC21143 PCI Ethernet LAN controller supports ANSI 802 3 100BASE T and 10BASE T standards It supports direct memory access DMA and has a direct interface to the 32 bit PCI bus The Ethernet LAN controller contains large independent receive and transmit FIFOs Also it supports autodetection between IOBASE T and MII SYM 100BASE T ports For detailed programming information refer to the Programmer
20. 41 3 3V 42 SERR 43 C BE 1 44 Ground 0V 45 AD 14 46 AD 13 47 Ground 0V 48 AD 10 49 AD 08 50 3 3V 51 AD 07 52 N C 53 3 3V 54 N C 55 N C 56 Ground 0V 57 N C 58 N C 59 Ground 0V 60 N C 61 ACK64 62 3 3V 63 Ground 0V 64 N C PCI signals active when low PMC JTAG is not used on the motherboard and TDI TMS TCK inputs have pull ups CA DT 129 5e 28 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Connectors 5 1 7 3 J13 PMC Connector Pin Assignment 1 N C 2 Ground 0V 3 Ground 0V 4 C BE 7 5 C BE 6 6 C BE 5 7 C BE 4 8 Ground 0V 9 V 1 O 10 PAR64 11 AD 63 12 AD 62 13 AD 61 14 Ground 0V 15 Ground 0V 16 AD 60 17 AD 59 18 AD 58 19 AD 57 20 Ground 0V 21 V 1 O 22 AD 56 23 AD 55 24 AD 54 25 AD 53 26 Ground 0V 27 Ground 0V 28 AD 52 29 AD 51 30 AD 50 31 AD 49 32 Ground 0V 33 Ground 0V 34 AD 48 35 AD 47 36 AD 46 37 AD 45 38 Ground 0V 39 V I O 40 AD 44 41 AD 43 42 AD 42 43 AD 41 44 Ground 0V 45 Ground 0V 46 AD 40 47 AD 39 48 AD 38 49 AD 37 50 Ground 0V 51 Ground 0V 52 AD 36 53 AD 35 54 AD 34 55 AD 33 56 Ground 0V 57 V 1 0 58 AD 32 59 N C 60 N C 61 N C 62 Ground 0V 63 Ground 0V 64 N C PCI signals active when low Thales Computers 29 CA DT 129 5e Artisan Technology Group Quality Instr
21. 5 7 68 71 90 N NVRAM RTC See Memory O Operating Systems 1 9 90 P Parity 25 31 41 48 55 96 PCI 1 3 5 7 31 51 66 32 Bit 65 66 72 90 Configuration 60 VIO 44 64 Bit 31 32 65 66 90 Configuration 61 Bus 31 65 66 67 83 Interrupt 70 Carrier Card 67 90 Ethernet Controller 72 Host Bridge 65 Interrupt 70 Mapping 83 Master 54 SCSI Controller 74 Slot 67 83 106 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com PCI to VME Interface See ALMA_V64 Chip PMC 61 66 Slot 67 90 PMC Sites PCI 32 Keying Pin 44 VIO 44 Power 23 26 32 41 47 91 95 96 Absence 95 Leads 95 Requirements 91 Supply 22 95 Up 48 49 54 55 56 96 PowerPC 1 5 7 65 PReP 5 Processor 65 R Registers 56 Related Documents 4 Reset Spread 82 86 Reset Switch 49 56 Resets 25 32 35 41 96 Hard 35 49 55 56 Power on 56 Remote 56 Soft 55 56 SYSRESET 19 23 55 56 RISAbus 71 76 RTC See Memory S SCSI 1 5 7 8 24 25 41 48 51 57 60 66 74 90 95 See also Connectors LED 75 Register 75 Terminator 26 41 74 82 95 Self Tests 67 68 Serial Ports 1 5 7 8 24 38 48 71 76 82 84 90 See also Connectors Controller 76 Shock 92 Slave Operation 22 69 89 Thales Computers Index System Controller 69 95 System Flash See Links Memory T Te
22. A RT ETIN SATA FEET EP dese Er E UE 50 8 4 Memory Maps iu eere vedi ov eae a Re VIRUS E iR oe Viera au e 51 8 41 Example of Memory Map Seen by the Processor 53 8 4 2 Example of PCI Memory Space Seen by the 32 bit PCI Master 0 0 00 cee eee eee 53 8 4 3 Example of PCI Memory Space Seen by the 64 bit PCI Master eese 54 8 4 4 Example of PCI I O Space Seen by the 32 bit PCI Master 00 0 cece eee eee eee 54 8 4 5 Example of PCI I O Space Seen by the 64 bit PCI Master oo ooococcoccoccocccc ee 54 846 Memory Space c use pri e pex RU ER RR CREE RARE SEER RGR KE eS 54 8 5 Interrupts and Error Reporting 0 ccc cece ccc ccc ce ee e e e hh n ht nnn 55 8 5 1 TYPOS OF Reset pei pete oe pedes Echarpe Rege copa be oe poe E eg turc Reden id 56 6 9 LI Hard Reset ik doen EIEE RA Rn e EE RA SE BA eg 56 EDIL Soft Reset a oo UR eem ER e tere odia e dpi e d E ass 56 8 5 2 Machine Check Exception 4 isses e exa hae kg ip E eR EORR a aaa aa 57 8 5 3 External Interrupt INT ed 57 8 54 System Management Interrupt SMI 0 0 0 erreen I e 57 8 5 5 External Device Interrupts INTEXT seseseeeeee m mn 57 85 6 PCliInt rt ptS oec Re der RENE LIE RN E RE EE C Ped 59 8 6 3 bit PCI Configuration 4 csse hr ehh REP xe i ER ER EP Se EE RE eR 60 8 7 64 bit PCI Configuration 2 2 0 0 ccc ccc cee ehe hh hh hh hh hn nnn 61 CA DT 129 5e ii Thales Computers Artisan Technology Group Qu
23. Bus Mode 64 Bits mode PCI Bus Devices Bus 0 Slot 3 CETIA COBRA I O Controller Rev 0 Bus 0 Slot 4 DEC DC21143 Fast Ethernet Ctrlr Rev 4 1 Bus 0 Slot 5 SYM 53C875 Ultra Wide SCSI Rev 4 CA DT 129 5e 82 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com VMPCBug Debugging Monitor Bus 0 Slot 6 IBM PCI VME Bridge Rev 2 1 Bus 0 Slot 7 CMD USB0673 USB Ctrl Rev 5 Bus Seri 1 No PCI Devices Detected al Port used Channel 1 Two simplified lines on front panel No On Board SCSI Terminators ON VME System Controller ON VME System Reset Spread VME Board Id O VME Slave A16 Base Offset 0x0 VME Slave A16 Base Address is 0x0 VME to DRAM A32 Base Offset 0x0 VME to DRAM A32 Gap 0x8000000 VME to DRAM A32 Base Address is 0x0 VME autoslotid 0 auto 1 manual 0x0 VME slave windows 0 A32 A16 1 A16 2 A32 3 none L2 Cache Option Copy Back Concerning the PCI Bus Devices information Bus 0 refers to the local PCI bus Bus 1 refers to the extended PCI bus slot x for each device detected on the PCI bus x is the devsel value i e the device number of this particular device on this bus CONF D gt Display the PCI device mapping The following example shows the information displayed with the CONF D command COMMAND gt CONF D Device BAR CPU Addr PCI Addr Size IO MEM 3 0 0x80010000 0x00010000 0x00001000 1
24. ENV gt Display all VMPC6a PReP environment variables The following example shows the information displayed with the ENV command COMMAND gt ENV Environment Variables ETHER INTERFACE 0 SCREEN DEF 3 Description and possible values of environment variables are given in Appendix B of the VMPCBug NOTE User s Manual Thales Computers 87 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com VMPCBug Debugging Monitor ENV Variable Name gt lt Value gt gt Update the selected environment variable The following example shows how to update the ETHER INTERFACE variable COMMAND ENV ETHER INTERFACE 1 The ETHER INTERFACE variable is set to 1 ENV Variable Name gt D gt Delete the selected environment variable The following example shows how to delete the ETHER INTERFACE variable COMMAND ENV ETHER INTERFACE D The ETHER INTERFACE variable is deleted ENV S gt Save NVRAM into the first system flash The NVRAM saving feature is used to save the NVRAM contents into the first socketed system flash This can be useful for example when the NVRAM battery is removed from the VMPC6a This feature requires writes into the system flash to be enabled so the LK2 link must be set see section 4 2 page 15 when the command is entered To save the NVRAM contents type the command COMMAND gt ENV S At this time creation modification of an enviro
25. Northampton NN4 7EX United Kingdom Tel 44 0 1604 700 221 Fax 44 0 1604 700 112 www thalescomputers com With ISO 9001 certification O Thales Computers guarantees YW Yee Tota Customer Satisfaction AFAQ N 1995 3356b THALES COMPUTERS Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com A rtisan Artisan Technology Group is your source for quality Technology Group new and certified used pre owned equipment FAST SHIPPING AND SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT DELIVERY Experienced engineers and technicians on staff Sell your excess underutilized and idle used equipment TENS OF THOUSANDS OF at our full service in house repair center We also offer credit for buy backs and trade ins IN STOCK ITEMS www artisantg com WeBuyEquipment 7 EQUIPMENT DEMOS HUNDREDS OF InstraV ea REMOTE INSPECTION LOOKING FOR MORE INFORMATION MANUFACTURERS Remotely inspect equipment before purchasing with Visit us on the web at www artisantg com 7 for more our interactive website at www instraview com 7 information on price quotations drivers technical LEASING MONTHLY specifications manuals and documentation RENTALS ITAR CERTIFIED CEP BAD tia Contact us 888 88 SOURCE sales artisantg com www artisantg com
26. O voltage level is 5V With the PMC VIO Key 3 3V option it is 3 3V Check your VMPC6a designation and look at on the board the voltage keying pin position near the PMC connectors Default 5V V O Voltage Level Option 3 3V Connected to the INTEXT 6 input of the COBRA DS Interrupt Controller Connected to the INTEXT 7 input of the COBRA INTB Interrupt Controller 64 bit PCI Interrupts Connected to the INTEXT 8 input of the COBRA INTC Interrupt Controller Connected to the INTEXT 9 input of the COBRA INTD Interrupt Controller Bus Number 2 Indicates which PCI bus is being configured Device Number or IDSEL 1 Decoded in the AVIGNON CPC710 used to select the PMC to be configured on the 64 bit PCI bus The AVIGNON CPC710 provides on the AD 11 line of the 64 bit PCI Address Data bus the IDSEL of the PMC to be configured on the 64 bit PCI bus ADIx line of the 64 bit PCI Address Data Bus Table 6 1 PMC Site Information For more information see also section 8 5 6 page 59 for the description of the PCI interrupts for the PMC slot and section 8 7 page 61 for the PCI configuration physical connection for the PCI device Thales Computers 43 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com PMC Site 6 2 Voltage Keying Pins The VMPC6a and the PMC PCI bus have to operate on the same signaling level In order to prevent
27. PCI I O space A0000000 BFFFFFFF 512MB Reserved Reserved C0000000 D8000000 D7FFFFFF DFFFFFFF 384MB 128MB 00000000 to 17FFFFFF 18000000 to 1FFFFFFF 32 bit PCI Memory space User Flash BAR 32 bit PCI E0000000 FEFFFFFF 512MB 16MB Reserved Reserved FF000000 FFDFFFFF 15 MB No PCI cycle AVIGNON CPC710 access space FFE00000 FFEFFFFF 1MB No PCI cycle Flash boot EPROM 212 FFF00000 FFF7FFFF 512KB No PCI cycle Flash boot EPROM 1 1 1 This Flash boot EPROM is situated on the top side of the board and contains the VMPCBug and self tests 2 This Flash boot EPROM is situated on the bottom side of the board and contains the user programs such as VxWorks Processor Address Range PCI Address Range Cycle Type FF400000 FFAFFFFF 64 bit PCI cycle 64 bit eo register space FF500000 FF5FFFFF 32 bit PCI cycle 32 bit PCI register space 8 4 2 Example of PCI Memory Space Seen by the 32 bit PCI Master PCI Memory Address Range Local Memory Cycle Cycle Type 00000000 1FFFFFFF No local memory cycle 32 bit ens memory space 80000000 FFFFFFFF Thales Computers Artisan Technology Group Quality Instrumentation 00000000 to 7FFFFFFF 53 System memory space CA DT 129 5e Guaranteed 888 88 SOURCE www artisantg com Operating Instructions 8 4 3 Example of PCI Memory Space
28. RII 72 9 2 0 SCSI Controller 4 ssp hh ake sland a di ibas e UE 74 9 2 10 Serial VO Controller 0 e ME 76 9 2 11 Keyboard and Mouse Controller o oooooococcoororocrr e TI 9 3 Temperature Control 2 322 92499 ste 9 9 ev blerexge niv udenPrrrelEN PEG ERE 77 Chapter 10 VMPCBug Debugging Monitor 0 cece cece cere eee reece eee como 79 10 1 Using The VMPCBug Debugger cece ccc cece eee cece hh eee hr tmn 79 10 2 Debugger Commands cc ccc cece cece cere ee e e eee hh htt hr rns 79 10 2 1 VPD Command oi ci oie 9 e e I Ree ad 82 10 2 2 CONE Command asco mr e A FALE ERU RET Nur RUE aaa eB Sete a 82 10 2 35 DEV Command oy Ree OPER ORE P ENE ea ye e 87 10 2 4 ENV Command leeeeeeeeeee ehh hm nen emer ern 87 Appendix A Specifications 5 o err retep ER Rer RR E ICE P eR RR SR ew TUE 89 A X VMEbus Compliance 211 3 toes t en a ARA TCRER ace ps awe Rr 89 AA LocalR so rces 91 00 29 92 A apa UR ege AAA RM E S 90 A 3 Power Requirements ccc cece ce cece eee ee ee eh eee ee ht hr rr rn 91 A 4 EMC Regulatory Compliance and Reliability cc cece cece cece cece rere eee eees 91 A 5 Flammability Rating 0 cc ccc cc ccc ete rere ee eee hh hh hr seen 91 A 6 Environmental Specifications 0 cece ccc cc cece rere eee eee eect hh hh rn 92 AGT Operating Environment ep p hacks KEK MEN ERE SOG OS REE Me ERR OS EG Be EE EE 92 A 6 2 Stora
29. Seen by the 64 bit PCI Master PCI Memory Address Range Local Memory Cycle Cycle Type 00000000 1FFFFFFF No local memory cycle 64 bit Po lm monegaca memory space 80000000 FFFFFFFF 00000000 to 7FFFFFFF System memory space 8 4 4 Example of PCI I O Space Seen by the 32 bit PCI Master PCI I O Address Range Local Memory Cycle Cycle Type 00000000 0000FFFF 64KB No local memory cycle Reduced emissum 7 space 00010000 1FFFFFFF 512KB 64KB No local memory cycle 32 bit PCI I O space 8 4 5 Example of PCI I O Space Seen by the 64 bit PCI Master PCI I O Address Range Local Memory Cycle Cycle Type 00000000 OFFFFFFF 256KB No local memory cycle 64 bit exbiPCl Ospace I O space 8 4 6 Memory Space SDRAM The SDRAM is accessed directly by CPU the firmware sets up AVIGNON CPC710 memory controller after power up System Flash The System Flash is accessed directly by the CPU NVRAM and User Flash These memory spaces are mapped through COBRA I O and interrupt controller Refer to the Programmer s Reference Guide for more details about BAR programming in the COBRA controller CA DT 129 5e 54 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Operating Instructions 8 5 Interrupts and Error Reporting The various external interrupt sources to each processor CPUO and CPU1 on a VMPC6a Dual board and their relativ
30. This yellow LED connected to the 64 bit PCI bus FRAME signal PMC PCI indicates an activity on the PCI bus ETH LED The green LED indicates that the Ethernet interface is working The red LED is either OFF in IOBASE T mode or ON in 100BASE T mode These LEDs can be programmed by software CA DT 129 5e 50 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Operating Instructions 8 4 Memory Maps The VMPC6a supports both contiguous and non contiguous CHRP compliant memory maps The following descriptions relate to the contiguous map unless otherwise stated No fixed addresses are given for PCI connected resources SCSI Ethernet VME bridge and PMC slots since these addresses are configured by the boot process All these address ranges can be modified by the user the firmware and or by the standard software AIX LynxOS VxWorks The VMPC6a mapping is entirely dynamic The memory map PCI Memory space and PCI I O space seen under the VMPCBug after the boot reset are detailed in the figure on the next page They are accessed by the AVIGNON CPC710 Registers refer to the Programmer s Reference Guide or the CPC710 User s Manual for more details about the memory map Examples of memory maps are given in the sections 8 4 1 8 4 2 8 4 3 8 4 4 and 8 4 5 The mapping of the Thales Computers VMPC6a board is ENTIRELY RECONFIGURABLE IN THE NOTE FIR
31. VMPC6a board Each channel is handled by a TL16C550C component which is controlled by COBRA through the RISA bus Both serial channels contain receiver and transmitter FIFOs software compatible with the INS8250N B PC16550A and PC16450 These FIFOs store up to 16 bytes including three additional bits of error status per byte for the receiver FIFO Each interface supports the modem control functions CTS RTS DSR DTR RI and DCD as well as the TXD and RXD transmit receive data signals Baud rates are programmable from 50 bauds to 115 2 Kbauds including MIDI data rate Refer to the Programmer s Reference Guide and to the TL16C550C data sheet for further information Each serial controller can generate an interrupt handled by COBRA Refer to the Programmer s Reference Guide the COBRA Interrupts and I O Controller Reference Manual and to the TL16C550C data sheet for further information On the SERIAL front panel connector either full modem serial port 1 or both simplified serial ports are available This management is made either through the debugging monitor see section 10 2 2 CONF Command page 82 or by programming the COBRA GPIO 29 refer to the Programmer s Reference Guide When Two simplified lines on front panel field is set to NO full modem serial port 1 is available on the front panel connector and both serial ports are available on the P2 connector When Two simplified lines on front panel
32. Vital Product Data is factory configured before shipment and must not be modified The following example shows the information displayed with the VPD command COMMAND gt VPD Machine Type amp Model Header VMPC6a Part Number 0A30A040 Engineering Change Number 001000 Processor ID E 000035 Field Replacement Unit Number E 0A30A040 Manufacturing Location 069708 10 2 2 CONF Command With this command you can display or modify the configuration of your VMPC6a board CONF command may be executed with options Depending on the option you can display the PCI device mapping the checksum of the first System Flash EPROM VMPCBug or the second Slot Flash EPROM or modify some parameters as VME addresses to reach the PCI VME bridge internal registers VMPC6a SDRAM Serial Port Used onboard SCSI Terminators VME System Reset Spread VME Board ID AutoslotID VME slave windows L2 Cache Mode etc Examples of information given with each option are explained below CONF gt Display the VMPC6a board configuration The following example shows the information displayed with the CONF command COMMAND CONF VMPC6a Firmware VMPCBug 2 5 00139 CPU PPC750 450 MHz Rev 3 0 Bus Frequency 100 MHz Host Bridge AVIGNON 1 0 Memory Size 128 Mbytes DRAM Type SDRAM without ECC checking disabled NVRAM Type M48T18 L2 cache size 1024 Kbytes 8 Mbytes of User Flash detected Extended PCI
33. association of VMPC 6a slots and PMC with incompatible signaling voltages a voltage keying is required Check the VMPC6a and the PMC PCI bus use the same signaling bus level By default the VMPC6a 64 bit PCI bus operates on the 5V signaling level which is connected to the V I O pins of the PMC connectors and provides a 5V keying pin near the PMC connectors refer to Section 6 3 for the key position Your PMC PCI bus has to operate on the 5V signaling level and provide a 5V keying hole On the VMPC6a with the PMC slot VIO Key 3 3V manufacturing option the 64 bit PCI bus operates on the 3 3V signaling level which is connected to the V I O pins of the PMC connectors and provides a 3 3V keying pin near the PMC connectors refer to Section 6 3 for the key position Your PMC PCI bus has to operate on the 3 3V signaling level and provide a 3 3V keying hole Before installing your PMC on the VMPC6a check the VMPC6a voltage keying pin is compatible with the PMC signaling voltages and its keying hole Do not remove the keying pins on the VMPC6a They are agree with the V I O supplied by the board Do not insert PMCs which do not provide the associated keying hole If both voltages can be supported by your PMC then both holes shall be provided CA DT 129 5e 44 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com PMC Site 6 3 PMC Installation Please
34. compatible o Weight 425 gr approximatively Thales Computers 93 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Specifications CA DT 129 5e 94 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix B Troubleshooting This chapter gives some suggestions for what to do when your VMPC6a doesn t work 1 Use a step by step method for looking at the problem 2 Try to diagnose the problem type i e hardware or software 3 Ifall else fails phone fax or e mail your nearest Thales Computers technical support group for assistance B 1 Step 1 No Power Check that your enclosure s mains power lead is plugged into the mains outlet and into the chassis Check that you have switched on at the mains and at the system Check that you are receiving power from the mains outlet test this with a lamp for example Ensure that no fuses have blown If the system refuses to start up this suggests a problem with the power supply It is essential that only qualified personnel deal with the problem from now on B 2 Step 2 Power On Unexpected Behaviour Ensure that the board is firmly seated and secured in the rack and that all male female connectors mate together correctly Check the links on the board and the system backplane If you are unsure of which link configuration to use use the
35. data is stored in memory Big endian data is stored with the most significant byte at the lowest address 68XXX style See also Little endian BLT BLock Transfer on the VMEbus Byte An 8 bit data structure Cache A small fast access memory between the processor and the larger slower main memory Used to store the most recently used instructions data to improve overall memory access time CHRP Common Hardware Reference Platform Chassis See enclosure Chassis Ground A HE RE e OE ER MERE OE Ret ee ere E een Most applications require the chassis to be connected to earth normally via a main cable or separate earthing strap Thales Computers 99 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Glossary CPCIGx One of the Thales Computers Graphics mezzanine module CPMC GIX 8 uta iria aia Ara dara One of the Thales Computers Graphics mezzanine module CPU uu Central Processing Unit CR CSR Configuration ROM Control and Status Register on data and address lines CTS usus Clear To Send A serial signal See RTS D64 Sending and receiving data 64 bits at a time over DOO to D31 and A01 to A32 LWORD on the VMEbus D32 ee Sending and receiving data 32 bits at a time over DOO to D31 on the VMEbus D16 Sending and receiving data 16 bits at a time over DOO to D15 on the VMEbus D08 EO Sending and receivi
36. default configuration initially See section 4 4 Table of Default Link Settings page 16 Check that the VME rack has terminators if these are not built in the manual for your rack should tell you whether the terminators are built in Check that the power supply is within VME limits on 5V 3 3V 12V 12V if used on PMC with a digital volt meter Check that there is only one board configured as system controller and that this is in slot 1 Check that there are no vacant slots in the rack without jumpers or that an automatic daisy chaining backplane is being used If you are still getting unexpected behaviour try removing all other VME boards from the rack and proving the VMPC6a s operation in isolation then adding a board at a time until the offending element is found If you are using the SCSI bus then check that the cable stub length is less than 10 cm Also ensure that the bus terminator is only enabled if the VMPC 6a is at the end of the SCSI bus The battery for the RTC NVRAM may be exhausted causing corruption of environmental variables See section 9 2 5 3 NVRAM RTC page 68 for more details Thales Computers 95 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Troubleshooting B 3 Step 3 Power On No Terminal Display Check that all cables are plugged in correctly If you have made your own cable check that the pin assignment is correc
37. memory controller included in the AVIGNON CPC710 host bridge performs Error Correction Coding ECC at full speed The SDRAM is protected by eight ECC error bits per 64 data bits Single bit and double bit errors are detected In addition single bit errors are corrected All system memory is contiguous and is shared between the processor and the two PCI busses 9 2 5 2 System Flash EPROM 1 5 MBytes of System Flash EPROM is available through 2 devices a 4 Mbit 3 3V System Flash device in a 32 pin PLCC socket located on the top side of the board See Figure 2 1 page 6 for socket identification and a TSOP 1 MByte System Flash located on the bottom side of the board Supported PLCC System Flash types on the VMPC6a Reference Manufacturer 29LV040 AM29LV040B 120J1 AMD 39VF40 SST39VF040 70 4CNH SST SST39VF040 90 4CNH M29W040B 120K6 29W040 M29W040B 120K1 ST SGS THOMSON M29W040 120K1 29LF040 TMS29LF040 10C5FME TI 29 VF040 TI The removable flash memory on the top side of the board contains the debugging monitor VMPCBug and the self tests The 1MB flash memory which is located on the bottom side of the board may contain for example VxWorks software See Figure 2 1 page 6 for socket identification of the removable flash memory Link LK2 enables or disables writes to the System Flash EPROMs see section 4 2 page 15 Both flash memories may be upgraded from a media CD ROM ethernet Refer to the VMPCBug Us
38. s Reference Guide the 21143 data sheet or the 21143 Hardware Reference Manual Boot ROM Board Control PCI CardBus External Reg Serial ROM and LEDs PCI CardBus BOOT ROM Serial ROM General Interface Port Port Purpose Reg 32 32 32 4 32 32 T O FIFO 16 16 RxM TxM 1 4 Physical Coding SIA Interface NWAY Sublayer PCS 4 4 Scrambler Descrambler 10BASE T Interface MII SYM Interface i 10 Mb s 10 100 Mb s Figure 9 5 PCI 10 100 Mb s Ethernet LAN Controller Block Diagram CA DT 129 5e 72 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Functional Description Connectors In standard connection to the 1OBASE T or 100BASE T interface is made through a RJ45 connector P6 on the front panel refer to the P6 pin assignment information in section 5 2 4 page 42 With the Ethernet routed to backplane manufacturing option the IOBASE T or 100BASE T interface is available on the P2 connector refer to the P2 pin assignment information in section 5 1 5 page 24 LED ETHERNET Activity LEDs ETH are mounted on the bottom side of the board behind the front panel see section 8 3 page 50 The green LED indicates that the Ethernet interface is working The red LED lights when the Ethernet interface is running in 100BASE T mode and is off in IOBASE T mode These LEDs can be overridden by sof
39. to the VMPCBug User s Manual CA DT 129 5e 68 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Functional Description 9 2 6 VMEbus Interface The ALMA_V64 PCI to VME bridge is a device developed by IBM and Thales Computers This component is a highly integrated single chip solution to interface VME64 from a 32 bit PCI bus Features include a system controller a bus requester a master interface a slave interface an interrupt handler an interrupt generator and a 2 channel DMA controller Appendix A details the VMEbus compliance of the VMPC6a External Interrupts Bus Request VME Bridge Interrupt to PCI Bus Grants Bus Request 1 4 5 Bus Grant PCI Bus PCI Bus PCI Bus PCI Bus Interrupt PCI Bus Controller Arbiter Requestor Interface Function Registers 256 Bytes 2 Channel DMA Controller Resets gt Timers Clock VME Bus VME Bus VME Bus VME Bus System Interrupt Data Transfer Controller Requestor Controller Interface Utility Data Transfer Priority Interrupt Data Transfer Bus Bus Arbitration Bus Bus Figure 9 3 PCI to VME Bridge Block Diagram 9 2 6 1 VMEbus Master Access The VME module provides D32 D16 D8 and UAT under A32 A24 or A16 addressing modes plus D64MBLT and D32BLT under A32 and A24 addressing modes The VME block mode D64 or D32 can be automatically star
40. window is closed VME autoslotid is automatically disabled 1 The VME board ID is given by the preceding VME Board ID field CA DT 129 5e 86 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com VMPCBug Debugging Monitor VME slave windows 0 A32 A16 1 A16 2 A32 3 none 0 0 A32 A16 default VME slave windows are opened 1 A16 VME slave window is opened 2 A32 VME slave window is opened 3 A32 and A16 default VME windows are closed L2 Cache Mode Write Through 0 Copy Back 1 Disabled 2 1 0 L2 cache mode is Write Through 1 L2 cache mode is Copy Back 2 L2 cache is disabled 10 23 DEV Command This command lists the controllers and their related identifier The following example shows the information displayed with the DEV command COMMAND gt DEV 0x3 RAM device 0x4 Flash EPROM 0x5 User Flash 0x6 NVRAM device 0x8 NULL device Oxc SCSI controller Entering the DEV command with the Identifier number option i e the device number will display the name of the device associated to this device number COMMAND DEV Identifier number 10 2 4 ENV Command This command sets up environment variables The environment variables are located in the NVRAM in the PReP format ENV command may be executed with options According to the option entered the command lists updates or deletes the environment variable _
41. www artisantg com Page 2 of 2 26 Thales Computers Connectors 5 1 7 PMC Connector Pin Assignment 5 1 7 1 J11 PMC Connector Pin Assignment Pin Signal Pin Signal TCK 12V Ground 0V INTA INTB INTC BUSMODE 1 5V INTD N C Ground 0V N C CLK Ground 0V Ground 0V GNT REQ 5V V 1 O AD 31 AD 28 AD 27 AD 25 Ground 0V Ground 0V C BE 3 AD 22 AD 21 AD 19 5V V I O AD 17 FRAME Ground 0V Ground 0V IRDY DEVSEL 5V Ground 0V LOCK 41 SDONE 42 SBO 43 PAR 44 Ground 0V 45 V I O 46 AD 15 47 AD 12 48 AD 11 49 AD 09 50 5V 51 Ground 0V 52 C BE 0 53 AD 06 54 AD 05 55 AD 04 56 Ground 0V 57 V I O 58 AD 03 59 AD 02 60 AD 01 61 AD 00 62 5V 63 Ground 0V 64 REQ64 PCI signals active when low Thales Computers 27 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Connectors 5 1 7 2 J12 PMC Connector Pin Assignment 2 3 TMS 4 N C 5 TDI 6 Ground 0V 7 Ground 0V 8 N C 9 N C 10 N C 11 BUSMODE 2 12 3 3V 13 RST 14 BUSMODE 3 15 3 3V 16 BUSMODE 4 17 N C 18 Ground 0V 19 AD 30 20 AD 29 21 Ground 0V 22 AD 26 23 AD 24 24 43 3V 25 IDSEL 26 AD 23 27 3 3V 28 AD 20 29 AD 18 30 Ground 0V 31 AD 16 32 C BE 2 33 Ground 0V 34 N C 35 TRDY 36 3 3V 37 Ground 0V 38 STOP 39 PERR 40 Ground 0V
42. 29 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CA DT 129 5e VMPCBug Debugging Monitor m CST j 5 o T G Go and Insert Temporary breakpoint G G G Help Command Device I O M Memory Modify MD Memory Display Usual Commands Page 2 of 3 80 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com VMPCBug Debugging Monitor CO emesms 0 m emen o o esewus o Set the horizontal timing registers for a graphics PMC VOESSELH in VGA mode Set the vertical timing registers for a graphics PMC in VGA mode VM VME Memory Modify VPD VPD Display VT NOVT Set Reset VT100 Mode Usual Commands Page 3 of 3 VGASETV Table 10 1 Usual Commands 1 The AUTO command may be used to run the self tests available for VMPC6a and to retrieve a report of these tests refer to the Self tests for VMPC6 Boards User s Manual 2 The FCT command must be only used to run the manufacturing tests Certain debugger commands as VPD CONF DEV and ENV give information concerning the configuration of the VMPC6a board Thales Computers 81 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com VMPCBug Debugging Monitor 10 2 1 VPD Command This command displays the Vital Product Data stored in the EEPROM The
43. 3 1 0xc0000000 0x00000000 0x00040000 0 3 2 0x80000000 0x00000000 0x00010000 3 4 0xd8000000 0x18000000 0x08000000 0 4 0 0x80011000 0x00011000 0x00001000 1 4 1 0xc0040000 0x00040000 0x00001000 0 5 0 0x80012000 0x00012000 0x00001000 1 5 1 0xc0041000 0x00041000 0x00001000 0 5 2 0xc0042000 0x00042000 0x00001000 0 6 0 0x80013000 0x00013000 0x00001000 1 7 0 0xc0043000 0x00043000 0x00001000 0 Thales Computers 83 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com VMPCBug Debugging Monitor CONF C gt Display the checksum of the first System Flash EPROM VMPCBug The following example shows the information displayed with the CONF C command COMMAND gt CONF C Checksum of System Flash EPROM First Slot VMPCBug 0x1ff2600 _ CONF S gt Display the checksum of the second System Flash EPROM The following example shows the information displayed with the CONF S command COMMAND gt CONF S Checksum of System Flash EPROM Second Slot 0x3fc000 CONF M gt Display and modify the VMPC6a board configuration The following example shows the information displayed with the CONF M command The first screen appears COMMAND CONF M VMPC6a Firmware VMPCBug 2 5 00139 CPU PPC750 450 MHz Rev 3 0 Bus Frequency 100 MHz Host Bridge AVIGNON 1 0 Memory Size 128 Mbytes DRAM Type SDRAM without ECC checking disabled NVRAM Type M48T18 L2 c
44. 6 69 70 Interrupt Controller 70 Register 70 82 86 Altitude 92 Antistatic Precautions 11 Applications 1 66 67 97 Audience 2 AVIGNON Chip 58 Host Bridge 60 61 65 66 67 Interrupts 57 Memory Controller 54 Register 51 56 63 B Backplane Links 47 95 Board Configuration 84 Identification 12 C Cables 95 96 Carrier Card 1 5 7 61 67 Checkstop 57 CHRP 51 COBRA Chip 54 60 66 68 71 76 GPIOs 74 76 Interrupts 57 Peripheral 71 Register 59 63 Configuration Default 95 Link 95 System 47 48 67 VMEbus Interface 68 70 Connectors 11 17 47 95 Front Panel 10 100BASE T 42 73 90 Keyboard Mouse 37 77 90 SCSI 40 75 90 Thales Computers Index Serial 38 76 90 PO 7 18 90 P2 8 22 24 47 48 90 Local I Os 7 8 73 75 76 77 90 PMC I Os 7 8 PMC 27 28 29 30 Processor RISCWatch JTAG 33 34 RISCWatch L2 SRAMs JTAG Resets 56 Serial 48 SRAMs JTAG 34 VMEbus 19 22 Conventions 3 Cooling 92 CPC710 See AVIGNON Chip D Debugging Monitor 48 49 67 68 79 88 96 Command List 79 CONF Command 38 70 74 76 82 83 84 DEV Command 87 ENV Command 68 70 87 88 System Flash 15 Use 79 User Flash 16 VPD Command 82 Debugging Tools 33 34 Device Number 60 61 83 87 Dimensions 93 DMA Controller 69 70 E ECC 67 EMC 91 Environment 92 Operating 92 Storage 92 EPROM See Memory Errors 22 31 55 97 Ethernet 1 5 7
45. 6 1 provides an industry standard high speed from 132 Mbytes second to 533 Mbytes seconds depending on data width and frequency local expansion bus designed for graphics high speed communications e g ATM multi media and user defined custom functions PCI has established itself as the leading local interconnect standard and the wide availability of compatible devices coupled with its adoption on an array of platforms ensures that PCI based modules offer both high performance and low cost The highly integrated nature of the VMPC6a makes it a true single board computer and allows the VME64 interface to become an optional feature for appropriate applications The VMPC6a comes with different build options which are listed in the following table C PowertngineB Order Code ca Twa T ma a ow vmecsa T T PI Envir Boards with large memory require specific O S application management Please check O S type and release PCI signaling level on the VMPCBa and on the PMC devices should match Table 2 1 VMPC6a Order Code Thales Computers 5 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com USB Cont i General Information PPC750 CPU0 AVIGNON CO 4 074 L Host Bridge COBRA Interrupt and I O Controller SCSI CONTROLLER 10 100BASE T Transformer PPC750 ALMA_V64
46. CMD USB0673B controller It supports USB keyboard and mouse devices Connectors Two separate USB ports are available on the board one on the P3 front panel and the other on the P2 connector Connections to the mouse and keyboard are made through an USB type plug connector P3 on the front panel refer to the P3 pin assignment information in section 5 2 1 page 37 and or the P2 connector refer to the P2 pin assignment information in section 5 1 5 page 24 9 3 Temperature Control The board temperature is controlled by the temperature supervisor DS1620 When the authorized temperature is overstepped an interrupt is sent via the COBRA I O controller see section 8 5 5 page 57 The temperature supervisor instructions are managed by the COBRA GPIO 21 23 refer to the Programmer s Reference Guide Thales Computers 77 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Functional Description CA DT 129 5e 78 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 10 VMPCBug Debugging Monitor The debugging monitor VMPCBug for the VMPC6a which controls its operation after power up is contained in the first Flash memory socket See Figure 2 1 page 6 for socket identification VMPCBug is described in the VMPCBug User s Manual SD DT A35 and the main upgrades between the last
47. EPROM Link LK2 0 0 ccc ccc cc ccc cece cece ee hh hh rr rh nnn 15 4 3 User Flash EPROM Link EK3 ooo c5 5 a e RR ERE RERO mI RE SEE AE 16 44 Table Of Default Link Settings o ooooooooomocrororororcrononorrorororccccccac oo 16 Chapter 5 Connectors cmo A SKS DEE TS ERE URCETE ERE REY 17 5 Onboard Connectors 4 2 1 2 20 929 Bc 9 RR aa 17 5 1 1 PO Connector Pin Assignment Optional o oooooocoococoorc e 18 5 1 2 P1 and P2 Row B VMEbus Connector Pin Assignment oooococcococoorco cor 19 5 1 3 Geographical Address Pin Assignment 0 0 0 cece ee 21 5 1 4 VMEbus Signal Description o ooooooooorrr e 22 5 1 5 P2 Connector Pin Assignment i cess pe I RR ai 24 2 46 P2 Signal Descriptions 22 eee epee rd ACESS pu Ar rd 25 5 1 7 PMC Connector Pin Assignment o 27 5 1 7 1 JII PMC Connector Pin Assignment csse 27 5 1 7 2 J12 PMC Connector Pin Assignment csse 28 5 1 7 3 J13 PMC Connector Pin Assignment oooooocconononon e 29 5 1 7 4 JI4 PMC Connector Pin Assignment ooooococconononca eee eas 30 Thales Computers i CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Table Of Contents 5 18 PMC Signal Description o oooo eI et 31 5 41 9 P7CPUO RISCWatch Connector Pin Assignment 0 0 0 e 33 5 1 10 P8 CPUI RISCWatch Connector Pin Assignment 00 0 0 ee eee 34 5 1 11 P7 and P8 Signal Desc
48. Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Glossary l VMPC6a Thales Computers processor card based on the PowerPC 750L Write Posting This is a pipelining technique that can be used for example in the VME interface chip to increase system performance In Master Write Posting when a local bus master writes to the VMEbus instead of requesting and arbitrating for the bus transferring data to the slave and waiting for the acknowledgement the VME interface chip acknowledges the local bus master immediately after gaining VMEbus ownership and captures the address and data to write The local bus master can then continue with its processing and the VME interface chip transfers the data for the host Slave Write Posting works in a similar way Write operations to the VME interface chip as a VME slave do not wait for the chip to write the data to the host memory and do not wait for its acknowledge The VME interface chip acknowledges the VME bus immediately after gaining local bus ownership and captures the address and data to write Another transfer can then take place on the VMEbus while the VME interface chip writes the data from the previous one CA DT 129 5e 104 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Index A Addressing Extended 22 69 89 Short 22 69 89 Standard 22 69 89 ALMA_V64 Chip 7 60 6
49. I PMC IO 18 13 PMC IO 20 RST SCSI 5V DB12 SCSI PMC IO 19 14 GND MSG SCSI D16 DB13 SCSI PMC IO 21 15 PMC IO 23 SEL SCSI D17 DB14 SCSI PMC IO 22 16 GND C D SCSI D18 DB15 SCSI PMC IO 24 17 PMC IO 26 REQ SCSI D19 DBP1 SCSI PMC IO 25 18 GND 1 0 SCSI D20 N C PMC IO 27 19 PMC IO 29 TERMPWR D21 TERMPWR PMC IO 28 20 GND DATA D22 CO GPIO 1 PMC IO 30 21 PMC IO 32 DATA D23 CO GPIO 2 PNC IO 31 22 GND GND GND CO GPIO 3 PMC IO 33 23 PMC IO 35 N C D24 CO GPIO 4 PMC IO 34 24 GND PWRFLT2 D25 CO GPIO 5 PMC IO 36 25 PMCIO38 M S2 TXD D26 CO GPIOJ 6 PMC IO 37 26 GND Ng S2 RXD D27 N C PMC IO 39 27 PMCIO41 lg S2_RTS D28 S1 TXD PMC IO 40 28 GND HN S2Rn D29 S1 RXD PMC IO 42 29 PMC IO 44 g S2 CTS D30 S1_RTS PMC IO 43 30 GND MW S2 DTR D31 S1 CTS PMC IO 45 31 PMCIO46 S2 DCD GND S1 DTR GND 32 GND Ng S2 DSR 45V S1 DCD 45V Signals active when low Y Signals not available in Two simplified lines on front panel mode T Ethernet signals only available with the Ethernet routed to backplane manufacturing option In standard do not connect these pins e This signal is not used on VMPC6a CA DT 129 5e 24 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Connectors 5 1 6 P2 Signal Descriptions The VME signals row b are described in section 5 1 4 Mnemonic Description
50. Interface A standard and associated hardware for general purpose communication usually between a processor and large capacity storage devices e g hard disks 102 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Glossary Slave A slave detects VMEbus cycles initiated by a master and when these cycles specify its participation transfers data between itself and the master Slot A position where a board can be inserted into a backplane If the system has both a J1 and a J2 backplane or a combination J1 J2 backplane each slot provides a pair of 96 or 160 pin connectors SMI System Management Interrupt SPECint95 A benchmark package produced in 1995 measuring the integer performance of a processor SPECfp95 A benchmark package produced in 1995 measuring the floating point performance of a processor Superscalar A superscalar processor is a processor with multiple execution units that may operate in parallel System Controller loire le ce iio hd a de A board in slot 1 of the VMEbus backplane It must have a SYSCLK driver an arbiter an IACK daisy chain driver and a bus timer TBD To Be Defined TCP IP Transport Control Protocol Internet Protocol A collection of network protocols that together support host to host communication for hosts connected to any of a number of heterogeneous networks Netw
51. MSB Signal names ending with an asterisk denote active low signals all other signals are active high Following the PCI convention signal names ending with a denote active low signals all other signals are active high The term VMPC6a is used generically to refer to the VMPC6a using one PowerPC 7501 and VMPC6a Dual using two PowerPC 750L boards The devices are specifically referenced where necessary Thales Computers 3 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Introduction 1 6 Related Documents Due to the complexity of some of the devices used on VMPC6a you will need to refer to the following documents for more detailed information Thales Computers Documentations Q VMPC6a or VMPC6a Dual Board Hardware Release Notes publication number CA DT 328 Q VMPC6 Boards Connection Guide publication number CA DT 319 Q VMPC6 Boards Programmer s Reference Guide publication number CA DT 318 Q Supplement for VMPC6a RA or VMPC6a Dual RA Boards User s Guide publication number CA DT 132 Q VMPC6a RC or VMPC6a Dual RC Boards User s Guide publication number CA DT 128 Q Self Tests for VMPC6 Boards User s Manual publication number CA DT 320 Q Release Notes VMPCBug and Self Tests publication number SD DT A51 Q VMPCBug User s Manual publication number SD DT A35 Q CPCIGx Board Thales Computers Graphics Mezzanine Board publ
52. MWARE VMPCBug AND THE OPERATING SYSTEMS LynxOS VxWorks AIX Also it depends on the hardware configuration PMCs How to obtain the CPU and PCI addresses To obtain the CPU address then the PCI address you must 1 Read the CNFR AVIGNON CPC710 register This register selects the type of PCI bus 32 bit PCI bus or 64 bit PCI bus 2 Read the BAR AVIGNON CPC710 register associated with the corresponding PCI bus 3 Retrieve the Base Address of the PCI MEM or PCI I O on the CPU address space for this read at the BAR value plus the SMBAR register address or SIBAR register address respectively 4 Retrieve the Base Address of the PCI MEM or PCI I O on the PCI address space for this read at the BAR value plus the PMBAR register address or PIBAR register address respectively 5 Generate PCI configuration cycle on PCI busses for this use the CONFIG_ADDR and CONFIG_DATA AVIGNON CPC710 registers These registers specify the bus and the device number associated with each resource Refer to section 8 6 page 60 or section 8 7 page 61 for more information about the device number associated with each VMPC 6a device NOTE You can read these registers It is also possible to modify them but Thales Computers does not guarantee any consequence of these modifications Refer to the CONF D command in the section 10 2 2 page 82 for more details about the PCI BAR mapping Thales Computers 51 CA DT 129 5e Artisan Technol
53. ND 15 N C 16 GND 17 N C 18 GND 19 N C 20 GND 21 N C 22 GND 23 N C 24 GND 25 N C 26 GND 27 N C 28 GND 29 N C 30 GND 31 N C 32 GND is VME signals active when low te This signal is not used on VMPC6a Thales Computers Artisan Technology Group Quality Instrumentation 9 Not used on VMPC6a except 12 V and 12 V for the supplies of the PMC mounted without PMC carrier card Geographical address pins refer to section 5 1 3 page 21 for more information CA DT 129 5e Guaranteed 888 88 SOURCE www artisantg com Connectors Do not exceed the maximum rated input voltages or apply reversed bias to the assembly If such conditions occur toxic fumes may be produced due to the destruction of components Only use the VMPC6a in VME IEEE1014x or VME64 backplanes that supply power on both P1 and P2 connectors Failure to observe this warning may result in damage to the board Only use 5 row connector VME backplane to avoid cross talk and ground bounce noises over the VMEbus CA DT 129 5e 20 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Connectors 5 1 3 Geographical Address Pin Assignment The 6 geographical address pins GAO GA1 GA2 GA3 GA4 and GAP shall be tied to ground or left open floating on the backplane J1 connector as per VME64x norm Number Pin Pin Pin Pin Pi
54. OR ROC RNE Early BBSY release Bus capture and hold FAIR requester 1 to 256 us disabled Programmable Write Posting Prefetch Read coupled mode AutoslotID Programmable BB2BLT mode 4 shared 8 bit Semaphore registers Geographical addressing Auto system controller IACK Daisy Chain Driver SYSCLK Driver 89 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com e Processor SDRAM L2 Cache System Flash EPROM User Flash EPROM RTC NVRAM 32 bit PCI 64 bit PCI SCSI Ethernet PMC Slot Serial I O Keyboard and Mouse Counter Timers Status LEDs Operating Systems ICPMC 6 PCI Carrier Manufacturing Option CA DT 129 5e Specifications A 2 Local Resources One or two PowerPC 750L 32 bit microprocessors with clock frequency from 450 MHz and upwards Up to 512 MB with ECC onboard 1 MB per processor with L2 cache frequency from 180 MHz and upwards 1 5 MB with a 4 Mbit Flash EPROM in JEDEC standard 32 pin PLCC socket and a TSOP 8 Mbit Flash EPROM no socket Up to 32 MB of byte wide Flash EPROM M48T18 RTC with 8Kx8 of battery backed NVRAM 32 bit 33 MHz 64 bit 33 or 66 MHz depending on the number and capability of PCI agents Ultra or Wide Ultra SCSI via a 68 way SCSI 3 socket connector on the front panel and or the P2 connector IEEE 802 3 100BASE T or 1OBASE T via a RJ45 connector on the front panel or the P2 connector d
55. OURCE www artisantg com Connectors 5 2 2 P4 Serial Connector SERIAL The P4 serial connector SERIAL supports two different pin assignments selectable by software one single serial channel with full modem control signals or two simplified serial channels with transmit and receive signals only This management is made through the CONF M debugging monitor refer to the section 10 2 2 CONF Command page 82 or by programming the COBRA GPIO 29 refer to the Programmer s Reference Guide Serial lines should only be used on one connector either on the SERIAL or P2 connector 5 2 2 1 SERIAL Connector with One Full Modem Serial Channel When the Two simplified lines on front panel field is set to NO this 9 way micro D type plug connector provides a PC style serial channel 1 It has the following pin assignment 1 DCD 6 DSR 2 RXD 7 RTS 3 TXD 8 CTS 4 DTR 9 RI 5 Serial Ground Shell Chassis Ground Signal Description SERIAL CTS Channel 1 Clear To Send DCD Channel 1 Data Carrier Detect DSR Channel 1 Data Set Ready DTR Channel 1 Data Terminal Ready RI Channel 1 Ring Indicator RTS Channel 1 Ready To Send RXD Channel 1 Receive Data TXD Channel 1 Transmit Data Serial Ground Quiet ground internally connected to OV CA DT 129 5e 38 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www arti
56. PMC I Os As a manufacturing option the 10 100BASE T Ethernet port could be available on P2 connector replacing the Ethernet front panel connectivity For more information about the P2 pin assignment refer to section 5 1 5 page 24 Using P2 I O minimizes the effort needed to remove boards from a rack improving maintainability and reliability For example the P2 I Os may be attached by a VME64 P2 transition module CP2IOWSRU refer to the Connection Guide for more information about the P2 transition module pin assignments GEM 7 16 bit SCSI connector CP2IOWSRU 1 PMC IO connector COBRA GPIO connector Serial line connector Figure 2 2 Auxiliary O Connection CA DT 129 5e 8 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com General Information 2 4 Operating System Support The following operating systems are supported on the VMPC6a as Thales Computers standard products AIX LynxOS and VxWorks Tornado Contact Thales Computers for more information Thales Computers 9 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com General Information CA DT 129 5e 10 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 3 Unpacking and Ident
57. SI terminators are de activated Terminators are de activated when SCSI devices are not connected or are connected to both SCSI connectors P2 and front panel at the same time except for the case below 2 Means that onboard SCSI terminators are half activated Useful when Wide SCSI devices are connected to one connector P2 or front panel and when the second connector only has to support narrow 8 bits SCSI devices P2 connector P5 front panel connector t bitSCSK 8 bitSCSI 16 bitSCSI 8 bitSCSI an L1 po ere X ON 0 X ON 0 X X ON 0 2 ON 0 X OFF 1 X HALF 2 X X OFF 1 2 ON 0 HALF 2 OFF 1 HALF 2 2 ON 0 2 OFF 1 2 X X HALF 2 2 Ox x x x f orm 1 A specific connection is required for 16 bit SCSI devices to the P2 connector x Xx x Xx x lt 2 In these configurations a specific connection is required Thales Computers 85 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com VMPCBug Debugging Monitor VME System Reset Spread YES 0 NO 1 0 0 Only when system controller the VME system reset is spread on the VME bus at reboot time Default 1 The VME system reset is not spread on the VME bus VME Board Id 0x0 OxFF 0 The VME Board ID identifies the VMPC6a on the VME bus Each VMPC6a on the VME bus must be configured with a different value for the VME Bo
58. UT signals form the bus grant daisy chain i e the BGxOUT of one board forms the BGxIN of the next board in the daisy chain Bus Grant 0 to 3 Out These signals are generated by requesters to tell the next board BGOOUT to BG3OUT in the daisy chain that if it is requesting the bus on that level then it may use the bus Otherwise the board should pass the signal down the daisy chain Bus Request 0 to 3 A low level generated by a requester on one of these lines shows BROTO BRS that some master needs to use the bus Data Bus 0 to 31 These signals are used to transfer data between masters and slaves and status ID information from interrupters to interrupt handlers DOO to D31 Data Strobe 0 1 These signals are used with LWORD and A01 to show how many byte locations are being accessed 1 2 3 or 4 Also during a write cycle the falling edge of the first data strobe shows that valid data is available on the bus On a read cycle the rising edge of the first data strobe shows that data has been accepted from the data bus DSO DS1 Page 1 of 2 CA DT 129 5e 22 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Connectors Mnemonic Signal Description Data Transfer Acknowledge This signal is generated by a slave The falling edge shows that valid data is available on the data bus during a read cycle or that data has be
59. a 8 1 Power up After you have verified that 1 all necessary hardware configuration has been done refer to Chapter 4 2 connections have been made correctly refer to Chapter 5 or to the Connection Guide 3 your PMC has been correctly plugged into the VMPC6a refer to Chapter 6 or to the Connection Guide 4 the backplane configuration is complete you have taken note of the system configuration suggestions see Chapter 7 and the VMPC6a firmly secured in the rack you can power up the system When power is applied the VMPCBug debugging monitor executes various self tests and then displays the debugger prompt COMMAND gt You can enter a debugger command to execute the self tests set your environment parameters or boot your system For further information about the VMPCBug firmware refer to Chapter 10 VMPCBug Debugging Monitor or to the VMPCBug User s Manual SD DT A35 8 2 Reset Switch The front panel reset pushbutton can be pushed to generate a hard reset NOTE When the board is the VME system controller asserting the front panel Reset will also assert SYSRESET on the VME bus resetting the whole VME configuration This may be disabled by the CONF command refer to section 10 2 2 page 82 for more information about the CONF command Thales Computers 49 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Operating Instructions
60. a functional description Q Chapter 10 gives an overview of the VMPCBug Debugging Monitor s commands O Appendix A is a board specification O Appendix B gives troubleshooting guidelines There are also a glossary and an index provided CA DT 129 5e 2 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Introduction 1 5 Conventions All numbers are expressed in decimal except addresses and memory or register data which are expressed in hexadecimal The prefix Ox shows a hexadecimal number following the C programming language convention Information of particular importance is in bold typeface and is further highlighted by the WARNING box General information is sometimes in bold typeface and is further highlighted by the NOTE box NOTE The multipliers k M and G have their conventional scientific and engineering meanings of 103 106 and 10 respectively The only exception to this is in the description of the size of memory areas when K M and G mean 210 220 and 230 respectively NOTE When describing transfer rates k M and G mean 103 106 and 10 nor 210 220 and 230 In PowerPC terminology multiple bit fields are numbered from 0 to n where 0 is the MSB and n is the LSB PCI and VMEbus terminology follows the more familiar convention that bit 0 is the LSB and n is the
61. ache size 1024 Kbytes 8 Mbytes of User Flash detected Extended PCI Bus Mode 64 Bits mode PCI Bus Devices Bus 0 Slot 3 CETIA COBRA I O Controller Rev 0 Bus 0 Slot 4 DEC DC21143 Fast Ethernet Ctrlr Rev 4 1 Bus 0 Slot 5 SYM 53C875 Ultra Wide SCSI Rev 4 Bus 0 Slot 6 IBM PCI VME Bridge Rev 2 1 Bus 0 Slot 7 CMD USB0673 USB Ctrl Rev 5 Bus 1 No PCI Devices Detected Then the configuration fields are displayed for each field modify the configuration if needed or press the Enter key to display the following fields A Serial Port used Channel 1 0 or Channel 2 1 0 0 Selects channel 1 as standard TTY port by the VMPCBug Default 1 Selects channel 2 as standard TTY port by the VMPCBug CA DT 129 5e 84 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com VMPCBug Debugging Monitor Two simplified lines on front panel YES 1 or NO 0 0 0 Full modem serial port 1 is available on the SERIAL connector 1 Both simplified serial ports 1 and 2 are available on the SERIAL connector A but only simplified channel 1 is directed to P2 On Board SCSI Terminators ON 0 OFF 1 or HALF 2 0 A 0 Means that onboard SCSI terminators are activated Terminators are activated when SCSI devices are only connected to SCSI front panel connector or P2 SCSI connector but not to both of them at the same time Default 1 Means that onboard SC
62. ality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Functional Description 9 2 General Description 9 2 1 Host Bridge The AVIGNON host bridge named CPC710 by IBM is a device developed by IBM and Thales Computers It handles the processor bus controller two PCI bridges an SDRAM memory controller and the system I O interface including the System Flash EPROM This highly integrated host bridge provides the arbitration for up to two processors and supports two levels of pipelining per processor along with 64 byte buffers The processor bus controller operates at 100 MHz and upwards It contains two PCI host bus bridges One PCI bridge supports a standard 32 bit 33 MHz PCI bus which is used for native VO refer to section 9 2 4 1 page 66 The second PCI bridge supports a 64 bit PCI bus clocked at 33 MHz or 66 MHz refer to section 9 2 4 2 page 66 The memory controller for AVIGNON CPC710 is designed to support Synchronous DRAM from 100 MHz and upwards For more information about the programming refer to the IBM CPC710 PowerPC chip support with dual PCI Bridge amp SDRAM User s Manual or to the Programmer s Reference Guide 9 2 2 Processor The PowerPC has become the most widely used of the new generation of RISC processors Its pedigree is unequalled jointly developed by IBM and MOTOROLA Main features of PowerPC 750 processor on VMPC6a O Superscalar 3 instructions per clock cycle 2
63. ality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Table Of Contents Chapter 9 Functional Description 0 0 cece ec cece cece ce reece renee eee eeees 63 9 1 VMPC6a Block Diagram coi a PRG T ENS 64 9 2 General Description 3 50 65 sds 5206s 92 wale aes age 5 I rs RTR Bes Ba tars Sale ba Died PI Ra EEE ES 65 9 2 1 Host Bridge isa Soe pid ease ra RE RR RARE Edd RE hg EY aie a gw ee 65 pu o E HET 65 9 2 3 Secondary Level Cache ssec eese ere eer E y ep e UR EE be pner eus 65 024 POIL A dia 66 924 L 32 bit PEL D S ice ea oe CR RA RR Ron AR a Ul e e e e RU P 66 9 242 64 bit PCI bus ii UR RR a P VE e r4 E ER E 66 92 13 PCI Carrier Card 5 A is alge pede 67 PPS MEN uo Cm 67 92 5 SDRAM ive td de T E AR E X e Ye wee Hee EY 67 92 5 2 System Flash EPROM esse terere e Ra or RR de 67 9233 NVRAMIREG sert ESAE A ERE bebe e deberi dore doe d 68 9 2 5 4 User Flash EPROM cdi reo a ue a acu rr be ie oso ee abl 68 02 6 VMEbus Interface uses ap CR DR ETUR RA REC REED ERU E Rd a es 69 9 2 6 1 VMEbus Master Access oo oooooo hh hs 69 9 2 6 2 VMEbus Slave Access isssseeesee e hrs 69 9 26 3 VMEbus Arbitrdtioft o es see Re RA RR Ro e Re tba ER AR 70 92 65 4 DMA Channels lt A re A eda UU e E E 70 9 2 6 5 Interrupt Management cesses Ih e he 70 9 2 7 Utility I O and Auxiliary Function Bus ooooocoocococrrr e 71 9 2 8 PCI 10 100 Mb s Ethernet LAN Controller 0 0 0 0 ccc cc
64. ard ID In this example the VME Board ID is set to O The VME Board ID is used to calculate two VME base addresses to reach the PCI VME bridge internal registers and the VMPC6a SDRAM respectivelly VME Slave A16 Base Offset 0 The VME Slave A16 Base Offset is an optional parameter VME Slave A16 Base Address will become 0x0 The VME address of the PCI VME bridge internal registers is called Slave A16 Base Address This value is calculated with the VME Board ID and the VME Slave A16 Base Offset For more details about the VME Slave A16 Base Address refer to the VMPCBug User s Manual VME to DRAM A32 Base Offset 0 The VME to DRAM A32 Base Offset is an optional parameter VME to DRAM A32 Gap 8000000 By default the VME to DRAM A32 Gap is set to 0x8000000 Be careful if you change this value not to create VME address conflicts VME to DRAM A32 Base Address will become 0x0 The VME address of the VMPC6a SDRAM is called VME to DRAM A32 Base Address This value is calculated with the VME Board ID the VME to DRAM A32 Base Offset and the VME to DRAM A32 Gap For more details about the VME to DRAM A32 Base Address refer to the VMPCBug User s Manual VME autoslotid 0 auto 1 manual 0 0 The VME Board ID is automatically calculated It will correspond to the relative board number in comparison with the system controller board into the VME backplane VME autoslotid needs VME A16 slave window if this slave
65. at uses address lines as well as data lines Mezzanine The American term for a daughter board MSB Most Significant Bit MTBF Mean Time Between Failures Thales Computers 101 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com RIS CA DT 129 5e Glossary Network File Server Non Maskable Interrupt Non volatile RAM Memory that does not lose its information when powered down Original Equipment Manufacturer Personal Computer Printed Circuit Board Peripheral Component Interconnect Plastic Leadless Chip Carrier PCI Mezzanine Card Portable Operating System Environment An IEEE standard PowerPC Reference Platform An example implementation of a philosophy designed to allow 10096 binary compatibility across different platforms when based on the PowerPC processor Prioritised A VMEbus arbiter that prioritises the four VMEbus request lines from BRO the lowest to BR3 the highest and responds with BGOIN to BG3IN It also informs the VMEbus master when there is a higher level request than that being processed by driving BCLR low Random Access Memory Memory that can be read from or written to at any time A VMEbus requester requests use of the VMEbus when it is required by a master Ring Indicator A serial line signal Reduced Instruction Set Computer The basic principle is to have a small set of
66. be expanded from one on board up to three by using a companion carrier card ICPMC 6 PMCs available directly from Thales Computers include high performance graphics ATM fast Ethernet asynchronous serial lines and MIL STD 1553B with a wide range of other PMC types available from Third Parties Additional I Os for twin serial and PMC I Os are also available Thales Computers proposes a complete solution providing customers with a single interface from the development environment to the Target Board Computer from the system software right through to hardware and system For example Thales Computers offers full support for multihead graphics systems based on the POWERENGINE Thales Computers PowerPC single board computer coupled with several graphics PMC modules Thales Computers cluster architecture allows the cohabitation on a single bus of several POWERENGINE VME CPU s each executing an OS AIX LynxOS VxWorks and dialoguing by means of a TCP IP type mechanism or by message passing over the VME backplane By exercising full control over the source code of the system software offering Thales Computers is able to guarantee perfect interoperability Thales Computers is a source code licensee for both AIX and LynxOS UNIX Operating System AIX compatible with IBM RS 6000 LynxOS a POSIX conformant Real Time OS with single and multiprocessing X11 MOTIF TCP IP are supported Native and cross development environments are available C
67. celerator multi channel communications SCSI Ethernet and ATM These are all fully compliant with the IEEE P1386 1 standard PCI provides a synchronous 32 or 64 bit multiplexed address and data bus allowing a theoretical burst data transfer rate of 512 Mbytes second 66 MHz 64 bits The PCI mezzanine format also provides 64 I O pins for user definition By using a dual PCI architecture the VMPC6a can maintain concurrent bus operation This allows applications using PMCs for routing and communications to operate efficiently in parallel with native PCI devices and VME without being blocked CPU System Bus Memory Bus 64 bit PCI Bus Host 32 bit PCI Bus PCI Carrier Card PCI Device PCI Device PCI Device ES Figure 9 2 PCI Interconnectivity generic use 9 2 4 1 32 bit PCI bus The 32 bit PCI bus is a high performance synchronous 32 bit bus running at 33 MHz The VMPC6a implements a 32 bit PCI with peak burst data rates up to 132 Mbytes second possible between PCI agents It supports the COBRA I O controller the Ethernet controller the SCSI controller the keyboard mouse controller and the ALMA V64 VME PCI bridge Section 8 6 page 60 describes the physical connection for each of these PCI devices to the host bridge The 32 bit PCI bus structure of the VMPC6a is shown in the block diagram page 64 and in section 9 2 4 9 2 4 2 64 bit PCI bus The 64 bit PCI bus is a high performance synchronous 64 bit bus
68. com Specifications A 3 Power Requirements Power Requirements are given excluding SCSI external terminators keyboard mouse NOTE Specifications for mezzanine modules optional PCI mezzanine can be found in the documentation of those modules VMPC6awith up to VMPC6a Dual with up 256 MB of DRAM to 256 MB of DRAM 5 V 1 2 5 96 2 5 33V B 45 95 2 5 96 0 A not used 0 A not used 12 V9 45 95 2 5 96 0 A not used 0 A not used 12 V3 5 2 5 0 A not used 0 A not used 1 If an SCSI device is connected to the VMPC6a the 5V power consumption may be increased by 0 25 A 2 If keyboard and mouse are connected to the VMPC6a the 5V power consumption may be increased by 0 25 A 3 These supplies are not used by the VMPC6a except to supply the PMC if needed when it is mounted without the PMC carrier card When a PMC module is plugged to the VMPC6a 5 V 12V and 12V power consumptions of this PMC are NOTE supplied directly by the VME backplane 3 3V power consumption is supplied via a VMPC6a power supply and in this case the VMPC6a 5V power consumption is increased See the PMC specifications to get the additional power consumptions on 3 3V 5V 12V and 12V WARNING Only use the VMPC6a in backplanes that supply power on both P1 and P2 connectors Failure to observe this warning may result in damage to the board A 4 EMC Regulatory Compliance and Rel
69. dard Physical and Environmental Layers for PCI Mezzanine Cards PMC Q M48T18 CMOS 8Kx8 TIMEKEEPER SRAM Data Sheet SGS Thomson publication number M48T18 on VMPC6a Q M48T59 CMOS 8Kx8 TIMEKEEPER SRAM Data Sheet SGS Thomson publication number M48T59 on VMPC6a RA Q TI16C550C Asynchronous Communications Element with Autoflow Control Texas Instruments publication number SLLS177E CA DT 129 5e 4 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 2 General Information This chapter contains general information for the VMPC6a product Chapter 9 gives a functional description of the board 2 1 Introduction The VMPC6a is a highly integrated PReP compatible VMEbus processor card based on the PowerPC 750L RISC CPU This product offers an extensive range of standard functions and expansion options including one VMPC6a or two VMPC6a Dual processor s clocked from 450 MHz and upwards secondary cache of 1 MB per processor onboard user memory up to 512 MBytes with ECC onboard serial and Ethernet channels 1 5 MBytes of system Flash memory up to 32 MBytes of user Flash memory a Wide Ultra SCSI peripheral interface a 64 bit 66 MHz PMC module site a 64 bit VMEbus interface and direct connection for a keyboard and mouse With the PCI carrier card ICPMC 6 expansion capabilities are provided for up to three PCI interface slots PCI PMC IEEE P138
70. details about the COBRA Vector Priority register More information about the interrupt priorities and modes are given in the Programmer s Reference Guide 8 5 6 PCI Interrupts The four PCI interrupt lines A B C and D from the PMC slots are connected to the INTEXT6 to INTEXT9 inputs of the interrupt controller as shown in the following diagram PMC or ICPMC COBRA A INTEXT6 B INTEXT7 C INTEXT8 D INTEXT9 See Chapter 6 page 43 for the PCI slot position Thales Computers 59 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Operating Instructions 8 6 32 bit PCI Configuration The 32 bit PCI bridge function inside the host bridge is responsible for executing load and store operations from the CPU to the 32 bit PCI bus Also the PCI bridge logic provides an interface for PCI devices to access system memory To generate a configuration cycle to PCI refer to the CPC710 User s Manual The following table describes the physical connections for each of the PCI devices on the host bridge HOST BRIDGE SIGNALS ARB Level REQ GNTO Device Number VMPC6a Device No device connected No device connected 1 COBRA REQ GNT3 ETHERNET REQ GNT4 SCSI REQ GNT2 ALMA V64 REQ GNT1 USB Table 8 2 Devices connected to the 32 bit PCI bus 1 No con
71. e operation of the processor 1 The pin assignment is as follows Pin Signal 1 TDO1 2 Reserved 3 TDI 4 TRST1 5 PD2 6 3 3V 7 TCK1 8 Reserved 9 TMS1 10 N C 11 SRESET1 12 Reserved 13 HRESET1 14 Reserved 15 CHECKSTOP1 16 Ground 0V Signals active when low CA DT 129 5e 34 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Connectors 5 1 11 P7 and P8 Signal Description Mnemonic Description Ground 0V Signal ground CHECKSTOPO Processor 0 checkstop output CKSPTOUTO signal CHECKSTOP1 Processor 1 checkstop output CKSPTOUT1_ signal HRESETO Processor 0 hard reset input HRESETO signal HRESET1 Processor 1 hard reset input HRESET1 signal N C This pin is not connected PD1 This pin is connected to the Ground via a 470 Ohm resistor PD2 This pin is connected to the Ground via a 470 Ohm resistor Reserved Do not use this pin SRESETO Processor 0 soft reset input SRESETO signal SRESET1 Processor 1 soft reset input SRESET1 signal TCKO Processor 0 JTAG Test Clock TCK1 Processor 1 JTAG Test Clock TDIO Processor 0 JTAG Test Data In TDI Processor 1 JTAG Test Data In TDOO Processor O JTAG Test Data Out TDO1 Processor 1 JTAG Test Data Out TMSO Pr
72. e priorities are shown in the table below The table also shows whether the prior state of each processor is recoverable or not Priority Exception CPU Signal Recoverability HRESET System Reset SRESET Power on Hard reset Soft reset Non recoverable Transfer Error Acknowledge Input TEA Address or Data Parity Non recoverable Machine Check Input MCP TEAY Machine Check MCP Recoverable unless External Interrupt External Interrupt Input INT Machine Check or System Reset occurs Recoverable unless Machine Check or System Reset occurs System Management Interrupt Systemi pr o a impui Thales Computers 55 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Operating Instructions 8 5 1 Types of Reset There are two types of reset that may be applied to the VMPC6a Hard and Soft 8 5 1 1 Hard Reset The hard reset resets all onboard resources and causes each processor to immediately branch to OXFFF00100 The hard reset may be generated by The power on reset The front panel reset pushbutton The VME reset SYSRESET signal A reset due to watchdog function via the PCI to VME bridge The Power System Controller Power Supply Level Supervisor when the 5 V supply from the VME or the internally generated supplies are out of range e A remote reset from the RISCWatch connectors P7 and or P8 3 3V Pow
73. en DTAGK accepted from the data bus during a write cycle The rising edge shows that the slave has released the data bus at the end of a read cycle GND The DC voltage reference for the system Interrupt Acknowledge This signal is used by the interrupt handler to acknowledge an IACK interrupt request It is routed to the IACKIN pin of slot 1 where it is monitored by the IACK daisy chain driver Interrupt Acknowledge In This signal tells the board receiving it that board can respond IACKIN to the interrupt acknowledge cycle in process or pass it down the daisy chain IACKIN IACKOUT form the interrupt acknowledge daisy chain IACKOUT Interrupt Acknowledge Out This signal is sent by a board to tell the next board in the daisy chain that it can respond to the interrupt acknowledge cycle in progress IRQ1 to IRQ7 Interrupt Request 1 to 7 These signals are driven low by interrupters to request an interrupt on the corresponding level Longword This signal is used with DSO DS1 and A01 to select which byte location s ENORD within the 4 byte group are accessed during the data transfer N C This pin is not connected System Clock This signal provides a constant 16 MHz clock signal that is independent of SYSCLK dn any other bus timing System Fail This signal shows that a failure has occurred in the system It can be SYSFAIL generated by any board in the system It is also asser
74. eneration of product in Thales Computers s POWERENGINE family based on VME PowerPC boards With this new generation Thales Computers confirms its leadership in the arena of PowerPC Real Time Systems as the first supplier of PowerPC VME SBC s beginning in November 1993 Designed for users who require scalable high performance processors sophisticated I O subsystems and high levels of on board integration the VMPC6a offers a cost effective solution to a wide range of application requirements Based on the industry standard PowerPC architecture the VMPC6a with one or two PowerPC 750L RISC CPUs onboard offers a choice of processor frequencies starting at 450 MHz The VMPC6a is based on the highly integrated host bridge AVIGNON named CPC710 by IBM which interfaces the system bus running at 100 MHz and upwards to both a 32 bit and a 64 bit PCI bus The board provides 1 MB of L2 cache connected directly on each processor via a 64 bit backside L2 cache bus with an operating frequency corresponding to half the CPU frequency up to 512 MB of onboard high performance Synchronous DRAM combined with Error Checking and Correcting ECC for high system integrity System and User Flashes and also an interrupt controller Local connection of Wide Ultra SCSI 10 100BASE T Ethernet interface keyboard mouse interface and VME64 bus use the 32 bit PCI bus With its IEEE P1386 1 PMC site allowing 64 bit 66 MHz PCI operations the number of PMC sites can
75. epending on the manufacturing option Default 5V V I O signaling voltage 32 bit IEEE P1386 1 compliant slot with front panel and or P2 I O PMC Slot VIO Key 3 3V manufacturing option to set V I O signaling voltage to 3 3V 33 or 66 MHz PCI 32 or 64 bits bus width One full modem serial port or two simplified serial ports via a 9 way micro D connector Both serial ports available via the P2 connector Keyboard and Mouse interface via an USB type plug connector on the front panel and or the P2 connector Four independent 31 bit global timers counting from 180 ns to 960x10 s These timers may be linked as two 62 bit timers One independant programmable 16 bit timer handled with an internal or external clock One independant 16 bit timer counter handled with an internal or external clock 11 LEDS STOP FAULT CPU VME SCSI EPCI ETH on the bottom side of the board behind the front panel including 3 software programmable LEDs SCSI and ETH AIX 4 4 3 x and further versions LynxOS 3 0 1 and further versions VxWorks 5 3 x Tornado and further versions Compliance PMC standard Space 1 VME slot Number of PMC slots 3 onboard I Os Front panel or VME P2 connector User Flash sizes 8 or 32 MB SDRAM sizes 128 256 or 512 MB Ethernet routed to backplane PO connector fitted PMC slot VIO key 3 3V 90 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg
76. er Supply gt 2 gt VME bus Level Supervisor 5V CPU core Power ALMA_V64 Supply Level Supervisor 32 bit PCI OR bit reset Front panel reset 64 bit PCI reset pushbutton AVIGNON CPC710 A p HRESET to CPUs P7 RISCWatch connector P8 RISCWatch connector Hard Reset CPUO and Hard Reset CPU1 from AVIGNON CPC710 are wired to each CPU through gates to accept Hard Reset from the P7 and P8 RISCWatch connectors respectively Except ALMA_V64 all devices wired to each PCI 32 bit or 64 bit are reset by the 32 bit PCI or 64 bit PCI reset issued from the AVIGNON CPC710 respectively 8 5 1 2 Soft Reset The soft reset causes for each processor to inconditionally branch to either 0x0100 or OxFFFO0100 depending on the state of the IP bit in the processor s Machine State Register The soft reset may be generated by An access to AVIGNON CPC710 register CPU Soft Reset Register e A remote soft reset from the RISCWatch connectors P7 and or P8 CPU Soft Reset register A OR CPUs P7 RISCWatch connector P8 RISCWatch connector CA DT 129 5e 56 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Operating Instructions 8 5 2 Machine Check Exception A machine check exception is initiated after an address or data parity error occured on the bus or in a cache after receiving a qualified tra
77. er s Manual for further information Thales Computers 67 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Functional Description 9 2 5 3 NVRAM RTC For maintenance of general system parameters such as environment variables and VME configuration the 8 KBytes of onboard NVRAM provides a convenient battery backed storage area The NVRAM and the Real Time Clock RTC are integrated on one M48T18 chip The RTC furnishes seconds minutes hours day date month and years in BCD 24 hour format Corrections for 28 29 leap year and 30 day months are made automatically Refer to the Programmer s Reference Guide and to the M48T18 data sheet for detailed programming and battery life information The battery and crystal are contained in a separate SNAPHAT housing to allow the user to replace remove and store it separately The SGS Thomson part number for replacement batteries is MAT28 BRI2SHI The Small Outline package provides sockets with gold plated contacts on both ends for the SNAPHAT housing The SNAPHAT battery package is mounted on top of the MT48T18 device The battery housing is keyed to prevent reverse insertion To avoid leakage discharge never store the SNAPHAT housing on a conductive surface such as dedicated anti static foam pad used for ESD sensitive devices It is possible to save the NVRAM content into the first system flash EPROM or res
78. errupt requests on VMEbus lines IRQx to IRQy Interrupter An interrupter generates an interrupt request on the VMEbus and then provides status ID information when requested by the interrupt handler Interrupt Handler ete RR a EEUEREURREERbs LEE a RAE RAE hbase An interrupt handler detects interrupt requests on the VMEbus generated by interrupters It acknowledges these requests with an IACK and responds to them by requesting Status ID information YO minis Input Output ISA Industry Standard Architecture Very commonly used bus in PC architectures ISO International Standards Organisation JEDEC Joint Electronic Devices Engineering Committee JTAG Joint Test Action Group A standard for chip level testing KBD Keyboard L1 Cache First level cache Integrated inside the processor L2 Cache Second level cache Often implemented outside the processor LED Light Emitting Diode A semiconductor diode that radiates light LEDs that emit in the visible region are used as indicators or warnings Little endian Refers to the way in which multi byte data is stored in memory Little endian data is stored with the least significant byte at the lowest address See also Big endian LSB Least Significant Bit Master A VMEbus master initiates bus cycles to transfer data between itself and a slave module MBIT Multiplexed BLock Transfer A data block transfer th
79. es peripherals systems cabling grounding VME and communications There is a glossary provided at the back of this guide that explains some of the terms used and expands all abbreviations 1 3 Scope This guide describes all variants of the VMPC6a It does not cover any daughter boards PMC modules or the carrier card which are described in specific guides see section 1 6 Related Documents 1 4 Structure This guide is structured in a way that will reflect the sequence of operations from receipt of the board up to getting it working in your system Each topic is covered in a separate chapter and each chapter begins with a brief introduction that tells you what the chapter contains In this way you can skip any chapters that are not applicable or with which you are already familiar The chapters are Q Chapter 1 this chapter gives a brief introduction this guide s objectives and audience the structure some warn ings conventions and related documentation Q Chapter 2 is a VMPC6a general information Chapter 3 contains unpacking inspection and identification instructions Q Chapter 4 describes the board configuration Q Chapter 5 describes the board s connectors and signals used Q Chapter 6 describes the mezzanine boards and PMC installation Q Chapter 7 describes installation of the board in a system Q Chapter 8 describes power up and subsequent operation of the board Q Chapter 9 is
80. es mechanical support for boards inserted into the backplane ensuring that the connectors mate properly and that adjacent boards do not touch each other It also guides the cooling airflow through the system and ensures that inserted boards do not disengage themselves from the backplane due to vibration or shock ESD Electrostatic Sensitive Device Ethernet Ethernet is a baseband thick wire network based on an access method called CSMA CD It was originally developed by the Xerox Corporation in 1972 FIFO First In First Out A data queuing mechanism or the implementation of it in which the first item stored is the first item processed CA DT 129 5e 100 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Glossary Flash Memory A IO R tos A type of high capacity E2PROM FPU Floating Point Unit FTP File Transfer Protocol See TCP IP GND The Ground 0V signal or supply rail Handler See Interrupt Handler I x y The interrupter can generate interrupt requests on VMEbus lines IRQx to IRQy IBM International Business Machines ICPMC Thales Computers 3 slot PMC carrier board ID es Identification IDSEL Device Number IEEE Institute of Electrical and Electronic Engineers IH x y The interrupt handler can generate interrupt acknowledge cycles in response to int
81. f appropriate A detailed description of the problem Any messages and error messages being generated What has been tried so far The software revision level hardware platform hardware revision and operating system level Other boards that you are using in the system with the VMPC6a If you are reporting a bug give detailed instructions on how to reproduce the problem and sample code if possible if the bug occurs in an application e Telephone and Fax Numbers Q USA Telephone Eastern region 19 1 617 494 0987 Fax Eastern region 19 1 617 494 8786 Telephone Western region 19 1 408 247 2430 Fax Western region 19 1 408 247 5132 Q France T l phone Customer support 33 4 98 16 34 15 Fax Customer support 33 4 98 16 34 22 Q UK Telephone 19 44 1604 497791 Fax 19 44 1604 497792 e E Mail Addresses supportOthalescomputers com OR support thalescomputers fr Thales Computers 97 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Troubleshooting CA DT 129 5e 98 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Glossary NOTE The VMEbus signals are detailed in chapter 5 A16 Providing or decoding addresses on VMEbus address lines A01 to A15 A2A Providing or decoding addresses on VMEbus address lines A01 to A23 A32 Providin
82. field is set to YES both simplified serial ports are available on the front panel connector and only simplified serial port 1 is available on the P2 connector Serial lines should only be used on one connector either on the front panel or P2 connector Connectors Lx Two simplified lines on front panel field is set to NO On the front panel through a 9 way micro D connector P4 full modem serial port 1 is available Refer to the pin assignment information about the SERIAL front panel connector in section 5 2 2 1 page 38 On the P2 connector serial ports 1 and 2 are available In this case channel 1 is restricted to 6 wires refer to the pin assignment information in section 5 1 5 page 24 Lx Two simplified lines on front panel field is set to YES On the front panel through a 9 way micro D connector P4 simplified serial ports 1 and 2 are available Refer to the pin assignment information about the SERIAL front panel connector in section 5 2 2 2 page 39 On the P2 connector simplified serial port 1 is only available Refer to the pin assignment information in section 5 1 5 page 24 Serial lines should only be used on one connector either on the front panel or P2 connector CA DT 129 5e 76 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Functional Description 9 2 11 Keyboard and Mouse Controller A Keyboard and Mouse interface is provided by the
83. g or decoding addresses on VMEbus address lines A01 to A31 AIX Advanced Interactive Executive from IBM UNIX AMD Advanced Micro Devices A chip manufacturer ANSI American National Standards Institute API Application Program Interface Arbiter An arbiter accepts requests and grants control to one requester at a time ARPA The US Defence Advanced Research Projects Agency ASCH American Standard Code for Information Interchange A 7 bit code established by ANSI to achieve compatibility between data services Equivalent to the international ISO 7 bit code ATM Asynchronous Transfer Mode AUI Attachment Unit Interface The cable that connects the DTE to the MAU Also called the Drop Cable Backplane VMEbDbus coso ds pope Ve ect aer ies dence A ee is os A PCB with 96 or 160 pin connectors and signal paths that bus the connected pins Some systems have a single PCB called the J1 backplane This provides the signal paths needed for basic operation Other systems also have a second PCB called the J2 backplane This provides the additional 96 or 160 pin connectors and signal paths needed for wider data and address transfers The J1 and J2 sections may be combined into a single J1 J2 backplane PCB BBSY Bus Busy on the VMEbus BCLR Bus Clear on the VMEbus BERR Bus ERRor on the VMEbus Big endian Refers to the way in which multi byte
84. ge Environment ides iia ibi 92 Thales Computers iii CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Table Of Contents A J Mechanical Construction vivi it es 93 Appendix B Troubleshooting eeeeeeeeeeeeeeee eh e hh hh hh nnn 95 Bal Step L No Power 2 2 4 499 ieee cet PREDGO GRE NEQOE IO d ded reni E eG ad 95 B 2 Step 2 Power On Unexpected Behaviour o oooocooococcocnoocrrororarncoraccnco noo 95 B 3 Step 3 Power On No Terminal Display 0 cece eee cece cere rh HH Hh hn 96 BA Step 4 Overheating 2 23 5 4 00 in ze 9a EE ED ERE UG da cat ETE c we 96 B 5 Step5 VMPC6a Locks up ccc ccc cc cece cere cree sh hh eh t nn 96 B 6 D bugging oii cick sical Oa dae RI I9 LIRE a e Re ad OR EERONEDEN RE A RET 96 B 7 When Phoning Faxing or E Mailing to Technical Support Be Prepared To Give 97 Glossary EO 99 Index 2cswcrekRXREERRRIEWER G RE X AV RRRC QE RENS RepRE TRAN PER RIRVEEREE RC ROREP EIE ERE 105 CA DT 129 5e iv Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Table Of Contents List Of Figures Figure 2 1 Top View of the VMPC6a o ooccocoocccc RR Ih eh 6 Figure 2 2 Auxiliary I O Connection 00 0 I ee 8 Figure 4 1 VMPC6a Link Positions 0 0 eee I I e 13 Figure 5 1 Connector Positions and Numbering
85. he table below 0 SCSI 1 Ethernet 2 ALMA_PCI_INTA 3 ALMA_PCI_INT1 4 ALMA_PCI_INT2 5 ALMA_PCI_INT3 6 PMC_INTA 7 PMC_INTB 8 PMC_INTC 9 PMC_INTD Thales Computers 57 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Operating Instructions 10 AVIGNON CPC710 1 11 NVRAM 12 Serial Channel 1 13 Serial Channel 2 14 Keyboard Mouse 15 User Flash amp Flash EPROM 16 AVIGNON CPC710 2 17 Temperature supervision 18 VME_IRQ1 19 VME_IRQ2 20 VME_IRQ3 21 VME_IRQ4 22 VME_IRQ5 23 VME_IRQ6 24 VME_IRQ7 25 Not Used 26 Not Used 27 CHECKSTOP CPUO 28 CHECKSTOP CPU1 29 VME ACFAIL 30 Machine Check CPUO 31 Machine Check CPU1 Table 8 1 External Interrupts INTEXT CA DT 129 5e 58 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Operating Instructions Example of Interrupt priorities and modes For the SCSI interrupt IINTEXTO the value in the corresponding COBRA Vector Priority register is 0x80410000 This means that this SCSI interrupt is masked bit 31 1 for the moment and that to unmask it bit 31 must be set to 0 is active on low level bit 22 1 has the priority level 1 low priority Refer to COBRA Reference Manual for more
86. iability The EMC qualifications EN55022 1998 A1 2000 EN61000 3 2 2000 EN61000 3 3 95 A1 2001 and EN61000 6 2 2001 of the VMPC6a are carried out on the level system and not on a board alone A 5 Flammability Rating All PCBs are manufactured by UL approved manufacturers and have a flammability rating of UL 94V 0 Thales Computers 91 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Specifications A 6 Environmental Specifications B The thermal and mechanical qualification are carried out by taking as reference the standard MIL STD 810 A 6 1 Operating Environment The VMPC6a will operate under the following conditions Temperature range Cooling requirement Relative humidity Altitude Thermal Shock Sinusoidal Vibration Random Vibration Mechanical shock 0 to 55 C ambient air temperature A linear airflow of not less than 1 2 m s across the board is recommended Up to 9096 without condensation from 1640 to 15000 feet 500 to 4572 meters approximatively 3 C per minute Displacement 1 25 mm peak from 5 Hz to 20 Hz Acceleration 2g peak from 20 Hz to 500 Hz Hz 10 40 100 200 2000 g Hz 0 01 0 01 0 0007 0 0007 0 00005 20 g for 11 ms half sine 6 directions 3 shocks direction when mounted in a suitable enclosure For operating environment exceeding the above specification ruggedized versions of VMPC6a board are NOTE available
87. ication number CA DT 118 Q ICPMC 6 Board Thales Computers PMC Carrier Board for VMPC6 Boards publication number CA DT 130 Q COBRA Interrupts and I O Controller Reference Manual publication number CI DT 405 NOTE The publication numbers of the AIX and LynxOS documentations are not listed because they depend on the AIX and LynxOS version distributed with your board Other Documentations Q VME64 Specification ANSI VITA 1 1994 Q VME64 Extensions ANSI VITA 1 1 1997 PCI Local Bus Specification Revision 2 2 december 18 1998 PCI Special Interest Group Q PCI System Design Guide Rev 1 0 9 93 PCI Special Interest Group Q PowerPC Reference Platform PReP Specification Version 1 1 IBM Q PowerPC Architecture Books I II III and IV Motorola Inc IBM Q MPC750 RISC Processor User s Manual Motorola Inc publication number MPC750UM AD Q SYM53C875 PCI SCSI I O Processor with UltraSCSI Data Manual Revision 2 0 Symbios Logic Inc Q Digital Semiconductor 21143 PCI CardBus 10 100 Mb s Ethernet LAN Controller Data Sheet Order Number EC QWC3B TE Q Digital Semiconductor 21143 PCI CardBus 10 100 Mb s Ethernet LAN Controller Hardware Reference Manual Order Number EC QWCAB TE Q CPC710 AVIGNON PowerPC chip support with dual PCI 32 64 Bridge amp SDRAM Controller IBM Q ALMA V64 PCI to VME Bridge Data Sheet IBM March 1998 Q IEEE P1386 Draft Standard for a Common Mezzanine Card Family CMC Q IEEE P1386 1 Draft Stan
88. ification This chapter gives guidelines on unpacking inspecting and identifying the VMPC6a CAUTION THIS PRODUCT IS CLASS 1 ELECTROSTATIC DISCHARGE SENSITIVE USE ESD PRECAUTIONARY MEASURES WHEN HANDLING IT 3 1 Unpacking Thales Computers boards are protected by an antistatic envelope Observe antistatic precautions and work at an approved antistatic work station when unpacking the board The VMPC 6a is shipped in an individual reusable shipping box When you receive the shipping container inspect it for any evidence of physical damage If the container is damaged request that the carrier s agent is present when the carton is opened Keep the contents and packing materials for the agent s inspection and notify Thales Computers customer service department of the incident Retain the packing list for reference Assuming that there is no obvious damage you may still want to keep the shipping carton in case you want to ship the VMPC a on elsewhere This package has been designed for shipping and it is not suitable for long term storage nor storage under VAN severe conditions Fore more information please visit our web site www thalescomputers com readfirst 3 2 Inspection Assuming that the VMPC6a is not obviously damaged you can now go on to inspect it It is possible for components connectors socketed chips etc to work loose or be dislodged in transit or in the process of unpacking although this is extremely unlikely
89. instructions Branches Q Dual 32 KB Instructions and Data non blocking caches Dual MMUs Q Hardware Tablewalk Q Double precision Floating Point Unique with multiply and add capability Q External L2 cache interface with integrated controller and cache tags 1 MB 2 way set associativity Also the PowerPC 750 has dynamic power management and is a low power static design Refer to the MOTOROLA MPC750 RISC Processor User s Manual reference MPC750UM AD for further information 9 2 3 Secondary Level Cache A 1 MB secondary level cache for each processor is available It is directly connected to each CPU through a high speed dedicated bus backside L2 The L2 cache data bus width is 64 bits Its operating frequency starts from 180 MHz and upwards Thales Computers 65 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Functional Description 9 2 4 PCI PCI has become a highly desirable local interface bus due to its high bandwidth glueless interface and low cost The VMPC6a has two PCI busses the first one for local interconnect of onboard devices Ethernet SCSI I O controller and VME64 all of which have direct PCI connectivity and the second one for communication with optional mezzanine expansion modules PMCs A wide range of PMCs are available from Thales Computers or through Third Parties including Thales Computers high performance graphics CPCIGx ac
90. is case don t take into account the pin assignment given above but refer to the P2 pin assignment in section 5 1 5 CA DT 129 5e 42 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 6 PMC Site Thales Computers standard PMC offering includes Graphics PMC ATM PMC ETHERNET PMC etc These PMCs are fully supported by the VMPC6a firmware located in the system flash EPROM By setting Environment variables the PMC site can operate at 33 MHz or 66 MHz with data width of 32 or 64 bits for more information refer to the VMPCBug Release Notes The VMPC6a onboard PMC site can be fitted with one PMC or with one Thales Computers ICPMC 6 PMC carrier which can host up to three PMC modules If a carrier board is used the PMC site will operate only at 33 MHz For EMC protection reasons when not used the PMC slots are fitted with a blanking plate 6 1 Information Needed The following table sums up all information concerning the PMC site needed for software and hardware configuration FUNCTION VALUE MEANING A PCI MEZZANINE _ Name given to the PMC on the front panel of the PMC Front Panel Designation CARD VMPC6a Jil Contain the signals for the 32 bit PCI bus J12 Contain the signals for the 32 bit PCI bus PMC Connectors J13 Contain the signals for the 64 bit PCI bus J14 Contain the User Defined I O signals By default the V I
91. is correctly inserted into the backplane connectors CAUTION THIS PRODUCT IS CLASS 1 ELECTROSTATIC DISCHARGE SENSITIVE USE ESD PRECAUTIONARY MEASURES WHEN HANDLING IT 7 1 System Backplane Configuration Before plugging the VMPC6a into a rack you should first check the rack s backplane configuration links Most of the VME backplanes now have an automatic daisy chain configuration for the Interrupt Acknowledge IACK daisy chain and the four Bus Grant BGx daisy Chains If your backplane does not provide the automatic daisy chain feature you could have to configure links on the backplane to ensure proper operations 7 2 Chassis Ground To ensure optimum operation of the VMPC6a with regard to EMC when using I O connections from the front panel connectors there should always be a connection from the front panel to the chassis ground of the system When using I O connections from P2 use the Thales Computers P2 accessory kits Thales Computers 47 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com System Installation 7 3 3 3V Power Recommendations Internal and PMC 3 3V power supplies are delivered by the VMPC6a from 5V supply The 3 3V voltage rise time must be monotonic and should not last for more than 25 ms 7 4 System Configuration Suggestions NOTE Check the P2 connections of the slot before powering up Use the VMPC6a in a rack on its own at firs
92. lear To Send not available in Two simplified lines on front panel 1 CTS mode m Channel 1 Data Terminal Ready not available in Two simplified lines on front S1 DTR panel mode x Channel 1 Data Carrier Detect not available in Two simplified lines on front 1 DCD panel mode x Channel 2 Transmit Data not available in Two simplified lines on front panel S2 TXD mode M Channel 2 Receive Data not available in Two simplified lines on front panel S2_RXD mode x Channel 2 Request To Send not available in Two simplified lines on front S2 RTS panel mode S2 RI Channel 2 Ring Indicator not available in Two simplified lines on front panel E mode 2 Channel 2 Clear To Send not available in Two simplified lines on front panel S2 CTS mode Channel2 Data Terminal Ready not available in Two simplified lines on front S2 DTR panel mode Channel 2 Data Carrier Detect not available in Two simplified lines on front S2 DCD panel mode Channel 2 Data Set Ready not available in Two simplified lines on front panel S2 DSR mode T i Ethernet transmit data available with Ethernet routed to backplane ransmit manufacturing option SCSI bus terminator power Supplies power for external SCSI bus TERMPWR terminators Fused at 1 Amp 5V 5 Volts DC power 5V Fused 5 Volts fused at 750 mA CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE
93. mperature 77 92 Troubleshooting 95 U Unpacking 11 USB Chip 60 User Flash See Links Memory V Vibration Random 92 Sinusoidal 92 VME Block Mode 69 Master BLT 69 Slot 67 VME to PCI Bridge See ALMA V64 Chip VMEO4A 1 5 7 66 89 VMEbus 1 3 5 7 56 67 95 Arbitration 70 89 Bridge 51 56 Compliance 69 89 Identification 70 82 86 88 Interface 69 Interrupt 70 Master Access 69 89 Master BLT 69 89 Signal Descriptions 22 Slave Access 69 89 Slave BLT 89 Slave Offset 86 Slave Windows 70 82 86 87 System Controller 70 89 VMPCBug See Debugging Monitor W Warnings 47 91 107 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Index CA DT 129 5e 108 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Corporate Headquarters 150 rue Marcelin Berthelot Zl Toulon Est BP 244 83078 Toulon Cedex 9 France Tel 33 0 4 98 16 34 OO Fax 33 0 4 98 16 34 01 International Sales Department 67 rue Charles de Gaulle 78350 Jouy en Josas France Tel 33 O 1 39 56 72 72 Fax 33 0 1 39 56 72 70 USA Headquarters 3100 Spring Forest Road Raleigh NC 27616 USA Tel 1 800 848 2330 1 919 231 8000 Fax 1 819 231 8001 United Kingdom Cornwell Business Park 31 Salthouse Road Brackmills
94. n Pin 3 oe oes Oe Om ome 9o 3 om open om om ono Opn 3 ew open om p om om ow s pom open om ew open Open 5 ew open om ono open ow s ew open om ono om Opn 7 em open om ono o ow s Dom open oo Dom om Onn 5 ew open e pom om ow ow ew open co om Nb Open on pom open cx Dom oxo ow m ew open ow ew open om m pom e ew p ew om ow ow Dom open ow p ew omo Opn s ew we o ew oxo ow 16 Dom on oven om Om Om v ew ew oven om om Ow sw ew ew oven p om oxo Opn o om ew f om om oxo ow o ew ew oven ow open om a oven ano ow and om aw The device that samples the levels of the geographical address pins will read the inverted value of the slot number into which the board is plugged When the board is plugged into a VME VME64 backplane i e not VME64x the slot number will be zero with a parity error GAP open Thales Computers 21 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Connectors 5 1 4 VMEbus Signal Description The VMEbus signals occupy rows a b and c of the P1 connector and row b of the P2 connector Mnemonic Signal Description Address Bus bits 1 to 15 Address lines that are used to broadcast a short standard or A01 to A15 extended address Address Bus bits 16 to 23
95. ncluding without limitation consequential or incidental damages Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by customer s technical experts Thales Computers does not convey any license under its patent rights nor the rights others Thales Computers products are not designed intended or authorized for use as components in systems intended for surgical implant into body or other applications intended to support or sustain life or for any other application in which the failure of the Thales Computers product could create a situation where personal injury or death may occur Should Buyer purchase or use Thales Computers products for any such unintended or unauthorized application Buyer shall indemnify and hold Thales Computers and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Thales Computers was negligent regarding the design or manufacture of the part Restricted Rights Legend Use duplication or disclosure by the contractor or the Government is subject to restrictions as set forth in subdivision b 3 ii of the Rights in Technical Data and Computer Software clause 52 227
96. nection since COBRA is a slave only device Except ALMA V64 the other devices are reset by the 32 bit PCI reset issued from the host bridge refer to section 8 5 1 1 Hard Reset CA DT 129 5e 60 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Operating Instructions 8 7 64 bit PCI Configuration The 64 bit PCI bridge function inside the host bridge is responsible for executing load and store operations from the CPU to the 64 bit PCI bus Also the PCI bridge logic provides an interface for PCI devices to access system memory To generate a configuration cycle to PCI refer to the CPC710 User s Manual The following table describes the physical connections for each of the PCI devices on the host bridge HOST BRIDGE SIGNALS ARB Level Device Number VMPC6a Device REQ GNTO PMC REQ GNT1 No device connected REQ GNT 2 No device connected Table 8 3 Devices connected to the 64 bit PCI bus All devices are reset by the 64 bit PCI reset issued from the host bridge refer to section 8 5 1 1 Hard Reset See Chapter 6 page 43 for the PCI slot position and the PMC Configurations section in the ICPMC 6 user s guide Thales Computers 61 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Operating Instructions CA DT 129 5e 62 Thales Compu
97. ng data 8 bits at a time over DOO to D07 or D08 to D15 on the VMEbus D08 O Sending and receiving data or Status ID 8 bits at a time over DOO to D07 on the VMEbus Daisy Chain A signal line that propagates a signal from board to board or chip to chip starting with the first slot and ending at the last slot There are 4 VMEbus grant daisy chains and one VMEbus interrupt acknowledge daisy chain DC uem Direct Current DCD Data Carrier Detect A serial signal DMA Direct Memory Access A direct rapid link between a peripheral and main memory that avoids the use of the processor to transfer each item of data DRAM Dynamic RAM Memory that must be refreshed periodically to maintain the storage of information DSR Data Set Ready A serial signal DTE Data Terminal Equipment The data terminal devices themselves A category that includes the computer DTR cc Data Terminal Ready A serial signal D type A connector that has the approximate shape of a capital letter D E PROM or EEPROM sind di Electrically Erasable PROM PROM whose contents can be erased electrically so allowing the device to be re used with new data ECC sa Error Correcting Code The data is protected by Error Correction Coding capable to detecting all single bit and double bit errors and correcting single bit errors EMC Electro Magnetic Compatibility Enclosure A rigid framework that provid
98. nment variable will be lost at next firmware boot unless another NVRAM saving command is provided In this case a warning message is displayed on the console If a NVRAM backup exists in the system flash the NVRAM contents are restored at each firmware boot i e power on or reset For further information about saving and restoring the NVRAM contents refer to the VMPCBug User s Manual ENV C gt Cancel the NVRAM backup into the first system flash COMMAND gt ENV C CA DT 129 5e 88 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix A Specifications This appendix gives a specification of the VMPC6a It also covers items such as power requirements environment specifications etc A 1 VMEbus Compliance The VMPC6a conforms to VME64 Extensions ANSI VITA 1 1 1997 standard Master Slave e Interrupt Handler Interrupter VMEbus Arbiter VMEbus Requester e Bus Time out Module e Other features e System Controller functions Thales Computers A16 A24 and A32 D08 EO D16 D16 UAT D32 D32 BLT D32 UAT D64MBLT A16 A24 and A32 8 programmable channels D08 EO D08 EO RMW indivisibility with local processor accesses is not guaranteed D16 D16 RMW D16 UAT D32 D32 RMW D32 BLT D32 UAT D64MBLT D08 O IH 1 7 I 1 7 RRS PRI fixed arbitration time out of 8 ms BCLR generation R
99. note that if you plan to use the ICPMC 6 PMC carrier card the VMPC6a onboard PMC slot will not be available A and you must fit PMCs onto the ICPMC 6 By setting Environment variables the PMC site can operate at 33 MHz or 66 MHz with data width of 32 or 64 bits for more information refer to the VMPCBug Release Notes Prior to fitting your own PMC module you should remove the blanking plate from the appropriate slot The module s bezel will fill the slot and will usually provide connection to the module PMC modules are delivered with a full kit of parts for mounting them and the user guide for the module normally contains instructions on how to fit the module For more information about the PMC installation refer to the Connection Guide 5V keying pin 3 3V key position 5V Key hole Mounting points Bezel Thales Computers 45 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com PMC Site CA DT 129 5e 46 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 7 System Installation This chapter describes the installation of the VMPC6a board in a system WARNING Only use the VMPC6a in backplanes that supply power on both P1 and P2 connectors Failure to observe this warning may result in damage to the board WARNING Ensure that your VMPC6a
100. nsfer error acknowledge TEA indication on the CPU bus or after the machine check interrupt MCP signal has been asserted The MCPO0 and MCPI outputs of the AVIGNON CPC710 host bridge then the external interrupts INTEXT 30 and INTEXT 31 of the COBRA I O controller are connected to the Machine Check input of the CPUO and CPUI respectively The AVIGNON CPC710 host bridge generates a checkstop to each CPU if the following errors are detected e Address parity error detected on the CPU system bus if enabled e Data parity error detected on the CPU system bus if enabled e Internal timeout due to no response from slave on load For more information refer to the Programmer s Reference Guide 8 5 3 External Interrupt INT The INTb 0 and INTb 1 outputs of the COBRA I O controller are connected to the INT input of the CPUO and CPU1 respectively 8 5 4 System Management Interrupt SMI The INTb 2 and INTb 3 outputs from the COBRA I O controller are connected to the System Management Interrupt SMI pin of the CPUO and CPUI respectively to support high priority interrupts 8 5 5 External Device Interrupts INTEXT The COBRA I O controller handles the interrupt from external devices There are up to 32 external interrupts INTEXTO to INTEXT31 These external interrupts are connected to the INTb 0 and INTb 1 outputs of the COBRA I O controller The external interrupt corresponding to each source is described in t
101. ntroller e VMPC6a identification on the VME bus Each SBC in a rack must have an unique identification on the VME bus This ID depends on the board number into the VME rack and is used to calculate two VME base addresses to reach the PCI VME bridge internal registers and the VMPC6a SDRAM respectively This environment variable named VME BOARD ID is stored in the serial access EEPROM and copied to the NVRAM memory by the firmware each time an operating system boot command is used By using the CONF debugging monitor command this VME BOARD ID can be determined either manually or automatically by selecting the VME autoslotid option VME Autoslotid needs VME A16 slave window opens if this slave window is closed VME autoslotid is automatically disabled Refer to the section 10 2 2 CONF Command page 82 or the VMPCBug User s Manual for more details about the configuration of these values e VMPC 6a geographical addressing In addition to the BOARD ID reflecting the VMPC6a numbering in the chassis the VME geographical address of the board on the chassis i e its VME slot position can be read from an ALMA V64 VME bridge register after a power on reset For more information about this register refer to the Programmer s Reference Guide The VME geographical address is stored in the serial access EEPROM and copied to the NVRAM memory in the GEO ID environment variable by the firmware at each firmware start up
102. ntron com THALES COMPUTERS Where COTS Meets Reality VMPCGa or VMPC6a Dual PowerPC VME64 Boards User s Guide CA DT 129 5e June 2003 www thalescomputers com T H AN L E c Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com THALES COMPUTERS Thales Computers The Ruggedizer UNI RT and POWERENGINE are registered trademarks of Thales Computers S A PowerPC AIX AlXwindows RISC System 6000 IBM are registered trademarks of IBM Corp Linux is a registered trademark of Linus Torwards Red Hat is a registered trademark of Red Hat Inc LynxOS is a registered trademark of LynuxWorks Inc TORNADO and VxWorks are registered trademarks of Wind River System Inc UNIX is a registered trademark licensed exclusively by X Open Company Limited All other product names trademarks and registered trademark are the property of their respective holders Copyright Thales Computers 1987 2003 FO Lynx05S UA LTH one ve WIND RIVER amp Omn nus 1 o H Thales Computers reserves the right to make changes further notice to any products herein Thales Computers makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Thales Computers assume any liability arising out of the application or user of any product or circuit and specifically disclaims any and all liability i
103. ocessor O JTAG Test Mode Select TMS1 Processor 1 JTAG Test Mode Select TRSTO Processor O JTAG Test Reset TRST1 Processor 1 JTAG Test Reset 3 3V Thales Computers Power on status signal to RISCWatch hardware 35 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Connectors 5 2 Front Panel Connectors JANYAHLA y QYVO 3NINVZZAW Id Figure 5 2 VMPC6a Front Panel NOTE The cables and connectors which can be connected to the front panel connectors are described in the Connection Guide This guide gives the Thales Computers cable references and shows the different available connections CA DT 129 5e 36 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Connectors 5 2 1 P3 Keyboard and Mouse Connector KBD MS The Keyboard Mouse interface shares an USB type socket connector that has the following pin assignment Pin Signal 5V Fused KBD MS DATA DATAS Pin 1 Pin 4 4 GND CASE M GND _ Signal Description DATA Differential data pair 5V Fused 5 Volts Fused at 750 mA GND Logical Ground M GND Case Ground Chassis Ground Thales Computers 37 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 S
104. ogy Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Operating Instructions FFFF FFFF _ PROGRAMMABLE REGISTERS User Flash 32 bit PCI PCI32 MSIZE MEMORY 512MB PC1I32 SMBAR 90008 Reserved 512 MB RISA 32 bit PCI I O 512 MB PCI32 IOSIZE PCI32 SIBAR ELL e Reserved 256 MB 64 bit PCIVO PCI64 IOSIZE 256 MB PC1I64 SIBAR 64 bit PCI PCI64 MSIZE 4 MEMORY 512MB 4000 0000 PCI64 SMBAR gt CPU ADDRESS CA DT 129 5e Onboard chips PMC etc External chips 32 bit PCI MEMORY VO MEMORY _ 32 bit PCI BUS BRIDGE 52 64 bit PCI T O e e EN 64 bit PCI MEMORY T O MEMORY 64 bit PCI BUS BRIDGE Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Operating Instructions 8 4 1 Example of Memory Map Seen by the Processor Processor Address Range 00000000 3FFFFFFF Size Range 1GB PCI Address Range No PCI cycle Cycle Type System memory space 40000000 5FFFFFFF 512MB 00000000 to 1FFFFFFF 64 bit PCI Memory space 60000000 6FFFFFFF 256MB 00000000 to OFFFFFFF 64 bit PCI I O space 70000000 7FFFFFFF 256MB Reserved Reserved 80000000 9FFFFFFF 512MB 00000000 to 1FFFFFFF Reduced ISA 32 bit
105. ork Layer Protocols ISO Level 3 IP Provides internet transaction services for Layer 4 clients Generally considered as providing Host to Host datagram delivery Transport Layer Protocols ISO Layer 4 TCP A connection oriented reliable byte stream protocol UDP An unacknowledged transaction oriented protocol parallel to TCP Session Presentation and Application Layer Protocols ISO Layers 5 to 7 FTP Permits exchange of complete files between computers Telnet Provides virtual terminal services for interactive access by terminal servers to hosts Telnet The ARPA application level protocol A bi directional byte oriented communications protocol See TCP IP Timeout The elapsing of a period of time within which an action should have happened TSOP Thin Small Outline Package m The U is a standard unit of height measurement e g 3U One U is 4 445 centimetres 1 75 inches UAT Unaligned Address Transfer A VMEbus data transfer cycle that sends or receives data in an unaligned fashion USB Universal Serial Bus UDP User Datagram Protocol See TCP IP NCC The five volt supply rail VITA VMEbus International Trade Association VME Versa Module Europe Often used as an abbreviation for VMEbus VMEbus AnANSVIEEE standard 1014 1987 for a versatile backplane bus based on the Eurocard mechanical standard Thales Computers 103 CA DT 129 5e Artisan Technology
106. rface ALMA V64 PCI to VME bridge VME64 master slave capability Full VME system controller and interrupt generator handler capability Flexible address mapping Two DMA channels Hardware semaphores for multiprocessing e Manufacturing option User Flash sizes 8 or 32 MB SDRAM size 64 128 256 or 512 MB W I O PMC 3 3 V for the PCI PMC slot Ethernet routed to backplane PO connector available Single slot GU VME64x board e ANSI VITA 1 1994 VME64 compliant e ANSI VITA 1 1 1997 VME64 Extensions Thales Computers 7 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com General Information 2 3 Inputs Outputs The VMPC6a has a wide variety of possible I O connectivity including Wide Ultra SCSI Ethernet serial and mouse keyboard ports The front panel can provide one keyboard and mouse port one 10 100BASE T Ethernet port and one SCSI 3 port In addition a firmware configuration enables to select either one RS232 serial I O channel on one connector or both RS232 serial I O channels on the same connector for more information about this configuration refer to section 10 2 2 page 82 For more information about the pin assignment of the front panel connectors refer to section 5 2 page 36 The VMPC6a P2 connector can provide Local I Os Ultra or Wide Ultra SCSI asynchronous serial lines and mouse keyboard ports and
107. ription o ooooooooorror ee 35 5 2 Front Panel Connectors csse io rere RE e Rer a ERR gene EE EE 36 5 2 1 P3 Keyboard and Mouse Connector KBD MS 0 cece ene 37 5 22 P4 Serial Connector SERIAL o o ooooooooo hr n 38 5 2 2 1 SERIAL Connector with One Full Modem Serial Channel eese 38 5 2 2 2 SERIAL Connector with Two Simplified Serial Channels celles 39 5 2 3 PS SCSI 3 Connector SCSI 00 nen enn e beeen ene nee 40 5 2 4 P6 ETHERNET 10BASE T 100BASE T Connector ETHERNET 00000000 42 Chapter 6 PMC Site srt rry eet renti oen PR CYRUS so ears ai oasis Inca e 43 6 1 Information Needed oooooooooccocccccccccccccccao ehh 43 6 2 Voltage Keying Pins 5 1 A A TE EE S E E E E 44 63 PMC Installation osos coge eo hy ht sos Sie Ni GON NS GLOW Ee CER E Ve 45 Chapter 7 System Installation eeeeeeeeeeeeeeee hh hh hh htm nn 47 7 4 System Backplane Configuration 0 ccc cece cece cece eee hh hh hh hn n n n n 47 7 3 Chassis Ground como e626 6 eoe c ehe dne rhy e 47 7 3 3 3V Power Recommendations 0 c cece cece eect ence eee ehh nnn 48 7 4 System Configuration Suggestions cc cece cee reece cece ehh hh hh n nnn 48 Chapter 8 Operating Instructions 0 eee cece cece cece ce ehh hh hn 49 Sl Power up 230 ira A A eaves GNE A Aa 49 3 2 Reset Switch 42i ose eec eer a aa 49 83 EDS 5425232329 999 3 2 4 R3 E rna
108. running at 33 or 66 MHz To run at 66 MHz two requirements should be met only one PMC connected to the host bridge and this PMC must be able to operate such a rate Section 8 7 page 61 describes the physical connection for each of these PCI devices to the host bridge The 64 bit PCI bus structure of the VMPC6a is shown in the block diagram page 64 and in section 9 2 4 CA DT 129 5e 66 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Functional Description 9 2 4 3 PCI Carrier Card One PMC slot is provided as standard on the VMPC6a For those configurations that require additional PCI PMC slots a PMC Carrier Card ICPMC 6 allows three PMC modules to be fitted in an adjacent VMEbus slot Applications requiring up to three PCI slots can therefore easily be built The following table shows the number of PMC slots available with without the carrier board ICPMC 6 For more information about the ICPMC 6 carrier board refer to ICPMC 6 Board User s Guide Carrier Board PMC Slots Available VME Slots Absent 1 1 Present 3 2 9 2 5 Memory 9 2 5 1 SDRAM Between 64 and 512 MBytes of system memory is available Up to 512 MBytes of synchronous DRAM can be fitted directly to the main board using 256 Mbit devices in two interleaved banks of 64 bit wide SDRAM controlled by the AVIGNON CPC710 host bridge This SDRAM runs at 100 MHz and upwards The
109. s refer to section 5 1 8 page 31 CA DT 129 5e 18 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Connectors Row a Signal D00 D01 D02 D03 D04 D05 D06 D07 GND SYSCLK GND DS1 DS0 WRITE GND DTACK GND AS GND IACK IACKIN IACKOUT AM4 A07 A06 A05 A04 A03 A02 A01 12Vt 5V P1 Connector Row b Signal BBSY BCLR ACFAIL BGOIN BGOOUT BG1IN BG10UT BG2IN BG20UT BG3IN BG30UT BRO BR1 BR2 BR3 AMO AM1 AM2 AM3 GND N C N C GND IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 N C 45V Row c Signal D08 D09 D10 D11 D12 D13 D14 D15 GND SYSFAIL BERR SYSRESET LWORD AM5 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A09 A08 12Vt 5V P1 and P2 Row B VMEbus Connector Pin Assignment 5V GND N C N C N C N C N C N C GAP t GAO0 t GA1 t 3 3Vt GA2 3 3Vt GA3 43 3Vt GA4 t 3 3Vt N C 3 3Vt N C 3 3Vt N C 3 3Vt N C 3 3Vt N C 3 3Vt N C 3 3Vt GND 5V Row d Signal P2 Row b Signal 5V GND RETRY A24 A25 A26 A27 A28 A29 A30 A31 GND 5V D16 D17 D18 D19 D20 D21 D22 D23 GND D24 D25 D26 D27 D28 D29 D30 D31 GND 5V 5 1 2 P namer Row z Signal 1 N C 2 GND 3 N C 4 GND 5 N C 6 GND 7 N C 8 GND No 10 GND 11 N C 12 GND 13 N C 14 G
110. s initialization of the TAP controller Target Ready Driven low by the current target to signal its ability to complete TRDY the current data phase Power supply delivered by the board In standard on the PMC connectors 5 V 1 0 Volt power is supplied With the PMC slot VIO Key 3 3V manufacturing option 3 3Volt power is supplied Contact Thales Computers 3 3V 3 3 Volts DC power 5V 5 Volts DC power 12V 12 Volts DC power 12V 12 Volts DC power Page 2 of 2 CA DT 129 5e 32 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Connectors 5 1 9 P7CPUO RISCWatch Connector Pin Assignment This connector allows the connection of software debugging tools that use the CPUO s RISCWatch port to control the operation of the processor 0 The pin assignment is as follows Pin Signal 1 TDOO 2 Reserved 3 TDIO 4 TRSTO 5 PD1 6 3 3V 7 TCKO 8 Reserved 9 TMSO 10 Reserved 11 SRESETO 12 P_TCK 13 HRESETO 14 Reserved 15 CHECKSTOPO 16 Ground 0V Signals active when low Thales Computers 33 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Connectors 5 1 10 P8 CPU1 RISCWatch Connector Pin Assignment This connector allows the connection of software debugging tools that use the CPU1 s RISCWatch port to control th
111. santg com Connectors 5 2 2 2 SERIAL Connector with Two Simplified Serial Channels When the Two simplified lines on front panel field is set to YES this 9 way micro D type plug connector provides both simplified serial channels 1 and 2 It has the following pin assignment 1 Reserved 6 S2_RXD S E R AL 2 S1 RXD 7 Reserved 3 S1 TXD 8 Reserved 4 S2 TXD 9 Reserved 5 Serial Ground Shell Chassis Ground Signals active when low Signal Description Mnemonic Description Reserved Do not use this pin Sx RXD Channel 1 or 2 Receive Data Sx TXD Channel 1 or 2 Transmit Data Serial Ground Quiet ground internally connected to OV Thales Computers 239 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Connectors 5 2 3 P5 SCSI 3 Connector SCSI This 68 way SCSI 3 socket connector provides the SCSI 3 16 bit bus The pin assignment is as follows 16 GND 50 GND SCSI 17 TERMPWR 51 TERMPWR 15 GND 49 GND 18 TERMPWR 52 TERMPWR S M 19 N C 53 N C 20 GND 54 GND 21 GND 55 ATN 22 GND 56 GND 23 GND 57 BSY 24 GND 58 ACK 25 GND 59 RST 26 GND 60 MSG 27 GND 61 SEL 28 GND 62 C D 29 GND 63 REQ 30 GND 64 1 0 31 GND 65 DB8 32 GND 66 DB9 33 GND 67 DB10 34 GND 68 D11 i Signals active when low CA DT 129 5e 40 Thales Computers Artisan Technology Group Quality Instrumentation
112. simple instructions that execute very quickly i e in one cycle This means that programs are longer in size and sometimes more complicated but run faster Read Modify Write An indivisible VMEbus cycle that is used to both read from and write to a slave without permitting any other master to access that slave during the cycle This is most useful in multiprocessing systems where certain memory locations are used to control access to certain resources e g semaphores Release NEver A bus release mode that applies to VMEbus Release On Clear A bus release mode that applies to VMEbus Read Only Memory Semiconductor memory whose components are not alterable by computer instructions and power off Release On Request An access scheme in which the VMEbus requester only relinquishes control of the bus when it is required by another requester This has an advantage over the RWD scheme in that if no other master uses the bus the bus request phase of a transfer is avoided Round Robin Select Round robin is a VMEbus arbitration scheme for resources in which resource bandwidth is shared equally between competing requests of different levels A requester that is granted a resource on one arbitration cycle has the lowest priority on the next arbitration cycle The normal serial interface found in most PCs and terminals It usually uses a 9 or 25 pin connector Ready To Send A serial signal See CTS Real Time Clock Small Computer Systems
113. t Check that all connections are tight Check that the terminal is receiving power and is on Check that the terminal is set up for DTE 9 6 Kbaud 8 bits character 1 stop bit parity disabled data leads only If a CPCIGx or a CPMC GTX 8 graphics controller is in a PMC slot it will be providing console output If an USB keyboard is connected it will be providing console input B 4 Step 4 Overheating Check that no grilles are blocked in the chassis either internally or externally Check that the fans are working Clean or replace any air filters fitted to fans Check that there is a free air flow around the chassis exterior i e it should not be in an alcove or other confined space or on thick pile carpet Check that the enclosure is not next to a radiator or other heat source B 5 Step 5 VMPC6a Locks up Ensure that your VMPC6a is correctly inserted into the backplane connectors Remove your board and re plug it Try resetting the VMPC6a or powering the system down and then up again B 6 Debugging When debugging software disable the caches to make tracing the software execution easier CA DT 129 5e 96 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Troubleshooting B 7 When Phoning Faxing or E Mailing to Technical Sup port Be Prepared To Give Your name work address work telephone and fax numbers and e mail address i
114. t and only plug it in with other cards later if other cards are to be used This enables you to try basic operation before tackling any system configuration issues To interact with the VMPC6a debugging monitor you need to attach a terminal to the VMPC6a By default this terminal will use the serial port 1 signals either on the SERIAL front panel connector or P2 To select serial port 2 on P2 as standard TTY port use the CONF M monitor command for more information about the CONF command refer to section 10 2 2 page 82 Alternatively a graphics PMC module CPCIGx and an USB compatible keyboard may be used If these devices are used the firmware detects their presence and uses them automatically Both serial interfaces SERIAL 1 and SERIAL 2 are configured as DTE 9 6 Kbaud 8 bits character 1 stop bit parity disabled However cables optionally supplied by Thales Computers permit direct connection to a terminal without use of a null modem cable for more information about the VMPC6a connections refer to the Connection Guide See section 9 2 9 page 74 for considerations to be taken into account when using the SCSI bus CA DT 129 5e 48 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 8 Operating Instructions This chapter describes power up procedure descriptions of the RESET switch and LEDs memory maps and software initialization of the VMPC6
115. ted after a reset and released when the board reset selftests are passed successfully SYSRESET System Reset When this signal is low it causes the system to be reset RETRY This signal is not used WRITE Write This signal is generated by a master to show whether the data transfer cycle is a read or a write 3 3V 3 3 Volts DC power These supply pins are not used by the VMPC6x board 5V 5 Volts DC power 12V 12 Volts DC power Not used by the VMPC6a except to supply 12V to the PMC slot 12V 12 Volts DC power Not used by the VMPC6a except to supply 12V to the PMC slot Thales Computers Page 2 of 2 93 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CA DT 129 5e Connectors 5 1 5 P2 Connector Pin Assignment Pin Number Rowz Signal Row a Signal Row b Signal Row c Signal Row d Signal 1 PMC IO 02 DBO SCSI 45V GND PMC IO 01 2 GND DB1 SCSI GND Transmit Ethernet PMC IO 03 3 PMC IO 05 DB2 SCSI RETRY Transmit Ethernet PMC IO 04 4 GND DB3 SCSI A24 GND PMC IO 06 5 PMC IO 08 DB4 SCSI A25 Receive Ethernet PMC IO 07 6 GND DB5 SCSI A26 Receive Ethernet PMC IO 09 7 PMC IO 11 DB6 SCSI A27 GND PMC IO 10 8 GND DB7 SCSI A28 N C PMC IO 12 9 PMC IO 14 DBPO SCSI A29 DB8 SCSI PMC IO 13 10 GND ATN SCSI A30 DB9 SCSI PMC IO 15 11 PMC IO 17 BSY SCSI A31 DB10 SCSI PMC IO 16 12 GND ACK SCSI GND DB11 SCS
116. ted from a PCI burst The use of internal FIFOs allows maximum speed in decoupled mode Read Ahead or Write Posting In the same way since the PCI bus is faster than the VME bus even a suite of single PCI write transfers can be translated into VME D32BLT BB2BLT mode 9 2 6 2 VMEbus Slave Access The VME slave interface supports the same addressing mode and data size as the VME master interface Eight decoding channels are available for accessing the PCI bus from the VME bus Each channel is independently configurable in the A32 A24 or A16 address space These channels allow the user to program the PCI bus access parameters with a minimum granularity of IMB Thales Computers 69 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Functional Description 9 2 6 3 VMEbus Arbitration VME bus requester The VME PCI bridge drives the bus requests on one of the four levels BRO to BR3 and the release of the bus can be managed with ROR Release On Request ROC Release On Clear or RNE Release NEver policy In addition a FAIR requester policy can be programmed to better share the VME bus bandwidth for configuration with many VME slots populated e VME System Controller The VMPC6a board is VME system controller when the board is fitted in slot 0 or if it is the first board of the bus grant daisy chain The system controller mode is automatically detected Auto System Co
117. ters Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 9 Functional Description This chapter describes the VMPC6a board at a block diagram level The general description provides an overview of the VMPC6a followed by a detailed description of several blocks of circuitry Detailed descriptions of other VMPC6a blocks including programmable registers in the AVIGNON CPC710 COBRA and peripheral chips can be found in the Programmer s Reference Guide Thales Computers 63 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Functional Description 9 1 VMPC6a Block Diagram PO a VME64 Interface P1 y 32 Hits ofthe i VMEbus P2 64 bit PCI bus ALMA_V64 p xininai aria on aua ici ii VME64 PMC connectors Interface ii ia ur a AVIGNON CPC710 COBRA Host Bridge Interrupt and I O SEAT Controller Iw B PPC 750 PPC 750 onboard 450 MHz 450 MHz 1 5 MB of SDRAM or more or more FLASH up System up to 512 MB ial Kb M SCSI Ethernet o Adaptor Adaptor 1MB of 1MB of L2 cache L2 cache RST SCSI ETHERNET PCISLOT a KEYBOARD MOUSE Legend Optional CA DT 129 5e 64 Figure 9 1 VMPC6a Block Diagram Thales Computers Artisan Technology Group Qu
118. th low and high bits This management is made either through the debugging monitor see section 10 2 2 CONF Command page 82 or by programming the COBRA GPIO 30 31 refer to the Programmer s Reference Guide CA DT 129 5e 74 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Functional Description Connectors Connection to the SCSI bus is made through a 68 way SCSI 3 socket connector P5 on the front panel refer to the P5 pin assignment information in section 5 2 3 page 40 and or the P2 connector refer to the P2 pin assignment information in section 5 1 5 page 24 For more information about the enabled SCSI connections refer to section SCSI Connections in the Connection Guide L LED A software programmable SCSI Activity LED SCSI is mounted on the bottom side of the board behind the front panel see section 8 3 page 50 The default function of this LED is to indicate that the SCSI bus is active The state of this LED can be handled by the SCSI General Purpose Register refer to the Programmer s Reference Guide and to the SYM53C875 PCI SCSI I O Processor with UltraSCSI Data Manual Thales Computers 75 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Functional Description 9 2 10 Serial I O Controller Two RS 232C asynchronous serial channels are available on the
119. tore the NVRAM backup For that use the ENV debugging command and set the LK2 link see section 4 2 page 15 For example this is useful when no NVRAM battery is fitted For further information about saving and restoring the NVRAM content refer to section 10 2 4 ENV Command page 87 and the VMPCBug User s Manual The NVRAM mapping reserved for the debugging monitor and the self tests is 0 to 4 KB reserved for the debugging monitor VMPCBug SKB 256 10 to 8KB reserved for the self tests For more information about the NVRAM mapping refer to the Programmer s Reference Guide 9 2 5 4 User Flash EPROM The size of the user Flash EPROM available on the VMPC6a board is from 4 to 32 MBytes This user Flash EPROM is made of high performance 64 Mbit devices which feature block erasable nonvolatile random access memory organized as 8 MBytes x 8 a minimum of 100 000 writing and erasing cycles can be performed on each block two page buffers are incorporated to allow page data programs These devices are mapped beyond the COBRA I O controller as PCI devices with a dedicated base address register Refer to the Programmer s Reference Guide for detailed programming Link LK3 when set see section 4 3 page 16 enables writing and erasing operations to the User Flash EPROM which are not otherwise possible For further information about reading writing and erasing operations on User Flash EPROM refer
120. tware refer to the Programmer s Reference Guide the 21143 data sheet or the 21143 Hardware Reference Manual Thales Computers 73 CA DT 129 5e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Functional Description 9 2 9 SCSI Controller The SCSI interface is implemented using the SYM53C875A PCI SCSI I O Processor with UltraSCSI controller at a clock speed of 80 MHz This controller performs Ultra or Wide Ultra SCSI transfers in single ended mode It supports transfer rates up to Q 40 MB s in Wide Ultra SCSI mode Q 20 MB s in Ultra or Fast Wide SCSI mode Q 10 MB s in Fast SCSI mode PCI Master and Slave Control Block External Memory Memory Data SCSI Operating Config SCRIPT FIFO Scripts Control 536 Bytes Processor Registers Registers RAM Local SCSI FIFO and SCSI Control Block Memory Bus olerANT Drivers and Receiver SCSI Bus Figure 9 6 SCSI Controller Block Diagram SCSI Terminators The VMPC6a has onboard active SCSI terminators which may be enabled or disabled by software These SCSI terminators are divided in two parts 8 low bits connected to low SCSI terminators which are controlled by the COBRA GPIO 30 8 high bits connected to high SCSI terminators which are controlled by the COBRA GPIO 31 8 bit SCSI devices use low order bits only while 16 bit SCSI devices use bo
121. umentation Guaranteed 888 88 SOURCE www artisantg com Connectors 5 1 7 4 J14 PMC Connector Pin Assignment 1 PMC IO 01 PMC IO 03 3 5 PMC IO 05 7 PMC IO 07 9 PMC IO 09 11 PMC IO 11 13 PMC IO 13 15 PMC IO 15 17 PMC IO 17 19 PMC IO 19 21 PMC IO 21 28 PMCIO23 25 PMCIO25 27 PMCIO27 29 PMCIO 29 31 PMC IO 31 33 PMCIO33 35 PMCIO35 37 PMCIO 37 39 PMCIO39 41 PMCIO 41 43 PMCIO 43 45 PMCIO 45 47 N C 49 N C 51 N C 53 N C 55 N C 57 N C 59 N C 61 N C 63 N C PMC IO 02 PMC IO 04 PMC IO 06 PMC IO 08 PMC IO 10 PMC IO 12 PMC IO 14 PMC IO 16 PMC IO 18 PMC IO 20 PMC IO 22 PMC IO 24 PMC IO 26 PMC IO 28 PMC IO 30 PMC IO 32 PMC IO 34 PMC IO 36 PMC IO 38 PMC IO 40 PMC IO 42 PMC IO 44 PMC IO 46 N C N C N C N C N C N C N C N C N C CA DT 129 5e 30 Thales Computers Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Connectors 5 1 8 PMC Signal Description Mnemonic Description ADO to AD63 Address Data bits Multiplexed address and data bus AD32 to AD63 are specifics to 64 bit bus extension ACK64 Acknowledge 64 bit Transfer Driven low by the device to indicate that the target is willing to transfer data using 64 bits BUSMODE 1 Bus Mode 1 Driven low by a PMC module to indicate that it supports the current bus mode
122. ven low by a PCI agent to signal a parity error PMC IO 01 to PMC IO 46 Thales Computers PMC IO signals from J14 PMC to P2 connector Used to transmit I O signals from PMC board Page 1 of 2 31 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CA DT 129 5e Connectors Mnemonic Description REQ Request Driven low by a PCI agent to request ownership of the PCI bus REQG64 Request 64 bit Transfer Driven low by the current bus master indicates that it desires to transfer data using 64 bits RST Reset Driven low to reset the PCI bus SBO Snoop Backoff Indicates a hit of a modified line when asserted SDONE Snoop Done Indicates the status of the snoop for the current access SERR System Error Driven low by a PCI agent to signal a system error STOP STOP Driven low by a PCI target to signal a disconnect or target abort Test Clock Used to clock state information and test data into and out of the TCK device during operation of the TAP Test Data Input Used to serially shift test data and test instructions into the TDI device during TAP operation Test Data Output Used to serially shift test data and test instructions out of TDO A the device during TAP operation TMS Test Mode Select Used to control the state of the TAP controller in the device TRST Test Reset Provide an asynchronou
123. version and the previous version are described in the VMPCBug Release Notes SD DT A51 10 1 Using The VMPCBug Debugger VMPCBug is command driven it performs its various operations in response to commands that you enter at the keyboard The debugger is ready when the COMMAND gt prompt appears on the screen Type your debugger command listed in section 10 2 and press the Enter key to execute it A debugger command is made up of the following parts The command name either uppercase or lowercase e g AUTO or auto Any required arguments as specified by command At least one space before the first argument Precede all other arguments with either a space or comma One or more options Precede an option or a string of options with a semicolon If no option is entered the command s default option conditions are used 10 2 Debugger Commands The debugger commands are listed in the following table The commands are described in detail in the VMPCBug User s Manual All the available debugger commands can be listed by entering the HELP H command alone You can view the syntax for a particular command by entering H and the command mnemonic as listed below m swemweoHd O BHP PReP System Boot and Halt Like BHM for PReP image M Block Move Bo System Boot and Go HPM B BOM Boot with reserved Memory and Go PReP System Boot and Go Usual Commands Page 1 of 3 Thales Computers 79 CA DT 1

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