M68000 User Manual M68000
Contents
1. 64 Lead Quad Flat Pack Case 840B 01 p R G gt lt H gt lt gt M lt A 1 1 M 10 1 M 1 p S m 1 1 m 10 1 HN 3 gt lt L gt I K lt lt gt oe MILLIMETERS INCHES MIN MAX MIN MAX A 16 95 17 45 0 667 0 687 B 13 90 14 10 0 547 0 555 C 16 95 17 45 0 667 0 687 D 13 90 14 10 0 547 0 555 G 0 30 0 45 0 012 0 018 H 0 80 BSC 0 031 BSC K 2 15 2 45 0 085 0 096 L 0 13 0 23 0 005 0 009 M 2 00 2 40 0 79 0 094 R 12 00 REF 0 472 REF S 12 00 REF 0 472 REF 22 M68000 USER S MANUAL ADDENDUM For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc 11 0 PACKAGE DIMENSIONS PB SUFFIX Add the following to Section 11 2 64 Lead Thin Quad Flat Pack Case 840F 02 ree Meade DIM MILLIMETERS INCHES MIN MAX MIN MAX A 12 00 BSC 0 472 BSC Al 6 00 BSC 0 236 BSC B 10 00 BSC 0 394 BSC B1 5 00 BSC 0 197 BSC C 12 00 BSC 0 472 BSC C1 6 00 B2. DTACK DATA IN BERR BR NOTE 2 HALT RESET ASYNCHRONOUS INPUTS NOTE 1 NOTES 1 Setup time for the asynchronous inputs IPL2 IPLO and AVEC 47 guarantees their recognition at the next falling edge of the clock 2 BR need fall at this time only to insure being recognized at the end of the bus cycle 3 Timing measurements are referenced to and from a low voltage of 0 8 V and a high voltage of 2 0 V unless otherwise noted The voltage swing through this range should start outside and pass through the range such that the rise or fall is linear between 0 8 V and 2 0 V Figure 9 MC68SECO000 Read Cycle Timing Diagram 14 M68000 USER S MANUAL ADDENDUM For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc lt GA FC2 FCO x A Te Le A23 A0 LDS UDS DTACK DATA OUT BERR BR NOTE 2 HALT RESET ASYNCHRONOUS INPUTS NOTE 1 NOTES 1 Timing measurements are referenced to and from a low voltage of 0 8 V and a high voltage of 2 0 V unless otherwise noted The voltage swing through this range should start outside and pass through the range such that the rise or fall is linear between 0 8 V and 2 0 V 2 Because of loading variations R W may be valid after AS even though both are initiated by the rising edge of S2 specification 20A Figure 10 MC68SEC000 Write Cycl
3. V 23 A ADDRESS B cc C gt SS BUS E a _ gt DisD0 gt DATA BUS ea we FCO RW PROCESSOR __ FCI gt ASYNCHRONOUS STATUS S UDS w BUS CONTROL Ee LDS _ __DTACK MC68SEC000 mh lt _ __ __ BUS ARBITRATION BG CONTROL BERR guU RESET aoa SYSTEM PE INTERRUPT CONTROL HALT aee CONTROL MODE a EO Figure 1 Input and Output Signals MC68EC000 and MC68SEC000 2 1 Data Bus D15 D0 In Section 3 2 on page 3 4 replace The MC68EC000 and MC68HC001 use D7 D0 in 8 bit mode and D15 D8 are undefined with Using the MC68HC001 MC68EC000 and MC68SEC000 mode pin you can statically select either 8 or 16 bit modes for data transfer The MC68EC000 MC68SEC000 and MC68HC001 use D7 DO in 8 bit mode D15 D8 are undefined 2 2 Bus Arbitration Control In Section 3 4 on page 3 5 the sentence In the 48 pin version of the MC68008 and MC68EC000 no pin is available for the bus grant acknowledge signal this microprocessor uses a two wire bus arbitration scheme should read In the 64 pin MC68EC000 and MC68SEC000 no pin is available for the bus grant acknowledge signal These microprocessors use a two wire bus arbitration scheme 2 3 System Control The Mode subsection heading of Section 3 6 on page 3 7 should read Mode MODE MC68HC001 68EC000 68SEC000 2 4 MC68SEC000 Low Power Mode Add the following to Sections 4 and 5 Bus Operation The MC68SECO00 has been red
4. 10 10 Clks 5g BR Negated to AS LDS UDS R W Driven 1 5 1 5 1 5 Clks 5gA _ BR Negated to FC Driven 1 1 1 Clks Applies to 3 3V and 5V NOTES 1 2 3 13 For a loading capacitance of less than or equal to 50 pF subtract 5 ns from the value given in the maximum columns Actual value depends on clock period If 47 is satisfied for both DIACK and BERR 48 may be ignored In the absence of DIACK BERR is an asynchronous input using the asynchronous input setup time 47 For power up the MC68SEC000 must be held in the reset state for 100 ms to allow stabilization of on chip circuitry After the system is powered up 56 refers to the minimum pulse width required to reset the controller If the asynchronous input setup time 47 requirement is satisfied for DTACK the DIACK asserted to data setup time 31 requirement can be ignored The data must only satisfy the data in to clock low setup time 27 for the following clock cycle When AS and R W are equally loaded 20 subtract 5 ns from the values given in these columns The minimum value must be met to guarantee proper operation If the maximum value is exceeded BG may be reasserted M68000 USER S MANUAL ADDENDUM MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc gt lt 8 gt 6 A23 A0 LDS UDS
5. MIN MAX min max min max UNIT Frequency of Operation f 0 10 0 0 16 7 0 20 0 MHz 1 Cycle time tcyc 100 60 50 ns 2 3 Clock Pulse Width teL 45 27 21 ns teH 45 27 21 45 Clock Rise and Fall Times tor 10 5 E 4 ns tot 10 5 4 Applies to 3 3V and 5V NOTE Timing measurements are referenced to and from a low voltage of 0 8 V and a high voltage of 2 0 V unless otherwise noted The voltage swing through this range should start outside and pass through the range such that the rise or fall will be linear between 0 8 V and 2 0 V Figure 8 MC68SEC000 Clock Input Timing Diagram M68000 USER S MANUAL ADDENDUM MOTOROLA For More Information On This Product Go to www freescale com 12 Freescale Semiconductor Inc 7 0 MC68SEC000 AC ELECTRICAL SPECIFICATIONS READ AND WRITE CYCLES Add the following table and Figures 9 and 10 to Section 10 16 Applies to 3 3V and 5V GND 0 V Ta T to Ty see Figures 3 and 4 10MHz 16MHz 20MHz NUM CHARACTERISTIC MIN MAX MIN MAX MIN MAX UNIT 6 Clock Low to Address Valid 35 30 25 ns 6A Clock High to FC Valid 0 35 0 30 0 25 ns 7 fans to Address Data Bus High Impedance Maximum 55 50 42 ns 8 Clock High to Address FC Invalid Minimum 0 0 0 ns g Clock High
6. S MANUAL ADDENDUM MOTOROLA Freescale Semiconductor Inc ORDERING INFORMATION Add the following to Section 11 The following tables contains the ordering informat ion for the MC68SECOOO MC68SEC000 Ordering Information PACKAGE BODY SIZE LEAD SPACING SPEED INMHZ VOLTAGE SUFFIX TEMPERATURE FU 0C to 700 real 10 16 20 MHz 3 3Vor5 0V aas ee Se Serie PB 0C to 70C 10 0mm x 10 0mm CPB 40C to 85C MC68HC000 Ordering Information PACKAGE BODY SIZE LEAD SPACING SPEED INMHZ VOLTAGE SUFFIX TEMPERATURE DIP 81 91mm X 20 57mm 254mm 8 10 12 16 P 0C to 70C PLCC 8 10 12 16 20 5 0V FN 0C to 70C Reser hey 8 10 12 16 GFN 40C to 85C MC68EC000 Ordering Information PACKAGE BODY SIZE LEAD SPACING SPEED INMHZ VOLTAGE SUFFIX Mi 4 vir adi PLCC 25 57mm X 25 27mm 127mm 8 10 12 16 20 5 0V FN 0C to 70C PQFP 14 1mm X 14 1mm 0 8mm 8 10 12 16 20 FU DOCUMENTATION Add to Section 11 The documents listed in the following table contain detailed information that pertain to the MC68SECO000 processor You can obtain these documents from the Literature Distribution Centers listed on the last page of this document MC68SEC000 Documentation MC68SEC000 DOCUMENTATION DOCUMENT NUMBER M68000 Family M68000PM AD Programmer s Reference Manual M68000 User s Manual M68000UM AD High Performance Embedded Systems BR729 D Source Catalo
7. a cost effective static embedded processor engineered for low power applications In addition to providing the substantial cost and performance benefits of the MC68ECO000 the low power mode of the MC68SECO000 provides significant advantages in power consumption and power management The typical current consumption of the MC68SEC000 is only 0 5uA in static standby mode and 15 0mA in normal 3 3V operation The MC68SEC000 operates in either 3 3V or 5 0V systems The remarkably low power consumption small footprint packages and static implementation are combined in the MC68SEC000 for low power applications such as portable measuring equipment electronic games and battery operated hand held consumer products The HCMOS MC68SEC000 s static architecture is a direct replacement for the MC68ECO000 which offers the lowest cost entry point to 32 bit processing The internal 32 bit architecture provides fast and efficient processing that satisfies the requirements of sophisticated applications based on high level languages All of the existing third party developer tools widely available for the MC68ECO000 will directly support the MC68SECO00 You can find detailed descriptions of these tools in the High Performance Embedded Systems Source Catalog MOTOROLA M68000 USER S MANUAL ADDENDUM 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 0 SIGNAL DESCRIPTION Change Figure 3 3 on Page 3 2
8. affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part Motorola and are registered trademarks of Motorola Inc Motorola Inc is an Equal Opportunity Affirmative Action Employer Literature Distribution Centers USA EUROPE Motorola Literature Distribution P O Box 20912 Arizona 85036 JAPAN Nippon Motorola Ltd 4 32 1 Nishi Gotanda Shinagawa ku Tokyo 141 Japan ASIA PACIFIC Motorola Semiconductors H K Ltd Silicon Harbour Center No 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong es SEMICONDUCTOR PRODUCT INFORMATION m For More Information On This Product Go to www freescale com
9. of STOP gt lt Stop gt Address Instruction Figure 4 MC68SECO000 Clock Stop Timing for 16 Bit Data Bus Note While the MC68SEC000 is in the low power mode all inputs must be driven to Vpp or Vss or have a pull up or pull down resistor 3 This step is optional depending on whether your applications require the MC68SECO00 signals with three state capability to be placed into a high impedance state To place the MC68SEC000 into a three state condition the proper method for arbitrating the bus as described in 5 2 Bus Arbitration in the M68000 User s Manual Rev 8 should be completed during the fetch of the status register data for the STOP instruction A timing diagram with the bus arbitration sequence is shown in Figure 5 CLK S0 S1 S2 S3 S4 S5 S6 S7 SO S1 S2 S3 S4 S5 S6 S7 cuck LI LJ LJ LJ LI LI LI LI 1 Write to Fetch Immediate lt Low Power lt Data of STOP gt lt Stop gt Instruction Address Figure 5 MC68SEC000 Clock Stop Timing with Bus Arbitration for 16 Bit Data Bus M68000 USER S MANUAL ADDENDUM MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc After the previous steps are completed the MC68SECO000 will remain in the low power mode until it recognizes the appropriate interrupt External logic will also have to poll IPLB2 IPLBO to detect the proper interrupt When the correct interrupt level is received the following steps wi
10. tee SEVICONDUCTOR PRODUCT INFORMATION mmm 1997 Motorola Inc All Rights Reserved For More Information On This Product Go to www freescale com Freescale Semiconductor Inc The primary features of the MC68SEC000 embedded processor include the following e Direct Replacement for the MC68EC000 Pin for pin compatibility with the MC68ECO000 in the plastic QFP and TQFP packages Vast selection of existing third party development tools for the MC68ECO000 support the MC68SEC000 Software written for the MC68ECO000 will run unchanged on the MC68SECO000 e Power Management Low power HCMOS technology Static design allows for stopping the processor clock 3 3V or 5V operation Typical 0 5uA current consumption at 3 3V in sleep mode e Software Strength Fully upward object code compatible with other M68000 Family products M68000 architecture allows effective assembly code with a C compiler e Upgrade Fully upward code compatible with higher performance 680x0 and 68300 Family members ColdFire code compatible with minor modifications 1 MC68HCO00 The primary benefit of the MC68HCO00 is reduced power consumption The device dissipates less power by an order of magnitude than the NMOS MC68000 The MC68HC000 is an implementation of the M68000 16 32 bit microprocessor architecture The MC68HC000 has a 16 bit data bus implementation of the MC68000 and is upward code compatible with the MC6801
11. 0 and the MC68020 32 bit implementation of the architecture 1 1 MC68HCO001 The MC68HC001 provides a functional extension to the MC68HC000 HCMOS 16 32 bit microprocessor with the addition of statically selectable 8 or 16 bit data bus operation The MC68HC001 is object code compatible with the MC68HC000 You can migrate code written for the MC68HC001 without modification to any member of the M68000 Family 1 2 MC68EC000 The MC68EC000 is an economical high performance embedded controller designed to suit the needs of the cost sensitive embedded controller market The HCMOS MC68EC000 has an internal 32 bit architecture that is supported by a statically selectable 8 or 16 bit data bus This architecture provides a fast and efficient processing device that can satisfy the requirements of sophisticated applications based on high level languages The MC68EC000 is fully object code compatible with the MC68000 You can migrate code written for the MC68EC000 without modification to any member of the M68000 Family The MC68EC000 brings the performance level of the M68000 Family to cost levels previously associated with 8 bit microprocessors The MC68EC000 benefits from the rich M68000 instruction set and its related high code density with low memory bandwidth requirements 2 M68000 USER S MANUAL ADDENDUM MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 1 3 MC68SEC000 The MC68SEC000 is
12. Freescale Semiconductor Inc MOTOROLA OS rS2000UMADIAD M68000UMAD AD Communications and Advanced Consumer Technologies Group M68000 Addendum to M68000 User Manual August 7 1997 This addendum to the M68000UM AD User s Manual Revision 8 provides corrections to the original text as well as additional information This document and other information on this product is maintained on the World Wide Web at http www motorola com 68000 OVERVIEW This manual includes hardware details and programming information for the MC68HC000 the MC68HC001 the MC68ECO000 and the MC68SECOO0 For ease of reading the name M68000 MPUs will be used when referring to all processors Refer to M68000PM AD M68000 Programmer s Reference Manual for detailed information on the MC68000 instruction set The four microprocessors are very similar to each other and all contain the following features e Sixteen 32 Bit Data and Address Registers e 16 Mbyte Direct Addressing Range e Program Counter 6 Instruction Types e Operations on Five Main Data Types e Memory Mapped Input Output I O e 14 Addressing Modes The following processors contain additional features e MC68HC001 MC68EC000 MC68SECO000 Statically selectable 8 or 16 bit data bus e MC68HC000 MC68EC000 MC68HC001 MC68SEC000 Low power This document contains information on a product under development Motorola reserves the right to change or discontinue this product without notice
13. LA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc AC ELECTRICAL SPECIFICATIONS READ AND WRITE CYCLES Continued 10MHz 16MHz 20MHz NUM CHARACTERISTIC MIN MAX MIN MAX MIN MAX UNIT 29 AS LDS UDS Negated to Data In Invalid Hold Time on Read 0 0 0 ns 29A AS LDS UDS Negated to Data In High Impedance Read 150 90 75 ns 30 AS LDS UDS Negated to BERR Negated 0 0 0 ns 3125 DTACK Asserted to Data In Valid Setup Time on Read 65 50 42 ns 32 HALT and RESET Input Transition Time 0 150 0 150 0 150 ns 33 Clock High to BG Asserted 35 30 25 ns 34 Clock High to BG Negated 35 30 25 ns 35 IBR Asserted to BG Asserted 1 5 35 1 5 3 5 1 5 3 5 Clks 36 BR Negated to BG Negated 15 35 15 35 15 3 5 Clks 38 _ BG Asserted to Control Address Data Bus High Impedance AS 55 50 42 ns Negated 39 IBG Width Negated 1 5 1 5 1 5 Clks 44 AS LDS UDS Negated to AVEC Negated 0 55 0 50 0 42 ns 47 Asynchronous Input Setup Time 5 5 5 ns 4823 BERR Asserted to DTACK Asserted 20 10 10 ns 52 Data In Hold from Clock High 0 0 0 ns 53 Data Out Hold from Clock High Write 0 0 0 ns 55 _ R W Asserted to Data Bus Impedance Change Write 20 10 0 ns 564 HALT RESET Pulse Width 10
14. ND RAW NOTE Setup time to the clock 47 for the asynchronous inputs BERR BR DTACK IPL2 IPLO and VPA guarantees their recognition at the next falling edge of the clock Figure 11 Bus Arbitration Timing lt D157 D0 LL __ NOTE Waveform measurements for all inputs and outputs are specified at logic high 2 0 V logic low 0 8 V Figure 12 MC68SECO000 Bus Arbitration Timing Diagram MOTOROLA M68000 USER S MANUAL ADDENDUM 17 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc CLK Ny ae 5 O on ee BR G a lt BG R i gt AS N DS N e S re VMA N a RW N NOTES Waveform measurements for all inputs and outputs are specified at logic high 2 0 V logic low 0 8 V This diagram also applies to the 68EC000 Figure 13 Bus Arbitration Timing lIdle Bus Case 18 M68000 USER S MANUAL ADDENDUM MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 9 S 2 ai BR ol K 7 N BG N gt AS N _ DS N A EN y JS VMA RW j NOTE Waveform measurements for all inputs and outputs are specified at logic high 2 0 V logic low 0 8 V This diagram also applies to the 68EC000 Figure 14 Bus Arbitration Timing Active Bus Case MOTOROLA M68000 USER S MANUAL ADDENDUM 19 For More Information On
15. SC 0 236 BSC D 10 00 BSC 0 394 BSC D1 5 00 BSC 0 197 BSC G 0 17 0 27 0 007 0 011 H 0 50 BSC 0 020 BSC K a 1 60 0 063 L 0 09 0 20 0 004 0 008 M 1 35 1 45 0 053 0 057 MOTOROLA M68000 USER S MANUAL ADDENDUM For More Information On This Product Go to www freescale com 24 Freescale Semiconductor Inc 12 0 PACKAGE FREQUENCY AVAILABILITY Replaces Section 11 1 The following tables identify the packages and operating frequencies available for the MC68HC000 MC68HC001 MC68ECO000 and the MC68SECO000 MC68SEC000 PACKAGE FREQUENCY Quad Flat Pack FU Thin Quad Flat Pack PB VOLTAGE o lt NNNINNN For More Information On This Product Go to www freescale com MC68HC000 VOLTAGE PACKAGE FREQUENCY 5V Plastic DIP 8 10 12 16 20 MHz 3 Plastic Quad Pack PLCC 8 10 12 16 20 MHz 3 Plastic Quad Gull Wing __ Pin Grid Array Solder Lead Finish 8 10 12 16 20 MHz 3 Pin Grid Array Gold Lead Finish 8 10 12 16 20 MHz 3 Plastic Quad Pack PLCC 8 10 12 16 20 MHz 3 MC68HC001 VOLTAGE PACKAGE FREQUENCY 5V Plastic Quad Pack PLCC 8 10 12 16 MHz v Plastic Quad Gull Wing os 8 10 12 16 MHz S Pin Grid Array Gold Lead Finish 810 12 16 MHz 7 8 10 12 16 MHz v MC68EC000 VOLTAGE PACKAGE PREQuENCY 5V Plastic Quad Pack PLCC 8 MHz v Plastic Quad Flat Pack 10 MHz J 12 MHz v 16 MHz y 20 MHz y NOTE not recommended for new designs M68000 USER
16. SETS Gute ur sh ogy OUTPUT n l is cs VALID OUTPUTS 2 CLK OUTPUT n VALID OUTPUT 1 DRIVETO gt gt 24V INPUTS 3 CLK DRIVETO __ 0 5V INPUTS 4 CLK 2 0V ALL SIGNALS 5 0 8V E F 2 0V 0 8V NOTES 1 This output timing is applicable to all parameters specified relative to the rising edge of the clock 2 This output timing is applicable to all parameters specified relative to the falling edge of the clock 3 This input timing is applicable to all parameters specified relative to the rising edge of the clock 4 This input timing is applicable to all parameters specified relative to the falling edge of the clock 5 This timing is applicable to all parameters specified relative to the assertion negation of another signal LEGEND A Maximum output delay specification B Minimum output hold time C Minimum input setup time specification D Minimum input hold time specification E Signal valid to signal valid specification maximum or minimum F Signal valid to signal invalid specification maximum or minimum Figure 7 Drive Levels and Test Points for AC Specifications applies to all parts M68000 USER S MANUAL ADDENDUM MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 5 0 MC68SEC000 DC ELECTRICAL SPECIFICATIONS Add the following table to Section 10 13 on page 10 23 Voc 5 0 Vde 5 3 3 Vde 10 GND 0
17. This Product Go to www freescale com Freescale Semiconductor Inc nN 4 LIA eee gt AS Ny DS Ny et lt nae se A VMA a aaa O O R W A r ww NOTES Waveform measurements for all inputs and outputs are specified at logic high 2 0 V logic low 0 8 V This diagram also applies to the 68EC000 Figure 15 Bus Arbitration Multiple Bus Request 20 M68000 USER S MANUAL ADDENDUM MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 9 0 MECHANICAL DATA 9 1 PIN ASSIGNMENTS Add Figure 12 to Section 11 1 The following defines the pin assignment and the package dimensions of the 64 lead QFP FU package and 64 lead TQFP PB package for the MC68SECOO0 Note that it is pin to pin compatible with the MC68ECO00 3 2 oraod S von ogof E JIDitaaadeadqadnedoadnadead daa i HILT A A H R W e D12 DTACK D13 BG D14 BR D15 Voc A23 CLK A22 GND A21 MORE MC68SEC000FU PB Vcc HALT A20 RESET A19 AVEC A18 BERR A17 IPL2 A16 IPL1 A15 IPLO A14 FC2 A13 A12 FC1 FCO AO Al A2 A3 GND A4 A5 A6 A7 A8 A9 A10 A11 Figure 16 64 Lead Quad Flat Pack and 64 Lead Thin Quad Flat Pack MOTOROLA M68000 USER S MANUAL ADDENDUM 21 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 10 0 PACKAGE DIMENSIONS FU SUFFIX This diagram replaces the one on Page 11 16
18. Vdc Ta T to Ty 3 3 V 5 0 V CHARACTERISTIC SYMBOL MIN MAX MIN MAX UNIT Input High Voltage Vin 2 0 Voc 2 0 Voc V Input Low Voltage Vib GND 0 8 GND 0 8 V Input Leakage Current BERR BR DTACK CLK I PL2 IPLO AVEC lin 2 5 2 5 uA MODE HALT RESET 20 20 Three State Off State Input Current Its 2 5 2 5 uA Output High Voltage Vou 2 4 Voc 0 75 Output Low Voltage VoL IOL 1 6 mA HALT 0 5 0 5 IOL 3 2 mA A23 A0 BG FC2 FC0 0 5 0 5 IOL 5 0 mA RESET A tat 0 5 0 5 IOL 5 3 mA AS D15 D0 LDS R W UDS 0 5 0 5 Current Dissipation f 0 Hz Ip 0 7 1 0 mA f 10MHz 10 15 mA f 16 MHz 15 25 mA f 20 MHz 20 30 mA Capacitance Vin 0 V T4 25 C Frequency 1 MHz Cin 20 0 20 0 pF Load Capacitance HALT CL 70 70 pF All Others 130 130 During normal operation instantaneous Vcc current requirements may be as high as 1 5A Currents listed are with no loading Capacitance is periodically sampled rather than 100 tested 10 M68000 USER S MANUAL ADDENDUM MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 6 0 MC68SEC000 AC ELECTRICAL SPECIFICATIONS CLOCK TIMING See Figure 2 Add the following table and Figure 8 to Section 10 9 on page 10 9 10MHz 16MHz 20MHz NUM CHARACTERISTIC SYMBOL
19. _CLK Figure 2 MC68SECO000 Low Power Circuitry for 16 Bit Data Bus ADDRESS_MATCH CPU_CLI RESTART RESET Figure 3 MC68SECO000 Low Power Circuitry for 8 Bit Data Bus 2 Execute the STOP instruction The external circuitry shown in Figure 2 and Figure 3 will count the number of bus cycles starting with the write to the low power address and will stop the processor clock on the first falling edge of the system clock after the bus cycle that reads the immediate data of the STOP instruction Figure 3 has one more flip flop than Figure 2 because the MC68SEC000 in The preliminary specification for the MC68SEC000 s current drain while in the low power mode is Idd lt 2uA for 3 3V operation and Idd lt 5uA for 5 0V operation M68000 USER S MANUAL ADDENDUM MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 8 bit mode requires two bus cycles to fetch the immediate data of the STOP instruction After the processor clock is disabled it is often necessary to disable the clock to other sections of your circuit This can be done but be careful that runt clocks and spurious glitches are not presented to the MC68SECOO0 A timing diagram is shown in Figure 4 CLK S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7 CPU_CLK l l l l l l l l l reas Emaus Snn RW DTACK Write to Fetch Immediate lt lt Low Power lt Data
20. e Timing Diagram MOTOROLA M68000 USER S MANUAL ADDENDUM 15 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 8 0 MC68SEC000 AC ELECTRICAL SPECIFICATIONS BUS ARBITRATION Add the following table and Figure 11 to Section 10 17 GND 0 Vdc T T to Ty refer to Figure 13 10MHz 16MHz 20MHz NUM CHARACTERISTICp MIN MAX MIN MAX MIN MAX UNIT 7 Clock High to Address Data Bus High Impedance Maximum 55 50 42 ns 16 Clock High to Control Bus High Impedance 55 50 42 ns 33 Clock High to BG Asserted 0 35 0 30 0 25 ns 34 Clock High to BG Negated 0 35 0 30 0 25 ns 35 BR Asserted to BG Asserted 1 5 35 15 3 5 15 3 5 Clks 36 BR Negated to BG Negated 1 5 3 5 1 5 3 5 1 5 3 5 Clks 38 BG Asserted to Control Address Data Bus High Impedance AS 55 50 42 ns Negated 39 BG Width Negated 5 5 1 5 Clks 47 Asynchronous Input Setup Time 5 5 5 ns 58 BR Negated to AS LDS UDS R W Driven 1 5 1 5 1 5 Clks 58a BR Negated to FC Driven 1 1 1 Clks Applies to 3 3V and 5V 1 The minimum value must be met to guarantee proper operation If the maximum value is exceeded BG may be reasserted M68000 USER S MANUAL ADDENDUM MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc STROBES a oe A
21. esigned to provide fully static and low power operation This section describes the recommended method for placing the MC68SECO000 into a low power mode to reduce the M68000 USER S MANUAL ADDENDUM MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc power consumption to its quiescent value while maintaining the internal state of the processor The low power mode described below will be routinely tested as part of the MC68SEC000 test vectors provided by Motorola To successfully enter the low power mode the MC68SECO000 must first be in the supervisor mode A recommended method for entering the low power mode is to use the TRAP instruction which causes the processor to begin exception processing thus entering the supervisor mode External circuitry should accomplish the following steps during the trap routine 1 Externally detect a write to the low power address You select this address which can be any address in the 16 Mbyte addressing range of the MC68SECOO00 A write to the low power address can be detected by polling A23 A0 R W and FC2 FCO When the low power address is detected RAW is a logic low and the function codes have a five 101 on their output the processor is writing to the low power address in supervisor mode and user designed circuitry should assert the ADDRESS_MATCH signal shown in Figure 2 and Figure 3 ADDRESS_MATCH RESTART cal Bee SYSTEM
22. g MC68EC000 Product Brief MC68EC000 D MC68SEC000 Product Brief MC68SEC000 D MOTOROLA M68000 USER S MANUAL ADDENDUM For More Information On This Product Go to www freescale com 25 Freescale Semiconductor Inc Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries
23. ll bring the processor out of the low power mode 1 Restart the system clock if it was stopped 2 Wait for the system clock to become stable 3 Assert the RESTART signal This will cause the processor s clock to start on the next falling edge of the system clock Figure 6 shows the timing for bringing the processor out of the low power mode Both the RESTART and RESET signals are subject to the asynchronous setup time as specified in the Electrical Characteristics section of this addendum WARNING The system clock must be stable before the RESTART signal is asserted to prevent glitches in the clock An unstable clock can cause unpredictable results in the MC68SECOO0 cee ep EN CPU_CLK LI LI LI RESTART Figure 6 MC68SECO000 Clock Start Timing 4 If the MC68SECO000 was placed in a three state condition the BR signal must be negated before the processor can begin executing instructions 7 M68000 USER S MANUAL ADDENDUM MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc An example trap routine is as follows TRAP_x MOVE B 0 low_power_address Write that causes ADDRESS MATCH to assert STOP 2000 STOP instruction with desired interrupt mask RTE Return from the exception The first instruction MOVE B 0 low_power_address writes a byte to the low power address that will cause the external circuitry to begin the sequence that will stop the p
24. rocessor s clock The second instruction STOP 2000 loads the SR with the immediate data This lets you set the interrupt that will cause the processor to come out of the low power mode The final instruction RTE tells the processor to return from the exception and resume normal processing 3 0 MC68SEC000 ELECTRICAL SPECIFICATIONS Add to the following table to Section 10 1 3 1 MC68SEC000 MAXIMUM RATINGS RATING SYMBOL VALUE UNIT Supply Voltage Voc 0 3 to 6 5 V Input Voltage Vin 0 5 to 6 5 V Maximum Operating Ta T to Ty C Temperature Range 0 to 70 Commercial Extended C Grade 40 to 85 Storage Temperature Tstg 55 to 150 C 3 2 CMOS CONSIDERATIONS The following change should be made to Section 10 4 CMOS Considerations Although the MC68HC000 and MC68EC000 is implemented with input protection diodes care should be exercised to ensure that the maximum input voltage specification is not exceeded should read Although the MC68HCO000 MC68ECO000 and MC68SEC000 are implemented with input protection diodes be careful not to exceed the maximum input voltage specification M68000 USER S MANUAL ADDENDUM MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 4 0 MC68SECO000 AC ELECTRICAL SPECIFICATIONS Replace Figure 10 2 on page 10 6 with Figure 7 DRIVE TO24V CLK DRIVE TO 0 5V a VALID VALID TPUTS 1 CLK
25. to AS LDS UDS Asserted 3 35 3 30 3 25 ns 112 cress Valid to AS LDS UDS Asserted Read AS Asserted 20 15 10 ns 1142 FC Valid to AS LDS UDS Asserted Read AS Asserted Write 45 45 40 ns 421 Clock Low to AS LDS UDS Negated 3 35 3 30 3 25 ns 132 AS LDS UDS Negated to Address FC Invalid 15 15 10 ns 442 AS and LDS UDS Read Width Asserted 195 120 100 ns 14A2 LDS UDS Width Asserted Write 95 60 50 ns 152 AS LDS UDS Width Negated 105 60 50 ns 16 Clock High to Control Bus High Impedance 55 50 FF 42 ns 172 AS LDS UDS Negated to R W Invalid 15 15 10 ns 4g Clock High to R W High Read 0 35 0 30 0 25 ns 991 Clock High to RW Low Write 0 35 0 30 0 25 ns 20426 AS Asserted to RW Low Write 10 10 10 ns 942 Address Valid to RAW Low Write 0 0 0 ns 2142 FC Valid to RW Low Write 50 30 25 ns 292 R W Low to DS Asserted Write 50 30 25 ns 23 Clock Low to Data Out Valid Write 35 30 25 ns 252 AS LDS UDS Negated to Data Out Invalid Write 30 15 10 ns 262 Data Out Valid to LDS UDS Asserted Write 30 15 10 ns 275 Data In Valid to Clock Low Setup Time on Read 5 5 5 ns 282 AS LDS UDS Negated to DTACK Negated Asynchronous Hold 0 110 0 110 0 95 ns 28A _ Clock High to DTACK Negated 0 110 0 110 0 95 ns M68000 USER S MANUAL ADDENDUM MOTORO
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