KAI-4011 / KAI-4021 / KAI-04022 Imager Board User`s Manual
Contents
1. EVBUM2279 D KAI 4011 KAI 4021 KAI 04022 Imager Board User s Manual Description The KAI 4011 KAI 4021 KAI 04022 Imager Evaluation Board referred to in this document as the Imager Board is designed to be used as part of a two board set used in conjunction with a Timing Generator Board ON Semiconductor offers an Imager Board Timing Generator Board package that has been designed and configured to operate with the KAI 4011 KAI 4021 KAI 04022 Image Sensors The Timing Generator Board generates the timing signals necessary to operate the CCD and provides the power required by the Imager Board The timing signals in LVDS format and the power are provided to the Imager Board via the interface connector J1 In addition the Timing Generator Board performs the processing and digitization of the analog video output of the Imager Board The KAI 4011 KAI 4021 KAI 04022 Imager Board has been designed to operate the KAI 4011 KAI 4021 ON Semiconductor www onsemi com EVAL BOARD USER S MANUAL KAI 04022 CCDs with the specified performance at 40 MHz pixel clocking rate and nominal operating conditions See the KAI 4011 KAI 4021 KAI 04022 performance specifications for details For testing and characterization purposes the KAI 4011 KAI 4021 KAI 04022 Imager board provides the ability to adjust many of the CCD bias voltages and CCD clock level voltages by adjusting potentiometers on the board The2. Imager Board provides the means to modify other device operating parameters CCD reset clock pulse width VSS bias voltage by populating components differently on the board INPUT REQUIREMENTS Table 1 POWER REQUIREMENTS Power Supplies Minimum Typical 1 175 9 5 0 A 200 8 20 21 20 Table 2 SIGNAL LEVEL REQUIREMENTS Input Signals LVDS Vmin Vthreshold Vmax Units Comments H1A 3 0 40 1 24 H1A clock H1B 0 0 1 2 4 H1B clock Semiconductor Components Industries LLC 2014 October 2014 Rev 2 V V V1 clock V2 clock Publication Order Number EVBUM2279 D EVBUM2279 D Table 2 SIGNAL LEVEL REQUIREMENTS eB eB V3RD poo 0 1 2 4 V2 Clock 34 level VES 0 1 2 4 Electronic Shutter AMP_ENABLE o 0 1 2 4 Output Amplifier Enable ARCHITECTURE OVERVIEW The following sections describe the functional blocks of the KAI 4011 KAI 4021 KAI 04022 Imager Board Refer to Figure 1 Power Filtering and Regulation Power is supplied to the Imager Board via the J1 interface connector The power supplies are de coupled and filtered with ferrite beads and capacitors to suppress noise Voltage regulators are used to create the 15 V and 15 V supplies from the VPLUS and VMINUS supplies LVDS Receivers TTL Buffers LVDS timing signals are input to the Imager Board via the J1 interface connector These signals are shi
3. R FDG CKT e V1 K VES CKT DRIVER f H1A H1B H2B DRIVER DRIVER DRIVER LVDS TO TTL BUFFERS 15V AA AA REGULATOR RECEIVERS AA A 15V REGULATOR J1 BOARD INTERFACE CONNECTOR Figure 1 KAI 4011 KAI 4021 KAI 04022 Imager Board Block Diagram 100000 SIGNAL MEAN ELECTRONS 0 01 10000 1000 LINEARITY a e MEASURED FIT DEVIATION FROM FIT INTEGRATION TIME SECONDS Figure 2 Measured Performance Linearity http onsemi com Noise A D counts 100 10 EVBUM2279 D Photon Transfer x Slope el Adu 9 29 electrons Noise floor 3 65 counts 33 9 electrons LVSAT 30220 electrons lt VSAT 32980 electrons 10 100 1000 10000 Signal Mean Electrons 100000 Figure 3 Measured Performance Dynamic Range and Noise Floor http onsemi com 5 EVBUM2279 D CONNECTOR ASSIGNMENTS AND PINOUTS SMB Connectors J2 and J3 The emitter follower buffered CCD_VOUT signals are 75 Q should be used to connect the imager board to the driven from the Imager Board via the SMB connectors J2 Timing Generator Board to match the series and terminating and J3 Coaxial cable with a characteristic impedance of resistors
4. cation for details Clock Voltages Table 4 were correct at the time of this document s The following clock voltage levels are fixed or adjusted publication but may be subject to change refer to the with a potentiometer as noted The nominal values listed in KAI 4011 KAI 4021 KAI 04022 device specification Table 4 CLOCK VOLTAGES Reset Clock RESET CCD Low ba iin nz cm mmu Fast Dump Clock FDG CCD Low ee Rr 1E IE DRM Me The H1A_CCD H1B CCD H2A CCD and H2B CCD low levels are controlled by the same potentiometer R147 The H1A_CCD H1B CCD H2A CCD and H2B CCD high levels are controlled by the same potentiometer R127 V1 CCD and V2 CCD low levels are controlled by the same potentiometer R40 V1 CCD and V2 CCD mid levels are controlled by the same potentiometer R66 FDG is used to flush the device when operated in Still Mode lt lt lt lt lt lt lt QC DOT http onsemi com 3 EVBUM2279 D BLOCK DIAGRAM AND PERFORMANCE DATA J2 J3 SMB SMB LINE LINE M EMITTER p EMITTER ly O DRIVER FOLLOWER FOLLOWER DRIVER V V3RD DRIVER optional VOUT LEFT VOUT RIGHT RCLK RCLK V2 gt f DRIVER 1 SHOT DRIVER CCD SENSO
5. fted to TTL levels before being sent to the CCD clock drivers CCD Pixel Rate Clock Drivers H1 H2 amp Reset Clocks The pixel rate CCD clock drivers utilize two fast switching transistors that are designed to translate TTL level input clock signals to the voltage levels required by the CCD The high level and low level of the CCD clocks are set by potentiometers Reset Clock One Shot U15 not populated The pulse width of the RESET CCD clock used to be set by a programmable One Shot The One Shot was configured to provide a RESET CCD clock signal with a pulse width from 5 ns to 15 ns Now the pulse width control functionality is provided by the KSC 1000 Timing Generator Board and the one shot has been bypassed by removing U15 and inserting a shorting resistor on pads 1 and 2 of U15 CCD VCLK Drivers The vertical clock VCLK drivers consist of MOSFET driver IC s These drivers are designed to translate the TTL level clock signals to the voltage levels required by the CCD The high middle and low voltage levels of the vertical clocks are set by potentiometers buffered by operational amplifiers configured as voltage followers The current sources for these voltage levels are high current up to 600 mA transistors The V2 CCD high level clock voltage is switched from V MID to V HIGH once per frame to transfer the charge from the photodiodes to the vertical CCDs CCD FDG Driver The Fast Dump Gate FDG driver is a transistor t
6. hat will switch the voltage on the FDG pin of the CCD from FDG LOW to FDG HIGH during Fast Dump Gate operation When not in operation or when the Fast Dump Gate feature is not being utilized the FDG pin of the CCD is held at FDG LOW The FDG HIGH and FDG LOW voltage levels of the FDG driver are set by resistor divider circuits and are buffered by operational amplifiers configured as voltage followers VES Circuit The quiescent CCD substrate voltage VSUB is set by a potentiometer For electronic shutter operation the VES signal drives a transistor amplifier circuit that AC couples the voltage difference between the VPLUS and VMINUS supplies onto the Substrate voltage This creates the necessary potential to clear all charge from the photodiodes thereby acting as an electronic shutter to control exposure CCD Bias Voltages The CCD bias voltages are set by potentiometers buffered by operational amplifiers configured as voltage followers The bias voltages are de coupled at the CCD pin CCD Image Sensor This evaluation board supports the KAI 4021 and KAI 04022 Image Sensors KAI 4011 Emitter Follower The VOUT CCD signals are buffered using bipolar junction transistors in the emitter follower configuration These circuits also provide the necessary 5 mA current sink for the CCD output circuits Line Drivers The buffered VOUT CCD signals are AC coupled and driven from the Imager Board by operational amplifiers in a non inve
7. oard Kit may at their discretion make changes to the Timing Generator Board firmware ON Semiconductor can only support firmware developed by and supplied by ON Semiconductor Changes to the firmware are at the risk of the customer E mail info truesenseimaging com ON Semiconductor reserves the right to change any information contained herein without notice All information furnished by ON Semiconductor is believed to be accurate ON Semiconductor and the ON are registered trademarks of Semiconductor Components Industries LLC SCILLC or its subsidiaries in the United States and or other countries SCILLC owns the rights to a number of patents trademarks copyrights trade secrets and other intellectual property A listing of SCILLC s product patent coverage may be accessed at www onsemi com site pdf Patent Marking pdf SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parame
8. pe Middle East and Africa Technical Support Order Literature http www onsemi com orderlit Phone 303 675 2175 or 800 344 3860 Toll Free USA Canada Phone 421 33 790 2910 eee Fax 303 675 2176 or 800 344 3867 Toll Free USA Canada Japan Customer Focus Center For additional information please contact your local Email orderlit onsemi com Phone 81 3 5817 1050 Sales Representative EVBUM2279 D
9. rting configuration The operational amplifiers are configured to have a gain of 2 to correctly drive 75 Q video coaxial cabling from the SMB connectors http onsemi com 2 EVBUM2279 D OPERATIONAL SETTINGS The Imager board is configured to operate the KAI 4011 were correct at the time of this document s publication but KAI 4021 KAI 04022 Image Sensors under the following may be subject to change refer to the KAI 4011 operating conditions KAI 4021 KAI 04022 device specification DC Bias Voltages The following voltages are fixed or adjusted with a potentiometer as noted The nominal values listed in Table 3 Table 3 DC BIAS VOLTAGES Left Output Amplifier Supply VDDL 15 0 Right Output Amplifier Supply VDDR 15 0 Reset Drain VRD i 12 0 ESD Protection ESD Output Gate Left VOGL 7 5 Output Gate Right VOGR 7 5 1 Ifthe CCD is to be operated in single output mode only VOUT LEFT the unused output amplifier supply can be tied to ground to conserve power by not populating R71 R72 and C76 and by replacing C75 with a 0 Q resistor 2 The Output Gate signals VOGL and VOGR may be controlled independently or by installing R28 and R33 and removing R29 may be set to the same potential controlled by R11 3 The Min and Max voltages in the table indicate the imager board potentiometer adjustable voltage range These values may exceed the specified CCD operating conditions See the KAI 4011 KAI 4021 KAI 04022 device specifi
10. ters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT N American Technical Support 800 282 9855 Toll Free ON Semiconductor Website www onsemi com Literature Distribution Center for ON Semiconductor USA Canada P O Box 5163 Denver Colorado 80217 USA Euro
11. used on these boards Table 5 J1 INTERFACE CONNECTOR PIN ASSIGNMENTS Pin Signal Pin Signal 1 N C N C AGND V3RD 11 13 s 7 19 21 23 VES AGND AGND Oooo e 25 27 29 31 V2 1 R V AGND AGND 2 jocos cc pt 26 28 30 32 56 58 60 62 64 BET RN REPETI IGNES ft SET AGND H2A AGND 3 5 7 9 1 en 51 C 53 i 3 3 3 3 4 4 4 4 4 C 55 N C 57 AGND 59 AMP_ENABLE 61 5 V_MTR VMINUS_MTR N C AGND AMP_ENABLE 5 V_MTR 63 N C N C AGND AGND 5 V_MTR 5 V_MTR N C N C C AGND VPLUS MTR N VPLUS MTR C 65 67 C n E 75 C 77 3 9 C 7 http onsemi com 6 EVBUM2279 D Warnings and Advisories Ordering Information ON Semiconductor is not responsible for customer Please address all inquiries and purchase orders to damage to the Imager Board or Imager Board electronics The customer assumes responsibility and care must be taken Truesense Imaging Inc when probing modifying or integrating the 1964 Lake Avenue ON Semiconductor Evaluation Board Kits Rochester New York 14615 Phone 585 784 5500 When programming the Timing Board the Imager Board must be disconnected from the Timing Board before power is applied If the Imager Board is connected to the Timing Board during the reprogramming of the Altera PLD damage to the Imager Board will occur Purchasers of an Evaluation B
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