ARM9 System on Module Hardware user manual
Contents
1. Signal Alternate Option A Option B Option C SO Power REMARK DIMM PDO NANDOE NA 3 3V NAND PD1 NANDWE NA 3 3V NAND PD2 NANDALE NA 3 3V NAND PD3 NANDCLE NA 3 3V NAND PD4 NCS3 NA 3 3V NAND PD5 NWAIT NA 3 3V NAND PD6 D16 NA 3 3V NAND PD7 D17 NA 3 3V NAND PD8 D18 NA 3 3V NAND PD9 D19 NA 3 3V NAND PD10 D20 NA 3 3V NAND PD11 D21 NA 3 3V NAND PD12 D22 NA 3 3V NAND PD13 D23 NA 3 3V NAND PD14 D24 79 3 3V MCI1 CD PD15 D25 A20 80 3 3V MCIO CD PD16 D26 A23 81 3 3V PD17 D27 A24 82 3 3V PD18 D28 A25 83 3 3V ENSV A PD19 D29 NCS2 84 3 3V ENSV B PD20 D30 54 85 3 3V EN5V C 21 031 NCS5 NA 3 3V 20 AT 901 Hardware 1 0 Table 3 PIO D Signal Options CPSHIRATECH 3 6 2 Ports Allocation SAM9 X35 Signal Alternate Option A Option B Option C re Power REMARK DIM PAO USARTO TX SPI1 NPCS1 89 PA1 USARTO RX SPIO NPCS2 90 3 3V PA2 USARTO D1 91 3 3V RTS PA3 USARTO MCI 02 ETX1 92 3 3V CTS PA4 USARTO MCI1 D3 ETXER 93 3 3V CLK PA5 USART1 TX CAN1 TX 115 3 3V PA6 USART1 RX CAN1 116 3 3V PA7 USART2 TX SPIO NPCS1 100 3 3V PA8 USART2 RX SPI1 NPCSO 101 3 3V PA9 DGB RX CANORX 118 33V PA10 DBG TX CANO TX 119 3 3V PA11 SPIO MISO MCI DO 95 3 3V PA12 SPIO MOSI MCI1 CDA 96 3 3V PA13 SPIO SPCK2. COPSHIRATECH Signal Alternate Option A Option B Option C SO Power REMARK DIMM PCO LCDATO l2C1 D 129 3 3V PC1 LCDAT1 l2C1 130 3 3V PC2 LCDAT2 TIOA3 131 3 3V PC3 LCDAT3 TIOB3 132 3 3V PC4 LCDAT4 TCLK3 133 3 3V PC5 LCDAT5 TIOA4 134 3 3V PC6 LCDAT6 TIOB4 136 3 3V PC7 LCDAT7 TCLK4 137 13V PC8 LCDAT8 UARTO TX 138 3 3V PC9 LCDAT9 UARTO RX 139 PC10 LCDAT10 PMWO 140 3 3V PC11 LCDAT11 PMW1 141 3 3V PC12 LCDAT12 TIOAS 143 3 3V PC13 LCDAT13 TIOB5 144 3 3V PC14 LCDAT14 5 145 3 3V PC15 LCDAT15 PCKO 146 3 3V PC16 LCDAT16 UART1 TX 148 3 3V PC17 LCDAT17 UART1 RX 149 3 3V PC18 LCDAT18 PMWO 150 PC19 LCDAT19 PMW1 151 3 3V PC20 LCDAT20 PMW2 152 3 3V PC21 LCDAT21 PMW3 153 22 LCDAT22 155 3 3V PC23 LCDAT23 156 3 3V 24 LCDDISP 157 3 3V PC25 158 3 3V PC26 LCDPWM 159 3 3V PC27 LCDVSYN USART1 160 3 3V C RTS PC28 LCDHSYN USART1 162 3 3V CTS PC29 LCDDEN 163 3 3V PC30 LCDPCK 164 PC31 FIQ PCK1 165 3 3V 23 AT 901 Hardware 1 0 Table 6 PIO C Signal Options COCPSHIRATECH Signal Alternate Option A Option B Option C SO Power REMARK DIMM PDO NANDOE NA 3 3V PD1 NANDWE NA 3 3V PD2 NANDALE 3 3V PD3
3. DE 12 3 4 Debug OPTIONS 13 3 4 1 JTAG Interface eet eese dried EE 13 3 442 Debug nterface e 14 3 5 uideor EE 14 955315 Elene desee a e eL E cere eL ies 14 a pi M M M 14 353 UB Leer 15 354 15 2 AT 901 Hardware 1 0 COPSHIRATECH SRM IER 15 3 56 VARD ERR 16 3 527 ian 16 3 6 GPIO Ports AllOCat ERE 17 3 6 1 Ports Allocation SAM9 G25 17 3 6 2 Ports Allocation 9 5 21 3 7 LL RE 24 3 901 Hardware 1 0 COPSHIRATECH 1 Introduction The AT 901 is an industrial embedded System On Module using the latest ARM and Linux technology It is designed to serve as the controller and processing building block for embedded devices in applications such as medical devices communications and industrial automation The module can be provided with several levels of software integration starting from an out of the box Debian Linux and up to a full software solution Features e Using the SAM9Gx 400Mhz from Atmel offering a unique combination of an ARM9 processor comb
4. CK 97 3 3V PA14 SPIO NPCSO 98 3 3V PA15 MCIO DO 108 3 3V PA16 MCIO CDA 109 33V PA17 MCIO CK 110 3 18 MCIO D1 111 3 3V PA19 MCIO D2 112 199 20 MCIO D3 113 3 3v 21 TIOAO SPI1 MISO 102 3 3v PA22 TIOA1 SPI1 MOSI 103 3 3V PA23 TIOA2 SPI1 SPK 104 3 3V PA24 TCLKO TK 120 33V PA25 TCLK1 TF 121 3 3V PA26 TCLK2 TD EE PA27 TIOBO RD 123 3 3V PA28 TIOB1 RK 124 3 3V PA29 TIOB2 RF 125 3 3V PA30 l2Co D NPCS3 EMDC 106 3 3V PA31 2 0 SPI1 NPCS2 ETXEN 105 3 3V 21 AT 901 Hardware 1 0 Table 4 PIO A Signal Options CPSHIRATECH Signal Alternate Option A Option B Option C SO Power REMARK DIMM PBO USART2 NA VDDANA RTS PB1 ETHO RX1 USART2 NA VDDANA CTS PB2 ETHO RXER USART2 CK NA VDDANA PB3 RXDV SPIO NPCS3 NA VDDANA PB4 TXCK 1262 NA VDDANA PB5 2 2 CLK 174 VDDANA PB6 AD7 ETHO MDC 175 VDDANA PB7 AD8 ETHO TXEN NA VDDANA PB8 AD9 ETHO TXER NA VDDANA PB9 AD10 PCK1 NA VDDANA PB10 AD11 ETHO TX1 PCKO NA VDDANA PB11 ADO ETHO TX2 PMWO 181 VDDANA PB12 AD1 PMW1 182 VDDANA PB13 AD2 ETHO RX2 PMW2 183 VDDANA PB14 AD3 ETHO RX3 PMW3 184 VDDANA PB15 AD4 ETHO RXCK 185 VDDANA PB16 AD5 ETHO CRS 186 VDDANA PB17 AD6 ETHO COL 187 VDDANA PB18 IRQ ADTRG 189 VDDANA 22 AT 901 Hardware 1 0 Table 5 PIO B Signal Options
5. For full data sheet use the following links http www atmel com devices SAM9G25 aspx tab documents http www atmel com devices SAM9X35 aspx tab documents 2 2 2 Memories The AT 901 includes several types of memory for supporting booting program execution and ID The following figure describes the memories available on the AT 901 5 AT 901 Hardware 1 0 COPSHIRATECH 2 GBits 133 MHz 16 Bits 8 Bits 2 GBits 12C 1 Kbits One Wire MMCO 4 Bits AT 901 Memory configuration 2 2 2 1 DDR2 The AT 901 a incorporate a 16 bits wide DDR2 for its program execution The following are the DDR2 main features e Up to 2GBits 16 bits data bus Support for 8 banks Up to 133 MHz clock Uses CS1 ODT not supported OCD not supported The default configuration includes 128M bytes it can be enlarge to 256M bytes ordering option 2 2 2 2 flash The AT 901 incorporates 8 bits wide NAND flash The NAND is an SLC raw data NAND It stores the AT 901 second level boot in a secured sector and 2 last versions of the application SW It uses data signals D 16 23 The main features of the NAND flash 8 bits data bus e Up to 2Gbits memory volume 6 AT 901 Hardware 1 0 COPSHIRATECH CS3 Uses data bits D 16 23 3 3V interfaces The default configuration is 256M bytes Note The SOM s NAND flash is from Toshiba Any assembled flash need to be either from Toshiba or
6. NANDCLE 3 3V PD4 NCS3 NA 3 3V PD5 NWAIT NA 3 3V PD6 D16 NA 3 3V PD7 D17 NA 3 3V PD8 D18 NA 3 3V PD9 D19 NA 3 3V PD10 D20 NA 3 3V PD11 D21 NA 3 3V PD12 D22 NA 3 3V 023 3 3V PD14 D24 79 3 3V PD15 D25 A20 80 3 3V PD16 D26 A23 81 3 3V PD17 D27 A24 82 3 3V PD18 D28 A25 83 3 3V PD19 D29 NCS2 84 3 3V PD20 D30 NCS4 85 3 3V PD21 D31 NCS5 NA 3 3V Table 7 PIO D Signal Options 3 7 Identification The SOM ID and version is programmed in the 1 Wire EEPROM 24 AT 901 Hardware 1 0
7. to support the ONFI JEDEG standard 2 2 2 3 Micro SD The AT 901 has an option to run the software from a Micro SD It uses MCO of the PROCESSOR with up to 4 data lines The Micro SD is connected through the SO DIMM 200 connector 2 2 2 4 Other memory devices o Aone wire device which holds a build in unique ID along with board information o The AT 901 has an EEPROM option Currently not available 2 3 Buildin Ethernet interface The AT 901 supports a build in Fast Ethernet interface including a build in physical layer transceiver PHY The transceiver uses an RMII interface to interconnect with the processor s Ethernet port 0 The following figure describes the Fast Ethernet interface 2xTX TX Controls 50 Mhz 2x RX_ __RX Controls Int __NReset Fast Ethernet RMII Interface The RMII interface is running at 50 MHz The 50 MHz clock is generated by the Fast Ethernet PHY PB 8 of the PROCESSOR uses as an interrupt input for the Fast Ethernet PHY 7 AT 901 Hardware 1 0 COPSHIRATECH The Fast Ethernet PHY analog signals TX RX are connected the SO DIMM edge connector Two led signal from the FE PHY are also connected to the SOM edge connector Notes e The FE interface has a separate power plane that is separated from the common digital plane It sources from the edge connector VDDANA An additional Ethernet interface is availabl
8. AT 901 9 System on Module Hardware user manual Revision 1 0 CPSHIRATECH Contents T MONNA 4 2 AT 901 internal hardware description essere 4 21 BO Diagrams amd EN p M M M E IE 4 2 2 pie oT NL 5 2 2 1 926 5 5 sae aix er tor 5 222 vanns navna 5 2 2221 oC 6 22 22 NAND flash anne 6 2 2 2 3 MICOS mE 7 2 2 2 4 7 2 3 Build in Ethernet Interface oreet nete ertet de eti tan 7 2 4 Power Sc crt 8 2 4 MEME 8 242 UE 8 2 4 2 1 Power signals on the SO DIMM enne neni nnns nnns 9 2422 B ckupbaten vaare 10 2 5 Extension connector oo eie Eee 10 3 Hardware Software 11 3 1 pa D D Vd n 11 3 2 Interrupt amp 11 3 3 Booting SEQUENCE
9. DDANA PB13 AD2 ETHO RX2 PMW2 183 VDDANA PB14 AD3 ETHO RX3 PMW3 184 VDDANA PB15 AD4 ETHO RXCK 185 VDDANA PB16 AD5 ETHO CRS 186 VDDANA VBUS Sense PB17 AD6 ETHO COL 187 VDDANA Over Current PB18 IRQ ADTRG 189 VDDANA 18 AT 901 Hardware 1 0 Table 1 PIO B Signal Options Signal Alternate Option A Option B Option C SO Power REMARK DIMM PCO ISI DO I2C1D 129 3 3V PC1 ISI D1 I2C1 CK 130 3 3V PC2 ISI D2 TIOA3 131 3 3V PC3 ISI D3 TIOB3 132 3 3V PCA ISI D4 TCLK3 133 3 3V PC5 ISI D5 4 134 3 3V PC6 ISI D6 4 136 3 3V PC7 ISI D7 TCLK4 137 3 3V PC8 ISI D8 UARTO TX 138 3 3V PC9 ISI D9 UARTO RX 139 3 3V PC10 ISI D10 PMWO 140 3 3V PC11 ISI D11 PMW1 141 3 3V PC12 ISI PCK 5 143 3 3V PC13 ISI VSYNC TIOB5 144 3 3V PC14 ISIHSYNC TCLK5 145 3 3V PC15 ISI MCK PCKO 146 3 3V PC16 UART1 TX 148 3 3V PC17 UART1 RX 149 3 3V PC18 PMWO 150 3 3V PC19 PMW1 151 3 3V PC20 PMW2 152 3 3V PC21 PMW3 153 22 USART3 TX 155 3 3V PC23 USART3 RX 156 3 3V PC24 USART3 157 3 3V RTS PC25 USART3 158 3 3V CTS PC26 USART3 159 3 3V SCK PC27 USART1 160 3 3V RTS PC28 USART1 162 3 3V CTS PC29 USART1 163 3 3V SCK PC30 164 3 3V PC31 FIQ PCK1 165 3 3V 19 AT 901 Hardware 1 0 Table 2 PIO C Signal Options
10. PA11 SPIO MISO MCI DO 95 3 3V PA12 SPIO MOSI CDA 96 3 3V PA13 SPIO SPCK MCH CK 97 3 3V PA14 SPIO NPCSO 98 3 3V PA15 MCIO DO 108 3 3V uSD Card PA16 MCIO CDA 109 3 3V uSD Card PA17 MCIO CK 110 3 3V uSD Card PA18 MCIO D1 111 3 3V uSD Card PA19 MCIO D2 112 3 3V uSD Card PA20 MCIO D3 113 3 3V uSD Card 21 TIOAO SPI1 MISO 102 3 3V PA22 TIOA1 MOSI 103 3 3V PA23 TIOA2 SPK 104 3 3V PA24 TCLKO TK 120 3 3V PA25 TCLK1 TF 121 3 3V PA26 TCLK2 TD 122 3 3V PA27 TIOBO RD 123 3 3V PA28 TIOB1 RK 124 3 3V PA29 TIOB2 RF 125 3 3V PA30 2 0 D NPCS3 EMDC 106 3 3V PA31 2 0 CK NPCS2 105 3 3V 17 AT 901 Hardware 1 0 Table A signal Options CPSHIRATECH Signal Alternate Option A Option B Option C 50 REMARK DIMM PBO ETHO RXO USART2 NA VDDANA RMII RTS PB1 ETHO RX1 USART2 NA VDDANA ETHORMII CTS PB2 ETHO RXER USART2 CK NA VDDANA ETHORMII PB3 RXDV SPIO NPCS3 NA VDDANA ETHORMII PB4 TXCK 1262 NA VDDANA ETHORMII PB5 MDIO 12 2 CLK 174 VDDANA ETHORMII PB6 AD7 ETHO MDC 175 VDDANA ETHORMII PB7 AD8 ETHO TXEN NA VDDANA ETHORMII 8 AD9 ETHO TXER NA VDDANA ETHO Int PB9 AD10 ETHO TXO PCK1 NA VDDANA ETHORMII PB10 AD11 ETHO TX1 PCKO NA VDDANA ETHORMII PB11 ADO ETHO TX2 PMWO 181 VDDANA PB12 AD1 TX3 PMW1 182 V
11. ccess address to the 1010001 EEPROM Table 1 HW Configured After Reset 3 2 Interrupt amp I O Table The following table describes the AT 901 dedicated I O configuration Some of the configurations are valid only when the relevant interfaces are assembled e g Ethernet and USB When not assembled these pins can be used as l Os 11 AT 901 Hardware 1 0 CODSHIRATECH Signal Description Remarks EO INTR PB 8 Ethernet 0 interrupt Active Low E1 INTR PC 26 Ethernet 1 interrupt Active Low MCIO CD PD 15 uSD card detect 0 Card in 1 No CD PD 14 SD card detect 0 Card in 1 No card VBUS Sense 16 USB port A power sense 0 No power sensed 1 Power sensed OverCur USB PB 17 USB port A or Port B over Open Drain current ENSV HDA PD 18 USB port A power drive enable 0 Enable 1 Disable Default ENSV HDB 19 USB port B power drive enable 0 Enable 1 Disable Default ENSV HDC PD 20 USB port C power drive enable 0 Enable 1 Disable Default Table 2 Configured I O and Interrupts NOTE More interrupts are available through the PROCESSOR I O pins and can be configured according to the user application 3 3 Booting Sequence The AT 901 has 3 boot phases e First level boot loader running from internal ROM e Device configuration running from internal RAM e SW downloads from NVRAM NAND or SD Car
12. ce The SAM 9 integrates an internal debug controller with UART interface TX and RX signals only 3 5 Interfaces 3 5 1 Ethernet The SAM9 G25 X35 support a single dual Fast Ethernet interfaces Each interface has its own MDC MDIO controller The default PHY address is 0001 for both interfaces The MDC frequency is derived from the system clock and should not exceed 2 5MHz 3 5 2 126 There are up to three I2C interfaces dependent on PIO utilization The main features are Bit Rate Up to 400 Kbits Transfers in Master Mode Only Standard Compliances One Two or Three Bytes for Slave Address Sequential Read write Operations Master Multi master and Slave Mode Operation General Call Supported in Slave mode SMBUS Quick Command Supported in Master Mode Connection to DMA Controller DMA Channel Capabilities optimizes Data I2C Standard Atmel TWI Standard Mode Speed 100 KHz Supported Supported Fast Mode Speed 400 KHz 7 or 10 bits Slave Addressing START BYTE Supported Not Supported Repeated Start Sr Condition ACK and NACK Management Supported Supported Slope control and input filtering Fast mode Clock stretching Not Supported Supported Multi Master Capability Note 1 START b000000001 Ack Sr 14 AT 901 Hardware 1 0 Supported COPSHIRATECH 3 5 3 USB The AT 901 supports three 2 0 USB interfaces Port A can be used as a Host or a Device inter
13. d to DDR2 and execution After POR the processor runs the First Level Boot loader program stored in its internal ROM The program configures the SAM 9 clocks and looks for executable program in one of the non volatile memories See SAM 9 datasheet for a valid code for each of the optional memories The optional memories are Default Micro SD card Carrier e Serial NOR Carrier The following figure describes the optional boot memories and its priorities 12 AT 901 Hardware 1 0 COPSHIRATECH vcc Carrier som Figure 2 Boot Sequancing Priority If the First Level Boot Loader doesn t find an executable program in one of the non volatile memories it configures the Debug port RS 232 and the USB port Port 0 as device to wait for external program download from the PC For more information see the Atmel s boot sequencing chapter in the SAM 9 datasheet 3 4 Debug Options The SOM has two options for debug e JTAG Connector Debug interface PA 9 PA 10 Both debug options are available on the SO DIMM 200 edge connector 3 4 1 JTAG Interface A standard interface which can be used for the following options Debug using off the shelf Atmel s ICE Default e Standard JTAG emulation 13 AT 901 Hardware 1 0 COPSHIRATECH Choosing between the options is done by asserting the JTAGSEL signal available on the SO DIMM edge connector 3 4 2 Debug Interfa
14. e using the X25 version of the processor The interface available on the edge connector for the second Ethernet port will be RMII 2 4 Power amp Reset 2 4 1 Reset The AT 901 integrates an internal Power On Reset POR controller It monitors the power and drive the internal and external reset The NRST can be used as input for resetting the processor In that case the external reset should be an open drain solution asserted only when a reset action is required see the figure below The NRST can be used also as a programmable length reset for the carrier board between 60 us and 2 seconds Note A pull up resistor for the NRST is assembled on the carrier board PU Push Button NReset Reset mechanism 2 4 2 Power The power to the AT 901 module is coming from SO DIMM 200 edge connector The main power is a 3 3V 595 which generates all other powers 8 AT 901 Hardware 1 0 COPSHIRATECH Power Enable 3 3V 3 3 V 2 3A gt 1 0 562560 11 DDR TPS62560 TI Core TPS71710 TI PLL AT 901 Power Hierarchy The available power levels used are as follows e The 1V is used to power the processor internal core and the e 1 8V is used for to power the DDR2 interfaces e All I O signals are fed from the 3 3V power supply 2 4 2 1 Power signals on the SO DIMM connector The power signals VDDIOPO and VDDNF should be connected directly to the 3 3V powe
15. es Multidrop communications are also supported through address bit handling in reception and transmission 3 5 6 UART The Universal Asynchronous Receiver Transmitter features a two pin UART that can be used for communication and trace purposes Moreover the association with two DMA controller channels permits packet handling for these tasks with processor time reduced to a minimum 3 5 7 HSMCI The High Speed Multi Media Card Interface HSMCI supports the Multi Media Card Specification V4 3 the SD Memory Card Specification V2 0 the SDIO V2 0 specification and CE ATA V1 1 16 AT 901 Hardware 1 0 3 6 GPIO Ports Allocation The processor has several flavors each with a different set of optional interfaces The following tables describe the interfaces available in each option In bold are the FIXED options that can t be changed 3 6 1 Ports Allocation SAM9 G25 Signal Alternate Option A Option B Option C SO Power REMARK DIMM PAO USARTO TX SPI1 NPCS1 89 3 3V PA1 USARTO SPIO NPCS2 90 3 3V PA2 USARTO MCH D1 ETXO 91 3 3V RTS PA3 USARTO MCI D2 ETX1 92 3 3V CTS PA4 USARTO MCI D3 ETXER 93 3 3V CLK PA5 USART1 TX 115 3 3V PA6 USART1 RX 116 3 3V PA7 USART2 TX SPIO NPCS1 100 3 3V PA8 USART2 RX SPI1 NPCSO 101 3 3V PA9 DGB RX 118 3 3V PA10 DBG TX 119 3 3V
16. face and port B as a Host interface both support high speed operation and port C which support only full speed operation only 12Mbps The 5V power supply for the USB ports is SW Controlled and should be enable according to the application When Port A is used as a device Configurable the USB interface can sense if the Host device drives the USB power bus The following figure describes the USB interfaces USB 2 0 Host Device Figure 3 USB interfaces 3 5 4 SPI The Serial Peripheral Interface SPI circuit is a synchronous serial data link that provides communication with external devices in Master or Slave Mode It also enables communication between processors if an external processor is connected to the system There are up to two SPI interfaces depending on configuration Both interfaces are available on the SO DIMM 200 connector 3 5 5 USART The Universal Synchronous Asynchronous Receiver Transceiver USART provides one full duplex universal synchronous asynchronous serial link Data frame format is widely programmable data length parity number of stop bits to support a maximum of standards The receiver implements parity error framing error and overrun error detection The receiver time out enables handling variable length frames and the 15 AT 901 Hardware 1 0 COPSHIRATECH transmitter time guard facilitates communications with slow remote devic
17. ined with DDR2 for both enhanced performance and low cost solution The card offers two processor types o AT91SAM9G25 AT91SAM9X35 for touch screen and CAN interface support e RAM 128 MB DDR2 Flash 256 MB Flash Alarge variety of internal interfaces over a 200 pin SO DIMM 2 AT 901 internal hardware description 2 1 Block Diagram The following figure describes the AT 901 block diagram Options 1xRMII 4 x UART RX TX CTS RTS 2 x SPI CS 2x SD MMC card 2 12 8xAtoD 40 1 05 Other 3 3V AT 901 Block Diagram 4 AT 901 Hardware 1 0 CPSHIRATECH The AT 901 block diagram includes AT 901 system e AT 901 FE interface AT 901 power amp Reset AT 901 extension connector The following paragraphs describe each part of the system in details 2 2 AT 901 System 2 2 1 ARM 926EJ S Processor AT 901 uses Atmel s SAM 9 ARMO based series The SAM 9 is a family of processors which uses an enhanced version of the ARM 926EJ S processor The SAM 9 support different flavors e g Single dual Ethernet enhanced graphic accelerator LCD and more those flavors are footprint compatible and can be supported by the AT 901 module The SAM 9 main features are 400 MHZ core frequency 400 MIPS 16 Kbytes data and instruction cache System running at 133 MHz Integrated RTC POR and WDT Low power mode Multiplex peripherals bus 217 pins BGA package
18. ot all options are available at the same time The options are preconfigured by the software The main supported interfaces are e Up to 3 USART supporting TX RX CTS and RTS Upto 3 UART supporting TX RX only one of them is a debug port as well 10 AT 901 Hardware 1 0 CPSHIRATECH 0010 2 Fast Ethernet port an additional Ethernet port is available only with the X25 version different ordering option o Port 0 TX RX o Port1 RMII Up to 2 SPI interfaces with 2 Chip Select each Up to two 2 interfaces Up to 2 SDIO MMC ports supporting 4 data bits each Up to 6 A to D convertors with 10 bits resolution and 100 KHz sampling rate Other optional interfaces are o LCD monitor X35 only o Touch screen X35 only o Audio o CANinterface X35 only o Others GPIOs any un used pin can be configured as a GPIO for various control and monitor functions 3 Hardware Software interface 3 1 Hardware Configuration During power up some bits status is latch to configure the CPU The following table describes the bits and their functionality Signal Description Default BMS 0 Booting from CSO using parallel The AT 901 is always boot SOM NOR from the internal ROM 1 Booting from internal ROM JTAG Select 0 Normal JTAG chain According to the pin Carrier 1 ICE mode connected to the connector Address The access address to the Ethernet 0 0001 PHY EEPROM 2C The a
19. r plane VDDANA power for Analog interfaces should be connected to the 3 3V plane using a filter The VBAT pin on the SO DIMM connector should be either connected to an external battery located on the carrier board or shortens to 3 3V power source e ADREF is the A D reference voltage if not used connect directly to 3 3V 9 AT 901 Hardware 1 0 COPSHIRATECH 2 4 2 2 Backup battery The AT 901 has an option for build in backup power source for the Real Time Clock connected to the VDDBU pin of the processor The backup power device monitors the main power level and when it drops below a configurable threshold it switch to its internal power source On normal operation the device charges the internal power source using the main power input When installed the battery supports an approximately 1 hour work of the RTC and backup section of the processor when the main power fails Contact sales shiratech com for more information Note When using the option of a SoM with a build in battery the VBAT pin on the SO DIMM connector should be left un connected The following figure describes the AT 901 backup power MEN gt VDDIOPO VDDNF Shutdown WakeUp Figure 1 AT 901 Backup Power 2 5 Extension connector The AT 901 support varieties of interfaces through the SO DIMM 200 edge connector Some of the interfaces are multiplexed with other interfaces on the PROCESSOR processor and thus n
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