Power Model User`s Manual
Contents
1. 0 Leakage power from unused subblocks 0 W Power dissipated by this block 6 50786e 05 w Total Logic Block energy 0 000170879 w Description L BP ower echo contains information regarding the power dissipated by each logic block Following with the keyword block number is the number of a specific block Then a list of the subblocks included in this block is shown After that the number of unused subblocks in this block and the amount of leakage power from those unused subblocks are provided The power dissipated by this block consists of the power dissipated by subblocks and local connections inside the block Finally the total power dissipated by all the logic blocks CLBs in the circuits is listed 24 5 34 CLKPower echo File format Clock Network 0 Power 0 000312861 Delay 8 00063e 11 Description Currently the power model can only handle one clock network However multiple clock networks may be included in this power model in the future To investigate the power consumption of each clock network the CL K Power echo is provided Following the keyword Clock N etwork is the number of this particular clock network its power dissipation in Watt and the clock delay in seconds The clock delay is calculated by adding the clock buffer delay with the clock wire delay along the path from the clock input to the input of a CLB The clock skew has not been considered in this model The clock delay provided is only a2. K W Poon Power Estimation For Field Programmable Gate Arrays Master s Thesis University of British Columbia August 2002 7 E M Sentovich K J Singh C Moon H Savoj R K Brayton and A L Sangiovanni Vincentelli Sequential Circuit Design Using Synthesis and Optimization ICCD pp 328 333 1992 26
3. are listed below Option Description activity_in lt input activity file gt The input activity file ad which was generated by the activity estimator activity_out lt output activity The output activity file ac2 which contains the file gt switching activity information for each logic block This file will be ported to VPR later function_out lt function output gt The function output file fun which contains the configuration bits for each look up table in the logic blocks This piece of information will be used by VPR for power estimation 17 4 2 Output Activity File Format ac2 File Format global_net_probability clk 0 5 global_net_density clk 2 0 intercluster_probability a 0 intercluster_net_density a 0 intercluster_net_probability intercluster_net_density b 0 intercluster_net_probability intercluster_net_density z 0 ON WON o subblock_probability z subblock_density z 0 2 oo NO oo oo Su oo nS 00 57 On 03 05 Description The act2 will be used by VPR later on in the flow Each global net in the design has its corresponding global net probability and global net density lines Following the keyword global net probability or global net density the probability or the transition density value corresponding to the global net is listed Nets that connect clusters ie use the general purpose routing are listed usingintercluster net probability and interduster net density lines T
4. in the circuit by applying logic simulation It consists of two parts a vector generator and a logic simulator 3 3 1 Vector Generator The vector generator provides input vectors for the logic simulator Users can specify their own vectors instead but it would be more convenient to generate the vector file automatically using this vector generator Users can pipe the output to a vector file as an input file of the logic simulator To run the vector generator use the following command vecgen lt overall activity gt lt num of primary inputs gt lt num of vectors gt lt correlation gt gt lt vector_ file gt lt overall_activity gt Switching activity transition density at the primary inputs lt num_of primary inputs gt Number of primary inputs in the circuit lt num_of_vectors gt Number of vectors generated Note Using a larger number of vectors would increase the simulation time but the simulation results should be more accurate lt correlation gt The correlation between the primary inputs The value is between 0 and 1 A value of zero means the inputs are not correlated to each other whereas a value of one indicates the inputs are 100 correlated 3 3 2 Logic Simulator Commands Before executing any logic simulator commands in SIS the benchmark circuit in blif format has to be input to SIS first by using the following command read_blif lt benchmark blif gt 14 Here is the list of logic simu
5. written in C contains the VPR source code written in C Note A demo is available with the power model source code to help you understand the power estimation flow in VPR To run the demo execute the run_sample shell script in your new powermodel directory after you finish the compilation 10 3 Activity Generation Switching activities of the nodes in the benchmark circuit can be generated either by activity estimator using Transition D ensity Model 3 or by logic simulator using logic simulation The following are the commands for these two methods 3 1 Activity Estimator 3 11 Commands The activity estimator takes a technology mapped netlist of look up tables LUTs and flip flops in blif format and determines the switching activity of each node in the circuit by applying the transition density model To run the activity estimator use the following command ace f lt input blif gt o lt text output file gt n lt activity output file gt other options f lt input blif gt The input blif file contains the netlist for a specific circuit These files can be obtained from Microelectronics Center of North Carolina MCNC 0 lt text output file gt The text output file txt contains activity information in a readable format for user s reference only n lt activity output The activity output file ac contains activity information file gt which will be used by T V pack later e lt float gt error to
6. 0 Gate Delay including wire and attached capacitances ns Figure 3 1 Glitch width versus gate delay 3 3 3 Logic Simulator Output Format act File format a 0 500000 0 500000 b 0 500000 0 500000 c 0 937500 0 250000 d 0 984375 0 093750 Description The output activity file generated by the logic simulator is the same as that generated by the activity estimator of logic simulator As a result this output file can also be imported to T V Pack later on The first column is the name of the node the second and third columns list the corresponding static probability and transition density of each node respectively 4 Modified T VPack 4 1 Commands T V Pack takes the same technology mapped netlist in blif format as the one used for the activity estimator as its input and packs the look up table into clusters logic blocks For the power model T V Pack is employed to match the input switching activity information ac file produced by the activity estimator in section 3 with the inputs and outputs of the logic blocks 16 To run T V Pack use the following command t vpack lt input blif gt lt output net gt activity_in lt input activity file gt activity_out lt output activity file gt function_out lt function output gt other options Please refer to the VPR user s manual for the descriptions of the other options for this command To execute the power model three additional options are required These options
7. Power Model User s Manual Version 1 1 Prepared by Kara Poon July 30 2003 University of British Columbia Table of Content 1 APA O 4 1 1 WALL A ias 4 1 2 PIETER as 5 1 3 LLAMEWOI an 6 13 1 Original Pram ew Ori sisal Ae O A LO AA 6 1 3 2 Modified Framework ienna n O E E N EA A 7 2 A O 8 2 1 SEU O ey 8 2 2 BYA VIR A E REE EE T E T EEE E EES 9 3 Activity AAA si i ie ssri sasoe is noioso t sess rS sas ToS soa esoo S ESS 11 3 1 PL CLEV IL YE SELIM OF eann E E A E E A REE tae 11 3 1 1 ETAn TAa TEN aTa SR AE S EEEE EE EARE AT 11 E AEE ESE 12 3 2 1 Text Output File Format Ctx sssccssscsccsescssecvevsncoevecessnacevusenssesivovesacavsoussvessnesevsnvscivesnssvuvesneveusvesensvenses 12 3 2 2 Activity Output File Format ACE ooniciononinonconnncncnnconcncononcncnnanonon cn ronononcncononon conan oran coronan ones 13 3 3 Lar ia 14 3 3 1 Vector edo E e e eaae rE E Ee ENS 14 3 3 2 Logic Simulator Comm ii direis 14 3 3 3 Logic Simulator Output Format ACE occ csssesesessesesesesseseseetesesesesneseseesssesieseeceseseaesesneeseseees 16 4 Moditicd TV Pack nn sonsaeseasdsnedencoshenosessoussabesptndachsos ncnsosonns E SES TOEA NEES 16 4 1 COMAS A bi 16 4 2 Output Activity File Format Oc2 oococicoononnssonnssssssrsoniriononirinononananonononanonononanononananonononanononeninonoss 18 4 3 Output Function File Format fUN ococicicocionnnonnnonanininananinanananananananananananananonanananananananananananananananons 18 5 M
8. bination with VPACK or TVACK a logic block packing tool which packs each logic block to capacity and minimizes the number of inter cluster connections on the critical path 1 13 1 Original Framework VPR has two components a place and route tool and a detailed area and delay model See Figure 1 2 The place and route tool maps a circuit to an FPGA The area and delay models estimate the area and critical path delay based on results from the place and route tool The two components interact with each other to determine the best placement and routing for a user circuit A description of the underlying FPGA architecture is provided to the tool in the form of an architecture file which contains information such as segment length connection topologies logic block size and composition and process parameters User Circuit Architecture Description Detailed Area Delay Model Place and Route Tool Area Speed Estimates Figure 1 2 VPR framework 13 2 Modified Framework Figure 1 3 shows the VPR framework with the new power model In this framework the power model is part of the area and delay model An activity generator either the activity estimator or the logic simulator has been incorporated in the framework to estimate the switching frequencies of all nodes in the circuit In the current implementation the activity estimator and the power model are not used to guide the placement and routing It estimates the power con
9. e the logic simulator in SIS To run the sample script go to the sample directory and type the following commands run_vecgen lt sis executable gt lt sample sis command 2 2 Setup VPR This section shows you how to install the activity estimator and the power model The activity estimator is a stand alone program but the power model is incorporated in VPR 1 Make a new directory called powermodel 2 Go to the following site and download the version 4 30 of VPR to the powermodel directory The uncompressed version is recommended The site is http www eecg toronto edu vaughn vpr vpr html 3 Copy the powermodel_version_vpr tar under the powermodel_version directory to the powermodel directory Y our powermodel directory should now contain two tar files vpr_430 tar and powermodel_version_vpr tar 4 Decompress the vpr 430 tar file first and then decompress the powermodel_version_vpr tar file Y ou could use the following command to extract the files tar xvf lt tar_file name gt Run the setup_powermodel Perl script This script completes the compilation of the activity estimator T V pack and V PR automatically for you The script assumes that you are running a Solaris based machine and g and gx compilers are available If your compilers are different you may have to make some modifications to the mak efile situated in each of the following sub directories r ac contains the T V pack source code
10. he format of each of these lines is the same astheglobal net probability or global net density lines Each subblock LUT and or FF has its corresponding subblock probability and subblock density lines Following the keyword subblock probability or subblock density the subblock name is listed Then the activities of all inputs are then listed followed by the clock static probability or clock transition density Then the probability or transition density of the node between the LUT and flip flop if there is both a LUT and flip flop used within this subblock is listed this number is 0 if a flip flop is not used Finally the activity of the output is listed 4 3 Output Function File Format fun File Format subblock_function sb1 0011111111111111 subblock_function sb2 0011111111111111 Description The file will also be used by VPR in the power estimation flow Following the keyword subblock function is the name of the subblock and the corresponding logic function implemented in the subblock 18 5 Modified VPR 5 1 Commands To run VPR with the power model use the following command vpr lt circuit net gt lt fpga arch gt lt placed out gt lt routed out gt activity_file lt input activity file gt function_file lt input function file gt other VPR options Please refer to the VPR user manual 1 for other VPR options Two additional options have been added for power analysis activity_file lt input ac
11. lator commands to set the delay of gates in the input circuit Command Description Is_zero_delay Set the delay of all the gates to zero Is random_logic_delay lt base delay value gt Randomly generate the delay for all the gates based on the base delay value Is_logic_delay lt num gt Set the delay of all gates as a specific value num Unit seconds After setting the delay value run the logic simulator by typing Is simulate_circuit d lt delay_portion gt f lt filter value gt lt input vector file gt lt output activity file gt Option Description d lt delay portion gt Both parameters are for modeling the filtration of eres glitches by the gate If a signal pulse is shorter than d gate_delay f then the pulse would be filtered out by the gate The equation is derived by plotting the glitch width against the gate delay Figure 3 1 shows the relationship between the glitch width and the gate delay by assuming the glitch is around 50 of the gate delay Based on our HSPICE simulation the slope of the graph d is 0 89 and the y intercept f is 6 4e11 Users can define the values according to the characteristics of their circuits Note the number of simulator cycles is equal to the number of vectors in your input vector files 15 800 T 700 o y 0 89x 64 01 S 600 o D 500 x Oo 9 400 2 S 300 200 2 100 0 100 200 300 400 500 600 700 800 90
12. lerance for the static probability calculation The value has to be between 0 and 1 default 0 05 max number of iterations default 10 output static probability only output transition density only default d p Note Both static probability and transition density are available in the output files by default Y ou need both for T Vpack l lt K gt look up table LUT size ne default 4 s lt float gt static probability for the primary inputs The value is between 0 and 1 default 0 5 11 t lt float gt transition density of the primary inputs default 0 5 r lt float gt rise and fall time expressed as a value relative to the clock period This value is used for the low pass filter mechanism of the Transition D ensity Model 4 6 default 0 1 which means the rise and fall time is 10 of the clock frequency 3 2 3 2 1 Text Output File Format txt File format Number of Luts 10 Lut 0 Input a Static Probability 0 500000 Transition Probability 0 500000 Transition Density 0 500000 Input b Static Probability 0 500000 Transition Probability 0 500000 Transition Density 0 500000 Input c Static Probability 0 937500 Transition Probability 0 117188 Transition Density 0 250000 Output d Static Probability 0 984375 Transition Probability 0 030762 Transition Density 0 093750 Output is high for values 12 3 45 6 7 Order of luts to be done 0 is lu
13. lt float gt Characteristics of an NMOS transistor which includes Description Vth lt float gt Threshold voltage Unit volt CJ lt float gt Area junction capacitance Unit F m CJSW lt float gt Sidewall junction capacitance Unit F m CJSWG lt float gt Zero bias gate edge sidewall bulk junction capacitance Unit F m CGDO lt float gt gate drain overlap capacitance Unit F m COX lt float gt Gate oxide capacitance Unit F m EC lt float gt Piecewise carrier drift velocity These parameters are used in the capacitance model and leakage current calculation described in 6 Pmos Vth lt float gt CJ lt float gt CJSW lt float gt CJSWG lt float gt CGDO lt float gt COX lt float gt EC lt float gt Characteristics of an PMO S transistor similar to those for the NMOS transistor These parameters are used in the capacitance model and leakage current calculation described in 6 20 10 poly Cpoly lt float gt poly_extension lt float gt Characteristics of the polysilicon which are Cpoly lt float gt capacitance of the polysilicon Unit F m poly_extension lt float gt The extension of the polysilicon line Unit m Refer to Figure 5 1 These parameters are used in the capacitance model described in 6 m gt 0 poly_ extension Figure 5 1 Transistor layout min _transistor_size length lt float gt width lt float gt Size of a mini
14. mum transistor length lt float gt channel length see Le in Figure 5 1 Unit m transistor width see W in Figure 5 1 Unit m Vdd lt float gt supply voltage Unit volt Vswing lt float gt swing voltage Unit volt 21 11 Vgs_ for leakage lt float gt Gate source voltage when the transistor is off This parameter is used for leakage current calculation Unit volt 12 SRAM_leakage lt float gt Leakage current inside the SRAM cell Unit Amp 13 short circuit power percentage lt float gt Short circuit power is represented as a percentage of the dynamic power within the circuit For example if this value is set to 0 1 then short circuit power is modeled as 10 of the dynamic power dissipation Note Two architecture sample files 4lut_sanitized arch and 4x4lut_sanitized arch are provided in the samples directory to show you the rmat of the additional parameters However the values in the sample files have been tailored to fulfill the non disclosure agreement that we signed with TSMC 22 5 3 Power Analysis Output Files The following are the formats of the four output files from VPR 5 3 1 Power echo File format Critical_Path 1 08982e 08 layout of FPGA 2 x 2 operation temperature 25 inputs 6 outputs 8 total clbs 3 total global 0 net num 16 block num 17 Power Analysis routing Power 0 000826981 W 62 961876 percent Total Logic Block Power 0 000173622 W 13 218604 pe
15. odified VBR ccssar seisein e o i e ieai iiS 19 5 1 COMMANGES A A ENE E Ble ads ae a aan aa 19 5 2 Architecture File cc scc css scsi epece ts tage a 19 5 3 POWer Analysis Output TUES is 23 5 3 1 Powerechors RN 23 5 3 2 IL r ECNO nein aenn a riai E A E EE EEEE R ENN aS 24 5 3 3 JD AONA A RTE OAE EET E ET E T T 24 5 3 4 A AA OAA T E 25 6 COT A sauce densnsisbesbonatased ugencdusuadaoswasasdcobseacdesuceccosensuscessniness 25 7 REC dae ici 26 1 Introduction The power model is for non commercial use only For commercial use please contact the authors for their consent N ote This manual is for users who are familiar with SIS and VPR SIS is available at http www cad eecs berkeley edu Software software html VPR can be downloaded at http www eecg toronto edu vaughn vpr vpr html The power model is built on top of SIS 7 and VPR CAD tool 1 This manual focuses on how to use the power model For the algorithms and theories applied in the power model please refer to the references in section 6 In this document the italicized words in angled brackets lt gt should be replaced by appropriate file names values or options while the bolded words are keywords 1 1 What is new The first version version 1 0 of this power model was posted online in August 2002 Since then several changes have been made to the original power model Here is the list of the changes Update on version 1 1 1 A logic simulator is added so
16. rcent Clock Power Dissipation 0 000312861 W 23 819517 percent otal Power Dissipation 0 00131346 W Leakage Power Analysis Routing Leakage Power 1 99469e 05 W 1 518652 percent Logic Block Leakage Power 2 74211e 06 W 0 208770 percent Clock Leakage Power 0 W 0 000000 percent Total Leakage Power 2 2689e 05 W 1 727421 percent of the total power dissipation Energy Analysis Routing Energy 9 01257e 12 J Logic Block Energy 1 89216e 12 J Clock Energy 3 4096le 12 J Total Energy 1 43143e 11 J Power Analysis Completed Description Power echo first lists both the overall power including dynamic short circuit and leakage power dissipation from the routing logic blocks and clock network Then it lists only the leakage portion of the overall power Finally it includes an analysis on the energy dissipation for the circuit 23 5 3 2 ROUTING Power echo File format net 0 0 000113028 W Description ROUTIN G Power echo records the power dissipation of each net in the circuit Following the keyword net is the net number and the power dissipation of that particular net 5 3 3 LBPower echo File format xxx Logic Block Power Analysis x x block number 1 subblock name a subblock power 1 02171e 05 W subblock name b subblock power 1 07384e 05 W subblock name c subblock power 1 02171e 05 W subblock name d subblock power 1 23027e 05 W Number of unused subblocks
17. roject First benchmark circuits were optimized and mapped using SIS 4 The mapped netlist are imputed to either an activity estimator or a logic simulator to generate activities for all nodes in the mapped circuits The activity estimator applies the Transitional Density Model 3 a probabilistic method while the logic simulator applies logic simulation for activity generation Afterwards TV Pack groups the LUTs and registers into logic blocks based on the user specified cluster size Then V PR is used to perform placement and routing for the circuits Each circuit is mapped to logic block array with sufficient logic blocks and pads The V PR router determines the minimum number of tracks per channel required to route the circuit The power estimation step has been incorporated in VPR to calculate power dissipation based on the specified architecture 1 stimuli meu Vector File ogic Optimization 2 g Switching echnology Mapping Activity Estimator Stand alone Activity Mapped Information gt Vector Generator Input Stand alone S Logic Simulator SIS Netlist Packing A modified_TVPack Parametized sane VPR Power Estimation IVPR Power Estimates Figure 1 1 Power estimation flow 1 3 Framework This power model is built on top of The Versatile Place and Route VPR CAD tool VPR is a widely used placement and routing tool available for FPGA architectural studies It is used in com
18. rough estimation 6 Conclusion This power model is developed to establish a practical platform for future research on power analysis and optimization within FPG As It consists of a vector generator logic simulator activity estimator and a power model We understand that there is always room for improvement for us to build a more robust power model Your feedbacks and comments about the future development of this power model is invaluable for our team and the FPGA research community Please feel free to let us know about your opinions Thank you for you interest in our power model and good luck on your research 25 7 References 1 V Betz VPR and T VPack User s Manual ver 4 30 March 2000 2 J Cong and Y Ding Flowmap An Optimal Technology Mapping Algorithm for D elay Optimization in Lookup Table Based FPGA Designs IEEE Trans on Computer Aided Design of Integrated Circuits and Systems Vol 13 No 1 pp 1 12 January 1994 3 F N Najm Transition Density A New Measure of Activity in Digital Circuits Texas Instruments Technical Report 7529 0032 August 1991 4 F N Najm Low pass Filter for Computing the Transition D ensity in Digital Circuits IEEE Transactions on ComputerAided Design vol 13 no 9 pp 1123 1131 September 1994 5 K Poon A Yan SJ E Wilton A Flexible Power Model for FPGAs in International Conference on Field Programmable Logic and Applications September 2002 6 K
19. sumption only after placement and routing has occurred However it is possible to use the power estimates to guide the placement and routing process in order to optimize for power User Circuit Architecture Description Place and Route Area Speed Power Estimates Figure 1 3 Framework with power model 2 Setup If you haven t downloaded the powermodel go to the following site and download the latest version of the power model to the powermodel directory The latest version is version 1 1 http www ece ubc ca stevew powermodel html Decompress the lt powermodel_ version tar gt file by typing tar xvf lt powermodel_ version tar gt You should find two tar files powermodel version sis tar and powermodel_version_vpr tar under the powermodel_version directory Note the version in the directory and file names above indicates the current version number of the power model As you may have noticed the current powermodel has two sections one section of the model is incorporated in SIS while the other section is incorporated in VPR As a result these sections have to be installed separately The current version of the power model works on Solaris based Unix machines and it can be compiled using g and ge compilers Y ou may have to make modifications if you use other operation systems or compilers Follow the instructions below to download the software 2 1 Setup SIS This section shows you how to install the
20. t 8 Now printing out the latch names and probability values latchNameln e latchNameOut f inProb 0 455149 outProb 0 455149 12 Description The txt file is for user s reference only It will not be used by T Vpack or V PR The first line indicates the total number of look up tables LUT in the circuit Then the activity information of each LUT is shown In this example a LUT with three inputs a b and c and the output d is illustrated The corresponding static probability transition probability and transition density are also provided in this text file The line with Output is high for values shows the numerical values of the logic functions when the output of the LUT is high After that the order of the LUTs is listed in the file Finally the static probability information of each latch in the circuit is printed at the end of the file 3 2 2 Activity Output File Format act File format a 0 500000 0 500000 b 0 500000 0 500000 c 0 937500 0 250000 d 0 984375 0 093750 Description The act file will be used by T V Pack later on It contains the static probability and transition density information of each node in the circuit The first column is the name of the node the second and third columns list the corresponding static probability and transition density of each node respectively 13 3 3 Logic Simulator The logic simulator takes a technology mapped netlist to determine the switching activity of each node
21. tivity file gt The input activity file ac2 was created by T VPack function_file lt input function The input function file fun was generated by file gt T V Pack 5 2 Architecture File The following are the parameters in the architecture file for power analysis 1 global_clock_num lt int gt Number of global clock network in the circuit The current version of power model can only handle one global H tree clock network 2 clock_network buffer_R lt float gt buffer Cin lt float gt buffer Cout lt float gt Rwire lt float gt Cwire lt float gt Cin_per clb_clock_ pin lt float gt The characteristics of a clock network which includes Parameter Description Dean OO Wire capacitance per unit segment length Cin_per_clb_clock_pin lt float gt Input capacitance for the clock input pin of each logic block 19 CLB_Cwire lt float gt Wire capacitance per segment length for local connections inside the logic block temp lt int gt NMOS NFS lt float gt PMOS NFS lt float gt NFS is the current fitting parameter that determines the slope of the sub threshold current voltage characteristic Specific NFS values are required for both NMOS and PMOS transistors at a particular operation temperature 6 These parameters are used for sub threshold current calculation N mos Vth lt float gt CJ lt float gt CJSW lt float gt CJSWG lt float gt CGDO lt float gt COX lt float gt EC
22. users can generate the switching activity for each node in the benchmark circuits using logic simulation 2 The power model has been revised Here is a list of modified files read arch c read arch h power c power h vpr_types h The following is a list of specific changes read_arch c Added four new functions 1 calc num buffer stages FO desired_stage_effort 2 Calc buffer stage effort N FO 3 Calc internal buffer cap FO desired stage effort 4 Calc internal switch caps num switch types read_arch h Added two function declarations 1 calc num buffer stages FO desired stage effort 2 Calc buffer stage effort N FO N ote these are now used in power c for calculating leak age within buffers power c 1 Modified function find_routing_power to also consider the capacitance between cascaded buffer stages 2 Modified function find_logic_ block power While calculating the leakage power of a logic block the variable unused CLB_ leakage wasn t initialized to 0 0 causing the leakage power to be exagerated 3 Modified function calculate switch leakage Fixed calculation error power h Added two function declarations 1 find cap 2 calculate INV_cap vpr_types h Added one member to the s switch inf structure 1 float Cinternal N ode this new member stores the internal capacitance of a cascaded buffer for the given switch type 1 2 Power Estimation Flow Figure 1 1 shows the power estimation flow employed for this p
23. vector generator and the logic simulator The vector generator is a stand alone program but the logic simulator is incorporated inside SIS Also you may need to download other additional SIS packages such as Flowmap 2 based on the need of your research 1 Download and compile SIS by following the instruction at http www cad eecs berkeley edu Software software html 2 Copy the powermodel_version_sis tar file from the powermodel version directory to the parent directory of SIS 3 Decompress powermodel version_sis tar using the following command tar xvf lt powermodel version sis tar gt Under the parent directory of SIS you should have three new directories which are listed below and a script file named setup_sis pl Contains the source code of the vector generator written in C actsim Contains the source code of the logic simulator which will be moved as a sub directory of the sis directory after running setup_sis pl Contains sample scripts 4 First of all install the vector generator by executing the following commands cd vecgen compile_vecgen cd 5 Then install the logic simulator by executing the setup_sis pl script in the parent directory using perl setup_sis pl 6 Recompile SIS with the logic simulator by typing make i You should have a SIS executable now Note Sample scripts for SIS are available under the sample directory These scripts are provided to give you an example on how to us
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