EP8641A 1.1 (DES0222), User Manual
Contents
1. Disable CPU boot hold off mode normal operation NOTES 1 on closed position logic 0 off open position logic 1 2 Refer to the MPC8641D Reference Manual for additional information e600 Core 1 Configuration Switch SW504 configures the e600 core 1 options Table 4 6 describes the configu ration options Refer to Figure 2 3 for the location of the switch 24 8 February 2007 Preliminary P5010000087RA00 AdvancedMC EP8641A 1 1 Chapter 4 Setup Table 4 6 e600 Core 1 Configuration SW504 7 8 Option 12345678 Description xxxxxx0x Core 1 disabled XXXXXxX1x Core 1 enabled xxxxxxx0 Enable low memory offset for e600 core 1 real address A in range 0 to 256 MByte translated to address A 256 MByte xxxxxxx1 Disable low memory offset for e600 core 1 system address real address NOTES 1 on closed position logic 0 off open position logic 1 2 Refer to the MPC8641D Reference Manual for additional information SRIO Configuration P5010000087RA00 Preliminary Switches SW502 and SW505 configure SRIO options Table 4 7 through 4 9 describe the configuration options Refer to Figure 2 3 for the location of the switch Table 4 7 SERDES Port Configuration SW502 1 4 Option fae 12345678 Description 1001xxxx SERDES1 disabled SERDES2 x4 SRIO 3 125 Gbaud interface 125 MHz reference clock 1010xxxx SERDES1 disabled SERDES2 x4 SRIO 2 5 Gbaud interface 100 MHz re2. SDA_L 12V 8 February 2007 Chapter 5 Connectors and Headers 33 Chapter 5 Connectors and Headers 34 Table 5 8 AMC Connector P3 continued 8 February 2007 AdvancedMC EP8641A 1 1 Preliminary P5010000087RA00 Operation Chapter 6 This chapter describes the reset switch and board LED indications for the EP8641A board It also provides some firmware description and communication information system Reset Pushbutton The system reset pushbutton SW1 can be used to reset the board This pushbut ton activates a power on reset POR to the board Refer to Figure 2 2 for the loca tion of the pushbutton Board LEDs Table 6 1 describes the indications for the EP board LEDs Table 6 1 Board LEDs Definition On AMC hot swap indicator Blue AMC LED1 Red AMC LED2 Green AMC LED3 Amber 12 VDC power OK Yellow 5V power OK Yellow 3 3V power OK Yellow 1 1V e600 power OK Yellow 2 5V PHY power OK Yellow 1 8V DDR power OK Yellow Heart Beat Yellow Morse Version Green Ethernet port 3 RXD Green Ethernet port 3 TXD Green Ethernet port 4 RXD Green Ethernet port 4 TXD NOTE AMC LEDs are under MMC control Ethernet Port LEDs Green Table 6 2 describes the indications given by the Ethernet p
3. AdvancedMC EP8641A 1 1 DES0222 User Manual Developing Embedded Applications and Products Utilizing Freescale MPC86xx Integrated Host Processors P5010000087RA00 8 February 2007 Preliminary P5010000087RA00 AdvancedMC EP8641A 1 1 Copyright Notice Trademarks P5010000087RA00 Preliminary Copyright 2007 Embedded Planet LLC All Rights Reserved This manual is copyrighted by Embedded Planet LLC No part of this document may be copied or reproduced in any form or by any means without the express written permission of Embedded Planet LLC Embedded Planet LLC reserves the right to modify the information contained herein as necessary Embedded Planet assumes no responsibility for any errors which may appear in this document Information in this document is provided solely to enable system and software implementers to use Embedded Planet products This manual in whole or in part is to be considered the intellectual property of Embedded Planet This document is intended for the sole purpose of the owner of an Embedded Planet product Neither the document nor reproductions of it nor information derived from it is to be given to others nor used for any other purpose other than for development of Embedded Planet computing engine applications by original authorized owners of Embedded Planet products Embedded Planet Linux Planet Blue Planet RPX LITE and RPX LICC are trademarks or registered trademarks of
4. SD2_RX 4 7 SD2_RX 4 7 SD2_ REF_CLK SD2_REF_CLK Operating Modes The EP board can operate in two different modes e Stand alone mode e AdvancedMC mode Stand alone mode is primarily intended for development AMC mode provides the ability to use the same development board in a carrier card or chassis environ ment SW500 determines stand alone or AMC mode operation refer to Table 4 10 Thermal The MPC8641D processor is fitted with a heat sink The choice of size and type of heat sink is dependant on the environment in which the board is operating Fac tors such as processor speed ambient temperature and air flow all dictate the specific characteristics of the heat sink required Additionally the choice of heat sink is dependant on the space available which is ultimately determined by the mechanical constraints of the system in which the EP board will operate The heat sink used when the card is situated in a chassis environment with forced air flow will differ from that used when the card operates stand alone Refer to the MPC8641D Reference Manual for the processor thermal characteristics Firmware U boot is open source firmware for the embedded PowerPC architecture It can be installed in a boot ROM and used to initialize and test hardware or to download and run application code The EP8641A board is shipped with the u boot firmware residing in FLASH memory U boot loads at the address 0xFFF
5. and programming Power requirements 12 VDC 5A maximum from barrel connector stand alone or via AMC backplane connector 3 3 VDC 100 mA maximum via AMC backplane connector Operating temperature 0 C to 70 C 32 C to 158 F NOTES 1 Contact Embedded Planet for information about an industrial temperature version board 2 The means of disconnection from the mains power supply is the plug 3 No serviceable parts P5010000087RA00 Preliminary 8 February 2007 9 Chapter 1 Introduction First Steps Reminder AdvancedMC EP8641A 1 1 While it may be tempting to jump right into application development it is recom mended that you take a few minutes to review the Getting Started material pay ing special attention to the following recommended first steps 1 Register your EP board go to Support at www embeddedplanet com 2 Complete the steps in Chapter 3 when ready to connect and powerup the EP board for development You must register your EP board to become eligible for customer assistance or more detailed technical support from Embedded Planet Refer to Customer Sup port in this chapter How to Use This Manual 1 Refer to Chapter 2 for a description of the board features and functions 2 Refer to Chapter 3 for quick start information connection configuration and powerup 3 Refer to Chapter 4 for setup information including switch and jumper settings 4 Refer to Chapter 5 for a de
6. is needed when issuing commands to the FLASH devices due to the address line connections Chapter 2 Description LA29 LA28 LA27 LA26 LA25 LA24 LA23 LA22 LA21 LA20 LA19 LA18 LA17 LA16 LA15 LA14 LA13 LA12 LA11 LA10 LA9 ILA8 LA7 LA6 LA5 LA4 3 3V LCSON U16 AO A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 BY TE CE OE WE RESET WP ACC LD31 DQO LD30 DO LD29 DQ2 LD28 DQ3 LD27 DQ4 LD26 DQS LD25 DQ6 LD24 DQ7 LD23 DQ8 LD22 DQ9 LD21 DQ13 D17 DQ14 Ce DQ15 A 1 RY BY U17 LA29 LA28 AO LA27 Al LA26 A2 LA25 A3 LA24 A4 LA23 AS LA22 A6 LA21 A7 LA20 A8 LA19 A9 LA18 A10 CAT A11 LA16 A12 LA15 A13 LA14 A14 LA13 A15 LA12 A16 LA11 A17 LA10 A18 LAQ A19 ILA8 A20 LA7 A21 CAS A23 A25 3 3V BY TE LCSON CE OE WE RESET WP ACC DQO DO DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 A 1 RY BY LD15 LD14 LD13 LD12 LD11 LD10 LD9 LD8 LD7 LD6 LD5 LD4 LD3 LD2 LD1 LDO T00327A Figure 2 4 FLASH Address and Data Lines Table 2 1 lists the FLASH memory devices and their device IDs that are currently supported on the board Refer to the Spansion datasheets for detailed information about the FLASH memory devices Command codes for all Spansion devices are the same Device ID varies among the different devices Sector addre
7. AMC 0 R1 0 Advanced Mezzanine Card Base Specification e AMC 4 Rx x Advanced Mezzanine Card Serial RapidIO 12 8 February 2007 Preliminary P5010000087RA00 Description Chapter 2 This chapter provides some description of the EP8641A board features including the PowerPC processor external interfaces and u boot firmware Figure 2 1 is a simplified block diagram of the EP board Figures 2 2 and 2 3 show the top and bottom views of the board layout These figures show the headers unpopulated De without pins or connectors NOTE JP1 shown in Figure 2 2 is intended for development purposes only and should not be populated during normal operating conditions CFG SWITCH SW500 O LEDS FLASH SDRAM SDRAM 16 MHZ LOCAL BUS DDRC1 BUS BUS 20 MHZ CLOCKS t t 66 MHZ 12C2 MPC8641D CPLD JTAG HD1 gt CFG SWITCH SW502 503 504 505 LY m A STTM o O_ fr Ws st KO we H gt Ww o BD LU QUAD T CFG EH GBIT XCVR O SWITCH O O SW501 Sei Es ei Lu a e lt oc x n o x D COP SERIAL 10 100 1000 AMC JTAG SERIAL HD3 P4 ETHERNET CONNECTOR BDM JP2 P1 P2 P3 HD4 T00323A Figure 2 1 Simplified Block Diagram MPC8641D Clocks P5010000087RA00 Preliminary Refer to PowerPC Processor in this chapter All of the clocks used on the EP board are generated locally There are three dis tinct clocking environments on the board e System and real time clocks e Eth
8. Embedded Planet Freescale PowerQUICC and QUICC Engine are trademarks of Freescale Semiconductor Inc IBM and PowerPC are registered trademarks of International Business Machines Inc AdvanceTCA and ATCA are registered trademarks of PCI Industrial Computer Manufacturers Group PICMG AdvancedMC and MicroTCA are trademarks of PICMG Wind River Systems VxWorks and Tornado are registered trademarks of Wind River Systems Inc All other names and trademarks are the property of their respective owners and are hereby acknowledged 8 February 2007 3 AdvancedMC EP8641A 1 1 8 February 2007 Preliminary P5010000087RA00 AdvancedMC EP8641A 1 1 Contents Chapter 1 INtroduUC hoN EE 9 P OS E 9 EE CG ee 10 How to Use This Manual E 10 Ap poul Ei OCICS el EE 10 EEN 11 Contact Embedded Planet EE WE 11 Document Conventions E 11 Reference Documents seenen unn EEN A ee eeso ee raes see eeaeee 12 Chapter 2 Description EE a aenar nnnnnnnnnnnnnn nanna nnn nnmnnn nnna na 13 PowerPC e ET E 16 SDRAM OFS ati ZatlON EE e E 16 PLA R Ee E EEN OS EE 17 Processor I O Interface Signals gg scssccsssscssscscessecssessesessessssessesssesseseseeseeeesesesesoseens 18 Oia tit e a a E A 19 Bt ge E ME ee 19 Firmware E MEP nee EE 19 Restoring MAC e EE E Aa E ENA 20 Chapter 3 Getting Started 30f SHUgMMessscccssssccsnsscccnsssscnsesseensseccnnnsecnnesseensssecnnnesensesseensssens 21 Serial Monitor Connection Qgeitng ccccccc
9. Fan Header Pinout HD2 seeesessessseeesessssssssereesssssssseeeeeesssssseeeeeessssseeseeeseess J2 AME CONE Or E e a a E EA O E E EEEE 32 EEN LEDS era tee teenterte erent tein E eee ere ere eee rennet 35 Lhermet Prot i dle EC E 36 EEN 37 FE CSTE E WE 38 8 February 2007 7 AdvancedMC EP8641A 1 1 8 February 2007 Preliminary P5010000087RA00 Introduction Chapter 1 The EP8641A board is a single width full height advanced mezzanine card AMC based on the Freescale MPC8641D Integrated Host Processor The EP8641A board can operate as an AdvancedMC module within an Advanced TC AO system when plugged into an ATCA carrier or MicroTCA chassis The board can also operate as a stand alone module for rapid application development outside of the integrated ATCA or MicroTCA environment Functions The functions included on the EP board are listed in Table 1 1 Table 1 1 Hardware Features Entity Function Form factor Single width full height AMC O compliant Processor MPC8641D up to 1 5 GHz SDRAM 512 MBytes x64 DDR2 256 MBytes DDR controller 1 256 MBytes DDR controller 2 FLASH Up to 128 MBytes x32 Ethernet 2 10 100 1000 front panel RJ 45 2 10 100 1000 AMC connector port 0 and port 1 Serial port 2 wire RS 232 front panel RJ 45 Serial RIO AMC 4 compliant x1 x4 data AMC connector port 4 5 6 7 1 25 2 5 or 3 125 Gbaud 8b 10b encoding Debug JTAG COP port access for software debug
10. O0000 U boot utilities provide the ability to initialize the board and auto execute an operating system or application Refer to online u boot documentation for complete information about u boot and its utilities P5010000087RA00 Preliminary 8 February 2007 19 Chapter 2 Description AdvancedMC EP8641A 1 1 Restoring MAC Addresses The EP board has four media access control MAC address assigned to it The MAC address is the physical address of a device connected to a network expressed as a 48 bit hexadecimal number The EP boards are assigned MAC addresses during manufacture using the following convention Enet controller 1 MAC 0x0010ECxxxxxx ORed with 0x000000000000 Enet controller 2 MAC 0x0010ECxxxxxx ORed with 0x000000800000 Enet controller 3 MAC 0x0010ECxxxxxx ORed with 0x000000400000 Enet controller 4 MAC 0x0010ECxxxxxx ORed with 0x000000CO00000 where XXXXXX EP board serial number The serial number can be found in decimal form on a label affixed to the Ethernet port on the board e g 007573 For example a board with a serial number of 007573 decimal 001D95 hexadeci mal has a MAC address of 00 10 EC 00 1D 95 for Enet controller 1 00 10 EC 80 1D 95 for Enet controller 2 If it becomes necessary to restore a missing or corrupted MAC address use the above procedure to determine the EP board s MAC addresses and issue the fol lowing commands in u boot setenv ethaddr MAC ADDRESS 1 gt ENTER setenv ethtadd
11. RIO at either 1 25 2 5 or 3 125 Gbaud A frequency synthesizer device IC5840001 34 generates the 100 MHz or 125 MHz clock from an onboard 25 MHz crystal oscillator FX532 or equivalent input An LVDS clock fan out buffer ICS8545 selects either the 100 MHz or 125 MHz single ended input and distributes it to the processor as an LVDS refer ence clock SD2_REF_ CLK SD2_REF_CLK NOTE An option to clock the SERDES interface from CLK3 of the AMC connector is pro vided Additionally an option to source CLK3 to the AMC connector is provided These options are controlled from a BCSR register refer to Table 4 10 Memory The board has DDR2 SDRAM memory and FLASH memory Table 1 1 The processor supports two DDR controller interfaces DDRC1 and DDRC2 The board is typically configured as shown in Table 1 1 with both DDRC1 memory and DDRC2 memory populated Each bank has a 64 bit bus width refer to SDRAM Organization in this chapter for additional information There is no ECC option 14 8 February 2007 Preliminary P5010000087RA00 AdvancedMC EP8641A 1 1 Chapter 2 Description ff Oo SW504 O E O O O O 86 SW500 SW501 ouer SW503 arene e G 2 A T00326A Figure 2 3 EP Board Bottom View RS 232 Ethernet STTM P5010000087RA00 Preliminary The FLASH memory is Spansion MirrorBit The memory bu
12. ary 2007 AdvancedMC EP8641A 1 1 Preliminary P5010000087RA00 Connectors and Headers Chapter 5 The EP8641A board has the following connectors for I O functions and expand ability e One connector for power used for stand alone only e One RJ 45 connector for processor RS 232 monitor port e Two RJ 45 connectors for the 10 100 1000 Ethernet ports e One 2 x8 header for COP access e One 2 x5 header for JTAG access e One 1x3 header for MMC RS 232 serial port e One 2x8 header for MMC debug port e One 1 xX 2 header for external 12 VDC fan e AMC bus connector This chapter describes these connectors and headers Refer to Figure 2 2 for the locations of these connectors and headers Power Refer to Table 1 1 for input power requirements Stand Alone When operating in stand alone mode the EP board is powered from 12 VDC supplied through the barrel connector P5 An onboard regulator generates 3 3 VDC to power the MMC The specifications for the mating connector are Inner diameter 2 1 mm 0 083 inches Outer diameter 5 5 mm 0 217 inches Outer shell is GND Inner shell is 12 VDC AMC When operating in AMC mode the EP board is powered from the AMC connector of the carrier card or from the chassis backplane Both 12 VDC to power the board and 3 3 VDC to power the MMC are required Processor Monitor Port The RS 232 monitor port is connector P4 It is an RJ 45 connector Table 5 1 shows the port pinout The
13. cal Dimensions Appendix A P5010000087RA00 Preliminary This appendix contains mechanical dimension drawings for the EP8641A board The board is designed as a single width full height AMC module Figure A 1 shows the dimensions for the EP board NOTE The dimensions in this document are believed correct but if this unit is to be placed into a housing that has cut outs an actual unit must be procured to verify all required connec tor cut outs In addition the vendor datasheets for the connectors should be referenced to determine the tolerances of the connectors 8 February 2007 39 Appendix A Mechanical Dimensions AdvancedMC EP8641A 1 1 i med E B Wel E B lee o9 es ec LI L Z91L 0 H NNN me SE ay all OI g l O O O O o e s T T O 3 VEEN 53 SKU 2 ol cao i w dhe g 40 8 February 2007 Preliminary P5010000087RA00 AdvancedMC EP8641A 1 1 P5010000087RA00 Preliminary 8 February 2007 4 Embedded Planet 4760 Richmond Road Suite 400 Warrensville Heights OH 44128 www embeddedplanet com Form P5010000087RA00 Preliminary Litho in U S A Feb2007 Copyright 2007 Embedded Planet LLC All Rights Reserved AdvancedMC EP8641A 1 1 Phone 216 245 4180 Fax 216 292 0561
14. ccccccccccsssssscecesssscceeeesenssscececessneeeceesssantereresseneeecers 15 FLASH Address and Data Lines 17 Mechanical reegen eegener 40 Title Page SE en AnP DE 9 EIB Ee VMs T sem esata soacan A E EEE 17 MS E ses ssa ee O eat E eae E 18 MPX Clock PLL Ratio Configuration SW503 1 4 oo cece ccseeeseeeeeeeseceeeeeaes 23 e600 Core Clock PLL Ratio Configuration SW504 1 5 eee eee ceseeereeeeees 23 ig Frequency Configuration SW504 6 ssessecssesscsenssessensenenssnenes 24 Boot ROM Location Configuration SW503 5 8 eee eee ce eeeteetneteeeeeeeeeneees 24 CPU Boot Configuration WBO 24 e600 Core 1 Configuration SW504 7 8 oo eee ceseceseceseeeeecneeceseeeseeseeceeecneeeeeeeaeens 25 SERDES Port Configuration SW 502 124 iesse edereeederegee neue ebe 25 SRIO Device ID and System Size Configuration SW502 5 8 oo eee eee eeeee 25 SRIO Host Agent Contieuranon SVV O05 EZ eesse 26 ser Op ENTREE 26 MMC CO it a OV OU BAY EE 27 Monitor Port Pinout TA sce cs sauseisarrsencatassacennstesusencuestauesoddestnasicndadeeteneeuueaiauenrouxtonsnanan 30 Lhermet Ort Pirro PL P2 E 30 CPLD AG Port Tinon TDT aE I S 30 COP Pore Pinout HE 31 MMC Serial Port Pinout P2 sessiun e nere EEEE a eiS 31 8 February 2007 Preliminary P5010000087RA00 AdvancedMC EP8641A 1 1 List of Tables continued No 5 6 5 8 6 1 7 1 7 2 P5010000087RA00 Preliminary Title Page MMC Debus Fort Finou enges 31 12 VDC
15. e 5 5 shows the pinout Table 5 5 MMC Serial Port Pinout JP2 MMC Debug Port The MMC debug port is HD4 It is a 2 x 8 0 1 x 0 1 header Table 5 6 shows the utility header pinout Table 5 6 MMC Debug Port Pinout HD4 Function i Function 2 TMS GND 4 R I GND 6 TCK RST_IN 8 TDI IPMCV TDO GND ALLPST ALLPST ALLPST ALLPST 12 VDC Fan Header The 12 VDC fan header is connector HD2 Itis a 1 x 2 0 1 x 0 1 header Table 5 5 shows the pinout P5010000087RA00 Preliminary 8 February 2007 31 Chapter 5 Connectors and Headers AdvancedMC EP8641A 1 1 Table 5 7 12 VDC Fan Header Pinout HD2 AMC Connector Table 5 8 lists the pin assignments for the AMC connector P3 The AMC connec tor signal assignments follow the AMC standard Table 5 8 AMC Connector P3 GND 12V PS1 3 3V IPMCV GAO Olo NiO aA Ri WwsNM 32 8 February 2007 Preliminary P5010000087RA00 AdvancedMC EP8641A 1 1 P5010000087RA00 Preliminary Table 5 8 AMC Connector P3 continued ENABLE 12V GND TX4 TX4 GND RX4 RX4 GND TX5 TX5 GND RX5 RX5 GND SCL_L 12V GND TX6 TX6 GND RX6 RX6 GND TX7 TX7 GND RX7 RX7 GND
16. ernet clock e SERDES clock An onboard 66 MHz clock oscillator ECS 3953C or equivalent generates the sys tem clock SYSCLK input to the MPC8641D processor This is the primary clock 8 February 2007 13 Chapter 2 Description AdvancedMC EP8641A 1 1 CPLD AMC JTAG POWER CONNECTOR MONITOR SERIAL ae P4 l P2 HD4 P3 10 100 1000 a em ETHERNET K P1 a HD3 HD2 JP2 d e e d i ER f COP MMC MMC 12V FAN SERIAL JTAG BDM T00325A Figure 2 2 EP Board Top View input to the device An onboard 16 MHz clock oscillator ECS 3953C or equiva lent generates the real time clock RTC input to the processor This clock input can be used to clock the global timers in the programmable interrupt controller PIC of the processor A second onboard 66 MHz clock oscillator provides a clock input to the CPLD for timing An onboard 25 MHz crystal oscillator FX532 or equivalent provides the clock input needed by the Ethernet transceiver The Ethernet controller eTSEC of the processor requires a 125 MHz external clock input The Ethernet transceiver gen erates the 125 MHz clock to the processor EC1_GTX_CLK125 EC2_GTX_CLK125 from its 25 MHz clock input The high speed SERDES interface of the processor requires either a 100 MHz or 125 MHz LVDS clock reference to operate S
17. espectively There is one serial temperature and thermal monitor STTM device on the local I2C bus The STTM part is a 2 wire digital temperature sensor Its functionality is equivalent to the Microchip TCN75 part The minimum resolution provided by this part is a 9 bit temperature conversion The STTM address is hard wired to 0x90 0b1001000x 8 February 2007 15 Chapter 2 Description COP JTAG MMC AdvancedMC EP8641A 1 1 The HD3 header provides access to the COP port of the processor for debug access The HD1 header provides access to the CPLD JTAG port for program ming The module management controller MMC funtionality required for AMC 0 compliance is implemented in an MCF5213 Coldfire processor The MMC com municates with the ATCA carrier or microTCA carrier hub over the IPMB L bus using I2C protocol The carrier and MMC communicate through a limited set of IPMI commands Two serial temperature sensors and internal FLASH memory implement the tem perature sensor and FRU information storage device requirements for AMC 0 compliance The temperature devices are accessed via the SPI bus of the Coldfire processor Additionally access to the RS 232 serial port and JTAG BDM port of the Coldfire processor are provided for development purposes Refer to Chapter 5 for more information and pinouts for the connectors PowerPC Processor The EP board incorporates an MPC8641D dual core integrated host processor This 32 bi
18. ference clock 1011xxxx SERDES1 disabled SERDES2 x4 SRIO 1 25 Gbaud interface 100 MHz reference clock NOTES 1 on closed position logic 0 off open position logic 1 2 Refer to the MPC8641D Reference Manual for additional information Table 4 8 SRIO Device ID and System Size Configuration SW502 5 8 Position Description cfg_device_id 5 cfg_device_id 6 cfg_device_id 7 0 large system size up to 65 536 devices 1 small system size up to 256 devices NOTES 1 If SRIO host device ID is cfg_device_id 5 7 If SRIO agent device ID is OxFF ANDed with cfg_device_id 5 7 2 on closed position logic 0 off open position logic 1 8 February 2007 25 Chapter 4 Setup AdvancedMC EP8641A 1 1 Table 4 9 SRIO Host Agent Configuration SW505 1 2 Option 1234 Description SERDES2 agent SERDES2 host SERDES2 agent SERDES2 host NOTES 1 on closed position logic 0 off open position logic 1 2 Refer to the MPC8641D Reference Manual for additional information User Options Switch SW500 provides some additional user options Table 4 10 describes the options Refer to Figure 2 3 for the location of the switch Table 4 10 User Options SW500 1 4 Position Description Selects operating mode 0 stand alone mode 1 AMC mode Select SERDES clock source 0 SERDES interface clocked from external clock AMC CLK3 1 SERDES
19. interface clocked from local clock Enables or disables inversion of memory interface address bit 8 LA8 from the CPU to the FLASH memory 0 normal FLASH memory bank LA8 to FLASH is not inverted 1 alternate FLASH memory bank LA8 to FLASH is inverted Controls power up of the board in stand alone mode If SW500 1 1 to select AMC mode then this bit has no effect O power enabled 1 power disabled NOTE on closed position logic 0 off open position logic 1 MMC Configuration Switch SW501 configures the MMC processor options Table 4 11 describes the configuration options Refer to Figure 2 3 for the location of the switch NOTE This switch is primarily for development purposes It is factory set and should not be changed 26 8 February 2007 Preliminary P5010000087RA00 AdvancedMC EP8641A 1 1 Chapter 4 Setup Table 4 11 MMC Configuration SW501 1 4 Position Description RCON selects serial FLASH programming mode 0 enable serial FLASH programming mode 1 disable serial FLASH programming mode JTAG_EN selects between debug and JTAG mode 0 debug mode 1 JTAG mode NOTES CLKMOD 1 0 determines the clock mode 00 PLL disabled 10 PLL in normal mode 1 on closed position logic 0 off open position logic 1 2 Refer to the MCF5213 Reference Manual for additional information P5010000087RA00 Preliminary 8 February 2007 27 28 8 Febru
20. monitor port is from UARTO P5010000087RA00 Preliminary 8 February 2007 29 Chapter 5 Connectors and Headers AdvancedMC EP8641A 1 1 Table 5 1 Monitor Port Pinout P4 Function i Function NOTE 1 Pin numbering is from right 1 to left 8 when looking into the RJ 45 jack with the locking tab on top Ethernet Port The 10 100 1000 Ethernet ports are connectors P1 and P2 The connectors are shielded RJ 45 jacks Table 5 2 shows the RJ 45 jack pinout Table 5 2 Ethernet Port Pinout P1 P2 Function i Function NOTE 1 Pin numbering is from right 1 to left 8 when looking into the RJ 45 jack with the locking tab on top CPLD JTAG Port The CPLD JTAG port is HD1 It is a 2 x 5 0 1 x 0 1 header Table 5 4 shows the JTAG header pinout Table 5 3 CPLD JTAG Port Pinout HD1 Function i Function 1 TCK 2 GND 3 TDO 4 3 3V 5 TMS 6 7 2 9 TDI 10 GND COP Port The COP port is HD3 It is a 2 x 8 0 1 x 0 1 header Table 5 4 shows the COP header pinout 30 8 February 2007 Preliminary P5010000087RA00 AdvancedMC EP8641A 1 1 Chapter 5 Connectors and Headers Table 5 4 COP Port Pinout HD3 Function i Function TDO TDI TRST 3 3V 3 3V TCK CHKSTOP_IN TMS SRESET HRESET CHKSTOP_OUT MMC Serial Port The MMC serial port is connector JP2 It is a 1 x 3 0 1 x 0 1 header Tabl
21. oard refer to Table 5 7 The fan should be placed next to the board and in a position so as to maximize airflow over the processor After all connections have been properly made connect the 12 VDC power sup ply to the barrel connector P5 Fig 2 2 The EP board will boot up into u boot automatically Refer to online u boot documentation for complete information about u boot and its utilities 8 February 2007 Preliminary P5010000087RA00 setup Chapter 4 This chapter describes the various configuration switches that setup the EP8641A board for operation NOTE JP1 shown in Figure 2 2 is intended for development purposes only and should not be populated during normal operating conditions Processor Clock Configuration Switches SW503 and SW504 configure the processor clock options Tables 4 1 through 4 3 describe the configuration options Refer to Figure 2 3 for the location of the switch Table 4 1 MPX Clock PLL Ratio Configuration SW503 1 4 Option 12345678 OO0OO0OXxXxxxXx 0010xxxxX 0011xXXXX 0100xXXXX 0101xXXXX 0110xXXXX 1000xxxx 1001xxxx NOTES 1 on closed position logic 0 off open position logic 1 2 Refer to the MPC8641D Reference Manual for additional information MPC SYSCLK Table 4 2 e600 Core Clock PLL Ratio Configuration SW504 1 5 Option 12345678 01000xxx 01100xxx e600 MPX 10000xxx 11100xxx 10100xxx 01110xxx NOTES 1 on cl
22. ort LEDs P1 P2 Refer to Figure 2 2 for the location of the Ethernet port P5010000087RA00 Preliminary 8 February 2007 35 Chapter 6 Operation AdvancedMC EP8641A 1 1 Table 6 2 Ethernet Port P1 P2 LEDs Indication LED1 Yellow LED2 Green Amber No RXD TXD activity 10 Mbps RXD TXD activity 100 Mbps amber 1000 Mbps green User Applications The u boot firmware assumes the board is connected to a dumb terminal or a PC based terminal emulator and requires user intervention for the utilities The dumb terminal or PC serial port should be set as follows e 115200 baud default e 8 data bits e 1 stop bit e No parity e No hardware handshake Proper interfacing to the serial port via the correct RS 232 connections must be insured as described in RS 232 Connection in this chapter RS 232 Connection A DB 9 or DB 25 to RJ 45 connection is required for RS 232 communication Table 5 1 provides the pinouts for the RJ 45 connector The EP board has its serial ports wired as DTE A null modem type of connection is required when interfac ing to a DIE port For DTE DB9 3 TXD DB25 2 TXD DB9 2 RXD DB25 3 RXD DB9 8 CTS DB25 5 CTS DB9 7 RTS DB25 4 RTS DB9 5 GND DB25 7 GND 36 8 February 2007 Preliminary P5010000087RA00 Memory and Interrupts This chapter contains memory map and interrupt information for the EP8641A board Memory Map Table 7 1 Memory Map Chi
23. osed position logic 0 off open position logic 1 2 Refer to the MPC8641D Reference Manual for additional information P5010000087RA00 Preliminary 8 February 2007 23 Chapter 4 Setup AdvancedMC EP8641A 1 1 Table 4 3 Platform Frequency Configuration SW504 6 Option 12345678 xxxxx0xx Platform frequency MPX clock 400 MHz or less Description XXXXX1xXxX_ Platform frequency MPX clock 500 MHz or greater NOTES 1 Must be set consistent with MPX clock PLL ratio refer to Table 4 1 2 on closed position logic 0 off open position logic 1 3 Refer to the MPC8641D Reference Manual for additional information Processor Boot Configuration Switches SW503 and SW505 configure the processor boot options Tables 4 4 and 4 5 describe the configuration options Refer to Figure 2 3 for the location of the switch Table 4 4 Boot ROM Location Configuration SW503 5 8 Option 12345678 Description xxxx0010 SRIO xxxx0100 DDRC1 Xxxxx0101 DDRC2 xxxxX1111 Local bus GPCM 32 bit normal operation NOTES 1 on closed position logic 0 off open position logic 1 2 Refer to the MPC8641D Reference Manual for additional information Table 4 5 CPU Boot Configuration SW505 3 4 Description Boot vector fetched from default boot ROM location OxFFFO0100 Enable CPU boot hold off mode e600 core 0 is prevented from booting until configured by an external master
24. p Select LCSO Chapter 7 Table 7 1 describes the default memory map for the EP board NOTE The address map is recommended for the EP board and is as defined in u boot Other mappings can be utilized for any given application Function Address OxF8000000 Description 32 bit GPCM LCS1 Unused LCS2 Unused LCS3 Unused LCS4 Unused LCS5 Unused LCS6 Unused LCS7 Unused D1_MCS0 D1_MCS1 D1_MCS2 D1_MCS3 DDR SDRAM Ox00000000 64 bit DDRC1 controller Unused Unused Unused D2_MCSO D2_MCS1 D2_MCS2 D2_MCS3 DDR SDRAM Ox10000000 64 bit DDRC2 controller Unused Unused Unused CCSRBAR External Interrupts P5010000087RA00 Preliminary OxE0000000 Memory mapped processor registers All onboard external interrupts are active low signals Each IRQ line has a 10 Kohm pull up resister All used IRQ lines should be programmed for level sense Table 7 2 identifies the IRQ lines used by the EP board 8 February 2007 37 Chapter 7 Memory and Interrupts 38 Table 7 2 External Interrupts Interrupt Source Unused Unused Unused Unused Ethernet port 1 Ethernet port 2 Ethernet port 3 Ethernet port 4 STTM Unused Unused Unused 8 February 2007 AdvancedMC EP8641A 1 1 Preliminary P5010000087RA00 Mechani
25. perating system of their choice ready to run out of the box Hardware developers gain access to pro 8 February 2007 Preliminary P5010000087RA00 AdvancedMC EP8641A 1 1 Deploy Customer Support Chapter 1 Introduction duction designs and prototyping systems to test advanced system functionality Fully integrated software and hardware platforms simplify and shorten the devel opment cycle Embedded Planet products are ready to go to market today Our designs are pro duction proven and ready to be manufactured in quantity We offer full lifecycle management to simplify the deployment of your embedded solution Embedded Planet provides complete support for our product line Embedded Planet technical support includes product assistance for EP firmware and hard ware Technical support can assist with setup installation configuration docu mentation product related questions and expansion guidelines Second level software support for SDP s is handled through our partners We also provide development tools for all of our PowerPC boards Using our online support system our technical support engineers can assist you with questions regarding Embedded Planet products Via a browser our support team can access your system directly and quickly answer your technical ques tions Please contact us today to learn more refer to Contact Embedded Planet in this chapter Contact Embedded Planet Company E mail Directory Embedded Plane
26. r lt MAC ADDRESS2 gt ENTER setenv eth2addr MAC ADDRESS3 gt ENTER setenv eth3addr lt MAC ADDRESS4 gt ENTER saveenv ENTER 20 8 February 2007 Preliminary P5010000087RA00 Getting Started Chapter 3 This chapter describes how to get the EP board up and running in stand alone mode including initial configuration connection and powerup The board comes preprogrammed with u boot firmware An RS 232 serial monitor connection is required to access u boot utilities A network connection is required to transfer files to the EP board using TFTP To start up and begin communicating with the EP board 1 Verify the switches are configured properly for stand alone operation refer to Chapter 3 2 Establish a serial connection refer to Serial Monitor Connection in this chap ter 3 Establish a network connection if required refer to Network Connection in this chapter 4 Apply power refer to Power Up in this chapter Serial Monitor Connection A terminal emulator program on the host machine e g minicom Tera Term or HyperTerminal or a dumb terminal is required to interact with the EP board To establish a serial monitor connection with the host system 1 Connect the RJ 45 patch cable to the RJ 45 monitor port Fig 2 2 2 Connect the opposite end of the RJ 45 cable to the RJ 45 to DB 9 adapter 3 Connect the DB 9 adapter to a serial port on the host machine or dumb ter minal The default settings for the monitor por
27. s is 32 bit bus width refer to FLASH Organization in this chapter for additional information NOTE The local bus address and data lines are multiplexed An external demultiplexer con trolled by the LBC address latch enable LALE and LBC data buffer control LBCTL signals is used to separate the address and data bus The local bus is buffered using two bus trans ceiver SN74ALVCH32973 or equivalent There is one RS 232 serial port available at the front panel P4 The port commu nicates via UARTO of the processor The serial port uses an Intersil ICL3225E RS 232 transceiver or equivalent There are two 10 100 1000 Ethernet ports available at the front panel P1 P2 Two additional 10 100 1000 Ethernet ports are available at the AMC connector The Ethernet ports communicate via eTSEC1 eTSEC2 eTSEC3 and eTSEC4 of the processor and use a Marvell 88E1145 quad transceiver device The interface to the processor is RGMII Port 3 of the transceiver device routes to AMC port 0 and port 4 of the transceiver device routes to AMC port 1 in the common options region of the AMC port map pings The interface to the AMC connector is SERDES using SGMII protocol An external PHY or SERDES device is required to complete the interface to the media The MII management connection MDC MDIO to the processor is for configura tion and monitoring of the transceiver device The default Ethernet PHY addresses are 0b00000 0600001 0b00010 and 0b00011 r
28. scription of the connectors and headers available on the board 5 Refer to Chapter 6 for information about the operation of the EP board 6 Refer to Chapter 7 for memory map and interrupt information About Embedded Planet Design Develop Embedded Planet is a leading single board computer and embedded systems solution provider Our capabilities range from standard off the shelf single board computer products and embedded operating systems to full custom design and intellectual property solutions In 1997 Embedded Planet pioneered the Design Develop Deploy process for embedded systems engineering This process allows our customers to take advan tage of production tested reusable product designs in all phases of system devel opment to reduce time to market project risk and development costs Embedded Planet products help remove risk and shorten the design cycle through production tested integrated hardware and software designs CPU mod ule design is becoming more complicated with advanced memory interfaces and highly integrated communications processors Our production proven modules help OEMs eliminate the risky and time intensive design and verification of the CPU module and focus on their value added application Embedded Planet products provide early access to production modules for all members of the engineering team to allow for a parallel development path Soft ware developers get access to turnkey platforms with the o
29. scsssssssssesscsccsssssssnsecsesccsssssssrececcsecssssesssccesesecssssessssceesees 21 Network Connection sAr EE 21 BOWS Up ecaro EE 22 Chapter 4 Setup EE nn E 23 Processor Clock Con te TEE 23 Processor Doot e e E 24 2600 C ore UC Hutt Er d WE 24 ei DIEN Ce E 25 User OO OS gia GE 26 DUA rat te RE 26 Chapter 5 Connectors and Headers ccccccssecceseeceeesenseceneeneensceseceesseenssoenesenssnensseees 29 Ol cs ie GE 29 Processor VEC WMP Port GE 29 E Reme TOLD EE 30 TED EEN EE 30 CDE EE 20 DIN EE e GE 31 MMC Debug TOE ege 31 Aa Ee EE RA A E A OEA A 31 ANIC CONO E 32 Chapter 6 Operation EE 35 VeA E e O E 35 Boar WE OR EE 35 E hemet EE eegene eeng 35 P5010000087RA00 Preliminary 8 February 2007 5 AdvancedMC EP8641A 1 1 Contents continued Chapter 6 Operation continued WSC ee INS ae a E tions eases E E OAE T 36 E Te E 36 Chapter 7 Memory and Interrupts ccceeeeceeeceeeeeeeencesensesenneeenseecesseconsecoeseseeseeseneeees 37 Memory NaP E 37 Externat EC UD E arverutes WE 37 Appendix A Mechanical Dimensions ccccceeeceeseeeeeseseeeeseseseeeeeeenseeesenenseeasseeseoeaseenees 39 List of Figures No 2 1 2 2 2 3 2 4 A 1 List of Tables No 1 1 2 1 4 1 4 2 4 4 4 5 4 6 4 7 4 8 4 9 4 10 4 11 5 1 5 2 5 4 5 5 Title Page Sea EI ER Block RE dE E 13 EP B ard Top VIS Wi d fin VE 14 EP Board Bottom View SIBBBm c
30. sses also vary among the different devices Table 2 1 FLASH Devices Device S29GL128 Device ID 0x2101 S29GL256 0x2201 S29GL512 0x2301 The following guidelines apply to x32 ported FLASH memory P5010000087RA00 Preliminary 8 February 2007 17 Chapter 2 Description AdvancedMC EP8641A 1 1 e FLASH devices configured in 16 bit mode e Sector and chip erases should be performed only on a long word 32 bit basis e Programming should be done on a long word 32 bit basis if possible Processor I O Interface Signals Table 2 2 lists the processor I O interface signals used on the EP board Table 2 2 UO Signals Interface Signal UART_SOUTO UART_SINO UART_SOUT1 UART_SIN2 Ethernet EC_MDC EC_MDIO EC1_GTX_CLK125 EC2_GTX_CLK125 TSEC1_TXDJ 3 0 TSEC1_TX_EN TSEC1_GTX_CLK TSEC1_RXDJ 3 0 TSEC1_RX_DV TSEC1_RX_CLK TSEC2_TXD 3 0 TSEC2_TX_EN TSEC2_GTX_CLK TSEC2_RXD 3 0 TSEC2_RX_DV TSEC2_RX_CLK TSEC3_TXD 3 0 TSEC3_TX_EN TSEC3_GTX_CLK TSEC3_RXD 3 0 TSEC3_RX_DV TSEC3_RX_CLK TSEC4_TXD 3 0 TSEC4_TX_EN TSEC4_GTX_CLK TSEC4_RXD 3 0 TSEC4_RX_DV TSEC4_RX_CLK 18 8 February 2007 Preliminary P5010000087RA00 AdvancedMC EP8641A 1 1 Chapter 2 Description Table 2 2 I O Signals continued Interface Signal IIC1_SDA IIC1_SCL IIC2_SDA IIC2_SCL SD2_TX 4 7 SD2_TX 4 7
31. t 4760 Richmond Road Suite 400 Warrensville Heights OH 44128 Phone 216 245 4180 Fax 216 292 0561 www embeddedplanet com Marketing marketing embeddedplanet com Sales sales embeddedplanet com Information Request info embeddedplanet com Technical Support techsupport embeddedplanet com Webmaster webmaster embeddedplanet com Document Conventions Display Item User Data Input P5010000087RA00 Preliminary This document uses standard text conventions to represent keys display items and user data inputs Italic Identifies an item that displays on the screen such as a menu option or mes sage e g File gt Open Bold Identifies any part of acommand or user entry that is not optional or vari able and must be entered exactly as shown Italic Identifies any part of acommand or user entry that is a variable parameter Identifies any part of a command or user entry that is an optional parameter text within the brackets follows the previously described conventions KEY Identifies a specific key that is not alphabetic numeric or punctuation 8 February 2007 11 Chapter 1 Introduction AdvancedMC EP8641A 1 1 Press ENTER Press Esc V M press and release each key in sequence Press CTRL ALT DEL press all keys in sequence simultaneously File Names Name Indicates a file or directory name Example file h bin Reference Documents e MPC8641D Integrated Host Processor Reference Manual e
32. t are 115200 baud 8 data bits 1 stop bit No parity No flow control Network Connection P5010000087RA00 Preliminary A network connection between the development target i e EP board and host system is needed if planning to use TFIP services to transfer files to the EP board A TFIP server must be running on the host machine to use the network connec tion for file transfer Connect to the EP board in one of two ways directly or through a network hub or switch 8 February 2007 21 Chapter 3 Getting Started 22 Direct Hub or Switch Power Up AdvancedMC EP8641A 1 1 To directly connect to the host machine use a Ethernet crossover cable connected between the RJ 45 Ethernet port on the EP board Fig 2 2 and the Ethernet port on the host machine To connect to the host machine via a hub or switch use a standard Ethernet patch cable connected between the RJ 45 Ethernet port on the EP board Fig 2 2 anda free port on the hub NOTE Most new Ethernet cards hubs and switches have auto crossover capabilities which means the same cable may be able to be used for either direct hub or switch connection NOTE Start the terminal emulation program e g minicom Tera Term or HyperTerminal or make sure the dumb terminal is connected before powering up the EP board When operating stand alone an external cooling fan is required Optionally a 12 VDC fan can be powered from the fan header HD2 of the EP b
33. t processor includes an integrated PowerPC core and peripheral inter faces that can be used in a variety of embedded networking telecom military storage and pervasive computing applications The MPC8641D processor incor porates e e600 core scaling up to 1 5 GHz e Dual DDR memory controllers operating at up to 667 MHz data rate e Local bus controller operating at up to 166 MHz e Dual UART DUART e Dual I2C interfaces master or slave mode e Serial RapidIO interface unit e PCI Express interface unit not accessible on EP board e Four enhanced three speed Ethernet controllers eTSEC e Programmable interrupt controller PIC e Four channel DMA controller e Device performance monitor SDRAM Organization Memory Clock 256 MByte The DDR SDRAM clock speed is generated internal to the CPU and is 1 2 the platform clock i e MPX bus clock The maximum is 600 MHz data rate 300 MHz clock for the MPC8641D processor with a 66 MHz SYSCLK 512 Mbit 32M x 16 bit devices 4 Micron MT47H32M16 or equivalent 16 MBytes x 4 banks x 4 devices 256 MBytes total 2 bit bank address BAO BA1 13 bit row address AO A12 10 bit column address A0 A9 8 February 2007 Preliminary P5010000087RA00 AdvancedMC EP8641A 1 1 FLASH Organization The FLASH memory on the EP board is accessed using the general purpose chip select machine GPCM of the processor Figure 2 4 shows the address and data line connections An offset
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