DS92LV16 Bus LVDS SERDES Demo Kit User Manual - Digi-Key
Contents
1. 20 Demo Board PCB 20 Demo Board PCB Bill of Material 20 BLVDS16EVK User Manual Rev 2 31 Introduction National Semiconductor s BLVDS16EVK evaluation board demonstrates the DS92LV16 BLVDS Serializer and Deserializer SERDES interface device This evaluation board verifies the e Serializer block that serializes the 16 bit parallel bus into a serial stream with embedded clock Deserializer block that deserializes the serial data stream into a 16 bit parallel bus with associated clock e The BLVDS drivers line driving capability across a short Z pack cable The serializer accepts up to sixteen 3V LVTTL LVCMOS data signals from an incoming data source along with the clock TCLK and then converts the parallel signals into a single serialized BLVDS data stream The deserializer recovers the BLVDS serialized data stream and converts it back into parallel 3VLVTTL LVCMOS data and clock output signals Note that the DS92LV 16 serializer block and the deserializer block can operate independently of each other The device also includes several test modes By enabling the LINE LOOPBACK LINE LE function the signal integrity of the link may be checked Powering up the evaluation board is very simple The user simply needs to provide the proper LVTTL LVCMOS data inputs and clock to the serializer block and the proper clock2. 20 of J1 Serializer data inputs The serializer data signals must be driven from a source with 3V logic levels Input pins are not 5V tolerant Note some test equipment may require a 500 termination on these pins These pins include termination resistors R1 R10 on the board for this purpose DIN10 to DIN15 Pin 2 4 6 8 10 12 of J2 Serializer data inputs The serializer data signals must be driven from a source with 3V logic levels Input pins are not 5V tolerant Note some test equipment may require a 500 termination on these pins These pins include termination resistors R11 R16 on the board for this purpose TCLK Pin 14 of J2 The TCLK pin drives the serializer PLL and is used to strobe data at the DIN inputs The clock signal should be within the operating frequency of the device 125MHz 80 2 and it is important that the clock signal source be driven with a 3V logic signal The inputs are not 5V tolerant Note some test equipment may require a 50O termination on this pin This pin includes a termination resistor pad R17 on the board BLVDS16EVK User Manual Rev 2 31 TPWDN Pin 2 of J5 and Header pin J6 The serializer power down function can be controlled two ways A header pin J6 is available for pulling the signal High or it may be driven through pin 2 of J5 The following states are possible J6 Tied to HIGH will cause the Serializer block to enable J6 Open will connect the device s T
3. CONFIG1 J5 Header pin J12 Control Input CONFIG2 J5 Header pin J13 Control Input SYNC J5 Header pin J14 Control Input LOCK J5 LED 01 and Header pin J20 Control Output Serializer s Differential Output Serializer s Differential Output Deserializer s Differential Input REFCLK SMA J17 Header pin J15 and J16 Deserializer s Differential Input Deserializer Frequency Reference Clock Input BLVDS16EVK User Manual Rev 2 31 The following sections explain each functional block of the DS92LV 16 and the EVK Serializer Block The Serializer block accepts up to sixteen LVTTL LVCMOS 3V data signals from an incoming data source along with the clock TCLK signal These signals are serialized into the BLVDS data stream The serial data stream includes a start bit and stop bit appended by the Serializer which frames the sixteen data bits The Serializer transmits the data and clock bits at 18 times 16 2 clock bits the TCLK frequency At 80MHZz the line rate is 1 44 Gbps and the payload data rate is 1 28 Gbps The 18 bit parallel inputs are available at the 20 pin headers J1 J2 on the board Note all odd pins on J1 and J2 are connected to GND The serialized differential data out is available through header P1B see Differential Signals Connection and Termination for detail DINO to DIN9 Pin 2 4 6 8 10 12 14 16 18
4. board for the user to monitor the status of the LOCK indicator A 50MHz oscillator U2 is provided on board as an alternative REFCLK source There are two pairs of differential signal lines connected to the 2mm Hard Metric Header P1B The User can also utilize the Loopback test functions of the DS92LV16 to verify device operation The signal function vs connector pin number are listed in table 1 Table 1 Signal Function vs Connector Pin Number Signal Function Connector Pin number Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Serializer Clock Input Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output BLVDS16EVK User Manual Rev 2 31 ROUT10 Data Output ROUT 11 Data Output ROUT12 Data Output ROUT13 Data Output ROUT14 Data Output ROUT15 Data Output RCLK TPWDN Header pin J6 Deserializer Clock Output Control Input RPWDN J5 Header pin J7 Control Input DEN J5 Header pin J8 Control Input REN J5 Header pin J9 Control Input LOCAL LE J5 Header pin J10 Control Input LINE LE J5 Header pin J11 Control Input
5. driven through pin 18 of J5 The following states are possible J14 Closed HIGH will cause the serializer to output sync patterns J14 Open will connect the device s SYNC pin to Pin 18 of J5 J14 Open and a no connect on Pin 18 of J5 will place the serializer in normal operation mode Note the SYNC pin is internally pulled low as a result when the SYNC pin isa left floating the device is in normal operation mode BLVDS16EVK User Manual Rev 2 31 Deserializer Block The Deserializer block recovers the BLVDS data stream back into LVTTL LVCMOS parallel data and clock During synchronization the Deserializer s PLL uses the Reference Clock REFCLK as a frequency reference to lock to the incoming BLVDS data stream After the Deserializer s PLL locks to the embedded clock the LOCK pin goes low and valid data and clock will appear on the deserializer outputs The 16 bit parallel outputs are available at the 20 pin headers J3 J4 on the board Note all odd pins on J3 J4 are connected to GND The serialized differential data in is applied through header P1B see the section titled Differential Signals Connection and Termination for details ROUTO to ROUT9 Pin 2 4 6 8 10 12 14 16 18 20 of J3 Deserializer parallel data outputs These pins are LVCMOS level Note 0805 pads in series R18 R27 default are shorted out are provided if the user needs to install 4500 series resistors This is required if directly co
6. locked RCLK ROUT data is valid The status of the LOCK pin can be monitored by either probing pin 20 of J5 or by monitoring the state of LED D1 Note the LOCK LED CONTROL header pin J20 must be CLOSED in order to enable D1 Power Supply Connection Power and Ground must be applied through power terminals J18 and J19 They are the main power supply connection for the EVK Ground should be applied to J18 and 3 3V 4 5 should be applied to J19 Option Loopback Test The DS92LV 16 includes two test modes for testing the functionality of the device and the transmission line continuity They are LOCAL Loopback mode and LINE Loopback mode Please see the datasheet for details BLVDS16EVK User Manual Rev 2 31 LOCAL LE Pin 10 of J5 and Header pin J10 The LOCAL LE pin controls the LOCAL Loopback test that enables the user to check the integrity of the transceiver from the local parallel bus By enabling the LOCAL Loopback mode the parallel data inputs DIN 0 15 loop back to the parallel data outputs ROUT 0 15 post serialization The connection route includes all the functional blocks of the Transceiver The serial data outputs DO are automatically disabled during the LOCAL Loopback mode The following states are possible J10 Tied to HIGH will cause the device to go into LOCAL Loopback mode J10 Open will connect the device s LOCAL LE pin to Pin 10 of J5 J10 Tied to LOW will cause the device to operate as indi
7. 8 ROUT11 R29 ROUT 12 R30 ROUT13 R31 ROUT14 R32 ROUT15 R33 RCLK R34 16 BLVDS16EVK User Manual Rev 2 31 LVCMOS LVTTL Termination Default For parallel inputs 50O termination resistors to GND are included on the board see Table 3 and Figure 2 These resistor locations are labeled R1 R19 Table 3 and Figure 2 LVCMOS LVTTL Termination INPUT Resistor DINO R1 DIN1 R2 DIN2 R3 DIN3 R4 DIN4 R5 DIN5 R6 DING R7 DIN7 R8 DIN8 R9 DIN9 R10 DIN10 R11 DIN11 R12 DIN12 R13 DIN13 R14 DIN14 R15 DIN15 R16 TCLK R17 LVTTL LVCMOS Input 500hm Drive Recommended 50 ohm Termination Default 17 BLVDS16EVK User Manual Rev 2 31 Differential Signals Connection and Termination Differential signals connection can be found at the 2mm Hard Metric Header P1B The user can access the serializer differential outputs on pins A1 DO and B1 DO of P1B Connection to the deserializer s differential inputs can be found on pins D2 RIN and E2 RIN of P1B Two probing points are available at the deserializer s differential inputs for the user to monitor the integrity of the differential input signal Plese see Figure 3 A 100 O termination resistor R39 is provided at the deserializer inputs RIN and an optional unpopulated resistor pad R40 is provided at the serializer outputs DO so the user can add a differential terminati
8. BLVDS16EVK User Manual Rev 2 31 National Semiconductor The Sight amp Sound of Information DS92LV16 Bus LVDS SERDES Demo Kit User Manual P N BLVDS16EVK Rev 2 31 October 2003 Network Interface Products BLVDS16EVK User Manual Rev 2 31 Table of Contents ag 10 og TP 3 Demo Kit Contents LTS aate scs M 4 EVK FEE Arr 4 Ove NiS W TH 5 Table 1 Signal Function vs Connector Pin Number 5 Serializer Block Le 7 Deserializer BIOCK Gud HE 9 Power Supply 11 Option Loopback d ihn 11 Setting up BEVDS IGE VK nisse t Et rere ior xcd 13 Quick check Tor EIS ais ue Lenne 13 External loopback data transfer setup 13 Typical Connection Test 15 LVCMOS LVTTL Termination 15 Table 2 and Figure ANA 16 LVCMOS LVTTL Termination 17 Table 3 and Fig re 2 preesse xeu aE ERR eere xac de edant dag 17 Differential Signals Connection and Termination 18 FE enm 18 Additional 19 VEN 0 6151 0 ER 20 AMP s 2mm Hard Metric Connector and Z pack Cable
9. PWDN pin to Pin 2 of J5 J6 Tied to LOW will cause the Serializer block to power down When TPWDN is driven LOW the PLL of the serializer will lose lock the output of the serializer will enter TRI STATE and the supply current will drop into the nA range When TPWDN is driven HIGH the Serializer is enabled and will operate as indicated by the other control and input pins DEN Pin 6 of J5 and Header pin J8 The DEN pin controls the serializer s outputs The serializer outputs will enter TRI STATE when the DEN pin is LOW When DEN is HIGH the outputs are active A header pin J8 is available for pulling the signal High or it may be driven through pin 6 of J5 The following states are possible J8 Tied to HIGH will enable the serializer outputs J8 Open will connect the device s DEN pin to Pin 6 of J5 J8 Tied to LOW will disable the serializer outputs and cause the outputs to enter TRI STATE SYNC Pin 18 of J5 and Header pin J14 The SYNC pin enables the SYNC function of the serializer By enabling the SYNC function the serializer transmits the special synchronization pattern sync pattern The sync pattern is a fixed pattern consisting of 9 bits high and 9 bits low as shown in the datasheet Logic HIGH on this pin will force the sync patterns to be sent per datasheet details and a logic LOW places the serializer in normal operation mode A header pin J14 is available for pulling the signal High or it may be
10. cated by the other control and input pins LINE LE Pin 12 of J5 and Header pin J11 The LINE LE pin controls the LINE Loopback test mode that enables the user to check transmission line continuity By enabling the LINE Loopback mode the serial data inputs RIN connect to the serial data outputs DO in addition to the parallel data outputs ROUT 0 15 The following states are possible J11 Tied to HIGH will cause the device to go into LINE Loopback mode J11 Open will connect the device s LINE LE pin to Pin 12 of J5 J11 Tied to LOW will cause the device to operate as indicated by the other control and input pins CONFIG1 Pin 14 of J5 and Header pin J12 This pin corresponds to pin 43 CONFIG 1 of the device Users are required to pull this pin J12 to HIGH LOW reserved for future use CONFIG2 Pin 16 of J5 and Header pin J13 This switch corresponds to pin 418 CONFIG 2 of the device Users are required to pull this pin J13 to HIGH LOW reserved for future use BLVDS16EVK User Manual Rev 2 31 Setting up BLVDS16EVK There are many ways to set up this EVK for bench testing and performance measurements The following are just a few of the many ways to set up the kit Quick check for EVK The user can perform the following to ensure the functionality of the EVK 1 Apply a 3 3V 4 5 to Power Terminal J19 and apply ground to Power Terminal J18 2 Connect one end of the AMP 2mm Z pack cable to row 1
11. e signal HIGH or it may be driven through pin 4 of J5 The following states are possible Tied to HIGH will enable the Deserializer block J7 Open will connect the device s RPWDN pin to Pin 4 of J5 J7 Tied to LOW will cause the Deserializer block to power down 10 BLVDS16EVK User Manual Rev 2 31 When RPWDN is driven LOW the PLL of the deserializer will lose lock the output of the deserializer will go into TRI STATE and the supply current will drop into the uA range When RPWDN is driven HIGH the deserializer is enabled and will operate as indicated by the other control and input pins REN Pin 8 of J5 and Header pin J9 The REN pin controls the deserializer outputs The deserializer outputs will enter TRI STATE when the REN pin is LOW When REN is HIGH the outputs are active A header pin J9 is available for pulling the signal High or it may be driven through pin 8 of J5 The following states are possible J9 Tied to HIGH will enable the deserializer outputs J9 Open will connect the device s REN pin to Pin 8 of J5 JO Tied to LOW will disable the deserializer outputs LOCK LED D1 Pin 20 of J5 The LOCK pin indicates the status of the deserializer block PLL The user can monitor this pin to see whether the deserializer has locked to the BLVDS data stream LOCK HIGH LED ON deserializer s PLL unlocked RCLK and ROUT data are invalid LOCK LOW LED OFF deserializer s PLL
12. frequency must be within 5 of the TCLK signal frequency and it has no phase relationship with the deserializer output User may either select the on board 50 MHz oscillator and operate the device at 50 MHz or apply an external clock for the REFCLK Selection of clock source is accomplished using REFCLK CONTROL header pin J15 The following states are possible Connecting J15 to SMA will tie the device REFCLK pin to the SMA connector J17 When using external clock to drive REFCLK signal the user supplies the clock signal to the SMA connector J17 on the board The signal source must be o Driven with a signal of 3 3V o Capable of driving a 500 resistive load When selected for external clock source the board presents a 500 R49 termination to GND for the user s signal generator Connecting J15 to OSC will tie device REFCLK pin to the on board 50 MHz oscillator U2 The user must leave header pin J16 OPEN to enable the oscillator When J16 is CLOSED the oscillator will be disabled Note that this is a 3 3V device When the on board 50 MHz oscillator is used as the supply for the REFCLK signal the signal source driving the TCLK signal must also be at 50 MHz See clock tolerance requirements 5 in the datasheet REFCLK driven by signal applied through SMA J17 RPWDN Pin 4 of J5 and Header J7 The deserializer power down function can be controlled two ways A header pin J7 is available for pulling th
13. nnecting to a 50Q input on a scope The pad is unpopulated from the factory and in order to use this option the user must cut the signal line between the pads before installing the 4500 series resistors ROUT10 to ROUT15 Pin 2 4 6 8 10 12 of J4 Deserializer parallel data outputs These pins are LVCMOS level Note 0805 pads in series R28 R33 default are shorted out are provided if the user needs to install 4500 series resistors This is required if directly connecting to a 500 input on a scope The pad is unpopulated from the factory and in order to use this option the user must cut the signal line between the pads before installing the 4500 series resistors RCLK Pin 14 of J4 RCLK is the Recovered Clock of the deserializer block This LVCMOS LVTTL output signal contains information of the parallel data rate clock recovered from the serial data stream The RCLK signal is used to strobe the ROUT data Note an 0805 pad in series R34 default is shorted out is provided if the user needs to install 4500 series resistor This is required if directly connecting to a 500 input on a scope The pad is unpopulated from the factory and in order to use this option the user must cut the signal line between the pads before installing the 4500 series resistor BLVDS16EVK User Manual Rev 2 31 REFCLK Header pin J15 SMA J17 Header pin J16 The REFCLK input is used as a frequency reference to the deserializer s PLL Its
14. of the 2mm Hard Metric Header P1B on the board and the other end to row 2 of P1B on the same board 3 Tied the following header pins on the board to HIGH TPWDN J6 RPWDN J7 DEN J8 REN J9 CONFIG1 J10 CONFIG2 J11 SYNC J12 LOCK LED CONTROL J14 Note The demo kit comes fully loaded with all configuration jumpers connected Unused modes should have their jumpers removed 4 Apply a 50MHz LVTTL LVCMOS 3V clock signal from a clock source signal generator BERT tester etc to the TCLK pin 14 of J2 5 Tie REFCLK CONTROL J15 to OSC Make sure jumper J63 is open 6 Monitor the state of the LOCK INDICATOR LED D1 If the LED is NOT ON the EVK is functioning properly and the serializer and deserializer are synchronized External loopback data transfer setup The user can also use the following setup to perform a Bit Error Rate Test and a quick check of the LVDS signal 1 Apply a 3 3V 4 5 to Power Terminal J19 and apply ground to Power Terminal J18 BLVDS16EVK User Manual Rev 2 31 2 Connect one end of the AMP 2mm Z pack cable to row 1 of the 2mm Hard 4 5 7 Metric Header P1B on the board and the other end to row 2 of P1B on the same board Close the following header pins on the board TPWDN J6 RPWDN J7 DEN J8 REN J9 CONFIG1 J12 CONFIG2 J13 LOCK LED CONTROL J14 Apply a LVTTL LVCMOS 3V clock signal from a clock so
15. on resistor on the serializer output if needed In addition a couple of unpopulated pads R52 and R53 are provided at the deserializer inputs RIN for optional failsafe biasing Please see Figure 3 and the schematic for the location of these terminations Figure 3 R40 100 Optional dn nd uondo ne ESH O O O O B A G pin connected to GND 18 BLVDS16EVK User Manual Rev 2 31 Additional Information For more information on BLVDS Serializers Deserializers please refer to National s LVDS website at www national com appinfo lvds Interface Applications Hotline The Interface Hotline number is 1 408 721 8500 BLVDS16EVK User Manual Rev 2 31 Appendix AMP s 2mm Hard Metric Connector and Z pack Cable AMP cable connector specifications and drawings are available at www amp com PART NUMBER 352041 7 Demo Board PCB Schematic Document available upon request Please ask for BLVDS16PCB rev2 2 pdf Demo Board PCB Bill of Material Document available upon request Please ask for BLVDS16BOM rev2 2 pdf 20
16. signal to the REFCLK input The deserializer block features a random lock function thus the serialized stream simply needs to be connected to the deserializer inputs and the recovered data and clock will be available at the output pins for monitoring checking the random data The deserializer may also be locked using the SYNC pin function on the serializer National Semiconductor s DS92LV 16 is intended to be used in mainly point to point applications It should be terminated with 1000 loads or 50Q loads with reduced margins BLVDS16EVK User Manual Rev 2 31 Demo Kit Contents One demonstration board BLVDS16PCB One 1 meter AMP 2mm Hard Metric Z pack cable BLVDS16EVK User Manual this document DS92LV16 Datasheet EVK Features National Semiconductors BLVDS DS92LV16 Serializer Deserializer Optional On board 50MHz oscillator clock source On board LED for LOCK indicator Configuration header pins for o Power down controls o SYNC Pattern selection o Line and Local loopback enables for test modes o Output disable controls BLVDS16EVK User Manual Rev 2 31 Overview The BLVDS16EVK SERDES demo board has independent 16 bit parallel input and output ports J1 and J2 comprise the input pins and include 500 terminations to ground J3 and J4 comprise the output pins J5 provides access to all the control input signal pins and LOCK pin Note that the odd number pins are connected to ground for J1 J5 ALED D1 is provided on
17. st of typical test equipment that may be used to monitor the output signals from the Rx LVTTL LVCMOS outputs 1 TEK MB100 BERT Deserializer 2 Any oscilloscope with 500 inputs used in conjunction with the optional 4500 series resistor pads on the board or with high impedance probes LVTTL LVCMOS signals to the EVK can be connected to the pattern generator oscilloscope with any pin header cable The following is the cable that was used in testing Tektronix SMB pin header cable 20in P N 012150300 LVDS signals may be easily measured with high impedance high bandwidth differential probes such as the TEK P6247 P6248 or P6330 differential probes LVCMOS LVTTL Termination Options Pads are provided for output signal attenuation for compatibility with 500 scope heads For parallel outputs series 4500 resistors can be added for compatibility with 50O scope inputs see Table 2 and Figure 1 These resistor locations are labeled R20 R38 Note the output series resistor pads are shipped with a shorting trace To use the series resistor option the trace must be cut between the mounting pads prior to installing a resistor BLVDS16EVK User Manual Rev 2 31 Table 2 and Figure 1 LVCMOSILVTTL Termination Resistor 450ohm Series Termination ROUTO R18 Optional ROUT1 R19 ROUT2 R20 ROUT3 R21 ROUT4 R22 ROUT5 R23 ROUT6 R24 ROUT7 R25 ROUT8 R26 ROUT9 R27 ROUT10 R3
18. urce signal generator BERT tester etc to TCLK pin 14 of J2 Note the TCLK signal should be between 25 and 80 MHz Apply a LVTTL LVCMOS 3V data signal from a data source signal generator BERT tester etc to the two DIN signal connectors on the board J1 J2 See Table 1 for the pin mapping of J1 and J2 Tie REFCLK CONTROL J15 to SMA Apply a LVTTL LVCMOS 3V clock signal from a clock source to the REFCLK pin via the SMA connector J17 on the board Note the frequency of the signal applied to REFCLK must be within 5 of the TCLK signal frequency Data applied to the inputs are now serialized transmitted deserialized and re driven to the deserializer outputs ROUT 0 15 The user can also monitor the integrity of the LVDS signal by probing the LVDS signal probe points on the board BLVDS16EVK User Manual Rev 2 31 Typical Connection Test Equipment The following is a list of typical test equipment that may be used to generate signals for the TX LVTTL LVCMOS inputs 1 HFS9009 This pattern generator along with 9062 Cards may be used to generate input signals and the clock signal 2 TEK DG2020 This generator may also be used to generate data and clock signals 3 TEK MB100 BERT This bit error rate tester may be used for both signal source and deserializer 4 Any other signal pattern generator that generates the correct input levels as specified in the DS92LV 16 datasheet The following is a li
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