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CC1010 Data Sheet

1. CPOL 1 CPHA 1 MO MI YONA ZY 3X 4X 5X 861 7X DORD 0 MO MI XX SXSX 4X 3X 2X 3X 9X DORD 1 SPSR SPA SPDR read by 8051 Data received during last byte transmission New data lt ________ SPSR WCOL is set if SPDR is written here Figure 18 SPI Data Flow TEXAS INSTRUMENTS SWRS047 Page 74 of 152 Chipcon Products from Texas Instruments 16 9 DES Encryption Decryption DES encryption decryption is supported by hardware in 227010 Blocks of data ranging from 1 to 256 bytes can be encrypted decrypted in one operation by the DES module Multiple encryption decryption operations can also be used on larger data blocks Encryption is the process of encoding an information bit stream to secure the data content The DES algorithm is a common simple and well established encryption routine An encryption key of 56 bits is used to encrypt the message The receiver must use the exact same key to decrypt the message otherwise the message will be scrambled The encryption and decryption operations in the DES algorithm are symmetrical operations with the same computational requirements The operations produce the same number of output bytes as input bytes The strength of an encryption algorithm is determined by the number of bits in the key the more the better The DES algorithm offers a low to medium level of security If higher lev
2. 8 DVDD DVDD _ 64 3 2 61 60 59 58 7 ES 58 GA E3 2 E E BS amp 55448 296 AVDD 23 8 288 E 1 AVDD 8 g P3 0 RXDO 48 ___ 2 avop P3_1 TXDO a7 1 27 Aono P3 2 INTO 86 Antenna ar rm I 4 RF IN L5 H5 5 Rr our P2 4 C42 ___ 6 DVDD 234 fiat 132 7 AGND 52 e AGND oeno aH AVDD 8 AGND DVDD faa 70 11 P2 2 39 zu m 12 Pt 4 B8 I 2 P1 a 81 13 CHP_OUT P1_2 86 14 R Bias Pt 25 t5 Po 1 37 R131 15 AGND a v Poo sek B3 85 585898 g al Eg PEE 8 8 z 668886 zz 3 Be 7 18 19 20 22 23 24 25 26 27 28 E 0 XTAL cas som Figure 20 Typical application circuit Note Decoupling capacitors not shown Please see CC1010EM reference design TEXAS INSTRUMENTS SWRS047 Page 86 of 152 Chipcon Products from Texas Instruments CCT010 Item 433 MHz 868 MHz 915 MHz C31 10 pF 5 COG 0603 8 2 pF 5 COG 0603 8 2 pF 5 COG 0603 41 6 8 pF 5 COG 0603 Not used Not used C42 8 2 pF 5 COG 0603 10 pF 5 COG 0603 10 pF 596 COG 0603 C171 18 pF 5 0603 18 pF 5 COG 0603 18 pF 5 COG 0603 C181 18 pF 5 0603 18 pF 5 COG 0603 18 pF 5 COG 0603 132
3. SWRS047 Page 147 of 152 4 TEXAS INSTRUMENTS Chipcon Products from Texas Instruments 30 Ordering Information 01010 Ordering part number Description MOQ CC1010 STY1 CC1010 TQFP64 package standard leaded assembly trays with 160 pcs per tray 160 tray CC1010 STR1 CC1010 TQFP64 package standard leaded assembly T amp R with 1500 pcs per reel 1500 tape and reel CC1010 RTY1 CC1010 TQFP64 package RoHS compliant Pb free assembly trays with 160 pcs per tray 160 tray CC1010 RTR1 CC1010 TQFP64 package RoHS compliant Pb free assembly T amp R with 1500 pcs per reel 1500 tape and reel CC1010DK 433 CC1010 Development Kit 433 MHz 1 CC1010DK 868 CC1010 Development Kit 868 915 MHz 1 CC1010SK CC1010 Sample Kit 5 pcs 1 CC1010SK RoHS CC1010 Sample Kit 5 pcs Pb free 1 TEXAS INSTRUMENTS SWRS047 MOQ Minimum Order Quantity Page 148 of 152 from Taxas lnstrumente 2071010 31 General Information 311 Document History Revision Date Description Changes 13 2004 12 17 Added history table Various corrections and clarifications Preliminary status removed Added Smith charts for LNA input impedance and inactive PA input impedance Added sensitivity vs data rate information Added information about power consumption of Schmitt trigger in
4. Table 26 ADC input impedance vs sampling frequency The average input impedance accounts for the average input current to the ADC but cannot be used for estimation of conversion errors due to voltage division between the source impedance and the ADC input impedance For that purpose the charging time of the sample capacitor must be considered TEXAS INSTRUMENTS Table 27 Maximum source impedance for ADC The ADC can be operated in 4 modes controlled by ADCON ADCM Each ADC sample conversion takes 11 ADC clock cycles In Clock Mode 1 when X32CON CMODE is set the 32 kHz clock is applied directly to the ADC The conversion time is then 344 ys In Clock Mode 0 the ADC clock input is derived from the main oscillator clock using the divider selected by ADCON2 ADCDIV The register must be set so that the resulting ADC clock frequency is less than or equal to 250 kHz If the clock frequency is equal SWRS047 Page 79 of 152 Chipcon Products C from Texas Instruments to 250 kHz then the conversion time is 44 us In single conversion mode each conversion is initiated by setting the ADCON ADCRUN control bit The ADC interrupt flags EXIF ADIF and ADCON2 ADCIF are set by hardware if the 8 MSB of the latest sampled value is greater than or equal to the threshold value stored in the ADTRH register An interrupt service routine is then executed if the interrupt enable flags EIE ADIE and ADCON2 A
5. C from Texas Instruments 201070 96 97 98 99 10 m 5 102 in 103 N 104 105 NEN 107 60 40 20 0 20 40 60 80 Frequency offset kHz Figure 31 Sensitivity versus frequency offset 868 MHz 2 4 kBaud Manchester 98 99 100 101 5 8 102 103 8 104 8 105 106 107 e o 108 80 60 40 20 20 40 60 Frequency offset kHz Figure 32 Sensitivity versus frequency offset 433 MHz 2 4 kBaud Manchester SWRS047 Page 106 of 152 TEXAS INSTRUMENTS Chipcon Products from Texas Instruments 17 12 Frequency programming RX mode 2071010 f f T fio low side Receive frequency fio high side lt fe gt lt fe TX mode gt f fre fi f LowerFSK Center frequency Upper FSK we frequency frequency 8 fen _____ sop Figure 33 Relation between fico fi and LO frequency The frequency synthesiser PLL is controlled by the frequency word in the configuration registers There are two frequency words A and B which can be programmed to two different frequencies One of the frequency words can be used for RX local oscillator frequency and other for TX transmitting frequency fo This makes it possible to switch very fast between RX mode and TX mode They can also be used for RX or TX on two different channels Selection of frequency word A or B is performed by using the RFMAIN F REG contr
6. is set the interrupt flag EXIF ADIF is also set which will generate an interrupt if is set See the Interrupts section on page 28 for details on interrupts The duration of a DES encryption decryption operation is shown in Table 25 Accessing external RAM from the 8051 while encrypting decrypting may delay the operation slightly since the access is multiplexed DES keys stored in Flash memory will be protected by the Flash memory read protection For the security of the Flash protection please refer to the disclaimer at the end of this document Mode Duration clock cycles Single DES 2 25 Data Bytes 21 LOADKEYS Table 25 DES Encryption Decryption duration TEXAS INSTRUMENTS SWRS047 Page 76 of 152 Chipcon Products from Texas Instruments 2071010 CRPCON 0xC3 Encryption Decryption Control Register Bit Name RW Reset value Description T RO 0 Reserved read as 0 6 CRPIE R W 0 Encryption Decryption interrupt enable flag In order for to raise an interrupt EIE ADIE must also be set 5 CRPIF R W 0 Encryption Decryption interrupt flag CRPIF is set by hardware when an encryption decryption is completed CRPIF must be cleared by software Because the encryption decryption shares an interrupt line with the ADC EXIF ADIF must also be cleared by software before exiting the interrupt service routine EX
7. Parameter Min Typ Max Unit Condition Power on reset POR voltage 2 7 2 9 3 1 40 to 85 Brown out voltage 27 29 3 1 40 to 85 RTC start up time 160 ms Current consumption MCU 14 8 mA 14 7456 MHz main oscillator Active mode 1 3 mA 32 kHz RTC oscillator See page 33 for explanation of modes See Figure 1 page 6 for supply current vs clock frequency Current consumption MCU Idle 12 8 mA 14 7456 MHz main oscillator mode 29 4 pA 32 kHz RTC oscillator Current consumption Power 0 2 1 uA Down mode Current consumption Power 34 uA on reset circuit when enabled Current consumption Main 67 uA 14 7456 MHz crystal crystal oscillator Current consumption RF 9 1 mA Current for RF transceiver Transceiver Receive mode 11 9 alone 433 868 MHz Current consumption RF The output power is delivered Transceiver Transmit mode to a single ended 500 load 433 868 MHz see also page 123 Current is for RF transceiver alone P 0 01 mW 20 dBm 5 3 8 6 mA P 0 3 mW 5 dBm 8 9 13 8 mA P 1 mW 0 dBm 10 4 17 mA P 2 5 mW 4 dBm 24 8 mA 23 5 P 10 mW 10 dBm 26 6 NA mA 32 kHz oscillator crystal load 12 pF capacitance TEXAS INSTRUMENTS Table 4 Electrical specifications SWRS047 Page 7 of 152 Chipcon Products from Texas Instruments 61010 6 ADC Parameter Min Typ Max Unit Condition Number of bits 10 bits Differential Nonlinearity DNL
8. oua ata zua u sua 918 Lua 92 00000000 IHNVH NANYE NOONWH 15x0 Lp UMOYS aie pue Ja sIBal sseJppe ui Sys Ile Jo Alewwns v 21 00000000 OLNOdNO LINOdNO ZINJ INOdHO SINOdNO 91NOdHO L1NOdNO 1NOdNO 99 0 11 00000000 4 4 1 0 90 0 445 82 yesou u sua 9138 010122 1uouinjgjsu SEXO 12npoagd uoodiu5 D 000 S1uounajsu Sexo from Texas Instrumente 2071010 29 Alphabetic Register Index ACC 0xE0 Accumulator Register ADCON 0x93 ADC Control Register ADCON 2 0 96 ADC Control Register 2 ADDATH 0x95 ADC Data Register High Bits ADDATL 0x94 ADC Data Register Low Byte ADTRH 0x97 ADC Threshold Register B 0xF0 B Register BSYNC 0xD4 Byte Synchronisation Register CAL 0 5 PLL Calibration Control Register CHVER 0x9F Chip Version Revision Register CKCON 0x8E Timer Clock rate Control Register CRPCNT 0xC6 Encryption Decryption Counter CRPCON 0xC3 Encryption Decryption Control Register CRPDAT 0xC5 Encryption Decryption Data Lo
9. tIN3HHOO 5 21531 84x0 82 00000000 0 LINIdHO Z LINIdHO T S LINIdHO 9 LINIdHO L LINIdHO 00000 0OVG 1vO Lovd NO 1v9 OVG NO 11521 V3Xxo 84 00000000 O OINIdSO Z OlNIdNO OINIdNO S OINIdHO SOINI JYI ZOINIGHD OINIdHO vaxo 3000000 OAVHHY LAVHHV ZAVHHY EAVHHV E 01551 630 00000000 5 gt 3 ve 00000LLL did Zld dvd Eld l d dia 83x0 00000000 x E E zao 62 10000000 0 I3dvHs4 Vad VHS 2 4 5 13dVHS3 V I3dvHS4 S 3dVHS3 9 13dVHS4 L 3dvHS3 12x0 00000000 E 190 11000000 O Z3dvHS4 L 3dvHS4 ZZ3dvHS4 Z3dvHS4 VZ3dvHS4 S Z3dvHS3 9 Z3dvHS4 L Z3dvHS4 z3dvHSd 93X0 OS 10101100 Ved zed d ved 9 d 01100000 0 3dvHS4 VeadVHS4 Zt3dVHS4 3dVHS3 VE3dVHS4 S 3dvHS3 9 3dvHS4 l 3dVHS4 ___ S3X0 00000000 ONGVINH bavi ZHGViNH HGVINH HSVIJYM OdT HSYH Id Hsvid E NODT dvxo 01010000 O r3dvHS4 L P3dVHS4 Zv3dvHS4 v3dvHS3 V y3dvHSd 9 V3dvHS4 L v3dvHSd v3dvHSd vX0 v 00000000 avis zuavi4 guavid INGVd 3vxo 62 00001000 0 S3dvHS4 V S3dvHs4 Z 53dvHS4 S3dVHS3 vS3dvHS4 S 53dVHSJ 9 S3dvHS4 I S3dvHS4 S3dvHS4 30 09 00000000 O
10. f X32 PD RW 1 32 768 kHz oscillator power down signal 0 The oscillator is powered up 1 The oscillator is powered down default after reset 0 CMODE RW 0 Select different Clock Modes for the 8051 and its peripherals 0 Clock Mode 0 is selected default after reset 1 Clock Mode 1 is selected SWRS047 Page 36 of 152 TEXAS INSTRUMENTS Chipcon Products from Texas Instruments 15 10 Flash Program Memory 01010 has 32 kBytes of on chip Flash program memory It is divided into 256 pages of 128 bytes each It can be programmed erased through a serial SPI interface or page by page from the 8051 as described in the following sections The endurance for the Flash program memory is typically 20 000 erase write cycles The Flash program memory can be locked for further reading writing by setting appropriate lock bits through the serial interface Chip erase must be performed to unlock the memory This provides a way to prevent software from being copied by 15 11 SPI Flash Programming The on chip Flash program memory can be programmed using the SPI Flash programming protocol described in this section SPI Flash programming is enabled when the pin PROG is held low This enables the SPI slave using the pins SCK P0 0 as the clock input SI PO 1 as the serial data input and SO P0 2 as the serial data output A Windows based Flash programmer is also available free of charge at the Ch
11. Chi Prod from Texas instruments 6610 10 C1010 Single Chip Very Low Power RF Transceiver with 8051 Compatible Microcontroller Applications Very low power UHF wireless data e RKE Remote Keyless Entry with transmitters and receivers acknowledgement 315 433 868 and 915 MHz ISM SRD Low power telemetry band systems Toys Home automation and security AMR Automatic Meter Reading Product Description The 201010 is a true single chip UHF transceiver with integrated high performance 8051 microcontroller with 32 kB of Flash program memory The RF transceiver can be programmed for operation in the 300 1000 MHz range and is designed for very low power wireless applications The 221010 together with a few external passive components constitutes a powerful embedded system with wireless communication capabilities 1010 is based on Chipcon s SmartRF 02 technology in 0 35 um CMOS Key Features 300 1000 MHz RF Transceiver e 8051 Compatible Microcontroller e Very low current consumption 9 1 Typically 2 5 times the performance mA in RX of a standard 8051 High sensitivity typically 107 dBm 32 Flash 2048 128 Byte SRAM e Programmable output power up to 3 channel 10 bit ADC 4 timers 2 10 dBm PWMs 2 UARTs RTC Watchdog Data rate up to 76 8 kbps SPI DES encryption 26 general I O e Very few external components pins Fast PLL settling all
12. BSYNC 0xD4 Byte Synchronisation egister Bit Name RIW Reset value Description 7 0 BSYNC 7 0 RW 0x00 BSYNC defines the byte that triggers byte synchronisation during RF preamble detection TEXAS INSTRUMENTS SWRS047 Page 102 of 152 Chipcon Products from Texas Instruments The hardware support for preamble detection consists of a seven bit counter which keeps track of the number of successive alternating bits It is reset whenever two bits are equal and incremented whenever two successive bits are different The counter is limited and will not overflow A seven bit threshold is programmable through PDET PLEN Not until this counter equals or exceeds PDET PLEN will a synchronization byte be accepted 221010 is able to detect preambles including the synchronization byte with minimum lengths from 10 to 135 bits When the requisite number of alternating zeros and ones has been received a special state is entered where a deviation from the 0 1 pattern is searched for Once a bit does not correspond to the alternating bits pattern a synchronization byte matching that defined in BSYNC must occur within a maximum of seven bits otherwise the receiver will reset its preamble counter and go back to the preamble detection mode If however a match is found before the timeout the synchronization byte is transferred to RFBUF and an EXIF RFIF interrupt request gene
13. 3 0 VCO ARRAY 3 0 R 0x00 Status vector defining the applied VCO array TEXAS INSTRUMENTS SWRS047 Page 115 of 152 Chipcon Products C from Texas Instruments Start single calibration Y Write FREQ A FREQ Write CAL CAL DUAL 0 2071010 Frequency register A is used for RX mode register B for TX IAS PD 0 RX frequency register A is calibrated first Write CURRENT VCO CURRENT RX current Write PLL REFDIV RX reference divider Write TEST6 0x1B RX current is the VCO current to be used in RX mode Write CAL CAL_START 1 Wait for maximum 26 ms Read CAL and wait until CAL CAL_COMPLETE 1 Write CALCAL START 0 Calibration is performed in RX mode Result is stored in TESTO and TEST2 RX register Calibration time depends on the reference frequency see text Write RFMAIN 1 F REG 1 PD 1 TX PD 0 FS PD 0 CORE PD 0 PD 0 RESET N I TX frequency register B is calibrated second v Write CURRENT VCO CURRENT TX current TX current is the VCO current to be Write PLL REFDIV TX reference divider used in TX mode Write TEST6 0x3B PA is turned off to prevent spurious Write 0x00 emission Write CAL CAL_START 1 Y Wait for 26 ms or Read CAL and wait until CAL CAL_COMPLETE 1 Write C
14. ENCODER JconTroL 4 REGISTERS IBIAS 41 9 R_BIAS LPF 6 PD R lt 05 Figure 19 Simplified block diagram of the RF Transceiver A simplified block diagram of the RF transceiver is shown in Figure 19 Only analog signal pins are shown together with the internal SFR data bus that is used to TEXAS INSTRUMENTS configure the RF interface and to transmit and receive data In receive mode the 661010 is configured as a traditional super heterodyne receiver The RF input signal is amplified by the SWRS047 Page 83 of 152 Chipcon Products C from Texas Instruments low noise amplifier LNA and converted down to the intermediate frequency IF by the mixer MIXER In the intermediate frequency stage IF STAGE this down converted signal is amplified and filtered before being fed to the demodulator DEMOD As an option a RSSI signal or the IF signal after the mixer is available at the AD2 RSSI IF pin After demodu lation the digital data is sent to the RFBUF register Interrupts can be generated for each bit or byte received EXIF RFIF In transmit mode the voltage controlled oscillator VCO output signal is fed directly to the power amplifier PA The RF output is frequency shift keyed FSK by the digital bit stream fed to the RFBUF register Interrupts can be generated for TEXAS INSTRUMENTS 207101
15. External Interrupt 0 from P3 2 interrupt priority control 0 Interrupt has low priority Interrupt has high priority EIP 0xF8 Extended Interrupt Priority Register Bit Name R W Reset value Description 7 R1 1 Reserved read as 1 6 R1 1 Reserved read as 1 5 R1 1 Reserved read as 1 4 PRTC RW 0 Realtime Clock interrupt priority control Interrupt has low priority 1 Interrupt has high priority 3 RW 0 Timer 3 interrupt priority control 0 Interrupt has low priority 1 Interrupt has high priority 2 PAD RW 0 ADC DES interrupt priority control 0 Interrupt has low priority 1 Interrupt has high priority 1 PT2 RW 0 Timer 2 interrupt priority control 0 Interrupt has low priority interrupt has high priority 0 PRF RW 0 0 Interrupt has low priority 1 Interrupt has high priority TEXAS INSTRUMENTS SWRS047 Page 31 of 152 Chipcon Products C from Texas Instruments 15 7 External interrupts Two external interrupt pins are available in the 221010 They are located on pins P3 2 and P3 3 and can be set up to be either level or edge sensitive by setting the IT1 and IT2 bits in the TCON register see page 54 for more information When the external interrupts are activated in the IE 15 8 Main Crystal Oscillator An external clock signal or the main crystal oscillator can be used as main frequency reference and microcont
16. that enabled Idle Mode Activate any reset condition All registers are then reset and program execution will resume from address 0x0000 when the reset condition is cleared the power off and on The Power On Reset module should then be enabled or an external reset signal should be applied during power up TEXAS INSTRUMENTS 2071010 15 9 3 Power Down Mode After completing the instruction that sets the PCON STOP bit the controller core and the peripherals are stopped In Power Down Mode the clock trees of the 8051 and peripherals are disabled Only the ADC clock tree is running This enables the ADC to generate reset as will be described in the ADC section Note that the PCON STOP bit does not affect the clock oscillators these will still be running if they are switched on when entering Power Down Mode To ensure minimum power consumption the ADC should be switched off and Power down mode should be entered by switching off the oscillators instead of using the PCON STOP bit There are 2 ways to exit Power Down Mode Activate any reset condition All registers are then reset and program execution will resume when the reset condition is cleared Program execution will then resume from address 0x0000 e the power off and on The Power On Reset module should then be enabled or an external reset signal should be applied during power up More information about minimising the
17. 0 2 LSB VDD is reference voltage Integral Nonlinearity INL 1 3 LSB VDD is reference voltage Offset 3 LSB 7 Hz test tone Total Harmonic Distortion 59 dB 7 Hz test tone THD SINAD 54 dB 7 Hz test tone 9 bits Internal reference tolerance 10 Conversion time 44 us When ADC is operated at 250 kHz Clock frequency 32 250 250 kHz 250 kHz recommended for full 10 bit performance External reference voltage 13 2T External reference voltage should never exceed 2 7 V It is recommended to use a reference voltage close to 1 3 V to have the best possible linearity Input voltage 0 Vref 7 section general Table 5 ADC characteristics Parameter Min Typ Max Unit Condition RF Frequency Range Data rate 300 1000 MHz 0 6 76 8 kBaud Programmable in steps of lt 250 Hz NRZ or Manchester encoding 76 8 kBaud equals 76 8 kbps using NRZ coding See page 94 Table 6 General RF characteristics TEXAS INSTRUMENTS SWRS047 Page 8 of 152 Chipcon Products from Texas Instruments 8 RF transmit section 2071010 Chipcon Products 2 from Texas Instruments 9 RF receive section 2071010 Parameter Min Typ Max Unit Condition Parameter Min Typ Max Unit Condition Binary FSK frequency
18. 2048 byte pu azke LE PregammmgDMA SRAM Pats FLASH E J E Timers 128 byte PWMs SRAM 8051 core Timers Watchdog 5 17 Counters General 7 S pupose tio PROG TAE eal L uarts Special Function Realtime eh Registers ____ ___ clock SFRs 32 kHz crystal ADO K ADI DOE System Multiplexer AD2 MUX lock RSSUF REIN CODEC Bit synchronizer Iran SM SeraizerDeseralzer A Bias resistor A Main Crystal 7 e 1 Oscilator 3 24 MHz VCO inductor Figure 2 CC1010 Block Diagram SWRS047 Page 18 of 152 TEXAS INSTRUMENTS Chipcon Products from Texas Instruments 15 8051 Core 15 1 General description The 667010 microcontroller core is based on the industry standard 8051 architecture The MCU core is 8 bit with program and data memory located in separate memory spaces Harvard architecture The internal registers are organised as four banks of 8 registers each The instruction set supports direct indirect and register addressing modes Program memory can be addressed using indexed addressing The core registers are comprised of an accumulator a stack pointer and dual data pointer registers in addition to the general registers Data memory is split into internal and external RAM The name external RAM is in fact misleading since in the case of the 227010 all the RAM is internal to the chip The difference between external and int
19. 5 96 0 E xxm 5 860 601 _ 001000 Twav Hwaviv qavsi wav EFEN Tid 99 00000000 0 0n8s ones 2 03185 04085 yoangs s ognas 903ngs Zonas 66x0 zi 11110000 N3MOdMOT Vd s3MOdMOT Vd YSMOdMOT Vd 3MOdMOT Vd H3MOdH9IH Vd Vd N3MOdHOIH Vd Vd MOd Vd zaxo 19 00000000 0 TH ou 0 88 0 0 0 ZWS 0 WS 0 OWS ONOOS 86x0 OLOLOOLL O3AING Vd LINAO Vd O1 O7 ZIN3HNAO ODA 13X0 28 00000000 LHHLOV EHHLOV vHHLOV SHHLOV SHYLA HHIGV 26 0 ez 00000000 000v 190v ZOOW 2007 TOOV 9007 9007 190v OOV 03X0 28 00000000 3loav ZNOOQV 96X0 00000000 daxo 18 00000000 Sivdav 61vaav E B E Hivaay Sexo 00000000 00000000 oLvagy zivaav lvdav vivaav s1vaav 91vaav 1lvdav vady 6 0 01010000 O3WILOM TINOM ZANILOMTS ESNILOMTS VANILOMT4 S3NILOM 1d wild 00000001 ouavav Luavav Nnuoav Jduodqv OWOQV 1WOGV E ad av NOOGV 6 02 00000000 OHOLW XL LHOLVIW XL ZHOLVW XL HO1VIN XL OHOLW LHOLVIN ZHOLVN HOLVIN XY HOLVN OQX0 zz 00000000 035VdW 13OVdW z3ovdw 3ovd
20. called splattering may occur This will result in a very wide RF spectrum that may intrude into neighbouring channels or extend out of band To minimise this effect Chipcon recommends that the PA POW register be used to turn the PA gradually on and off The optimal pattern is to follow the sequence 0x00 0x01 Ox1E Ox8F OxEF when going from RX to TX and consequently using OxEF Ox8F Ox1E 0x01 0x00 when going from TX to RX PA POW should be left set to 0x00 in RX mode and OxEF in TX mode SWRS047 Page 132 of 152 Chipcon Products from Texas Instruments 19 10 PCB Layout Recommendations Chipcon provide reference layouts that should be followed in order to achieve the best performance The reference designs can be downloaded on the Chipcon website A four layer PCB is highly recommended The top layer should be used for signal routing and the open areas should be filled with metallisation connected to ground using many vias The second layer of the PCB should be the ground plane Layer three is used for power supply and layer four for general routing and decoupling A few components are also placed at the reverse side VCO inductor and power filtering The ground pins should be connected to ground as close as possible to the package pin using individual vias for each pin The de coupling capacitors should also be placed as close as possible to the supply pins and connected to the ground plane by separate
21. 15 12 8 Write Lock Bits The reading through SPI and writing to the Flash program memory can be disabled by setting the lock bits as described in this section This should be used for software protection The lock bits are set using the Write Lock Bits instruction A block of programmable size at the top of the Flash program memory can be locked for writing using the LSIZE bits Page 0 can be independently locked for writing by using the BBLOCK bit Reading data through the SPI interface can be disabled using the SPIRE bit The detailed description of all lock bits is given in Table 18 TEXAS INSTRUMENTS 2071010 Bit Name Function T3 Reserved write as 0 4 BBLOCK Boot Block Lock 0 Page 0 is write protected 1 Page 0 is writeable unless LSIZE is 000 3 1 LSIZE 2 0 Lock Size sets the size of the upper Flash area which is write protected Byte sizes and page numbers are listed below 000 32768 All pages 001 16384 page 128 255 010 8192 page 192 255 011 4096 page 224 255 100 2048 page 240 255 101 1024 page 248 255 110 512 page 252 255 111 0 no pages 0 SPIRE SPI Read Flash Enable Disable 0 SPI Interface returns all zeros on the Read Program Memory instruction 1 SPI Interface returns valid Flash data on the Read Program Memory instruction Table 18 Flash Lock Bits Lock bits can only be erased set high by issuing the Ch
22. Chipcon Products C from Texas Instruments 2071010 System clock Watchdog Prescaler Enable P WDTPRE 1 0 WDTCLR Clear 8 Bit Watchdog Counter Enable Overflow WDTEN System Reset Figure 14 Watchdog Timer Setting different prescaler settings combined with different Main Crystal Oscillator frequencies generates reset at an interval of 256 2 CHWDTPRE The intervals for the maximum and minimum clock frequencies are shown in Table 21 below WDTPRE 1 WDTPRE O Division Rate Reset timing given Reset timing given fxosc 3MHz fxosc 24MHz 0 0 2048 175 ms 21 8 ms 0 1 4096 350 ms 43 7 ms 1 0 8192 699 ms 87 4 ms 1 1 16384 1400 ms 175 ms Table 21 Watchdog Timer timing 16 5 1 Disabling the Watchdog Timer The Watchdog Timer is enabled after System reset through the Watchdog Timer enable flag WDT WDTEN To disable the Watchdog Timer this flag must be cleared However clearing this flag requires the user to first set the flag WDT WDTSE and then clearing WDT WDTEN within 16 system clock periods preferably in the next instruction TEXAS INSTRUMENTS If interrupts are enabled while disabling the Watchdog Timer the user must make sure that WDT WDTEN is actually cleared This could for instance be done as follows SWRS047 Page 64 of 152 Chipcon Pr
23. LAV 30S ZAV 5 AV130S4 VAY 30S SAV130S4 9AV 30S 1Av130S4 AVTaqS4 6 22 00000000 OOM vds 5 5 usds 6z 00000111 EEN 213 ETa 13 31014 E 8270 Z1 00000000 08045 14845 24045 64045 puads SHdds 9udds 1HddS wads zvxo Sp 00000000 0 G3AH3S3H ECEE ZG3AH3S3H d3AHasaH EEGEN S T3AN3S3H S d3AN3S3H L G3AH3S3H G3AWSSSM 3X0 zz 00000000 0895 Jogo quoa 3ds MOdS Ivxo H H OS 0 Ved ted Ezd ved S Zd 97d Id Zd 0vxo 62 00000000 0 31vOS3ud 5 ANOUS 3l 4 OLNSYYND Yd OONIMS Yd LONIMS Sud 5 93x0 abed yesoy zua u vua sua 918 Lua owen abed 3050Y DET zua eua vua sua 918 0 s3uoumnajsu 0 223 s3u9unajsu sexoj uoodiu3 j2npoag uo2diuj SINTATHISN SINTWIMISM SVKaL SAL 29130 Lvl Zy0SYMS 29 Jo p afed Zv0SYMS Sv 10000000 OATH diHO VAM 03921 badAL 9 dlHO vadAL SAdAL YIAHO Jexo 10100000 z3lvHall 3I31dWOO WO INIAN WO Wo LEVIS VO wo saxo 00000000 E E E E 360 HLONST AOWVENDOV 00000000 i 46 0 OLL XX000000 INVISN 5001 73001 Tid 3001 v3xo 00000000
24. Nominal setting 1 Output of IF Front amp is switched to the AD2 RSSI IF pin 1 RW 0 Reserved for future use always write 0 0 0 Reserved for future use always write 0 TESTMUX 0xEF Test Multiplexer Control Register for prototype testing Bit Name RIW Reset value Description TA RO 0x00 Reserved read as 0 3 0 TESTMUX R W 0x00 Select internal test signals to be output to PO 2 0 3 0 This function is enabled when TESTMUX 0000 The port directions are still set by PODIR TEXAS INSTRUMENTS SWRS047 Page 130 of 152 Chipcon Products from Texas Instruments 2071010 19 System Considerations and Guidelines 19 1 SRD regulations International regulations and national laws regulate the use of radio receivers and transmitters SRDs Short Range Devices for licence free operation are allowed to operate in the 433 and 868 870 MHz bands in most European countries In the United States such devices operate in the 260 470 and 902 928 MHz bands 22 070 is designed to meet the requirements for operation in all these bands A summary of the most important aspects of these regulations can be found in Application Note AN001 SRD regulations for licence free transceiver operation available on Chipcon s web site 19 2 Low cost systems In systems where low cost is of great importance the 661010 is the ideal choice Very few external comp
25. after Idle Mode is entered No data will be written It is not possible to read or write the Flash lock bits from the 8051 s INSTRUMENTS 15 13 1 Example Code Example C code writing data buffered at address 0x100 0x17F in external RAM to the second page in Flash address 0x080 OxOFF is shown below The system clock frequency is assumed to be 3 6864 MHz An interrupt service routine must be present at address 0x33 which clears the interrupt flag EICON FDIF and returns from the interrupt RETI SWRS047 Page 43 of 152 Chipcon Products from Texas Instruments C1010 FLTIM 0x05 Set Flash timing for 3 6864 MHz clock frequency FLADR 0x01 Write data to the second page in Flash EICON 0x20 Enable Flash interrupt IE amp 0x80 Disable other interrupts FLCON 0x10 0x100 gt gt 7 Enable Flash writing RAM buffer from addr 0x100 0 01 Enter Idle Mode to start Flash writing 15 14 Flash Power Control The Flash module can be set into different power modes using the control bits FLCON FLASH LP 1 0 introduced in the previous section After reset the Flash module is always active drawing static current of approximately 2 5 mA at nominal 15 15 In Circuit Debugging In order to facilitate a software monitor for in circuit debugging emulation capabilities a number of hardware support features have been implemented A breakpoint instruction has bee
26. be used to do the temperature compensation of the crystal if the temperature drift curve is known and a temperature sensor is included in the system Even initial adjustment can be done using the frequency programmability This eliminates the need for an expensive TCXO and trimming in some applications In less demanding applications a crystal with low temperature drift and low ageing could be used without further compensation A trimmer capacitor in the crystal oscillator circuit in parallel with C171 could be used to set the initial frequency accurately The fine frequency step programming cannot be used in RX mode if optimised frequency settings are required see page 111 19 5 High reliability systems Using a SAW filter as preselector between the antenna and the RF input will improve the communication reliability in harsh environments by reducing the probability of blocking The receiver sensitivity and the output power will be reduced due to the filter insertion loss By inserting the filter in the RX path only together with an external RX TX switch only the receiver sensitivity is reduced and output power is unaffected Any general purpose I O pins can be SWRS047 Page 131 of 152 Chipcon Products from Texas Instruments configured to control an external LNA RX TX switch or power amplifier 19 6 Frequency hopping spread spectrum systems Due to the very fast frequency shift properties of the PLL the 027
27. before reading the newly received byte in order to maximise the data rate If data is written to SPDR while a transmission is in progress this is regarded as a collision After each new byte written to SPDR the write collision flag SPSR WCOL is updated If a collision occurs the data written to SPDR is ignored and the data must be written to SPDR again for it to be sent 61010 It is also possible to check the SPI status bit SPSR SPA before writing to SPDR to avoid collisions This bit is set only when data is being transmitted SPI timing data order clock polarity and clock phase are shown in Figure 18 It is also possible to use the master SPI interface to interface with a two pin serial interface that uses a bi directional data line such as the interface used by the Chipcon CC1000 RF transceiver In this case you would connect the MO and MI pins together on your PCB as shown in Figure 17 In the software the PODIR 1 bit must be set correctly according to whether data is being written or read MO MI DIO DCLK SCK C1010 Two wire peripheral Figure 17 Two wire serial interface TEXAS INSTRUMENTS SWRS047 Page 73 of 152 Chipcon Products from Texas Instruments 2071010 SPDR is written by 8051 here while SPCR SPE is active SCK CPOL 0 CPHA 0 SCK CPOL 0 CPHA 1 SCK CPOL 1 CPHA 0 SCK
28. high byte DPL1 0x84 Data Pointer 1 low byte Bit Name RW Reset value Description 7 0 DPL1 7 0 0x00 Data Pointer 1 low byte DPH1 0x85 Data Pointer 1 high byte Bit Name RW Reset value Description 7 0 DPH1 7 0 R W 0x00 Data Pointer 1 high byte SWRS047 Page 21 of 152 TEXAS INSTRUMENTS Chipcon Products from Texas Instruments DPS 0x86 Data Pointer Select 2071010 Bit Name RW Reset value Description TA RO 0x00 Reserved read as 0 0 SEL RW 0x00 Data Pointer Select for external RAM access 0 DPHO and DPLO are used 1 DPH1 and DPL1 are used MPAGE 0x92 Memory Page Select Register Bit Name Reset value Description 7 0 MPAGE 7 0 R W 0x00 Memory Page A total of 119 Special Function Registers SFRs are accessible from the microcontroller core The names and addresses of all SFRs are listed in Table 11 All standard 8051 registers are available in addition to SFRs which are 1010 specific controlling modules such as the RF Transceiver DES encryption ADC and Real Time Clock All SFRs will be described in the following sections A more detailed overview is provided in Table 41 on page 144 which also includes all reset values SFRs with addresses ending with O or 8 leftmost column of Table 11 are bit adressable 0 8 179 3 8
29. 0 64 65 kHz The frequency corresponding Receiver Sensitivity 107 dBm 2 4 kBaud Manchester coded separation to the digital 0 is denoted fo 433 868 MHz 106 data 64 kHz frequency while f corresponds to a separation BER 10 digital 1 The frequency separation is See Table 33 and Table fi fo The RF carrier 34page 105 for typical frequency fc is then given by sensitivity figures at other 2 data rates The frequency deviation is given by fa f1 fo 2 System noise bandwidth 30 kHz 2 4 kBaud Manchester coded The frequency separation is data programmable in 250 Hz Cascaded noise figure 12 13 dB steps Separations up to 65 433 868 MHz kHz are guaranteed at 1 MHz reference frequency Larger Saturation maximum input 10 dBm 2 4 kBaud Manchester coded separations can be achieved level data BER 10 at higher reference frequencies 1 dBm 76 8 kBaud NRZ BER 103 Input IP3 26 dBm From LNA to IF output Output power 20 0 10 4 dBm Delivered to single ended 50 433 868 MHz Q load Blocking 40 dBc At 1 MHz The output power is programmable see page 123 LO leakage 57 dBm RF output impedance 140 80 Q Transmit mode optimum load Input impedance Receive mode series 433 868 MHz impedance For matching equivalent details see Input output 90413 e at 315 MHz matching p 120 68 24 Q at 433 MHz 3611 at 868 MHz Harmonics Conducted measur at 3613 Q at 915 MHz maximum output power An 2 harmonic 433 868 MHz 71 1
30. 17 MOV direct Ri Move data memory to direct byte 2 2 86 87 INC DPTR Increment data pointer 1 3 MOV direct data Move immediate to direct byte 3 3 75 MUL AB Multiply A by B 1 5 x x x MOV Ri A MOV A to data memory 1 1 F6 F7 DIV AB Divide A by B 1 5 84 x x x MOV Ri direct Move direct byte to data memory 2 2 A6 DA A Decimal adjust A 1 1 D4 x x AT Logical MOV Ri data Move immediate to data memory 2 2 76 77 ANL A Rn AND register to A 1 1 58 5F x MOV DPTR data Move immediate to data pointer 3 3 90 ANL A direct AND direct byte to A 2 2 55 x A A DPTR Move code byte relative DPTR to 1 3 93 x ANL A Ri AND data memory to A 1 1 56 57 x A ANL A data AND immediate to A 2 12 54 x MOVC Move code byte relative PC to A 1 8 83 x ANL direct A AND A to direct byte 2 2 52 MOVX A Ri Move external data A8 to A 1 2 9 Es x ANL direct data AND Immediate data to direct byte 3 3 53 MOVX GDPTR Move extemal data A16 to A 1 29 x peu MOVX Ri A Move A to external data A8 1 29 F2F3 ORL Wa Sees OR direct byte Yo e MOVX DPTR A Move A to external data A16 1 29 Fo ORL Ay ERE OR data memory to A LE MEE x PUSH direct Push direct byte onto stack 2 2 ORL A date ORimmediate tah 2 2 4 x POP direct Pop direct byte from stack 2 2 00 ORL direct OR to direct byte 2 12 42 Exchange and register A 1 C8 x ORL direct
31. 2071010 parity flags that reflect the current CPU state In addition the CPU uses the accumulator register A accessed via the SFR space as ACC B for multiplication and division and the stack pointer SP These registers are shown below Note that the hardware stack pointer SP is increased when pushing and decreased when popping data unlike many other microcontroller architectures Bit Name RW Reset value Description T cx RW 0 Carry Flag set to 1 when the last arithmetic operation resulted in a carry during addition or borrow during subtraction otherwise cleared to 0 by all arithmetic operations CY is also used for rotation instructions 6 AC RW 0 Auxiliary carry flag Set to 1 when the last arithmetic operation resulted in a carry into during addition or borrow from during subtraction the high order nibble otherwise cleared to 0 by all arithmetic operations 5 FO RW 0 Flag 0 Available to the user for general purpose 4 RS1 RW 0 Register bank select 3 RSO RW 0 RS1 RSO Working register bank and address 0 0 0 00 0 07 0 1 Bank1 0x08 0x0F 1 0 Bank2 0 10 0 17 1 1 Bank3 0x18 0x1F 2 ov RW 0 Overflow flag Set to 1 when the last arithmetic operation resulted in a carry addition borrow subtraction or overflow multiply or divide Otherwise the bit cleared to 0 by all arithmetic operations 1 Fl RW 0 Flag 1 Available to the user for general purpose 0
32. 4 5 0 GE TIF OxF8 EIP TESTO TESTl TEST2 TEST3 TEST4 TESTS TEST6 OxFO B FSHAPE7 FSHAPE6 FSHAPES FSHAPE4 FSHAPE3 2 FSHAPEl OxE8 EIE FSDELAY FSEPO FSEP1 FSCTRL RTCON FREND TESTMUX OxEO ACC CURRENT PA POW PLL LOCK CAL PRESCALER RESERVED 0 08 EICON MODEM2 MODEMI MODEMO MATCH FLTIM 0xDO PSW X32CON WDT PDET BSYNC OxC8 RFMAIN RFBUF FREQ 0A FREQ 1 FREQ 2A FREQ FREQ 1B FREQ 2B OxCO SCON1 SBUF1 RECON CRPKEY CRPCNT RANCON 0xB8 IP RDATA RADRL RADRH CRPINI4 CRPINIS CRPINI6 CRPINI7 OxBO P3 CRPINIO CRPINI1 CRPINI2 CRPINI3 IE TCON2 T2PRE T3PRE T2 T3 FLADR FLCON 2 SPCR SPDR SPSR PODIR PIDIR P2DIR P3DIR 0x98 SCONO SBUFO CHVER 0x90 P1 EXIF MPAGE ADCON ADDATL ADDATH ADCON2 ADTRH 0x88 TCON TMOD TLO TLI THO THI CKCON 0x80 PO SP DPLO DPHO DPLI DPS PCON Table 11 200 SFR Overview SWRS047 Page 22 of 152 TEXAS INSTRUMENTS Chipcon Products from Texas Instruments 15 4 CPU Registers CCIOIO provides 4 register banks of 8 registers each These register banks are mapped in the the internal data memory see the Memory section on page 33 at addresses 0x00 0x07 0x08 OxOF 0x10 0x17 and 0x18 Ox1F Each register bank contains the 8 8 bit registers RO through R7 The different register banks are selected through the Program Status Word PSW RS 1 0 as shown below PSW also contains carry overflow and PSW 0 00 Program Status Word
33. 6 1 255 1 254 0 255 1 252 1 251 1 250 192 1 253 1 250 0 253 0 252 1 241 1 238 9 6 1 250 1 244 0 250 0 248 1 226 1 220 4 8 1 244 1 232 0 244 0 240 1 196 1 184 24 1 232 1 208 0 232 0 224 1 136 1 112 1 2 1 208 1 160 0 208 0 192 1 16 0 160 Table 23 Baud rate examples SMODx 1 16 7 2 MODE1 Mode 1 provides standard asynchronous full duplex communication using a total of 10 bits 1 start bit 8 data bits and 1 stop bit For receive operations the stop bit is stored in SCONO RB8 0 or SCON1 RB8 1 Data bits are received and transmitted with their LSB first The baud rate for mode 1 is a function of timer 1 overflow Each time the timer increments from its maximum count OxFF a clock pulse is sent to the baud rate circuit to be further divided by 16 or 32 as set by PCON SMODO EICON SMOD1 to give the baud rate SMODx Baud Rate Timer overflow As can be seen from the equation above if both serial ports are in use simultaneously the baud rate is equal or different by a factor 2 It is common to use Timer 1 in Mode 2 8 bit counter with auto reload for baud rate generation although any timer mode can be used The Timer 1 reload value is stored in the TH1 register which makes the complete baudrate using mode 2 asi Baud Rate 32 12 8 1 256 TH1 TEXAS INSTRUMENTS 1 in the above equation is in register CKCON see page 55 and controls the i
34. 61010 Chipcon Products from Texas Instruments 61010 Mnemonic Description Mnemonic Description g g BE i sie e sie e 5 2 J b5 2 8 23 SUBB Ri Subtract data memory from A with 1 1 96 97 x x x x MOV A Ri Move data memory to A a i E6 x borrow ET SUBB A data Subtract immediate from A with 2 2 94 x x x x MOV A data Move immediate to A 2 2 74 x borrow MOV Rn A Move A to register 1 1 F8 FF INC A Increment A 4 1 04 x MOV Rn direct Move direct byte to register 2 2 AB INC Rn Increment register 1 1 08 0F AF INC direct Increment direct byte 2 2 05 data Move immediate to register 2 2 78 7F INC Ri Increment data memory 1 1 06 07 MOV direct A Move A to direct byte 2 2 F5 DEC A Decrement A 1 1 14 x MOV direct Rn Move register to direct byte 2 2 88 8F DEC Rn Decrement register 1 1 18 1F MOV direct Move direct byte to direct byte 3 3 85 DEC direct Decrement direct byte 2 2 15 direct DEC Ri Decrement data memory 1 1 16
35. 7 3 6 V supply voltage 40 85 C operational temperature 3 24 MHz crystal up to 50 ppm for the main crystal oscillator Packaging 64 lead TQFP SWRS047 Page 4 of 152 Chipcon Products from Texas Instruments 2 Absolute Maximum Ratings 2071010 Under no circumstances must the absolute maximum ratings given in Table 1 be violated Stress exceeding one or more of the limiting values may cause permanent damage to the device Parameter Min Max Units Condition Supply voltage VDD 0 3 5 0 V Voltage on any pin 0 3 VDD 0 3 V max 5 0 Input RF level 10 dBm Storage temperature range 50 150 Un programmed device Storage temperature range 40 125 C Programmed device data retention gt 0 49 years at 125 C Lead temperature 260 108 Table 1 Absolute Maximum Ratings Caution ESD sensitive device Precaution should be used when handling tad the device in order to prevent permanent damage 3 Recommended Operating Conditions Tc 40 to 85 C VDD 2 7 to 3 6 V if nothing else stated Parameter Min Typ Max Unit Condition Supply voltage DVDD AVDD 2 7 3 3 3 6 Supply voltage during normal operation Supply voltage DVDD AVDD 2 7 3 6 Supply voltage during program erase Flash memory Operating temperature free air 40 85 Main oscillator frequency 3 24 MHz RTC oscilla
36. 8Ri A and MOV Ri data use indirect addressing MOV A direct MOV Rn direct MOV direct A MOV direct Rn MOV direct direct and MOV direct data use direct addressing MOV Ri direct uses indirect and direct addressing All direct addressing instructions can also be used to access the SFRs 661010 also implements the option to access SFRs indirectly as described in the In Circuit Debugging section on page 44 661010 has dual data pointers to external RAM provided in the 16 bit registers DPTRO and DPTR1 SFRs DPHO DPLO DPH1 and DPL1 If a high level language compilator is used it should be set up to make use of both pointers for better performance The data pointer is selected through DPS SEL Access to the external RAM is performed using the Movx instruction and indirect addressing using either the 16 bit data pointers or the 8 bit registers RO or R1 together with MPAGE MOVX A DPTR and MOVX DPTR A moves data to from the accumulator TEXAS INSTRUMENTS 01010 from to the address pointed to by the currently selected data pointer The instructions Ri and GRi moves data to from the accumulator from to the address given by the memory page address register MPAGE and the register Ri RO or R1 MPAGE gives the 8 most significant address bits while the register Ri gives the 8 least significant bits In many 8051 implementations this type of external RAM access is perfo
37. End Control Register 2071010 Bit Name R W Reset value Description 76 RW 0 Reserved should always be written 0 5 BUF_CURRENT RW 0 Control of current in the LNA FOLLOWER 0 520uA use for f 500 MHz 1 690uA use for f 500 MHz 43 LNA_CURRENT 1 0 RAW 00 Control of current in LNA 00 0 8mA 01 1 4mA use for f lt 500 MHz 10 1 8mA use for f gt 500 MHz 11 2 2mA 2 IF EXTERNAL RW 0 Controls where the output from the mixer goes 0 To internal IF filter and demodulator 1 To the AD2 RSSI IF pin for external filtering and demodulation 1 RSSI 0 0 RSSI output disconnected from AD2 RSSI IF pin 1 RSSI output connected to AD2 RSSI IF pin Reserved should always be written 0 TEXAS INSTRUMENTS SWRS047 Page 119 of 152 Chipcon Products C from Texas Instruments 17 18 Input Output Matching A few passive external components combined with the internal T R switch circuitry ensures match in both RX and TX mode The matching network is shown in Figure 36 Component values for various frequencies are given in Table 28 Component values for other frequencies can be found using the SmartRF Studio software 2071010 The register MATCH should initially be set as shown in the register description below The MATCH register controls a capacitor array located at the RF_OUT pin The register can be used to fine tune the impedance ma
38. Germany Chipcon AS Riedberghof 3 D 74379 Ingersheim GERMANY Tel 49 7142 9156815 Fax 49 7142 9156818 Email Germanysales chipcon com Sales Office Asia Sales Office Korea amp South East Asia Chipcon AS Chipcon AS Unit 503 5 F 37F Asem Tower Silvercord Tower 2 30 Canton Road Samsung dong Kangnam ku Tsimshatsui Hong Kong Seoul 135 798 Korea Tel 852 3519 6226 Tel 82 2 6001 3888 Fax 852 3519 6520 Fax 82 2 6001 3711 Email Asiasales chipcon com Email KAsiasales chipcon com Sales Office Japan Chipcon AS 403 Bureau Shinagawa 4 1 6 Konan Minato Ku Tokyo Zip 108 0075 Japan Tel 81 3 5783 1082 Fax 81 3 5783 1083 Email Japansales chipcon com SWRS047 Page 152 of 152
39. Intel 8051 Peripheral units including general purpose I O 2 standard 8051 timers 2 extra timers with PWM functionality a watchdog timer a real time clock an SPI master interface hardware DES encryption a true random bit generator and ADC are all described from page 47 and out Dual data pointers are available for faster data transfer module as described in the Power On Reset Brown Out Detection section at page 62 e Brown out detection reset The POR will also detect low supply voltage and generate a reset e Watchdog timer reset The watchdog timer can generate a reset as described in the section on page 63 e ADC reset The ADC module can be programmed to generate a reset signal if its inputs exceed a programmed threshold See the ADC section on page 79 for details The POR and ADC reset signals will be held for 1024 clock periods after the signal is released This will ensure a safe clock start up if the crystal oscillator is currently not running SWRS047 Page 19 of 152 Chipcon Products from Texas Instruments 15 3 Memory Map The 207010 memory map is shown in Figure 3 01010 has 2 blocks of RAM on chip This includes the 128 bytes Internal RAM and the 2048 bytes External RAM The 2048 byte RAM will be referred to as External RAM although it is on chip Direct access to off chip RAM is not implemented Access to the internal RAM is performed using the MOV instruction MOV A Ri MOV
40. MHz 011 12 16 MHz 14 7456 MHz recommended 100 16 20 MHz 18 4320 MHz recommended 101 20 24 MHz 22 1184 MHz recommended 110 Reserved for future use 111 Reserved for future use TEXAS INSTRUMENTS SWRS047 Page 93 of 152 Chipcon Products C from Texas Instruments 17 7 Baudrates Baud rates from 0 6 kBaud to 76 8 kBaud are programmable in the MODEMO BAUDRATE control bits MODEMO XOSC FREQ must also be set BAUDRATE 2 2071010 according to the crystal in use Baud rates are generated as follows RF RF_BAUDRATE is the output baud rate in kBaud BAUDRATE and XOSC_FREQ are control bits in MODEMO Using one of the standard crystals mentioned the MODEMO XOSC FREQ description will produce the standard baud rates 0 6 1 2 2 4 4 8 9 6 19 2 38 4 or 76 8 kBaud XOSC FR Js 0 6 kBaud EQ 1 3 6864 MHz Other crystal frequencies will scale the baud rate as described above Baud rates up to and including 19 2 kBaud can be generated for any crystal frequency Above 19 2 kBaud a few combinations are possible as shown in Table 30 MODEMO BAUDRATE MHz 1 05 FREQ RF_BAUDRATE 3 6864 7 3728 11 0592 14 7456 18 4320 22 1184 kBaud 0 6 0 0 0 1 0 2 0 3 0 4 0 5 1 2 1 0 1 1 2 1 3 1 4 1 5 24 2 0 21 2 2 2 3 2 4 2 5 48 3 0 3 1 3 2 3 3 3 4 35 9 6 4 0 4n 4 2 4 3 4 4 4 5 19 2 5 0 5 1 5 2 5 3 5
41. Memory Page at address a Read Program o010 aaaa aaaa bbbb bbxx oooo Read data o at address Memory a b H Write Lock Bits Bits aidi daiji written will be ANDed Write Lock Bits 1010 1100 111x xxxx XXXX XXXX iiii iiii together with the existing lock bits Read Lock 0101 1000 xxxx xxxx xxxx 0000 0000 Read lock bits Bits Read 0011 0000 xxxx xsss 0000 0000 Read signature byte Signature Byte at address 5 a Page address s Signature byte address b Even byte address i Input data H Odd or even high or low byte 0 Output data Clock timing bits x Don t care Table 16 SPI Flash Programming Instructions Each instruction is sent in the order bytes 1 to 4 most significant bits first All 4 bytes must be sent even if the last bits are x TEXAS INSTRUMENTS The timing for the SPI interface is shown in Figure 5 All timing parameters are listed in Table 17 SWRS047 Page 38 of 152 Chipcon Products from Texas Instruments Tsck high Tsck low 61010 Tsck rise Tsck fall SCK P0 0 Lr VI SI P0 1 4 y y 31 Yo y so P0 2 1 aX Y j pig Tsi setup Tsi hold Tso delay Figure 5 SPI Flash Programming Timing Symbol Min Max Units Conditions Fsck fxosc 8 Tsck high 4 Txosc The minimum time SCK must be held high Tsck low 4 Txosc The
42. N A Performed by Performed Performed by Regeneration UART internally A hardware violation to the Manchester coding format is reported in MVIOL Bitmode N A N A Both possible Bytemode is forced when Bytemode using preamble detection Preamble N A N A If PDET PEN 1 a configurable number of detection alternating 0 and 1 s PDET PLEN followed by a one byte start of frame delimiter as defined in BSYNC is needed to trigger reception Bytemode is forced when PDET 7 Table 29 Properties of different data modes MODEMO DATA FORMAT TEXAS INSTRUMENTS SWRS047 Page 92 of 152 Chipcon Products from Texas Instruments 0xDB Modem Control Register 0 2071010 R W Reset value Description 75 BAUDRATE 2 0 RW 011 000 0 6 kBaud 001 1 2 kBaud 010 2 4 kBaud 011 4 8 kBaud 100 9 6 kBaud 101 19 2 38 4 and 76 8 kBaud 110 Not used 111 Not used 4 3 DATA FORMAT 1 0 RW 10 00 NRZ mode 01 Manchester mode 10 Transparent mode 11 UART mode 2 0 XOSC FREQ 2 0 R W 001 Select the current crystal oscillator frequency 000 3 4 MHz 3 6864 MHz recommended Also used for 76 8 kBaud for 14 7456 MHz and 38 4 kBaud for 7 3728 MHz 001 6 8 MHz 7 3728 MHz recommended Also used for 38 4 kBaud for 14 7456 MHz 010 9 12 MHz 11 0592 MHz recommended Also used for 38 4 kBaud for 22 1184
43. REFDIV to create the RF reference frequency frer Valid REFDIV settings are 2 through 24 as described above 2 ALARM RW 0 Disable Enable the generation of the ALARM_H and DISABLE ALARM_L bits 0 Alarm function enabled 1 Alarm function disabled 1 ALARM_H R None Status bit for tuning voltage out of range too close to VDD The PLL should be re calibrated if this bit is set 0 ALARM L R None Status bit for tuning voltage out of range too close to GND The PLL should be re calibrated if this bit is set SWRS047 Page 109 of 152 TEXAS INSTRUMENTS Chipcon Products from Texas Instruments 17 13 Lock Indication The frequency synthesis PLL has a lock indicator which can be read from the LOCK register LOCK INSTANT is a single sample of the phase difference between the reference frequency and the divided VCO frequency This bit gives a lock accuracy of gt 25 96 depending on the division ratio set by the FREQ registers To be used as a lock indicator this bit must be sampled over a period of time to increase the accuracy LOCK 0xE4 PLL Lock Register 2071010 Otherwise LOCK_CONTINUOUS should be used It is filtered version of LOCK_INSTANT giving a lock accuracy of 99 3 with PLL LOCK ACCURACY cleared If lock is not achieved the PLL should be recalibrated as described on page 113 Name R W Reset value Description RO 0 Reserved read as 0
44. SPE The 661010 ports deviate from the These alternate functions may or may not standard 8051 port in the following ways override the direction setting from PxDIR e No pull ups pull downs on pins as shown When reading the Px registers data is E ee recon ipite ih read from the directly from the pin When 9 using read modify write instruction such CMOS output levels on all ports me All VO pi ted t ANL 0 01 the output register Wu EED MA lud a m pos value is read and modified regardless of ads B 4 Pt pi din RIS which is rated to sink or source 8 mA the setting in PXDIR SWRS047 Page 47 of 152 SWRS047 Page 48 of 152 TEXAS TEXAS INSTRUMENTS INSTRUMENTS Chipcon Products C from Texas Instruments Alternate function enable 61010 Alternate function static direction or PxDIR y PxDIRy Alternate data Read output register enable 5 Chipcon Products 2 from Texas Instruments P2 0xA0 Port 2 Data Register 2071010 Bit Reset value Description P2_7 RW 1 Data of port 2 bits 0 to 7 6 P26 RW 1 5 P2 5 RW 1 4 p24 RW 1 3 P23 RW 1 2 P2 2 RW 1 1 P2 1 RW 1 r20 RW 1 P3 0xB0 Port 3 Data Register Bit RW Reset value Description 7 RO
45. The Flash Debug Interrupt if enabled always has the highest priority and is the only interrupt that can have the highest priority All other interrupts can be assigned either low or high priority set by the registers IP and EIP listed below IP 0xB8 Interrupt Priority Register 2071010 Two interrupts with the same interrupt priority that occur simultaneously are resolved through their natural priority The natural priority is shown in Table 13 The interrupt having the lowest natural priority will be serviced first Once an interrupt is being serviced only an interrupt of higher priority level can interrupt the service routine of the interrupt currently being serviced Bit Name Reset value Description T R1 1 Reserved read as 1 6 51 RW 0 Serial Port 1 interrupt priority control Interrupt has low priority 1 Interrupt has high priority Reserved for future use 4 PSO RW 0 Serial Port 0 interrupt priority control 0 Interrupt has low priority 1 Interrupt has high priority 3 PTl RW o Timer 1 interrupt priority control 0 Interrupt has low priority 1 Interrupt has high priority 2 PX1 RW 0 External Interrupt 1 from P3 3 interrupt priority control 0 Interrupt has low priority 1 Interrupt has high priority 1 PTO RW 0 Timer 0 interrupt priority control 0 Interrupt has low priority 1 Interrupt has high priority 0 RW o
46. accordance with EIA Specification 481 Tape and Reel Specification Package Tape Width Component Hole Reel Units per Reel Pitch Pitch Diameter TQFP 64 24 mm 16 mm 4mm 13 1500 SWRS047 Page 139 of 152 TEXAS INSTRUMENTS Chipcon Products 2 from Texas Instruments 27 List of Abbreviations ADC Analog to Digital Converter AMR Automatic Meter Reading Cipher Feedback Mode CMOS Complementary Metal Oxide Semiconductor e Central Processor Unit DES Data Encryption Standard e DMA Direct Memory Access FCC Federal Communication Committee FSK Frequency Shift Keying IDE Integrated Development Environment e IF Intermediate Frequency e ISM Industrial Scientific Medical e ISR Interrupt Service Routine e LNA Low Noise Amplifier LO Local Oscillator e LPF Loop Filter e LSB Least Significant Bit or Byte Minimum Order Quantity Most Significant Bit or Byte e NRZ Non Return to Zero 01010 e OFB Output Feedback Mode e Printed Circuit Board e PLL Phase Locked Loop POR Power On Reset e Pulse Width Modulation e Random Access Memory e RF Radio Frequency RSSI Received Signal Strength Indicator e RTC Real Time Clock RX Receive e SFR Special Function Register e Serial Peripheral Interface SRAM
47. bits 1 start bit 8 data bits a programmable 9th bit and 1 stop bit The data bits are transmitted and received LSB first The mode 2 baud rate is either fsystem 32 or fsystem 64 set by PCON SMODO EICON SMOD1 The baud rate is then SMODx Baud Rate To transmit data in mode 1 write data to SBUFO SBUF1 Transmission is then performed on pin TXDO TXD1 in the following order start bit 8 data bits LSB first 9th bit from TB8 0 TB8 1 and then the stop bit The transmit interrupt flag TI 0 TI 1 is set when the stop bit is placed on the transmit pin Reception must be enabled by setting REN 0 REN 1 It is then initiated by the falling edge of a start bit received on RXDO 1 RXD1 The input pin is sampled 16 times per baud Majority decision is made as with mode 1 When the majority decision is made for the stop bit the following conditions must be met e RI_0 RI_1isO f SM2 0 SM2 1 is set the 9th bit and the stop bit must be one TEXAS INSTRUMENTS 01010 If these conditions are met the received data is buffered in SBUFO SBUF1 the received stop bit is stored in RB8 8 1 and the receive interrupt flag RI 0 RI 1is set If not the received data is lost and RB8 and the receive interrupt flag remains unchanged 16 7 4 MODE 3 Mode 3 provides asynchronous full duplex communication using a total of 11 bits as with mode 2 1 start bit 8 data bits a programmable 9
48. by SJMP and conditional jumps e bit Direct bit address e data 8 bit constant e data 16 16 bit constant e addr 16 16 bit destination address e addr 11 11 bit destination address used by ACALL and AJMP The branch will be within the same 2 kB block of program memory of the first byte of the following instruction The Bytes column shows the number of bytes of Flash memory used Further the number of instruction cycles is shown Each instruction cycle requires four clock cycles The 4 rightmost columns shows which flags in the program status word PSW see page 23 are affected by the instructions Mnemonic Description 28 TEE 2212 Arithmetic ADD A Rn Add register to A 1 1 28 2 x x x x ADD A direct Add direct byte to A 2 2 25 x x x x ADD A Ri Add data memory to A 1 1 26 27 x x x x ADD A data Add immediate to A 2 24 x x x ADDC A Rn Add register to A with carry 1 1 38 3F x x x x ADDC A direct Add direct byte to A with carry 2 2 35 x x x x ADDC A Ri Add data memory to A with carry 1 1 36 37 x x x x ADDC A data Add immediate to A with carry 2 34 x x x x SUBB A Rn Subtract register from A with A 1 98 9F x x x x borrow SUBB A direct Subtract direct byte from A with 2 2 95 x x x x borrow SWRS047 Page 24 of 152 TEXAS INSTRUMENTS Chipcon Products from Texas Instruments
49. configurations are used For best performance the frequency separation should be as high as possible especially at high data rates Figure 31 and Figure 32 show typical figures for how sensitivity varies as a function of the frequency offset between the transmitter and the receiver Data rate Separation 433 MHz 868 MHz kBaud kHz NRZ Manchester NRZ Manchester mode mode mode mode 0 6 64 109 108 106 106 12 64 107 106 104 104 24 64 105 105 101 103 48 64 104 103 98 100 9 6 64 102 101 96 98 19 2 64 100 99 96 96 38 4 64 97 98 94 94 76 8 64 96 96 93 93 Table 33 Typical receiver sensitivity as a function of data rate at 433 and 868 MHz BER 10 3 frequency separation 64 kHz Datarate Separation 433 MHz 868 MHz kBaud kHz NRZ Manchester NRZ Manchester mode mode mode mode 0 6 20 105 105 100 102 12 20 104 103 99 101 24 20 101 101 97 99 48 20 98 100 96 98 9 6 20 98 99 94 96 192 20 97 98 94 94 38 4 20 N R N R N R N R 76 8 20 N R N R N R N R Table 34 Typical receiver sensitivity as a function of data rate at 433 and 868 MHz BER 10 3 frequency separation 20 kHz N R Not recommended data rate too high compared to frequency separation TEXAS INSTRUMENTS SWRS047 Page 105 of 152 Chipcon Products
50. examples are shown in Figure 29 that the Manchester baud rate is twice the NRZ baud rate in the figure The preamble must consist of an alternating 0 1 pattern followed by a synchronization byte of eight bits Unless the average filter is already locked at the arrival of the synchronization byte in NRZ mode it is vital that the synchronization byte is DC balanced equal number of zeros and ones and contains no more than two consecutive ones or zeros It is also required that the synchronization byte contains two consecutive ones or zeros This means that e g OxCC is not a legal synchronization byte but is NRZ Bit value OPO AP OPO Manchester Bit value TiO TO OF Of oO 1 Of oO 1 0 gt lt gt lt Preamble Byte sync Data Figure 29 Preamble detection examples PDET 0xD3 Preamble Detection Control Register Name R W Reset value Desc ription 7 PEN RW 10 1 Preamble and byte synchronisation is enabled Preamble and byte synchronisation enable 0 Receiver mode is defined by RFCON BYTEMODE RFCON BYTEMODE is don t care 6 0 PLEN R W 0x00 Preamble length Define the number of alternating bits required before byte synchronisation PLEN must be greater than zero
51. frequency fxosc 16 10 SCK clock frequency fxosc 32 11 SCK clock frequency fxosc 64 SPDR 0xA2 SPI Data Register Bit Name R W Reset value Description 7 0 SPDR 7 0 R W 0x00 SPI Data Register Writing to SPDR when SPCR SPE is set will initiate a data transmission Reading SPDR will read the data input buffer which is only updated after each completed transmission SPSR 0xA3 SPI Status Register Bit Name RW Reset value Description T2 RO 0x00 Reserved read as 0 1 SPA R 0 SPI Active status bit 0 The SPI interface is currently not transmitting data 1 The SPI interface is currently transmitting data 0 wcoL R 0 Write collision flag This flag is updated by hardware when SPDR is written 0 The previous write to SPDR did not generate a data collision 1 The previous write to SPDR generated a data collision Writing data to SPDR when SPCR SPE is are transmitted and received with the data set will initiate a data transmission 8 bits order clock polarity clock phase and data m SWRS047 Page 71 of 152 SWRS047 Page 72 of 152 TEXAS 5 TEXAS INSTRUMENTS INSTRUMENTS Chipcon Products from Texas Instruments rate as set by SPCR DORD SPCR CPOL SPCR CPHA and SPCR SPR Reading data from SPDR will read the input buffer which is only updated after each complete transmission This means that a new byte can be written to SPDR
52. from Texas Instruments 2071010 CHVER 0x9F Chip Version Revision Register e SFRs hardware registers Bit Name R W Reset value Description normally only be addressed directly baw o t hoc onthe 7 2 CHIP TYPE R 0x00 CHIP TYPE is a read only status word which i e by hardwiring the specific address Uu da of 621010 gives the type number of the chip into the corresponding MOV p n 000000 221070 instruction This would make code in Great caution should be used when the 000001 111111 Reserved for future use ___ a debug monitor which returns the RADR is written Since the address 1 0 CHIP_REV R 0x01 CHIP REVisa read only status word which gives value of SFRs to a PC rather bloated consists of two bytes RADRL and he oP number ofthe Currentenp Using the instruction replacement there will be a short interval where the mechanism on the operand byte of the address is not valid as only one of the move instruction instead of the opcode bytes are written at a time If this byte allows indirect addressing of intermediate address point to the very SFRs same location as of the code modifying the Chipcon provides software for in circuit Mei a Canon vill ran One debugging which may be downloaded P DRH ion ae hi 2 irst ene from
53. in the 227070 IDE User Manual Chipcon also supplies a wide range of examples for the 667010 These examples TEXAS INSTRUMENTS 61010 include simple examples which show off the various features of the 207070 as well as examples showing RF communication and more sophisticated application related examples Source code as well as pre compiled HEX files are available for all examples A ZIP file including all examples and documentation is available from the Chipcon web pages Make sure to check the web pages regularly as improvements to existing examples as well as all new examples are added as they are available 19 8 Development tools Chipcon supplies a full featured development kit for the 22 010 that includes everything you need to start and finish your design The development kit is documented in the CC1010DK User Manual The development kit includes evaluation version of the Keil C compiler this is limited to a code size of 2 kBytes If the user wishes to compile larger programs a full version of the compiler must be purchased from Keil The Keil development environment supports in circuit debugging using the second serial port The 201010 is supported by several compiler vendors More information about compiler support can be found on Chipcon s web pages 19 9 PA splattering In systems where the PA is turned on and off rapidly for example in a system that switches rapidly between RX and TX so
54. performance of a standard 8051 Dual data pointers Idle and sleep modes e In circuit interactive debugging is supported for the Keil Vision IDE through a simple serial interface Data and Non volatile Program Memory 32 kB of non volatile Flash memory in system programmable through a simple SPI interface or by the 8051 core e Typical Flash memory endurance 20 000 write erase cycles 39 thas INSTRUMENTS 2071010 e Programmable read and write lock of portions of Flash memory for software security 2048 128 Byte of internal SRAM Hardware DES Encryption Decryption e DES supported in hardware Output Feedback Mode or Cipher Feedback Mode DES to avoid the requirement that data length must be a multiple of eight bytes Peripheral Features Power On Reset Brown Out Detection Three channel max 23 kSample s 10 bit ADC e Programmable watchdog timer e Real time clock with 32 kHz crystal oscillator Two timers pulse counters and two timers pulse width modulators Two programmable serial UARTs Master SPI interface 26 configurable general purpose l O pins e Random bit generator in hardware Low Power 8051 core and peripherals can use the RTC s 32 kHz clock e Idle and sleep modes for reduced power consumption System can wake up on interrupt or when ADC input exceeds a set threshold Low power fully static CMOS design Operating Conditions 2
55. pin 1 1 RW 0 Timer Counter 0 mode select bits 0 M0 0 RW 0 00 13 bit counter 01 16 bit counter 10 8 bit counter with auto reload 11 Two 8 bit counters Chipcon Products C from Texas Instruments 2071010 TCON 0x88 Timer Counter 0 and 1 control register Bit Name R W Reset value Description 7 RW 0 Timer 1 overflow flag TF1 is setto 1 by hardware when the Timer 1 count overflows and is cleared by hardware when the 8051 vectors to the interrupt service routine Timer 1 run control bit 0 Timer Counter 1 is disabled imer Counter 1 is enabled Timer 0 overflow flag TFO is setto 1 by hardware when the Timer 0 count overflows and is cleared by hardware when the 8051 vectors to the interrupt service routine Timer 0 run control bit 0 Timer Counter 0 is disabled 1 Timer Counter 0 is enabled 3 R WO 0 External interrupt 1 edge detect interrupt flag If external interrupt 1 is configured to be edge sensitive 171 1 IE1 is set by hardware when a negative edge is detected on the INT1 pin and is cleared by hardware when the 8051 vectors to the corresponding interrupt service routine In edge sensitive mode IE1 can also be set by software If external interrupt 1 is configured to be level sensitive TCON 171 0 IE1 is set when the INT1 pin is low and cleared when the INT1 is high In leve
56. som 7 RO 0 Reserved read as 0 mm 6 RO 0 Reserved read as 0 3iornd 5 RO 0 Reserved read as 0 4 TIM RW 0 Timer 1 clock select T1M has no effect in counter mode 0 Timer 1 uses uC clock divided by 12 for compatibility with the 80C32 1 Timer 1 uses the uC clock divided by 4 3 TOM RW 0 Timer 0 clock select TOM has no effect in counter mode 0 Timer 0 uses the uC clock divided by 12 for compatibility with the 80C32 1 Timer 0 uses the uC clock divided by 4 20 2 0 RW 007 MD 2 0 controls the memory stretch cycles when accessing the external RAM The reset value is 001 but for faster access to external RAM MD 2 0 should always be written 000 16 22 Mode 0 Mode 0 operation is illustrated for timer or counter 0 and 1 in Figure 8 The timer counter uses bit 0 to 4 of TLO TL1 and all 8 bits of THO TH1 as a 13 bit counter TCON TRO TCON TR1 must be set to enable the Timer Counter The bit in selects the Timer or Counter clock source as described Transitions are counted from the selected source as long as TMOD GATEO TMOD GATE1 is 0 or TMOD GATEO TMOD GATE1 is 1 and the corresponding interrupt pin INTO INT1 is When the 13 bit count increments from Ox1FFF all ones the counter rolls over to all zeros The overflow flag TCON TFO TCON TF1 is then set The 3 most significant bits in TLO TL1 are undetermi
57. these products with program code do so at their own risk and agree to fully indemnify Chipcon AS for any damages resulting from the use or sale of such products Chipcon believes that the Flash memory protection used in this product is one of the most secure in the market today when used in the intended manner and under normal conditions However there might be methods to breach the code protection feature Neither Chipcon nor any other semiconductor manufacturer can guarantee the security of their code protection Code protection does not mean that we are guaranteeing the product as unbreakable This Chipcon product contains hardware DES encryption Chipcon does not guarantee the security of the key protection or the security of the encryption scheme Chipcon customers using or selling products with DES do so at their own risk and agree to fully indemnify Chipcon AS for any damages resulting from the use or sale of such products 31 4 Trademarks SmartRF is a registered trademark of Chipcon AS SmartRF is Chipcon s RF technology platform with RF library cells modules and design expertise Based on SmartRF technology Chipcon develops standard component RF circuits as well as full custom ASICs based on customer requirements and this technology All other trademarks registered trademarks and product names are the sole property of their respective owners 31 5 Life Support Policy This Chipcon product is not designed for use in life su
58. to generate different baud rates Serial port 1 is primarily for use with an in circuit debugger but can also be used for general purpose serial communication A block diagram is shown in Figure 16 The ports that map to the same physical pins as the serial ports 2071010 must be configured in a certain way in order to allow serial communication This is summarized in Table 22 The mode is set in SCONO SMx 0 SCON1 SMx 0 To receive data SCONO REN 0 SCONI REN 1 must be enabled for the ports Separate transmit and receive interrupt flags are available in SCONO TI 0 RI 0 and SCON1 TI 1 RI 1 Note that the baud rate also depends on the Clock Mode selected see page 35 Data Bus RTCON 0xED Real time Clock Control Register Bit Name R W Reset value Description T RTEN RW 0 Real time Clock Enable Disable Write SBUF Read SBUF 0 Real time Clock is disabled 1 Real time Clock is enabled 6 0 RT 6 0 R W 0x00 Real time Clock interrupt interval control RT 6 0 gives TXDO TXD1 4 Rm eh the desired interrupt interval in seconds RT 6 0 must be between 1 and 127 ML Mode 0 Load SBUF Transmit XOSC32 01 i XOSC32 Q2 1 1 gt Receive E 2276 di d RXDO RXD1 Shift Register cis 9 gt went Request RLO RI 1 TLOITI 1 Figure 15 RTC oscillator circuit SCONO SCON1 Figure 16 Serial ports block diag
59. to operating frequency RX TX mode and output power The receiver sensitivity will also affected by the current settings Recommended settings for the CURRENT VCO CURRENT bits are shown in the CURRENT register table following below 2071010 The bias current for the LNA and the LO and PA buffers are also programmable through FREND LNA CURRENT FREND BUF CURRENT CURRENT LO DRIVE and CURRENT PA DRIVE CURRENT 0 1 RF Current Control Register Bit Name R W Reset value Description 7 4 VCO CURRENT R W 1100 3 0 Control of current in VCO core for TX and RX 0000 0001 0010 0011 450 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 1504A 250A 350A 950pA use for RX f lt 500 MHz 1050 1A 11501 use for RX f gt 500 MHz 1250 1450pA use for TX f lt 500 MHz 1550 pA 1650pA 1750pA 22504A 23504A 2450 2550 use for TX f gt 500 MHz 32 LO_DRIVE RW 10 170 Control of current in VCO buffer for LO drive 00 0 5mA use for TX 01 1 0mA use for RX when f lt 500 MHz 10 1 5mA 11 2 0mA use for RX 500 MHz 10 PA DRIVE RW 10 1 0 Control of current in VCO buffer for PA 00 1mA use for RX 01 2mA use for TX 500 MHz 10 3mA 11 4mA use for TX f 500 MHz TEXAS INSTRUMENTS SWRS047 Page 118 of 152 Chipcon Products from Texas Instruments FREND 0xEE Front
60. value Description 7 0 FREQ A 7 0 R W 0xCB 8 LSB of frequency control word A FREQ 2B 0xCF Frequency B Control Reg ister 2 Bit Name R W Reset value Description 7 0 FREQ B 23 16 R W 0x75 8 MSB of frequency control word B It must be programmed such that FREQ_2B gt 01000000 FREQ 1B 0xCE Frequency B Control Regi ister 1 Bit Name R W Reset value Description 70 FREQ B 15 8 RW 0x45 Bit 15 to 8 of frequency control word B TEXAS INSTRUMENTS SWRS047 Page 108 of 152 Chipcon Products from Texas Instruments 2071010 FREQ 0B 0xCD Frequency B Control Register 0 Bit Name R W Reset value Description 70 FREQ B 7 0 RW OdE 8 LSB of frequency control word B FSEP1 0xEB Frequency Separation Control Register 1 Bit Name R W Reset value Description T3 RO 0 Reserved read as 0 2 0 FsEP 10 8 RW 0x00 of the frequency separation control word FSEP FSEPO 0xEA Frequency Separation Control Register 0 Bit Name Reset value Description 7 0 FSEP 7 0 R W 0x59 8 LSB of the frequency separation control word FSEP PLL 0xE3 PLL Control Register Bit Name R W Reset value Description 7 3 REFDIV 4 0 R W 0x02 Reference divider setting The main crystal oscillator frequency is divided by
61. value Description 7 R1 1 Reserved read as 1 6 R1 1 Reserved read as 1 5 R1 1 Reserved read as 1 4 RTCIE RW 0 Realtime Clock interrupt enable disable 0 Interrupt is disabled 1 Interrupt is enabled when also EA is set 3 ET3 RW 0 Timer 3 interrupt enable disable 0 Interrupt is disabled 1 Interrupt is enabled when also EA is set 2 ADIE RW 0 ADC DES interrupt enable disable 0 Interrupt is disabled 1 Interrupt is enabled when also EA is set 1 ET2 RW 0 Timer 2 interrupt enable disable 0 Interrupt is disabled 1 Interrupt is enabled when also EA is set 0 RFIE RW 0 RF Interrupt enable disable 0 Interrupt is disabled 1 Interrupt is enabled when also EA is set SWRS047 Page 29 of 152 TEXAS INSTRUMENTS 4 RFIF 0 RF Transmit receive interrupt flag RFIF is set by hardware when an interrupt request is generated from the RF transceiver block RFIF may also be set by software RFIF must be cleared by software before exiting the ISR Reserved read as 1 RO Reserved read as 0 n o DE Az ojojoj Reserved read as 0 Reserved read as 0 TEXAS INSTRUMENTS SWRS047 Page 30 of 152 Chipcon Products from Texas Instruments 15 6 3 Interrupt Priority Interrupts are prioritised in two stages Interrupt level and natural priority The interrupt level low high or highest takes precedence over the natural priority
62. value that sets the PWM period T2 0xAC Timer 2 Low byte counter value Bit Name R W Reset value Description 7 0 T2 7 0 R W 0x00 In Timer Mode T2 sets the 8 least significant bits of the 16 bit counter reload value In PWM Mode T2 sets the PWM duty cycle T3 0xAD Timer 3 Low byte counter value Bit Name RIW Reset value Description 7 0 T3 7 0 RIW 0x00 In Timer Mode T3 sets the 8 least significant bits of the 16 bit counter reload value In PWM Mode T3 sets the PWM duty cycle 16 3 2 PWM Mode Timer 2 Timer 3 can be set in PWM Mode by setting the bit TCON2 M2 TCON2 M3 The pins P3 4 P3 5 are then enabled as outputs overriding the port direction bit P3DIR 4 P3DIR 5 The port direction is overridden independent of the timer run control bit TCON2 TR2 TCON2 TR3 Interrupts are not generated in PWM mode TEXAS INSTRUMENTS P3 4 is the PWM output for timer 2 P3 5 is the PWM output for Timer 3 The PWM operation is illustrated in Figure 13 The PWM period for timer n is set by TnPRE 255 TnPRE 1 lamt oo osten SWRSO047 Page 60 of 152 Chipcon Products from Texas Instruments The PWM high state duration for 61010 This means that in PWM mode setting Tn timer n is set by Tn to 0 produces a constant low output and 1 setting Tn to 255 produces a constant high Tn TnPRE 1 output The timi
63. vias For 868 and 915 MHz operation some of the AVDD supply pins should be fitted with ferrite beads in 19 11 Antenna Considerations 1010 can be used together with various types of antennas The most common antennas for short range devices are monopole helical and loop antennas Monopole antennas are resonant antennas with a length corresponding to one quarter of the electrical wavelength 4 They are very easy to design and can be implemented simply as a piece of wire or even integrated into the PCB Non resonant monopole antennas shorter than 2 4 can also be used but at the expense of range In size and cost critical applications such an antenna may very well be integrated into the PCB Helical antennas can be thought of as a combination of a monopole and a loop antenna They are a good compromise in size critical applications But helical TEXAS INSTRUMENTS 2071010 series to prevent noise from coupling from one supply pin to another Please see the reference layouts for more information For 433 and 315 MHz operation these beads are not required and can be replaced with 0 ohm resistors or PCB traces The external components should be as small as possible and surface mount devices are required The VCO inductor must be placed as close as possible to the chip and symmetrical with respect to the input pins It is important to keep the coupling between the VCO inductor and the matching network low i
64. 0 each bit or byte to be transmitted EXIF RFIF The internal T R switch circuitry makes the antenna interface and matching very easy using a few passive components The frequency synthesiser generates the local oscillator signal which is fed to the MIXER in receive mode and to the PA in transmit mode The frequency synthesiser consists of a crystal oscillator XOSC phase detector PD charge pump CHARGE PUMP internal loop filter LPF VCO and frequency dividers R and N An external crystal must be connected to the XOSC Only one external inductor is required for the VCO A detailed pin description is given at page 15 SWRS047 Page 84 of 152 Chipcon Products from Texas Instruments 17 3 RF Application Circuit Very few external components are required for operation of the RF transceiver A typical application circuit is shown in Figure 20 Component values are shown in Table 28 17 3 1 Input output matching C31 L32 is the input match for the receiver and L32 is also used as a DC choke for biasing C41 L41 and C42 are used to match the transmitter to a 50 Ohm load An internal T R switch circuit makes it possible to connect the input and output together and match the transceiver to 50 Q in both RX and TX mode See the Input Output Matching section on page 126 for details 17 3 2 inductor The VCO is completely integrated except for the inductor L101 Component values for the ma
65. 0 0 9INIdHO L 9INIdHO Z 9INIdHO 9INIdHO S 9INIdHO 9 9INIdHO L OINIdHO 9INIdHO Sseuppe Aq papos 45 Lp alge 82 00000000 O GINIdSO V GINIdHO Z GINIdHO SINIdMO V S SINIdNO 9 GINIdNO L SINIdHO SINIdNO QgX0 82 00000000 OPINED L vINIdHO Z vINIdHO VINIdNO T vINIdHO S VINIdNO 9 rINIdHO L VINIdNO VINIdHO Sy 00000000 OMQvH LAYA zv HOVH AVY suave guava Hyv Exo v 00001000 009 LOD dHO 209 09 vOO __ 4 1144001 MW3lilddOO 91531 34 0 Sy 00000000 SHOVH ELAVA Tuave vaxo 00010000 00 LOV ZOV OV _ sisal 3 0 sv 00000000 Ov1vaH 1vivau zvlvaH E VIVOH 9vivau Iv1VOH vivdu SiL 10100100 veal V 0ODIZ1 200101 2700101 7001921 900121 1531 Q3x0 te 00000001 Old Xd 0Sd di ZN3dO N3dO 82 00000000 O EINIdO V EINIdHO Z EINIdMO S EINIdNO FEINI JYI LEINIdNO 28 0 SiL 00100000 qvo vo Wo Wo _ 3001 vaya 6158 04 0 82 00000000 V ZINIdHO Z ZlNIdHO ZINIdNO S ZINIdHO 9 ZINIdHO ZZINIGHD ZiNIdHO 98X0 St 00x00 dHO
66. 0 Reserved read as 0 6 RO 0 Reserved read as 0 5 5 RW 1 Data of port 3 bits 0 to 5 P34 RW 1 3 P33 RW 1 2 P3 2 RW 1 1 P31 RW 1 2 RW 1 PODIR 0xA4 Port 0 Direction Register Bit Name R W Reset value Description F RO 0 Reserved read as 0 6 S RO 0 Reserved read as 0 5 RO Reserved read as 0 4 RO 0 Reserved read as 0 3 PODIR 3 1 Port 0 direction register bit O to 3 Each bit sets the 2 PODIR 2 1 direction of the associated pin on Port 0 1 PODIR 1 RW 1 0 Associated pin is an output 0 PODIR 0 RW 1 1 Associated pin is an input P1DIR 0xA5 Port 1 Direction Register XN Px y PAD Internal Data Bus D Output register Read Pin Enable N Figure 7 Port x bit y structure PO 0x80 Port 0 Data Register Bit Name RW Reset value Description 7 at RO 0 Reserved read as 0 6 RO 0 Reserved read as 0 5 RO 0 Reserved read as 0 4 RO 0 Reserved read as 0 3 PO 3 RW 1 Data of port 0 bits 0 to 3 2 P02 RW 1 1 Poi RW 1 0 PO 0 RW 4 1 0x90 Port 1 Data Register Bit RW Reset value Description 7 17 RW 1 Data of port 1 bits O to 7 6 P16 RW 5 P15 RW 4 Pl 4 RW 1 3 RW 1 2 P12 RW 1 1 Pl 1 RW 1 gt 10 RW 1 SWRS047 Page 49 of 152 TEXAS INSTRUMENTS Bit Name R W R
67. 070 is very suitable for frequency hopping systems Hop rates of 10 1000 hops s are usually used depending on the bit rate and the amount of data to be sent during each transmission The two frequency registers FREQ A and FREQ are designed such that the next frequency can be programmed while the present frequency is used The switching between the two frequencies is done through the control bit Frequency hopping improves the reliability and increases the security of a wireless link The US ISM band at 902 928 MHz is very suitable for frequency hopping protocols The FCC regulations allow the use of transmitted output powers to 1W if frequency hopping is used and certain requirements are met Please see application note SRD regulations for licence free transceiver operation for more information about this and other radio regulations issues 19 7 Software Chipcon provides world class software support for the 227070 The HAL Hardware Abstraction Library library provides easy to use functions and macros to access the 601010 hardware without having to access SFRs directly It also provides functions simple RF communications routines The CUL Chipcon Utility Library library contains more sophisticated RF communication routines with support for CRC checking automatic acknowledgment and retransmission Both libraries are supplied with full source code and are documented
68. 10 Port Available Alternate Function 16 8051 Peripherals pins Normal operation Flash Programming 0 SCK SPI Serial Clock output SCK SPI Serial Clock Input 61010 offers the following peripherals e Real time clock P0 1 MO SPI Master Output SI SPI Slave Input units controlled by the 8051 compatible e SPI master P0 2 MI SPI Master Input SO SPI Slave Output core P0 3 n e Four general purpose I O ports with e Hardware DES encryption decryption ae 26 I O pins in total e Random bit generator 1 2 e Two standard 8051 timers e 10 bit ADC P1 3 e Two timers with PWM functionality These modules are described in the ri E Watchdog timer following sections Pl 6 2 P1 7 16 1 General Purpose I O P2 0 RXD1 Serial port 1 input 5 7 P2 1 TXD1 Serial port 1 output Four general purpose l O ports are Writing to the Px registers writes to the P2 2 n available PO P1 P2 and P3 Table 20 output register and sets the I O pin state P2 3 z shows each port and the pins on each Using a read modify write operation reads P2 P2 4 x port from the output register modifies the value P2 5 P according to the instruction executed and P2 6 Each port is associated with two registers writes the result back into the output The port register PO P1 P2 or P3 and register modifying the l O pin state LEER d the direction register PODIR P1DIR aceordinal P3 0 RXDO Serial port 0 input P
69. 27 of 152 IE EA is the global interrupt enable for all interrupts except the Flash Debug interrupt When IE EA is set each interrupt is masked by the interrupt enable bits listed in Table 13 When IE EA is cleared all interrupts are masked except the Flash Debug interrupt which has its own interrupt mask bit FDIE 15 6 2 Interrupt Processing When an enabled interrupt occurs the CPU jumps to the address of the interrupt service routine ISR associated with that interrupt as shown in Table 13 Most interrupts can also be initiated by setting the associated interrupt flag from software Dr XAS RUMENTS interrupt level occurs Each ISR ends with a RETI return from interrupt instruction After executing the RETI 607010 returns to the next instruction that would have been executed if the interrupt had not occurred 221010 always completes the instruction in progress before servicing an interrupt If the instruction in progress is RETI or a write access to any of the IP IE EIP or EIE SFRs 007010 completes additional instruction before servicing the interrupt SWRS047 Page 28 of 152 Chipcon Products from Texas Instruments IE 0xA8 Interrupt Enable Register 2071010 Chipcon Products C from Texas Instruments EICON 0xD8 Extended Interrupt Control 2071010 Bit Name RW Reset value Description Bit Name Reset value De
70. 28 6 4194304 400000 11 0592 9 4194304 400000 14 7456 12 4194304 400000 18 4320 15 4194304 400000 22 1184 18 4194304 400000 433 3 433 302000 3 6864 Low side 3 5767168 580000 7 3728 6 5767168 580000 11 0592 9 5767168 580000 14 7456 12 5767168 580000 18 4320 15 5767168 580000 22 1184 18 5767168 580000 433 9 433 916400 3 6864 Low side 3 5775360 582000 7 3728 6 5775360 582000 11 0592 9 5775360 582000 14 7456 12 5775360 582000 18 4320 15 5775360 582000 22 1184 18 5775360 582000 434 5 434 530800 3 6864 Low side 3 5783552 584000 7 3728 6 5783552 584000 11 0592 9 5783552 584000 14 7456 12 5783552 584000 18 4320 15 5783552 584000 22 1184 18 5783552 584000 868 3 868 277200 3 6864 Low side 2 7708672 75A000 7 3728 4 7708672 75A000 11 0592 6 7708672 75A000 14 7456 8 7708672 75A000 18 4320 10 7708672 75A000 22 1184 12 7708672 75 000 868 95 868 938800 3 6864 high side 2 7716864 75C000 7 3728 4 7716864 75C000 11 0592 6 7716864 75C000 14 7456 8 7716864 75C000 18 4320 10 7716864 75C000 22 1184 12 7716864 75C000 SWRS047 Page 111 of 152 Note When using high side LO injection the data received in RFBUF will be inverted Table 35 Recommended settings for ISM frequencies TEXAS INSTRUMENTS SWRS047 Page 112 of 152 Chipcon Products from Texas Instruments 17 15 VCO Only one external inductor L101 is required for the VCO The inductor will determine the operating frequency range of the c
71. 2DIR P3DIR 9 P3 1 TXDO Serial port 0 output n In practice this means that the mov 3 2 INTO External interrupt 0 Each bit in the Px registers has its instruction should only be used when associated bit in the direction registers writing to all the pins in the port To modify P3 3 INT External interrupt 1 Setting PXDIR Y will make Px y only a few pins use a read modify write P3 4 TO Counter input 0 to Timer 0 or an input which can be read in Px All instruction Also be careful of using PWM2 PWM out z put from Timer 2 pins are inputs after reset Clearing constructs in C or another high level P3 5 TL Counter in 4 iput 1 to Timer 1 or PxDIR y Wil make the pin Px y output language that result in a mov from the Px PWM3 PWM out 1 j ta H put from Timer 3 the data from the register All Px registers modify the result and write it and PxDIR register descriptions are back without using read modify write Table 20 Available l O Ports shown from page 49 instructions as this will cause problems if The structure for a single I O bit y on port not all O pinsitn port are configured e shi in Fi 7 8 rts hi as outputs In amp and xs snownon TRG 1 SOMO Polls Nave operators should be used to set clear and alternate functions such as the SPI toggle pins respectively interface which are enabled through other registers such as SPCR
72. 3 PLL LOCK ACCURACY 0 0 Sets Lock Threshold 127 Reset Lock Threshold 111 for continuous lock Corresponds to a worst case accuracy of 99 3 1 Sets Lock Threshold 31 Reset Lock Threshold 15 for continuous lock Corresponds to a worst case accuracy of 97 2 2 PLL LOCK LENGTH RW 0 0 Normal PLL lock window 1 Not used 1 LOCK_INSTANT R None Status bit from Lock Detector The result of one sample of the lock window on the PLL reference clock 0 LOCK CONTINUOUS R None Status bit from Lock Detector set according to the LOCK ACCURACY setting TEXAS INSTRUMENTS SWRS047 Page 110 of 152 Chipcon Products from Texas Instruments 61010 17 14 Recommended Settings for ISM Frequencies The recommended frequency synthesiser settings for a few operating frequencies in the popular ISM bands are shown in Table 35 These settings ensure optimum configuration of the synthesiser in receive mode for best sensitivity For some settings of the synthesiser combinations of RF frequencies and reference frequency the receiver sensitivity is degraded The performance of the transmitter is not affected by the settings but recommended transmitter settings are included for completeness The FSK frequency separation is set to 64 kHz The SmartRF Studio software can be used to generate the optimised configuration data as well Also an application note ANO11 and a spreadshe
73. 4 5 5 38 4 NA 5 0 NA 5 1 NA 5 2 76 8 NA NA NA 5 0 NA NA Table 30 Baud rates versus crystal frequency SWRS047 Page 94 of 152 TEXAS INSTRUMENTS Chipcon Products from Texas Instruments 17 8 Transmitting and receiving data In the Transparent or UART modes outgoing and incoming data is routed directly to the modulator in transmit mode and directly from the demodulator in receive mode In the NRZ and Manchester 2071010 modes however data buffering occurs in RFBUF as illustrated in Figure 24 This buffering has some repercussions that must be considered when receiving or transmitting data particularly in bytemode 4 RF D RF Transmitter 8 bit shift reg Receiver Modulator 4 Demodulator 3 Figure 24 RF Data Buffering Dotted lines show bitmode RFBUF 0xC9 RF Data Buffer Bit Name R W Reset value Description 7 0 RFBUF 0x00 RF Data Buffer 8 bits RFBUF is used as described below 17 8 1 Transmission When transmitting data in bytemode RFCON BYTEMODE 1 the buffering scheme shifts out bits of an 8 bit shift register to the modulator one at a time MSB first at periods specified by the selected baud rate When this shift register is empty it will load a new byte from RFBUF and continue shifting out bits The contents of the RFBUF register remain unchanged after a shift register load An interrupt
74. 5 dBm external LC filter should be For matching details see 3 harmonic 433 868 MHz 27 29 used to reduce harmonics Input output matching p emission to comply with SRD 120 requirements See p 128 Turn on time 11 128 Baud The demodulator settling Table 7 RF transmit characteristics time which is programmable determines the turn on time See page 97 for details Table 8 RF receive characteristics SWRS047 Page 9 of 152 SWRS047 Page 10 of 152 TEXAS TEXAS INSTRUMENTS INSTRUMENTS Chipcon Products Chipcon Products from Texas Instruments 2010710 C from Texas Instruments 201010 10 IF section 11 Frequency synthesizer section Parameter Min Typ Max Unit Condition Parameter Min Typ Max Unit Condition Intermediate frequency IF 150 kHz Internal IF filter Crystal Oscillator Frequency 3 24 MHz Crystal frequency can be 3 4 433 868 MHz 130 6 8 or 9 24 MHz 10 7 MHz External IF filter Recommended frequencies are 3 6864 7 3728 11 0592 IF bandwidth noise bandwidth 175 kHz 14 7456 18 4320 and 22 1184 MHz See page 32 RSSI dynamic range 105 60 for details RSSI 3 dB bandwidth 260 kHz 868 MHz CW 70 dBm Crystal frequency accuracy 50 ppm 433 MHz RSSI accuracy See 126 for details requirement 25 868 MHz The crystal frequency RSSI linearity t2 dB accuracy and drift ageing and temperature oe dependency will determine Table 9 IF characteristics the frequency accuracy of the transmitted signal Crystal op
75. 5 or pulse width modulator CHP_OUT 13 136 P1 2 T1 1 3 s output or Timer Counter 1 external input R BIAS P4 1 30 P3 4 PWM2 O Digital high Z I O 8051 port 3 bit 4 or pulse width modulator TO I 2 s output or Timer Counter 0 external input AVDD 15 P0 1 MOSI 31 P3 3 INTI q Digital high Z 8051 port 3 bit 3 interrupt 1 input AGND 16 P0 0 SCK 0 configurable as level or edge sensitive 32 DGND 0 Ground connection digital part 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 P0 0 SCK 0 Digital high Z 8051 port 0 bit 0 or SPI master interface 2588589299 u 255223952 SCK I serial clock output or Flash programming 8 o o s mw g oo 5 n B Bon SPI slave clock input 2288 a 34 _ MO 0 Digital high Z 70 8051 port 0 bit 1 or SPI interface master xx Be 5 SI I output or Flash programming SPI slave x M serial data input 35 P1 1 Digital high Z 8051 port 1 bit 1 36 P1 2 Digital high Z 8051 port 1 bit 2 37 P1 3 Digital high Z 8051 port 1 bit 3 Pin Pinname Alternate Pin type Description 38 P14 Digital high Z 1 0 8051 port 1 bit 4 function 39 P22 P Digital high Z 1 0 8051 port 2 bit 2 1 AVDD Power A Power supply ADC Schmitt trigger 2 AVDD Power A Power supply Mixer and IF input 3 AGND Power A Ground connection Mixer and IF 40 DVDD Power D Digital power supply 4 RF IN RF input RF signal
76. 61010 Clearing PLL ALARM DISABLE will enable generation of the frequency alarm bits PLL ALARM H and PLL ALARM L These bits indicate that the frequency synthesis PLL is unable to generate the frequency requested and the PLL should be recalibrated as described in the VCO and PLL self calibration section on page 113 It is recommended that the LOCK_CONTINOUS bit in the LOCK register is checked when changing frequencies and when changing between RX and TX mode If lock is not achieved a calibration should be performed as described on page 113 Chipcon recommends using the frequency settings described in the Recommended Settings for ISM Frequencies section on page 111 Chipcon recommends the use of the SmartRF Studio software to calculate RF settings for the CC1010 Using the Print registers to file option in the File menu generates a text file with a C constant structure that can be passed to the RF configuration routines in the HAL library FREQ_2A 0xCC Frequency A Control Register 2 Bit Name R W Reset value Description 7 0 FREQ 23 16 R W 0x75 8 MSB of frequency control word A It must be programmed such that FREQ_2A gt 01000000 FREQ_1A 0xCB Frequency A Control Register 1 Bit Name R W Reset value Description 7 0 FREQ A 15 8 RW 0xA0 Bit 15 to 8 of frequency control word A FREQ 0A 0xCA Frequency A Control Register 0 Bit Name R W Reset
77. 68 nH 10 0805 12 nH 10 0805 12 nH 10 0805 Coilcraft 0805CS 680XKBC Collcraft 0805CS 120XKBC Coilcraft 0805CS 120XKBC 141 62 nH 10 0805 2 5 nH 10 0805 2 5 nH 10 0805 Coilcraft 0805HQ 6N2XKBC Collcraft 0805HQ 2N5XKBC Coilcraft o805HQ 2N5XKBC L101 27 nH 5 0805 3 3 nH 5 0805 3 3 nH 5 0805 Koa KL732ATE27NJ Koa KL732ATE3N3C Koa KL732ATE3N3C R131 82 1 0603 82 1 0603 82 1 0603 XTAL 14 7456 MHz crystal 14 7456 MHz crystal 14 7456 MHz crystal 16 pF load 16 pF load 16 pF load Table 28 Bill of materials for the application circuit Note Shaded items are different for different frequencies Note that the component values for 868 and 915 MHz can be the same However it is important that the layout is optimised for the selected VCO inductor in order to centre the tuning range around the operating frequency to account for inductor tolerance The VCO inductor must TEXAS INSTRUMENTS be placed very close and symmetrical with respect to the pins L1 and L2 Chipcon provides reference layouts that should be followed very closely in order to achieve the best performance The reference design can be downloaded from the Chipcon website SWRS047 Page 87 of 152 Chipcon Products from Texas Instruments 17 4 Transceiver Configuration Overview The RF transceiver configuration can be optimised to achieve the best performance for different applicati
78. AL CAL_START 0 End of calibration Calibration is performed in TX mode Result is stored in TESTO and TEST2 TX registers Figure 34 Single calibration algorithm for RX and TX TEXAS INSTRUMENTS SWRS047 Page 116 of 152 Chipcon Products from Texas Instruments Start dual calibratie Write FREQ A FREQ B Write CALCAL DUAL 1 2071010 Frequency registers A and B are both used for RX mode or both for TX mode Write REMAIN RXTX 0 F 0 RX PD 0 TX PD 1 FS PD 0 CORE PD 0 BIAS PD 0 Either frequency register A or B is selected v Write CURRENT VCO CURRENT RX current Write PLL REFDIV RX reference divider Write TEST6 0x1B RX current is the VCO current to be used in RX mode TEST6 0x3B if TX mode Write CAL CAL_START 1 Wait for maximum 26 ms or Read CAL and wait until CAL CAL_COMPLETE 1 v Write CAL CAL START 0 End of calibration Dual calibration is performed Result is stored in TESTO and TEST2 for both frequency A and B registers Calibration time depends on the reference frequency see text Figure 35 Dual calibration algorithm for RX mode TEXAS INSTRUMENTS SWRS047 Page 117 of 152 Chipcon Products gt from Texas Instruments 17 17 VCO LNA and buffer current control The VCO current is programmable and should be set according
79. Bit Name R W Reset value Description 7 0 FLADR 7 0 R W 0x00 The number of of the Flash page to be written 8 MSB of the byte address FLCON 0xAF Flash Write Control Register Bit_ Name R W Reset value Description 7 RO Reserved read as 0 6 5 FLASH_LP RW 00 Flash Low Power control bits 1 0 00 The Flash module is always active 01 The Flash module enters standby mode when the 8051 is put in Idle mode or Stop mode 10 The Flash module enters standby mode between instruction fetches and when the 8051 is put in Idle Mode or Stop Mode 11 Reserved for future use 4 WRFLASH RW 0 Write Flash Start bit Starting a Flash page programming is done by first setting this bit and then setting the 8051 in Idle Mode If the WRFLASH bit is cleared before Idle Mode is entered no programming is performed 3 0 RMADR 3 0 R W 0x0 RAM Buffer address RMADR 3 0 contains the 4 most significant bits of the RAM address where the data is buffered before writing to Flash FLTIM 0xDD Flash Write Timing Register Bit Name R W Reset value Description 7 0 FLTIM 7 0 R W 0x0A Flash Write Timing control FLTIM must be set as described in this section prior to using the 8051 Flash programming If an attempt is made to write data to a Flash page which is locked see the previous section a Flash Debug interrupt will be generated immediately
80. CO DO EO FO FF 14 0x03 21 9 0x05 24 8 PA_POW Hexadecimal 13 0x03 21 9 0x06 25 o Opi power a consumption 12 0x04 22 2 0x07 25 2 Sce ee en 11 0x04 22 2 0x08 25 4 10 0x05 22 4 0x09 25 7 Figure 39 Typical output power and total current consumption 433 MHz 9 0x05 22 4 Ox0A 25 9 8 0x06 22 7 0x0B 26 7 0x07 22 9 0x0C 26 2 40 0 6 0x08 23 2 0x0E 26 6 s 5 0x09 23 5 OxOF 26 8 a t E Ox0A 23 8 0x50 29 3 3 0x0B 24 0 0x60 29 9 E 2 0x0D 24 5 0x70 30 5 2 1 OxOE 249 0x80 31 0 gw 0 0x40 26 0 32 1 90 97 1 0x50 27 0 0xC0 33 1 H oo 2 0x60 28 0 OxEO 34 2 468 A 3 0x60 28 0 OxFO 34 7 4 0x70 28 9 OxFF 38 5 Hi un 5 0x80 30 0 6 0x90 31 0 lus 7 OxBO 33 2 i 8 OxCO 343 LM 9 OxEO 36 7 40 OxFF 428 don Note The current consumption is measured at for a 14 7456 MHz main oscillator frequency and is for the entire 227010 both MCU and RF transceiver If the crystal frequency is changed the current consumption for the MCU will change the relationship between crystal frequency and MCU current consumption is shown in Figure 1 Table 37 Output power settings and typical current consumption SWRS047 Page 123 of 152 4 TEXAS INSTRUMENTS 012345 67 8 9 AB C D E F 10 20 30 40 50 60 70 80 90 A0 B0 CO 00 EO FO FF PA POW Hexadecimal e Output power amp Current consumption Figure 40 Typical output power and total current consumptio
81. DCIE are set To always get an interrupt upon completion of a conversion ADTRH should be set to 0 The ADCON ADCRUN control bit is cleared by hardware when the conversion is finished In the multi conversion modes the ADC starts a new conversion every 11th ADC clock cycle All multi conversion modes can be stopped by clearing ADCON ADCRUN after which the ADC will abort its current conversion and then stop In all modes an action is taken when the 8 MSB of the latest sample value is greater than or equal to the value written in ADTRH these are Multi conversion continuous When the threshold comparison holds true value gt TEXAS INSTRUMENTS 61010 ADTRH 4 an interrupt is generated and the corresponding interrupt service routine is then executed if the interrupt enable flags EIE ADIE and ADCON2 ADCIE are set The ADC will continue its conversions regardless of the result of the threshold comparison To always get an interrupt upon completion of a conversion ADTRH should be set to 0 Multi conversion stopping When the threshold comparison holds true value gt ADTRH 4 an interrupt is generated and the corresponding interrupt service routine is then executed if the interrupt enable flags EIE ADIE and ADCON2 ADCIE set The ADC will stop when the threshold comparison holds true clearing ADCON ADCRUN Multi conversion reset generating When the threshold comparison holds true value gt ADTRH 4 a sys
82. EL VeL TEL EEL YEL S EL IEL Ll L OLLOLOO0 0 93dvHS4 L 93dvHs4 Z93dvHS4 93dvHS3 V93dvHS4 S 93dVHS3 9 93dVHS4 L 93dvHS4 93dvHSd 2 0 09 00000000 021 VEL faa 21 voL SZL 921 21 OVXo 00111000 0 3dvHS4 V 134vHS4 Z13dvHS3 3dVHS3 V 13dvHS4 S 3dVHS3 9 3dvHS4 3dVHSd 4 0 09 00000000 Z3HdEL 3HdEL S3HdEL ISHdEl 3udel avxo Ez 00000000 08 za 8 va sa 9a 09 00000000 03NdzL PENETAN Egad y3udzL 13 921 3udzl OEL 00000000 01951591 11951531 21351891 21351531 z _ a30 6S 00000000 2 ZAL N EUL d ZNOOL 00000000 ISSY WNYSLXa 31 VNI LINAYYNO WNT n9 3ng8 S a30 62 00000000 013 xa ua 0S3 2 va 3 8vxo 99 00000000 01M LLA Z1 ELY 91H NOO1H oulaed baled led eulded guided 8 O L 10000000 N 13S3H 54 3dvus OH3HLIG uar Da 741953 93 0 vs oulded baled lazda ul zd pulded dzd 9 0 601 00000000 8d3S4 68854 019393 d 14854 H3X0 OS Ould balled Subd 9 0 60 100L1010 04854 19353 24854 24854 74854 94854 98854 29353 09359 v3xo os 11110000 ouldod Paldod zuldod euldod 5 MIG0d 1 0100
83. ENTS 2071010 The RSSI measures the power referred to the RF_IN pin The input power can be calculated using the following equations 48 8 Vrssr 57 2 dBm at 433 MHz 46 9 Vrssr 53 9 dBm at 868 MHz The external network for RSSI operation is shown in Figure 41 R281 27 kQ C281 1nF A typical plot of RSSI voltage as function of input power is shown in Figure 42 When using the on chip A D converter set ADCON 0x06 to initiate a single conversion using VDD as reference The converted RSSI voltage can then be read from the ADDATH and ADDATL registers Voltage poopoopoo z lt gt 20 105 100 95 90 85 80 75 70 45 60 55 50 dBm Figure 42 Typical RSSI voltage vs input power SWRS047 Page 126 of 152 Chipcon Products from Texas Instruments 17 21 IF output CCIOI0 has a built in 10 7 MHz IF output buffer This buffer can be used in applications requiring image frequency rejection The system is then built with 201010 a 10 7 MHz ceramic filter SAW front end filter and an external 10 7 MHz demodulator The matching network for an 2071010 external IF filter is shown in Figure 43 R281 470 Q C281 3 3nF This external network provides a 330 Q source impedance for the 10 7 MHz ceramic filter H 1 1 1 AD2 RSSUIF 1 H To 10 7MHz filter and demodulator C281 R281 Figure 43 IF
84. Hz Ohm Ohm 2 Mkr MHz __48 J 1 315 008 8 760 98 57 2 434 088 6 382 49 78 868 028 5 432 2 362 915 020 5 858 21 9279 Figure 38 Typical inactive PA pin impedance 300 1000 MHz SWRS047 Page 121 of 152 SWRS047 Page 122 of 152 TEXAS TEXAS INSTRUMENTS TRUMENTS Chipcon Products Chipcon Products from Texas Instruments 201070 from Texas Instruments 201070 17 19 Output Power Programming The RF output power is programmable the entire 227070 with both the RF and controlled by the POW register transceiver and MCU active Table 37 shows the closest programmable de the PA Pow should 468 a value for output powers in steps of 1 dB Ni power cown mode ne PA anou cr The typical current consumption is also be set to 0x00 for minimum leakage H T shown for a 14 7456 MHz main oscillator current frequency The current consumption is for 5 T E Outputpower RF frequency 433 MHz RF frequency 868 MHz 400 dBm PA POW Current consumption PA POW Current consumption 00 typ mA typ mA 1 20 0x02 217 0 02 24 2 3 100 19 0 02 217 0 02 24 2 amp 18 0x02 21 7 0x03 24 4 8 200 17 0x02 217 0x03 24 4 16 0x02 21 7 0x04 24 6 300 15 0x02 21 7 0x04 24 6 12 34 5 6 7 8 9 A B C D E F 1020 30 40 50 60 70 80 90 AO BO
85. IF ADIF should be cleared before CRPIF so that the 8051 is ready to receive a new interrupt immediately after CRPIF is cleared 4 LOADKEYS RW 0 Enable disable loading of keys at start up 0 New keys are not loaded at encryption decryption start up The same keys as used during the previous encryption decryption will be used again 1 New keys are loaded from RAM at encryption decryption start up The key RAM location is given by CRPKEY 3 CRPMD RW 0 OFB CFB Mode 0 OFB Output Feedback Mode is selected 1 CFB Cipher Feedback Mode is selected 2 ENCDEC R W 0 Encryption Decryption select 0 Encryption is selected 1 Decryption is selected 1 TRIDES R WO 0 Reserved write 0 CRPEN RW1 0 Encryption Decryption start and status bit When set by software encryption decryption is initiated It cannot be cleared by software but will be cleared by hardware when the encryption decryption is completed CRPKEY 0xC4 Encryption Decryption Key Location Register Bit Name R W Reset value Description 7 0 CRPKEY 7 0 R W 0x00 CRPKEY 7 0 gives the 8 most significant bits of the external RAM location of the DES keys The keys are located in RAM as given in Table 24 CRPDAT 0xC5 Encryption Decryptio n Data Location Register Bit Name RIW Reset value Description 7 0 CRPDAT 7 0 R W 0x00 CRPDAT 7 0 gives the 8 most sign
86. IM should be set to 5 15 12 4 Chip Erase The Chip Erase instruction erases all data in the Flash memory including the lock bits All bits will be set high Wait 450 ms depending on Set Flash Timing after sending the Chip Erase instruction before issuing a new instruction 15 12 5 Load Program Memory Page The Load Program Memory Page instruction is used to load the 128 bytes of data in a page to a buffer in RAM Each instruction writes one byte to the 7 bit address specified in the instruction SWRS047 Page 39 of 152 Chipcon Products from Texas Instruments 15 12 6 Write Program Memory Page The Write Program Memory Page instruction writes the 128 bytes buffered through the Load Program Memory Page instructions to Flash memory After issuing this command wait 5 4 ms for it to complete It is also possible to use the Read Program Memory instruction to poll when the program memory has been written When writing is in progress all read instructions will return OXFF Reading an address containing data different from OxFF can then be used to check when the write is completed 15 12 7 Read Program Memory The Flash program memory can be read back byte by byte using the Read Program Memory instruction The data is returned in byte 4 of the instruction Wait at least 9 Txosc between the last negative transition on SCK for byte 3 before issuing the first positive edge on SCK for byte 4 to receive valid data
87. M1 LOCK_ MODEM1 LOCK _ receiver is turned on SETTLING AVG_MODE 1 AVG_MODE 1 AVG_MODE 0 AVG_MODE 0 1 Lock of Average Filter is controlled 1 0 MODEM1 LOCK _ MODEM1 LOCK _ MODEM1 LOCK_ 1 _ by LOCK IN AVG IN 0 5 1 AVG_IN 0 1 AVG IN X AVG IN X 4 LOCK STAT R 0 Average filter status bit 00 4 M 16 16 0 Average filter is free running 01 25 22 32 32 1 Average filter is locked 10 46 43 64 64 3 2 SETTLING 1 0 RW 11 Settling time of average filter 11 89 86 128 128 00 11 baud settling time worst case Table 31 Minimum preamble bits for locking the averaging filter NRZ and UART mode Notes The averaging filter is locked when MODEM1 LOCK AVG set to 1 X Do not The timer for the automatic lock is started when RX mode is set in the REMAIN register Also please note that in addition to the number of bits required to lock the filter you need to add the number of bits needed for the preamble detector See the next section for more information Settling Free running Manchester mode MODEMI MODEMI LOCK SETTLING AVG MODE 1 1 0 MODEM1 LOCK AVG IN 0 00 23 01 34 10 55 11 98 Table 32 Minimum number preamble chips for averaging filter Manchester mode TEXAS INSTRUMENTS SWRS047 Page 99 of 152 1 2dB loss in sensitivity 01 22 baud settling time worst case 0 6
88. MPLIANT PB FREE 23 RECOMMENDED PCB FOOTPRIN 24 PACKAGE THERMAL COEFFICIENTS 25 TRAY SPECIFICATION 26 CARRIER TAPE AND REEL SPECIFICATION 27 LIST OF ABBREVIATIONS 28 SFR SUMMARY 29 ALPHABETIC REGISTER INDEX 30 ORDERING INFORMATION 31 GENERAL INFORMATION 31 1 DOCUMENT HISTORY 31 2 PRODUCT STATUS DEFINITIONS 31 3 DISCLAIMER 314 TRADEMARKS 31 5 LIFE SUPPORT POLICY 32 ADDRESS INFORMATION ION SWRS047 Page 3 of 152 39 texas INSTRUMENTS 1 Chipcon Products from Texas Instruments Features Fully Integrated UHF RF Transceiver e Programmable frequency in the range 300 1000 MHz High sensitivity typically 107 dBm at 2 4 kBaud e Programmable output power 20 to 10 dBm e Very low current consumption RX 9 1 mA e Very few external components required and no external RF switch or IF filter required Single port antenna connection e Fast PLL settling allows frequency hopping protocols FSK modulation with a data rate of up to 76 8 kBaud e Manchester or NRZ coding and decoding of data performed in hardware Byte delineation of data can be performed in hardware to lessen the processor burden RSSI output which can be sampled by on chip ADC e Complies with EN 300 220 and CFR47 part 15 High Performance and Low Power 8051 Compatible Microcontroller e Optimised 8051 core which typically gives 2 5x the
89. NS 8X0 9 01000000 3a0W2 Gd ZEX SSVdAG ZEX 5 NOOZEX LOXO zz 00000000 TAS 5 d Sda 98xo ez 00000000 d 1d AO 05 154 03 ov MSd 00000000 V 1Hdd ZIHdd Hdd vIHdd S 1Hdd 91Hdd L Hdd 9 801 10101110 918 0884 1d O34 918 354 614 O34 028 0384 128 O34 258 0884 ezg 0884 az 30 0 z 00000000 oid Erda 2 dd S Vida v8X0 801 10100101 88 0383 68 org 0884 L1 0884 219 0884 18 0884 vig 0884 Sig 0883 8l 3OXO LZ 00000000 vOHAG S OHdd 9 0Hdd 8x0 60L OLLLOOLO 08 O3H4 18 O3H4 zg O3H4 8 O33 vd O34 Sd O33 98 O34 1H O34 H0 LZ 00000000 Toda Koda zoldd o1dd yoda Odd 28 0 801 10101110 0884 ZW 0884 0884 61V 0884 ozv 0884 12 0884 22 0884 ezv OdH4 ve 20 0 vz 11100000 0 85 vds 245 eds vds 945 945 ZdS ds 180 801 0000010 8V O3HJ 6V O33 O32 LIV 0384 ziv O34 O38 OdH4 Vi gOXO 11110000 Od Od 208 0d Od 904 909 2 04 Od 801 1 010011 0884 zv 0884 V bv 0884 SV O33 9V 0884 O3H4 VOXO S6 00000000 0JngJs ENEE 4 3ngds ng Sanat 93ngJs 13ng3s anad 69 0 68 00011100 8 ad svig Gd 3809 dd 54 XL XL 89x0
90. Output TEXAS INSTRUMENTS SWRS047 Page 127 of 152 Chipcon Products from Texas Instruments 17 22 Optional LC Filter An optional low pass LC filter may be added between the antenna and the matching network in certain applications The filter will reduce the emission of harmonics and increase the receiver selectivity The filter topology is shown in Figure 44 Component values are given in Table 38 The filter is designed for 50 Q terminations The component values may have to be tuned to compensate for layout parasitics C1010 The design equations for a 3dB equal ripple filter are 1 2 LLL Oc 2 far n 35 6 0 067 where c is the cut off frequency and is the transmitted RF frequency Figure 44 LC Filter Item 315 MHz 434 MHz 869 MHz 915 MHz 30 20 pF 10pF 10 pF C72 30pF 20 pF 10pF 10 pF 171 15nH 12nH 5 6 nH 4 7 nH Table 38 LC Filter component values TEXAS INSTRUMENTS SWRS047 Page 128 of 152 Chipcon Products from Texas Instruments 2071010 18 Reserved registers and test registers The 207010 contains a few registers intended for test purposes only Normally these registers should not be written to The FSHAPEn FSDELAY and FSCTRL registers are reserved for future use A separate reset signal for the PLL is available in FSCTRL FS RESET N This will reset the frequency divider part of the PLL
91. P RW 0 Parity flag Set to 1 when the modulo 2 sum of the 8 bits in the accumulator is 1 odd parity cleared to 0 on even parity ACC 0xE0 Accumulator Register Bit Name Reset value Description 7 0 7 0 RW 0x00 Accumulator B 0xF0 B Register Bit Name RW Reset value Description 7 0 B 7 0 RW 0x00 B is used for multiplication and division TEXAS INSTRUMENTS SWRS047 Page 23 of 152 Chipcon Products C from Texas Instruments SP 0x81 Stack Pointer 2071010 Bit Name RW Reset value Description 7 0 SP 7 0 RW 0x07 Stack Pointer used for pushing and poping data to and from the stack Note that the reset value for SP is 0x07 15 5 Instruction Set Summary The 8051 instruction set is summarised in Table 12 below All mnemonics are Copyright Intel Corporation 1980 One non standard 8051 instruction TRAP with opcode OxA5 is included to enable setting of breakpoints This instruction is described in the In Circuit Debugging section at page 44 Symbols used in the table are Accumulator Register pair A and B B Multiplication register e c Carry flag e DPTR Data pointer Rn Register RO R7 PC Program counter e direct 8 bit data address Internal RAM 0x00 0x7F SFRs 0x80 0xFF e Internal register pointed to by RO R1 except MOVX e rel Two s complement offset byte used
92. Power down 2 PD RW O0 Power down of main crystal oscillator core 0 Power up 1 Power down 1 Bras PD RW O Power down of bias current generator and crystal oscillator buffer 0 Power up 1 Power down Reserved read as 0 TEXAS INSTRUMENTS SWRS047 Page 89 of 152 ic Chipcon Products from Texas Instruments 2071010 TX RX or TX Turn on RX RFMAIN RXTX 0 F REG 0 RX_PD 0 FS PD 0 CURRENT RX current Wait 250 ps RX mode Turn off RX REMAIN RX PD 1 FS_PD 1 TEXAS INSTRUMENTS Turn on TX 00h RFMAIN RXTX 1 F REG 1 TX PD 0 FS PD 0 CURRENT TX current Wait 250 ps Y Output power Wait 20 us Tum off TX RFMAIN TX 1 PD 1 00h RF Power Down Figure 22 RF Transceiver power on sequence SWRS047 Page 90 of 152 Chipcon Products from Texas Instruments 17 6 Data Modem and Data Modes Four different data modes are defined for transmission and reception programmable through MODEMO DATA FORMAT These modes differ in data encoding how incoming and outgoing data is delivered and accepted and whether resynchronisation of the bitstream is performed clock regeneration or not The data format should be selected before enabling the RF Transceiver Two of the modes Synchronous NRZ
93. RATION 17 1 GENERAL DESCRIPTIO 17 2 RF TRANSCEIVER BLOCK DIAGRAM 17 3 RF APPLICATION CIRCUIT 17 4 TRANSCEIVER CONFIGURATION OVERVIEW 17 5 RF TRANSCEIVER RX TX CONTROL AND POWER MANAGEMENT 17 6 DATA MODEM AND DATA MODE 17 7 BAUD RATES 17 8 TRANSMITTING AND RECEIVING DATA 39 thas INSTRUMENTS 2071010 SWRS047 Page 2 of 152 fro foxes Instruments t 10 10 17 9 DEMODULATION AND DATA DECISION 17 10 SYNCHRONIZATION AND PREAMBLE DETECTION 17 11 RECEIVER SENSITIVITY VERSUS DATA RATE AND FREQUENCY SEPARATI 17 12 FREQUENCY PROGRAMMING 17 13 LOCK INDICATION 17 14 RECOMMENDED SETTINGS FOR ISM FREQUENCIES 17 15 17 16 1717 LNA AND BUFFER CURRENT CONTRO 17 18 INPUT OUTPUT MATCHING 17 19 OUTPUT POWER PROGRAMMING 17 20 RSSI OUTPUT 17 21 IF OUTPUT 17 22 OPTIONAL LC FILTEI 18 RESERVED REGISTERS AND TEST REGISTERS 19 SYSTEM CONSIDERATIONS AND GUIDELINES 19 1 SRD REGULATIONS 19 2 LOWCOST SYSTEMS 19 3 BATTERY OPERATED SYSTEMS 19 4 NARROW BAND SYSTEMS 19 5 RELIABILITY SYSTEMS 19 6 FREQUENCY HOPPING SPREAD SPECTRUM SYSTEM 19 7 SOFTWARE 19 8 DEVELOPMENT TOOLS 19 9 PA SPLATTERING 19 10 LAYOUT RECOMMENDATION 19 11 ANTENNA CONSIDERATIONS 20 PACKAGE DESCRIPTION TQFP 64 21 SOLDERING INFORMATION 22 PACKAGE MARKIN 22 1 STANDARD LEADEI 222 ROHS CO
94. REF ADCON AD PD should be set when the ADC is not used in order to save power A conversion can be started 5 us after clearing the bit when using VDD or an external reference or 100 us afterwards when using the internal 1 25V reference The input impedance of the ADC is a 3 2pF switched capacitor that samples the input signal once for each conversion The average input impedance is thus A Average input impedances for minimum and maximum sampling frequencies are shown in Table 26 2071010 In each conversion cycle the input signal is sampled on the sample capacitor during one half clock period During this time the accuracy of the voltage on the capacitor must reach at least LSB accuracy in order to get the full accuracy of the conversion Charging of the capacitor follows the Caharing formula E Y 5 t 1 y B 2f In err in The result of this formula is the maximum output resistance of the source for a given ADC clock frequency and accuracy 30 safety margin should be used due to non perfect duty cycle etc ie a maximum output resistance 30 less than calculated should be used For LSB accuracy in the charging Table 27 shows the maximum output resistance that should be used for the source at maximum and minimum ADC clock frequencies feik Rmax 250 kHz 57 32 kHz 450 fei fs Rin 250 kHz 22 7 kHz 714 MO 32kHz 2 9 kHz 7107
95. SM1_0 Mode is 0 If SM2_1 1 in mode 1 RI_1 will only be activated if a 6 0 RW 0 0 0 0 Synchronous half duplex valid stop bit is received In mode 0 5 2 1 establishes the 1 1 Asynchronous full duplex start stop bit baud rate when SM2 1 0 the baud rate is clk 12 when 1 0 2 Asynchronous full duplex start stop bit SM2 1 1 the baud rate is clk 4 9th data bit 1 1 3 Asynchronous full duplex start stop bit 4 REN 1 RW 0 Receive enable When REN_1 1 reception is enabled 9th data bit Defines the state of the 9th data bit transmitted in modes 2 and 5 SM2 0 RW 0 Multiprocessor communication enable In modes 2 and 3 3 5 2_0 1 enables the multiprocessor communication feature 2 1 0 In modes 2 and 3 RB8 1 indicates the state of the 9th bit In mode 2 or 3 0 will not be activated if the received 9th bit received In mode 1 RB8 1 indicates the state of the received is 0 If SM2 0 1 in mode 1 RI 0 will only be activated if a stop bit In mode 0 RB8 T is not used valid stop bit is received In mode 0 SM2_0 establishes the 1 TI1 RW O Transmit interrupt flag Indicates that the transmit data word baud rate when SM2_0 0 the baud rate is clk 12 when has been shifted out In mode 0 1 is set at the end of the SM2 0 1 the baud rate is clk 4 8th data bit In all other modes TI 1 is set when the stop bi
96. Some calibration times for different reference frequencies are listed in Table 36 When CAL CAL WAIT 0 it takes 12825 cycles but this is not recommended TEXAS INSTRUMENTS 2071010 Typical tuning range for the integrated varactor is 20 25 Component values for various frequencies are given in Table 28 Component values for other frequencies can be found using the SmartRF Studio software Reference frequency Calibration time MHz Ims 24 10 69 20 12 83 15 1710 10 25 65 Table 36 Calibration times The CAL START bit must be cleared after the calibration is done This will also clear the CAL CAL COMPLETE status bit There are separate calibration values for the two frequency registers If the two frequencies A and B differ more than 1 MHz or different VCO currents are used CURRENT VCO CURRENT 3 0 the calibration should be done separately When using a 10 7 MHz external IF the LO is 10 7 MHz below above the transmit frequency hence separate calibration must be done The CAL CAL DUAL bit controls dual or separate calibration The single frequency calibration algorithm using separate calibration for RX and TX frequency is illustrated in Figure 34 In Figure 35 the dual calibration algorithm is shown for two RX frequencies It could also be used for two TX frequencies or even for one RX and one TX frequency if the same VCO current is used In multi channel and frequency
97. Static RAM SRD Short Range Device e TQFP Thin Quad Flat Pack e TBD To Be Defined e TX Transmit e UART Universal Asynchronous Receiver Transmitter e UHF Ultra High Frequency e VCO Voltage Controlled Oscillator e XOSC Crystal Oscillator SWRS047 Page 140 of 152 SIXTWIMISN STIS SCIL de SYL de ZS Jo Zp Zy0SYMS 29 30 yp afed Zv0SYMS ZZ 00000000 OASDdHO TEREKE ZA3WdHo GENES ENE TENE vOXO 92 00000000 N3dHO SSM SASMQVOT 31980 21490 NOOdNO vor 01100000 3aowaiag OLIN JOIN 3 Noose 20 0 19 00000000 0 1Jngs Vanes 24185 13ngs 74185 9 14185 913nas 213085 13085 10 0 89 00000000 DIT Dam 1 1 V T ZNS TINS 1 ONS 1NOOS 00 0 82 00000000 0 ZINIdHO V ZINIdHO ZINIdNO Y ZINIdHO S ZINIdNO 9 ZINIdHO L IINIdNO IINIdHO J8xo 82 0000000
98. T low and apply a clock signal to XOSC 01 Release RESET after at least 3 clock periods and then wait at least 4 clock periods Execute the Programming Enable instruction to complete the SPI Flash programming Initialisation 220 is now ready to be programmed as described in the next section SWRS047 Page 41 of 152 Chipcon Products from Texas Instruments 15 12 12 Programming the Flash Memory After the initialisation is completed SPI programming can be performed as follows e Device identity can be verified using the Read Signature Byte instruction e Perform Chip Erase e Load one page into the buffer using the Load Program Memory Page instruction e Write the buffer to Flash by using the Write Program Memory Page instruction 15 13 8051 Flash Programming Each of the 256 pages 128 bytes each in Flash program memory can be programmed individually from the 8051 The 8051 must be set in Idle Mode while programming the Flash since it has no access to the program memory while the writing is in progress The step for writing a page to Flash is described as follows Set the correct write cycle time according to the current crystal oscillator frequency in the FLTIM SFR This number is used to generate the timing to the on chip Flash interface as was also done with SPI Flash programming It must be set so that Fien sis 0 8MHz 0 4MHz The time used for programming a Flash page is s
99. The violation detection is determined by how balanced the bit is by looking at the 14 samples A perfect bit is 14 all samples are correct The limit can be set from 1 7 001 111 0 disable the violation detection function to 0 BYTEMODE 0 Select bit or bytemode 0 Bitmode is enabled Data is transmitted and received bit by bit through RFBUF 0 1 Bytemode is enabled Data is transmitted and received byte by byte through RFBUF with MSB first BYTEMODE is ignored if PDET PEN 1 TEXAS INSTRUMENTS SWRS047 Page 101 of 152 Chipcon Products from Texas Instruments 17 10 Synchronization and preamble detection Most RF communication protocols will have a preamble designated to let the receiver synchronise reception on a bit and byte level 227010 contains hardware that will perform these tasks easily in synchronous NRZ and Manchester encoded modes The byte synchronization mechanism ensures that the framing of bytes in the received data bit stream is correct thus freeing the software from needing to perform shifting and recombination of data bytes In addition the synchronization byte functions as a start of frame delimiter The preamble detection mechanism reduces the workload for the processor when the exact time of the start of a transmission is uncertain Both mechanisms are active when PDET PEN is set See PDET register definition below Two preamble 2071010
100. The reset is active when a zero is written and a one must be written for the reset to be released FSCTRL EXT FILTER can be set in order to use an external PLL loop filter However this is not recommended in a normal application The PRESCALER register controls the prescaler current and should always be set to 0x00 which is the reset state The TESTMUX register is not needed for normal operation of 667010 but is included here for completeness TESTMUX should always be set to 0x00 TESTMUX P0 2 1 0 0000 Normal operation Normal operation Normal operation 0001 CLK REF CLK PHASE DET OUT MODEM TX OUT 0010 LOCK DET CONTINUOUS LOCK DET INSTANT ANALOG WINDOW SYNC 0011 SER PAR IRQ TIMER2 IRQ TIMER3_IRQ 0100 RTC_IRQ ADC_IRQ DES_IRQ 0101 ANALOG ALARM ANALOG ALARM L CAL DIG COMPLETE 0110 MODEM BIT CLK MODEM RX DATA ANALOG OUT 0111 MODEM BIT CLK MODEM TX DATA MODEM TX OUT 1000 ADC SAR ADCCLK EN ANALOG COMP ADC SAR EOC 1001 CLK RTC RTC IRQ CLK UC 1010 DES DEBUG 0 1011 DES DEBUG 1 1100 DES DEBUG 2 1101 DES DEBUG 3 1110 FLASH WRITE IRQ 1111 CAL DIG COMPLETE Table 39 TESTMUX modes FSHAPEn 0xF1 0xF7 1 7 Frequency Shaping Register n Bit Name RW Reset value Description 75 0 00 Reserved read as 0 40 FSHAPEn 4 0 0xxx Reserved for future use FSDELAY 0xE9 Frequency Shaping Dela
101. as an output and MI as an input The direction bit PODIR 1 still determines the direction of the master data output pin MO This allows the SPI master to communicate with a bi directional data line PODIR 1 should then be cleared when transmitting and set when receiving data with MO and MI connected together externally For normal full duplex operation of the SPI master PODIR 1 must be cleared to set MO as an output Any other general purpose may be used for slave select signals to the peripheral modules Chipcon Products from Texas Instruments SPCR 0xA1 SPI Control Register 2071010 Bit Name R W Reset value Description T RO 0 Reserved read as 0 6 RW 0 Reserved write 0 5 SPE RW 0 SPI Enable 0 SPI interface is disabled 1 SPI interface is enabled 4 DORD RW 0 Data Order 0 Least significant bit LSB is transmitted received first 1 Most significant bit MSB is transmitted received first 3 CPOL RW 0 Clock Polarity 0 SCK has negative clock polarity 1 SCK has positive clock polarity 2 CPHA RW 0 Clock Phase 0 Data is output on DO when SCK goes from CPOL to CPOL and is sampled from DI when SCK goes from CPOL to CPOL 1 Data is output on DO when SCK goes from CPOL to CPOL and is sampled from DI when SCK goes from CPOL to CPOL 1 0 SPR 1 0 RW 0 SPI Data Rate SPR 1 0 00 SCK clock frequency fxosc 8 01 SCK clock
102. ash Power Control section on page 44 SWRS047 Page 35 of 152 Chipcon Products C from Texas Instruments PCON 0x87 Power Control Register C1010 Bit Name RW Reset value Description 7 SMODO 0 Serial Port 0 baud rate doubler enable 0 Serial Port 0 baud rate is not doubled 1 Serial Port 0 baud rate is doubled 6 0 Reserved 5 R1 1 Reserved read as 1 4 R1 1 Reserved read as 1 3 GF1 RW 0 General purpose flag 1 Bit addressable general purpose flag for software control 2 GFO RW 0 General purpose flag 0 Bit addressable general purpose flag for software control 1 STOP RW 0 Power Down Stop mode select Setting the STOP bit places 661010 core and peripherals in Stop Mode 0 IDLE RW 0 Idle mode select Setting the IDLE bit places 227070 in Idle Mode core is stopped but peripherals are running X32CON 0 01 32 768 kHz Crystal Osc illator Control Register Bit Name Reset value Description ri 0 Reserved read as 0 6 RO 0 Reserved read as 0 5 RO 0 Reserved read as 0 4 RO 0 Reserved read as 0 3 0 Reserved read as 0 2 X32 BYPASS R W 0 32 768 kHz oscillator bypass control signal 0 The internal 32 768 kHz oscillator is used to generate the 32 768kHz clock 1 The internal 32 768 kHz oscillator is bypassed and an external clock signal can be applied to the XOSC32 01 pin
103. ated write to Flash program memory is completed or a TRAP instruction is executed FDIF may also be set by software FDIF must be cleared by software before exiting the ISR 3 RTCIF R W 0 Real time clock interrupt flag RTCIF is set by hardware when an interrupt request is generated from the real time clock RTCIF may also be set by software RTCIF must be cleared by software before exiting the ISR 2 0 Reserved read as 0 1 RO 0 Reserved read as 0 0 RO 0 Reserved read as 0 EXIF 0x91 Extended Interrupt Flag Bit Name RW Reset value Description 7 R W 0 Timer 3 interrupt flag TF3 is set by hardware when an interrupt request is generated from Timer 3 TF3 may also be set by software TF3 must be cleared by software before exiting the ISR 6 ADIF R W 0 ADC DES Interrupt flag ADIF is set by hardware when an interrupt request is generated from the ADC block ADCON2 ADCIF or by the DES Encryption Decryption block CRPCON CRPIF These interrupts must also be enabled by setting ADCON2 ADCIE and CRPCON CRPIE ADIF may also be set by software ADIF must be cleared by software before exiting the ISR 5 TE2 R W 0 Timer 2 interrupt flag TF2 is set by hardware when an interrupt request is generated from Timer 2 TF2 may also be set by software TF2 must be cleared by software before exiting the ISR Bit Name Reset
104. cation For serial port 0 pin RXDO P3 0 is used for data input and output while TXDO P3 1 provides the bit clock for both transmit and receive For serial port 1 the corresponding pins are RXD1 P2 0 and TXD1 P2 1 The serial mode 0 baud rate is set by SCONO SM2_0 SCON1 SM2_1 If this bit is cleared the baud rate is the system clock divided by 4 If the bit is set the system clock is divided by 12 TEXAS INSTRUMENTS Data transmission begins when an instruction writes to the SBUFO or SBUF1 register The serial port shifts the data byte out LSB first at the selected baud rate Data reception starts when SCONO REN 0 1 SCONI REN 1 is set and the receive interrupt flag SCONO RI 0 SCON1 RI_1 is cleared The bit clock is activated and the UART shifts data in on each rising edge of the bit clock until 8 bits have been received Immediately after the 8th bit is shifted in the receive interrupt flag is set and reception stops until the software clears the flag SWRS047 Page 68 of 152 Chipcon Products from Texas Instruments The clock output is high when the serial port is idle In reception data is shifted in on the rising edge of the clock In 61010 transmission each new bit is set on the falling edge of the clock Baudrate TiM TH1 kBaud Fxosc Fxosc Fyose Fxosc Fxosc Fxosc 3 6864 7 3728 11 0592 14 7456 18 4320 22 1184 MHz MHz MHz MHz MHz MHz 57
105. cation Register CRPINIn ne 0 7 0xB4 0xB7 OXBC OxBF DES Initialisation Vector CRPKEY 0xC4 Encryption Decryption Key Location Register CURRENT 0 1 RF Current Control Register DPHO 0x83 Data Pointer 0 high byte 0x85 Data Pointer 1 high byte DPLO 0x82 Data Pointer 0 low byte DPL1 0x84 Data Pointer 1 low byte DPS 0x86 Data Pointer Select EICON 0 08 Extended Interrupt Control EIE OxE8 Extended Interrupt Enable Register EIP OxF8 Extended Interrupt Priority Register EXIF 0x91 Extended Interrupt Flag FLADR Flash Write Address Register FLCON OxAF Flash Write Control Register FLTIM 0xDD Flash Write Timing Register FREND Front End Control Register FREQ 0A 0xCA Frequency A Control Register 0 FREQ 0B 0xCD Frequency B Control Register 0 FREQ 1 0xCB Frequency A Control Register 1 FREQ 1B 0xCE Frequency B Control Register 1 SWRS047 Page 145 of 152 TEXAS INSTRUMENTS Chipcon Products FREQ 2 0xCC Frequency A Control Register 2 FREQ 2B 0xCF Frequency B Control Register 2 FSCTRL Frequency Synthesiser Control Register FSDELAY 0xE9 Frequency Shaping Delay Control Register FSEPO Frequency Separation Control Register 0 FSEP1 Frequency Separation Control Register 1 from Texas Instrum
106. communication with a host PC without disrupting applications that use the main serial port for other purposes Setting breakpoints and executing the instructions which have a_ breakpoint attached involves writing new data to the Flash instruction memory several times Since the Flash memory can only withstand 20000 typical erase write cycles a simple instruction replacement mechanism has been implemented This feature allows the surveillance of an address in the instruction memory space as defined in registers RADRL and RADRH When this address is encountered on the Flash program memory address bus the data returned on the data bus is replaced by the contents of register RDATA Setting RADRH RADRL 0 disables the replacement mechanism This instruction replacement mechanism can be used in different ways e A simple way of setting a single soft not stored in FLASH breakpoint by setting RDATA to OxA5 the TRAP instruction and RADR to the breakpoint address e A simple way of restoring the original opcode byte of an instruction which has been subjected to a hard stored SWRS047 Page 44 of 152 Chipcon Products from Texas Instruments in Flash breakpoint so that it can be executed in single step mode 61010 which can then not be used for other purposes If in circuit debugging is not required the RESERVED register shown ic Chipcon Products
107. d be used for general I O Chipcon strongly recommends that the synchronous modes be used The other data modes bypass the data decision circuitry of the RF transceiver and do not support bytemode The Transparent mode is only intended for testing 17 6 1 Manchester encoding In Manchester mode the data clock is transmitted along with the data A 1 is encoded as a high frequency f followed by a lower frequency fo 0 is encoded as a low frequency fy followed by a higher frequency f This is illustrated in Figure 23 See the Frequency programming section on page 106 for definitions of fo and The Manchester code ensures that the signal has a constant DC component which is necessary in some FSK demodulators Using this mode also ensures compatibility with 2400 22900 designs The properties of the different data modes are summarized in Table 29 SWRS047 Page 91 of 152 Chipcon Products from Texas Instruments data Figure 23 Manchester encoding Transparent UART mode Synchronous Synchronous NRZ mode Manchester mode encoded mode Baudrate User defined Defined by UART Generated by hardware as defined by configuration through Timer 1 MODEMO BAUDRATE Data encoding User defined Defined by UART Manchester None NRZ settings encoding Bitrate is half of baudrate Data Input amp RFBUF 0 N A RFBUF bytemode RFBUF 0 in bitmode Output Clock
108. dB loss in sensitivity 10 43 baud settling time worst case 0 3dB loss in sensitivity 11 86 baud settling time worst case 0 15dB loss in sensitivity 3 PEAKDETECT RW Peak detector and remover enable disable 0 Peak detector and remover is disabled 1 Peak detector and remover is enabled MODEM RESET RW Separate reset of tte MODEM 0 The Modem is reset 1 The Modem reset is released MODEN2 0xD9 Modem Control Register 2 Bit Name R W Reset value Description 7 0 Reserved read as 0 60 PLO 6 0 RW 0x16 Peak Level Offset threshold level for peak the peak detector and remover in the demodulator which is activated when MODEM1 PEAKDETECT is set PLO should be set as described on page 97 TEXAS INSTRUMENTS SWRS047 Page 100 of 152 Chipcon Products from Texas Instruments RFCON 0xC2 RF Control Register 2071010 Bit Name R W Reset value Description rm RO Reserved read as 0 4 MVIOL R 0 Manchester code violation status of current bit in bitmode or the aggregate OR of the Manchester code status of all bits in the current byte in bytemode Only valid when MODEMO DATA FORMAT 01 Manchester encoding 33 MLIMIT 2 0 RW 011 Limit value used by the clock regeneration logic in Manchester mode to determine whether the current symbol constitutes a Manchester code violation
109. data OR immediate data to direct byte 3 43 CF XRL A Rn Exclusive OR register to A 1 1 68 6F x XCH A direct Exchange A and direct byte 2 2 C5 x XRL A direct Exclusive OR direct byte to A 2 2 65 x XCH GRi Exchange A and data memory 1 1 C6 x XRL A Ri Exclusive OR data memory to A 1 1 66 67 x XRL data Exclusive OR immediate to A 2 2 64 x XCHD A Ri Exchange A and data memory 1 1 D6 x XRL direct A Exclusive OR A to direct byte 2 2 62 nibble D7 XRL direct data Exclusive OR immediate to direct 3 3 63 Boolean byte CLR C Clear carry 1 T x CLR A Clear A 1 1 E4 x CLR bit Clear direct bit 2 2 C2 CPL A Complement A 1 1 F4 x SETB C Set carry 3 1 D3 x SWAP A Swap nibbles of A 1 1 SETB bit Set direct bit 2 2 02 RLA Rotate A left 1 1 23 CPL C Complement carry 1 1 B3 x RLC A Rotate A left through carry 1 1 33 x x CPL bit Complement direct bit 2 2 B2 RRA Rotate A right 1 1 03 ANL C bit AND direct bit to carry 2 2 82 x RRC A Rotate A right through carry 1 1 13 x x ANL C bit AND direct bit inverse to carry 2 2 x Data Transfer ORL C bit OR direct bit to carry 2 2 72 x MOV A Rn Move register to A 1 1 E8 x ORL C bit OR direct bit inverse to carry 2 2 AO x EF MOV C bit Move direct bit to carry 2 j2 A2 x MOV A direct Move direct byte to A 2 2 5 x MOV bit C Move carry to direct bit 2 2 92 SWRS047 Page 25 of 152 SWRS047 Page 26 of 152 TEXAS TEXAS INSTRUMENTS INSTRUMENTS Chipcon Products Chipcon Products from Texa
110. ding to IPC JEDEC J STD 020B July 2002 TEXAS INSTRUMENTS SWRS047 Page 136 of 152 Z rom Tense instruments 2071010 22 Package marking When contacting technical support with a chip related question please state the entire marking information not just the date code 221 Standard leaded S 221010 0444CP2482 00 0444 is the date code week 44 year 04 CP2482 00 is the lot code 22 2 RoHS compliant Pb free 2 0444CP2482 00X 0444 is the date code week 44 year 04 CP2482 00 is the lot code X means Pb free SWRS047 Page 137 of 152 TEXAS INSTRUMENTS Chipcon Products 2 from Texas Instruments 23 Recommended PCB footprint 2 032mm TO MN 0 455mm 61010 305mm 8 84mm Note The figure is an illustration only and not to scale See the CC1010EM reference design for recommended PCB layout 24 Package thermal coefficients Package thermal coefficients K W Power W Min Avg Max Min Avg Max 71 1 80 8 90 5 0 4 0 5 0 6 SWRS047 Page 138 of 152 XAS RUMENTS 2 Rom Texas Instrumente 2071010 25 Tray Specification TQFP 64 antistatic tray 8 by 20 devices Tray Specification Package Tray Width TrayLength Tray Units per Height Tray 64 135 9 mm 322 6 mm 7 62 mm 160 26 Carrier Tape and Reel Specification Carrier tape and reel is in
111. e See also page 133 for layout recommendations AGND DGND Ground for analog and digital modules respectively Normally one common ground plane is recommended If two separate analog and digital grounds are used they should be interconnected in one place and one place only RFIN This is the RF input internally connected to the low noise amplifier LNA The signal source antenna should be TEXAS INSTRUMENTS ground is needed for LNA biasing RFOUT This is the RF output internally connected to the power amplifier PA The external load antenna should be matched to the output impedance optimum load impedance This pin must be DC coupled to AVDD for PA biasing open drain output L1 L2 Connection to internal voltage controlled oscillator VCO An inductor should be connected between these pins The inductor value will determine the VCO tuning range The inductor should be place very close to the pins in order to minimize paracitic inductance CHP OUT Charge Pump output If the RF transceiver is configured for external loop filter this is the current output from the charge pump Normally the internal loop filter should be used and this pin should be left open not connected SWRS047 Page 15 of 152 POR E Enable signal for the on chip power on reset module The power on reset is enabled when POR E is connected to DVDD and disabled when connected to DGND PROG Active low Flash programming
112. e cleared by software In Timer mode interrupts are generated with an interval as given by where 2 3 255 TnPRE 256 Tn 1 G RR sten As long as TnPRE and Tn are set before TCON TRn the first interrupt is generated Tnwr after enabling the timer and then with intervals SWRS047 Page 59 of 152 Chipcon Products C from Texas Instruments 2071010 Timer 2 Timer 3 16 bit counter ok Seem ove ek si zs sapis onov Tmer2 EXIF TF2 ve or Timer 3 E CE ereta on mera MPEP e TS TATS T7 T2 orT3 De T2PRE or T3PRE or TR3 Figure 11 Timer Mode operation for Timer 2 Timer 3 T2PRE 0xAA Timer 2 Prescaler Control Bit Name RW Reset value Description 7 0 T2PRE 7 0 RW 0x00 Timer 2 Prescaler Control In Timer Mode T2PRE sets the 8 most significant bits of the 16 bit counter reload value In PWM Mode T2PRE sets the prescaler value that sets the PWM period T3PRE 0xAB Timer 3 Prescaler Control Bit Name R Reset value Description 7 0 T3PRE 7 0 0x00 Timer 3 Prescaler Control In Timer Mode T3PRE sets the 8 most significant bits of the 16 bit counter reload value In PWM Mode T3PRE sets the prescaler
113. ed wait 450ms after the instruction before issuing Write 7 Flash memory is programmed one page at a time Each page consists of 128 bytes Load all bytes of the page that is to be programmed with the Load Program Memory Page instruction 8 When all bytes of a page has been loaded issue Write Program Memory Page with the page address The write operation finishes within 5 4ms SWRS047 Page 37 of 152 Chipcon Products from Texas Instruments Reading an address while writing will return OxFF This can be used for polling to determine when a page write is finished When a read instruction returns anything other than FF all flash write operations 2071010 15 12 1 SPI Flash Programming Instructions 9 instructions are defined to perform the serial Flash programming These are have finished shown in Table 16 Instruction Byte 1 Byte 2 Byte 3 Byte 4 Operation Enable serial Programming 1010 1100 0101 0011 xxxx xxxx xxxx xxxx programming after Enable PROG is set low Set Flash 1010 1100 0101 1101 xxii iiii Set the Flash timing Timing register Chip erase Clears all Chip Erase 1010 1100 100x xxxx xxxx xxxx Xxxx xxxx pages including the lock bits Load data i to Load Program 0100 H000 xxxx xxxx bbbb bbxx iiii iiii Programming Buffer at Memory Page address b H Write Program o100 1100 aaaa aaaa xxxx xxxx xxxx xxxx Write the loaded page
114. ee rose MODEMO XOSC _ FREQ 1 IF and Af is the deviation SmartRF Studio may be used to configure this correctly 61010 It is important that the peak detector is program med with a correct value an error may result in incorrect data reception 150kHz 2 fp XTAL accuracy Average fiter equal e g Manchester code or a In a polled receiver system the automatic balanced preamble locking can be used This is illustrated in Sampler nd Decimator pud gt Therefore all modes also synchronous Figure 26 If the receiver is operated NRZ mode need a DC balanced preamble continuously searching for for the internal data slicer to acquire preamble the averaging filter should be Figure 25 Demodulator block diagram correct comparison level from the locked manually as soon as the preamble averaging filter The suggested preamble is detected This is shown in Figure 27 If is a 010101 bit pattern The same bit the data is Manchester coded there is no Data package to be received pattern should also be used in Manchester Natum E g mode giving a 011001100110 chip AVG INE pattern This is necessary for the bit Figure 28 Noe Preamble NRZ data synchronizer to synch
115. els of security are required a triple DES algorithm can be used Triple DES can be achieved by running the DES algorithm three times sequentially using three different 56 bit encryption keys The keys must be used in reverse order when decrypting The DES algorithm works internally on entities of 8 bytes The Output Feedback Mode OFB and Cipher Feedback Mode CFB are DES modes of operation that permit data lengths that are not a multiple of eight bytes The operation mode is selected through the CRPCON CRPMD control bit The same DES mode of operation must be used both for encryption and decryption to yield correct results CFB is recommended as it is more secure than OFB CRPCON ENCDEC should be cleared when encrypting data and set when decrypting data 56 bit DES keys are stored in external RAM as shown in Table 24 The location is given by the register CRPKEY s INSTRUMENTS 2071010 containing the 8 most significant address bits New keys are loaded only at the beginning of an encryption decryption if CRPCON LOADKEYS is set If not the same keys as used in the previous run will be used again The DES keys do not contain parity bits If DES keys with parity bits are given the parity bits must be removed before performing encryption decryption The keys are therefore stored as 7 successive bytes in RAM After running the DES a output block of length CRPCNT bytes is generated by encrypting decrypt
116. enable pin When this signal is active driven to DGND a Flash programmer can be connected to the SPI interface Under normal operation it must be driven to DVDD RESET Active low asynchronous system reset It has an internal pull up resistor and can be left unconnected during normal operation ADO AD1 Analog inputs to A D converter channels 0 and 1 respectively When not used these pins can be left open not connected RSSI IF Analog input to A D converter channel 2 This pin can also be configured to be RSSI TEXAS INSTRUMENTS directional CMOS I O port with 2 mA drivers A direction register P1DIR controls whether each pin is an output or input and the register P1 is used to read the input or control the logical value of the output PORT 2 Port 2 is an 8 bit P2 7 P2 0 bi directional CMOS I O port with 2 mA drivers except for P2 3 that has an 8 mA output buffer A direction register P2DIR controls whether each pin is an output or input and the register P2 is used to read the input or control the logical value of the output Pins P2 0 and P2 1 can be configured to become the RXD1 and TXD1 pin respectively of UART 1 Pin P2 2 has a Schmitt trigger input stage Note that while this pin does have hysteresis it will draw a large input current 70 5 mA if the input voltage is close to VDD 2 PORT 3 Port is a 6 bit P3 5 P3 0 bi directional CMOS I O port with 2 mA drivers direct
117. ents FSHAPEn OxF1 OxF7 ne1 7 Frequency Shaping Register n IE 0xA8 Interrupt Enable Register IP 0xB8 Interrupt Priority Register LOCK 0xE4 PLL Lock Register MATCH 0xDC Match Capacitor Array Control Register 0xDB Modem Control Register MODEM 0xDA Modem Control Register 1 MODEM2 0xD9 Modem Control Register 2 MPAGE 0x92 Memory Page Select Register PO 0x80 Port 0 Data Register PODIR 4 Port 0 Direction Register P1 0x90 Port 1 Data Register P1DIR 0xA5 Port 1 Direction Register P2 0xA0 Port 2 Data Register P2DIR 0xA6 Port 2 Direction Register 0xBO Port 3 Data Register P3DIR 0xA7 Port 3 Direction Register PA POW 0 2 PA Output Power Control Register PCON 0x87 Power Control Register PDET 0xD3 Preamble Detection Control Registe PLL 0xE3 PLL Control Register PRESCALER 0xE6 Prescaler Control Register PSW 0 00 Program Status Word RADRH 0xBB Replacement address high byte RADRL 0xBA Replacement address low byte RANCON 0xC7 Random Bit Generator Control Registe RDATA 0xB9 Replacement Data RESERVED 0xE7 Reserved register used by Chipcon debugger software RFBUF 0xC9 RF Data Buffer RFCON 0xC2 RF Control Register 39 thus SWRS047 2071010 Page 146 of 152 2 from Texa
118. eration Parallel C171 and C181 are loading capacitors Crystal load capacitance 12 20 30 pF 3 4 MHz 20 pF recommended 12 16 30 pF 6 8 MHz 16 pF recommended 12 16 16 pF 9 16 MHz 16 pF recommended 12 12 16 pF 16 24 MHz 12 pF recommended Crystal oscillator start up time 5 ms 3 6864 MHz 16 pF load 15 ms 7 3728 MHz 16 pF load 2 ms 16 MHz 16 pF load Output signal phase noise 85 dBc Hz At 100 kHz offset from carrier PLL lock time RX TX turn 200 us time PLL turn on time 250 us Table 10 Frequency synthesizer characteristics SWRS047 Page 11 of 152 SWRS047 Page 12 of 152 TEXAS TEXAS INSTRUMENTS INSTRUMENTS Chipcon Products from Texas Instruments 2071010 Chipcon Products 2 from Texas Instruments 61010 Pin Pin name Alternate Pin type Description 12 Pin Configuration function 13 CHP_OUT Analog output Charge pump current output when external m Top vie
119. ernal is that external RAM can only be accessed by a few instructions Therefore frequently accessed variables as well as the stack should be kept in internal RAM 15 2 Reset C1010 must be reset at start up There are several sources for reset 661010 External reset pin RESET Applying a low signal to this pin at any time will reset almost all registers in 227070 Exceptions can be found in Table 41 on page 144 The input is asynchronous and is synchronised internally so that the reset can be released independent of the timing of the active clock signal If the main crystal oscillator is inactive the reset input should be held long enough for the oscillator to start up and stabilize See Electrical Specifications page 7 for oscillator start up timing Power On Reset POR The internal POR module can generate reset upon power up Special requirements for power consumption or power supply voltage may require an external POR s INSTRUMENTS 61010 The various peripherals are controlled through Special Function Registers SFRs located in the internal RAM space The 8051 core is instruction set compatible with the industry standard 8051 It also has one additional instruction TRAP to enable advanced in circuit debugging features This is described on page 44 The instruction cycle time is 4 clock cycles which typically gives a 2 5X average reduction in instruction execution time over the original
120. eset value Description 7 PIDIR 7 RW 1 Port 1 direction register bit 0 to 7 Each bit sets the 6 PIDIR 6 RW 1 direction of the associated pin on Port 1 5 PIDIR 5 1 0 Associated pin is an output 4 PIDIR 4 RW 1 1 Associated pin is an input 3 PIDIR RW 1 2 PIDIR2 RW 1 1 PiDIR 1 RW 1 RW 1 TEXAS TRUMENTS SWRS047 Page 50 of 152 from Texas Instrumente 2071010 P2DIR 0xA6 Port 2 Direction Register Bit Name R W Reset value Description T P2DIR 7 R W 1 Port 2 direction register bit 0 to 7 Each bit sets the P2DIR 6 RW direction of the associated pin on Port 2 P2DIR 5 RW 0 Associated pin is an output PZDIR 4 RW 1 Associated pin is an input P2DIR 2 RW P2DIR RW o n e a o 1 1 1 P2DIR 3 1 1 1 1 P2DIR 0 RW P3DIR 0xA7 Port 3 Direction Register Bit Name R W Reset value Description 7 RO 0 Reserved read as 0 Reserved read as 0 P3DIR_5 RW Port 3 direction register bit 0 to 7 Each bit sets the P3DIR 4 RW direction of the associated pin on Port 3 P3DIR 3 RW 0 Associated pin is an output P3DIR 2 RW 1 Associated pin is an input P3DIR_1 RW n w fo P3DIR 0 RW Chipcon Products 2 from Texas Instruments 16 2 Timer 0 Timer 1 C1010 contains
121. et are available from Chipcon generating configuration data for any frequency giving optimum sensitivity Chipcon Products from Texas Instruments C1010 ISM Actual Crystal Low side Reference Frequency Frequency Frequency frequency frequency high divider word word MHz MHz MHz side REFDIV RX mode RX mode Lo decimal FREQ FREQ decimal hex 869 525 869 506000 3 6864 Low side 3 11583488 BOCO00 7 3728 6 11583488 BOCO00 11 0592 9 11583488 BOCO00 14 7456 12 11583488 BOCO00 18 4320 15 11583488 BOCO00 22 1184 18 11583488 BOCO00 869 85 869 860400 3 6864 High side 2 7725056 75 000 7 3728 4 7725056 75 000 11 0592 6 7725056 75 000 14 7456 8 7725056 75 000 18 4320 10 7725056 75 000 22 1184 12 7725056 75 000 915 915 018800 3 6864 High side 2 8126464 7C0000 7 3728 4 8126464 7C0000 11 0592 6 8126464 7C0000 14 7456 8 8126464 7C0000 18 4320 10 8126464 7C0000 22 1184 12 8126464 7C0000 ISM Actual Crystal Low side Reference Frequency Frequency Frequency frequency frequency high divider word word MHz MHz MHz side REFDIV RX mode RX mode Lo decimal FREQ FREQ decimal hex 315 315 3372 3 6864 low side 3 4194304 400000 7 37
122. for byte 4 to receive valid data as with the Read Program Memory instruction The lock bits can only be read through the SPI interface and not from the 8051 core 15 12 10 Read Signature Byte A 6 byte chip signature can be read through the SPI interface using the Read Signature Byte instruction The 3 bit TEXAS INSTRUMENTS 61010 signature byte address is issued and the value is then returned as byte 4 Signature byte address Value Meaing 000 Ox7F JEDEC manufacturer 001 Ox7F ID identifies Chipcon 010 Ox7F AS as the 011 Ox9E manufacturer 100 0x95 Identifies 32 kBytes of Flash memory 101 0x00 Identifies 227070 Table 19 Signature Bytes Wait at least 9 Txosc between the last negative transition on scK for byte 3 before issuing the first positive edge on SCK for byte 4 to receive valid data as with the Read Program Memory instruction 15 12 11 SPI Flash Programming Initialisation C1010 must be set into the Flash programming mode to allow SPI Flash operations This is done as follows e Apply power between all DVDD and DGND pins e Hold PROG low f a crystal is connected between XOSC 01 and XOSC 02 hold RESET low and wait for the oscillator to start up Crystal oscillator start up times are given in Table 10 Release RESET and wait at least 4 crystal oscillator periods e If a crystal is not connected between XOSC 01 and XOSC 02 hold RESE
123. ftware and a more accurate crystal will be recommended if required SWRS047 Page 32 of 152 Chipcon Products from Texas Instruments 61010 XOSC Q1 ni XOSC Q2 bd XTAL 7 Figure 4 Crystal oscillator circuit Item Ciz 12 pF C 20 pF C171 15 pF 30 pF C181 15 pF 30 pF Table 14 Crystal oscillator component values TEXAS INSTRUMENTS SWRS047 Page 33 of 152 Chipcon Products C from Texas Instruments 15 9 Power and Clock Modes Several power modes are defined to save power when running 667010 The modes are described below See also Table 15 15 9 1 Active Mode In active mode the 8051 is running normally executing instructions from the Flash program memory The clock used in this mode could either be the main crystal oscillator or it could be the 32 kHz oscillator The current consumption depends on the actual frequency used 15 9 2 Idle Mode After completing the instruction that sets the PCON IDLE bit Idle Mode is entered In Idle Mode the 8051 processing is stopped and internal registers maintain their current data but all peripherals are still running There are 3 ways to exit Idle Mode e Activate any enabled interrupt This clears the IDLE bit terminating Idle Mode and executes the ISR associated with the received interrupt The instruction at the end of the ISR causes the 8051 to return to the instruction following the
124. homepage This locati is di 5 8 memory software uses the RESERVED register locaton not used Dy the coge RESERVED 0xE7 Reserved register used by Chipcon debugger software Bit Name R W Reset value Description 7 0 RESERVED 7 0 R W 0x00 Reserved register which is used by Chipcon debugger software RESERVED may be used for other purposes if Chipcon s debugger software is not needed RDATA 0xB9 Replacement Data Bit Name R W Reset value Description 7 0 RDATA 7 0 R W 0x00 Replacement data Used to replace the byte at program memory address RADR with the data from RDATA if RADR gt 0 RADRH 0xBB Replacement address high byte Bit Name R W Reset value Description 7 0 RADR 15 8 RW 0x00 Replacement address high byte Used to replace the byte at program memory address RADR with the data from RDATA if RADR gt 0 RADRL 0xBA Replacement address low byte Bit Name R W Reset value Description 7 0 RADR 7 0 R W 0x00 Replacement address low byte Used to replace the byte at program memory address RADR with the data from RDATA if RADR 0 15 16 Chip Version Revision 667010 has a SFR register CHVER that can current revision The register description is be read to decide the chip type and shown below SWRS047 Page 45 of 152 SWRS047 Page 46 of 152 TEXAS TEXAS INSTRUMENTS INSTRUMENTS Chipcon Products Chipcon Products from Texas Instruments 201070 gt from Texas Instruments 2010
125. hopping applications the PLL calibration values may be read and stored for later use By reading back calibration values and frequency change can be done without doing a re calibration which could take up to 25 ms After a calibration is completed SWRS047 Page 113 of 152 Chipcon Products C from Texas Instruments the result of the calibration is stored in the TESTO VCO capacitance array setting and TEST2 Charge pump current setting registers The access of these registers depend on the RFMAIN F REG bit as there are two physical registers mapped to the same address one for frequency A and one for frequency B The calibration result can be read back from TESTO and TEST2 and later written back in 2071010 TEST5 VCO AO 3 0 and TEST5 CHP CO 4 0 respectively TEST5 VCO OVERRIDE and TEST6 CHP OVERRIDE must be set in order to make the override values to take effect The rest of the TESTn registers are not needed for normal operation of 227070 but are included here for completeness CAL 0xE5 PLL Calibration Control Register Bit Name Reset value Description 7 CAL_START RW 0 1 Calibration started 0 Calibration inactive Calibration is started after a positive transition on CAL START CAL START must manually be written to 0 after calibration is complete read the CAL COMPLETE flag 6 CAL DUAL RW 0 1 Store calibration in both A and B dual calibration 0 Store calibration in A or B defi
126. ificant bits of the external RAM address of the first byte to be encrypted decrypted The 3 least significant address bits are all zeros CRPCNT 0xC6 Encryption Decryption Counter Bit Name R W Reset value Description 7 0 CRPCNT 7 0 R W 0x00 CRPCNT 7 0 gives the number of bytes to be encrypted decrypted If CRPCNT 0 256 bytes are encrypted decrypted TEXAS INSTRUMENTS SWRS047 Page 77 of 152 Chipcon Products C from Texas Instruments CRPINIn ne 0 7 0xB4 0xB7 0xBC 0xBF DES Initialisation Vector 2071010 Bit Name R W Reset value Description 7 0 CRPINIn R W 0x00 7 0 The 8 registers CRPINIn n c 0 7 contains the 64 bit DES initialisation vector Bits 8 n 1 down to 8 n are located in register CRPINIn 16 10 Random Bit Generation LCIUIU can generate real random bit sequences to be used as encryption keys seed for a software pseudo random generator or other purposes The data is generated from amplifying noise in the RF receiver path To enable random bit generation set RANCON RANEN and clear RFMAIN RX PD Wait at least 1 ms before reading data from RANCON RANBIT The period between reads should be at least 10 us for the data to be as random as possible For applications requiring guaranteed DC free data software should process the generated data for example by xor ing two successive bi
127. ing the input block I of same length as using key as follows O Ex I encryption O Dxi I decryption The following is an example on how to use the single DES algorithm hardware in C1010 First the 56 bit encryption key must be stored in the external RAM Then the CRPKEY register must be written to point to the start of the encryption key Note that the encryption key must start on a RAM address location divisible by 8 Then the data bit stream to encrypt must be stored in the external RAM The data bit stream must consist of at least 1 byte up to a maximum of 256 bytes and it must also start on a RAM address location divisible by 8 The CRPDAT register must be written to point to the start of the data bit stream and CRPCNT must be written to give the number of bytes to be encrypted Then the CRPINIO CRPINI1 CRPINI2 CRPINI3 CRPINI4 CRPINI5 CRPINI6 CRPINI7 registers must be written to contain the DES initialisation vector used in the OFB and CFB modes of operation For simplicity it can be set to all zeros Note that the initialisation vector must be the same for both encryption and decryption to yield correct results To initiate the encryption the CRPCON register must be written The bits in this register select encryption decryption feedback mode SWRS047 Page 75 of 152 Chipcon Products from Texas Instruments and DES interrupt enable When the encryption has been completed CRPCON CRPEN goes low a
128. input from antenna external AC 41 DGND Power D Ground connection digital part coupling 42 P23 Digital high Z 8 8051 port 2 bit 3 5 RF OUT RF output RF signal output to antenna mA 6 AVDD Power supply LNA and PA 43 DVDD Power D Digital power supply T AGND Ground connection LNA PA 44 P2 4 Digital high Z VO 8051 port 2 bit 4 8 AGND Power A Ground connection PA 45 P2 5 Digital high Z 1 0 8051 port 2 bit 5 9 AGND Power A Ground connection VCO and prescaler 46 P32 NTO q Digital high Z 8051 port 3 bit 2 or interrupt 0 input 10 L1 Analog Connection 1 for external VCO tank uj configurable as level or edge sensitive inductor 47 P3 1 TXDO O Digital high Z 8051 port 3 bit 1 or TX of serial port 0 11 12 Analog Connection 2 for external VCO tank 48 P3 0 RXDO I Digital high Z 8051 port 3 bit 0 or RX of serial port 1 inductor 49 DGND Power D Digital ground connection 12 AVDD Power A Power supply VCO and prescaler 50 DVDD Power D Digital power supply SWRS047 Page 13 of 152 SWRS047 Page 14 of 152 TEXAS TEXAS INSTRUMENTS INSTRUMENTS Chipcon Products Chipcon Products from Texas Instruments 201070 from Texas Instruments 201070 Pin Pin name Alternate Pin type Description RBIAS output or IF output The pin is configured function ES Current output from internal band gap cell by the FREND register When not used this 51 P02 MI I Digi
129. interrupt pins cannot wake the 661010 from Power Down mode The parasitic capacitance is constituted by pin input capacitance and PCB stray capacitance Typically the total parasitic capacitance is 3 5pF A trimming capacitor may be placed across C171 for initial tuning if necessary The crystal oscillator is of an advanced amplitude regulated type A high current is used to start up the oscillations When the amplitude builds up the current is reduced to what is necessary to maintain a 600 mVpp amplitude This ensures a fast start up keeps the current consumption and the drive level to a minimum and makes the oscillator insensitive to ESR variations As long as you follow the crystal loading capacitance requirements do not worry about ESR or drive levels a typical drive level is 4 uW for 3 MHz The main crystal oscillator circuit is shown in Figure 4 Typical component values for different values of C are given in Table 14 Recommended load capacitance versus frequency is given in Table 10 on page 12 The initial tolerance temperature drift ageing and load pulling should be carefully specified in order to meet the required frequency accuracy in certain application By specifying the total expected frequency accuracy in SmartRF Studio together with data rate and frequency separation the software will calculate the total bandwidth and compare to the available IF bandwidth Any contradictions will be reported by the so
130. ion register P3DIR controls whether each pin is an output or input The register P3 is used to read the input or control the logical value of the output SWRS047 Page 16 of 152 Chipcon Products from Texas Instruments Pins P3 0 and P3 1 can be configured to become the RXDO and TXDO pin respectively of UART 0 Pins P3 2 and P3 3 are connected to the external interrupt inputs INTO and INT1 respectively and can cause interrupts if the corresponding interrupt enable flags are set in register IE The interrupts inputs TEXAS INSTRUMENTS 61010 can be configured to be either level sensitive or edge sensitive Pins P3 4 and P3 5 can be configured to become the pulse width modulator PWM outputs of Timer PWM 2 and Timer PWM 3 respectively When pulse width modulation is enabled the corresponding bits in P3DIR and P3 are overridden SWRS047 Page 17 of 152 Chipcon Products from Texas Instruments 14 Block Diagram 01010 The 207010 Block Diagram is shown Figure 2 below Programmable General purpose or alternate function Port 0 Port2 poem DES Module reset Hn x E EEE A FLASH
131. ip Erase instruction If multiple Write Lock Bits instructions are issued without chip erase in between each lock bit will be AND ed together with the previously written lock bits In effect this means that it is not possible to unlock the Flash program memory without also erasing it The effect of the different lock size bits are illustrated in Figure 6 SWRS047 Page 40 of 152 Chipcon Products from Texas Instruments E s 8 5 eee Ta 8 Hee RAR A 3 g 9 99999939 OXTFFF yg um 254 n 253 eB 252 M S 28 BH 250 S E 248 0x7C00 is H 246 242 n P 6 240 oxre00 349 BH 238 a 9 lo ox7000 224 B 8 77223 e H M E 222 9 B B re B5 193 al E 192 192 HB 190 Bi z E B 129 e E cono 728 LB 127 B 9 126 E 2 2 5 00000 0 is locked when BBLOCK is cleared Figure 6 Flash Lock Bits illustration 15 12 9 Read Lock Bits The lock bits described in the previous section can be read through the SPI interface by using the Read Lock Bits instruction The instruction will return the 8 lock bits in byte 4 of the instruction Wait at least 9 Txosc between the last negative transition on SCK for byte 3 before issuing the first positive edge on SCK
132. ipcon web site 15 12 Serial Programming Algorithm When writing serial data to the SPI interface data is clocked at the rising edge of SCK When reading data from the SPI interface data is clocked at the falling edge of SCK see Figure 5 1 Apply power between and DGND while SCK is set to 0 If a crystal is not connected between XOSC Q1 and XOSC 02 apply a clock signal to the XOSC Q1 pin 2 Give RESET a negative pulse of at least one XOSC period TEXAS INSTRUMENTS 2071010 others It can also prevent parts of the Flash memory from being modified by software such as a boot loader that should remain unchanged Other parts of the Flash may still be updated by the boot loader For the security of the Flash protection please refer to the disclaimer at the end of this document Erasing a Flash page takes 10 20 ms depending on the FLTIM register Writing to a Flash page takes 5 10 ms 3 Set PROG low 4 Send the Programming Enable command Check that the slave is synchronised by verifying that the second byte of the instruction is echoed back when issuing the third byte If the second byte did not echo issue a positive pulse on SCK and try again In the worst case it will take 32 attempts to synchronise 5 Send the Set Write Cycle Time command according to the device clock oscillator frequency c 16 clock period must be between 20 40us for safe flash programming 6 Ifa chip erase is perform
133. ircuit It is important to place the inductor as close to the pins as possible in order to reduce stray inductance It is recommended to use a high Q low tolerance inductor for best performance 17 16 VCO and PLL self calibration To compensate for supply voltage temperature and process variations the VCO and PLL must be calibrated The calibration is done automatically and sets optimum VCO tuning range and optimum charge pump current for PLL stability The calibration is controlled by using the CAL register After setting up the device at the operating frequency the TEST6 register must be programmed depend on operation mode Then the self calibration is initiated by setting the CAL CAL START bit The calibration result is stored internally in the chip and is valid as long as power is not turned off If large supply voltage variations than 0 5 V temperature variations more than 40 degrees occur after calibration a new calibration should be performed For more details on the calibration data see the description for test and calibration registers page 128 When CAL CAL WAIT 1 the calibration is complete and the CAL CAL_COMPLETE flag is set after 25650 reference clock cycles frer see the Frequency programming section at page 106 The user can poll this bit or simply wait 25650 reference clock cycles The lowest permitted reference frequency 1 MHz gives a wait time of 25 65 ms which is the worst case
134. k mode 1 WDT WDTPRE 1 0 The divided clock controls an 8 bit timer which generates System reset upon overflow A block diagram for the Watchdog Timer is shown in Figure 14 Note that the watchdog timer is not active in Power down mode and therefore cannot wake up the 667010 from Power Down mode WDT 0xD2 Watchdog Timer Control Register Bit Name R W Reset value Description 7 x RO 0 Reserved read as 0 6 0 Reserved read as 0 5 RO 0 Reserved read as 0 4 WDTSE RW 0 Watchdog Timer Stop Enable used to disable the watchdog timer 3 WDTEN RW 1 Watchdog Timer Enable Disable 0 The watchdog timer is disabled 1 The watchdog timer is enabled The watchdog timer is enabled after reset To disable the watchdog timer WDTSE must be used as described in this section 2 WDTCLR RO 0 Watchdog timer clear signal WOTCLR must periodically Ww be set to prevent the watchdog timer from resetting the system WDTCLR is cleared by hardware and is thus always read 0 0 Normal watchdog operation 1 Watchdog timer is cleared 1 0 WDTPRE 1 RW 11 Watchdog timer prescaler control WDTPRE 1 0 controls the division of the main crystal oscillator clock to generate the watchdog timer clock 00 fwpr fxosc 2048 01 fwor fxosc 4096 10 fwor fxosc 8192 11 fxosc 16384 SWRS047 Page 63 of 152 TEXAS INSTRUMENTS
135. l 0 XOSC_Q2 should be left open not PODIR 2 and PODIR 1 62 AD1 Analog input ADC input channel 1 connected i 63 AD2 RSSI O Analog input output ADC input channel 2 RSSI Receiver signal KOC DI XOSCUS QD Used d os ping SCK IF O strength indicator output or IF output when So 16 i using external demodulator These are the real time clock RTC PORT 1 64 AGND Analog ground connection oscillator connection pins An external Port 1 is an 8 bit P1 7 P1 0 bi Analog D Digital input O Output 13 Pin description AVDD DVDD matched to the input impedance A DC crystal should be connected between these pins and load capacitors should be connected between each pin and ground If an external oscillator is used the clock signal should be connected to the XOSC32_Q1 pin and XOSC32_Q2 should be left open not connected Supply voltages for analog and digital modules respectively All supply pins should be decoupled by capacitors In particular the digital and analog supply domains should be properly decoupled from each other a ferrite bead can be used to prevent high frequency noise from coupling from one supply domain to another The placement and size of decoupling capacitors and supply filtering are critical with respect to LO leakage and sensitivity Chipcon s reference layout designs should be used available from Chipcon s websit
136. l function 1 Charge Pump is disabled 4 VCO OVERRIDE RW 0 VCO array override 0 VCO array is not overridden normal function 1 VCO array is set by VCO AO 3 0 3 0 AO 3 0 R W 0x08 VCO Array override value TESTA 0xFD PLL Test Register 4 Bit Name R W Reset value Description 7 6 R W 0x00 Reserved read as 0 5 0 L2KIO R W 0x25 Constant charge pump current scaling rounding factor Sets bandwidth of PLL Default value is 0x25 and shall be used for all modes TEST3 0xFC PLL Test Register 3 Bit Name Reset value Description T5 RO 0x00 Reserved read as 0 4 BREAK_LOOP RW 0 Break frequency synthesis PLL 0 PLL loop closed normal operation 1 PLL loop open 3 0 CAL_DAC_OPEN RW 100 Calibration DAC override value active when 3 0 BREAK LOOP is set TEST2 0xFB PLL Test Register 2 Bit Name R W Reset value Description T4 RO 0x00 Reserved read as 0 4 0 CHP_CURRENT R None Status vector defining the applied charge pump 4 0 current TEST1 0xFA PLL Test Register 1 Bit Name R W Reset value Description TA RO 0x00 Reserved read as 0 3 0 3 0 R None Status vector defining the applied calibration DAC value TESTO 0xF9 PLL Test Register 0 Bit Name R W Reset value Description 0x00 Reserved read as 0
137. l sensitive mode software cannot write to IE1 2 ITl RW 0 External interrupt 1 type select 0 The INT1 interruptis triggered when INT1 is low level sensitive 1 The INTI interrupt is triggered on the falling edge edge sensitive 1 R WO 0 External interrupt 0 edge detect interrupt flag If external interrupt 0 is configured to be edge sensitive TCON ITO 1 is set by hardware when a negative edge is detected on the INTO pin and is cleared by hardware when the 8051 vectors to the corresponding interrupt service routine In edge sensitive mode IEO can also be set by software If external interrupt 0 is configured to be level sensitive TCON ITO 0 is set when the INTO is low and cleared when the INTO is high In level sensitive mode software cannot write to IEO 0 ITO RW 0 External interrupt 0 type select 0 The INTO interruptis triggered when INTO is low level sensitive 1 The INTO interrupt is triggered the falling edge edge sensitive SWRS047 Page 53 of 152 SWRS047 Page 54 of 152 TEXAS TEXAS INSTRUMENTS INSTRUMENTS Chipcon Products Chipcon Products from Texas Instruments 201070 from Texas Instruments 201070 CKCON 0x8E Timer Clock rate Control Register R Dmdeby 12 40 system Ck Bit Name RIW Resetvalue Description 77 Nom
138. llows e 13 bit timer counter Mode 0 TEXAS TRUMENTS e 16 bit timer counter Mode 1 e 8 bittimer counter with auto reload Mode 2 e Two 8 bit timers counters Mode 3 Timer 0 only See the register descriptions for TMOD and TCON on the following pages SWRS047 Page 52 of 152 Chipcon Products from Texas Instruments 2071010 TMOD 0x89 Timer Counter 0 and 1 Mode register Bit Name R W Resetvalue Description GATEl RW 0 0 Timer Counter 1 gate control imer Counter 1 will clock only when TCON TR1 is set 1 Timer Counter 1 will clock only when TCON TR1 is set andthe INTO inputis high c T1 RW 0 Counter Timer select for Counter Timer 1 0 Timer 1 is clocked by the system clock divided by 4 or 12 depending on the state of CKCON T1M see page 55 1 Timer 1 is clocked by the T1 pin 10 Timer Counter 1 mode select bits 4 M1 0 RW 0 00 13 bit counter 01 16 bit counter bit counter with auto reload 11 Timer 1 off 3 GATEO RW O Timer Counter 0 gate control 0 Timer Counter 0 will clock only when TCON TRO is set 1 Timer Counter 0 will clock only when TCON TRO is set andthe INTO inputis high 2 RW 0 Counter Timer select for Counter Timer 0 0 Timer 0 is clocked by the system clock divided by 4 or 12 depending on the state of CKCON TOM see page 55 1 Timer 0 is clocked by the TO
139. lock can be applied to the XOSC32 01 pin after setting the X32CON X32 BYPASS bit After 2 to 3 clock periods on the 32 768 kHz oscillator a glitch free transition has been made from the main crystal oscillator to the 32 768 kHz oscillator If desired the main crystal oscillator can then be set in power down to save more power by setting RFMAIN CORE PD and RFMAIN BIAS PD This has the disadvantage that a later transition from TEXAS INSTRUMENTS Clock Mode 1 to Clock Mode 0 will require the main crystal oscillator to be powered up again Since the Flash program memory draws a static current Idle Mode together with Flash Power Control see page 44 should be applied for maximum power saving in Clock Mode 1 The RF receiver cannot be activated in Clock Mode 1 15 9 6 Entering Clock Mode 0 from Clock Mode 1 To enter Clock Mode 0 from Clock Mode 1 the main crystal oscillator must first be set in power up if powered down This requires clearing RFMAIN CORE PD and RFMAIN BIAS PD and then waiting at least 5 ms depend on main oscillator frequency see Electrical Specifications page 7 If the oscillator is already powered up no waiting is required Clearing X32CON CMODE will then cause glitch free transition from Clock Mode 1 to Clock Mode 0 after 2 to 3 clock periods on the main crystal oscillator 15 9 7 Flash Power Control The Flash program memory current consumption can be controlled as described in the Fl
140. minimum time SCK must be held low Tsck rise Txosc 2 ns The maximum rise time on SCK Tsck fall Txosc 2 ns The maximum fall time on SCK Tsi setup Txosc The minimum setup time for SI before the positive edge on SCK Tsi hold Txosc The minimum hold time for SI after the positive edge on SCK Tso delay Txosc The delay from the negative edge on SCK to valid data on SO Table 17 SPI Flash Programming Timing Parameters 15 12 2 Programming Enable Programming Enable is always the first instruction to be sent It must be sent to synchronise the data flow and enable 667010 to receive further instructions Synchronisation is achieved when byte 2 of the instruction 0x53 is echoed back from the SPI interface as byte 3 If synchronisation is not achieved byte 3 will return all zeros In this case an extra clock pulse should be inserted on SCK and the Programming Enable instruction should be resent If synchronisation is not successful within 32 attempts Programming Enable is unsuccessful and further debugging is needed 15 12 3 Set Flash Timing The Set Flash Timing instruction is needed to generate internal timing for the Flash module FLTIM must be set in instruction byte 4 so that s INSTRUMENTS disces dide 0 8MHz 0 4 MHz It is recommended to set FLTIM to the smallest number satisfying the equation above to reduce the time needed for Flash programming For a 3 6864 MHz crystal FLT
141. mode and Synchronous Manchester encoded mode transmit or receive data using a baudrate as specified in MODEMO BAUDRATE The modem does resynchronisation of the bit stream during reception In the Manchester mode the modem also does the Manchester encoding and decoding The NRZ and Manchester modes accept and deliver data either one bit or one byte at a time programmable through RFCON BYTEMODE In most applications these two modes are recommended Data to be transmitted or data received are stored in the RFBUF register During transmission or reception the need for more data or the arrival of new data bit by bit or byte by byte depending on RFCON BYTEMODE is signaled by generating an interrupt EXIF RFIF Depending on whether the RF interrupt is enabled or not EIE RFIE transmission or reception can be handled by an interrupt service routine or be performed by polling During reception when using NRZ or Manchester mode hardware preamble and start of frame detection can optionally be activated using the registers PDET and BSYNC This is described the TEXAS INSTRUMENTS 2071010 Synchronization and preamble detection section on page 102 Two other modes Transparent mode and UART mode simply passes data between the FSK modem and the RFBUF register and UARTO respectively allowing custom baud rates and data encoding When using the UARTO in the UART mode the pin P3 1 is not used for UART output and can instea
142. n 868 MHz SWRS047 Page 124 of 152 TEXAS TRUMENTS Chipcon Products from Texas Instruments 2071010 PA POW 0xE2 PA Output Power Control Register Bit Name R W Resetvalue Description 7 4 PA HIGHPOWER R W 0x00 Control of output power in high power array 3 0 Should be 0000 in PD mode See Table 37 for details 3 0 LOWPOWER R W 3 0 Control of output power in low power array Should be 0000 in PD mode See Table 37 for details TEXAS INSTRUMENTS SWRS047 Page 125 of 152 Chipcon Products C from Texas Instruments 17 20 RSSI Output has a built in RSSI Received Signal Strength Indicator giving an analog output signal at the AD2 RSSI IF pin RSSI is enabled when setting FREND RSSI see 119 The output current of this pin is then inversely proportional to the input signal level The output should be terminated in a resistor to convert the current output into a voltage A capacitor is used to low pass filter the signal The RSSI voltage range is from 0 1 2 V when using a 27 kQ terminating resistor giving approximately 50 dB V This RSSI voltage can be measured by the on chip A D converter using the AD2 input Note that a higher voltage means a lower input signal 20101 AD2 RSSI IF 4 C281 R281 Figure 41 RSSI circuit TEXAS INSTRUM
143. n added to the 8051 s instruction set The instruction given the mnemonic TRAP is a single byte instruction with the opcode OxA5 In the original 8051 the OxA5 opcode is executed as a NOP instruction opcode 0x00 In the modified core this instruction raises a highest level interrupt Flash Debug by setting the corresponding interrupt flag EICON FDIF and waiting sufficient number of instruction cycles to allow the interrupt to take effect before the next instruction The TRAP instruction can thus be written over the first byte opcode of any other instruction the execution of which then will result in a branch to a software debugging monitor in the highest priority interrupt service routine Single stepping through instructions 15 supported since exactly one instruction is executed if an interrupt condition exists when returning from an interrupt service routine Thus single stepping can be accomplished simply by not clearing the corresponding interrupt flag in the interrupt service routine associated with the software monitor TEXAS INSTRUMENTS operating conditions However to save power the Flash module can be set in a power down mode between instructions in Active mode and always in Idle or Power Down mode This will save approximately 1 5 mA of the Flash current consumption during operation in Active mode and 2 5 mA during Idle or Power Down mode A second serial port has been added to enable debugging
144. n order to reduce LO leakage Due to this the VCO inductor is placed at the reverse side of the PCB A development kit with a fully assembled PCB is available and can be used as a guideline for layout Full documentation and Gerber PCB layout files are available on Chipcon s web site antennas tend to be more difficult to optimise than the simple monopole Loop antennas are easy to integrate into the PCB but are less effective due to difficult impedance matching because of their very low radiation resistance if they are made small For low power applications the 2 4 monopole antenna is recommended giving the best range and because of its simplicity The length of the 4 4 monopole antenna is given by L 7125 f where f is in MHz giving the length in cm An antenna for 869 MHz should be 8 2 cm and 16 4 cm for 434 MHz The antenna should be connected as close as possible to the IC If the antenna SWRS047 Page 133 of 152 Chipcon Products from Texas Instruments is located away from the input pin the antenna should be matched to the feeding transmission line 50 Q TEXAS INSTRUMENTS 2071010 For more thorough primer on antennas please refer to Application Note SRD Antennas available on Chipcon s web site SWRS047 Page 134 of 152 Chipcon Products from Texas Instruments 20 Package Description TQFP 64 001010 201010 is packaged TQFP 64 package The package is
145. nd store the last bit into RFBUF 0 which in turn generates a RF interrupt request so that the new bit can be read In order to be able to read the next bit from RFBUF 0 within one bit period at high baud rates it is advisable to use a tight polling loop instead of an interrupt based receive procedure No special considerations have to be taken at the start of or end of receptions SWRS047 Page 96 of 152 Chipcon Products from Texas Instruments 17 9 Demodulation and data decision A block diagram of the digital demodulator is shown in Figure 25 The IF signal is sampled and its instantaneous frequency is detected The result is decimated and filtered In the data slicer the data filter output is compared to the average filter output to generate the data output The averaging filter is used to find the average value of the incoming data While the averaging filter is running and acquiring samples it is important that the number of high and low bits received is 2071010 transceiver will be switched away from receive mode as soon as it is determined that no data is present If the averaging filter is locked MODEM1 LOCK_AVG_MODE 1 the acquired value will be kept also after Power Down or Transmit mode After a modem reset MODEMI MODEM RESET or a main reset using any of the standard reset sources the averaging filter is reset Chipcon Products C from Texas Instruments where
146. nd the DES interrupt flag is set The external RAM will now contain the encrypted data bit stream 2071010 in the same location as the input data bytes were originally put To perform the reverse operation write CRPCON again with the CRPCON ENCDEC bit set Key First RAM Location Last RAM Location Ky 8 CRPKEY 8 CRPKEY 6 Table 24 DES key location in RAM Encryption decryption is done in place i e each byte of data read from external RAM for encryption decryption will be written back to the same location after encryption decryption as described above The input and output blocks must start on an address which is a multiple of eight CRPDAT then gives the 8 most significant address bits to the first data byte The encryption decryption initialization vector should be written to registers CRPINIO to CRPINI7 These registers must be written prior to encrypting decrypting a new block of data as they are modified by hardware They should be left unchanged between multiple encryption decryption operations for DES blocks larger than 256 bytes A zero value initialisation vector can be used or additional security can be effected by using the initialisation vector as an additional key Encryption decryption is started when CRPCON CRPEN jis set When the encryption decryption is completed CRPCON CRPEN is cleared by hardware and the interrupt flag CRPCON CRPIF is set If
147. ned by RFMAIN F REG 5 CAL WAIT RW 0 1 Normal Calibration Wait Time Recommended 0 Half Calibration Wait Time The calibration time is proportional to the internal reference frequency frer See the main text CAL CURRENT 0 1 Calibration Current Doubled 0 Normal Calibration Current Recommended 3 CAL COMPLETE R 0 Status bit which is set when the calibration is complete 2 0 CAL ITERATE RW 101 Iteration start value for calibration DAC 000 101 Not used lormal start value TEST6 0xFF PLL Test Register 6 Name R W Reset value Description 7 LOOPFILTER_TP1 RW 0 Testpoint 1 select 0 CHP_OUT tied to GND 1 Select testpoint 1 to CHP OUT 6 LOOPFILTER TP2 RW 0 Testpoint 2 select 0 CHP_OUT tied to GND 1 Select testpoint 2 to CHP OUT 5 CHP_OVERRIDE RW 0 Charge pump current override enable 0 use calibrated value Used in RX mode 1 use CHP CO 4 0 value Used in TX mode 4 0 CHP_CO 4 0 R W 0x10 Charge pump current DAC override value applied when CHP_OVERRIDE is high Use Ox1B in TX mode SWRS047 Page 114 of 152 TEXAS INSTRUMENTS Chipcon Products from Texas Instruments TESTS5 0xFE PLL Test Register 5 2071010 Bit Name R W Reset value Description T6 RO 0x00 Reserved read as 0 5 CHP_DISABLE RW 0 PLL Charge Pump disable 0 Charge Pump is enabled norma
148. ned in Mode 0 and should be masked by software for evaluation In Mode 0 the timer timeout period is determined by 12 8 CKCON TxM Y8192 THx TLx S rose where THx TLx is the contents of the THx TLx registers if this is reloaded in the interrupt handler or 0 if no reload is done T mori gt Ree ceareo cares m INTO NT Timer 0 Timer 1 WA interrupt request Figure 8 Mode 0 and Mode 1 operation for Timer Counter 0 or 1 16 2 23 1 16 24 Mode 2 Mode 1 operation is illustrated for Timer Mode 2 operation is illustrated for Timer Counter 0 and 1 in Figure 8 The counter Counter 0 and 1 in Figure 9 Mode 2 is configured as a 16 bit counter as operates as 8 bit counter with compared to the 13 bits in Mode 0 and all automatic reload of the start value bits in TLO or TL1 are thus used The The Timer Counter is controlled as for fone the count Mode 0 and Mode 1 but when TLO TL1 a overflows THO TH1 is loaded into TLO Otherwise Mode 1 operation is the same TL1 as Mode 0 In Mode 2 the timer timeout period is In Mode 1 the timer timeout period is determined by determined by _ 12 8 256 THx 12 8 TxM 65536 THx TLx Jose deasserted SWRS047 TEXAS INSTRUMENTS Page 55 of 152 where THx TLx is the contents of the THx TL
149. ng of the PWM outputs is nhPWM Tien illustrated in Figure 12 Trew Tapwm PWMn Output TohPwM i TohPwM Figure 12 PWM Timing illustration Timer 2 or Timer 3 Divide by 8 bit counter System Cik TnPRE 1 counts 0 254 A PWM output A gt B TnPWM B Figure 13 PWM operation for Timer 2 Timer 3 SWRSO047 Page 61 of 152 TEXAS INSTRUMENTS Chipcon Products C from Texas Instruments 16 4 Power On Reset Brown Out Detection The Power On Reset functionality detects power on and brown out situations and includes glitch immunity and hysteresis for noise and transient stability The power on reset functionality 15 disabled using the dedicated POR E pin Grounding POR E will disable the internal power on reset An external power on TEXAS INSTRUMENTS 2071010 reset module should then be connected to the external RESET pin The Power On Reset and Brown Out Detection voltage levels are specified in the Electrical Specifications section at page 7 SWRS047 Page 62 of 152 from Taxas Instruments 2071010 16 5 Watchdog Timer 7070 includes an 8 bit watchdog timer Chipcon recommends that the watchdog that is clocked by the system clock The timer should be disabled when the 667010 clock is divided by a number in the range is clocked from the 32 kHz oscillator from 2048 to 16384 controllable through Cloc
150. nitial division in Timer 1 between 4 and 12 Some example baud rates and reload values are shown in Table 23 The setting for other baud rates and oscillator frequencies can be determined by using the above equation To transmit data in mode 1 write data to SBUFO SBUF1 Transmission is then performed on TXD1 in the following order start bit 8 data bits LSB first and then the stop bit Reception begins on the falling edge of a start bit received on RXDO RXDI if reception is enabled in SCONO REN 0 SCON1 REN_1 The data input is sampled 16 times per baud for any baud rate Each bit decision is performed as a majority decision between 3 successive samples in the middle of each baud If the majority decision is not equal to zero for the start bit the serial port will stop reception and wait for a new start bit When the majority decision is made for the stop bit the following conditions must be met RI_0 RI_1is0 e If SM2_0 SM2 1is set the state of the stop bit must be one If these conditions are met the received data is buffered in SBUFO SBUF1 the SWRS047 Page 69 of 152 Chipcon Products from Texas Instruments received stop bit is stored in RB8 0 8 1 and the receive interrupt flag is set If not the received data is lost and RB8 0 RBB8 1 and the receive interrupt flag remains unchanged 16 7 3 MODE2 Mode 2 provides asynchronous full duplex communication using a total of 11
151. oducts from Texas Instruments while WDT 0x08 WDT 0x10 Set WDTSE WDT amp 0x08 Clear WDTEN 16 6 Real time Clock The real time clock can generate interrupts with intervals ranging from 1 to 127 seconds It is connected to the 32 768 kHz crystal oscillator which is disabled after reset It must be enabled as described in the section on page 33 An external 32 768 kHz clock signal can also be applied as described The interrupt interval is programmed in the range from 1 through 127 seconds by setting RTCON RT 6 0 The timer is 2071010 16 5 2 Enabling the Watchdog Timer Enabling the Watchdog Timer is simply done by setting WDT WDTEN Using the WDT WDTSE control bit is not required enabled by setting RTCON RTEN The first interrupt will be generated RT seconds after RTEN is set The real time clock interrupt must be enabled as described in the Interrupts section on page 28 The RTC oscillator circuit is shown in Figure 15 The loading capacitors values can be calculated as described for the main crystal oscillator at page 32 Chipcon Products C from Texas Instruments 16 7 Serial Port 0 and 1 Two serial ports serial port 0 and 1 are implemented They are controlled through the SCONO and SCON1 control register The data is buffered in SBUFO and SBUF1 Serial port 0 may be used for general purpose serial communication Timer 1 may be used
152. ol bit The frequency word FREQ is 24 bits 3 bytes located in FREQ 2A FREQ 1A FREQ 0A and TEXAS INSTRUMENTS FREQ 2 1B FREQ OB for the A and B word respectively The FSK frequency separation two times the deviation FSEP is programmed in the FSEP1 FSEPO registers 11 bits The frequency word FREQ can be calculated from FREQ FSEP 8192 16384 where TXDATA is 0 or 1 in transmit mode depending on the data bit to be transmitted In receive mode TXDATA is always 0 fu The reference frequency frer is the crystal oscillator clock divided by PLL REFDIV a SWRS047 Page 107 of 152 Chipcon Products from Texas Instruments number between 2 and 24 that should be chosen such that 1 00 MHz lt fret lt 2 40 MHz Thus the reference frequency frer is jp Im 7 REFDIV fvco is the Local Oscillator LO frequency in receive mode and the f frequency in transmit mode lower FSK frequency The LO frequency must be far fir giving low side or high side LO injection respectively Note that the data in RFBUF will be inverted if high side LO is used Please also note that depends on the RF frequency 150 and 130 kHz for 433 and 868 MHz respectively The upper FSK transmit frequency is given by fim fo where the frequency separation fsep is set by the 11 bit separation FSEP1 FSEPO FSEP 16384
153. old for determining what constitutes a Manchester coding violation can be configured in RFCON MLIMIT RFCON MVIOL is set when in bitmode the currently available bit in RFBUF 0 was determined to violate Manchester coding or in bytemode when one or more of the bits in the byte currently available in RFBUF were determined to violate the Manchester coding This can be used for example to detect start of frame and end of frame delimiter bytes Note that even if RFCON MVIOL is set when receiving data RFBUF will still be set to the best guess data received In applications where no Manchester violations are transmitted it is therefore advisable to ignore RFCON MVIOL at reception In order to be able to send Manchester violations MODEMO DATA FORMAT must CCT be changed to NRZ mode for the byte in question When in NRZ mode two bytes must be sent for each Manchester coded byte A flagrant violation of Manchester coding could be for example the two byte sequence 11001100 00110011 In order to provide this functionality MODEMO DATA FORMAT is buffered in much the same way as data so that the change does not take effect until the following byte During transmission the desired data format should be updated in connection with writing new data to RFBUF The byte currently being transmitted from the shift register will not be affected It is then possible to have a NRZ preamble pattern with Manchester data following Thi
154. onents keep the total cost at a minimum The oscillator crystal can then be a low cost crystal with 50 25 ppm frequency tolerance at 433 868 MHz respectively 19 3 Battery operated systems In low power applications the RF Transceiver power down mode should be used when no communication takes place Using receiver polling that is listening for transmissions for a few milliseconds at regular intervals will also save a lot of battery power The RSSI can be used as a first indication that a transmission is received See page 89 for information on how effective power management can be implemented Utilizing the Idle mode and Power down modes and clock modes of the MCU will also reduce the power consumption significantly See page 33 for details Also of interest is Application Note 17 Low Power Systems Using the CC1010 available on Chipcon s web site TEXAS INSTRUMENTS 19 4 Narrow band systems C6400 2900 and 21020 recommended for best performance in narrow band applications The phase noise of these chips is superior and for systems with 25 kHz channel spacing or less with strict requirements to ACP Adjacent Channel Power low phase noise is important The selectivity of 227010 can be improved by using an external ceramic filter and demodulator at 10 7 MHz Such ceramic filters are typically 180 or 280 kHz wide A unique feature 207010 is the very fine frequency resolution of 250 Hz This can
155. ons Through the SFR registers the following key parameters can be programmed e Receive transmit mode RF output power Frequency synthesiser key parameters RF output frequency FSK frequency separation deviation crystal oscillator reference frequency e Power down power up mode Data rate and data format NRZ Manchester coded Transparent or UART interface Synthesiser lock indicator mode Optional RSSI or external IF output 61010 174 1 SmartRF Studio Chipcon provides users of 227010 with a Windows application SmartRF Studio which generates all necessary 661010 RF configuration settings based on the user s selections of various parameters These SFR register settings can be used in a 61010 program to configure the RF In addition SmartRF Studio will provide the user with the component values needed for the input output matching circuit and the VCO inductor Chipcon recommends using the register settings found using the SmartRF Studio software These are the register settings that Chipcon can guarantee across temperature voltage and process Please visit the Chipcon web site regularly for updates to the SmartRF Studio software or subscribe to the Chipcon Developers Newsletter to be notified of updates Figure 21 shows the user interface of SmartRF Studio 94 Figure 21 SmartRF Studio TEXAS INSTRUMENTS SWRS047 Page 88 of 152 Chipcon Products f
156. owing frequency e In circuit interactive debugging is hopping protocols supported for the Keil uVision2 IDE RSSI through a simple serial interface EN 300 220 and FCC CFR47 part 2 7 3 6 V supply voltage 15 compliant 64 lead SWRS047 Page 1 of 152 Chipcon Products from Texas Instruments Table Of Contents 10 IF SECTION FREQUENCY SYNTHESIZER SECTION 12 PIN CONFIGURATION 13 PIN DESCRIPTION 14 BLOCK DIAGRAM 15 8051 CORE 16 8051 PERIPHERALS 17 RF TRANSCEIVER 9ouonmRONBI FEATURES ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITION DC CHARACTERISTICS ELECTRICAL SPECIFICATIONS ADC RF SI RF TRANSMIT SECTION RF RECEIVE SECTION 15 1 GENERAL DESCRIPTION 15 3 Memory 15 4 CPU REGISTERS 15 5 INSTRUCTION SET SUMMARY 15 6 INTERRUPTS 15 7 EXTERNAL INTERRUPT 15 8 MAIN CRYSTAL OSCILLATOI 15 9 POWER AND CLOCK 15 10 FLASH PROGRAM MEMORY 15 11 SPI FLASH PROGRAMMING 15 12 SERIAL PROGRAMMING ALGORITHM 15 13 8051 FLASH PROGRAMMING 15 14 FLASH POWER CONTROL 15 15 IN CIRCUIT DEBUGGING 15 16 CHIP VERSION REVISION 16 1 GENERAL PURPOSE 16 2 TIMER 0 TIMER 1 16 3 TIMER 2 3 WITH P 16 4 POWER ON RESET BROWN OUT DETECTION 16 5 WATCHDOG TIMER 16 6 REAL TIME CLOCK 16 7 SERIAL PORT 0 AND 1 16 8 SPI MASTER 16 9 DES ENCRYPTION DECRYPTION 16 10 1641 RANDOM BIT GENE
157. power consumption of the CC1010 can be found in Application Note ANO17 Low Power Systems Using The CC1010 SWRS047 Page 34 of 152 Chipcon Products from Texas Instruments 2071010 Peripherals Typical current Exit condition consumption Main osc Main osc 14 8 mA at Writing SFR Active 14 7456 MHz RTC osc RTC osc 1 3mA Writing SFR 32kHz _ 32 kHz Stopped Main osc 12 8 mA at Interrupt 14 7456 MHz Reset Idle Stopped RTC osc 29 4 uA Power off on 32 kHz ADC Off Stopped ADC On 200 uA ADC value exceeds threshold 32 kHz Reset Power Down Power off on Stopped Stopped 0 2uA Reset Power off on Note 1 Flash duty cycle reduction is used for all modes Table 15 Operating modes summary 15 9 4 Clock Modes The 8051 and its peripherals can be run on both the main crystal oscillator Clock Mode 0 and the 32 768 kHz oscillator Clock Mode 1 The clock mode is set in X32CON CMODE 15 9 5 Entering Clock Mode 1 from Clock Mode 0 After reset the 8051 and its peripherals are running on the main crystal oscillator and the 32 768 kHz oscillator is in power down To enter Clock Mode 1 the 32 768 kHz oscillator must first be powered up This requires clearing X32CON X32 PD and then waiting at least 160 ms after which X32CON can be set to enter Clock Mode 1 If an external 32 768 kHz clock source is already available in the system this c
158. pport appliances devices or other systems where malfunction can reasonably be expected to result in significant personal injury to the user or as a critical component in any life SWRS047 Page 150 of 152 Sos UMENTS from Taxas instruments 61010 support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness Chipcon AS customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Chipcon AS for any damages resulting from any improper use or sale 2003 2004 Chipcon AS All rights reserved SWRS047 Page 151 of 152 TEXAS INSTRUMENTS from Taxas lestrumente 01010 32 Address Information Web site http www chipcon com E mail wireless chipcon com Technical Support Email support chipcon com Technical Support Hotline 47 22 95 85 45 Headquarters Chipcon AS Gaustadall en 21 NO 0349 Oslo NORWAY Tel 47 22 95 85 44 Fax 47 22 95 85 46 E mail wireless chipcon com US Offices Chipcon Inc Eastern US Sales Office Chipcon Inc Western US Sales Office 35 Pinehurst Avenue 19925 Stevens Creek Blvd Nashua New Hampshire 03062 Cupertino CA 95014 2358 USA USA Tel 1 603 888 1326 Tel 1 408 973 7845 Fax 1 603 888 4239 Fax 1 408 973 7257 Email eastUSsales chipcon com Email USsales chipcon com Sales Office
159. pt immediately after ADCIF is cleared 5 0 ADCDIV RW 0x00 ADC clock divider Selects ADC clock divider in steps of 16 000000 Divider is 16 000001 Divider is 32 111111 Divider is 1024 ADTRH 0x97 ADC Threshold Register Bit Name R W Reset value Description 7 0 ADTRH 7 0 R W 0x00 ADC comparator threshold value used to generate ADC interrupt or chip reset when the threshold is exceeded SWRS047 Page 82 of 152 TEXAS INSTRUMENTS Chipcon Products from Texas Instruments 17 RF Transceiver 17 1 General description The 2271010 UHF RF Transceiver is designed for very low power and low voltage applications The transceiver circuit is mainly intended for the ISM Industrial Scientific and Medical and SRD Short Range Device frequency bands at 315 433 868 and 915 MHz but can easily be programmed for operation at other frequencies in the 300 1000 MHz range The main operating parameters of 207070 can be programmed via Special Function Registers SFRs thus making 207070 a very flexible and easy to use transceiver 17 2 RF Transceiver Block Diagram 2071010 Very few external passive components required for operation of the RF Transceiver The key parameters for the RF transceiver are listed in Table 6 Table 7 Table 8 Table 9 and Table 10 starting page 8 AD2 RSSI IF o IFSTAGE DEMOD gt RFBUF 9 intemal 8051 SFR Bus SFR
160. put Added power consumption spec for main crystal oscillator Added chapter numbering Reorganized electrical specifications Ordering info updated Added current consumption for Power on reset circuit Added recommended PCB footprint Added section about PA splattering Added specification for ADC input voltage Added specification for 32 kHz oscillator crystal load capacitance Added information about flash programming times Added RoHS Pb free chip and sample kit ordering information SWRS047 Page 149 of 152 from Taxas instruments 01010 31 2 Product Status Definitions Data Sheet Identification Product Status Definition Advance Information Planned or Under This data sheet contains the design specifications for Development product development Specifications may change in any manner without notice Preliminary Engineering Samples This data sheet contains preliminary data and and First Production supplementary data will be published at a later date Chipcon reserves the right to make changes at any time without notice in order to improve design and supply the best possible product No Identification Noted Full Production This data sheet contains the final specifications Chipcon reserves the right to make changes at any time without notice in order to improve design and supply the best possible product Obsolete Not In Production This data sheet contains specifica
161. ram P3DIR O P3DIR 1 E P2DIR 0 P2DIR 1 Mode 0 5 1 3 Mode 0 Mode 1 3 Table 22 Configuration of general purpose I O for UARTO and UART1 SWRSO047 Page 65 of 152 SWRS047 Page 66 of 152 TEXAS TEXAS INSTRUMENTS INSTRUMENTS Chipcon Products Chipcon Products from Texas Instruments 201070 from Texas Instruments 201070 SBUFO 0x99 Serial Port 0 data buffer SCON 1 0 0 Serial Port 1 Control Register Bit Name R W Reset value Description Bit Name R W Reset value Description 7 0 SBUFO 7 0 RW 0x00 Serial Port 0 data buffer 7 0 6 SMi 1 RW O 0 Serial Port 1 mode bits decoded as 5 0 1SMl 1 Mode SBUF1 0xC1 Serial Port 1 data buffer 0 0 Synchronous half duplex 0 3 1 Asynchronous full duplex start stop bit Bit Name R W Reset value Description 1 0 2 Asynchronous full duplex start stop bit 7 0 SBUF1 7 0 R W 0x00 Serial Port 1 data buffer 9th data bit 1 1 3 Asynchronous full duplex start stop bit SCONO 0x98 Serial Port 0 Control Register Sth data bit Multiprocessor communication enable In modes 2 and 3 Bit Name R W Reset value Description SM2 1 1 enables the multiprocessor communication feature 7 SMO 0 RW 0 Serial Port 0 mode bits decoded as In mode 2 or 3 RI_1 will not be activated if the received 9th bit SMO 0
162. rated after which the receiver enters normal reception mode For both the examples shown in Figure 29 BSYNC should be set to 10100101 0xA5 PDET PEN is not cleared by hardware when the preamble is detected but it will not affect the reception of data It can be cleared or left set decided by what is more practical for the software developer However before a new preamble detection session is initiated PDET PEN must be cleared If manual average filter locking is performed the average filter should be locked after receiving the synchronization byte in NRZ mode See the Reception section on page 96 for details As mentioned above it is vital that the synchronization byte is DC balanced and contains no more than two consecutive ones or zeros in order to achieve a good average filter lock in this case XAS INSTRUMENTS 20110 17 10 1 Estimating the required preamble length The preamble length is determined by several factors First the receiver circuitry needs some time to settle Second the averaging filter must acquire a correct value Third the preamble detection circuit must receive the required number of bits The first factor depends on the data rate and will be limited to only a few bits The number of bits required by the averaging filler is a bit tricky to calculate but estimates of the maximum bound are given in Table 31 and Table 32 The number of bits required will vary because the upda
163. request is generated EXIF RFI so that RFBUF can be loaded with a new data byte If a new byte is not written within eight bit periods eight baud periods in NRZ mode and 16 baud periods in Manchester TEXAS INSTRUMENTS mode the next time the shift register is empty it will load the same byte from RFBUF again E g when transmitting a preamble consisting of alternating 0 and 1 it is only necessary to write the byte to RFBUF once and then wait the desired number of byte cycles for the preamble to be transmitted bitmode RFCON BYTEMODE 0 the same buffering occurs but only for one bit at a time Thus the shift register will load a new bit from after each transmitted bit which in turn generates a RF interrupt request so that a new bit can be loaded In order to be able to write the next bit to RFBUF 0 within one bit period at high baud rates it is advisable to use a SWRS047 Page 95 of 152 Chipcon Products from Texas Instruments tight polling loop instead of an interrupt based transmit procedure In order to start transmission of data as quickly as possible the first bit byte to be transmitted should be written to RFBUF before the modulator is turned on RFMAIN TX 0 It wil then be immediately loaded into the shift register and an interrupt request will be generated for the second bit byte It is especially important to take the buffering scheme into account at the end of a
164. rmed using P2 to give the most significant address bits Existing software may therefore have to be adapted to make use of MPAGE instead of 2 The program memory can be read using the A A DPTR and MOVC A A PC instructions which moves a byte from the program memory address given by A DPTR or A PC respectively The program memory can not be written using MOV commands but uses the method described in the 8051 Flash Programming section on page 42 22100 also provides a possibility to stretch the access cycle to external RAM through CKCON MD 2 0 see page 55 The default value for CKCON MD is 001 It is recommended to set CKCON MD to 000 for faster RAM access SWRS047 Page 20 of 152 Chipcon Products from Texas Instruments 2071010 Flash Program Memory Ox7FFF External RAM Ox7FF Internal RAM SFR OxFF Special Function Accesible Accesible Registers SFR through indirect through indirect accessible addressing addressing through Direct Addressing Ox7F Internal RAM Accessible through Direct and Indirect Addressing 0x00 0x00 0x00 Figure 3 Memory Map DPLO 0x82 Data Pointer 0 low byte Bit Name RW Reset value Description 7 0 DPLO 7 0 R W 0x00 Data Pointer 0 low byte DPHO 0x83 Data Pointer 0 high byte Bit Name RW Reset value Description 0 DPHO 7 0 R W 0x00 Data Pointer 0
165. roller clock signal An external clock signal should be connected to XOSC Q1 while 02 should be left open The microcontroller core and main oscillator will operate at any frequency in the range 3 24 MHz However the crystal frequency should be in the range 3 4 6 8 or 9 24 MHz because the crystal frequency is used as reference for the data rate in the RF transceiver part as well as other internal functions The following frequencies are recommended as they will provide standard data rates 3 6864 7 3728 11 0592 14 7456 18 4320 and 22 1184 MHz The selected crystal frequency range must be set in MODEMO XOSC FREQ 2 0 in order to get the correct data rate see page 93 Using the main crystal oscillator the crystal must be connected between the pins XOSC Q1 and 02 The oscillator is designed for parallel mode operation of the crystal In addition loading capacitors C171 and C181 for the crystal are required The loading capacitor values depend on the total load capacitance C specified for the crystal The total load capacitance seen between the crystal terminals should equal C for the crystal to oscillate at the specified frequency 1 E NE m C parasite c pot Cn TEXAS INSTRUMENTS 2071010 register any pulse longer than 8 clock cycles will always generate an interrupt The 100 will wake up from Idle mode when an external interrupt pin is activated but the external
166. rom Texas Instruments 2071010 17 5 RF Transceiver RX TX control and power management The RFMAIN register controls the operation mode RX or TX use of the dual frequency registers and several power down modes In this way the 661010 offers great flexibility for RF power management in order to meet strict power consumption requirements in battery operated applications Different power down modes are controlled through individual bits in the RFMAIN register There are separate bits to control the RX RFMAIN 0xC8 RF Main Control Register part the TX part the frequency synthesiser and the crystal oscillator This individual control can be used to optimise for lowest possible current consumption in a certain application A typical power on sequence for minimum power consumption is shown in Figure 22 The figure assumes that frequency A is used for RX and frequency B is used for TX If this is not the case simply invert the F REG setting Bit Name R W Reset value Description T RXTX RW 0 RX TX Switch 0 RX 1 TX 6 F REG RW 0 Select the frequency registers A or B 0 Select frequency registers A 1 Select frequency registers B Select power down for the LNA mixer IF filter and digital demodulator 0 Power up 1 Power down Select power down of the digital modem and PA 0 Power up 1 Power down 3 PD RW 7 Select power down of the frequency synthesizer 0 Power up 1
167. ronize correctly The minimum length of the preamble RX PD RX The averaging filter must be locked before depends on the acquisition mode selected E any NRZ data can be received This can and the settling time Table 31 gives the Averaging filter locked be done in one of two ways minimum recommended number of chips MEM for the preamble NRZ and UART e After receiving the preamble and byte modes In this context chips refer to the Averaging filter synchronisation see the data coding Using Manchester coding free running not used Synchronization and preamble every bit consists of two chips For detection section on page 102 set Manchester mode the minimum Automatically locked after a short period depending on SETTLING MODEM1 LOCK_AVG_IN 1 to stop recommended number of chips is shown updating the averaging filter in Table 32 Figure 26 Automatic locking of the averaging filter Set MODEM1 LOCK MODE A special feature in the data filter is a peak gt Data package to be received and then enter Receive mode remover acting like a low pass filter The RFMAIN RX_PD 0 The averaging peak threshold must programmed Noise Preamble NRZ data Noise filter will then be automatically locked according to the deviation and expected after a preset number of baud periods frequency drift When PD RX programmable in MODEM1 SETTLING MODEM1 PEAKDETECT is enabled The settling time is programmable MODEM2 PLO sho
168. s Instruments 201010 from Texas Instruments 2010710 Description 3 3 15 6 Interrupts o amp In 667010 there are a total of 15 interrupt interrupt enable and interrupt flag is also g e sources which share 12 interrupt lines shown in the table and will be described amp 2 518181 These are all shown in Table 13 Each below Branching interrupt s natural priority interrupt vector ACALL addr 11 Absolute call to subroutine 2 3 11 F1 LCALL addr 16 Long call to subroutine 3 4 12 Interrupt Natural Priority Interrupt Interrupt Interrupt Flag RET Return from subroutine 114 22 Priority Control Vector Enable RETI Return from interrupt 1 4 32 Flash Debug interrupt 0 0 33 EICON EICON AJMP addr 11 Absolute jump unconditional 2 3 01 E1 FDIE FDIF LJMP addr 16 Long jump unconditional 14 02 External Interrupt 0 1 0x03 TCON IEO 7 SUMP rel Short jump relative address 2 13 80 Timer 0 Interrupt 2 IP PTO 0x0B IE ETO TCON TFO 7 JC rel Jump on carry 1 2 3 40 External Interrupt 1 3 0 13 TCON IE1 7 JNC rel Jump on carry 0 2 3 50 Timer 1 Interrupt 4 Ox1B IE ETl TCON TF1 7 JB bit rel Jump on direct bit 1 4 20 Serial Port 0 Transmit Interrupt 5 50 0 23 IE ESO SCONO TI 0 JNB bit rel Jump on direct bit 0 l4 30 Serial Port 0 Receive Interrupt SCONO RI 0 JBC bit rel Jump on direct bit 1 and clear 5 4 10 Serial Port 1 Transmit Interrupt 6 IP PS1 O
169. s instruments CCT010 RFMAIN 0xC8 RF Main Control Register RTCON 0xED Realtime Clock Control Register SBUFO 0x99 Serial Port 0 data buffer SBUF1 0xC1 Serial Port 1 data buffer SCONO 0x98 Serial Port 0 Control Register SCON1 0xC0 Serial Port 1 Control Register SP 0x81 Stack Pointer SPCR 0xA1 SPI Control Register SPDR 0xA2 SPI Data Register SPSR 0xA3 SPI Status Register T2 0xAC Timer 2 Low byte counter value T2PRE 0xAA Timer 2 Prescaler Control T3 OxAD Timer 3 Low byte counter value T3PRE 0xAB Timer 3 Prescaler Control TCON 0x88 Timer Counter 0 and 1 control register TCON 2 0xA9 Timer Control register 2 TESTO 0xF9 PLL Test Register 0 TEST1 PLL Test Register 1 TEST2 0xFB PLL Test Register 2 TESTS OxFC PLL Test Register 3 TESTA OxFD PLL Test Register 4 TESTS PLL Test Register 5 TEST6 OxFF PLL Test Register 6 TESTMUX OxEF Test Multiplexer Control Register for prototype testing THO 0x8C Timer Counter 0 High byte counter value TH1 0x8D Timer Counter 1 High byte counter value TLO 0x8A Timer Counter 0 Low byte counter value TL1 0x8B Timer Counter 1 Low byte counter value TMOD 0x89 Timer Counter 0 and 1 Mode register WDT 0xD2 Watchdog Timer Control Register Seni X32CON 0xD1 32 768 kHz Crystal Oscillator Control Register
170. s is illustrated in Figure 30 NRE Pica Manchester data gt lt aal Bit value 41 054989447i10 4 109 1205120 1 170204 4 0 gt lt gt lt Preamble Byte sync Data Figure 30 Switching data mode after preamble Changing the desired data mode during reception of NRZ preamble and Manchester data is straightforward A new value of MODEMO DATA_FORMAT does not take effect before an RF interrupt request is generated After having started a reception using preamble detection byte synchronization and the NRZ data mode the DATA_FORMAT should be set to Manchester The whole preamble detection process will then work with NRZ TEXAS INSTRUMENTS data and the new DATA FORMAT will not take effect until valid NRZ synchronization byte is found and an interrupt request generated It is not recommended to change the data format during reception for new protocols but the functionality is included for compatibility with existing protocols SWRS047 Page 104 of 152 Chipcon Products from Texas Instruments 2071010 17 11 Receiver sensitivity versus data rate and frequency separation The receiver sensitivity depends on the data rate the data format FSK frequency separation and the RF frequency Typical figures for the receiver sensitivity BER 10 are shown in Table 33 for 64 kHz frequency separations and in Table 34 for 20 kHz Optimised sensitivity
171. scription Td EA RW 0 Global Interrupt enable disable 0 All interrupts except the Flash debug interrupt are disabled 1 Each interrupt is enabled by its individual masking bit 51 Serial Port 1 interrupt enable disable 0 Interrupt is disabled 1 Interrupt is enabled when also EA is set Reserved for future use ESO Serial Port 0 interrupt enable disable 0 Interrupt is disabled 1 Interrupt is enabled when also EA is set Timer 1 interrupt enable disable 0 Interrupt is disabled 1 Interrupt is enabled when also EA is set EX1 External interrupt 1 from P3 3 enable disable 0 Interrupt is disabled 1 Interrupt is enabled when also EA is set ETO Timer 0 interrupt enable disable 0 Interrupt is disabled 1 Interrupt is enabled when also EA is set EXO External interrupt 0 from 2 enable disable 0 Interrupt is disabled 1 Interrupt is enabled when also EA is set EIE 0xE8 Extended Interrupt Enable Register 7 SMOD1 R W 0 Serial Port 1 baud rate doubler enable disable 0 Serial Port 1 baud rate is normal 1 Serial Port 1 baud rate is doubled 6 R1 A Reserved read as 1 5 FDIE R W Flash Debug interrupt enable 0 Interrupt is disabled 1 Interrupt is enabled independent of IE EA 4 FDIF R W 0 Flash Debug interrupt flag FDIF is set by hardware when an 8051 initi
172. shown Figure 45 below and the dimensions are listed in Table 40 Please note that the drawing in Figure 45 is not to scale TOP SIDE n 33 ALL ROUND D14 D3 PN M ALL ROUND lai e FRONT B1 i ES DETAIL 9 Re GAGE PLONE J Li b Figure 45 TQFP 64 package T SWRS047 Page 135 of 152 XAS Chipcon Products from Texas Instruments 61010 Symbol Dimensions mm Remarks A 1 20 max Overall height A1 0 05 0 15 Standoff A2 1 00 0 05 Package thickness D 12 00 0 20 Terminal dimension D1 9 95 0 10 Top package width D3 10 00 0 10 Bottom package width 12 00 0 20 Terminal dimension E1 9 95 0 10 Top package length 10 00 0 10 Bottom package length R1 0 08 Min First radius R2 0 15 Ref Second radius p 0 7 Foot angle pt 0 Min Shoulder angle p2 12 Top draft angle p3 12 Bottom draft angle 0 09 0 20 Lead thickness L 0 60 0 15 Foot length L1 1 0 Ref Lead length 5 0 20 0 080 Coplanarity Ddd 0 080 Max Bent lead e 0 50 Lead pitch b 0 17 0 27 Lead tip width Table 40 TQFP 64 package dimensions 21 Soldering Information The recommended soldering profiles for both leaded and Pb free packages are accor
173. t is 4 REN 0 R W 0 Receive enable When REN 0 1 reception is enabled placed on the TXD1 pin TI 1 must be cleared by the 7 software 3 TB8 O RW 0 Defines the state of the 9th data bit transmitted in modes 2 and 0 RI 1 RW 0 Receive interrupt flag Indicates that a serial data word has 2 RB8 0 RW O In modes 2 and 3 RB8 0 indicates the state of the 9th bit mue ma k end BH received In mode 1 RB8_0 indicates the state of the received stop bit In mode 0 RB8 o isinotiusad incoming stop bit subject to the state of SM2 1 modes 2 1 TI RIW O Transmit interrupt flag Indicates that the transmit data word anda RI Tls etatthe end of the last sample o RB 1 has been shifted out In mode 0 TI 0 is set at the end of the RI 1 mustbe cleared by thie software 8th data bit In all other modes TI 0 is set when the stop bit is placed on the TXDO pin 0 must be cleared by the software 0 RI 0 RW 0 Receive interrupt flag Indicates that a serial data word has been received In mode 0 0 is set at the end of the 8th data bit In mode 1 RI 0 is set after the last sample of the incoming stop bit subject to the state of SM2 0 In modes 2 and 3 0 is set at the end of the last sample of RB8_0 RI 0 must be cleared by the software TEXAS INSTRUMENTS SWRS047 Page 67 of 152 16 7 1 MODE 0 Serial mode 0 provides synchronous half duplex serial communi
174. t values are still available in the TL1 and TH1 registers Control of Timer 1 when Timer 0 is in mode 3 is done through the Timer 1 mode bits To turn Timer 1 on set Timer 1 to mode 0 1 or 2 To turn Timer 1 off set it to mode 3 Timer 1 can count clock cycles divided by 4 or 12 or high to low transitions on the T1 pin The GATE function is also available In Mode 3 the timer timeout periods are determined by 12 8 CKCON TxM 256 TYx Sros where TYx is the contents of the THx or TLx register if this is reloaded in the interrupt handler or 0 if no reload is done SWRS047 Page 57 of 152 Chipcon Products C from Texas Instruments 2071010 mo Daer o H Brie Ei Timer 1 m request clock TRO pensi a De 5 Teer erp TF J request wo Figure 10 Mode 3 operation for Timer Counter 0 SWRS047 Page 58 of 152 TEXAS INSTRUMENTS Chipcon Products from Texas Instruments 16 3 Timer 2 3 with PWM 1010 also features two timers with pulse width modulation PWM outputs Each timer generate interrupts as described in the Interrupts section on page 28 The timers are individually set in one of two modes timer mode or PWM mode This is controlled through the bits M2 and TCON2 0xA9 Timer Control register 2 2071010 M3 in the TCON2 control register sho
175. tal high Z I O 8051 port 0 bit 2 or SPI interface master bias generator A precision resistor 82 pin can be left open not connected 50 0 input Flash programming SPI slave serial kQ 1 should be connected between ORT G data output om POR 52 P03 Digital high Z 70 8051 port 0 bit 3 eee one ground to set the correct blas Port 0 is a 4 bit PO 3 0 bi directional 53 P1 5 Digital high Z I O 8051 port 1 bit 5 d CMOS port with 2 mA drivers A 54 P1 6 Digital high Z I O 8051 port 1 bit 6 XOSC Q1 XOSC Q2 direction register PODIR controls whether 55 P17 Digital high Z 1 0 8051 port 1 bit 7 These are the main oscillator connection each pin is an output or input and the 56 P2 6 Digital high Z 1 0 8051 port 2 bit 6 pins An external crystal should be register PO is used to read the input or Br PET Digital high Z VO ___ 8051 port 2 bit 7 connected between these pins and load control the logical value of the output 58 PROG Digital input Flash program enable pad active low capacitors should be connected between 59 Digital input pul Syst USE each pin and ground If an external Pins P0 0 P0 2 can be configured to RESET igital input pull up System reset pin active low oscillator is used the clock signal should become a master SPI interface in register 60 DVDD Power D Digital power supply be connected to the XOSC Q1 pin and SPCR and will then override 2 0 61 ADO a Analog input ADC input channe
176. tch for a particular layout and component selection The tuning can be accomplished by stepping the register values until optimum sensitivity and output power is reached HDD DEN REIN 1 1 1 TO ANTENNA OUT 7 i E 52 1 i 1 9151 5142 A 1 1 1 1 AVDD 3V Figure 36 Input output matching network MATCH 0xDC Match Capacitor Array Control Register Bit Name R W Reset value Description 7 3 RKX MATCH 0000 Selects matching capacitor array value for RX step size is 3 0 0 4 pF 0000 Use for RF frequency 500 MHz 1100 Use for RF frequency 500 MHz 3 0 TX MATCH R W 0000 2 Selects matching capacitor array value for TX step size is 3 0 0 4 pF Recommended setting is 0000 TEXAS INSTRUMENTS SWRS047 Page 120 of 152 S rote Texas instruments 2071010 gt Reflection Smith 1 FS ba Off 1 4 915 000 MHz 10 36 490 12 832 13 55pF Start 380 000 MHz top 1 808 280 MHz Mkr MHz __ Ohm 2 Mkr Hz dB 315 008 69 82 12 95 434 088 67 88 23 33 858 008 36 27 11 91 l 915 008 36 49 12 83 Figure 37 Typical LNA input impedance 300 1000 MHz from Taxas instruments 01010 gt Reflection Smith 1U FS P2 0ff o leasi Mkr4 915 000 MHz 5 8580 21 87ma 3 665pH Start 302 208 MHz Stop 220 028 MHz HiMkr M
177. tching network and VCO inductor are easily calculated using the SmartRF Studio software for any operation frequency TEXAS INSTRUMENTS 2071010 17 3 3 Additional filtering Additional external components e g RF LC or SAW filter may be used in order to improve the performance in specific applications See also the Optional LC Filter section on page 128 for further information If a SAW filter is used it should be included in the RX path only an external RX TX switch should then be used 17 3 4 Voltage supply decoupling Voltage supply filtering and de coupling capacitors must be used not shown in the application circuit These capacitors should be placed as close as possible to the voltage supply pins of 227070 The placement and size of the decoupling capacitors and power supply filtering are very important to achieve the best sensitivity and lowest possible LO leakage and the reference layouts should be followed SWRS047 Page 85 of 152 Chipcon Products from Texas Instruments
178. ted at the end of the current conversion by clearing this bit When ADCM 10 the hardware clears this bit when stopping 10 ADADR 1 0 R W 00 Select the analog input to the ADC 00 Mux data from the ADO pin 01 Mux data from the AD1 pin 10 Mux data from the AD2 RSSI IF pin 11 Mux data from the ADO pin with AD1 as an external reference ADCREF is ignored in this setting ADDATL 0x94 ADC Data Register Low Byte Bit Name R W Reset value Description 7 0 ADDAT 7 0 R 0x00 8 LSB of ADC data output ADDATH 0x95 ADC Data Register High Bits Bit Name R W Reset value Description 72 RO 0x00 Reserved read as 0 TO ADDAT 9 8 R 0x00 2 MSB of ADC data output latched when ADDATL is read TEXAS INSTRUMENTS SWRS047 Page 81 of 152 ic Chipcon Products from Texas Instruments 2071010 ADCON 2 0x96 ADC Control Register 2 Bit Name R W Reset value Description 7 ADCIE RW 0 ADC interrupt enable flag In order for to raise an interrupt EIE ADIE must also be set 6 ADCIF RW 0 ADC interrupt flag ADCIF must be cleared by software Because the ADC shares an interrupt line with the DES module EXIF ADIF must also be cleared by software before exiting the interrupt service routine EXIF ADIF should be cleared first so that the 8051 is ready to receive a new interru
179. tem reset is generated This mode can be used in conjunction with the 8051 s stop mode and the 32 kHz oscillator to achieve very low power consumption while monitoring a signal The value stored in ADDATH and ADDATL is not affected by a reset so that the sampled value can be read back after the reset has taken effect SWRS047 Page 80 of 152 Chipcon Products from Texas Instruments 2071010 ADCON 0x93 ADC Control Register Bit Name R W Reset value Description ri AD PD RW 1 ADC Power down bit 0 ADC is active 1 ADC is in power down 6 0 Reserved read as 0 54 ADCM 1 0 R W 00 ADC Mode 00 Single conversion mode Interrupt when threshold condition holds true stop after one conversion 01 Multi conversion mode continuous Interrupt when threshold condition holds true continue sampling 10 Multi conversion mode stopping Interrupt when threshold condition holds true stop sampling 11 Multi conversion mode reset generating Generate reset when threshold condition holds true 3 ADCREF RW 0 Select the internal ADC Voltage Reference 0 Voltage reference is VDD 1 Voltage reference is 1 25 V generated on chip 2 ADCRUN RW 0 ADC run control Setting this bit in software will start ADC operation in single or multi conversion mode In single conversion mode this bit is cleared by hardware when the single conversion is done Multi conversion operation can be hal
180. th bit and 1 stop bit The data bits are transmitted and received LSB first Transmission and reception in mode 3 is identical to mode 2 except for the baud rate generation which is identical to mode 1 16 7 5 Multiprocessor Communications The multiprocessor communication feature is enabled in mode2 and mode 3 when the 5 2 0 SM2 1 bit is set The 9th bit received is then stored in RB8_0 RB8 1 and the interrupt bit is only set if this bit is 1 An address byte can then be transmitted with the 9th bit set to generate an interrupt on all slaves The slave s with the correct address decoded in software may then clear SM2 0 SM2 1 to receive the rest of the data which is transmitted with the 9th bit low All other slaves will then ignore the data received SWRS047 Page 70 of 152 Chipcon Products from Texas Instruments 16 8 SPI Master The SPI master interface allows 661010 to communicate with peripheral devices such as an external serial EEPROM interface It has a programmable data rate up to 3 MHz depending on the frequency of the main crystal The SPI master interface is controlled using the SPCR register shown below Setting SPCR SPE enables the SPI interface Pins P0 0 PO 1 and PO 2 then reconfigured as the serial clock output SCK the serial data output pin and the serial data input pin MI The direction bits set in PODIR 0 and PODIR 2 are then ignored setting SCK 61010
181. ting of the averaging filter is not synchronised to the start of the transmission RF noise can complicate the issue further To determine an approximate preamble length add the estimated number of bits required by the averaging filter with the preamble detector setting Round the number of bits up to the closest multiple of 8 and use this as a starting point For time critical applications where it is important to use as short preamble as possible the preamble length should be optimized by experimentation 17 10 2 Manchester violations In some RF applications using Manchester coding violations of the Manchester coding have been used for start and end of frame delimiters Furthermore some implementations use a sequence of all ones or all zeros for a preamble instead of an alternating zero one sequence Although an all zero or all one sequence will certainly be DC balanced once Manchester coded the receiver is unable to decide whether it is receiving an all zero or an all one sequence since only the bit synchronization will separate these In order to facilitate reception and transmission of such special cases support has been implemented in 207070 for allowing the data format to be changed in the middle of reception transmission Furthermore violations of the Manchester coding format is reported in the status bit RFCON MVIOL The SWRS047 Page 103 of 152 Chipcon Products from Texas Instruments thresh
182. tions on a product that has been discontinued by Chipcon The data sheet is printed for reference information only 31 3 Disclaimer Chipcon AS believes the information contained herein is correct and accurate at the time of this printing However Chipcon AS reserves the right to make changes to this product without notice Chipcon AS does not assume any responsibility for the use of the described product neither does it convey any license under its patent rights or the rights of others The latest updates are available at the Chipcon website or by contacting Chipcon directly As far as possible major changes of product specifications and functionality will be stated in product specific Errata Notes published at the Chipcon website Customers are encouraged to sign up to the Developers Newsletter for the most recent updates on products and support tools When a product is discontinued this will be done according to Chipcon s procedure for obsolete products as described in Chipcon s Quality Manual This includes informing about last time buy options The Quality Manual can be downloaded from Chipcon s website Compliance with regulations is dependent on complete system performance It is the customer s responsibility to ensure that the system complies with regulations This Chipcon product contains Flash memory code protection However Chipcon does not guarantee the security of this protection Chipcon customers using or selling
183. tor frequency 32768 Hz Table 2 Recommended Operating Conditions TEXAS INSTRUMENTS SWRS047 Page 5 of 152 Chipcon Products 2 from Texas Instruments 4 DC Characteristics The DC Characteristics of 667010 are listed in Table 3 below 25 C VDD 3 3 V if nothing else stated 61010 Digital Inputs Outputs Min Max Unit Condition Logic 0 input voltage 0 0 3 VDD V Logic 1 input voltage 0 7 VDD VDD V Logic 0 output voltage 0 0 4 V Output current 2 0 mA ports P0 3 P0 0 P1 7 P41 0 P2 7 P2 4 P2 2 P2 0 Logic 1 output voltage 25 VDD Output current 2 0mA ports P0 3 P0 0 P1 7 P1 0 P2 7 P2 4 P2 2 P2 0 Logic 0 output voltage 0 0 4 V Output current 8 0 mA port P2 3 Logic 1 output voltage 25 VDD v Output current 8 0mA port P2 3 Logic 0 input current NA 1 pA Input signal equals GND Logic 1 input current NA 1 uA Input signal equals VDD Table 3 DC Characteristics 25 z 20 5 15 2 9 40 a a 5 0 0 8 12 16 20 24 Frequency MHz Figure 1 Typical CPU core supply current vs clock frequency TEXAS INSTRUMENTS SWRS047 Page 6 of 152 Chipcon Products from Texas Instruments 5 Electrical Specifications Tc 25 C VDD 3 3 V if nothing else stated All electrical specifications are measured on Chipcon s CC1010EM reference design 2071010
184. transmission When the last byte of a data frame or packet is loaded into the shift register it is still not transmitted Thus the interrupt request generated at the same time must not turn off either analog or digital parts of the transmit chain The transmission can not be ended safely until nine bit periods later in bytemode and two bit periods later in bitmode when the last bit has been shifted out and has propagated through the transmit chain to the antenna A simple solution is to always transmit two extra bytes in bytemode or two extra bits in bitmode at the end of the real data content In bytemode this will result in that approximately seven of these bits will be transmitted along with the real data This should cause no problems in practice TEXAS INSTRUMENTS 61010 17 8 2 Reception When receiving data the buffering scheme works in reverse of what it does during transmitting Bit by bit from the demodulator is shifted into the eight bit shift register MSB first When the shift register is full it is loaded into RFBUF and an interrupt request is generated EXIF RFIF The byte must be read within one byte period eight baud periods in NRZ mode and 16 baud periods in Manchester mode If not it will be overwritten by the next byte received and the data is lost In bitmode the same buffering occurs but only for one bit at a time Thus when a new bit arrives from the demodulator the shift register will store it a
185. trongly dependent on the setting in FLTIM It is therefore recommended to set FLTIM as low as possible as with the SPI Flash programming Write the desired Flash page number to the FLADR register TEXAS INSTRUMENTS 2071010 e Repeat the loading and writing of each new page e Programming can be verified using the Read Program Memory instruction e Set the lock bits using the Write Lock Bits instruction e Lock bits can be verified by using the Read Lock Bits instruction e M Disable all interrupts except the Flash Debug interrupt which must be enabled through EICON FDIE Store the 128 bytes of data to be written in the external data memory The address of the first byte in the buffer must be a multiple of 128 e Write the 4 most significant bits of the RAM buffer address to FLCON RMADR 3 0 Also set the bit FLCON WRFLASH e Set the 8051 in Idle Mode by setting PCON IDLE The Flash page is then automatically erased and programmed The sequence of the above steps is not important Flash programming is started whenever entering Idle Mode while FLCON WRFLASH is set A Flash Debug interrupt will be generated when the page write operation is completed which will get the 8051 out of Idle Mode An ISR must be present to service the Flash Debug interrupt SWRS047 Page 42 of 152 Chipcon Products from Texas Instruments FLADR 0xAE Flash Write Address Register 2071010
186. ts The random data generated has a relatively white spectrum but tones have been observed when the random bit generator has been enabled for more than one second If this is not sufficient for the application to generate the random bits required the random bit generator should be disabled and enabled following the procedure described above before generating more data RANCON 0xC7 Random Bit Generator Control Register Bit Name RW Reset value Description LESS RO 0x00 Reserved read as 0 1 RANEN R W 0 Random Bit Generator Enable 0 Random Bit Generator is disabled 1 Random Bit Generator is enabled RFMAIN RX PD must also be cleared to generate random bits 0 RANBIT R 0 RANBIT returns one random bit generated from the RF receiver path SWRS047 Page 78 of 152 TEXAS INSTRUMENTS Chipcon Products from Texas Instruments 16 11 ADC The on chip 10 bit ADC is controlled by the registers ADCON and ADCON2 Three analog pins can be sampled selected by ADCON ADADR This register is also used to select the AD1 pin as external reference when using ADO When the AD1 pin is used as external reference only two ADC inputs are available The ADC output is unipolar with an output value of 0 corresponding to OV and 1023 corresponding to the reference voltage 1 25 V or VDD depending on the setting of the ADCREF bit The analog reference voltage is controlled by ADCON ADC
187. two standard 8051 timers counters Timer 0 and Timer 1 which can operate as either a timer with a clock rate based on the system clock as defined by the current clock mode or as an event counter clocked by the TO P3 4 for Timer 0 or T1 P3 5 for Timer 1 inputs 01010 Each Timer Counter has a 16 bit register which is readable and writeable through TLO and THO for Timer Counter 0 and TL1 and TH1 for Timer Counter 1 These registers are described below TLO 0x8A Timer Counter 0 Low byte counter value Bit R W Reset value Description 7 0 TLO 7 0 R W 0x00 Timer Counter 0 low byte counter value TL1 0x8B Timer Counter 1 Low byte counter value Bit Name R W Reset value Description 7 0 TL1 7 0 R W 0x00 Timer Counter 1 low byte counter value THO 0x8C Timer Counter 0 High byte counter value Bit Name R W Reset value Description 7 0 THO 7 0 R W 0x00 Timer Counter 0 high byte counter value TH1 0x8D Timer Counter 1 High byte counter value Bit Name R W Reset value Description TO TH1 7 0 R W 0x00 Timer Counter 1 high byte counter value SWRS047 Page 51 of 152 TEXAS INSTRUMENTS 16 2 1 Timer Counter 0 and 1 Modes Timer Counter 0 and 1 can individually be programmed to operate in one out of four different modes controllable through the registers TMOD and TCON They are as fo
188. uld be set such that Averaging fir free running Averaging filter locked from 11 to 86 bauds The average filter lock status can be read through PLO s f 3 MODEM1 AVG FILTER STAT IEn ogg 8 Please note that the locking is only m automatic in that the lock is enabled the programmed number of bit periods Manually locked after preamble is detected after receive mode is entered The automatic locking should therefore Figure 27 Manual locking of the averaging filter only be used in situations where the SWRS047 Page 97 of 152 SWRS047 Page 98 of 152 TEXAS TEXAS INSTRUMENTS INSTRUMENTS Chipcon Products Chipcon Products frome Texas Instruments 2010710 from Texas Instruments 2010710 Data package to be received p MODEM1 0xDA Modem Control Register 1 Bit Name R W Reset value Description Noise Preamble Manchester encoded data Noise T 0 Reserved read as 0 6 LOCK_AVG_IN RW 0 Lock control bit of average filter PD RX 0 Average Filter is free running used for receiving zero average Averaging filter always free running eme br Manehester 1 Lock average filter used for NRZ Figure 28 Free running averaging filter data 5 LOCK AVG MODE R W 1 Automatic lock of average filter Settling Manual Lock Automatic Lock 0 Lock of Average Filter is controlled NRZ mode UART mode NRZ mode UART mode automatically use when zero average data is present when the MODEM1 MODEM1 LOCK_ MODEM1 LOCK_ MODE
189. w loop filter is used E 14 R BIAS Analog Connection for external precision bias 5 3 resistor 82 1 amp alto Zoo 15 AVDD Power A Power supply misc analog modules 6858 B 5 16 AGND Power A Ground connection misc analog modules a hnDiri 000nn0n65020 aT AGND Power A Analog ground connection 54 63 62 61 50 B9 58 El 56 55 41083 52 pi ol fel 18 XOSC Q1 Analog input owe crystal pin 1 or external clock input AVE 48 P3 0 RXDO 19 XOSC Q2 Analog output 3 24 MHz crystal pin 2 AVDD 2 47 P3 1 TXDO 20 XOSC32 0 Analog output 32 kHz crystal pin2 AGND 3 46 P3 2 INTO 2 RF IN 4 48 P2 5 21 Analog input 32 kHz crystal pin1 or external clock input RF OUT 5 44 P2 4 22 AGND Power A Analog ground connection AVDD 6 43 DVDD 23 DGND 0 Digital ground connection AGND 7 42 P2 3 24 DGND 0 Digital ground connection 25 POR_E Digital input Power on reset enable AGND 8 41 DGND 0 Disable internal power on reset module AGND 9 40 DVDD 1 Enable internal power on reset module L1 39 P2 2 26 P1 0 Digital high Z I O 8051 port 1 bit O 27 P2 0 RXD1 I Digital high Z 8051 port 2 bit 0 or RX of serial port 1 12 38 P14 28 P21 TXD1 O Digital high z ___ 8051 port 2 bit 1 or TX of serial port 1 AVDD 12 37 P1 3 29 P3 5 PWM3 O Digital high Z 8051 port 3 bit
190. w v3ovdw S3ovdw S3ovdw I3ovdw Bova zexo 26 _1000 10 00343 OSOX voaud OSOX ZO3MJ OSOX OlVWHOd Viva LLvWHOJ Viva O31vsanva iaivsanva za3ivuanva ON3GOW O 00010000 3 EIE 231 aiv 3X3 L6X0 Old Vid Zid eld vid 914 kd 06x0 96 LLLIOLO0 13588 W3QOW OONMLLAS LONIULLAS WLS OAV 3001 OW DAV 5901 31901 vaxo 00000000 5 E aexo 001 OLLOLO00 007d 1079 9019 ZW3GOW SS 10000000 oaw ZON WOL WLL WZL sexo 00000010 E 3103 ETF 2 NOOI3 zs 00000000 ZiHL S IHL 9 1HL LHL 00000000 d 200 zs 00000000 O 0HL VOHL ZOHL 0HL S 0HL 9 0Hl O8X0 00000000 E g 9axo zs 00000000 RTI FAL zIu L RTI SL gru vin Sexo 00000000 z 5 saxo zs 00000000 OO FOU 2011 EOU voll 9011 FOUL Lol vexo zor 00000000 0 ZONASA ONASH YONAS SONASH 9 1ONASH ONASE vOXO es 00000000 ow VN Jo 31v9 ON VN 19 alvo GONL 68X0 201 00000000 ZN31d Nad 9N31d N3d 130d eaxo YS 00000000 OL EI 081 OaL va NOOL 88X0 9 11010000 O3HdlGM Vaud LOM NILAM ISLOM zaxo 9 00001100 Enel 3015 049 139 gt 0dO
191. wn below Timer 2 and Timer 3 are enabled individually through the bits TCON2 TR2 and TCON2 TR3 Bit Name R W Resetvalue Description 7 0 Reserved read as 0 6 0 Reserved read as 0 5 RO 0 Reserved read as 0 4 RO 0 Reserved read as 0 3 TR3 RW 0 Timer 3 run control 0 Timer 3 is disabled The Timer counter is cleared 1 Timer 3 is enabled 2 M3 RW 0 Timer 3 mode control 0 Timer 3 is in timer mode 1 Timer is PWM mode 5 is set to be an output overriding PSDIR 5 1 TR2 RW 0 Timer 2 run control 0 Timer 2 is disabled The Timer 2 counter is cleared 1 Timer 2 is enabled 0 M2 RW 0 Timer 2 mode control 0 Timer 2 is in timer mode Timer 2 is in PWM mode 4 is set to be an output overriding PSDIR 4 16 3 1 Timer Mode Timer 2 Timer can be set in Timer Mode by clearing the bit TCON2 M2 TCON2 M3 Timer Mode operation is illustrated in Figure 11 The 16 bit counter is preloaded with T2 and T2PRE or T3 and T3PRE as shown When disabling the timer through clearing TCON2 TR2 or TCON2 TR3 the counter is also preloaded The counter value cannot be read by software When the counter underflows decrements from a zero value it is loaded with the contents of T2 T3 and T2PRE T3PRE and the interrupt request bit EXIF TF2 EXIF TF3 is set by hardware The TEXAS INSTRUMENTS interrupt request must b
192. x registers if this is reloaded in the interrupt handler or 0 if no reload is done TEXAS INSTRUMENTS SWRS047 Page 56 of 152 Chipcon Products from Texas Instruments Divide by 12 1o TOM TIM System ck Divide by 4 Twm 61010 po morcm 7RO TRI aureo Gate os INTO INTE THO THI Timer 0 Timer 1 interrupt request 7 L Figure 9 Mode 2 operation for Timer Counter 0 or 1 16 2 5 Mode 3 In Mode 3 which is illustrated in Figure 10 Timer 0 is operated as two separate 8 bit counters and Timer 1 stops counting and holds its value TLO is configured as an 8 bit counter controlled by the normal Timer 0 control bits It counts either clock cycles divided by 4 or by 12 as given by CKCON TOM high to low transitions on TO as given by TMOD C T 0 It is also possible to use the GATE function for TLO to set INTO as count enable THO is locked into a timer function and takes over the use of TR1 and TF1 from Timer 1 It counts clock cycles divided by 4 or 12 as given by CKCON T1M THO may then generate Timer 1 interrupts Timer 1 has limited usage when Timer 0 is in mode 3 This is because Timer 0 uses the Timer 1 control bit TR1 and the interrupt flag TF1 However Timer 1 can TEXAS INSTRUMENTS still be used for baud rate generation and the Timer 1 coun
193. x3B IE ES1 SCON1 TI 1 JMP A DPTR Jump indirect relative DPTR 113 73 Serial Port 1 Receive Interrupt SCON1 TI 1 JZ rel Jump on accumulator 0 9 60 RF Transmit Receive Interrupt 7 EIP PRF 0x43 EIE RFIE EXIF RFIF JNZ rel Jump on accumulator 0 2 3 70 Timer 2 Interrupt 8 EIP PT2 0x4B EIE ET2 EXIF TF2 A direct Compare A and direct jump 4 5 ADC Interrupt 9 EIP PAD 0x53 EIE ADIE EXIF ADIF rel relative if not equal and ADCON2 and CONE A 4d rel Compare A and immediate jump 3 4 B4 x ADCIE ADCON2 relative if not equal ADCIF CJNE Rn d rel Compare reg and immediate 4 B8 x DES Encryption Decryption EIE ADIE EXIF ADIF jump relative if not equal BF Interrupt and and Ri d rel Compare ind and immediate jump 3 4 B6 x relative if not equal B7 CRPIE CRPIF DJNZ Rn rel Decrement register jump relative 2 3 D8 Timer 3 Interrupt 10 EIP PT3 0x5B EIE ET3 EXIF TF3 ifnotzero DF Realtime Clock Interrupt 11 EIP PRTC 0x63 EIE RTCIE EICON RTCIF DJNZ direct rel Decrement direct byte jump 3 4 05 Interrupt flag is cleared by hardware relative if not zero Misc NOP No operation 1 1 00 Table 13 667070 Interrupt overview TRAP Set EICON FDIF 1 usedfor 1 3 A5 E C1010 executes the ISR to completion breakpoints 15 6 1 Interrupt Masking unless another interrupt set at a higher Table 12 Instruction Set Summary SWRS047 Page
194. y Control Register Bit Name RW Reset value Description 70 FSDELAY 7 0 RW __ 0x2F Reserved for future use TEXAS INSTRUMENTS SWRS047 Page 129 of 152 Chipcon Products C from Texas Instruments 2071010 FSCTRL 0xEC Frequency Synthesiser Control Register Bit Name R W Reset value Description 75 0x00 Reserved read as 0 4 EXT_FILTER 0 Setting for external loop filter not recommended 0 Internal loop filter recommended 1 External loop filter 3 DITHER1 RW 0 Reserved for future use Write as 0 2 DITHERO RW 0 Reserved for future use Write as 0 1 5 0 Reserved for future use Write as 0 rs RESET 1 Separate reset of frequency synthesiser 0 Frequency synthesiser is reset 1 Frequency synthesiser reset is released PRESCALER 0xE6 Prescaler Control Register Bit Name R W Reset value Description 7 PRE_SWING R W 00 Prescaler swing Fractions for PRE_CURRENT 1 0 1 0 00 00 1 Nominal Swing 01 10 11 2 3 Nominal Swing 7 3 Nominal Swing 5 3 Nominal Swing 5 PRE CURRENT R W 00 1 0 Prescaler current scaling 00 01 10 11 1 Nominal Current 2 3 Nominal Current 1 2 Nominal Current 2 5 Nominal Current 3 IF_INPUT RW 0 0 Nominal setting 1 AD2 RSSI IF is input to IF strips 2 IF_FRONT RW 0 0

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