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V850E2/ML4 CPU Board R0K0F4022C000BR User`s Manual
Contents
1. CHANGE SCALE MDO 7 0 5 5 2 5 1 12 610 54 1 02 P5 15 1 1 TIO C IO SSI SDCKE TA1 O3 ADCNV1 P5 AIINTP1G TA1 MITE1 TH CSIO RYI SDRAS TA1 04 0910 RYO ADCNV2 MDO0 UDI ROM writer P5 S INTP17 TA1 15 TE1 AURXD1 SDCAS TA1 05 MDO1 d P5 6 INTP18 TA1 IG TE1 BUSDWE TA1 O6 TXD1 MDO2 P5 7 INTPA9 TA1 ITITE1 ZIRXD1F LLDQM TA1 O7 MDO3 P5 B INTP20 TA1 IBILUDQM TA1 OB TXD1F MDO4 PS 9IINTP21 P5 9 INTP21 TA1 IS CSI1 SSI ULDQM TA1 OSIDMAAK2 MDOS P5_10 INTP22 TA1_110 CSI1_RYVUUDQM TA1 O10 DMATC2 CSH RYO1 MDO6 P5 11 INTP23 TA1 IT1 SCKT REFRQ TA1 011 0 4 MDO7 1 R19 520 P5 12 INTP24 TA1 12 SO1 BUSRQ TA1 O12 DMATCA 102 AW MCKO 5 P5 13 INTP25 TA1 H3 HLDAK TAT O13 MSEOO MSEOO 5 P5 14 INTP26 TA1 HA HLDRQISH TAT 014 MSEO1 MSEO 5 P5 15 INTP27 TA1 M5 TA1 015 3 6 P6 15 0 EVTI 5 Evro H 5 P6 O INTPO ETH CRS TAO IO TEO TIO TAO OO 1 INTP1 ETH COL TAO 11 TA0 O1 DCK TCK FLSCK 5 PG 2 INTPZ ETH I2 TEO TH TAO 02 DDITOUFLSVFLRXD 125 TDI 5 P6 3 INTP3 ETH TXD2 TAO I3 TA0 DDO TDO FLSO NW TDO
2. 0 8 OxAL R CHANGE Renesas Solutions Corp SCALE DRAWN CHECKED DESIGNED APPROVED ROKOF4022C000BR CAN 4 Serial port EEPROM LCD 6 DATE D ROKOF4022C000BR C B 12 05 15 P2 15 0 avec avec U10A UA R123 R122 HD74LVIGWI7A HDZALVIGWOZA avec 12V0C Ri24 2200 1 6 R125 DO P20 4 l Open drain NMI I 838 1000 PGFP5 E SWITCH D EE N _7616 6002PL gl avcc a 3 4 H siR A some vonz p 1 CP53 cC SCK T U108 R130 dus VDE NC R129 HD74LVIGWI7A HD74LV1GWO7A CLK ROJ 15 y lot use 2 FLMD1 124 FLMD1 Notused2 167 8131 a 22004 ma 4 FS P23 2 FLMDO FLMDO E ad 24 RESET ki At sm INTP1 j 835 1000 s ATA Rt SWITCH i 3vcc 3vcc Output g KE sl El unc 3 2
3. Number Function SW1 User DIP switch 4 package Refer to 2 12 for details SW2 Operation mode setting DIP switch 4 package Refer to Table 3 32 for settings SW3 External interrupt switch NMI Refer to 2 11 for details SWA External interrupt switch INTP1 input and ADTRG input Refer to 2 11 for details SW5 External interrupt switch INTP2 Refer to 2 11 for details SW6 Reset switch Refer to 2 15 for details SW7 Ethernet PHY setting DIP switch 8 package Refer to Table 3 33 for settings Table 3 31 Operation Mode Setting DIP Switch SW2 Settings Number Setting SW2 1 ON Set theV850E2 ML4 pin to high OFF Set theV850E2 ML4 MODES pin to low SW2 2 ON Set theV850E2 ML4 MODE2 pin to high OFF Set theV850E2 ML4 MODE2 pin to low SW2 3 ON Set theV850E2 ML4 FLMD1 pin to high OFF Set theV850E2 ML4 FLMD1 pin to low SW2 4 ON Set theV850E2 ML4 FLMDO pin to high OFF Set theV850E2 ML4 FLMDO pin to low Note set by default Table 3 32 Settings of the V850E2 ML4 Operation Mode Setting SW2 1 SW2 2 SW2 3 SW2 4 V850E2 ML4 operation mode MODE3 MODE2 FLMD1 FLMDO OFF OFF OFF OFF Normal operation mode L L L L Connectable with the E1 emulator OFF OFF OFF ON Flash memory programming mode CL L L H OFF OFF ON ON Boundary scan mode L L H H Setting prohibited for the ROKOF4022C000BR Comb
4. Notes 1 These pins are connected to through holes via zero ohm resistors installed by default 2 These pins are connected to through holes via zero ohm resistors NOT installed by default R20UTO778EJ0100 Rev 1 00 TzENESAS page 5of 26 May 31 2012 V850E2 ML4 CPU Board ROK0F4022C000BR Table 3 4 Application Header JA3 Pin Descriptions 2 2 3 Operational Specification Pin No Signal Name Signal connected to JA3 by default Other connection 37 P4 0 A16 TA1 08 P4 0 38 P4 1 17 P4 1 P5 11 SCK1 REFRQ TA1 0112 39 2 187 P4 2 P5 13 HLDAK TA1 013 40 P4 3 A19 P4 3 LED2 41 P4 4 A20 P4 4 LED3 7 A23 SCKOF 42 P4 5 21 50 P4 5 JA6 12 P5 0 24 5007 43 P4 6 A22 SO0F P4 6 SDRAM BAO JA6 9 P5 1 A25 ESO2 44 P4 8 BUSCLK P4 8 SDRAM CLK 45 P2 2 WAIT RXDO P2 2 E 14 52 46 P5 3 TA1 O3 SDCKE P5 3 SDRAM CKE 47 10 LUWR P4 10 P5 8 LUDQM TXD1F 48 P4_9 LLWR P4 9 P5_7 IRXD1F LLDQMITA1 I7 TA1 O7 49 P5 5 TE1 AI SDCAS P5 5 SDRAM CAS JA5 17 50 P5_4 INTP16 SDRAS TA1_14 P5 4 SDRAM RAS JA5 10 Notes 1 These pins are connected to through holes via zero ohm resistors installed by default 2 These pins are connected to through holes via zero ohm resistors NOT installed by default R20UT0778EJ0100 Rev 1 00 May 31 2012 RENESAS page 6of 26 V850E2 ML4 CPU Board ROK
5. 10 1 208V CHANGE Renesas Solutions Corp SCALE DRAWN CHECKED DESIGNED APPROVED UDI ROKOF4022C000BR Reset Push SW Power 5 6 DATE D ROKOF4022C000BR C B 12 05 15 12 12 3 234 123 ANI 11 6 D 15 0 P1 15 0 P2 15 0 P3 15 0 P4 15 0 P5 15 0 P6 15 0 P7 1 0 ANI 11 0 2 4 P2 15 5DA1 235 RESET 2 P5 PS 1 0 ANI 11 0 AVDD 3vcC AVDD 5VCC _FFC 26BMEP HONDA l lt _FFC 26BMEP HONDA lt _FFC 50BMEP HONDA lt R238 R239 R20 X OO PAM PS 6 a 1 P5 1T 24 P2 15 CANOTXD P2 14 SCL1 1 2 2 SCIaRX 2 P6 4 RS232TX 241 14 8189 PS P6 1 0 ANI 11 0 _FFC 24BMEP HONDA lt _FFC 24BMEP ll HONDA lt RIZA VV Y 00 RIZADO RS232RX 2 P2_14 CANORXD 24 CHANGE Renesas Solutions Corp SCALE DRAWN CHECKED DESIGNED APPROVED ROKOF4022C000BR Application Header 6 6 DATE 12 05 15 D ROKOF4022C000BR C B
6. nal 1 AF war kz ApF par 2 6 System Power svcc lip T5 SVCC RI28 _ CE13 10pF 25V 19 KLDX SMT2 0202 A Kycon 4 3 LEDO UB1111C Y Blue 5 D3 CP54 1NA148W 0 01pF 1 VLCF4020T 4R7N1R2 u24 TDK w 5 sw 6 15 8 16 R138 a 04 31 6k0 4 8188 MOUF 16V T ouF t6v FB 447 777 EN GND MZT34X NS EL 5 Ds CP58 Vref RL R2 RL 1NA148W 0 01yF lkR 10kR 1 12 12 VLCF4020T 4R7N1R2 025 5 5 sw _ 20 2147 _ cE21 R148 a D6 R148 asna T iouF 16V T220uF 6 3V D 4 EN GND R150 M2734X NS 3vcc EVDD R15 00 Sw EVDD OSCVDD 3 3V Ext ES ba GVS bos A2 2PA 2 54DSA VDD 1 rl LA i le Jl UVDD DVDD S 1 Fea BLM21PG300SNT 1 3AVDD 15 9 uPD60610 T 00 AVDD 16 9 1 1 BLM21PG300SNT AVDD CE23 10HF 16V 1 7 0 PLLVDD i BLM21PG3005NT CE24 10pF 16V 15 XG85 0331 NRO VSS AVss La Sa ae BLMZ1PG300SNT
7. Red P4 1 A17 INTPB TA1 19 1 OS CSIOF CS1 P1 1 D17 TAO H OCI INTPG TAO O1 Header SML 310MT Green LED3 SML 310VT P4_2 A18 INTP9 TA1_110 TA1_O10 CSIOF_CSO P1_2 018 TAO_12 TE0_TI INTP7 TAO_O2 IN SML 310DT Orange RI xd A BLA P4_S A19IINTP10 TA1_M1 CSIOF_RYITA1_O11 CSIOF_RYO P1_3 D19 TAO_I3 INTP8 TAO_O3 PPON Ri BMLCSOVT Red AW P4_4 A20INTP11 TA1_ 112 CSIOF_SSI TA1 012 P1_4 D20 TA0_14 TE0_AVINTP9 TAO_04 SML 310DT 15 SML 310YT Yellow 36 B BUSCLK lt gt 34 6 P5 15 0 S AZ1INTP12 TA1 H3 SIOF T 1 O13 6 A22 INTP13 TA1 MA SOOF TAT 014 P4_7 A23 INTP14 TA1_115 SCKOF TAT_015 BIBUSCLK P4 S9 LLBE LLWR P4_10 LUBE LUWR P4_11WRIRW 12 80 P4 13 CS1 57 IMATC5 CSI1F_CS6 0 ESO0 TA1_I0 SO0 A24 TA1_O0 P5 1 ESO2JTA1_IH SCK0 A25 TA1_O1 P1 5 D21 TAO IS INTPTOITAO O5 1 6 D22 TAO I6 TEO BUINTP11 TAO O6 P1 7 D23 TAO I7 INTP12 TA0 O7 P1 B D24 TAO IB TEO 2 P1_9 D25 TAO I9 INTP14 TAO O9 P1 10 D26 TAD ITOINTP15 TAO O10 P1 11 D27 TAO 111 INTP16 TAO O11 P1 12 028 112 INTP17 TAO O12 P1 13 D29 TAO 113 INTP18 TAO 013 P1 14 D30 TAD 114 INTP19 TAO O14 P1 15 D31 TA0 O15 52 RI ty SI R8 AMATO e usa 48 UDPE 3 ul 4 R10 70 UDMF AN UDMF 3
8. o El O UARTJO O d J6 B connector d Application headers o gt gt al Eth V850E2 ML4 thernet connector gt gt ER U19 SDRAM SW4 OETP1 SW5 JA3 FOr wO cs USBH SW6 RESET 1 402405 USB function USB host connector connector Figure 3 1 ROKOF4022C000BR Connector Assignments R20UT0778EJ0100 Rev 1 00 ENESAS page 1of 26 May 31 2012 V850E2 ML4 CPU Board ROKOF4022C000BR 3 Operational Specification 3 1 1 Application Headers JA1 to JA3 JA5 and JA6 The ROKOF4022C000BR includes through holes for mounting application headers JA1 to JAS and JA6 to which the V850E2 MLA I O pins are connected The standard MIL connectors can be implemented to the through holes to connect an expansion board Figure 3 2 shows the pin assignments and Table 3 1 to Table 3 6 lists the pin descriptions for the application headers JA1 to JA3 JAS and JA6 Figure 3 2 Application Header Pin Assignments JA1 to JA3 JA5 and JA6 R20UTO778EJ0100 Rev 1 00 244 NE SAS page 2of 26 May 31 2012 V850E2 ML4 CPU Board ROK0F4022C000BR Table 3 1 Application Header JA1 Pin Descriptions 3 Operational Specification Pin No Signal Name Signal connected to JA1 by default Other connection 1 5VCC 5VCC 2 GND GND 3 3VCC 3VCC 4 GND GND
9. 66 667MHz e On chip memories Flash memory 1MB On chip RAM 64KB H bus shared memory 64KB Flash cache 16KB Source voltage Internal 1 2V 1 0 3 3V 5V external supply when using the AD converter with 5 0V e Package 216 pin QFP 0 4mm pitch External memories SDRAM 16MB CS4 space EEPROM 8KB 12C bus interface Connectors Serial port connector D sub 9 pin RS232C Through holes CAN connector 3 pin CD connector 14 pin USB host connector Series A receptacle USB function connector Series Mini B receptacle ETHERNET connector 100Base T 8 pin RJ 45 E1 connector 14 pin Through holes for the expansion connector Application header JA1 JA2 26 pins for each 50 pins JA5 JA6 24pins for each Switches Reset switch 1 External interrupt switches 3 NMI INTP1 INTP2 e Operation mode setting DIP switch 1 4 package e Users DIP switch 1 4 package Ethernet PHY setting DIP switch 1 LED Potentiometer Power LED 1 User LEDs 4 connected with the I O port pins of the V850E2 ML4 Fthernet PHY LEDs 3 10kQPotentiometer 1 Resonator for CPU 10MHz e Oscillator for USB 48MHz Resonator for Ethernet PHY 25MHz Dimensions Dimensions 125mm x 170 mm Lamination Mounting form 4 layered double sided thickness 1 6mm Number of boards 1 R20UTO778EJO100 Rev 1 00 a2 AS Page 3 of 7 May 20 2012 ENES V850E2 M
10. ide view Side vie 9 5066 5 00000 Figure 3 6 Serial Port Connector J5 Pin Assignments on crossover cable by a male jack Table 3 11 Serial Port Connector J5 Pin Names on crossover cable by a male jack Pin No Signal Name Pin No Signal Name 1 NC 6 DSR 2 RXD 7 RTS 3 TXD 8 CTS 4 DTR 9 NC 5 GND Note Pins 4 to 6 and Pins 7 to 8 are loop back connected respectively R20UTO778EJ0100 Rev 1 00 244 NE SAS page 12of 26 May 31 2012 V850E2 ML4 CPU Board ROKOFA4022C000BR 3 Operational Specification 3 1 6 LCD Connector J6 The ROKOF4022C000BR includes the LCD connector 16 Figure 3 7shows the LDC connector J6 pin assignments and Table 3 12 lists the LCD connector pin names Top view of the component side Board edge Figure 3 7 LCD Connector J6 Pin Assignments Table 3 12 LCD Connector J6 Pin Names Pin No Signal Name Pin No Signal Name 1 GND 2 5VCC 3 NC 4 LCDRS P5 11 5 R W Pulled down by a 1k Q resistor 6 LCDE P5 10 7 NC 8 NC 9 NC 10 NC 11 LCDD12 P5 12 12 LCDD13 P5 13 13 LCDD14 P5 14 14 LCDD15 P5 15 R20UTO778EJ0100 Rev 1 00 244 NE SAS page 13of 26 May 31 2012 V850E2 ML4 CPU Board ROKOFA4022C000BR 3 Operational Specification 3 1 7 External Power Supply Connectors J7 and J12 to J14 The ROKOF4022C000BR includes four external power supply connectors J
11. P2 BIINTPS TA1 14 TE1 TI SHF TA1 O4 ADCNV2 161 P2 9 INTPA TA1 IS TE1 Os CSHF 80 JAS m C ANIOO P2_10 INTPS TA1_16 TE1_B PPON TA1_06 CSI1F_CS4 L lt gt USB JAM 88 amor P2_MINTPS TA1_I7 TE1_Z1 UCLKITA1_OT OSHE_OS5 59 3 Potentiometer 134 P2_12 TJ_10 SCLO RXDOF TJ_00 197 lt gt 7 ANIOS P2_13 TJ_M ADTRGO1 SDAO TJ_O1 TXDOF gt d Serial port 14 TJ I2IADTRG11 SCL1 CANORXD TJ 02 155 gt CAN er O ANIOB P2_15 TJ_I3 ADTRG21 SDA1 TJ_O3 CANOTXD 154 EEPROM Pa woes k lt Al 8 4 ANI10 MODE2 Operation mode JA5 Lia P8 FLMD1 22 setting switch IAJ 22 R20UT0778EJ0100 1 00 31 2012 Figure 2 1 V850E2 ML4 Block Diagram RENESAS page 2 of 20 V850E2 ML4 CPU Board ROKOF4022CO00BR 2 Function Specification 2 3 External Memory 2 3 1 SDRAM The ROK0F4022C000BR includes 16 MB SDRAM 2 Mword x 16 bit x 4 bank which is controlled by V850E2 ML4 memory controller CS4 The pins used for SDRAM control are also connected to the application headers JA3 JAS and JA6 as pins related to bus pins related to the SCI and pins related to timer respectively These pins cannot be used to avoid overlaps Uninstall the CS4 jumper JP11 when using the application headers Figure 2 2 shows the circuit configuration for the connection between the V850E2 MLA
12. R20UT0778EJ0100 Rev 1 00 TENESAS Page 6 of 7 May 20 2012 V850E2 ML4 CPU Board ROK0F4022C000BR 2 Function Specification 2 1 Functions Overview Table 2 1 lists the ROKOF4022COOOBR function modules Table 2 1 ROK0F4022C000BR Function modules 2 Function Specification Section 2 2 2 3 Function CPU External Memory Description V850E2 ML4 e Input XIN clock 10MHz e CPU clock Up to 200MHz Memory contoroller bus E bus clock Up to 66 667MHz SDRAM Interface Up to 50MHz Perepheral bus P bus clock Up to 66 667MHz e Internal memory Flash memory 1MB Internal RAM 64KB H bus shared memory 64KB Flash cache 16KB e SDRAM 16MB CS4 space e EEPROM 8KB I2C bus interface 2 4 1 0 Ports Connects the V850E2 ML4bus and port to the application header 2 5 Serial Port Interface Connects the V850E2 ML4 UART JO signal to the serial port connector 2 6 CAN Interface Connects the V850E2 ML4 CAN signal to the CAN connector via the CAN transceiver 2 7 LCD Interface Character LCD interface 2 8 USB Interface Connects the V850E2 ML4 USB signal to the USB connector 2 9 Ethernet Interface Connects the V850E2 MLA Ethernet MAC signal to the Ethernet connector via the PHY 2 10 Emulator Interface Connects the V850E2 ML4 OCD signal to the E1 connector 14 pin Enables debug evaluation with the E1 emulator 2 11 Switches e Use
13. RS232TX of the application header JA6 to the serial port connector J5 Table 3 23 shows the serial port transmitted signal select jumper JP5 settings Table 3 23 Serial Port Transmitted Signal Select Jumper JP5 settings Number Setting Description JP5 1 2 Connects the V850E2 ML4 P2_13 TXDOF to the serial port connector J5 2 4 Connects a 5 pin RS232TX of the application header JA6 to the serial port connector 45 set by default 3 2 1 5 P2 9 Select Jumper JP7 JP7 is a jumper to specify whether to use the V850E2 MLA P2 9 for the USB host control or for a 14 pin of the application header JA5 on the board Short circuit pins 1 and 2 of JP7 to use the USB host connector J1 and short circuit pins 2 and 3 of JP7 to use P2 9 as a 14 pin of the application header JAS Table 3 24 shows the P2 9 select jumper 7 7 settings Table 3 24 P2 9 Select Jumper JP7 Settings Number Setting Description JP7 1 2 Uses the USB host connector J1 2 3 Connects the V850E2 ML4 P2 9 to a 14 pin of the application header JA5 Note set by default R20UTO778EJ0100 Rev 1 00 244 NE SAS page 20of 26 May 31 2012 V850E2 ML4 CPU Board ROKOFA4022C000BR 3 Operational Specification 3 2 1 6 P2 10 Select Jumper JP9 JP9 is a jumper to specify whether to use the V850E2 MLA P2 10 of the USB host control or for a 23 pin of the application header
14. TXD2 TAO I3 TAO 18 E 79 P6 4 INTP4 ETH TXD1 TAO 14 0 AI DMATCO TAO O4 3 E 80 P6 5 ETH TXDO TAO I5 DMATC1 TAO O5 20 E 81 6 ETH TXEN TAO 16 BI DMAAKO TAO O6 2 E 82 P6 7 ETH TXCLK TAO I7 DMAAK1 TAO O7 E SW7 83 8 ETH TXER TJ 10 0 I8 TEO ZI TJ OO TAO O8 19 E 84 P6 9 ETH RXER TJ I1 TAO I9 TJ O1 TAO O9 20 E SW7 91 P6 10 RXCLK INTP21 TAO 110 0 010 SW7 92 P6 11 ETH RXDV INTP22 TAO 111 0 O11 25 E 93 12 ETH RXDO INTP23 TAO 112 0 O12 26 E SW7 Notes On board memory SD SDRAM E Ethernet U USB S CAN Serial LC LCD S L V Switches LED Potentiometer Not connected by default Connectable at a zero ohm resistor R20UT0778EJ0100 Rev 1 00 31 N SAS page 6 of 20 May 31 2012 V850E2 ML4 CPU Board ROK0F4022C000BR 2 Function Specification Table 2 4 I O Port Functions 3 5 V850E2 ML4 Application headers On board functions Pin No Pin name JA1 JA2 JA5 JAG M U C S LC S L V 94 13 ETH RXD1 INTP24 TAO O13 21 E 95 14 ETH RXD2 INTP25 TAO 114 0 O14 7 E SW7 96 15 ETH 115 0 015 22 SW7 97 P7 0 I2 INTP26 TJ O2 6 E 98 P7 1 I3 INTP27 TJ E 124 P8 5 ANI11 2 125 P8 4 ANI10 126 P8 3 ANIO9 12 SW1 127 P8 2 ANIO8 11 SW1 128 P8 1 ANIO7 10
15. 2012 V850E2 ML4 CPU Board ROKOFA4022C000BR 3 Operational Specification 3 2 Operating Components The ROKOF4022C000BR includes switches jumpers LEDs and a potentiometer as operating components 3 2 1 Jumpers JP1 JP2 JP4 JP5 JP7 to JP13 The ROKOF4022C000BR provides eleven jumpers JP1 JP2 JP4 JP5 and JP7 to JP13 3 2 1 1 P2_3 Select Jumper JP1 JP1 is a jumper to specify whether to use the V850E2 ML4 P2_3 for USB function control or for INTP1 SW4 and a 9 pin of the application header JA2 on the board Short circuit pins 1 and 2 of JP1 to use the USB function connector J3 and short circuit pins 2 and 3 of JP1 to use the P2_3 as INTP1 SW4 and a 9 pin of the application header JA2 Table 3 20 shows the P2_3 select jumper JP1 settings Table 3 20 P2_3 Select Jumper JP1 Settings Number Setting Description JP1 1 2 Uses the USB function connector J3 2 3 Connects the V850E2 ML4 P2_3 to INTP1 SW4 and a 9 pin of the application header JA2 Note set by default 3 2 1 2 Serial Port Received Signal Select Jumper JP2 JP2 is a jumper to switch signal wires the serial port received Short circuit pins 1 and 2 of JP2 when connecting the V850E2 MLA 2 3 to the serial port connector 15 Short circuit pin 2 and 4 of JP2 to connect a 6 pin RS232RX of the application header JA6 to the serial port connector J5 Table 3 21 shows the serial port received signal select ju
16. 5 AVDD AVDD 6 AVSS AVSS 7 AVDD AVDD 8 P2 3 INTP1 ADTRG20 P2 3 JP1 3 SWA INTP1 JA2 9 P1 14 TAO 0147 9 P8 O ANIOG P8 0 SW1 1 10 P8 1 ANIO7 P8 1 SW1 2 11 P8 2 P8 2 SW1 3 12 P8 109 P8 3 SW1 4 13 P3 0 A0 NC P5 21 14 P5 14 HLDRQ SM TA1 0147 NC P5 10 INTP22 TA1 010 15 P6 0 P6 0 Ethernet PHY POCRS 16 P6 1 P6 1 Ethernet PHY POCOLSD 17 P6 2 P6 2 Ethernet PHY POTXD3 18 P6 3 P6 3 Ethernet PHY POTXD2 19 P6 8 P6 8 Etherne tPHY POTXERR 20 P6 9 P6 9 Ethernet PHY PORXERR 21 P6 13 P6 13 Ethernet PHY PORXD1 22 P6 15 P6 15 Ethernet PHY PORXD3 23 P2 10 INTP5 TA1 16 TA1 O6 P2 10 USBH 24 NC NC 25 P2 15 SDA1 CANOTXD P2 15 JP10 1 EEPROM SDA 11 22 26 P2 14 SCL1 CANORXD P2 14 JP8 1 EEPROM SCL 12 INTP23 Notes 1 These pins are connected to through holes via zero ohm resistors installed by default and jumpers 2 These pins are connected to through holes via zero ohm resistors NOT installed by default R20UT0778EJ0100 Rev 1 00 May 31 2012 RENESAS page 3of 26 V850E2 ML4 CPU Board ROK0F4022C000BR Table 3 2 Application Header JA2 Pin Descriptions 3 Operational Specification Pin No Signal Name Signal connected to JA2 by default Other connection 1 RESET RESET Ethernet PHY E1 2 21 3 P2 O NMI P2 0 SW3 NMI P5 15 INTP27 TA 1
17. JA5 on the board Short circuit pins 1 and 2 of JP9 to use the USB host connector J1 and short circuit pins 2 and 3 of JP9 to use P2 10 as a 23 pin of the application header JA5 Table 3 25 shows P2 10 select jumper 7 9 settings Table 3 25 P2 10 Select Jumper JP9 Settings Number Setting Description JP9 1 2 Uses the USB host connector J1 2 3 Connects the V850E2 ML4 P2 10 to a 23 pin of the application header JA5 Note set by default 3 2 1 7 CAN EEPROM Select Jumper 8 is a jumper to specify whether to connect the V850E2 MLA P2 14 SCLI CANORXD to the CAN connector J4 and a 6 pin of the application header JA5 or to the EEPROM and a 26 pin of the application header JA1 on the board Short circuit pins 2 and 3 of JP8 when connecting the V850E2 ML4 P2 14 SCLI CANORXD to the CAN connector 74 and a 6 pin of the application and short circuit pins land 2 of JP8 to connect it to the EEPROM and a 26 pin of the application header JA1 Table 3 26 shows the CAN EEPROM select jumper JP8 settings Table 3 26 CAN EEPROM Switch Jumper JP8 Settings Number Setting Description JP8 1 2 Connects the V850E2 ML4 P2 14 SCL1 CANORXD to the EEPROM and a 26 pin of the application header JA1 2 3 Connects the V850E2 ML4 P2 14 SCL1 CANORXD to the CAN connector J4 and a 6 pinof the application header JA5 Note NM set by default 3 2 1 8 CAN EEPROM Sele
18. PORXD1 P6 12 INTP23 ETH RXDO AAA PORXDO 3AVDD 49 90 x4 220 P6 11 INTP22 ETH RXDV KA PORXDV 220 22 Z lt 2100x2 P6 10 ETH RXCLK zi PORXCLK GPIO3 2223 R259 P6 9 ETH RXER PORXERR E T Ethernet connector J2 220 P6 8 ETH TXER POTXERR GPIO9 TXP TD TD 229 TXN 7 TXCLK ANY POTXCLK P6_6 DMAAKO ETH_TXEN POTXEN 4 RD RXN RD 5 TAO OS ETH TXDO POTXDO e RCT P6_4 DMATCO ETH_TXD1 POTXD1 FG P6 3 ETH TXD2 POTXD2 GPIO11 y GND FG P6_2 ETH_TXD3 POTXD3 GPIO10 d AVSS AVSS AVSS 22 P6 1 ETH COL z R58 POCOLSDIGPIO19 CRS VAREL POCRS GPIO6 RESETB XCLKO 2 2 Refer to the supplemental circuit 25MHz Eug diagram for the power and GND t A E pins 2zxkQx3 VSS 09 VSS RESET 4 R261 LI 1518276 vss VSS 4 7kQ vss SW7 1 2 2 gt SWT 2 3 Application header JA6 SW7 3 SW7 4 E Q SWT 5 Application header JA5 SW7 6 SW7 7 7 SW7 8 201 RW Application header JA2 VSS Ethernet PHY setting DIP switch SW7 21 18 1075 18 93 Application header JA1 103 Optional z 1071 l 4 1070 Figure 2 8 Ethernet Interface Block Diagram R20UTO778bEJ0100 Rev 1 00 ENESAS page 14 of 20 May 31 2012 V850E2 ML4 CPU Board ROKOF4022CO00BR 2 Function Specification 2 10 Emul
19. PORXD1 PORXP RD AN PORXD2 GPIOB PORXN RD 5 u RIO We PORXD3 GPIO7 RCT 10 RIS AA 220 PORXERR NC FG EI 22 POTXCLK E POTXEN P6 15 P RXD3 PU PG l4 P RXD2 PU 26 porxpo P6 l0 PORXCLK PU BI POTXD1 ED 3 POTXD3 GPIO10 VDDIO Pu PU 35 POTXERR GPIO9 vopio 21 P6L12 PORXDO PD VDDIO P6 13 P RXDl PD 256 RESET ROSA 40 RESETB aa VDD33ESD 20 t AEJ VDDA33REG 46 SE R78 XCLK1 de ibi AMU AVOUT15 1 Bl u VDDA15 8 d o E VDDAPLL 42 1 6 353 Samo 09 2299 pvouris 27 J E uu Le ETI 66 0015 7 22 py aula 5524 224 254 584 25 000005006 AEL i seso ses ses Sm 25MHz MII Sen eo RMIT Soo 569 959 9 CHANGE Renesas Solutions Corp ROKOF4022C000BR SCALE DRAWN CHECKED DESIGNED APPROVED USB LAN SDRAM C a Z D ROKOF4022C000BR C B war La Us LS 26 P2 15 CANOTXD 26 P2 14 CANORXD lt 2 P2 13 TXDOF 2 P2 12 RXDOF C avcc CAN u20 R92 HA13721RPJE 5v
20. Pin No Pin name JA1 JA2 JA3 JA5 JA6 M E U CS LC S L V 170 P2 1 INTPO ADTRGOO CSI1F RYI BCYST TXDO RYO la 210013 171 P5 15 INTP27 TA1 I15 TA1 O15 3 24 LC 172 5 14 INTP26 TA1 M4 HLDRQ SM TA1 O14 14 23 7 LC 173 P5_13 INTP25 TA1_113 HLDAK TA1_013 39 22 LC 174 P5_12 INTP24 TA1_112 SO1 CPUBUSRQ TA1_012 DMATC4 21 LC 175 P5_11 INTP23 TA1_111 SCK1 REFRQ TA1_011 DMAAK4 38 20 10 LC 176 P5_10 INTP22 TA1_110 CSI1_RYI UUDQM TA1_010 DMATC2 CSI1_RYO M B 177 P5 9 INTP21 TA1 I9 CSI1 SS ULDQM TA1 O9 DMAAK2 13 180 P5_8 INTP20 TA1_I8 LUDQM TA1_O8 TXD1F 9 47 8 SD 181 P5 7 INTP19 TA1 I7 TE1 ZI RXD1F LLDQM TA1 07 022 48 9 7 SD 182 P5 6 INTP18 TA1 16 TE1 BI SDWE TA1 OG TXD1 20 26 18 SD 183 P5 5 INTP17 TA1 1 1 AI RXD1 SDCAS TA1 O5 49 17 SD 184 P5 4 INTP16 TA1 I4 TE1 TI1 CSIO RYI SDRAS TA1_04 CSIO_RYO s 25 187 P5 3 INTP15 TA1 I3 TE1 TIO CSIO SSI SDCKE TA1 46 SD 188 P5 2 ESO3 TA1 12 510 54 1 02 28 SD 189 P5 1 ESO2 TA1 M SCKO A25 TA1 O1 43 190 P5 O ESOO TA1 10 500 24 1 OO 24 42 191 P4 15 CS3 DMATC5 CSMF CS06 10 27 192 P4 14 82 CS7 26 28 45 193 P4 13 081 27 194 12 RD 25 195 P4 11 WR RW 26 196 10 LUBE LUWR 47 197 P4_9 LLBE LLWR 48 198 P4_8 BUSCLK 44 SD 205 P4_7 A23 INTP14 TA1_115 SCKOF TA1_015 13 41 11 sD 206 P4_6 A22 INTP13 TA1_114 SOOF TA1_014 11 43 9 SD 207 P4_5 A21 INTP12 TA1_113 SIOF
21. lt 0Q gt VA 4 149 external interrupt Y d Switch SW3 P Drain e Vss 09 x4 3 VV WWW yw 23 13 09 no d Optional P2 2 1 13 SCK1F P2 3 INTP1 ADTRG20 P2 0 NMI Application header JA1 ADTRG20 Application header JA2 NMI INTP1 INTP2 Application header JA5 TA1 13 Application header JA6 USB function connector J3 VBus R20UTO778bEJ0100 Rev 1 00 May 31 2012 Figure 2 10 Push Switch Block Diagram RENESAS page 16 of 20 V850E2 ML4 CPU Board ROK0F4022C000BR 2 12 LEDs and Potentiometer 2 Function Specification The ROKOF4022C000BR includes four user LEDs LEDO to LED3 a USB host bus LED LED4 three Ethernet PHY LEDs LED6 to LED8 and a power LED LED9 The user LEDs are controlled by V850E2 ML4 P1 4 P1 5 P4_3 and P4_4 The ROK0F4022C000BR also includes a potentiometer which is connected to the ANIOS of the A D converter Figure 2 11 shows LED user LED and potentiometer block diagram fs Du V850E2 ML4 tev Leos ee P1 4 TAO 14 TEO xx oe P1 5 021 15 3 A19 4 20 2 25 JA6 15 JA3 40 41
22. 2012 V850E2 ML4 CPU Board ROK0F4022C000BR 2 6 CAN Interface 2 Function Specification The ROK0F4022C000BR includes a 3 pin CAN connector J4 The V850E2 ML4 CAN0TXD is connected to J4 connector via the jumper a zero ohm resistor and the CAN transceiver and the CANORXD is connected to J4 connector via the jumper a zero ohm resistor and the level shifter and the CAN transceiver The CANOTXD and the CANORXD are also connected to the application header JA5 When using the application header JA5 remove zero ohm resistors on the CAN connector side The CAN signals both at the CAN connector and the application header cannot be used The V850E2 ML4 SDA1 CANOTXD and the SCLI CANORXD pins are also connected to the EEPROM and the application header JA1 and remove or install the jumper to specify the pin function The CAN connector and the EEPROM cannot be used at the same time When storing the Ethernet MAC address to the EEPROM both the CAN connector and the Ethernet MAC address cannot be accessed at the same time Figure 2 5 shows the CAN interface block diagram V850E2 ML4 P2_14 SCL1 CANORXD P2_15 SDA1 CANOTXD P7 0 INTP26 P6 12 INTP23 P6 11 INTP22 SVCC p 1 Optional L ad 22kQ lt 2
23. 28 SDRAM Jumper JP11 Settings Number Setting Description JP11 Short Uses the SDRAM Open Uses the multiplexed signal with the SDRAM connection signal on the side of the application header FH Note R set by default 3 2 1 10 OCD Jumper JP12 JP12 should be open to use 3 2 1 11 PG FP5 Connection Jumper JP13 JP13 is a jumper to specify the connection of the PG FP5 the V850 internal flash writing tool Short circuit pins 2 and 3 when using the 5 and short circuit pins 1 and 2 in any other case of the PG FP5 Table 3 29 shows the PG FP5 connection jumper J13 settings Table 3 29 PG FP5 Connection Jumper JP13 Settings Number Setting Description JP13 1 2 Uses other than PG FP5 2 3 Uses the PG FP5 Note R set by default R20UTO778EJ0100 Rev 1 00 tENESAS page 22of 26 May 31 2012 V850E2 ML4 CPU Board ROK0F4022C000BR 3 2 2 Switches 3 Operational Specification The ROKOF4022C000BR includes a user DIP switch SW1 an operation mode setting DIP switch SW2 four push switches SW3 to SW6 and an Ethernet PHY DIP switch SW7 Table 3 30 lists switches on the ROKOF4022C000BR Table 3 31 lists settings of the operation mode setting DIP switch SW2 Table 3 32 lists settings of the V850E2 MLA operation mode setting Table 3 33 lists settings of the Ethernet PHY setting DIP switch SW7 Table 3 30 Switches on the ROK0F4022C000BR
24. 3 This page is intentionally left blank REVISION HISTORY V850E2 ML4 CPU Board ROKOF4022CO000BR User s Manual Description Summary 1 00 May 31 2012 First edition issued V850E2 ML4 CPU Board ROK0F4022C000BR User s Manual Publication Date Rev 1 00 May 31 2012 Published by Renesas Electronics Corporation 24 NESAS SALES OFFICES Renesas Electronics Corporation http www renesas com Refer to http www renesas com for the latest and detailed information Renesas Electronics America Inc 2880 Scott Boulevard Santa Clara CA 95050 2554 U S A Tel 1 408 588 6000 Fax 1 408 588 6130 Renesas Electronics Canada Limited 1101 Nicholson Road Newmarket Ontario L3Y 9C3 Canada Tel 1 905 898 5441 Fax 1 905 898 3220 Renesas Electronics Europe Limited Dukes Meadow Millboard Road Bourne End Buckinghamshire SL8 5FH U K Tel 44 1628 651 700 Fax 44 1628 651 804 Renesas Electronics Europe GmbH Arcadiastrasse 10 40472 D sseldorf Germany Tel 49 211 65030 Fax 49 211 6503 1327 Renesas Electronics China Co Ltd 7th Floor Quantum Plaza No 27 ZhiChunLu Haidian District Beijing 100083 P R China Tel 86 10 8235 1155 Fax 86 10 8235 7679 Renesas Electronics Shanghai Co Ltd Unit 204 205 AZIA Center No 1233 Lujiazui Ring Rd Pudong District Shanghai 200120 China Tel 86 21 5877 1818 Fax 86 21 6887 7858 7898 Renesas Electr
25. 99 a 3VCC gt z PG FP5 E1 connector J10 mE o connector NOT OCD connector NOT installed installed Operation mode sana omis FLMD1 FLMDO FLMDO SW2 MODE2 i FLMD1 4 FLMDO 11 5 220 WCC SEES mus PNIS VSS Potentiometer User DIP switch VR1 10kQ SW1 10kQ ANIO5 o AVSS P8 O ANIOG 10 P8 1 ANIO7 P8_2 ANI08 P8_3 ANIO9 1 P8_4 ANI10 P8 5 ANI11 22kQ x4 o o VSS Figure 2 11 R20UT0778EJ0100 Rev 1 00 May 31 2012 LED and Potentiometer Block Diagram RENESAS page 17 of 20 V850E2 ML4 CPU Board ROKOF4022CO00BR 2 Function Specification 2 13 Power Module On ROKOF4022C000BR 5V power supply is input to the board to generate 3 3V and 1 2 V using the regulator A 3 3V is input to the AVDD although a 5V can be provided from the external power supply by removing the zero ohm resistor Figure 2 12 show the ROK0F4022C000BR power supply circuit block diagram IVDD V850E2 ML4 5V 1 2V IVDD DC power IVDD 1 L7 jack J9 External J14 uad power PLLVDD nput supply vss EVDD VSS 09 EVDD L3 ye T L OSCVDD External J7 SN e DVDD L5 OL LJ 3AVDD AVDD External 09 AVDD power 6 supply AVDD L8 VSS AVSS Note PLLVSS OSCVSS
26. AS TXDOF 4 1 ANIOS P2_B INTP3 TA1_I4 TE1_TI1 SI1F TA1_O4 6 SClaTX 3 4 RS232TX 6 P2_9 INTP4 TA1_IS TE1_AIDIOCITA1_OS CSI1F_CS3 16478 PB O ANIOG P2 10 5 1 16 1 BIO PPON TA1 CS4 vent latete i sw P8 1 07 P2 11 6 1 7 1 ZIO UCLK TA1 O7 CSMF 55 USB odd EPG avcc AGS 4104 P8 2 ANIOB P2 12 TJ I SCLO RXDOF TJ 00 P2 SIOCI 3 P2_14 CANORXD 4 6 OMRON PB 3 ANIOS P2 13 TJ I ADTRGO1 SDAQ TJ O1 TXDOF sw2 HWP 3P G 4 6 P8 A ANIO P2 1471 IZ ADTRG11 SCL1 CANORXD TJ O2 2684164 P2 10 k D P2 14 SCL1 4 6 2 ANT PB S ANI11 P2 18 TJ I3 ADTRG21 SDA1 TJ O3 CANOTXD OMRON USB CTRL3 JP10 HWP 3P G z 2 i MODES 1 10 PPON 3 P2 15 4 6 MODE2 x ze 400 00 00 o O O O O D 2 D 0 o 0 D O 0 D 0 N 0 3 FLMD1 LE P2 15 50 1 4 6 145 5 A A D A D D A D D D A A A D A D D A D B D D A A D A 9 5 4 5 x E x2 lt lt ESPERES t FEER AS i EEr d a FLMDO avcc SG 8002JF_48MHz EPSON E FLMDO 5 om 4 FLMD1 5 4J vccourd AER Ben S eem 22KO O eH Ps RS 22KQ ANT ROSA ANIZ AVDD EVDD OSCVDD PLLVDD R253 22K 3 22pF 22pF R254 A AA22kO 10 0000005006 P2 P3 _ 1 P4 Los Los Los Los ka Lon iem CE2 15 CE3 me Lor kal CE4 19 Lezo Loa a yes La pem ka CES Pai CES AEL 22 pur pur pur pu pw pepe pue Pe pe pu pue A
27. Caps CP Decoupling Caps L Inductor Renesas Solutions Corp ROKOFA022COOOBR D ROKOF4022C000BR_C B pee 3 CHANGE aav aav L 2v 12 011520 36 RAT 22kQ MNR14 220 AVDD VD VDD OSCVDD PLLVDD P00 1 ARA Poo 11 8 DO POIT 2 AW LT P0 1 2 LAW Di 833 LS Poa WS Ut 4 PO3 4 PO3 4 P3 150 V850E2 ML4 3 AN AW Renesas MNR14 22k0 RA4 MNR14 220 eg 88888888888 8 88 8 888888888888 8 es Ws TEN Su 995860559656 AS SSSSSSSSSSSS gt 0 D0 AW ANI ze 200000000000 5 88 5 3 PO 1 D1 by amp 2 A2 lt 2 02 4 Ed mam RAS MNR14 22kQ RAG MNR14 2 5 A5 PO 5 D5 urs FAN P3 6 A6 6 06 2 AW PONE 2 AN E LAW EET EE ORTU P uH MNR14 22k0 RAS MNR14 4 11 A11 CSI0F_CS7 P0 11 D11 LEM LEN P3 12 A12 CSIOF 86 P0 12 012 NES WWW P3713 M13 CSIOF_CS5 PO 13 D13 PO 15 E MW PO 15 41 MW P3_14 A14 CSIOF_CS4 P0 14 D14 AW AW P3_15 A15 CSIOF_CS3 15 D15 86 P4 15 0 P1 15 0 8 LED2 SML 310VT LEDO R3 acc P4 O AT6 INTP7 TA1 IB TA1 OB CSIOF 52 P1 0 D16 TAO IO TEO TIO INTPS TAO Applicati
28. High Impedance Inter Equipment bus Input Output Infrared Data Association Least Significant Bit Most Significant Bit Non Connection Phase Locked Loop Pulse Width Modulation Special Function Registers Subscriber Identity Module Universal Asynchronous Receiver Transmitter Voltage Controlled Oscillator All trademarks and registered trademarks are the property of their respective owners Table of Contents About This Manual rotar dn dee RUD er OR Dp 4 uj IOVOIVIOW RR 1 1 11 OVEIVICW roro ndo imn dae tad ettam 1 1 12 ROKOF4022CO000BR 1 2 1 3 ROKOF4022C000BR External Specification n a 1 3 1 4 Block Diagram for 0 4022 000 1 4 1 5 huie 1 5 1 6 Absolute Maximum Ratings iet e eunte 1 6 1 7 Operating Conditions idc ere ee eee d bed ev ee 1 6 22 Eunction SpecifICatioh e reet ER b t RM met m ret fei HM 2 1 2 1 FUNCUONS OVERVICW A aa Aa Su aka 2 1 2 2 eiu cuc 2 2 2 3 External Memory k Zayn Ert prt 2 3 2 3 1 SDRAM m igon ua ea 2 3 2 32 EEPROMI dota ph lio E eA Mice 2 4 24 ES 2 5 2 5 Serial Port Interfae tintas 2 10 2 6 GAN Inter
29. Jack J9 Pin Assignments Table 3 17 DC Power Jack J9 Pin Names Pin No Signal name 1 GND 2 GND 3 5VCC 3 5VCC R20UT0778EJ0100 Rev 1 00 TENESAS page 160f 26 May 31 2012 V850E2 ML4 CPU Board ROKOFA4022C000BR 3 Operational Specification 3 1 9 E1 Connector J10 The ROKOF4022C000BR includes a 14 pin El connector 110 to connect the El emulator Figure 3 10 shows the El connector 710 pin assignments Table 3 18 lists the El connector 710 pin names Top view of the component side Board edge J10 Figure 3 10 E1 Connector J10 Pin Assignments Table 3 18 E1 Connector J1 Pin Names Pin No Signal Name Pin No Signal Name 1 TCK 8 VDD 2 GND1 9 TMS FLMD1 3 TRST 10 RESET2 4 FLMDO 11 TRDY 5 TDO 12 GND2 6 NC1 13 RESET1 7 TDI 14 GND3 R20UTO778EJ0100 Rev 1 00 ENESAS page 17of 26 May 31 2012 V850E2 ML4 CPU Board ROKOFA4022C000BR 3 Operational Specification 3 1 10 GND Connector J15 The ROKOF4022C000BR includes GND connector 715 Figure 3 11 shows the GND connector J15 pin assignments Table 3 19 lists the GND connector J15 pin names Top view of the component side Board edge Figure 3 11 GND Connector J15 Pin Assignments Table 3 19 GND Connector J15 Pin Names Pin No Signal Name 1 GND 2 GND 3 GND R20UTO778EJ0100 Rev 1 00 244 NE SAS page 18of 26 May 31
30. SW1 129 P8 0 ANIOG 9 SW1 134 ANIO5 VR1 138 ANIO1 4 139 ANIOO 144 XI 2 145 2 148 RESET 1 149 P2 3 17 SW3 154 P2 15 TJ 13 ADTRG21 SDA1 TJ 25 EE CAN 155 P2 14 TJ IZ ADTRG11 SCL1 CANORXD TJ O2 26 6 EE CAN 156 P2 13 TJ M ADTRGO1 SDAO TJ O1 TXDOF 6 UR 157 P2 12 TJ IO SCLO RXDOF TJ OO 8 UR 158 P2 11 INTPG TA1 I7 TE1 ZIO UCLK TA1 7 CS5 HF 159 P2 10 INTP5 TA1 16 TE1 BI PPON TA1 O6 CSI1F 54 23 160 P2 9 INTPA TA1 15 1 AI OCI TA1 O5 CSI1F 16 14 161 P2 8 INTP3 TA1 I4 TE1 TI1 SI1F TA1 04 8 162 P2 2 1 I3 TE1 TIO SCK1F DMATC3 TA1 10 23 13 SW5 163 P2 6 5 1 I2 SO1F DMAAK3 TA1 O2 6 164 P2 5 502 1 M TA1 O1 CSMF CS2 14 12 165 P2 4 5 1 10 00 1 OO0 UUWR CSMF CS1 18 11 F 166 P2_3 INTP1 ADTRG20 ULBE ULWR CSI1F_CSO 8 9 F SW4 167 P2_2 WAIT ADTRG10 RXDO CSI1F_SSI 45 12 Notes M On board memory SD SDRAM E Ethernet U USB C S CAN Serial LC LCD S L V Switches LED Potentiometer Not connected by default Connectable at a zero ohm resistor R20UT0778EJ0100 Rev 1 00 TENESAS page 7 of 20 May 31 2012 V850E2 ML4 CPU Board ROK0F4022C000BR 2 Function Specification Table 2 5 I O Port Functions 4 5 V850E2 ML4 Application headers On board functions
31. TA1_013 42 12 208 P4_4 A20 INTP11 TA1_112 CSIOF_SSI TA1_012 41 LED3 209 4 3 A19 INTP10 TA1 I11 CSIOF RYI TA1 O11 CSIOF RYO 40 LED2 Notes On board memory SD SDRAM E Ethernet 0 USB S CAN Serial LC LCD S L V Switches LED Potentiometer Not connected by default Connectable at a zero ohm resistor R20UT0778EJ0100 Rev 1 00 31 N SAS page 8 of 20 May 31 2012 V850E2 ML4 CPU Board ROK0F4022C000BR 2 Function Specification Table 2 6 I O Port Functions 5 5 V850E2 ML4 Application headers On board functions Pin No Pin name JA1 JA2 JAS JAG M E LC S L V 210 P4_2 A18 INTP9 TA1_110 TA1_010 CSIOF_CSO 39 211 P4 1 A17 INTP8 TA1 19 1 O9 CSIOF CS1 38 212 P4 0 A16 INTP7 TA1 18 1 O8 CSIOF CS2 37 15 213 P3_15 A15 CSIOF_CS3 16 214 P3_14 A14 CSIOF_CS4 15 215 P3 13 A13 CSIOF CS5 14 216 12 A12 CSIOF CS6 13 SD Notes On board memory SD SDRAM E Ethernet 0 USB S CAN Serial LC LCD S L V Switches LED Potentiometer R20UTO778bEJ0100 Rev 1 00 May 31 2012 RENESAS page 9 of 20 V850E2 ML4 CPU Board ROKOF4022CO00BR 2 Function Specification 2 5 Serial Port Interface On the ROK0F4022C000BR the V850E2 ML4 UARTJO is connected to the serial port connector 15 via the RS 232C transceiver Also pins 5 and 6 of the application header JA6 can be connected to the serial p
32. default R20UT0778EJ0100 Rev 1 00 May 31 2012 RENESAS page 4of 26 V850E2 ML4 CPU Board ROKOFA4022C000BR 3 Operational Specification Table 3 3 Application Header JA3 Pin Descriptions 1 2 Pin No Signal Name Signal connected to JA3 by default Other connection 1 P3 0 A0 P3 0 2 P3 1 A1 P3 1 SDRAM A0 3 P3 2 A2 2 SDRAM A1 4 P3 3 A3 P3 3 SDRAM A2 5 P3 4 A4 4 SDRAM 6 P3 5 A5 P3 5 SDRAM A4 7 P3 6 A6 P3 6 SDRAM A5 8 P3 7 A7 P3 7 SDRAM A6 9 P3 8 A8 P3 8 SDRAM A7 10 P3 9 A9 P3 9 SDRAM A8 11 P3 10 A10 P3 10 SDRAM 9 12 P3 11 A11 P3 11 SDRAM A10 13 P3 12 A12 P3 12 SDRAM A11 14 P3 13 A13 P3 13 15 P3 14 A14 P3 14 16 P3 15 A15 P3 15 17 PO 0 DO PO 0 SDRAM 000 18 P0_1 D1 PO 1 SDRAM DQ1 19 PO 2 D2 PO 2 SDRAM DQ2 20 PO 3 D3 SDRAM DQ3 21 4 04 PO 4 SDRAM DQ4 22 PO 5 D5 5 SDRAM DQ5 23 PO 6 D6 PO 6 SDRAM DQ6 24 PO 7 D7 PO 7 SDRAM DQ7 25 12 RD P4 12 26 11 AWR RW P4 11 P5 6 SDWE TE1 27 P4_13 CS1 P4_13 15 53 28 14 527 P4 14 P5 2 0847 29 8 8 PO 8 SDRAM DQ8 30 PO 9 D9 PO 9 SDRAM DQ9 31 PO 10 D10 PO 10 SDRAM DQ10 32 PO 11 D11 PO 11 SDRAM DQ11 33 PO 12 D12 PO 12 SDRAM DQ12 34 PO 13 D13 PO 13 SDRAM DQ13 35 PO 14 D14 PO 14 SDRAM DQ14 36 PO 15 D15 PO 15 SDRAM DQ15
33. gt P5 10 INTP22 TA1 O10 LODE 9 RW Fized to write P5 11 SCK1 REFRQ TA1 O11 e ett LCDRS 4 3 5 kQ lt 100kQ 7 55 vss Application header JA1 EKSI 14 LAM DAC1 Application header JA2 0Q AAA Application header JA3 A A17 l VV 18 l l Application header JA5 19 M2 Up 20 M2 Un 21 M2 vp 22 M2 Vn 23 M2 Wp 24 M2 Wn 09 x2 Application header JA6 AN 7 SCIbRX 71 Optional VA 8 scibTx E ede 10 Scibck Figure 2 6 Character LCD Interface Block Diagram R20UTO778bEJ0100 Rev 1 00 ENESAS page 12 of 20 May 31 2012 V850E2 ML4 CPU Board ROKOF4022CO00BR 2 Function Specification 2 8 USB Interface The ROKOF4022C000BR includes the USB host connector series A receptacle 71 and USB function connector series Mini B receptacle J3 The V850E2 MLA USB host bus is connected to the series A receptacle and the OCI and PPON are connected to the USB host bus switch The OCI signal is connected to the application header JA5 as port and timer signals which can be selected instead of using the USB host bus switch The PPON signal is connected to the application header JA1 as IRQ signal which can be selected instead of using the USB host bus switch The V850E2 MLA USB function bus is connected to the series Mini B receptacle and 2 4 and are used to control the USB function The P2 4 and the INTPI are also connec
34. headers The signals connected to JA1 15 to JA1 22 JA2 20 JA6 1 and JA6 2 are also connected to the device U17 as the Ethernet PHY signals These signals cannot be used as other pin functions When using these signals as other pin functions remove the zero ohm resistor R261 and the 22 ohm resistors between JA1 15 JA1 16 JA1 20 to JA1 22 R61 R58 R259 R68 R70 respectively and install a 22 ohm resistor to R276 When pull ups and pull downs are required for the signals of JA1 17 to JA1 19 JA2 7 JA2 20 JA6 1 and JA6 2 use the resistor with up to 10k ohms The operational guarantee does not cover any remodeling including a remove install of a zero ohm resistor to change the application header signal connection R20UT0778EJ0100 Rev 1 00 May 31 2012 RENESAS page 8of 26 V850E2 ML4 CPU Board ROKOFA4022C000BR 3 Operational Specification 3 1 2 USB Connectors J1 and J3 The ROKOF4022C000BR includes a series A receptacle 71 as USB host connector and a series Mini B receptacle J3 as USB function connector Figure 3 3 shows USB Connector J1 and J3 Pin Assignments Table 3 7 and Table 3 8 list USB host connector J1 pin names and USB function connector J3 pin names respectively 12345 Top view of the component side c Side view Figure 3 3 USB connector J1 and J3 Pin Assignments Table 3 7 USB Host Connector J1 Pin Names Pi
35. peration mode setting DIP switch SW2 5 61700 PPT FLMODO 5 connector J8 FLMOD1 TDI _ RESET 8 FLMODO 9 FL MODI o ol TMS FLMOD1 5 gt T re Po AE 4 q gt gt 11 aa 9 TRDY VSS VSS 12 9 al GND2 a RESET MES MA Optional ENDS VSS Figure 2 9 E1 Connector Block Diagram R20UT0778EJ0100 Rev 1 00 ae ENESAS page 15 of 20 May 31 2012 V850E2 ML4 CPU Board ROK0F4022C000BR 2 11 Switches 2 Function Specification The ROKOF4022C000BR includes push switches for reset external interrupts NMI INTP1 and INTP2 and ADTRG input and DIP switches for users operation mode setting and Ethernet PHY The user DIP switch is connected to P8 0 to P8 3 The operation mode setting DIP switch executes settings for the V850E2 ML4 FLMDO FLMD1 MODE2 and MODES signals Refer to Figure 2 11 for these DIP switches and Figure 2 8 for the Ethernet PHY DIP switch Figure 2 10 shows the push switch block diagram related to the external interrupt input V850E2 ML4 10 9 2 4 7kQ 2209 _ 09 A gt gt AAA INTP2 external E EE Open interrupt switch SW5 E Drain e VSS 3vcc 10kQ L 4 7kQ 2209 02 gt AAA e 5 ANN 4 INTP1 external y interrupt switch SW4 Drain ves 3VCC 3vcc p 162 166 lt 10 9 4 7kQ 55a 2209
36. supplied LED6 Yellow Ethernet PHY LED LINK LED7 Yellow Ethernet PHY LED ACT LED8 Yellow Ethernet PHY LED DUPLEX LED9 Blue Power LED illuminates when the 5VCC is supplied R20UTO778EJ0100 Rev 1 00 31 N SAS page 25of 26 May 31 2012 V850E2 ML4 CPU Board ROK0F4022C000BR 3 Operational Specification 3 3 Dimensions Figure 3 12 shows the ROKOF4022C000BR dimensions k WP 8 E 3 2 3 3 7 00 x4 3 12 x6 3 20 x4 320 x6 2 7mm LOJN me 70 5 79 5mm t 85mm t 150 5mm y 163mm 170mm Figure 3 12 ROKOF4022C000BR Dimensions R20UT0778EJ0100 Rev 1 00 May 31 2012 RENESAS page 260f 26 V850E2 ML4 CPU Board ROK0F4022C000BR Appendix Appendix ROK0OF4022C000BR Schematics R20UTO778EJ0100 Rev 1 00 LENESAS 1 31 2012 TITLE INDEX Digital GND GND CPU V850E2 ML4 Clock User port USB LAN SDRAM CAN Serial port EEPROM LCD UDI Reset Push SW Power 5VCC Digital 5V Application Header 4 2 EVDD 3 3V for CPU I O VDD 3 3V for UVDD USB DVDD Debug OSCVDD 3 3V for Oscillator 3AVDD Analog 3 3V for uPD60610 1 2700 12V IVDD 1 2V for CPU Core PLLVDD 1 2V for PLL AVDD Analog 3 3V or 5V for ADC Analog GND AVss 1 Not mounted Fixed Resistors RA Resistor Array C Ceramic Caps CE Tantalum Electrolytic
37. the European Union s Waste Electrical and Electronic Equipment WEEE Directive 2002 96 EC As a result this equipment including all accessories must not be disposed of as household waste but through your locally recognized recycling or disposal schemes As part of our commitment to environmental responsibility Renesas also offers to take back the equipment and has implemented a Tools Product Recycling Program for customers in Europe This allows you to return equipment to Renesas for disposal through our approved Producer Compliance Scheme To register for the program click here http www renesas com weee This page is intentionally left blank About This Manual 1 Purpose and Target Readers This manual is designed to provide the user with an understanding of the functions and operating specifications of this CPU board A basic knowledge of electrical circuits logical circuits and microcomputers MCUs is necessary in order to use this manual This manual is composed of an overview of the CPU board its functional and operating specifications Carefully read all notes described in the body of text in the manual The Revision History summarizes the modifications and additions to the previous versions Refer to the text of the manual for details The following documents apply to the V850E2 ML4 CPU Board ROKOF4022C000BR Document Type Description Document Title Document No User s Manual Describes functions devices m
38. 0F4022C000BR 3 Operational Specification Table 3 5 Application Header JA5 Pin Descriptions Pin No Signal Name Signal connected to JA5 by default Other connection 1 P8 4 ANI10 P8 4 2 P8 5 ANI11 P8 5 3 ANI00 ANI00 4 ANI01 ANI01 5 P2 15 SDA1 CANOTXD P2 15 JP10 3 U20 TxD 6 P2_14 SCL1 CANORXD P2_14 JP8 3 U21 A P7 26 7 NC NC 8 NC NC 9 P5 7 INTP19 RXD1F LLDQM P5 7 SDRAM DQML 10 P5_4 INTP16 SDRAS TA1_14 P5 4 SDRAM RAS JA3 50 11 P2 4 1 IO TA1 00 P2 4 JP4 3 P1 15 TA0 O15 12 P2 117 2 5 I P1 11 TAO0 011 13 P2_7 TA1_13 SCK1F P2 7 JA2 10 JA2 23 14 P2 9 1 15 P2 9 JP7 3 P1 13 TA0 O13 15 P4 0 A16 TA1 08 P4 0 16 NC NC 17 P5 5 TE1 AI SDCAS P5 5 SDRAM CAS JA3 49 18 P5 6 SDWE TE1 BI P5 6 SDRAM WE 19 P5 10 INTP22 TA1 O10 P5 10 LCD J6 6 20 P5 11 SCK1 REFRQ TA1 O11 P5 11 LCD J6 4 JA6 10 21 P5 12 SO1 TA1 O12 P5 12 LCD J6 11 JA6 8 22 P5 13 HLDAK TA1 O13 P5 13 LCD J6 12 23 P5 14 HLDRQ SM TA1 O14 P5 14 LCD J6 13 JA6 7 24 P5 15 INTP27 TA1 O15 P5 15 LCD J6 14 Notes 1 These pins are connected to through holes via zero ohm resistors installed by default 2 These pins are connected to through holes via zero ohm resistors installed by default and jumpers 3 These pins are connected to through holes via zero ohm resistors NOT installed by default R20
39. 1 9 ET Connector J10 ied Hee de sete I 3 17 3 1 10 GND Gonnector J15 3 lh c m REG eR EO e eR Q EE e ob 3 18 3 2 Operating CompoOmennts cicer e tdi 3 19 3 2 1 Jumpers JP1 JP2 JP4 JP5 JP7 to JP13 n n na 3 19 3 2 2 Seit 3 23 3 2 3 Potentiometer un m tti tee anc ied e b am ER PEE 3 25 3 2 4 A O 3 25 3 3 DiMensiOnS tdt Leeds e a ll 3 26 V850E2 ML4 CPU Board ROKOFA4022C000BR 1 Overview 1 Overview 1 1 Overview The V850E2 MLA CPU Board ROKOF4022C000BR hereinafter called the ROKOF4022C000BR is the evaluation board designed to evaluate features and performance of the V850E2 MLA of Renesas Electronics 32 bit single chip microcontroller and to conduct development and evaluation for its application software The features of the ROKOF4022COOOBR are described below 1 1 1 Features of the ROK0F4022C000BR Usually includes 16MB SDRAM 16 bit bus connect and an 8KB EEPROM as external memories Usually includes a serial port connector RS 232C a USB connector an ETHERNET connector and a CAN connector as peripheral interfaces of the V850E2 ML4 The USB connector normally equips a Series A receptacle to evaluate the USB host controller and a Series Mini B receptacle to evaluate the USB function controller e The data bus the address bus and the pins of peripheral functions of
40. 2 HD74LVIGWI7A HD74LV1GWO7A 53 HTST 107 01 L DV CP56 Samtec 0 1uF 2 TCK 1 2 TMS 22 TMS FLMD1 2 TDI TDI NC1 E tj Too 5 TDO RESET2 be PANE 2 TRST s 130 TRST 2 TRDY 4 9 1 LIZ 1 3vcc 3vcc avcc g RESET U14A U15A R144 al R142 R143 HD74LVIGWI7A HD74LV1GWO7A 777 22kQ drain R145 AA 2200 1 1 8146 O P27 El ANS k 2 5767004 2 OCD sws 835 1000 INTP2 3vcc E al UAB MER cese SWITCH i HD74LV1GW17A g TDI 1 3 8 GND1 O JP12 2 HWP 2P G None ES NES R149 E 1 D avec 22k0 FLMDO Open drain p Evro REP 144 EVTO RESET PB LORE 2 H 1189 avec NC1 2 MCKO HIT Nc2 HE El RISO VER 447 Har 2 MSEOO MSEO1 NC4 i HD74LVAGWITA HD74LV1GWO7A MDO0 MDOO aL hes ynon gT MDO2 MDO10 28 MDO3 MDO11 MDO4 MDO12 20 MDOS MDO13 MDO6 MDO14 MDO7 MDO15 So SS us 4 2 MDO 7 0 avec T Power On Reset cP62 JP13 HWP 3P G 4 177 1 7 4 fc gt 236 ba AAAR159 2 00 E 4 Ue HDZALVAGTOBA 77 Renesas swe 835 1000 RNAS1957BFP 77 HD74LV1GWO7A aly LT avec EVDD 12VCC ka la Los pan tes cars jm
41. 2k0 vo vecs trarnsceiver CAN a aXe 1 AV A X 3 RXD e GND DIR e CANH E 51209 210 vss vss CANL S 5 22kQ L gt 22 VSS JP10 gt oQ AAA 4 0982 Application header 5 AAA RAAN i 6 NAA CAN1RX 5 CAN1TX e EEPROM e Application header CVV AN 26 IIC SCL VA 25 ic SDA R20UTO778bEJ0100 Rev 1 00 May 31 2012 Figure 2 5 CAN Interface Block Diagram RENESAS page 11 of 20 V850E2 ML4 CPU Board ROKOF4022CO00BR 2 Function Specification 2 7 LCD Interface The ROK0F4022C000BR includes a 14 pin character LCD connector J6 The V850E2 MLA P5 10 5 15 control the character LCD The signals are connected to the application headers JA5 and JA6 as timer and SCI signals The functions of these application headers are not available when using the LCD connector Remove the LCD connector to use the application headers Figure 2 6 shows the character LCD interface block diagram V850E2 ML4 P5 12 501 1 O12 e P5 13 HLDAK TA1 O13 P5 14 HLDRQ SM TA1 O14 P5 15 INTP27 TA1 O15 LCD connector J6 LCDD15_14 13 100014 LCDD13 12 0 11 100012 10 9 5VCC ul
42. 5 4 INTP4 ETH TXDI TAO 14 04 S ETH IS DMATCI TAO 05 DMS TMS TMS 5 P6 G ETH TXEN TAO IG TEO 06 DRSTITRST 118 gas 72 5 7 ETH TXCLK TAO 7 1 0 O7 TRDY E NW TRDY 5 B ETH TXER TJ 10 IB TEO ZI TJ OB P6 9 ETH RXER TJ I9 TJ O1 TAO O9 10 ETH RXCLK INTP21 TAO 10 O10 11 ETH RXDV INTP22 TAO 111 0 O11 avcc avcc 12 ETH RXDO INTP23 TAO 112 TA0 O12 P6 13 ETH RXD1 INTP24 TAO 113 TA0 013 P6 14 ETH RXD2 INTP25 TA0 H4 TAO O14 RESET 148 JRESET 3 5 6 6 27 P6 15 ETH RXD3 TAO 115 O15 38 P7 1 0 ero 37 O ETH_MDCIT ITP26 TJ 0 seer ET T 7 O ETH J I2 INTP26 TJ O2 w 1s Pinche PLi 98 A ETH MDIO TJ_ISIINTP27 TJ opea Em usd 6 ANI 1 0 P2 OS interru avon P2_1 INTPO ADTRGOO CSI1F_RYIBCYST TXDO CSI PF_RYO 1L0 etter 4 4 2 12IRXDOF 4 P2 2WAIT ADTRG10 RXDO CSI1F SSI P2_3 INTP1 3 6 SClaRX a RS232RX 6 b ANIOO P2_3 INTP1 ADTRG20 ULBE ULWRICSI1F_CSO P2_4 ESOO TA1_IO UUBE TA1_OO UUWRI CSI1F_CS1 JPS FEGABMER R28 ANIO2 P2 SIESO TA1 52 ced ANV ANIOS 2_6 1_ I2ISO1F DMAAK3 TA1 O2 ADCNVO Use CTRL HUI 4 la 04 P2_7 INTP2 TA1_I3 TE1_TIO SCK1F DMATC3 TA1_O3 ADCNV1 P2 AJUDPF 3 lt P2
43. 50E2 ML4 P3 PO 0 DO _1 1 1 p1 E P3 2 A2 2 02 3 03 28 4 A4 PO 4 04 5 A5 PO 5 D5 SDRAM lt gt 12 P3 6 46 PO 6 D6 lt gt P3_7 A7 77 32 m lt gt 8 08 33 pa 99 9 34 lt N 10 A10 10 D10 ne gt h P3_11 A11 CSIOF_CS7 P0_11 D11 gt P3 12 A12 CSIOF CS6 PO 12 D12 P3 13 A13 CSIOF CS5 PO 13 D13 P3_14 A14 CSIOF_CS4 14 014 lt gt 213 ps 15 15 PO 15 D15 E JAS L lt gt 212 pa QJA16 INTP7ITA1 IB TA1 OB CSIOF CS2 P1 0 D16 TAO I0 TEO O0 99 P4_1 A17 INTP8 TA1_I9 TA1_O9 CSIOF_CS1 P1_1 D17 TAO_M OCIINTPS TAO_O1 EE P4_2 A18 INTP9 TA1_MO TA1_O10 CSIOF_CSO P1 2 D18 TAO I2 TEO TIVINTP7 TAO O2 5 JAG 2091 pa 3 A19 INTP10 TA1_I11 CSIOF_RYVTA1_011 CSIOF_RYO P1_3 D19 TAO_I3 INTP8 TAO_O3 PPON 208 112 080 SSUTA1 012 P1 4 D20 TAO 04 P4_S A21 INTP12 TA1_113 SIOF TA1_013 P4 5 D21 TAO I5 INTP10 TAO 05 P4 G A22 INTP13 TA1 114 600 014 P1 6 D22 TAO I6 TEO B INTP11 TAO O6 205 7 A23 INTP14 TA1_I15 SCKOF TA1_O15 P4 7 D23 TAO I7 INTP12 TA0 O7 P4 8 BUSCLK 1 BID24 TAO 1 ZVINTP13 TAO 99 9 LLBE LLWR P4 9 025 I9 INTP14 TAO O9 P4 10 LUBE LUWR P4 10 D26 TA0 MO INTP15 TAO 010 65 MANRIRW P1_11 027 TAO_11 INTP16 TA0_O11 P4 12 R
44. 7and 712 to 714 to apply SV 3 3V 1 2V power and the A D converter power directly from external source not via the DC power jack 79 J7 and 712 to J14 connectors are not installed by default When operating the ROKOF4022C000BR by supplying 5V power from the external supply connector 77 do not connect the AC adaptor to the DC power jack J9 When supplying 3 3V power from the external supply connector J12 to the board remove the zero ohm resistor R155 Alternatively remove the zero ohm resistor R156 to supply the A D converter power from the external supply connector 713 or remove the zero ohm resistor R162 to supply 1 2V power from the external supply connector 714 to the board Figure 3 8 shows the external power supply connectors J7 and J12 to J14 pin assignments Table 3 13 to Table 3 16 list the external power supply connectors J7 and J12 to J14 pin names Top view of the component side Board edge e e J13 J7 1 o9 2 edge Figure 3 8 External Power Supply Connectors Pin Assignments R20UTO778EJ0100 Rev 1 00 244 NE SAS page 14of 26 May 31 2012 V850E2 ML4 CPU Board ROK0F4022C000BR Table 3 13 External Power Supply Connector J7 Pin Names 3 Operational Specification Pin No Signal Name Pin No Signal Name 1 5VCC 5V power supply 2 G
45. 83 H FF83 H FFAO H FFAO H FF3F H FF3F H FAOO H FAOO H F9FF H F981 H F981 H F980 H F980 H F980 H F980 H F97F H F97F H 8000 H 8000 Figure 1 3 Memory Mapping R20UT0778EJ0100 Rev 1 00 134 NE SAS Page 5 of 7 May 20 2012 V850E2 ML4 CPU Board ROKOFA4022C000BR 1 Overview 1 6 Absolute Maximum Rating Table 1 2 shows the absolute maximum rating on the ROK0F4022C000BR Table 1 2 Absolute Maximum Rating Symbol Item Value Remarks VCC 5V system power supply voltage 0 5V to 6 0V Reference voltage VSS 3VCC 3 3V system power supply voltage 0 5V to 4 1V Reference voltage VSS only direct supply 1 2VCC 1 25V system power supply voltage 0 5 to 1 6V Reference voltage VSS only direct supply Topr Operating ambient temperature OC to 50C Do not expose to condensation or corrosive gases Tstg Storage ambient temperature 20C to 60C Do not expose to condensation or corrosive gases Note The ambient temperature is the air temperature immediate to the board 1 7 Operating Conditions Table 1 3 lists the operating conditions on the ROKOF4022C000BR Table 1 3 Operating Conditions Symbol Item Value Remarks VCC 5V system power supply voltage 4 75V to 5 25V Reference voltage VSS Maximum consumption voltage on Up to 1 5A the board Topr Operating ambient temperature OC to 50C Do not expose to condensation or corrosive gases Note The ambient temperature is the air temperature immediate to the board
46. C D ens Vi 0 C o OO N LENESAS ROKOF4022C000BR V850E2 ML4 CPU Board User s Manual Renesas Microcomputer V850E2 ML4 Microcontroller Rev 1 00 All information contained in these materials including products and product specifications represents information on the product at the time of publication and is subject to change by Renesas Electronics Corporation without notice Please review the latest information published by Renesas Electronics Corporation through various means including the Renesas Electronics Corporation website http www renesas com Renesas Electronics www renesas com Rev 1 00 May 2012 10 11 12 Notice Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information Renesas Electronics has used reasonable care in preparing the information included in this document but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the i
47. D P4 12 D28 TA0 l12 INTP17 TAO O12 JA2 131551 P4 18 D29 TA0 M3 INTP18 TAO O13 2 gt P4 14 CS2IDMAAKBICSMF CS7 P1 14 D30 TAO MA INTP19 TAO 014 13 lt gt JA2 1 15 CSS DMATCBICSMF CS6 P4 15 D31 TA0 H5 INTP20 TAO 015 4 JA2 C 1904 ps 0 ESOO TA1_10 SO0 A24 TA1_00 upph 92 7 lt 188 ps tIESOZITA1 H SCKO A2S TA1 O1 upom 91 lt gt USE 188 P5_2 ESOS TA1_12 SI0 C54 TA1_O2 ADCNVO uper H8 lt gt lt gt 187 pg sIINTPAS TA1 IS TE1 TIO CSIO SSI SDCKE TA1 OS ADCNV1 JAS ra PS_4 IINTP16 TA1_14 TE1_TI1 CSIO_RYVSDRAS TA1_04 CSIO_RYO ADONV2 is 2183 5 5 AVRXDI SDCASITA1LOS gt lt gt 182 ps 6 INTP18 TA1 I6 TE1 BI SDWEITA1 OG TXD1 107 gt L lt A p5_7 INTP19 TA1_I7 TE1_ZI RXD1F LLDQM TA1_O7 106 gt L lt gt ps 2 I8 LUDQMWTA1 OB TXD1F mpos 109 gt lt gt ps gINTP21 TA1 I9 CSI1_SSVULDQMITA1 4 104 lt gt 18 Ps_10 INTP22 TA1_110 CSM_RY UUDQM TA1_O10 DMATC2 CSI1_RYO moos 103 sas P5_11 INTP23 TA1_I11 SCK1 REFRO TA1_O11 DMAAK4 MDO6 gt ak Lop 22 124 PS_12INTP24 TA1_112 S01 BUSRO TA1_O12 DMATOA MDO 10 UDI E1 and OCD Em P5 13 INTP25 TA1 H3 HLDARITA1 013 MCKO JA6 E lt 12 ps 14 INTP26 TA1 MA HLDRQ SH TA1 014 MsEOO 113 ROM writer PG FPS L IAJ ps 15 INTP27 TA1 115 TA1 015 MsEOo1 110 OCD an
48. DQ7 AS 006 4 005 004 A2 A1 002 A0 Dao 40 NC1 NC2 E P5 3 DCKE P53 26 SIBUSCLK VDD A vob H4 VDD CP45 46 CP47 H VDDQ H 89 VDDQ 8888 4 41 0 4HF 0 tyF rh a 8 8 8 8 LED MODE B 0000 8 8 Linka E E FD 6210 FEES MOS ADOBE ART avec Activity GPTO4 3 q 3 5 3 gt PS 9IINTP21 Ei SAYDO E Ethernet X s wa d TE 128 P7 sl uPD60610 lt Renesas 9 El 3 p gl ES P70 ss SIS ale 26 P6 15 0 MDC sel 464 MDIO POLINKLED GPIO0 y Ne INT GPIO4 sw7 34 E E zz 2 POCRS GPIO6 GPIO14 rri mi i R58 ppp 220 POCOLSD GPIO19 alal ole 88 ee 26 EE 1 R65 ayy 220 15 PORXCLK GPIO3 Porxp H TD 3 15 BU R66 Wood 25 PORXDV POTXN 4 TD 4 13 P69 P613 Res MW220 21 PORXDO 6 LA 1 P6 7 P614 R69 AWV220 18
49. EE pins are connected to VSS SDRAM EEPROM EVDD 1 External J12 Other devices and power connectors supply CAN Level shifter WiColoring of Power Supply Lines test pin 5V system power supply line USB host interface 3 3V system power supply line 1 _ _ Optional through hole 1 2V system power supply line Character LCD AVDD Power supply line EVDD or external supply Figure 2 12 Power Supply Circuit Block Diagram R20UT0778EJ0100 Rev 1 00 ENESAS page 18 of 20 May 31 2012 V850E2 ML4 CPU Board ROK0F4022C000BR 2 14 Clock Module 2 Function Specification The ROK0F4022C000BR connects the 10MHz resonator to the V850E2 MLA and X2 pins and the 48MHz oscillator to the UCLK pin A clock input can be provided to the EXTAL pin via the application header JA2 In this case remove the zero ohm resistor of X1 R35 and install a zero ohm R2 not installed by default A pull up resistor R29 can be installed if needed Figure 2 13 shows the ROK0F4022C000BR clock module block diagram V850E2 ML4 Optional ua o Application header JA2 Ro 2 R34 CON EXTAL 2 7 I 09 VSS VSS P4_8 BUSCLK P2_11 UCLK Oscillator 48MHz Application header JA3 Figure 2 13 Clock Module Block Diagram R20UTO778EJ0100 Rev 1 00 LENESAS May 31 2012 page 19 of 20 V850E2 ML4 CPU Board ROK0F4022C000BR 2 15
50. FF Set PORXDO pin to low 00 device uses address 00xxx for SMI SW7 8 ON Set PORXD1 pin to high 01 device uses address 01xxx for SMI OFF Set PORXD1 pin to low 10 device uses address 10xxx for SMI 11 device uses address 11xxx for SMI Note O set by default R20UT0778EJ0100 Rev 1 00 May 31 2012 RENESAS page 24of 26 V850E2 ML4 CPU Board ROKOFA4022C000BR 3 Operational Specification 3 2 3 Potentiometer The ROKOF4022C000BR includes a potentiometer to evaluate AN105 input Table 3 34 lists the information of the potentiometer model installed on the ROKOF4022C000BR For more details refer to the datasheet provided from the manufacturer Table 3 34 Potentiometer Number Part Number Manufacturer VR1 CT 6ETV10K 9 NIDEC Copal Electronics Corporation 3 2 4 LEDs The ROKOF4022C000BR includes four user LEDs LEDO to LED3 a USB host bus LED LED4 three Ethernet PHY LEDs LED6 to LED8 and a power LED LED9 Table 3 35 lists LEDs on the ROKOF4022C000BR Table 3 35 LEDs on the ROK0F4022C000BR Number Color Description Remarks LEDO Green User LEDO illuminates when P1 4 outputs low level signal LED1 Orange User LED1 illuminates when P1 5 outputs low level signal LED2 Red User LED2 illuminates when P4 3 outputs low level signal LED3 Red User LED3 illuminates when P4 4 outputs low level signal LED4 Yellow USB host bus LED illuminates when the 5VCC is
51. K0F4022C000BR 2 Function Specification 2 4 Ports On ROKOF4022C000BR the V850E2 ML4 I O ports are connected to the application headers Table 2 1 to Table 2 6 list the I O port functions The unused pins on the ROKOF4022C000BR are not listed Some of the I O ports are connected to devices I O connectors switches and LEDs on the board Refer to Chapter 3 Operational Specification for details Table 2 2 I O Port Functions 1 5 V850E2 ML4 Application headers On board function Pin No Pin name JA1 JA2 JA3 JA5 JA6 M E U 5 LC S L V 3 MODE2 SW2 4 MODE3 SW2 7 11 A11 CSIOF CS7 12 SD 8 P3 10 A10 11 SD 9 P3 9 A9 10 SD 10 8 A8 9 SD 11 7 A7 8 SD 12 P3 6 A6 7 SD 13 5 A5 6 SD 14 4 A4 5 SD 15 P3 3 A3 4 SD 16 2 A2 3 SD 17 P3 1 A1 2 5 18 0 0 13 1 22 FLMDO SW2 23 FLMD1 SW2 25 Po 0 DO 17 SD 26 1 01 18 5 27 Po 2 02 19 5 28 PO 3 03 20 SD 29 4 04 21 SD 30 PO 5 05 22 SD 31 Po 6 06 23 SD 32 Po 7 07 24 SD 33 8 08 29 SD 34 9 09 30 SD 35 PO_10 D10 31 SD 38 11 D11 32 SD 39 PO 12 D12 33 SD 40 PO 13 D13 34 SD 41 PO 14 D14 35 SD 42 PO 15 015 36 SD Notes On board memory SD SDRAM E Ethernet 0 USB S CAN Serial LC LCD S L V Switches LED Potentiometer Not c
52. L4 CPU Board ROKOFA4022C000BR 1 Overview 1 4 ROKOF4022CO000BR Block Diagram Figure 1 2 shows the ROK0F4022C000BRsystem block diagram USB host USB function Serial port connector M connector Ethernet connector El connector connector Resonator 25MHz PHY USBH UARTJ0 CAN connector 9Ve 3 3V C PORT A ar V850E2 ML4 EEPROM 200MHz 8KB Resonator CPU 10MHz CS4 CS4 space for SDRAM Oscillator 8 16 bits 16 bits USB 48MHz DC DC gt 3 3V Memory controller bus E bus Up to 66 67MHz 1 2V SDRAM interface Up to 50MHz for CPU specification 3 3V 8 16 bits AVDD converter 3 3V or 5V Power source 5V external supply selection Application header Figure 1 2 System Block Diagram R20UTO778EJO100 Rev 1 00 a2 AS Page 4 of 7 May 20 2012 ENES V850E2 ML4 CPU Board ROK0F4022C000BR 1 Overview 1 5 Memory Mapping Figure 1 3 shows the memory mapping on the V850E2 MLA and the ROKOF4022C000BR V850E2 ML4 ROKOF4022C000BR cum E H 1000 H 1000 H OFFF H OFFF User area CS4 space 64 H ODOO H OCOO ir dd SDRAM area 16MB H OBFF H OBFF CS3 space 64MB User area CS2 space 64MB User area CS1 space 32MB User area H FF84 H FF84 H FF
53. LE pur Ter p por pur jid pe p pepe Eur x1 gt UVDD nvon Renesas Solutions Corp ROKOF4022C000BR PU V E2 ML4 DRAWN CHECKED DESIGNED APPROVED CPU 850 2 6 DATE D ROKOF4022C000BR C B 12 05 15 1 2 en drain output 5vcc 43 2025 2 LEDS SML 310MT 2 P2 10PPON 4 our2 8 4 AAA 5 2 P2 9 lt 2 ne 7 GND out USB Host 22k 4 5 NC2 CP32 gt 1500 6 0 4uF UBA 4R D14T 4D H veus H 2 UDMH t D FGI 2 UDPH D 4 GND FRAME rH A l 01 HZM6 224MFA 85 IAE 27 USB Function VIH Min EVDD 0 8 2 64V 13 4 40V 1 8kR 1kR 1 8kR 2 829V 54819 0872 5 00V 1 8kR IkR 1 8kR 3 214V MOLEX 5 25V 1 8kR IKR 1 3 375V 4 TP 1D USB ID 2 P2_3 INTP1 14 vBus FG3 UDMF 21 D FG2 8 2 UDPF 3 10 FGI g GND FRAME D2 _HZM6 2Z4MFA D u18 EVDD HD74LV1GT126A Renesas 2 P2_4 UDPF 1 oE Hb 3 amp 2 2 6 D 15 0 26 15 0 SDRAM 16MB 2 6 15 0 ute 2 4 6 P5 15 0 ie BA1 0015 BAO 0014 DQ13 A11 DQ12 A10 DQ11 9 0010 099 AT Das
54. ND Table 3 14 External Power Supply Connector J12 Pin Names Pin No Signal Name Pin No Signal Name 1 EVDD 3 3V power supply 2 GND Table 3 15 External Power Supply Connector J13 Pin Names Pin No Signal Name Pin No Signal Name 1 AVDD 5V power supply 2 GND Table 3 16 External Power Supply Connector J14 Pin Names Pin No Signal Name Pin No Signal Name 1 IVDD 1 2V power supply 2 GND Note When supplying 5V from the external power supply connector J7 do not connect AC adapter to DC power jack J9 The ROKOF4022C000BR and AC adapter may be destroyed when the power is supplied from the external power supply connector J7 with the AC adapter connected When supplying 3 3V 1 2V power and the A D converter power from the external power supply connector J12 J13 J14 make sure to remove the zero ohm resistors R155 R156 and R162 The ROKOF4022C000BR may be destroyed when 3 3V 1 2V and the A D converter power is supplied from the external power supply connector 412 J13 andJ14 with these resistors installed R20UT0778EJ0100 Rev 1 00 May 31 2012 RENESAS page 15of 26 V850E2 ML4 CPU Board ROKOFA4022C000BR 3 Operational Specification 3 1 8 DC Power Jack J9 The ROK0F4022C000BR includes a DC power jack J9 Figure 3 9shows the DC power jack pin assignment Table 3 17 lists the DC power jack pin names Top view of the Board edge component side Figure 3 9 DC Power
55. O15 4 GND GND 5 NC NC 6 P2 6 SO1F P2 6 _ P2 13 TXDOF 14 INTP25 TAO 114 0 O14 P6 14 Ethernet PHY PORXD2 P2 8 SMF P2 8 _ P2 12 RXDOF 9 P2 3 INTP1 ADTRG20 P2 3 JP1 3 SWA INTP1 JA1 8 P1 3 INTP8 TAO I3 TAO P5 8 LUDQM TXD1F 40 P2 7 INTP2 TA1 I3 SCK1F P2 7 SW5 INTP2 P4 15 53 JA2 23 JA5 13 41 P1 9 TAO I9 TAO O9 1 9 6 22 800 3 12 P2 1 CSI1F RYI CSI1F RYO TXDO P2 1 13 P1 10 TAO 0107 P1 10 7 A23 SCKOF E 44 P1 11 TAO 0117 P1 11 P2 1 2 15 P1 12 0 O12 P1 12 P1 14 0 0143 i P1 1 6 O1 16 P1 13 TA0 013 P1 13 P2 9 TA1 153 17 P1 14 TAO O14 P1 14 P1 12 TA0 O12 B 18 P1 15 0 015 P1 15 P2 4 1 IO TA1 O0 Ni 19 P1 1 INTPG TAO O1 P1 1 20 P6 5 TAO O5 5 EtherPHY PO TXDO P5 6 SDWE TE1 BI 21 P1 O TEO TIO INTP5 P10 22 P1 2 0 12 P12 JA6 14 P5 7 INTP19 RXD1F LLDQM 23 P2_7 INTP2 TA1_13 SCK1F P2 7 SW5 INTP2 P1 8 TEO ZI INTP13 TAO I8 TAO JA2 10 JA5 13 24 P5 0 24 500 5 0 25 P1 4 TAO I4 TEO AI INTP9 P14 LEDO 26 P1 6 D22 TAO I6 TEO BI INTP11 6 JA6 16 14 CS2 Notes 1 These pins are connected to through holes via zero ohm resistors installed by default 2 These pins are connected to through holes via zero ohm resistors installed by default and jumpers 3 These pins are connected to through holes via zero ohm resistors NOT installed by
56. R 2 Function Specification 2 9 Ethernet Interface The ROK0F4022C000BR includes the Ethernet connector J2 via PHY The V850E2 MLA Ethernet related signals are connected to the application headers JA1 JA2 and JA6 as port signals When using the Ethernet related signals as port signal of JA1 remove the zero ohm resistor R261 and the 22 ohm resistors between JA1 15 16 and 20 to 22 and the PHY R61 R258 R259 R68 and R70 respectively and install a 22 ohm resistor at R276 When pull ups and pull downs are required for the signals of JA1 17 to 19 use the resistor with up to 10k ohms The MAC address can be stored in the EEPROM of the ROKOF4022C000BR When storing the MAC address in the EEPROM the CAN cannot be use Figure 2 8 shows the Ethernet interface block diagram V850E2 ML4 2 Ethernet PHY 017 xD LEDS 3309 x3 P7_1 ETH_MDIO MDIO POLINKLED GPIOO ANN P7 0 ETH MDC INT GPIO4 1 CTS 1 GPIO14 T AN 229 P6 15 ETH RXD3 AA PORXD3 GPIO7 220 220 AA gt P5_9 INTP21 P6 14 INTP25 ETH RXD2 e zi PORXD2 GPIO8 13 ETH RXD1 Me R68
57. Reset Module 2 Function Specification The ROKOF4022C000BR reset module generates RESET signal using the power on reset and reset switch SW Figure 2 14 shows the ROK0F4022C000BR reset module block diagram E1 connector J10 RESET2 RESET1 P PG FP5 connector NOT installed d Open drain output RESET P OCD connector NOT installed 4 gt 22kQ b RESET p 1 3vcc System reset IC lt 4 TKQ 259 0 1uF Reset switch 10kQ 0 1uF 2 uF 1 1 vss MReset IC output delay time td 0 34 x Cd pF 34ms Min 16ms Max 70ms MReset IC output detect voltage Ra 15kQ Rb 10kQ gt Vs 1 25 x 9 0 3 125 V gt o A V850E2 ML4 Ethernet PHY RESETB Application header JA2 1 RESET Figure 2 14 Reset Module Block Diagram R20UTO778bEJ0100 Rev 1 00 May 31 2012 RENESAS page 20 of 20 V850E2 ML4 CPU Board ROKOFA4022C000BR 3 Operational Specification 3 Operational Specification 3 1 Connector Overview Figure 3 1 shows the connector assignments for the ROKOF4022C000BR CAN connector Serial port connector LCD connector 4 E e J5 RS 232C 4 h i Character LCD Serial port CAN d
58. UT0778EJ0100 Rev 1 00 May 31 2012 RENESAS page 7of 26 V850E2 ML4 CPU Board ROK0F4022C000BR 3 Operational Specification Table 3 6 Application Header JA6 Pin Descriptions Pin No Signal Name Signal connected to JA6 by default Other connection 1 P1 7 INTP12 P1 7 2 P6 6 DMAAKO P6 6 Ethernet PHY POTXEN 3 P6 4 DMATCO P6 4 Ethernet PHY POTXD1 4 NC NC 5 RS232TX JP5 4 RS232TX JP5 4 6 RS232RX JP2 4 RS232RX JP2 4 7 P5 14 HLDRQ SM TA1 014 P5 14 J6 13 LCD JA5 23 P5 7 INTP19 RXD1F LLDQM 8 P5 12 SO1 TA1 O12 P5 12 J6 11 LCD JA5 21 P5 8 LUDQM TXD1F 9 P4 6 A22 SO0F P4 6 SDRAM BAO P2 1 5 RYI CSIF RYO BCYST JA3 43 10 P5 11 SCK1 REFRQ TA1 O11 P5 11 J6 4 LCD JA5 20 11 P4 7 A23 SCKOF P4 7 SDRAM BA1 12 4 5 21 80 P4 5 JA3 42 P2 2 WAIT RXDO 13 P1 8 TEO ZI INTP13 TAO IB TAO O8 P1 8 P2 1 5 RYI CSI RYO BCYST 14 P1 2 TAO 12 P12 JA2 22 15 P1 5 D21 TAO 15 1 5 LED1 16 P1 6 D22 TAO 16 TE0 BI INTP11 P1 6 JA2 26 17 P2 0 NMI NC 18 NC NC 19 NC NC 20 NC NC 21 NC NC 22 NC NC 23 5VCC NC 24 GND GND Notes 1 These pins are connected to through holes via zero ohm resistors installed by default 2 These pins are connected to through holes via zero ohm resistors NOT installed by default Precautions on using application
59. and the SDRAM Note The items of rising and falling of the bus clock do not satisfy with the requirement specification for the SDRAM on the ROKOF4022C000BR Only the ROK0F4022C000BR which have no operational problem are delivered We do not guarantee operation of the ROK0F4022C000BR when users apply it to their system Users should carefully execute evaluation on their system and determine its applicability 22kQ x6 1 V850E2 ML4 2 5 16 SDRAM 4 7 A23 6 A22 14 nid 2 Mword 16 bit x 4 bank 12 A12 1 A1 BA1 BAO A11 A0 P5 3 SDCKE CKE P4 8 BUSCLK CLK P5 254 cs P5 4 SDRAS RAS P5 5 SDCAS q CAS P5 6 SDWE q WE P5 8 LUDOM DQMH P5_7 LLDQM DQML PO 15 D15 PO 0 DO 1 0015 0 0 2 plication header B2 11 0 CKE CLK CS4n RASn CASn RDWRn WRHn DQMH WRLn DQML DQ15 DQ0 plication header JA2 Application header JA5 IRQ4 17 Composition 2M word x 16 bit x 4 bank jal MEETRCGUK Capacity 16MB 8M word 16 bit M2 TRDCLK row address AO to A11 l dress AO to AB M i 09x2 Application header JA6 777 optional DAN T SCIbRX 1 Options scibrx A22 9 scicrx A28 11 scicck Zero ohm resistors for damping and signal allocation are not indic
60. ated Figure 2 2 Circuit Configuration of SDRAM R20UTO778bEJ0100 Rev 1 00 ae ENESAS page 3 of 20 May 31 2012 V850E2 ML4 CPU Board ROK0F4022C000BR 2 3 2 EEPROM 2 Function Specification The ROK0F4022C000BR includes the 8 KB EEPROM 8 Kword x 8 bit which is controlled by the I2C bus IICB interface mounted in the V850E2 MLA The IICB signal is multiplexed with the CAN signal therefore the EEPROM is not available when the CAN connector is in use Install the jumper JP8 and JP10 in appropriate pin to use Figure 2 3 shows the circuit configuration of the V850E2 MLA and the EEPROM 22kQ x4 V850E2 ML4 amaxze db SES EEPROM lt lt 155 5 51 B Kword x 8 bit P2_14 SCL1 CANORXD 4 JP8 3 SCL o AE P2_15 SDA1 CANOTXD 4210 oe SDA 2 1 e A0 WP sess lt lt ZIKQx4 ves 0Qx4 Application header JA1 P6_12 INTP23 DAMA pp P6 11 INTP22 AAA 26 se 26 2 spa ANA CAN connector J4 00 x2 AAA ANN 0955 Application header JAS KAM pplication header JA5 KAN CAN1RX p E Optional MA 5 CAN1TX R20UTO778bEJ0100 Rev 1 00 May 31 2012 Figure 2 3 Circuit Configuration of EEPROM RENESAS page 4 of 20 V850E2 ML4 CPU Board RO
61. ator Interface The ROK0F4022C000BR includes 14 pin El connector 710 to connect to the emulator and enables to connect to the El emulator Figure 2 9 shows the E1 connector block diagram zc ul Pa V850E2 ML4 c amp lt Sel y 21 22kQ 22kQ 1 GJ HH GND2 1 lt lt DCK TCK FLSCK vecio 4 DMS TMS is H ts TRST DDI TDI FLSI FLRXD LL RESET i DDO TDO FLSO FLTXD HH FLMDO I MSEOO 11 MSEOO TROY T 229 MSEO1 MSEO1 EVTO FW HS 1 EVTI E MCKO HZ NC2 T 19 20 HY NC4 T MDOO 124 T 23 24 MDO1 MDO1 MDO9 74 25 26 MDO2 25 MDO10 e MDO3 2 MDO11 29 30 MDO4 29 MDO12 57 MDO5 MDO5 MDO13 MDO6 33 MDOS MDO14 5 MDO7 33 7 MDO15 37 24 GND3 GND4 l a ss a vss DRST TRST JP13 RESET OOO TRDY FW FLMODO e FLMOD1 JP12 EVTO EVTI D lt 22kQ avcc E1 connector J10 ves 1 2 Reset module 31 9 01 Operati de setti E
62. cc 22 RENESAS 117 3 T 3vcc u21 5vcc CP48 SN74LVC1T45DCK 5vct END 0 1pF B3P SHF 1AA LF SN Ti sl JST 550 VCCA VCCB 1 a iu CANH 1 IA R102 GND DIR 4 2 Ma A B RxD CP49 3 3V 5V R103 OF 1200 1 4W 3vcc CP52 Q tuF R108 u23 2k _ __ suow 20 Gia 71 2 T 7 TA ES 0 37uF 3vcc M C14 10 47pF Serial port H RIOR U W gt J5 Cu IS LERTA SOM c2 E 18 0 Tour Hz o 7 00 R10UT m oa ITIN T20uT HE RIS pp 0Q M GB a T2IN ome 10 R20uT Rain BUS yp pom 44 21 9 lt MAX3222CPW TRIA A OQ F 6 1l9 116 3 T 742R275 2 TRIS A ADOIF 1 Rtt9 Pam 177 ERNI 154188 MALE JPN for Male connector only for Female connector only 154236 FEMALE RSK Serial connector mount tab GND 3vcc e n EEPROM 64KB 888 922 222 220 AT24C64B ATMEL 26 P2 1461 s 2 1 26 P2 15 SDA1 SDA 1 m 3vcc 404 4 vec 8 7 552 LEE Character LCD 236 P5 15 0 18 svec SSM 107 LM DV P TR Samtec 1 3 P5 1 LCDRS 4 RW PS 10 LCDE 6 1 2 91 1101 P5 12 LCDD12 11 P5 13 LCDD13 1 P5 14 LCDD14 13 P5 15 LCDD15 14 8 Es amp
63. ct Jumper JP10 JP10 is a jumper to specify whether to connect the V850E2 MLA P2_15 SDA1 CANOTXD to the CAN connector 14 and a 5 pin of the application header JA5 or to the EEPROM and a 25 pin of the application header JA1 on the board Short circuit pins 2 and 3 of JP10 when connecting the V850E2 MLA P2 15 SDAI CANOTXD to the CAN connector 34 and a 5 pin of the application header JAS and short circuit pin 1 and 2 of JP10 to connect it to the EEPROM and a 25 pin of the application header JA1 Table 3 27 shows the CAN EEPROM select jumper JP10 settings Table 3 27 CAN EEPROM Select Jumper J10 Settings R20UTO778EJ0100 Rev 1 00 244 NE SAS page 210 26 May 31 2012 V850E2 ML4 CPU Board ROK0F4022C000BR 3 Operational Specification Number Setting Description JP10 1 2 Connects the V850E2 ML4 P2 15 SDA1 CANOTXD to the EEPROM and a 25 pin of the application header JA5 2 3 Connects the V850E2 ML4 P2 15 SDA1 CANOTXD to the CAN connector J4 and a 5 pin of the application header JA4 Note Po set by default 3 2 1 9 SDRAM Jumper JP11 JP11 is a jumper to specify whether to use the SDRAM or the signal multiplexed with the SDRAM connection signal on the side of the application header Short circuit JP11 only when using the SDRAM The signal multiplexed with the SDRAM connection signal on the side of the application cannot be used Table 3 28 shows the SDRAM jumper JP11 settings Table 3
64. d PG FPS with 114 optional connector R P6_O INTPO ETH_CRS TAO_10 TEO_TIO TAO_O0 Evro 15 m VINTP1 ETH COL TAO 11 O1 DCK TCK FLSCK lt gt 7 6_2 2 _ _12 0_ 11 0_ 2 118 P6 1 17 gt JA6 E TXD1 TAO 4 TEO O4 120 JA2 C P6 ISIDMATCT TAO O5 DRSTARST 119 3 JAS E P6 6 ETH I6 TEO BDMAAK TAO O6 Hc P6 7IETH TXCLK TAO IZIDMAAKTITAO O7 nir P6 8 ETH TXERVTJ 10 IB TEO ZI TJ OO TAO OB RESET 148 gt gt RESET L Ethernet P6 9 ETH RXER TJ H TAO 19 7 O1 TAO O9 91 pg 40 ETH RXCLK INTP21 TAO MOITAO O10 P2 OJNMI 7 gt 92 pg 11 ETH RXDV INTP22 TAO 111 0 011 P2_1 INTPO ADTRGO0 CSI1F_RYVBCYST TXDO CSI1F_RYO E P6 12 ETH 12 0 O12 P2_2 WAIT ADTRG10 RXDO CSI1F_SSI JA P6 13 ETH RXD1 INTP24 TAO M3ITAO 013 P2_3 NTP1 ADTRG20 ULBE ULWR CSMF_CS0 166 ug JA2 E P6_14 ETH_RXD2 INTP25 TAO_114 TA0_O14 P2_4 ESOO TA1_I0 VUBE TA1_OO UUWR CSIF_CS1 E m JA E P6_15 ETH_RXD3 TAO_115 TA0_015 P2_5 ESO2 TA1_M TA1_O1 CSIF_CS2 P2_6 ESO3 TA1_12 SO1F DMAAKR3 TA1_O2 ADCNVO 163 lt 97 7 I2 INTP26 TJ 02 P2 7IINTP2 TA1 IS TE1 TIO SCK1F DMATC3 TA1 162 gt INTP2 8 P7 11 IIINTP2TITJ
65. ducts are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or systems manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations You should not use Renesas Electronics products or technology described in this document for any purpose relating to military a
66. emory V850E2 ML4 CPU Board This publication maps electrical characteristics and ROK0F4022C000BR operating specifications connectors User s Manual and switches Installation Manual Describes how to set up hardware SH726B CPU Board R20UT0603JJ and software ROK5726BOCOOOBR Installation Manual The following documents apply to the V850E2 MLA Make sure to refer to the latest versions of these documents The newest versions of the documents listed may be obtained from the Renesas Electronics website Document Type Description Document Title Document No User s manual Hardware Hardware specifications pin assignments V850E2 ML4 R01UH0262EJ memory maps peripheral function User s manual specifications electrical characteristics Hardware timing charts and operation description Note Refer to application notes for details on using peripheral functions User s manual Description of CPU instruction set V850E2M R01US0001EJ Architecture User s manual Architecture Application note Applications sample programs Available from the Renesas Electronics Renesas technical update Product specifications updates on website documents etc 2 Frequently Used Abbreviations and Acronyms Asynchronous Communication Interface Adapter Bits per second Cyclic Redundancy Check Direct Memory Access Direct Memory Access Controller Global System for Mobile Communications
67. er intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury artificial life support devices or systems surgical implantations etc or may cause serious property damages nuclear reactor control systems military equipment etc You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application for which it is not intended Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Further Renesas Electronics pro
68. face teer ta tod Herd 2 11 2 7 LCD MITAC a eti eene nm ei abe 2 12 2 8 USB Interface cr EE rte rh He echar dentes rbi Dire ortos rubei 2 13 2 9 Ethernet Interace nin ete tte bic i ede d 2 14 2102 Emulator Interface da eene ee 2 15 2 11 SWItCheS once da i ade eae du vas DASA 2 16 2412 EEDS Potentiometers ita A bn ep tro ed e I 2 17 2 13 Power Module eet atte ete eas neni ete a 2 18 2 14 gt Glock Module 5 25 icd th beer Kozo PM oct Kuko st Decr ber 2 19 2 15 Reset Module i ne deo Ge Ue EA HD nich elke 2 20 3 Operational 7 3 1 3 1 dean eda eed ea cea met 3 1 3 1 1 Application Headers JA1 to JAS and JAG 3 2 3 1 2 USB Connectors Ja di da needa 3 9 3 1 3 Ethernet Connector 12 3 10 3 1 4 Gonnector JA et abeo aa nach Sabu 3 11 3 1 5 Serial Port Connnetor 45 cnn narrar rr cnn rc 3 12 3 1 6 LCD 6 e tu 3 13 3 1 7 External Power Supply Connectors J7 and J2 to J14 3 14 3 1 8 Power Jack J9 i Ae ede e Re X M EUR ea 3 16 3
69. ignal Name 1 CANH U20 2 GND 3 CANL U20 Note P2 14 SCL1 CANORXD and P2 15 SDA1 CANOTXD of the V850E2 ML4 are also connected to the EEPROM and SCL signal and SDA signal of the application header JA1 When using these connections switch the connection at JP8 and JP10 P2 14 SCL1 CANORXD and P2 15 SDA1 CANOTXD of the V850E2 MM are also connected to CAN signal of the application header JA5 and can be used by installing the zero ohm resistor CAN connector J4 cannot be used they are connected to the application header side R20UT0778EJ0100 Rev 1 00 May 31 2012 RENESAS page 110 26 V850E2 ML4 CPU Board ROKOFA4022C000BR 3 Operational Specification 3 1 5 Serial Port Connector J5 The ROKOF4022C000BR includes the serial port connector J5 The serial port connector 15 has two options for wiring on the ROKOF4022C000BR using a male jack with the crossover cable or a female socket with the straight cable by removing and installing zero ohm resistors R109 R111 R112 R113 R115 R117 R118 and R119 as appropriate The ROKOF4022CO000BR installs resistors R111 R113 R115 and R119 to include a male jack with crossover cable by default Figure 3 6shows the serial port connector J5 pin assignment on crossover cable by a male jack Table 3 11 lists the serial port connector J5 pin names on crossover cable by a make jack Board edge Top view of the component side Board edge 6
70. inations other than listed above Setting prohibited Note set by default R20UT0778EJ0100 Rev 1 00 TENESAS page 23of 26 May 31 2012 V850E2 ML4 CPU Board ROK0F4022C000BR 3 Operational Specification Table 3 33 Ethernet PHY DIP Switch SW7 Settings Number Setting Function Description SWT 1 ON Set PORXD3 pin to low Autoneg disabled 100BaseT OFF Set PORXD3 pin to high Autoneg enabled 100BaseT SW7 2 ON Set PORXD2 pin to low If Autoneg disabled Half Duplex If Autoneg enabled Parallel detect ends in half duplex OFF Set PORXD2 pin to high If Autoneg disabled Full Duplex If Autoneg enabled Forced Full Duplex in parallel detect SWT 3 ON Set PORXCLK pin to low Disable Quick Autonegotiation OFF Set PORXCLK pin to high If Autoneg enabled Quick Autonegotiation shortest times If Autoneg disabled Special Isolate In this mode the Phys will not set up a link unless programmed and enabled through the SMI SW7 4 ON Set PORXERR pin to low Configure RMII Interface OFF Set PORXERR pin to high Configure MII Interface SW7 5 ON Set POTXCLK pin to low Standard Mode JK required for Start of Frame detection OFF Set POTXCLK pin to high Fast Mode Only J required for Start of Frame detection SW7 6 ON Set POCRS pin to low AUTOMDI X disabled OFF Set POCRS pin to high AUTOMDI X enabled SWT 7 ON Set PORXDO pin to high Configures the upper two bits N and M of the Phy addresses O
71. mper JP2 settings Table 3 21 Serial Port Received Signal Select Jumper JP2 Settings Number Setting Description JP2 1 2 Connects the V850E2 ML4 P2_12 RXDOF to the serial port connector J5 2 4 Connects a 6 pin RS232RX of the application header JA6 to the serial port connector 45 Note set by default R20UTO778EJ0100 Rev 1 00 31 N SAS page 19of 26 May 31 2012 V850E2 ML4 CPU Board ROKOFA4022C000BR 3 2 1 3 P2 4 Select Jumper JP4 3 Operational Specification JP4 is a jumper to specify whether to use the V850E2 MLA P2_4 for the USB function control or for an 11 pin of the application header JA5 on the board Short circuit pins 1 and 2 of JP4 to use the USB function connector J3 and short circuit pins 2 and 3 of JP4 to use P2 4 as an 11 pin of the application header JA5 Table 3 22 shows the P2 4 select jumper JP4 settings Table 3 22 P2 4 Select Jumper JP4 Settings Number Setting Description JP4 1 2 Uses the USB function connector J3 2 3 Connects the V850E2 ML4 P2_4 to an 11 pin of the application header JA5 Note set by default 3 2 1 4 Serial Port Transmitted Signal Select Jumper JP5 JP5 is a jumper to switch signal wires the serial port transmitted Short circuit pins 1 and 2 of JP5 when connecting the V850E2 MLA P2_13 TXDOF to the serial port connector 15 and short circuit pins 2 and 4 of JP5 to connect a 5 pin
72. n No Signal Name 1 VBUS 2 DM 3 DP 4 GND Table 3 8 USB Function Connector J3 Pin Names Pin No Signal Name 1 VBUS 2 DM 3 DP 4 ID connected to test pin 5 GND R20UT0778EJ0100 Rev 1 00 31 N SAS page 9of 26 May 31 2012 V850E2 ML4 CPU Board ROKOFA4022C000BR 3 Operational Specification 3 1 3 Ethernet Connector J2 The ROK0F4022C000BR includes an Ethernet connector J2 Figure 3 4shows the Ethernet connector J2 pin assignments Table 3 9 lists the Ethernet connector J2 pin names Top view of the Top view of the component side surface Board edge Board edge J2 Figure 3 4 Ethernet Connector J2 Pin Assignments Table 3 9 Ethernet Connector J2 Pin Names Pin No Signal Name Pin No Signal Name 1 TD 2 TD 3 TCT 4 RD 5 RD 6 RCT 7 N C 8 GND R20UT0778EJ0100 Rev 1 00 TENESAS page 10of 26 May 31 2012 V850E2 ML4 CPU Board ROK0F4022C000BR 3 Operational Specification 3 1 4 CAN Connector J4 The ROKOF4022C000BR includes the CAN connector 14 to execute CAN transmission and reception Figure 3 5 shows the CAN connector J4 pin assignments Table 3 10 lists the CAN connector J4 pin names Top view of the component side Board 3 1 edge 94 Table 3 10 CAN Connector 44 Pin Names Figure 3 5 CAN Connector J4 Pin Assignments Pin No S
73. nformation included herein Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration modification copy or otherwise misappropriation of Renesas Electronics product Renesas Electronics products are classified according to the following two quality grades Standard and High Quality The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots etc High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems and safety equipment etc Renesas Electronics products are neith
74. onics Hong Kong Limited Unit 1601 1613 16 F Tower 2 Grand Century Place 193 Prince Edward Road West Mongkok Kowloon Hong Kong Tel 852 2886 9318 Fax 852 2886 9022 9044 Renesas Electronics Taiwan Co Ltd 13F No 363 Fu Shing North Road Taipei Taiwan Tel 886 2 8175 9600 Fax 886 2 8175 9670 Renesas Electronics Singapore Pte Ltd 1 harbourFront Avenue 06 10 keppel Bay Tower Singapore 098632 Tel 65 6213 0200 Fax 65 6278 8001 Renesas Electronics Malaysia Sdn Bhd Unit 906 Block B Menara Amcorp Amcorp Trade Centre No 18 Jln Persiaran Barat 46050 Petaling Jaya Selangor Darul Ehsan Malaysia Tel 60 3 7955 9390 Fax 60 3 7955 9510 Renesas Electronics Korea Co Ltd 11F Samik Lavied or Bldg 720 2 Yeoksam Dong Kangnam Ku Seoul 135 080 Korea Tel 82 2 558 3737 Fax 82 2 558 5141 O 2012 Renesas Electronics Corporation All rights reserved Colophon 1 2 V850E2 ML4 CPU Board ROKOF4022C000BR ENESAS Renesas Electronics Corporation R20UT0778EJ0100
75. onnected by default Connectable at a zero ohm resistor R20UT0778EJ0100 Rev 1 00 31 N SAS page 5 of 20 May 31 2012 V850E2 ML4 CPU Board ROK0F4022C000BR 2 Function Specification Table 2 3 1 O Port Functions 2 5 V850E2 ML4 Application headers Ob board functions Pin No Pin name JA1 JA2 JAS JAG M E U CS LC SL V 47 UDMF F 48 UDPF F 51 UDMH H 52 UDPH H 55 P1_0 D16 TAO_I0 TEO_TIO INTP5 TAO_OO 21 56 P1_1 D17 TAO_I1 OCI INTP6 TAO_O1 15 19 57 P1 2 018 0 I2 TEO TI1 INTPZ TAO O2 22 14 58 P1 3 D19 TAO I3 INTP8 TAO 9 59 P1 4 D20 TAO I4 TEO AI INTP9 TAO O4 25 LEDO 60 P1 5 D21 TAO I5 INTP10 TAO O5 15 LED1 61 P4 6 022 0 16 TEO 11 0 O6 26 16 62 P1 7 D23 TAO 12 0 O7 1 63 P1 8 D24 TAO 18 TEO ZI INTP13 TAO O8 23 13 64 P1 9 D25 TAO I9 INTP14 TAO O9 11 65 P1 10 026 0 MO INTP15 TAO O10 13 66 P1 11 D27 TAO 111 INTP16 TAO O11 14 12 71 P1 12 D28 TA0 M2 INTP17 TAO O12 15 17 72 P1 13 029 0 113 INTP18 TAO O13 16 14 73 P1 14 D30 TAO I14 INTP19 TAO O14 8 15 17 74 P1 15 D31 TAO I15 INTP20 TAO 015 18 11 75 P6 O INTPO ETH CRS TAO IO TEO TIO TAO OO 15 E SW7 76 P6 1 INTP1 ETH COL TAO I1 TAO O1 16 E 77 P6 2 2 TXD3 TAO 12 TI1 TAO O2 17 E 78 P6
76. ort connector J5 via the RS 232C transceiver by installing JP2 and JP5 in appropriate pin Short circuit is used for pins land 2 of both 7 2 and JP5 to connect to the serial port connector 15 When using the V850E2 ML4 UARTJO as the serial port it cannot be used as the application header Figure 2 4 shows the ROK0F4022C000BR serial port block diagram avcc V850E2 ML4 Serial port connector J5 22kQ S 22kQ lt RS 232C 09 Q transceiver LANA 098 P2 13 TXDOF 09 E HX AN 6 JP5 09 Ps 22 LZ ol 3 4 ilo VVV JP2 1 0Q P2 12 RXDOF T 2 lt 24 09 Zi I gt paS ej e 0 Q 0Q VSS Application header JA6 5 RS232TX p Male plug with the crossover cable optional 6 RS232RX 7 7 Female socket with the straight cable L optional R Male plug with the Female socket with the Application header JA2 crossover cable straight cable P2_6 S01F 6 T Y 4 8 7 P2 8 SMF B o 3 o 7 4 o 8 4 20 6 Aly B 1 5 O4 o GND O m ue _ _ E Optional Figure 2 4 Serial Port Block Diagram R20UT0778EJ0100 Rev 1 00 ae ENESAS page 10 of 20 May 31
77. pplications or use by the military including but not limited to the development of weapons of mass destruction When exporting the Renesas Electronics products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations It is the responsibility of the buyer or distributor of Renesas Electronics products who distributes disposes of or otherwise places the product with a third party to notify such third party in advance of the contents and conditions set forth in this document Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics products This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics 2012 4 WEEE Directive Renesas development tools and products are directly covered by
78. r swich 1 4 package Operation mode setting DIP switch 1 4 package External interrupt swiches NMI INTP1 and INTP2 e Reset swich 1 e Ethernet PHY Setting DIP switch 1 8 package 2 12 LEDs and Potentiometer User LEDs 4 e USB host bus LED 1 e Ethernet PHY LEDs Power LED 1 e 10kQ Potentiometer 1 2 13 Power Module Controls the ROKOF4022CO000BR system power supply 2 14 Clock Module e Resonator for CPU 10MHz e Oscillator for USB 48MHz e Resonator for Ethernet PHY 25MHz 2 15 Reset Module Executes reset control of the device which mounted in theROKOF4022CO00BR Operating specifications Refer to Chapter 3 for details on connectors jumpers switches LEDs and potentiometer R20UTO778bEJ0100 Rev 1 00 May 31 2012 RENESAS page 1 of 20 V850E2 ML4 CPU Board ROKOF4022CO00BR 2 Function Specification 2 2 CPU The ROK0F4022C000BR includes the V850E2 MLA the 32 bit RISK microcontroller which operates with a maximum CPU clock of 200MHz and a maximum peripheral clock of 66 667MHz The V850E2 MLA is the microcontroller which has 1 MB of flash memory 64 KB of RAM and 64 KB of H bus shared memory to support various applications such as data processing and equipment control Figure 2 1 shows the block diagram V850E2 MLA The unused pins on the ROKOF4022C000BR are not listed V8
79. ted to the application headers JA1 JA2 and JAS which can be selected instead of using the series Mini B receptacle Figure 2 7 shows the USB interface block diagram V850E2 ML4 Oscillator USB host 48MH 5VCC P2_11 UCLK connector J1 270 UDPH D 279 UDMH e D USBhost bus 00 S15kQ 215 0 m 22kQ Switch VIS VSS FG2 P2 9 OCI e jp7 OUT2 e e VBus FG1 FLG Q OUT1 1 5k GND FRAME e P2 10 PPON JP9 vec ec IN e vss vss 22kQ GND T 1804 vss vss vss ves VSS d JA2 16 P2 9 TA1 15 0Q JA5 14 P2 9 TA1 15 JA1 23 P2 10 INTPS TA1 I6 TA1 O6 09 JA2 18 P2 4 1 IO TA1 OO 08 11 P2 4 TA1_I0 TA1_O0 0Q JA1 8 P2_3 INTP1 ADTRG20 09 Wv JA2 9 P2_3 INTP1 ADTRG20 USB function 2 4 EVDD connector 93 VBus P2 3 INTP1 lJP1 15 9 27Q a UDPF pra D FG3 UDMF D 2 ae FG1L e ua GND FRAME e L Optional VSS VSS VSS VSS Figure 2 7 USB Interface Block Diagram R20UTO778bEJ0100 Rev 1 00 LENESAS page 13 of 20 May 31 2012 V850E2 ML4 CPU Board ROKOF4022CO00B
80. the V850E2 ML4 are connected to the expansion connector to enable timing evaluation with the peripheral devices using measurement hardware and development of expansion boards for the development purpose e Enables to evaluate the debugging with Renesas Electronics On chip Debugging Emulator 14 pin connector R20UTO778EJ0100 Rev 1 00 AS Page 1 of 7 May 20 2012 ENES V850E2 ML4 CPU Board ROK0F4022C000BR 1 Overview 1 2 System Configuration Figure 1 1 shows the system configuration with the ROK0F4022C000BR ROKOF4022C000BR Serial port CAN LCD connector connector connector E1 connector 14 pin ML JA2 JA3 USB function USB host connector connector AC adaptor Ethernet connector JAM 2 JA5 JAG Through holes for expansion connector application headers Integrated Development E1 Emulator Environment CubeSuite Host computer Note These are optional that should be prepared by user Figure 1 1 System Configuration R20UTO778EJO100 Rev 1 00 a2 AS Page 2 of 7 May 20 2012 ENES V850E2 ML4 CPU Board ROKOFA4022C000BR 1 Overview 1 3 External Specifications Table 1 1 lists the external specifications of the ROKOF4022C000BR Table 1 1 External Specifications Description V850E2 ML4 e Input XIN clock 10MHz e CPU clock Up to 200MHz e Memory controller bus E bus clock Up to 66 667MHz SDRAM interface Up to 50MHz Peripheral bus P bus clock Up
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