EVALSPEAR600FPG - evaluation board for the SPEAr600
Contents
1. UM0947 Evaluation board bill of materials BOM Table 12 Diodes connectors inductors amp transistors continued Mictor TYCO Electronics 27 2 J5 J6 Sasa ne 5767061 1 28 1 u7 CON22A TYCO Electronics 5 826925 0 AMP 29 2 J18 J8 CON20A TYCO Electronics 5 4634688 0 AMP 30 1 u9 BatCon MOLEX 53047 0210 Electronics 31 1 u14 Jumper2x2 TYCO Electronics 826925 0 AMP 32 1 J15 CON4 TOD BISCIONICS erasaeooy AMP 33 1 J16 CON10A TYCO Electronics 4 _1 34688 0 AMP 34 1 J17 CON20A TYCO EleciOnies 5 gagga AMP 35 1 J19 CON12 TY EO Electonics 5 ep6856 AMP 36 1 J20 CON10A TYCO Electonics 5 an6026 0 AMP 37 1 lJa CON30A SAMTEC CLP 115 02 L D 38 1 J22 CONS50A SAMTEC SFM 125 02 S D 39 1 J25 JK065401NL PULSE JK065401NL 40 1 J26 TAP_2 5mm CLIFF Electronics FC681491 41 1 u27 CON6 TYCO Electonics yogga AMP 42 1 l1 33uH COILCRAFT DO3316P 333MLB 43 1 L2 6 8uH COILCRAFT MSS6132 682MLC ale has BLM18AG102S MURATA BLM18AG102SN1 N1D D 45 1 P1 CON DB9 Male TYCO Electronics lt 7 47g 49 0 AMP 46 2 Q1 Q2 BCR112 INFINEON BCR112E6327 47 1 Q3 BC848 INFINEON BC848CE6327 Table 13 Resistors Item Qty Reference Part Manufacturer Manufacturer P N 48 6 R87 R44 R71 R77 R78 R79 1K Electronics oR Go603F1K0 49 3 R2 R3 R46 121K 1 ky Doc ID 17555 Rev 1 19 29 Evalu2. Table 11 Capacitors continued Item Qty Reference Part apm Manufacturer P N C103 C108 C110 C112 C138 KEMET 9 7 C140 0142 10uF El cirohics C1210C106Z4VAC 10 1 c104 22nF KEMET c0603C223K5RAC Electronics 100uF 11 2 C145 C105 6 3V AVX TPSC107K006R0150 Tantalum KEMET 12 1 C106 220pF Electroni s C0603C221J5GAC C107 C109 C111 C137 C180 C181 C182 C183 C184 C185 C186 C187 13 30 C188 C189 C190 C191 C192 C193 1uF ool ee C194 C195 C196 C197 C198 C199 ere C200 C201 C202 C203 C204 C205 14 1 c141 1nF KEMET c0603C102K5RAC Electronics 15 1 C144 100uF 16V Table 12 Diodes connectors inductors amp transistors Item Qty Reference Part Manufacturer Manufacturer P N 16 4 D1 D3 D6 D13 LED Green KINGBRIGHT KP 2012SGC 17 2 D2 D4 LED Red KINGBRIGHT KP 2012SRC PRV 18 6 D5 D7 D8 D9 D10 D11 LED Yellow KINGBRIGHT KP 2012SYC 19 1 D12 STPS2L60 STM STPS2L60A On 20 1 D14 BAV70 BAV70E6327 Semiconductor GTP1 GTP2 GTP3 GTP4 VERO 21 Gtps aTPe OFF Technologies 202139 22 4 JP1 JP2 JP3 JP4 JUMPER M 5 826629 0 JP5 JP6 JP7 JP8 JP9 JP10 i 23 13 JP11 JP12 JP13 JP14 JUMPER DRE Blectronies 5 826629 0 JP15 JP16 JP17 24 1 J1 YTQ 150 01 F SAMTEC TMMS 150 01 FM Q FS 25 1 J2 USB Device SAMTEC USB B S F B TH 26 2 J3 J4 USB HOST1 2 MOLEK 89485 8000 Electronics Doc ID 17555 Rev 1 4
3. 10 11 User manual and board schematic The user manual and board schematic are available on www st com spear Evaluation board bill of materials BOM Reference Spear600 BOM Board Rev 7 Sep 11 2009 Table 11 Capacitors Item Qty Reference Part enai Manufacturer P N C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C17 C18 C19 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C39 C40 C41 C42 C44 C45 C46 C47 C48 C49 C50 C52 C53 C54 C55 C56 C57 C66 C88 C89 C90 C114 C115 C116 4 9g C117 C118 C119 C120 C121 C122 4uF uae C0402C104K8PAC78 C123 C124 C125 C126 C127 C128 pile aks C129 C130 C131 C132 C133 C134 C136 C139 C143 C146 C147 C148 C149 C150 C151 C152 C153 C154 C155 C156 C157 C158 C159 C160 C161 C162 C163 C164 C166 C167 C168 C175 C176 C177 C16 C21 C71 C74 C78 C83 KEMET 2 13 oga ces ce6 c91 c92 0173 c174 10NF Electronics C0609C103K5RAC C20 C22 C33 C34 C43 C51 C58 C6 C61 C62 C63 C64 C65 C67 C68 3 36 C72 C73 C75 C82 C87 C93 C94 C9 1uF aii MR VJO603Y 104KX C96 C97 C98 C99 C100 C113 C135 C169 C170 C171 C172 C178 C179 4 4 C37 C38 C79 C80 15pF MURATA aa aati 5 2 C35 C36 10pF MURATA pr i 6 2 c77 c76 22uF KEMET 12100226Z8VAC Electronics 220uF 50V 7 4 c101 a07 vie PUBYCON 8 1 C102 1uF 25v KEMET co805c105Zz3VAC Electronics Doc ID 17555 Rev 1 17 29 Evaluation board bill of materials BOM UM0947 18 29
4. UM0947 JT User manual EVALSPEAR600FPG evaluation board for the SPEAr600 Introduction The EVALSPEAR600FPG evaluation board for SPEAr600 is intended to be used for three main purposes m To allow you to quickly evaluate and debug software for the SPEAr600 m To act asa learning tool to rapidly get familiar with the SPEAr600 features m To provide a reference design to be used as a starting point for the development of a final application board It is equipped with all the interfaces offered by the SPEAr600 A special version of the board populated with an FPGA also exists for developing customer specific IPs Figure 1 EVALSPEAR600FPG evaluation board June 2010 Doc ID 17555 Rev 1 1 29 www st com List of tables UM0947 List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 2 29 Switch 4 configuration 0 0 0 0 000 tte 9 Default settings for other jumpers 0 2 00 cc eee 10 Auto negotiation disabled 10 eee 10 Auto negotiation enabled advertised capability 0000 c eee eee eee 10 Eihemet LEDS 2 0 ccclae tide Mae id phe Cade Pana bao Ae ea dee RAO aes 11 Switch 1 configuration settings sasaaa aaua e eee ae 12 Switch 1 SoC functional configuration 0 000 tee 15 Switch 1 debug configuration 0 0 00 c eae 15 Switch 1
5. 5 12 Note 14 29 LCD Interface The J22 connector P N SFM 125 02 S D Samtec is provided to allow the user to connect an LCD daughter board It mates with TFM 125 02 S D The following signals are available on the J22 connector Allthe LCD interface signals Two analog inputs A D e Three GPIO lines e 12V 5V e GND For the connector pinout refer to the schematic drawing available on www st com spear Serial interface Two serial interface ports are available The 1st one typically used as an OS monitor is available on the P1 connector It is possible to simulate a cross cable by changing the posi tion of the J14 jumpers as shown in Figure 5 The 2nd serial interface port is available on J16 For the pinout of the connectors refer to the schematic drawing available on www st com spear Figure 5 Serial cable setting J14 J14 Cross Null 2 4 2 4 modem cable cable Reset switch A manual reset switch SW5 is available on the top side of the board Doc ID 17555 Rev 1 ky UM0947 Switch settings 8 Switch settings 8 1 Switch 1 SoC functional configuration Table 7 Switch 1 SoC functional configuration Bit Description 1 TestO see Debug configuration below Test1 see Debug configuration below Test2 see Debug configuration below Test3 see Functional configuration below Test4 see Functional configura
6. Up to 16 MB Serial Flash std 8 MB Up to 2 Gb NAND Flash std 64 MB 4 Kb Serial I C Two USB 2 0 full Host port channels One USB 2 0 HS Device 10 100 1000 Ethernet port Two Serial ports up to 115 Kbaud Debug ports JTAG ETM9 8 ADC channels 10 bit 1 Msamples 10 GPIOs LCD I F up to 24 bits per pixel bpp Additional 112 GPIOs when the external FPGA is used Block diagram Figure 3 Block diagram Expansion connector Power NOR NAND FPGA supply Flash Flash Virtex4 LX60 10 100 1000 PHY Ethernet USB2 Host 1 Serial I F 1 SPEAr600 USB2 a Serial I F 2 Host 2 2 1 Debug I F ia EJF pono Device 8 Channels A2D LCD I F Doc ID 17555 Rev 1 ky UM0947 Start up 4 4 1 4 2 4 3 Start up Unpacking Warning The EVALSPEAR600FPG Evaluation board is shipped in protective anti static packaging The board must not be subjected to high electrostatic potentials General practices for working with static sensitive devices should be applied when working with this board Before unpacking the evaluation board you should take the following precautions e Wear an anti static wristband Wearing a simple anti static wristband can help to prevent ESD from damaging the SPEAr600 evaluation board Be self grounded Touch a grounded conducting material before handling and periodically while handling the SPEAr600 evaluation board e Use an anti static pad When configuring th
7. UM0947 Evaluation board bill of materials BOM 4 Table 13 Resistors continued R124 R126 R128 R1 R132 i 69 6 R126 8 R130 R132 330 TYCO Electronics CRG0603F330R R154 UK 70 1 R140 3 9K i Electronics oR Go603F3k9 71 1 R142 1 2K a Electronics SRG0603F1K2 72 1 R150 22K 73 1 R157 100K es Electronics cRGo603F 100K Table 14 Switch semiconductors amp crystals Item Qty Reference Part Manufacturer Manufacturer P N 74 2 SW1 SW2 SW DIP 6 APEM DS06 Components 75 1 sws SW DIP 4 APEM DS04 Components 76 1 SW4 SW DIP 8 APEM DS08 Components 77 1 SW5 PUSHBUTTON OMRON B3S 1000 Electronics 78 1 lui MT47H64M16HR MICRON MT47H64M16HR 3 3E 79 1 U2 SPEAr600 STM SPEAR 09 P022 XXC4VLX60_11F XC4VLX60 S0 LAE FG668 XILINX 11FFG668C 81 1 U4 Socket Augat wi NSLOW W30514TT Adaptics 82 2 U5 U6 TPS2030 TEXAS TPS2030D Instruments 83 1 U7 74HC09 STM M74HCO9RM13TR 84 1 U8 M25P64 STM M25P64 VMF6P 85 1 U10 M24C04 STM M24C04 WMN6P 86 1 U11 ST3232CD STM ST3232CDR NandFlashx8_FB Nand512W3A2CZ 87 1 U12 GA63 STM A6 88 1 jut4 GigPhy DP83865 NATIONAL No 89 1 U15 L5972D STM E L5972D 90 1 U16 LD1117S33TR STM LD1117S33TR 91 1 U17 LD1117S25TR STM LD1117S25TR 92 1 U18 LD1117S18TR STM LD1117S18TR Doc ID 17555 Rev 1 21 29 Evaluation board bill of materials BOM UM0947 Table
8. archival copy and as the confidential information of ST Access to the source code of the Licensed Software shall be restricted to only those of Your employees with a need to know for the purpose of this Agreement You will not under any circumstances permit the source code of the Licensed Software in any form or medium including but not limited to hard copy or computer print out to be removed from your official premises as you have informed us The source code of the Licensed Software must remain inside your official premises as you have informed us You will lock the source code of the Licensed Software and all copies thereof in a secured storage inside your official premises at all times when the source code of the Licensed Software is not being used as permitted under this Agreement Doc ID 17555 Rev 1 25 29 License agreements UM0947 26 29 You will inform all Your employees who are given access to the source code of the Licensed Software of the foregoing requirements and You will take all reasonable precautions to ensure and monitor their compliance with such requirements You agree to promptly notify ST in the event of a violation of any of the foregoing and to cooperate with ST to take any remedial action appropriate to address the violation You shall keep accurate records with respect to its use of the source code of the Licensed Software In the event ST demonstrates to You a reasonable belief that the source code of the Licen
9. excluded to the fullest extent permitted by law LIMITATION OF LIABILITIES In no event ST or its licensors shall be liable to You or any third party for any indirect special consequential incidental punitive damages or other damages including but not limited to the cost of labour re qualification delay loss of profits loss of revenues loss of data costs of procurement of substitute goods or services or the like whether based on contract tort or any other legal theory relating to or in connection with the Licensed Software the documentation or this Agreement even if ST has been advised of the possibility of such damages In no event shall ST s liability to You or any third party under this Agreement including any claim with respect of any third party intellectual property rights for any cause of action exceed 100 US This section does not apply to the extent prohibited by law For the purposes of this section any liability of ST shall be treated in the aggregate TERMINATION ST may terminate this license at any time if You are in breach of any of its terms and conditions Upon termination You will immediately destroy or return all copies of the software and documentation to ST APPLICABLE LAW AND JURISDICTION In case of dispute and in the absence of an amicable settlement the only competent jurisdiction shall be the Courts of Geneva Switzerland The applicable law shall be the law of Switzerland Doc ID 17555 Rev 1 k
10. resistors R48 R49 R50 R51 and R52 with 0O ohm resistors Remove resistors R93 and R94 Please refer to the documentation of the trace box manufacturers for more information on the ETM interface www lauterbach com www agilent com www yokogawa com A D interface Eight analog input lines are provided on the J17 connector The connector also allows you to determine the conversion range by setting the conversion limits on pins J17 19 lower limit and J17 1 upper limit The default setting is to have pins 1 2 and 19 20 shorted by jumpers In this way the conversion range is set to the maximum value 0 2 5V with a granularity of 2 44 mV but by removing the two jumpers and providing different values on pin 1 and 19 it is possible to reduce the range and thus increase the granularity For example if you input 1 V on J17 19 and 2 V on J17 1 the range will be 1 V 2 V in steps of less than 1 mV In any case the following relationships between the pins should be ensured OV lt J17 19 lt J1717 3 lt J17 1 lt 25V AGND lt Vref_n lt ADC_In lt Vref_p lt AVDD channels Doc ID 17555 Rev 1 ky UM0947 Block descriptions 5 8 Real time clock battery powered The real time clock RTC is powered with a 3V external battery J9 in order to avoid losing its data even if the main power supply is switched off 5 9 General power supply From a 12 V 25 V external AC DC regulator power source this block generates all the requir
11. 14 Switch semiconductors amp crystals continued 93 1 U19 STM811 STM STM811SW16F 94 1 U20 PL5S 12C TDK Lambda PL5S 12 C 95 1 U21 XCF32PVOG48C_ XILINX XCF32PVOG48C 96 1 U22 L6926 STM L6926 97 1 Y1 32KHz FOX Electronics NC26LF 327 98 1 Y2 30MHz C MAC XTAL003342 99 1 Y3 25MHz FOX Electronics FOXS 250F 20 100 15 Jumper fetta W8010T50 101 4 Rubber feet PDE PD2115BL 22 29 Doc ID 17555 Rev 1 4 UM0947 License agreements Appendix A License agreements 4 DEMO PRODUCT LICENSE AGREEMENT By using this Demonstration Product You are agreeing to be bound by the terms and conditions of this agreement Do not use this Demonstration Product until You have read and agreed to the following terms and conditions The use of the Demonstration Product implies automatically the acceptance of the following terms and conditions LICENSE STMicroelectronics ST grants You the right to use the enclosed demonstration board offering limited features only to evaluate and test ST products including any incorporated and or accompanying demo software components and documentation identified with the order code STEVAL collectively the Demo Product solely only for your evaluation and testing purposes The Demo Product shall not be in any case directly or indirectly assembled as a part in any production of Yours as it is solely developed to serve demonstration purposes and has no direct function and is n
12. 16 Speed 1 select bit See Table 3 amp Table 4 1 2 3 1 2 JP12 JP17 3 5 3 i 5 Speed 0 select bit See Table 3 amp Table 4 Speed select strap These strap option pins have 2 different functions depending on whether Auto negotiation is enabled or not Refer to default settings for other jumpers Table 3 Auto negotiation disabled Speed 1 Speed 0 Speed enabled 1 1 Reserved 1 0 1000BASE T 1 100BASE T 0 10BASE T Table 4 Auto negotiation enabled advertised capability Speed 1 Speed 0 Speed enabled 1 1 1000BASE T 10BASE t 1 0 1000BASE T 1 1000BASE T 100BASE T 0 1000BASE T 100BASE T 10BASE T Doc ID 17555 Rev 1 UM0947 Block descriptions 5 4 2 Ethernet LEDs Table 5 Ethernet LEDs Reference Description D7 Duplex Status The LED is lit when the PHY is in Full Duplex operation after the link is established 1000M Speed and Good Link LED The LED output indicates that the PHY has established a good link at 1000 Mbps D8 In 1000BASE T mode the link is established as a result of training Auto negotiation completed valid 1000BASE T link established and reliable reception of signals transmitted from a remote PHY is received 100M Speed and Good Link LED The LED output indicates that the PHY has established a good link at 100 Mbps In 100BASE T mode the link is established as results of an input receive D9 amplitude compliant with T
13. ID 17555 Rev 1 STA UM0947 Contents of the kit 1 Contents of the kit The EVALSPEAR600FPG evaluation board kit contains SPEAr 00 evaluation board e AC adapter output voltage 12 V 2 power cords USA Europe e User manual Getting started documentation 2 Connectors locations Figure 2 Connectors locations J27 FPGAJTAG J9 RTC Battery J4 USB2 Host2 J3 USB2 Host1 J2 USB2 Device SW1 Functional Configur ation SW2 General Purpose 4 J1 Exp Connector SW4 Ethernet 4 configuration E JP8 JP17 z E 7 Ethemet E P Strap option FPGA Virtex4 lt 4 J25 Ethernet al J25 NAND a Flash selection U12 J21 NandFlash SPEAr600 J le lt lt _ P1COM1 C J14 COM1 Settings a m lt 4 J16 COM2 ST Microelectronics HX _ S15 IDA SPEAr 600 7 7 Rev 7 lt J8Jtag ARM1 z Apr 09 2009 Ove E T J17A2D J26 Power Jack J19 J22 LCD J18 Jtag ARM2 412V Manual Reset J5ETM9 J6 ETM9 ARM2 ARM1 amp ARM2 Doc ID 17555 Rev 1 5 29 Features and block diagram UM0947 3 3 1 3 2 6 29 Features and block diagram Features Up to 2 Gb DDR2 333 MHz std 128 MB
14. P PMD specifications which will result in internal generation of signal detect LINK100_LED will assert after the internal signal detect has remained asserted for a minimum of 500 us LINK100_LED will de assert immediately following the de assertion of the internal signal detect D10 10M Good Link LED In the standard 5 LED display mode this LED output indicates that the PHY has established a good link at 10 Mbps D11 Activity LED The LED output indicates the occurrence of either idle error or packet transfer 5 5 USB 2 0 subsystem 5 5 1 Host ports The board has two host ports that are fully compliant with the USB 2 0 specification two controllers with one port each This means that the two hosts can work in concurrent mode with the maximum possible bandwidth Each host has also full control of the VBUS supplied by the TPS2030 power switch that also provides overcurrent protection in case of a short circuit in the USB cable The ports are equipped with LEDs showing the power status of each port The green LED indicates the presence of VBUS and the red one the current limiter status 5 5 2 Device port A USB 2 0 Device port is also provided 5 6 Debug interface Two debug interfaces are provided The JTAG interface can be used for static debug This means that is possible to set a breakpoint and when the system stops to verify the contents of the memory and or registers and modify them if needed The ETM9 interface can be used fo
15. R LIFE SUSTAINING APPLICATIONS NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ST PRODUCTS WHICH ARE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2010 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com ky Doc ID 17555 Rev 1 29 29 Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery amp Lifecycle Information STMicroelectronics EVALSPEAR600FPG
16. also includes all the required magnetics Several configuration jumpers and several LEDs are present to display the line status activity 5 4 1 Configuration jumpers and switches Table 1 Switch 4 configuration Bit Description 1 PHY Address bit 1 default value 0 2 PHY Address bit 2 default value 1 3 PHY Address bit 3 default value 0 4 PHY Address bit 4 default value 0 Multiple Node Enable This pin determines if the PHY advertises Master multiple 5 nodes or Slave single node priority during 1000BASE T Auto Negotiation 1 Selects multiple node priority switch or hub 0 Selects single node priority NIC default value Auto MDIX Enable This pin controls the automatic pair swap Auto MDIX of the MDI MDIX interface 6 1 Enables pair swap mode 0 Disables the Auto MDIX and defaults the part into the mode preset by the MAN_MDIX_STRAP pin default value Clock To MAC Enable 7 1 CLK_TO_MAC clock output enabled default value 0 CLK_TO_MAC disabled 8 Not used Note When DIP switch SW4 x is in the ON position the bit value is 0 When the DIP switch is in the OFF position the bit value is 1 Doc ID 17555 Rev 1 9 29 Block descriptions UM0947 10 29 Table 2 Default settings for other jumpers Reference designator Description On Off JP8 JP13 PHY Address bit 0 1 2 3 1 2 JP9 JP14 Auto negotiation enable bit 1 2 3 1 2 JP10 JP15 Full Duplex select bit 1 2 3 1 2 JP11 JP
17. ated recycling the Demo Product is subject to differentiated recycling at the end of its life cycle therefore It is forbidden to dispose the Demo Product as an undifferentiated waste or with other domestic wastes Consult the local authorities for more information on the proper disposal channels It is mandatory to sort the demo product and deliver it to the appropriate collection centers or when possible return the demo product to the seller An incorrect Demo Product disposal may cause damage to the environment and is punished by the law 10 Nov 2008 4 Doc ID 17555 Rev 1 UM0947 License agreements 4 SOFTWARE LICENSE AGREEMENT This Software License Agreement Agreement is displayed for You to read prior to downloading and using the Licensed Software If you choose not to agree with these provisions do not download or install the enclosed Licensed Software and the related documentation and design tools By using the Licensed Software You are agreeing to be bound by the terms and conditions of this Agreement Do not use the Licensed Software until You have read and agreed to the following terms and conditions The use of the Licensed Software implies automatically the acceptance of the following terms and conditions DEFINITIONS Licensed Software means the enclosed demonstration software and all the related documentation and design tools licensed in the form of object and or source code as the case maybe Pro
18. ation board bill of materials BOM UM0947 Table 13 Resistors continued R4 R12 R16 R26 R68 R69 R112 R119 R120 R133 R134 R135 TYCO Electronics 50 19 R136 R137 R138 R139 R143 475 UK CRG0603F4K7 R152 R155 R5 R24 R105 R123 R125 R127 TYCO Electronics 1 2 2K RGO0603F2K2 51 8 R429 R131 UK CRGO6 R6 R7 R27 R28 R29 R30 R31 52 17 R34 R35 R36 R38 R39 R41 R42 10 ie Electronics CRG0603F10R R82 R101 R159 53 2 R8 R15 470 ee Electronics ORG0603F470R R9 R72 R93 R94 R95 R96 R97 TYCO Electronics 4 CRG0603ZR 54 9 R98 R99 g UK 55 2 R104 R10 33 o Electronics op Go603F33R 56 1 R11 180K i Electronics ORG0603F180K TYCO Electronics MR 57 4 R13 R14 R20 R21 100 Pa paendeeeiGer 58 1 RI7 470K a Electronics CRG0603F470K 59 1 R23 22 T Electronics CRG0603F22R R25 R53 R54 R55 R56 R57 R60 R61 R62 R63 R64 R65 R66 R70 l 60 28 R73 R74 R75 R83 R84 R85 R86 10K o Electronics RG0603F10K R87 R88 R89 R90 R91 R121 R122 61 3 R32 R40 R141 270 ae Electronics CRG0603F270R 62 4 R33 R43 R80 R81 150 a Electronics CRG0603F150R 63 1 R45 R156 1 5K 1 ei Electronics CRG0603F1K5 64 3 R59 R151 R153 100 es Electronics ORG0603F100R 65 1 R103 1M i Electronics CRG0603F1M0 66 1 R100 18 D Electronics CRG0603F18R 67 1 R102 9 76K 1 sg g R106 R107 R108 R109 R111 a99 R114 R115 R117 20 29 Doc ID 17555 Rev 1 4
19. d results ST has not authorized anyone to make any representation or warranty for the Licensed Software and any technical applications or design information or advice quality characterization reliability data or other services provided by ST shall not constitute any representation or warranty by ST or alter this disclaimer or warranty and in no additional obligations or liabilities shall arise from ST s providing such information or services ST does not assume or authorize any other person to assume for it any other liability in connection with its Licensed Software Nothing contained in this Agreement will be construed as i a warranty or representation by ST to maintain production of any ST device or other hardware or software with which the Licensed Software may be used or to otherwise maintain or support the Licensed Software in any manner and ii a commitment from ST and or its licensors to bring or prosecute actions or suits against third parties for infringement of any of the rights licensed hereby or conferring any rights to bring or prosecute actions or suits against third parties for infringement However ST has the right to terminate this Agreement immediately upon receiving notice of any claim suit or proceeding that alleges that the Licensed Software or your use or distribution of the Licensed Software infringes any third party intellectual property rights All other warranties conditions or other terms implied by law are
20. duct demonstration software and related documentation RESTRICTIONS You may not sell assign sublicense lease rent or otherwise distribute the Demo Product for commercial purposes unless you are an authorized ST distributor provided that all the other clauses of this DEMO PRODUCT LICENSE AGREEMENT shall apply entirely in whole or in part or use Demo Product in production system Except as provided in this Agreement or in the Demo Product s documentation You may not reproduce the demonstration software or related documentation or modify reverse engineer de compile or disassemble the demonstration software in whole or in part You warrant to ST that the Demo Product will be used and managed solely and exclusively in a laboratory by skilled professional employees of Yours with proven expertise in the use and management of such products and that the Demo Product shall be used and managed according to the terms and conditions set forth in the related documentation provided with the Demo Product According to European Semiconductor Industry Association ESIA letter ESIA Response on WEEE Review May 2008 of the Directive 2002 96 EC on Waste Electrical and Electronic Equipment WEEE Semiconductor products and evaluation amp demonstration boards are not in the scope of the Directive 2002 96 EC of the European Parliament and of the Council on waste electrical and electronic equipment WEEE Consequently aforementioned products do not have
21. duct means a product or a system that includes or incorporates solely and exclusively an executable version of the Licensed Software and provided further that such Licensed Software executes solely and exclusively on ST products LICENSE STMicroelectronics ST grants You a non exclusive worldwide non transferable whether by assignment law sublicense or otherwise revocable royalty free limited license to i make copies prepare derivatives works display internally and use internally the source code version of the Licensed Software for the sole and exclusive purpose of developing executable versions of such Licensed Software only for use with the Product ii make copies prepare derivatives works display internally and use internally object code versions of the Licensed Software for the sole purpose of designing developing and manufacturing the Products iii make use sell offer to sell import or otherwise distribute Products OWNERSHIP AND COPYRIGHT Title to the Licensed Software related documentation and all copies thereof remain with ST and or its licensors You may not remove the copyrights notices from the Licensed Software You may make one 1 copy of the Licensed Software for back up or archival purposes provided that You reproduce and apply to such copy any copyright or other proprietary rights notices included on or embedded in the Licensed Software You agree to prevent any unauthorized copying of the Licens
22. e SPEAr600 evaluation board place it on an antic static pad to reduce the possibility of ESD damage Only handle the board edges When handling the SPEAr600 evaluation board Connection To connect the board follow these steps 1 Connect a serial cable RS232 on P1 to a host PC see Figure 2 Connectors locations 2 Ona host PC running Windows or Linux start the Terminal program 3 Connect the AC Adapter to a power outlet 4 Power ON the board plug the jack of the AC Adapter on J26 A sequence of boot messages is displayed followed by the Linux console prompt For more information refer to the UM0844 Getting started with SPEAr Linux support package LSP available on www st com spearsoftware Booting procedure The EVALSPEAR600FPG evaluation board is able to boot a Linux kernel pre installed in the serial NOR Flash At power on the serial port outputs a brief header message with some uBoot information uBoot version SDK version and some internal hardware information At this point you can choose to e Stop the system directly in uBoot For this you have to press the spacebar on the host computer keyboard before the boot delay time expires default is 3 seconds e Boot Linux The system logs you in automatically as super user and the Linux shell prompt is displayed on the screen Doc ID 17555 Rev 1 7 29 Block descriptions UM0947 5 5 1 5 2 8 29 Block descriptions Dynamic memory
23. ed Software and related documentation RESTRICTIONS Unless otherwise explicitly stated in this Agreement You may not sell assign sublicense lease rent or otherwise distribute the Licensed for commercial purposes in whole or in part purposes unless you are an authorized ST distributor provided that all the other clauses of this DEMO PRODUCT LICENSE AGREEMENT shall apply entirely You acknowledge and agree that any use adaptation translation or transcription of the Licensed Software or any portion or derivative thereof for use with processors manufactured by or for an entity other than ST is a material breach of this Agreement and requires a separate license from ST No source code and or object code relating to and or based upon Licensed Software is to be made available by You to any third party for whatever reason You acknowledge and agrees that the protection of the source code of the Licensed Software warrants the imposition of security precautions and You agree to implement reasonable security measures to protect ST s proprietary rights in the source code of the Licensed Software You shall not under any circumstances copy duplicate or otherwise reproduce the source code of the Licensed Software in any manner except as reasonably necessary to exercise Your rights hereunder and make one back up copy You are granted the right to make one archival or backup copy of the source code of the Licensed Software which copy shall be marked as an
24. ed voltages as follows 1 0 V Switching regulator to supply the internal logic of the SPEAr600 1 2 V Switching regulator for the FPGA core e 1 8 V LDO regulator for the DDR2 memory e 2 5 V LDO regulator for the analog portion of SPEAr600 and for the Ethernet interface 3 3 V LDO regulator to supply the other interfaces 5V Switching regulator to supply the USB Host VBUS A power monitor is also present to provide the general reset of the board 5 10 General purpose I Os Ten general purpose I Os are present on the board Four of them are connected to a DIP switch to allow the user to select deselect them The other two GPIO4 and GPIOS5 drive two LEDs one green and one yellow All the GPIOs are also connected to the J19 connector which also has GND and 3 3V pins available Note For the connector pin out refer to the schematic drawing available on www st com spear 5 11 LEDs Several LEDs are present on the board They display the following status information D13 green Main power present D1 green VBUS present on USB HOST port 1 D3 green VBUS present on USB HOST port 1 D2 red Abnormal current flowing on USB HOST 1 port D4 red Abnormal current flowing on USB HOST 1 port D5 yellow Switched on off by GPIO4 D6 green Switched on off by GPIO5 D7 11 yellow Ethernet line status LEDs Refer to Section 5 4 Ethernet subsystem Doc ID 17555 Rev 1 13 29 Serial interface UM0947
25. ernet LEDs 0 0000 cece 11 55 USB 2 0 subsystem secon caw cs nda Medes dn cae dem ated nade ee see 11 5 5 1 HOSTIPONS dretes inek ioni eae eat at OR coe be ae 11 5 5 2 Dvico POM go scencetreat seme peed edie oleae ieee a vise ARF 11 5 6 Debug interface 25 xetesaats 4h Me bee Wa dkms tea dao Pada ewe 11 5 7 A D interface u nan ie ee aecend s Sao ain ae aes ae hee ee ers 12 5 8 Real time clock battery powered 0 0 e eee eee 13 5 9 General power supply 00 c eee eee 13 5 10 General purpose VOS is ec ueey ete eRe ewe sd eet be eek EMER wR EHS 13 Bel EEDS tacc sans aA sae dewe eee eee a ee bene eas 13 5 12 LOD IMtemate osc cc ianaeedvseestcateoGa diced ere eeaeesse beet 14 6 Serial interface cath in a cme en dee eh ean can eR ee 14 ky Doc ID 17555 Rev 1 3 29 Contents UM0947 7 Reset switch ie tecnica i ei ee aaa ee en i we eee 14 8 Switch SGUINGS cccreseen tee einen ean eae wae beat ew aa 15 8 1 Switch 1 SoC functional configuration 0000 0 eee eee 15 8 2 Switch 2 general purpose settings 0 00 e eee eee 16 9 Expansion connector 4 citi ctes sei deavacde ted endeev esa reeeeds 16 10 User manual and board schematic 00 eee eee eee eee 17 11 Evaluation board bill of materials BOM 00000e 17 Appendix A License agreements 00 00 cece eee eee 23 12 Revision history baw ane nt ete es see eee ee ab Qu erent a kheke awe 28 4 29 Doc
26. ettlement the only competent jurisdiction shall be the Courts of Geneva Switzerland The applicable law shall be the law of Switzerland The UN Convention on contracts for the International Sales of Goods shall not apply to these General Terms and Conditions of Sale SEVERABILITY If any provision of this agreement is or becomes at any time or for any reason unenforceable or invalid no other provision of this agreement shall be affected thereby and the remaining provisions of this agreement shall continue with the same force and effect as if such unenforceable or invalid provisions had not been inserted in this Agreement WAIVER The waiver by either party of any breach of any provisions of this Agreement shall not operate or be construed as a waiver of any other or a subsequent breach of the same or a different provision RELATIONSHIP OF THE PARTIES Nothing in this Agreement shall create or be deemed to create a partnership or the relationship of principal and agent or employer and employee between the Parties Neither Party has the authority or power to bind to contract in the name of or to create a liability for the other in any way or for any purpose RECYCLING The Demo Product is not to be disposed as an urban waste At the end of its life cycle differentiated waste collection must be followed as stated in the directive 2002 96 EC In all the countries belonging to the European Union EU Dir 2002 96 EC and those following differenti
27. functional configuration sessa 0000 eae 15 Switch 2 general purpose settingS 0 0 000 cece ae 16 Capacitors siias kindin iia PE Sy ae o a aa Yao Ba eae Mie eae a eas oe 17 Diodes connectors inductors amp transistors 1 ee eee 18 ROSIS Seersant ee Gee ae ae thst attics hee a E a Sh ace pee a e Se 19 Switch semiconductors amp crystals 0 0 tenet nee 21 Document revision history 0 ee ete nee 28 Doc ID 17555 Rev 1 ky UM0947 Contents Contents 1 Contents of the kit oa ea cn Re bean Red at nn oa 5 2 Connectors locations 000 cece eee eee 5 3 Features and block diagram 2 000 c eee eee eee 6 3 1 FOQUINGS cc ci be ee owl rantinpi sehen heseescacatew sags asea hee 6 3 2 BIOCK CIAGIaM seica mamaa vtinaet eed seieeieiegaetiteneed ees 6 4 Start UpP cdswsxsiceeietdenctctsaanaeseeredsetecectadaneeeeenns 7 4 1 UNPACKING svcuekndh dsr cdgaseued eee aE E a a O a E a aaa wee ede 7 4 2 CONNCCHOM s Fo 0heubete OE hbn Ekai kroken Set wees EARRA EEES 7 4 3 Booting procedure pesca fo obs bebe ee ee sD bee see he Sh SER lee oH Oe 7 5 Block descriptions 2 lt deck ive du dw eeee ews Hee ee Oe cds da seewweees 8 5 1 Dynamic memory subsystem 00 0 e ee ee 8 5 2 Static memory subsystem nanasan aaaea 8 5 3 External FPGA subsystem 0 000 eee 9 5 4 Ethernet subsystem 0 00 c eee 9 5 4 1 Configuration jumpers and switches 0000 c cece eee 9 5 4 2 Eth
28. nother can be used To do this deselect the on board Flash by removing jumper JP5 and connect an adapter board on J21 Figure 4 NAND Flash memory selection 1 2 3 1 2 3 U12 U12 Selected De selected JP5 JP5 Doc ID 17555 Rev 1 ky UM0947 Block descriptions 5 3 External FPGA subsystem This block includes an FPGA Xilinx Virtex4 LX60 plus its Flash memories and the JTAG interface for programming it The FPGA is connected to the SPEAr600 through a proprietary bidirectional bus This enables the development of IPs in the FPGA In this way the FPGA can be used as an expansion of the system When the FPGA is present 112 additional I O lines are provided on the expansion connector J1 A dedicated clock input line for the FPGA is also connected to socket U4 where an external oscillator can be installed if a special clock frequency needs to be input to the FPGA The oscillator output can be enabled or disabled using switch SW2 4 The interface between the FPGA and the SPEAr600 can be synchronous or asynchronous Its speed can also be set independently from the system speed This means that even with this interface is running at 60 80 MHz which can be considered as a reasonable speed all the other blocks of the SPEAr can still work at their maximum frequency 5 4 Ethernet subsystem This subsystem is based on the Ethernet GMII PHY DP83865 U14 and a connector that
29. ny other liability in connection with its Demo Products All other warranties conditions or other terms implied by law are excluded to the fullest extent permitted by law LIMITATION OF LIABILITIES In no event ST or its licensors shall be liable to You or any third party for any indirect special consequential incidental punitive damages or other damages including but not limited to the cost of labour re qualification delay loss of profits loss of revenues loss of data costs of procurement of substitute goods or services or the Doc ID 17555 Rev 1 23 29 License agreements UM0947 24 29 like whether based on contract tort or any other legal theory relating to or in connection with the Demo Product the documentation or this Agreement even if ST has been advised of the possibility of such damages In no event shall ST s aggregate liability to You or any third party under this agreement for any cause action whether based on contract tort or any other legal theory relating to or in connection with the Demo Product the documentation or this agreement shall exceed the purchase price paid for the Demo Product if any TERMINATION ST may terminate this license at any time if You are in breach of any of its terms and conditions Upon termination You will immediately destroy or return all copies of the demo software and documentation to ST APPLICABLE LAW AND JURISDICTION In case of dispute and in the absence of an amicable s
30. ot a finished product Certain demo software included with the Demo Product may be covered under a separate accompanying end user license agreement in which case the terms and conditions of such end user license agreement shall apply to that demonstration software DEMO PRODUCT STATUS The Demo Product is offering limited features allowing You only to evaluate and test the ST products You are not authorized to use the Demo Product in any production system and may not be offered for sale or lease or sold leased or otherwise distributed If the Demo Product is incorporated in a demonstration system the demonstration system may be used by You solely for your evaluation and testing purposes Such demonstration system may not be offered for sale or lease or sold leased or otherwise distributed and must be accompanied by a conspicuous notice as follows This device is not and may not be offered for sale or lease or sold or leased or otherwise distributed OWNERSHIP AND COPYRIGHT Title to the Demo Product demo software related documentation and all copies thereof remain with ST and or its licensors You may not remove the copyrights notices from the Demo Product You may make one 1 copy of the software for back up or archival purposes provided that You reproduce and apply to such copy any copyright or other proprietary rights notices included on or embedded in the demonstration software You agree to prevent any unauthorized copying of the Demo Pro
31. r dynamic debug The ETM9 block embedded in the SPEAr600 chip sends all the information about the AHB transactions during code Doc ID 17555 Rev 1 11 29 Block descriptions UM0947 5 7 12 29 execution to the external trace box and the external box stores this information in a local buffer This makes it possible by stopping the CPU activity to analyze the actual program flow For example if a particular data abort occurs you can set a breakpoint on the data abort location and then when the breakpoint is reached you can analyze the trace buffer With this information it becomes a simple task to identify the event that produced the problem The following configurations can be selected by setting SW1 bits 8 1 Table 6 Switch 1 configuration settings Switch 1 Description 3 2 1 0 0 0 No debug features available 0 0 1 The 1st ARM JTAG is connected to J8 0 1 0 The 2nd ARM JTAG is connected to J8 0 1 1 Both the ARM JTAGs are connected in a daisy chain on J8 The 1st ARM JTAG is connected to J8 and the 2nd ARM JTAG is connected to J18 1 0 1 ARM1 ETM bus available on J5 4 bit demultiplexed mode 1 1 0 ARM2 ETM bus available on J5 4 bit demultiplexed mode ARM1 ETM bus available on J5 and ARM2 ETM bus available on J6 Both in 4 bit demultiplexed mode 1 1 1 1 To make the ARM2 ETM bus fully available on J6 the board has to be set up as follows Populate
32. r to the miscellaneous register description in the SPEAr600 user manual available at www st com spear Switch 2 general purpose settings Default setting all bits OFF Table 10 Switch 2 general purpose settings Bit Description On The FPGA done signal controls the main reset to avoid any unwanted activity during the FPGA bit stream download 2 On The Serial Flash memories are protected against unwanted write operations 3 On Inhibits write operations on the I gt C EEPROM device 4 This switch controls the external oscillator U4 enable 5 This switch enables the boot through USB interface 6 This switch should be closed when the ETM interface is enabled and there is an LCD connected to prevent the LCD from disabling the LCD power by itself When DIP switch SW2 x is in the ON position the bit value is 0 When the DIP switch is in the OFF position the bit value is 1 Expansion connector An expansion connector J1 is provided to allow the user to add an additional board Part number TMMS 150 01 FM Q FS Samtec It mates with SQT 150 01 FM Q The following signals are available on connector J1 FPGA_GPIO 0 FRGA_GPIO 111 Three SoC GPIO lines Five Analog inputs A D 12V 1A 5V 1A 3 3V 200 mA 1 2V 200 mA For the connector pinout refer to the schematic drawing available on www st com spear Doc ID 17555 Rev 1 ky UM0947 User manual and board schematic
33. sed Software has been used or distributed in violation of this Agreement ST may by written notification request certification as to whether such unauthorized use or distribution has occurred You shall reasonably cooperate and assist ST in its determination of whether there has been unauthorized use or distribution of the source code of the Licensed Software and will take appropriate steps to remedy any unauthorized use or distribution You agree that ST shall have the right where ST reasonably suspects that the terms and conditions of this Agreement with reference to Restriction clause have not been complied with upon reasonable notice to enter Your official premises in order to verify your compliance with this Restriction clause NO WARRANTY The Licensed Software is provided as is and with all faults without warranty of any kind expressed or implied ST and its licensors expressly disclaim all warranties expressed implied or otherwise including without limitation warranties of merchantability fitness for a particular purpose and non infringement of intellectual property rights ST does not warrant that the use in whole or in part of the Licensed Software will be interrupted or error free will meet your requirements or will operate with the combination of hardware and software selected by You You are responsible for determining whether the Licensed Software will be suitable for your intended use or application or will achieve your intende
34. subsystem The dynamic memory subsystem is composed of three major parts Memory chip The memory used is a Micron DDR2 device and its part number is MT47H64M16HR 3 Its size is 128 Mb x 8 16 Mb x 8 x 8 banks Local power supply It is based on a linear regulator with a low drop voltage LD1117 1 8 It is generated locally in order to minimize the layout impact and also to avoid any noise injection between different subsystems Signal termination A parallel termination is added on the clock lines to compensate if needed the layout dissymmetry Two 100 Ohm resistors are used for each line in order to obtain an impedance of 50 ohms All the other terminations are directly inside the pads both on the SPEAr600 and the memory sides Static memory subsystem The static memory subsystem is composed of three major parts Serial Flash memory This block is based on an M25P64 ST Serial Flash memory device The size of this chip is 8 MB and with both the two banks populated we have a total of 16 Mbytes A switch SW2 2 is also provided to protect the Flash memory from any unwanted write access Serial IC EEPROM This block is based on the M24C04W ST Serial I gt C EEPROM The size of this chip is 4 Kb It also has a switch SW2 3 to protect the EEPROM from unwanted write access NAND Flash memory This block is based on ST NAND Flash NAND512W lt 3A U12 its size is 64 MB and its bus width x8 If required this chip can be replaced and a
35. tion below OIJ AJ wo N Test5 see Functional configuration below Table 8 Switch 1 debug configuration Test bit Debug configuration 3 2 1 0 0 0 Normal Mode No debug enabled 0 0 1 ARM1 JTAG connected to J8 0 1 0 ARM2 JTAG connected to J8 0 1 1 ARM1 and ARM2 JTAG connected in daisy chain to J8 1 0 0 ARM1 JTAG connected to J8 and ARM2 JTAG connected to J18 1 0 1 ARM1 ETM interface enabled J5 1 1 0 ARM2 ETM interface enabled J5 1 1 1 ARM1 and ARM2 ETM interface enabled ARM1 on J5 and AMR2 on J6 Table 9 Switch 1 functional configuration Test bit Functional configuration 6 5 4 0 0 O Default configuration 0 0 1 Nand Flash Interface disable not usable on the board 0 1 0 LCD interface disabled not usable on the board 0 1 1 GMAC interface disabled not usable on the board 1 0 0 FPGA interface enabled with clock and reset coming from FPGA to SPEAr 1 0 1 FPGA interface enabled with clock and reset coming from SPEAr to FPGA 1 1 0 Reserved 1 1 1 Reserved 4 Doc ID 17555 Rev 1 15 29 Expansion connector UM0947 Note 8 2 Note Note 16 29 When DIP switch SW1 x is in the ON position the bit value is 0 When the DIP switch is in the OFF position the bit value is 1 The default setting of SW1 is Bit 1 OFF all other bits 2 6 ON For more details on these settings refe
36. to be registered nor are they subject to the subsequent obligations NO WARRANTY The Demo Product is provided as is and with all faults without warranty of any kind expressed or implied ST and its licensors expressly disclaim all warranties expressed implied or otherwise including without limitation warranties of merchantability fitness for a particular purpose and non infringement of intellectual property rights ST does not warrant that the use in whole or in part of the Demo Product will be interrupted or error free will meet your requirements or will operate with the combination of hardware and software selected by You You are responsible for determining whether the Demo Product will be suitable for your intended use or application or will achieve your intended results ST shall not have any liability in case of damages losses claims or actions anyhow caused from combination of the Demo Product with another product board software or device ST has not authorized anyone to make any representation or warranty for the Demo Product and any technical applications or design information or advice quality characterization reliability data or other services provided by ST shall not constitute any representation or warranty by ST or alter this disclaimer or warranty and in no additional obligations or liabilities shall arise from ST s providing such information or services ST does not assume or authorize any other person to assume for it a
37. ts and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE ST PRODUCTS ARE NOT RECOMMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING O
38. y UM0947 License agreements SEVERABILITY If any provision of this agreement is or becomes at any time or for any reason unenforceable or invalid no other provision of this agreement shall be affected thereby and the remaining provisions of this agreement shall continue with the same force and effect as if such unenforceable or invalid provisions had not been inserted in this Agreement WAIVER The waiver by either party of any breach of any provisions of this Agreement shall not operate or be construed as a waiver of any other or a subsequent breach of the same or a different provision RELATIONSHIP OF THE PARTIES Nothing in this Agreement shall create or be deemed to create a partnership or the relationship of principal and agent or employer and employee between the Parties Neither Party has the authority or power to bind to contract in the name of or to create a liability for the other in any way or for any purpose 4 Doc ID 17555 Rev 1 27 29 Revision history UM0947 12 28 29 Revision history Table 15 Document revision history Date Revision Changes 1 Jun 2010 1 Initial release Doc ID 17555 Rev 1 UM0947 Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the produc
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