Programming the DSP56307/DSP56311 EFCOP in C Using
Contents
1. Initialize EFCOP Read input data from file Romeo peace umm a hu mo LA Lm L eLlLanmo mln Perform Residu on the DSP56300 Core DMA 1 finished Yes A A Disable EFCOP processed w Write output data to files End Update Data History Buffer EFCOP Performs Filtering Figure 15 Processing Steps Performed by Run resu c Programming the DSP56307 DSP56311 EFCOP in C For More Information On This Product Go to www freescale com T 1 2 3 4 5 6 7 8 Freescale Semiconductor Inc References Finally to maintain bit exactness with the ETSI standards saturation and two s complement rounding must be set For the EFCOP this is achieved by setting the Filter Rounding mode and the Filter Saturation mode For the DSP56300 core this is achieved using the following instructions _asm bset 20 SR Saturation Enabled asm bset 21 SR Two s complement rounding After running the code the results are verified by comparing the EFCOP result file out efcop_24 cod to the reference output file tvecs resu_24 cod Similarly the DSP56300 core results are verified by comparing the EFCOP result file out core_24 cod to the same reference output file tvecs resu_24 cod DSP56311 EFCOP and DSP56307 EFCOP Compared The DSP56311 EFCOP has a data memory ba2. Loop for each su bframe while fread amp coeff subframe_count t s_X 0 sizeof _fract Mtl fp in M 1 Initialiase Fi Copy coeffs lter Coefficients from X memory to Y memory i 0 for i lt M 1 ifdef DSP CORI coeffs Y i endif i P coeffs X i l For core calculation FCM buffer i coeffs X M i For EFCOP calculation reversed Para dag Zy at redde Be Mei d E doi im rimi Set up DMA Channel 0 to feed 50 data samples to EFCOP 40 samples in subframe 10 history samples Snan 2 ES Set up DMA Counter 0 for transfer of 25 2 items counter mode B Programming the DSP56307 DSP56311 EFCOP in C 47 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Code Listing for Residu Example DMA Counter 0 transfer of 25 4 items counter mode B 48 _asm movep 018001 x SFFFFED Source address start of input data buffer DSRO int input DMA destination address EFCOP Data Input Register DDRO int amp FDIR DMA Offset Regsiter 0 DORO 1 Offset 1 DMA ChO Control Register _asm movep 94AA04 x SFFFFEC DE 1 DMA Ch0 enabled KJ DIE 0 No interrupt at end of transfer DT 010 Line transfer 2D Clear DE
3. Define constants x X define FIR LENGTH 20 Length of FIR filter define INPUT LENGTH 200 Length of input data sequence Declare data buffers EFCOP coefficient and input data history buffers Located in bottom 4K as specified in efcopdma dsc _fract Y circ FCM buffer FIR LENGTH _fract X circ FDM buffer FIR LENGTH Other data buffers Located above 4K as specified in efcopdma dsc Programming the DSP56307 DSP56311 EFCOP in C 37 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Code Listing for FIR LMS Example _fract _X x INPUT_LENGTH Input signal _fract _X d INPUT LENGTH Desired signal _fract X y INPUT LENGTH Filter output signal _fract X e INPUT LENGTH Error signal _fract X d ptr d Pointer to desired signal x _fract X y ptr y Pointer to output signal x _fract X e ptr e Pointer to error signal fract mu2 0 02 FIR LMS filter convergence factor unsigned int count INPUT LENGTH Data sample counter EFCOP output interrupt service routine 2 ty void _long_interrupt 53 lms_isr void _fract Ke Local variable for 2ue n y ptr FDOR Get EFCOP output x Calculat n d n y n e ptr d_ptrt t y_
4. H I 0x000000 FDBA FDM buffer ee FCBA FCM_buffer pAr FCS EFCOP Control S R I 0x000000 FDOII FDIII IE ie js js js ni FDCM FCHL FISL 0 Scaling IIR Mode only FSA 0 24 bit Arithmetic Mode z FSM 0 No Saturation on Overflow FRM 0 Use Convergent Rounding FSCL 0 No scaling of output data EFCOP Decimation Channel Count Register 0 No Decimation EJ 0 No channels 1 EFCOP Data Buffer Base Address FDBA amp FDM_buffer 0 EFCOP Coefficient Buffer Base Address FCBA amp FCM_buffer 0 tatus Register 0 No Filter Data Out Interrupt EJ 0 No Filter Data Input Interrupt Programming the DSP56307 DSP56311 EFCOP in C 31 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Code Listing for FIR Filtering Example FSCO 0 No shared coefficients FPRC 0 State Initialization FMLC 0 Single Channel Mode FOM 00 Real FIR Filtering Mode XJ FUPD 0 No Filter Coefficient Update FADP 0 Non Adaptive Mode FLT 0 Filter Type FIR XJ FEN 0 Keep EFCOP Disabled for now lp ciertos 222 gt Initialize filter coefficients in FCM buffer reverse order o z L FCM_buffer 19 0 1825762 FCM_buffer 18
5. DPR 10 Priority 2 DCON 0 Continuous mode not needed DRS 10101 DMA Request is MDRQ11 EFCOP FDIBE D3D 0 Disable 3D mode DAM 100000 DMA Addressing Mode Source 000 2D DORO offset Dest 100 No update DDS 01 Destination FDIR is in Y memory DSS 00 Source input is in X memory k Set up DMA Channel 1 to take output from EFCOP Set DMA Counter 1 for transfer of 40 items counter mode A DCO1l L SUBFR 1 Note DCO No items 1 DMA source address EFCOP Data Output Register DSR1 int amp FDOR Destination address DDR1 int efcop output Programming the DSP56307 DSP56311 EFCOP in C For More Information On This Product Go to www freescale com ay a uu y E E ey Er Freescale Semiconductor Inc Code Listing for Residu Example Set up the DMA Control Register for Channel 1 DDR1 int efcop output Dest addess for DMA Chl amp efcop output 0 DMA Chl Control Register _asm movep 8EB2C1 x FFFFE8 DE 1 DMA Chl enabled api DIE 0 No interrupt at end of transfer DTM 001 Word Clear DE E7 DPR 11 Priority 3 DCON 0 Continuous mode not needed DRS 10110 DMA Request is MDRQ12 EFCOP FDOBF D3D 0 Disable 3D mode DAM 101100 DMA Addressing Mode Source 100 No updat
6. Source address start of input data buffer DSRO int input Destination address EFCOP s FDIR Programming the DSP56307 DSP5631 1 EFCOP in C 33 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Code Listing for FIR Filtering Example DDRO int amp FDIR DMA Offset Regsiter 0 DORO 1 Offset 1 DMA Ch0 Control Register DCRO I 0x14AA04 DE 0 DMA Ch0 disabled for now DIE 0 No interrupt at end of transfer DT 010 Line transfer 2D Clear DE DPR 10 Priority 2 DCON 0 Continuous mode not needed DRS 10101 DMA Request is MDRQ11 EFCOP FDIBE D3D 0 Disable 3D mode DAM 100000 DMA Addressing Mode Source 000 2D DORO offset Dest 100 No update DDS 01 Destination FDIR is in Y memory DSS 00 Source input is in X memory Ji B Set up DMA Channel 1 to transfer output data to EFCOP s FDOR DMA Counter 0 transfer of 81 items counter mode A DCO1 INPUT LENGTH FIR LENGTH Note DCO No items 1 Source address EFCOP s FDOR DSR1 int amp FDOR Destination address start of output data buffer DDR1 int output Offset 1 DMA Chl Control Register DCR1 I 0x0CB2C1 DE 0 DMA Chl disabled for now DIE 0 No interrupt at end of transfer
7. 10110 DMA Request is MDRO12 EFCOP FDOBF D3D O Disable 3D mode xj DAM 101100 DMA Addressing Mode Source 100 No update Dest 101 Post Inc by 1 16 Programming the DSP56307 DSP56311 EFCOP in C For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Transferring Data to and from the EFCOP DDS 00 Dest output is in X memory DSS 01 Source FDOR is in Y memory 4 2 3 DMA and DSP56300 Core Interaction The DSP56300 core sets up the DMA channels Then the EFCOP processes all of the data samples with no core intervention freeing the DSP56300 core to perform other tasks The DSP56300 core uses two different ways to check whether all samples have been processed e Polling The DSP56300 core checks the DMA Transfer Done DTD bit for the appropriate DMA channel in the DMA Status Register DSTR This bit is cleared by writing a one to it when the DMA transfer completes e Interrupts If the DMA Interrupt Enable DIE bit is set bit 22 of the DCRx register an interrupt occurs when the DMA transfer completes In both cases the DMA channel that is polled or configured to generate an interrupt at the end of the DMA transfer is normally the channel used to transfer data from the FDOR to memory since this is the last DMA transfer to take place 4 3 Interrupts The third method of transferring data to or from the EFCOP is to set the FDIBE or FDOBF bi
8. 0 1500447 FCM_buffer 17 0 1445724 FCM_buffer 16 0 1347942 FCM_buffer 15 0 0917701 FCM_buffer 14 0 0320759 FCM buffer 13 0 0027028 FCM buffer 12 0 0023077 FCM buffer 11 0 0008212 FCM buffer 10 0 0259985 FCM buffer 9 0 0611019 FCM buffer 8 0 0713257 FCM buffer 7 0 0528783 FCM buffer 6 0 0354474 FCM_buffer 5 0 0403820 FCM_buffer 4 0 0556321 FCM buffer 3 0 0559633 FCM buffer 2 0 0373912 FCM buffer 1 0 0203496 FCM buffer 0 0 0215175 Open input amp output files K 32 Programming the DSP56307 DSP56311 EFCOP in C For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Code Listing for FIR Filtering Example Open input file if fp_in fopen tvecs input txt r NULL printf Error Can t open tvecs input txt n exit 1 Open output file if fp out fopen out output txt w NULL printf Error Can t open out output txt n exit 1 fe Read data from input file E I for i 0 i INPUT LENGTH i if fscanf fp in x amp input i 1 printf Error reading input data n exit 1 ets Set up DMA Channel 0 to transfer input data to EFCOP s FDIR Memes ce e mem NND CP See re S ns c DMA Counter 0 transfer of 25 4 items counter mode B DCOO 0x018003
9. 7 Reserved 10 Programming the DSP56307 DSP56311 EFCOP in C For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Transferring Data to and from the EFCOP B int I facr type This union is then defined as follows which allows direct register access from the C code define FACR facr type Y OxFFFFB5 EFCOP ALU Control Register Two different union accesses are possible e Using the I member of the union for word access This method accesses the complete register and generates a single MOVEP instruction two program words FACR I 0x000001 Enable Filter Saturation e Using the B member of the union for bit field access This method accesses individual bits and generates BSET and BCLR instructions This method is not as efficient as the first one since more program words are used However it makes the code more readable and is useful while the code is developed and debugged FACR B FISL 0x0 Filter Input Scale applicable only in IIR mode FACR B FSA 0x0 Do not enable Sixteen bit Arithmetic Mode FACR B FSM 0x1 Enable Filter Saturation B B FACR B FRM 0x0 Choose rounding mode convergent FACR B FSCL 0x0 Choose Filter Scaling 1 no scaling 4 Transferring Data to and from the EFCOP The input data samples must be transferred from memory to the EFCOP data input register FDIR Simila
10. DT 001 Word Clear DE 34 Programming the DSP56307 DSP56311 EFCOP in C For More Information On This Product Go to www freescale com Ey X y E y s7 f y f Xy 7 Freescale Semiconductor Inc Code Listing for FIR Filtering Example DPR 10 Priority 2 DCON 0 Continuous mode not needed ay DRS 10110 DMA Request is MDRQ12 EFCOP FDOBF D3D 0 Disable 3D mode DAM 101100 DMA Addressing Mode Source 100 No update Dest 101 Post Inc by 1 DDS 00 Dest output is in X memory T DSS 01 Source FDOR is in Y memory E 2 Enable EFCOP and DMA channels DMA Chl first to allow at least 2 cycles to a occur before checking DTD1 bit E DCR1 B DE 0x1 Enable DMA Channel 1 DCRO B DE 0x1 Enable DMA Channel 0 FCSR B FEN 0x1 Enable EFCOP Xy 5 Core can now perform other processing tasks x m Amin eA d RE ciue n inum Other processing tasks are performed here Jum 5 Wait for output DMA transfer to finish ered a while DSTR B DTD1 0x0 Wait here until output DMA Ch1 finishes fx z Check FCONT for contention between EFCOP and Core N B If it is known that the core s activities cannot cause contention between the EFCOP and the core the abov 5 checking of FCONT can be omitt
11. and the offset when the EFCOP Data Output Buffer is full FDOBF is 6A The addresses are therefore VBA 68 and VBA 6A respectively 4 Table 7 shows the interrupt vectors for the EFCOP on the DSP56307 Table 7 EFCOP Interrupt Vectors Interrupt Interrupt rn Interrupt Address Number Interrupt Vector Priority Interrupt Enable Conditions VBA 68 52 Data input buffer empty 0 2 FDIIE FCSR 10 FDIBE 1 VBA 6A 53 Data output buffer full 0 2 FDOIE FCSR 11 FDOBF 1 18 Programming the DSP56307 DSP56311 EFCOP in C For More Information On This Product Go to www freescale com Freescale Semiconductor Inc EFCOP Initialization Mode In TASKING C a function is declared as an interrupt service routine using the special type qualifiers _long_interrupt and _fast_interrupt If a function declared as a fast interrupt cannot be implemented in two words or fewer the compiler automatically changes the function to a long interrupt service routine In this application note interrupts require more than two words of code so only long interrupts are used The following code segments illustrate the use of the long interrupt type qualifier for two interrupt service routines one triggered by the EFCOP FDIBE condition the other by the EFCOP FDOBF condition Example 4 Interrupt for FDIR void _long_interrupt 52 input isr void Note Interrupt number is 68 2 34 52 FDIR x_ptrt Load
12. 1 1 For details on the function of these registers consult the EFCOP chapter in the DSP56307 User s Manual Programming the DSP56307 DSP56311 EFCOP in C For More Information On This Product Go to www freescale com Freescale Semiconductor Inc EFCOP Overview Table 1 EFCOP Memory Usage Address Name Y FFFFBO Filter Data Input Register FDIR Y FFFFB1 Filter Data Output Register FDOR Y FFFFB2 Filter K Constant Input Register FKIR Y FFFFB3 Filter Count Register FCNT Y FFFFB4 Filter Control Status Register FCSR Y FFFFB5 Filter ALU Control Register FACR Y FFFFB6 Filter Data Buffer Base Address FDBA Y FFFFB7 Filter Coefficient Buffer Base Address FCBA Y FFFFB8 Filter Decimation Channel Register FDCH X 0 X 6FFF Filter Data Memory Bank FDM Y 0 Y SFFF Filter Coefficient Memory Bank FCM Table 2 lists the basic steps in programming the EFCOP along with the register s involved in each step Table 2 Overview of Steps in Programming the EFCOP and Its Registers Step Register Disable the EFCOP Filter Control Status Register FCSR FEN 0 Before filtering begins the DSP56300 core does the following Initialize the control and status register and the ALU control register Point to the start of the FCM Point to the start of the FDM Initialize the FCM buffer with the coefficients Copy the coefficients from the D
13. 8 References e 29 e f TM Ireescaie For More Information On This Go to www freescale semiconductor EFCOP inC c5 Te o ip e N o eo Te m n m o E D E E S Oo m Freescale Semiconductor Inc EFCOP Overview 1 Programming Examples Accompanying this application note are files containing examples of typical filtering configurations Each example presents an overview of relevant theory a description of implementation issues and techniques and a C code example You can obtain a zipped file containing all files required to run the examples from http www mot com SPS DSP documentation appnotes html This code was tested with the TASKING C C for DSP563xx 2 2 Rev 2 tool chain running under Windows NT 4 0 and Windows 98 The CrossView Pro Debugger runs the code on a DSP56307EVM 2 EFCOP Overview The DSP56307 EFCOP is a dedicated filtering hardware unit that implements many standard filtering structures It contains an independent filtering multiply and accumulate MAC unit giving the DSP56307 dual MAC capability It operates concurrently with the DSP56300 core giving the DSP56307 a maximum potential performance of 200 Million Instruction per Second MIPS The EFCOP supports two basic filtering architectures Finite Impulse Response FIR and all pole Infinite Impulse Response IIR These architectures can be combined to form a pole zero IIR filter Th
14. Assembler as563 Relocatable object files Obj Linker Ik563 TASKING STeering Program CC563 Object files out Locator 1c563 Absolute files abs Convertor TASKING EJ 37 ONCE JTAG i Debugger DSP56307 EVM RS232 Figure 5 Overview of TASKING Tools Suite Programming the DSP56307 DSP56311 EFCOP in C 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TASKING Tool Suite 3 2 FDM and FCM Source Code Declaration The FDM and FCM must be declared as arrays in the C source code with two specific names FDM_buffer and FCM_buffer respectively These names coincide with the section name declarations in the Efcopdma dsc description file Also the FDM and FCM buffers must match the fractional data format of the DSP56300 family architecture and be placed in X and Y memory respectively To achieve this match use the fract data type specifier and the X and Y memory specifiers Finally the FDM and FCM must be modulo buffers and therefore the compiler must place the two arrays FDM buffer and FCM buffer at modulo N addresses this is achieved using the circ specifiers The overall declaration is represented as follows fract X circ FDM buffer FIR FILTER LENGTH fract Y circ FCM buffer FIR FILTER LENGTH The correct memory mapping of the EFCOP array definition that is FDM buffer and FCM buffer is the result of the c
15. C using TASKING s Tool Suite for the DSP56300 family 6 The code was developed and tested on a DSP56307 evaluation module but the development approach the EFCOP concepts and the C code examples provided here apply equally to the DSP56311 The minor differences between the DSP56311 EFCOP and the DSP56307 EFCOP are stated in Section 7 Finally we recommend that you read this application note in conjunction with Chapter 10 of the DSP56307 User s Manual Enhanced Filter Coprocessor 1 Freescale Semiconductor Inc 2004 All rights reserved Order Number AN2106 u Rev 0 5 2001 Contents 1 Programming Examples 2 2 EFCOP Overview 2 2 EFCOP Modes eene 4 2 2 EFCOP Programming Model 4 3 TASKING Tool Suite 8 3 1 File Requirements for Programming the BECOP sseeeenren 8 3 2 FDM and FCM Source Code Declaration m 10 3 3 EFCOP Register Access in TASKING Cocieri 10 4 Transferring Data to and from the EFCOP 11 AD Polling oet 12 4 2 Direct Memory Access DMA 13 4 3 Interr pts ettet 17 5 EFCOP Initialization Mode 19 6 Application Examples 20 6 1 Software Installation and Concepts21 6 2 FIR Pilter iiisoeecee etin 21 6 3 Adaptive FIR filter 24 6 4 Residu Function from the GSM EFR AMR Vocoders27 7 DSP56311EFCOPandDSP56307 EFCOP Compared 29
16. MOTOROLA 1999 NOTES 1 DMA is used for sending data to and retrieving data from the EFCOP FEA A A A A Kk Ck Ck kk kk kk kk I A A AA AAA A AA AA Kk Kk kk kk ke ke ke ke ke ke kx include lt reg56307 h gt include lt stdio h gt include lt stdlib h gt a ear has bet sed es Fund Soa a ent er nt nd Define constants x define FIR_LENGTH 20 Length of FIR filter define INPUT LENGTH 100 Length of input data sequence LAN Declare data buffers eg ee ee PERPE XEM em eh iet EFCOP coefficient and input data history buffers Located in bottom 4K as specified in efcopdma dsc _fract Y circ FCM buffer FIR LENGTH _fract X circ FDM buffer FIR LENGTH Input and output data buffers Located above 4K as specified in efcopdma dsc _fract X input INPUT LENGTH 30 Programming the DSP56307 DSP56311 EFCOP in C For More Information On This Product Go to www freescale com _fract _X output INPUT_L void main Freescale Semiconductor Inc Code Listing for FIR Filtering Example FILE fp_in fp_out unsigned int i ENGTH FIR LENGTH 1 Initialize EFCOP i FCSR B FEN 0 Disable EFCOP for initialization Filter Count Register FCNT FIR LENGTH 1 5t FAC FDC f EFCOP ALU Control Register R I 0x000000
17. are written to the out output txt file This file should be identical to the reference file tvecs output txt 6 3 Adaptive FIR filter The adaptive FIR filter example presented in this section represents a 200 sample input signal filtered by a 20 tap filter 6 3 1 Theory Figure 13 shows the generic structure of an adaptive FIR filter The filter coefficients are time varying and are updated by an adaptation algorithm that modifies the coefficients so that the output signal of the FIR filter y k is as close as possible to some desired signal d k Many different adaptation algorithms exist In this example the well known Least Mean Squares LMS algorithm is used The filter coefficients of Eq 1 are modified at each time iteration according to the following update equation w k 1 w k 2ue k x k 2 where e w k is an Nx vector containing the filter coefficients at time k assuming an N tap filter e x k is an Nx 1 vector containing the N most recent input samples e e K is the difference at time k between the desired signal d k and the actual output of the filter x k e uis a convergence factor that controls the speed of adaptation u has a maximum limit beyond which the algorithm becomes unstable This limit depends essentially on the power of the input signal x k and careful choice of pt is therefore necessary d k yk 7 x k L 9 wg S gt e k Adaptati Sb 2 Afgorithr
18. data EFCOP Control Status Register Programming the DSP56307 DSP56311 EFCOP in C For More Information On This Product Go to www freescale com 39 Freescale Semiconductor Inc Code Listing for FIR LMS Example FCSR I 0x000884 FDOIE 1 Enable Filter Data Out Interrupt FDIIE 0 No Filter Data Input Interrupt ey FSCO 0 No shared coefficients FPRC 1 No State Initialization xy FMLC 0 Single Channel Mode FOM 00 Real FIR Filtering Mode xf FUPD 0 No Filter Coefficient Update Raf FADP 1 Adaptive Mode FLT 0 Filter Type FIR FEN 0 Keep EFCOP Disabled for now Af cns LL VeL Mute a Initialize of input data memory and filter coefficients X L4 for i20 i FIR LENGTH i FDM_buffer i 0 FCM_buffer i 0 Read reference signal from file a pron os Bac ak ey Open reference signal file if fpl fopen tvecs x txt r NULL printf Error Can t open tvecs x txt n exit 1 Read reference signal data for i 0 i INPUT LENGTH i if fscanf fpl Sx amp x il 1 printf Error reading input data n 40 Programming the DSP56307 DSP56311 EFCOP in C For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Code Listing for FI
19. e Value FDBA 1 gt x k Tj Data EET X K 2 received by FDM None x k 3 EFCOP starts alue Value processing Value Value lt o Value Value FDBA FCNT Value FDBA FCNT gt Value Four Input Samples FDIR Figure 9 EFCOP Data Memory in Non initialized Data Mode 6 Application Examples Three application examples illustrating the use of the EFCOP are presented in this section along with the C source code for each application e A Finite Impulse Response FIR filter e An Adaptive FIR filter using the Least Mean Square LMS algorithm e The Residu function from the Enhanced Full Rate EFR vocoder an FIR filtering process 20 Programming the DSP56307 DSP56311 EFCOP in C For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Application Examples 6 1 Software Installation and Concepts Create a directory for the software for example DSP56307 unzip the EFCOP_examples zip file and extract the software into the DSP56307 directory This operation creates three directories called efcop_fir efcop_firlms and efcop residu Within each directory two subdirectories are created out and tvecs as represented in Figure 10 efcop fir out tvecs DSP56307 efcop firlms out tvecs efcop residu out tvecs Figure 10 Directory Structure for the Filtering Examples Each directory contains the C source file s and the files required for program conf
20. in X memory Programming the DSP56307 DSP56311 EFCOP in C 15 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Transferring Data to and from the EFCOP The configuration principles are as follows e DMA Control Register DCR DMA Transfer Mode DTM word transfer triggered by request DMA Request Source DRS MDRQI2 see Table 3 4 DMA Address Mode DAM Source 1D counter mode B offset DORO Destination Selected by the user e DMA Counter Register DCO DpCOO0z number of samples 1 A 1 D DMA transfer from the FDOR register to memory programming example follows Example 3 DMA Transfer from FDOR to Memory vu Pc METTI T cer LIC L wr HDF UE EE ro M cH prr PCR Set up DMA Channel 1 to transfer output data to EFCOP s FDOR C m f PETIERE HET E p GER ar ae ae Gi p E DMA Counter 1 transfer of 81 items counter mode A DCO1 INPUT LENGTH FIR LENGTH Note DCO1 No items 1 Source address EFCOP s FDOR DSR1 int amp FDOR Destination address start of output data buffer DDR1 int output Offset 1 DMA Chl Control Register DCR1 I 0x0CB2C1 DE 0 DMA Chi disabled for now EA DIE 0 No interrupt at end of transfer DTM 001 Word Clear DE ay DPR 10 Priority 2 uf DCON O Continuous mode not needed L DRS
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22. transfers are used 4 1 Polling With the polling method of data transfer the core polls a status bit in the EFCOP FCSR to determine when it can transfer a data sample to or from the EFCOP The status bit polled depends on whether data is to be transferred from memory to the FDIR or from the FDOR to memory e For transfers from memory to FDIR the FDIBE bit which is set when the FDIR is empty is polled e For transfers from FDOR to memory the FDOBF which is set when the FDOR contains a valid output data sample is polled Recall that the filter buffer status bits FDIBE and FDOBF are directly accessed by FCSR B FDIBE and FCSR B FDOBF The following code segment illustrates the use of polling for both writing to the FDIR and reading from the FDOR This code is contained in a file named Transfer by Polling c Example 1 Use of Polling for Transferring Data main Initialize data buffers input and output Copy filter coefficients to FDM Initialize EFCOP Select arithmetic modes operating modes number of channels etc FCSR B FEN 1 Enable EFCOP for n 0 n NUMBER OF SAMPES n Poll FDIBE until set while FCSR B FDIBE 0 Wait for FDIBE to become 1 FDIR input n Feed data sample to FDIR Programming the DSP56307 DSP56311 EFCOP in C For More Information On This Product Go to www freescale com Freescale Semicon
23. AM 100000 DMA Addressing Mode Source 000 2D DORO offset Dest 100 No update DDS 01 Destination FDIR is in Y memory DSS 00 Source input is in X memory Jx EET CEDERE C da RET 25 as Set up EFCOP data output interrupts IPRP B EOL 2 Set EFCOP interrupt priority to 2 pragma asm Unmask all interrupt priorities er bclr 8 SR bclr 9 SR pragma endasm f K Enable EFCOP and DMA channel 0 in any order X FCSR B FEN 0x1 Enable EFCOP x DCRO B DE 0x1 Enable DMA Channel 0 pan tomtom panes pue tiri na ened pa Core can now perform other processing tasks 42 Programming the DSP56307 DSP56311 EFCOP in C For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Code Listing for FIR LMS Example Other processing tasks are here X Wait for filtering to finish ici en es while FCSR B FDOIE 1 Wait here until all samples have been processed Fl when count 0 in lms_isr FDOIE gets disabled Open output files Output signal y n if fpl fopen out y txt w NULL printf Error Can t open out y txt n exit 1 Error signal e n if fp2 fopen out e txt w NULL printf Erro
24. DSP56311 EFCOP in C 17 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Transferring Data to and from the EFCOP Table 5 and Table 6 list the priorities corresponding to these settings Table 5 Status Register Interrupt Masks ont iossinis interrupt Priority Level 0 0 IPL 0 1 2 3 0 1 IPL 1 2 3 1 0 IPL 2 3 1 1 IPL 3 Table 6 EFCOP Interrupt Priority Levels EOL1 IPRP 10 EoLo IPRP 11 FFCOP Star Priority 0 0 IPLO 0 1 IPL1 1 0 IPL2 1 1 IPL3 In the vectored interrupt architecture of the DSP56307 up to 128 interrupt sources cause the processor to jump to one of 128 program addresses These addresses are two words apart so if the interrupt can be serviced using only two words of machine code there is no need to jump to a larger interrupt service routine These interrupts are called fast interrupts In many cases however the interrupt requires more than two words of code In these cases the two words in the interrupt vector space contain a JMP instruction to the location of the interrupt service routine These interrupts are called ong interrupts The actual address of a particular interrupt vector consists of the Vector Base Address VBA which is stored in the VBA register plus an offset corresponding to the particular interrupt source For example the offset when the EFCOP Data Input Buffer is empty FDIBE is 68
25. FCOP output data n exit 1 Update data history for next iteration for i 0 i lt M i input i input i L_SUBFR Core buffer history End of while loop ifdef DSP_CORE Clear core ALU Saturation Mode and Rounding Mode asm bclr 20 SR Saturation Disabled Programming the DSP56307 DSP5631 1 EFCOP in C 51 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc asm bclr 21 SR No rounding fclose fp core out endif fclose fp_in fclose fp efcop out printf Residu completed n Sd subframes processed n n return END OF PROGRAM How to Reach Us Home Page www freescale com E mail support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Paci
26. FDIR with next value Example 5 Interrupt for FDOR void _long_interrupt 53 output isr void Note Interrupt number is 6A 2 35 53 y ptr4 FDOR Get value from FDOR If the interrupt service routines must perform further tasks such as error calculation for adaptive algorithms these tasks must be programmed within the routines 5 EFCOP Initialization Mode The EFCOP has two different filter initialization modes that are controlled by the Filter Processing Initialization Mode FPRC bit of the FCSR These modes inform the EFCOP of its processing starting point as follows see Table 8 e dnitialized data mode The EFCOP starts processing once the FDM buffer is full e Non Initialized data mode The EFCOP starts processing as soon as the FDIR receives the first sample Table 8 EFCOP Initialization Modes FPRC EFCOP Operation FPRC 0 The EFCOP starts processing once the FDM is full For an N tap filter the first output is Initialization mode generated after the Nth input is loaded into the FDIR FPRC 1 The EFCOP starts processing as soon as the first input sample is loaded into the FDIR No Initialization The values already in FDM are used to calculate FDOR so be careful to ensure that the FDM has been initialized manually before loading the first input data into the FDIR 5 The use of the fast interrupt and long interrupt type qualifiers is described in 7 Programming the DS
27. Freescale Semiconductor Inc Freescale Semiconductor Programming the DSP56307 DSP56311 EFCOP in C Using TASKING s Tool Suite Emmanuel Roy David Crawford Iain Stirling In the rapidly evolving arena of telecommunications the need for digital signal processors DSPs with ever greater performance continually leads to new high technology low cost devices with low power consumption and dissipation The DSP56307 DSP56311 processors are recent powerful additions to Motorola s high performance DSP56300 family of DSPs 1 2 4 Although the DSP56307 DSP56311 specifically target the telecommunications marketplace they are also ideally suited as general purpose devices Among the innovative features of the DSP56307 DSP56311 processors is a dedicated filtering hardware unit the Enhanced Filtering Coprocessor EFCOP that can potentially double the overall speed performance High level programming languages such as C and C greatly simplify the processors programing tasks including the EFCOP making the DSP56307 DSP56311 processors accessible to any engineer from DSP novices to DSP experts The combination of high processing performance and the ability to program in high level languages eases DSP56307 DSP56311 implementation reduces application development time and improves code readability and maintenance This application note examines the EFCOP modes of operation and explains how to configure and activate these modes from
28. M Contains the filter coefficients This bank of memory is mapped to the bottom 4K words of the Y data memory space The dual X and Y memory banks allow a simultaneous fetch of both the input sample and its corresponding filter coefficient so a complete MAC operation can be carried out in a single clock cycle The X and Y memory banks allocated to the EFCOP and shared with the DSP56300 core are each 4K x 24 bits so that filters with up to 4096 coefficients can be implemented In Multichannel mode the maximum number of coefficients for each filter is 4096 N where N is the number of filters being implemented For example for Freescale Semiconductor Inc N 64 which is the maximum value of N each filter can have up to 64 coefficients DMA BUS PMB Interface Control Logic FKIR Filter Constant GDB BUS 4 Word FDIR Data Input Buffer FDM Data Memory Bank 24 bit X Memory FONT Filter Count FCBA Coefficient Base FDBA Data Base Address Generator Y Memory FCM Coefficients Memory Bank 24 bit 24x24 56 bit Rounding and Limiting Output Buffer FDOR Figure 2 DSP56307 EFCOP Block Diagram Programming the DSP56307 DSP56311 EFCOP in C For More Information On This Product Go to www freescale com EFCOP Overview Freescale Semiconductor Inc EFCOP Overview 2 1 EFCOP Modes The EFC
29. OP operates in several different modes making it very flexible FIR filtering with real taps with complex taps generating a complex output that is real and imaginary for each complex input with complex taps generating alternate real and imaginary outputs in magnitude mode calculate the power of the input signal Note that decimation and input scaling can be used with these modes Adaptive FIR filtering Multichannel FIR filtering Note that decimation cannot be used with this mode All pole IIR filtering Note that input output scaling can be used with this mode Multichannel all pole IIR filtering Note that decimation cannot be used with this mode Initialization or non initialization of the EFCOP data buffer Data transfer using polling DMA or interrupts Several arithmetic options Two s complement rounding convergent rounding or no rounding 16 bit arithmetic mode Arithmetic saturation Examples in this application note include the following Use of the FIR and Adaptive FIR modes Initialization and non initialization modes 24 and 16 bit arithmetic modes Saturation mode Convergent and two s complement rounding modes Polling DMA and interrupt methods of data transfer 2 2 EFCOP Programming Model The EFCOP uses the FDM and FCM to store input data and filter coefficients EFCOP operation is controlled and monitored by nine memory mapped I O registers mapped in Y data memory as listed in Table
30. P56307 DSP56311 EFCOP in C 19 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Application Examples Figure 8 shows the EFCOP data memory in initialized data mode Although the FDM contains previous memory values the initialization mode fills the memory by the amount specified in the counter register FCNT before the EFCOP starts calculating the first output sample That is the first FCNT 1 samples are input before any filtering calculation is performed FDM FDM FDM FDM FOBA epe oe FDBA XX FDBA x Initialization FDBA 1 alue FDBA 1 x k 1 FDBA 1 x k 1 Value x K 2 x K 2 gees Value x k 3 x k 3 Value Value X K 4 starts processing Value Value x k 5 _ Value Value x k 6 FDBA FCNT Value FDBA FCNT _ Value FDBA FCNT _ x k 7 Automatic Four Input Samples Input Samples Transfer FDIR FDIR Figure 8 EFCOP Data Memory in Initialized Data Mode Figure 9 shows the EFCOP Data memory in non initialized data mode as soon as the first data samples are written into FDIR the EFCOP starts processing If this mode is used it is often worth initializing the initial data samples i e value in FDM to zero FDM FDM FDBA 1 FDBA gt Value FDBA gt x k
31. R LMS Example exit 1 fclose fpl Ser pa DERD Read desired signal from file ERN zoz Open desired signal file if fpl fopen tvecs d txt r NULL printf Error Can t open tvecs d txt n exit 1 Read desired signal data for i20 i INPUT LENGTH i if fscanf fpl Sx amp d i 1 printf Error reading input data n axa rjg fclose fp1 2inclnin c ncc IMPENDERE Lin L2 Set up DMA Channel 0 to transfer input data to EFCOP s FDIR Kc em LR olm Roe ENSE DMA Counter 0 transfer of 50 4 items counter mode B DCOO 0x031003 Source address start of input data buffer DSRO int x Destination address EFCOP s FDIR DDRO int amp FDIR Programming the DSP56307 DSP56311 EFCOP in C 41 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Code Listing for FIR LMS Example DMA Offset Regsiter 0 DORO 1 Offset 1 DMA Ch0 Control Register DCRO I 0x14AA04 DE 0 DMA ChO disabled for now DIE 0 No interrupt at end of transfer xf DT 010 Line transfer 2D Clear DE DPR 10 Priority 2 DCON 0 Continuous mode not needed DRS 10101 DMA Request is MDRQ11 EFCOP FDIBE D3D 0 Disable 3D mode D
32. SP56300 core to the FDM bank in reverse order Initialize the counter to N 1 where N is the length of the filter Initialize the decimation channel count Configure the EFCOP operation mode NOTE The coefficients must be stored in reverse order with respect to the input samples Filter Control Status Register FCSR and Filter ALU Control Register FACR Filter Coefficient buffer Base Address FCBA Filter Data Buffer Base Address FDBA EFCOP Coefficient Buffer Base Address Register FCBA Filter Data Buffer Base Address FDBA Filter Count Register FCNT Decimation Channel Count Register FDCH Enable the EFCOP Filter Control Status Register FCSR FEN 1 Programming the DSP56307 DSP56311 EFCOP in C For More Information On This Product Go to www freescale com Freescale Semiconductor Inc EFCOP Overview Table 2 Overview of Steps in Programming the EFCOP and Its Registers Step Register After the EFCOP has been triggered to begin filtering Input data samples are fed into the EFCOP to trigger it into calculating output samples The input samples can be transferred from a separate buffer in memory or from a memory mapped peripheral register for example A D converter Input samples can be transferred one two three or four words at a time since the FDIR is four words deep The EFCOP automatically stores these input samples in the FDM buffer which is essentially
33. This Product Go to www freescale com Freescale Semiconductor Inc Application Examples Initialize FCM Set up DMA 0 for transferring samples to the FDIR l Set up DMA 1 for transferring samples from FDOR Y Initialize EFCOP Y Read input data from file y Enable EFCOP v Enable DMA 0 and DMA 1 Y Perform other tasks while EFCOP performs filtering DMA 1 finished Write output data to file End Figure 12 Processing Step Performed by Fir c to Implement an FIR Filter Programming the DSP56307 DSP56311 EFCOP in C 23 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Application Examples After writing the filter coefficients to FCM setting up DMA channels 0 and 1 for data transfer to from the EFCOP and initializing the EFCOP itself the program reads the input data from the tvecs input txt file and then enables the EFCOP and the DMA channels to start the data transfers The EFCOP automatically starts an FIR filtering calculation when data is written to the FDIR The DSP56300 core then waits for DMA channel 1 to read the last sample from the FDOR DMA channel 1 is configured to produce an interrupt on completion of its transfer of all samples During this waiting period the DSP56300 core is free to perform other tasks in parallel with the EFCOP Finally the output data samples
34. a circular buffer of length N This ensures that the EFCOP has access to the N most recent data samples which are required to calcu late the corresponding output sample Filter Data Input Register FDIR The output sample is placed into the output register Once an output sample is available in the FDOR it must be read from the FDOR and can then be stored in memory or sent to a memory mapped peripheral regis ter for example a D A converter Data transfers to and from the EFCOP are initialized using polling DMA or interrupts These methods for transferring samples from memory to the FDIR and from the FDOR to mem ory are discussed in Section 4 Filter Data Output Register FDOR It is also important to note the location of the data sam ples and filter coefficients in the EFCOP memory banks Figure 4 represents both memory banks at an arbitrary time k where x k is the most recent input sample w are the filter coefficients and N is the filter length Note that for the next iteration FDBA will have advanced by one word and the filtering calculation will involve a wrap around Therefore the value held in FDBA varies as time progresses NOTE The EFCOP manages the value of FDBA and the placement of data samples in FDM The program mer need only be concerned with feeding values to the FDIR Filter Data buffer Base Address FDBA Figure 3 depicts the EFCOP operational model and Figure 4 shows how data is st
35. ductor Inc Transferring Data to and from the EFCOP ORK KK KK k KK IK I A KK I e x f EFCOP is now calculating output sample ORK IK KK KK AK I KK KK A I eee eee x f Poll FDOBF until set while FCSR B FDOBF 0 Wait for FDOBF to become 1 output n FDOR Get output data sample from EFCOP Repeat for next iteration End of main Although polling is the simplest method of transferring data to and from the EFCOP it suffers from the disadvantage that the DSP56300 core waits in a do nothing loop for the status bit to change The DSP56300 core is therefore unavailable for performing other tasks Polling is useful for testing the EFCOP configuration and verifying the proper functionality of an application However for greater efficiency other methods of data transfer that involve the DSP56300 core as little as possible are preferred 4 2 Direct Memory Access DMA DMA transfers input data samples from memory to the FDIR or output data samples from the FDOR to memory without requiring intervention from the DSP56300 core The DSP56307 has six DMA channels any of which can be used A DMA transfer using DMA Channel n involves the registers shown in Table 3 In addition to these general DMA registers the appropriate DMA offset registers must be used Table 3 DMA Registers Register n 0 5 Name Purpose DCRn DMA Control Register Sets the DMA modes req
36. e Dest 101 Post Inc by 1 DDS 00 Dest output is in X memory DSS 01 Source FDOR is in Y memory Initialize EFCOP FCSR I 0x000000 Clear register ensures EFCOP is disabled during initialization FDOIE 0 No Filter Data Out Interrupt ef FDIIE 0 No Filter Data Input Interrupt FSCO 0 No shared coefficients x FPRC 0 State Initialization 4 FMLC 0 Single Channel Mode FOM 00 Real FIR Filtering Mode x FUPD 0 No Filter Coefficient Update FADP 0 Non Adaptive Mode A FLT 0 Filter Type FIR FEN 0 Keep EFCOP Disabled for now FACR I 0x000035 Set up FACR pA FISL 0 Scaling IIR Mode only FSA 1 16 bit Arithmetic Mode wf Programming the DSP56307 DSP56311 EFCOP in C 49 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Code Listing for Residu Example FSM 1 Saturation on Overflow Ki FRM 01 Use 2 s comp Rounding x FSCL 01 Scaling of output data Scale lt lt 3 JUR to match C code implementation Ef FDCH I 0x000000 No decimation One channel FCNT M Filter length M41 xy FDBA FDM buffer EFCOP Data Buffer Base Address pr FCBA FCM buffer EFCOP Coefficient Buffer Base Address xf FKIR 0x000000 Clear Filter Constant Input Regi
37. e EFCOP architecture also has an adaptive FIR filtering mode with a flexible coefficient update mechanism that allows a range of adaptive algorithms to be used for example the Least Mean Square LMS algorithm the Normalized LMS and customized update algorithms However an adaptive IIR mode is not supported The EFCOP also runs in Multichannel mode with up to 64 FIR IIR filters We use the EFCOP to process data samples as shown in Figure 1 Input data samples are taken from the DSP56307 internal memory the EFCOP filters the data and the output data samples are stored back into internal memory Although we use internal memory in the applications discussed here external memory could also be used if desired x0 y0 Filtered Input x1 y1 Signal Signal x2 y2 x3 n EFCOP v X Y Memory r d H op 4 X Y Memory Xmemory Y memory bs Shared Memory dici NM DSP56300 Core access Figure 1 EFCOP Usage A block diagram of the EFCOP architecture is shown Figure 2 Programming the DSP56307 DSP56311 EFCOP in C For More Information On This Product Go to www freescale com Alongside the dedicated FMAC unit the DSP56307 EFCOP see Figure 2 uses two memory data banks e Filter Data Memory FDM Contains the filter input samples This bank of memory is mapped to the bottom 4K words of the X data memory space Filter Coefficient Memory FC
38. ed ER ai Programming the DSP56307 DSP56311 EFCOP in C 35 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Code Listing for FIR Filtering Example if FCSR B FCONT 0 printf s s s nFCONT 1 n Contention between EFCOP and Core occurred n No output written to file n else Write output data to file for i 0 i lt INPUT LENGTH FIR LENGTH 1 i fprintf fp out 06X n output i printf nFIR filtering complete n fclose fp in fclose fp out END OF PROGRAM 36 Programming the DSP56307 DSP56311 EFCOP in C For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Code Listing for FIR LMS Example Appendix B Code Listing for FIR LMS Example RK IK IK IK AA A A A A A A A kk kk I I I ke kk kk kk I FILENAME firlms c DESCRIPTION FIR LMS adaptive filtering using DSP56307 EFCOP PROJECT firlms pjt COPYRIGHT MOTOROLA 1999 NOTES 1 DMA is used for sending data to the EFCOP Interrupt service routines are used to retriev data from th EFCOP and to calculate the filter weight update constant FKIR FEA KA A A A kk kk kk kk A A A A A A KC A KK Kk Kk Kk kk kk ke ke ke ke ke ke e kf include lt reg56307 h gt include lt stdio h gt include lt stdlib h gt
39. evm dsc 56307evm cpu and 56307evm mem These files are for general purpose use of the DSP56307 processor and do not provide for use of the EFCOP because some applications do not need a dedicated filter coprocessor To use the EFCOP you need the following slightly modified versions of these files Efcopdma dsc Efcopdma cpu Efcopdma mem TASKING provides these EFCOP description files The key modifications pertain to the section location of the FDM and FCM buffers in the bottom 4K of memory at a modulo 2 address for example section XbssFDM buffer and section ybss FCM buffer which reside in the description file Ef copdma dsc All examples in this application note use the three E copdma xxx files and these files must be included into the application environment To use these description files you must set up the linker options in the EDE environment as follows e Target Hardware configuration DSP56307 Unified Memory Map e Select Use Project specific locator control file and write efcopdma 2 For details on TASKING contact 6 For details on the EDE tools suite refer to 6 7 and 8 3 For details on the description files refer to 7 8 Programming the DSP56307 DSP56311 EFCOP in C For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TASKING Tool Suite C files C C Pre processor and C compiler C563 Assembly files SIC
40. fic Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com subframe_count Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals
41. for Residu Example Located above 4K as specified in efcopdma dsc _fract X coeffs X M 1 _fract Y coeffs Y M 1 _fraet input L_SUBFR M X fract X core output L SUBFR X _fract efcop output L SUBFR Global variables unsigned int subframe_count 0 void main FILI Lu fp in fp efcop out ifdef DSP CORE I FILE fp core out endif unsigned int i Open data files for reading and writing ae if fp_in fopen tvecs resu_24 inp rb NULL printf Error Can t open input tvec tvecs resu_24 inp printf nProgram Aborted n exit 1 ifdef DSP CORE if fp core out fopen out core_24 cod wb NULL printf Error Can t open core output file out core_24 cod printf nProgram Aborted n exit 1 fendif 46 Programming the DSP56307 DSP56311 EFCOP in C For More Information On This Product Go to www freescale com if fp_efcop_out fopen out efcop_24 cod Freescale Semiconductor Inc Code Listing for Residu Example wb NULL printf Error Can t open EFCOP output file out efcop_24 cod printf nProgram Aborted n exit 1 ifdef DSP COR Set core ALU Sat _asm bset 20 SR Saturation uration Mode and Rounding Mode Enabled _asm bset 21 SR 2 s complement rounding endif
42. iguration Efcopdma cpu Efcopdma dsc and E copdma mem After creating a project for each application perform the following operations 1 Include the C file s in the project as appropriate 2 Setthe DSP56307 EVM as the target DSP within the EDE pull down menu Linker Locator Options Target Hardware 3 Within the same menu click on Use Project Specific Locator Control File and type E copdma into the window The application is now ready to compile and if the compilation is successful the CrossView Pro 8 high level debugger can be launched to run the code on the DSP56307 EVM The application reads input samples from existing data files in the tvecs directory and stores the filtered results in output files in the out directory These output files can then be compared to reference output files in t vecs to verify the application results However this process is specific to each application and is therefore further explained in the relevant sections that follow 6 2 FIR Filter In an FIR filter implementation using the EFCOP to minimize DSP56300 core intervention the DMA controller feeds the input data samples to the EFCOP and retrieves output data samples from the EFCOP The DSP56300 core is used only to set the EFCOP and the DMA modes and then to activate them The 6 The C Code for this example fir c is listed in Appendix A 7 See Section 4 Transferring Data to and from the EFCOP on page 11 for details
43. it Figure 13 Adaptive FIR Filter 9 The C Code for this example irlms c is listed in Appendix B 24 Programming the DSP56307 DSP56311 EFCOP in C For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Application Examples 6 3 2 Implementation The implementation of an LMS adaptive FIR filter on the EFCOP requires the steps shown in Figure 14 summarized as e Filtering of x k to produce y k This is identical to the fixed FIR filtering operation described in Section 6 2 FIR Filter on page 21 The filtering is triggered by writing an input data sample to the FDIR Updating the filter coefficients This is triggered by writing the value K 2ue k to the EFCOP FKIR The EFCOP must be in Adaptive FIR mode for adaptation to be triggered automatically The EFCOP then uses this value to update the filter coefficients according to Eq 2 After the EFCOP completes the filtering operation the DSP56300 core must calculate 2ue k which is 2u d k y k and then input this to FKIR to trigger the adaptation phase Therefore the DSP56300 core cannot be completely free in this instance The most efficient approach to this problem is to use the DMA controller to feed input values to the EFCOP via the FDIR and to configure the EFCOP to trigger an interrupt after calculating y k On receipt of the interrupt request the DSP56300 core then calculates K and feeds it to the FKIR thereb
44. it exact agreement with pre defined test sequences Therefore in this example the EFCOP is configured to conform to these requirements while processing the data 6 4 1 Implementation The Residu function that is performed on the EFCOP can also be performed on the DSP56300 core by defining the DSP CORE symbol within run resu c The input data in the tvecs resu_24 inp file is an ETSI test vector and is stored into an array input Both the DSP56300 core and the EFCOP use this input array After the data is filtered the filtered signals are stored in the array s core output and efcop output respectively These results are in turn written to the out Ncore 24 cod and out efcop_24 cod files Figure 15 shows the implementation flow Because of the 16 bit data requirements this application must be compiled in 16 bit arithmetic mode However you can still access all the memory range using the 24 bit addressing using the compiler option EDE C Compiler Options Project Options Code Generation l16 bit arithmetic 24 bit address This requirement modifies the way the DMA initialization is made Effectively from the two previous examples some registers are directly accessed using a union DCRO I 0x94AA04 DMA ChO Control Register This assignment is out of range since the constant is a 24 bit value so this value is truncated and compiled into the following movep SAA04 x lt lt SFFFFEC The most significant byte is los
45. itialize the Decimation Channel Count FDCH register 7 Initialize the EFCOP filter coefficients copy from the DSP56300 core to the FDM bank in reverse order 8 Enable the EFCOP set the FEN bit of the FCSR 9 Initialize data transfers to and from the EFCOP using polling DMA or interrupts 3 TASKING Tool Suite TASKING s DSP563xx Tool Suite is a high level development system that implements high level language applications C C and runs them efficiently on the DSP56300 family of processors You can use the highly flexible TASKING Tools Suite to program the DSP peripherals DSP interrupt service routines DMA transfers and for the DSP56307 DSP56311 the EFCOP The TASKING Tools Suite is accessed from the TASKING Embedded Development Environment EDE It includes a compiler assembler linker locator and debugger Figure 5 shows the overall suite which is customized for the application discussed here The examples in this document are all implemented from the EDE and run ona DSP56307 Evaluation Module EVM 3 1 File Requirements for Programming the EFCOP The TASKING Tools Suite uses different configuration files depending on the target hardware These files are description files that define device specific attributes such as memory sizes speed and so on They also define sections and locate the program and data words of an application into memory For the DSP56307EVM the TASKING defined description files are 56307
46. ming the DSP56307 DSP56311 EFCOP in C For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Code Listing for Residu Example Appendix C Code Listing for Residu Example RK HK IK kk IK A A A A A A A A kk kk kk kk kk kk kk ke kk kk kx kk FILENAME DESCRIPTION PROJE QI COPYRIGHT NOTES run resu c Test harness for running GSM EFR Residu on both the core and on the EFCOP residu pjt MOTOROLA 1999 1 DMA is used for sending data to and retrieving data from the 2 16 24 mode is residu on the EFCOP used since calculation of core needs 16 bit arithmetic Still need 24 bit addresses for on chip peripherals TK A A A A A kk kk kk kk Ck Ck A A A A A A AAA A A Kk Kk kk ke ko kk ke ke ke ke eek include include include include include define lt reg56307 h gt lt stdio h gt lt stdlib h gt enst h resu h DSP_COR P riens S Declare data buffers EFCOP coefficient and input data history buffers Located in bottom 4K fract fract Y circ FCM_buffer M 1 _X _circ FDM_buffer M 1 Other data buffers as specified in efcopdma dsc Programming the DSP56307 DSP56311 EFCOP in C 45 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Code Listing
47. mming the DSP56307 DSP56311 EFCOP in C For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Transferring Data to and from the EFCOP 4 2 2 EFCOP DMA Output Since the EFCOP output register FDOR is one word deep a 1 D DMA transfer from the EFCOP is necessary This type of transfer moves one word from the FDOR on each peripheral request Example 2 DMA Transfer from Memory to the FDIR m LM Ac EC ea aSa 2a A Set up DMA Channel 0 to transfer input data to EFCOP s FDIR x ee a P L DMA Counter 0 transfer of 25 4 items counter mode B DCOO 0x018003 Source address start of input data buffer DSRO int input Destination address EFCOP s FDIR DDRO int amp FDIR DMA Offset Regsiter 0 DORO 1 Offset 1 DMA Ch0 Control Register DCRO I 0x14AA04 DE 0 DMA ChO disabled for now DIE 0 No interrupt at end of transfer DT 010 Line transfer 2D Clear DE DPR 10 Priority 2 a DCON 0 Continuous mode not needed f DRS 10101 DMA Request MDRQ11 EFCOP FDIBE DBD 0 Disable 3D mode DAM 100000 DMA Addressing Mode Source 000 2D DORO offset Dest 100 No update DDS 01 Destination FDIR is in Y memory DSS 00 Source input is
48. nable EFCOP Y Enable DMA 0 Y Perform other tasks while EFCOP performs filtering Yes Write output data to file Error signal e k Output signal y k Coefficients w k End Interupt routine Ims isr Y Read y n from FDOR Y e n d n y n Y Ke 2me n Yes Last sample No FDOIE 0 Y Initialize EFCOP RTI Figure 14 Processing Steps by firlms c to Implement an Adaptive FIR Filter Programming the DSP56307 DSP56311 EFCOP in C For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Application Examples 6 4 Residu Function from the GSM EFR AMR Vocoders To illustrate the use of the EFCOP in a vocoder environment this section describes the implementation of the Residu function from the GSM EFR and AMR transcoders 9 Residu is an FIR filtering routine as described in Eq 1 that filters L 16 bit data samples L is typically equal to 40 through a FIR filter with N 16 bit coefficients N is typically equal to 11 For each value of k 0 k lt L the intermediate outputs have 32 bit precision Once all N coefficients and the corresponding data samples are multiplied and accumulated the 32 bit result is rounded to 16 bits to form y k GSM vocoders such as EFR and AMR use 16 bit fixed point arithmetic and the output data must be in b
49. nk and a coefficient memory bank of 10K words each As in the DSP56307 these banks are shared with the lowest 10K locations The DSP56311 EFCOP registers are identically memory mapped to the DSP56307 memory locations The DSP56311 is a 150 MHz part offering a potential performance of up to 300 MIPS with the DSP56300 core running concurrently with the EFCOP For details see the EFCOP chapter in the DSP56311 User s Manual The TASKING interface to the DSP56311 s EFCOP is the same as for the DSP56307 Contact TASKING 6 for details References DSP56307 User s Manual 24 Bit Digital Signal Processor Motorola Inc DSP56311 User s Manual 24 Bit Digital Signal Processor Motorola Inc DSP56307 24 Bit Digital Signal Processor Technical Data Motorola Inc DSP56300 Family Manual Motorola Inc APR23 D Using the DSP56300 DMA Controller Motorola Application Note Eliezer Sand 1997 http www tasking com TASKING C Compiler User s Manual TASKING CrossView Pro Debugger Manual Programming the DSP56307 DSP56311 EFCOP in C 29 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Code Listing for FIR Filtering Example Appendix A Code Listing for FIR Filtering Example RK HK IK IK IK A A A A A A KK KK KK Kk Kk I kk kk kk ck k oko k ko kk kk kk ke FILENAME forc DESCRIPTION FIR filtering using DSP56307 EFCOP PROJECT fir pjt COPYRIGHT
50. ombination of the array definition explained here and the configuration specified in Efcopdma dsc The EDE automatically generates these section names which are expected by the Efcopdma dsc description file If the described procedure is followed the EFCOP arrays declared are placed in shared EFCOP core memory that is X 0 X FFF and Y 0 Y FFF All arrays and variables declared with any other names are placed in shared DMA core memory namely X 1000 and Y 1000 unless the description file is modified to specify different section location addresses 3 8 EFCOP Register Access in TASKING C To facilitate reading and writing the EFCOP registers in C TASKING provides a header file for the DSP56307 processor reg56307 h that defines a memory map of all the DSP registers including peripherals Each declaration is based on the combination of unions and structures of bit fields that allow access to a complete register or to individual bits within a register These unions have two members e La24 bit integer e B agroup of bit fields totalling 24 or 16 bits For instance the union for the EFCOP Filter ALU Control Register FACR is typedef union EFCOP ALU Control Register struct unsigned FSCL 2 0 Filter Scaling unsigned FRM 2 2 Filter Rounding Mode int FSM 1 4 Filter Saturation Mode int FSA 1 5 Filter 16 bit Arithmetic Mode int FISL 1 6 Filter Input Scale int 17
51. on the DMA approach Programming the DSP56307 DSP56311 EFCOP in C 21 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Application Examples key steps involved in performing an FIR filtering task are described in the following subsections and a 100 sample signal with a 20 tap FIR filter is used in the example code The State Initialization mode is enabled 6 2 1 Theory Figure 11 shows the generic structure of an FIR filter The output sample at time index k is calculated as a weighted average of the N most recent input samples x k x k N 1 This is expressed mathematically as N x0 Y walk i 1 i 0 where N is the number of filter coefficients x k i is the input sample at time index k i y k is the output sample at time index k and w wy are the N coefficients of the filter x k y k Figure 11 FIR Filter Structure 6 2 2 Implementation The implementation of an FIR filter on the EFCOP using DMA for both input to the EFCOP and output from the EFCOP involves the steps shown in Figure 12 Since the implementation example uses the Initialization mode the EFCOP starts filtering after the FDM buffer is filled with the first N data samples 8 See Section 5 EFCOP Initialization Mode on page 19 for details on state initialization 22 Programming the DSP56307 DSP56311 EFCOP in C For More Information On
52. ored in the EFCOP Programming the DSP56307 DSP56311 EFCOP in C For More Information On This Product Go to www freescale com Freescale Semiconductor Inc EFCOP Overview FONT FCBA FDBA Address Generator FDM FCM Memory Memory Automatic X 0 X FFF Y 0 Y 6FFF 4 DSP56300 Core Access Transfer ji Filter Coefficients gt FDIR FMAC 7 FDOR r Input Samples Figure 3 EFCOP Modes of Operation FDBA EOM FOM A High FONTI x k wO l FCBA FCNT Address x k 1 wi Low WN 5 Address FDBA 1 x k N 2 wN PN FCBA 1 M FDBA x k N 1 wN4 lea FCBA EFCOP Calculation Figure 4 Storing Data Into the EFCOP Data and Coefficient Memory Banks In summary programing the EFCOP generally involves the following steps 1 Disable the EFCOP by resetting the FEN bit of the Control Status FCSR register 2 Initialize the EFCOP FCSR and ALU FACR registers 3 Initialize the EFCOP Filter Count FCNT register with the filter length 1 4 Initialize the EFCOP Data buffer Base Address FDBA 5 Initialize the EFCOP Coefficient buffer Base Address FCBA register Programming the DSP56307 DSP56311 EFCOP in C 7 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TASKING Tool Suite 6 In
53. ptrtt count Decrement data sample counter if count 0 If all input samples have been processed FCSR B FDOIE 0 Disable output interrupts to halt filtering else Adapt filter weights for next iteration Ke mu2 e ptr Ke 2 mu e FKIR Ke Load error constant into EFCOP s FKIR triggers weight update a 38 Programming the DSP56307 DSP56311 EFCOP in C For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Code Listing for FIR LMS Example void main FILE fpl fp2 fp3 unsigned int i LAK Initialize EFCOP FCSR B FEN 0 Disable EFCOP for initialization Filter Count Register FCNT FIR_LENGTH 1 EFCOP Data Buffer Base Address FDBA FDM_buffer FDBA amp FDM_buffer 0 EFCOP Coefficient Buffer Base Address FCBA FCM_buffer FCBA amp FCM_buffer 0 FKIR 0x000000 Clear Filter Constant Input Register EFCOP Decimation Channel Count Register FDCH I 0x000000 FDCM 0 No Decimation FCHL 0 No channels 1 k EFCOP ALU Control Register FACR I 0x000000 FISL 0 Scaling IIR Mode only FSA 0 24 bit Arithmetic Mode x FSM 0 No Saturation on Overflow FRM 0 Use Convergent Rounding FSCL 0 No scaling of output
54. r Can t open out e txt n exit 1 Filter weights w n if fp3 fopen out w txt w NULL printf Error Can t open out w txt n exit 1 aa 2 Check FCONT for contention between EFCOP and Core N B If it is known that the core s activities cannot cause Programming the DSP56307 DSP56311 EFCOP in C 43 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Code Listing for FIR LMS Example contention between the EFCOP and the core the abov checking of FCONT can be omitted e o Eire uta esie Mark isa isl e iur ii a i d d Rene i ho id Mee ete kid sa ui i nta o sd d i ce t Ie Sn id a Dei i ls d eh Mie ud a d n i if FCSR B FCONT 0 printf Ss s s nFCONT 1 n Contention between EFCOP and Core occurred n No output written to file n else Write output to files Write output signal y n to file for i20 i INPUT LENGTH i fprintf fpl 06X n y i Write error signal e n to file for i20 i INPUT LENGTH i fprintf fp2 s06X n e i Write filter weights w i to file reversed for i20 i FIR LENGTH i fprintf fp3 06XWMn FCM buffer FIR LENGTH 1 i printf NnFIR LMS complete Win fclose fpl fclose fp2 fclose fp3 END OF PROGRAM 44 Program
55. rly the output data samples must be transferred from the EFCOP data output register FDOR to memory as shown in Figure 6 EFCOP FDIBE 29 FDOBF TE nput 0 aaa as E RD eee ge cup iltere Signal i 1 Signal Transfer To FCSR Transfer From S y 0 X __ FDR FDOR 9 y 1 x 2 RET aA y 2 x 3 E p FMAC pos y 3 x 4 i NO te E 15 RUD et cn E X Y Memor i i gt i X Y Memor T FDM FCM i Figure 6 Transfer to and from the EFCOP Registers Programming the DSP56307 DSP56311 EFCOP in C 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Transferring Data to and from the EFCOP These transfers are accomplished using either polling DMA or interrupts All the different transfers rely on two status bits from the FCSR e Filter Data Input Buffer Empty FDIBE bit e Filter Data Output Buffer Full FDOBF bit The method for transferring data from memory to the FDIR need not be the same as the one for transferring data from FDOR to memory Any combination of the methods can be used For example transfers to the FDIR can use a DMA channel while transfers from the FDOR can use interrupts Note The FDIR register is a 4 word deep FIFO buffer so one to four words can be written to the FDIR at a time In this application note 4 word
56. ster Initialize data history to zero for i20 i lt M i input i 0 Core history buffer K Read input data from file 2 a a ee if fread amp input M sizeof fract L SUBFR fp in L SUBFR printf Error reading input data printf nProgram Aborted n exit 1 cm CHOR E mnl Enable EFCOP 4 FCSR B FEN 0x1 Enable EFCOP Perform Residu calculation on EFCOP ifdef DSP CORE 50 Programming the DSP56307 DSP56311 EFCOP in C For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Code Listing for Residu Example To Perform the same calculation on the core Call Residu on core Residu amp coeffs Y 0 amp input M amp core_output 0 int L_SUBFR fendif Check to make sure EFCOP has finished It will have while DSTR B DTD1 0 Wait here until DMA Chl has finished FCSR I 0x000000 Disable EFCOP ifdef DSP CORE Write core output to file if fwrite amp core output 0 sizeof fract L SUBFR fp core out L_SUBFR printf Error writing core output data n exit 1 endif Write EFCOP output to file if fwrite amp efcop output 0 sizeof _fract L_SUBFR fp efcop out L SUBFR printf Error writing E
57. t Note that x lt lt FFFFEC is the memory mapped address of the DCRO register Losing the two most significant digits is equivalent in this case to wrongly setting the counter register for DMA channel 0 There are several solutions to get round this issue The simplest is to force this assignment by replacing what the compiler sees as a register use of DCRO into an assembly instruction as _asm movep 94AA04 x lt lt SFFFFEC As a result the DSP data registers are avoided and the full 24 bit value is therefore transferred to DCRO Alternatively casting in C can be used to force the compiler to treat the value written to DCRO as a pointer 24 bit rather than as a 16 bit integer int X OxFFFFEC int 0x94AA04 C language version 10 The C Code for this example run resu c is listed in Appendix C Programming the DSP56307 DSP56311 EFCOP in C 27 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Application Examples 28 ifdef DSP_CORE Set Up For Core Code v Enable saturation and Two s Complement Rounding v Set Up For EFCOP Code Read Subframe Coefficients from File Y Initialize Coefficients Initialize FCM Y Set up and enable DMA 0 for transferring samples to FDIR Y Set up and enable DMA 1 for transferring samples from FDOR
58. t of the FCSR register to generate interrupts Unlike the DMA the FDIBE and FDOBF bits do not generate interrupt requests unless the EFCOP is configured to do so Interrupt service routines that service the appropriate interrupt request to perform the data transfer must be written and configured The interrupt method of data transfer requires DSP56300 core intervention since the DSP56300 core must stop its current activity to service the interrupt request However unlike polling the use of interrupts does not require the core to wait in a do nothing loop until FDIBE or FDOBF becomes set The following steps set up the interrupts for EFCOP data transfers 1 Set the interrupt mask bits bits 8 and 9 in the Status Register SR These bits determine which priorities of interrupt are masked 2 Set the priority levels of the EFCOP bits 10 and 11 of the Interrupt Priority Register Peripheral IPRP These priority levels should have a sufficiently high priority that they are not masked by the interrupt mask priority setting in bits 8 and 9 of the Status Register Setting the interrupt priority level is application dependent since other interrupts may be in use elsewhere in the system 3 Enable interrupt generation bits in the EFCOP status register FCSR Setting bit 10 FDIIE enables interrupt generation when the FDIR becomes empty setting bit 11 FDOIE enables interrupt generation when the FDOR becomes full Programming the DSP56307
59. the EFCOP is not used Memory below 4K is connected to the EFCOP instead of the on device DMA controller so only the EFCOP or the DSP56300 core can assess it 4 2 1 EFCOP DMA Input For the application discussed here four words are written to the FDIR each time A two dimensional 2 D DMA transfer to the EFCOP is also used This type of transfer moves four words into the FDIR on each DMA request as shown in Figure 7 A 1 D DMA channel could also be used without penalty see 4 Using a 2 D DMA transfer four words are transmitted each time a trigger from the EFCOP is received until the length of the input sequence is reached The only trick is to set the DMA offset register DORx to one The configuration principles behind this 2 D transfer are as follows e DMA Control Register DCR DMA Transfer Mode DTM line transfer triggered by request DMA Request Source DRS MDRQI1 see Table 3 4 DMA Address Mode DAM Source 2 D counter mode B offset DORO Destination No update no offset7 e DMA Counter Register DCO in mode B DCOL 3 DCOH number of 4 word blocks required 1 e DMA Offset Register DORO set to 1 Input samples 0s Transfer to FDM A 1 1 EFCOP 1 DORO 1 1 1 FDIR X Y Memory Figure 7 Four Word Deep FDIR Access Using DMA 4 For details on DMA refer to 4 and 5 14 Progra
60. uired DSRn DMA Source address Register Contains address of source data for DMA transfer DDRn DMA Destination address Register Contains address of destination for DMA transfer DCOn DMA Counter Register Contains number of items to be transferred For DMA transfers from memory to the FDIR set up the DMA channel to be triggered by FDIBE for DMA transfers from FDOR to memory set up the DMA channel to be triggered by FDOBF Issue DMA requests via internal peripheral DMA requests MDRQ11 and MDRQ12 respectively as shown in Table 4 Table 4 DMA Request Sources Request Condition Peripheral Request Number DCR Bits 15 11 DSR 4 0 FDIBE 1 MDRQ11 10101 FDOBF 1 MDRQ12 10110 Programming the DSP56307 DSP56311 EFCOP in C 13 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Transferring Data to and from the EFCOP The appropriate DMA channel should be set to respond to requests from MDRQI1 or MDRQI2 as required The EFCOP always generates DMA requests when FDIBE or FDOBF are set However a DMA transfer occurs only if the appropriate DMA channel is configured to respond to such a request If DMA transfers are used for both input and output two DMA channels are required The DMA controller cannot be used to access memory locations below 4K 1000 since the EFCOP uses this memory area for its coefficient and data buffers FCM and FDM This is true even when
61. y triggering the weight update phase Once the coefficient update phase completes the EFCOP starts the next filtering phase that is it waits for data to be input to the FDIR unless there is already data in FDIR and then it starts the next filtering operation to calculate y k Note The EFCOP can also be manually forced to update the filter coefficients when not in adaptive filtering mode This is achieved by setting the FUPD bit in the EFCOP FCSR Manual updating is useful in situations where adaptation of the coefficients is not required after every filtering operation but is only required occasionally The input files containing the input signal and the desired signal are tvecs Nx txt and tvecs Nd txt respectively Three output files are written into the out directory e out y txt contains the output signal e outVe txt contains the error signal e out w txt contains the updated coefficients These files should be identical to the reference files tvecs Ny txt tvecs e txt and tvecs w txt respectively Programming the DSP56307 DSP56311 EFCOP in C 25 For More Information On This Product Go to www freescale com 26 Freescale Semiconductor Inc Application Examples Main program flow Y Initialize EFCOP Y Initialize FCM amp FDM Y Read x n and d n signals from files Set up DMA 0 for transferring x n samples to FDIR Y Unmask interrupts Y E
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