ML67Q5260 - Digi-Key
Contents
1. 0 5 tscx 15 ns SPInSCK SPINSSN lag time 0 5 tscx 15 O 5 tscx 15 ns 1 Although actual values may become negative depending on the external load input the serial data so that the data hold time can be guaranteed 2 tSCK is the cycle time of the serial clock for SPI transferring which is obtained by dividing the frequency of the bus clock whose cycle time is tRUSCLK SPI master mode timing CPHA 0 SPINSSN A Output 7 lt tleap tsck A tac gt SPInSCK Po CPOL 0 Output SPInSCK A CPOL 1 Output K tsp tp A SPInMISO nou LSB i P X MSB to K 6 top SPInMOSI Output LSB 1 p X MB xX n 0 1 SPI master mode timing CPHA 1 SPINSSN Output A LEAD tsck gt tac SPInSCK CPOL 0 Output if SPInSCK CPOL 1 Output A A tsp top gt SPINMISO 0 Input LSB MSB il SPINMOSI top Output LSB MSB e f n 0 1 14 22 LAPIS Semiconductor Co Ltd Characteristics of slave mode timing Parameter Sim FEDL67Q5260 02 ML67Q5260 VDD coRE 1 62 to 1 98 V Vpp_10 3 0 to 3 6 V Ta 40 to 85 C Unit Serial clock cycle time tsck D ft ft 2 tBuscLk Serial clock High Low time O re ee teuscLk Data delay time output O tb Tos l e l ee ns Data setup time input tsp Ca ll A a Data hold time input tHo 30 p2. External Interrupt Input for FIQ S 4mA 1 D8 PBo8_ VO General Purpose PortB06__ O Smartcard IF Clock 4mA 1 D5 _PB05 _ 1 O General Purpose PortB05 O N Smartcard IF Reset 4maA 1 E8 PB04 _ 1 O General Purpose Port B04 1 O Smartcard IF Serial Data 4ma 1 F8 PB03 _ 1 O General Purpose PortB03_ O Smartcard IF Power Control 4ma 1 VO General Purpose Port B02__ O Smartcard IF Voltage Control 1 4ma 1 G8 PBOt VO General Purpose Port B01 O Smartcard IF Voltage Controlo 4ma 1 G7 PB00 VO General Purpose PortB00__ O Smartcard IF Card Detection 4ma 1 63 DM A USBdevD T fe 1 F4 DP A JjUSBdevD T fe CS fe G5 PUCTL O P USBdevPull up Control ama JO H8 TESTF A FLASHTestPin Csi F bal A8 BSEL1 P BootDeviceSelectt sf j i AFSEL_ P JTAG Select ARM FLASH sd PD 1 D1 TESTE P TestModeSelect lt o lt o o d e 6 22 FEDL67Q5260 02 Description Primary function Secondary function PU PD 1 5V Tolerant Initial direction Initial value I O Description Drive capacity 1 8V Power Supply for CORE VDDCORE p A1 A7 F7 B2 VDDIO E2 A6 F6 GNDIO 7 E6 D6 A5 G4 G
3. Smart Card interface Smartcard IF ISO UART x 1 channel Built in 16 byte FIFO Built in parity error counter in receive mode and transmit mode at automatic retransmission Supports asynchronous protocol of T 0 and T 1 according to ISO7816 and EMV Built in error detection code generation and error detection functions by hardware Supports DMA transfer e USB2 0 full speed device Compliant with Universal Serial Bus USB 2 0 Full speed 12 Mbps x 1 port End points 5 or 6 Supports all data transfer types control transfer bulk transfer interrupt transfer isochronous transfer Built in SOP generation and CRC5 16 generation functions Access size to data transfer FIFOs 8 bits 16 bits 32 bits FEDL67Q5260 02 ML67Q5260 2122 LAPIS Semiconductor Co Ltd e Random number generator RANDOM Generates 8 bit random numbers e Clock Input clock 12 MHz oscillator connected System clock CPU operating clock 32 MHz System clock is generated by PLL using 12MHz clock Output clock 6 12 MHz for fingerprint sensor e Power management Power saving mode Individual module clock stop mode Clock operation stop can be set for each functional block HALT mode Only CPU clock is stopped STOP mode All clocks are stopped and start stop of internal PLL and oscillator circuit are selectable e Package 63 pin WCSP Package S UFLGA63 4 03x4 01 0 50 W FEDL67Q5260 02 ML67Q5260 3122 LAP
4. is required when a slide sensor is used High speed authentication besides low power consumption The highly optimized fingerprint authentication accelerator achieves high speed authentication using a low speed clock Authentication lt 0 8 seconds 1 1 authentication lt 1 8 seconds 1 45 authentication Enrollment lt 2 seconds finger Applicable fingerprint sensor Slide sensor AuthenTec AES1751 128 x 8 pixels e CPU 32 bit RISC CPU ARM7TDMI S Little endian format Instruction system A high density 32 bit instruction and a 16 bit instruction of high object efficiency which is the subset of the 32 bit instruction can be executed in mixed mode General purpose register 32 bits x 31 registers Built in barrel shifter ALU and barrel shift operation can be executed by one instruction Built in debugging function JTAG interface The JTAG interface pin is shared with GPIO e Built in Memories 16 Kbyte working RAM for CPU 128 Kbyte Flash ROM for application program and fingerprint template data whose erase rewrite times are maximum 10 000 8 Kbyte Mask ROM for update of program in the Built in Flash ROM e Interrupt control 1 FIQ resource External 1 20 IRQ resources External 3 Internal 17 7 priority levels for each source CONNECTED ARM is a registered trademark of ARM Limited ARM7TDMI ARM7TDMI S AMBA are a trademark of ARM Limited 1122 LAPIS Semiconductor Co Ltd e DMA contro
5. specified in this document are not designed to be radiation tolerant While LAPIS Semiconductor always makes efforts to enhance the quality and reliability of its Products a Product may fail or malfunction for a variety of reasons Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury fire or any other damage caused in the event of the failure of any Product such as derating redundancy fire control and fail safe designs LAPIS Semiconductor shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual The Products are not designed or manufactured to be used with any equipment device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury such as a medical instrument transportation equipment aerospace machinery nuclear reactor controller fuel controller or other safety device LAPIS Semiconductor shall bear no responsibility in any way for use of any of the Products for the above special purposes If a Product is intended to be used for any such special purpose please contact a ROHM sales representative before purchasing If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and
6. the Foreign Trade Law you will be required to obtain a license or permit under the Law Copyright 2009 2011 LAPIS Semiconductor Co Ltd 22122
7. the clock oscillation stabilization 11 22 FEDL67Q5260 02 LAPIS Semiconductor Co Ltd ML67Q5260 Main Clock Timing Vpp_core noe to 1 98 V Vpp_10 3 0 to 3 6 V Ta 40 to 85 C Parameter Symbol Unit Main clock XI XO frequency EEE 12 x 0 9975 TER 12 x 1 0025 MHz l 83 33 x 83 33 x E 0 55 x Main clock XI XO H pulse width tsYscH 0 45 x tsysc t ns SYSC 0 55 x Main clock XI XO L pulse width tsyscL 0 45 x tsysc t ns SYSC 1 Main system bus clock within the LSI and operating clocks of CPU DMA etc Se IDC NS tsyscH tsyscL XI XO tBuscLk BUSCLK 12 22 FEDL67Q5260 02 LAPIS Semiconductor Co Ltd ML67Q5260 USB Access Timing Full Speed VDD coRE 1 62 to 1 98 V Vpp_UusB 3 0 to 3 6 V Ta 40 to 85 C Rise time 1 Te CL 50pF_ 4 20 ms Fall time 1 Te cl 50pF_ 4 20 ns Output signal crossover Vers CL 50 pF 25 V DP DM voltage Average bit rate e 12Mbps 0 25 19 EN pea TR and TF are transition time from 10 to 90 of Vpp uss 13 22 FEDL67Q5260 02 LAPIS Semiconductor Co Ltd ML6705260 SPI Access Timing Characteristics of master mode timing VDD coRE 1 62 to 1 98 V Vpop i0 3 0 to 3 6 V Ta 40 to 85 C Parameter Unit Data delay time output too o 35 ns Data setup time input 2 a n Data hold time input tHo CL 30pF o ns SPINSSN SPINSCK lead time O 5 tscx 15
8. 3x4 01 0 50 W Mr a IE PACKAGE MATERIAL EPOXY RESIN umt mm A Q51 68377 NOTES ERAN 1 THE DIMENSIONS ON PACKAGE OUTLINE INCLUDES THE TERMINAL SOLDER 2 THE BALL PITCH MEANS THE DISTANCES BETWEEN THE TERMINAL CENTERS a Od Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage Therefore before you perform reflow mounting contact ROHM s responsible sales person for the product name package name pin number package code and desired mounting conditions reflow method temperature and times 20 22 FEDL67Q5260 02 LAPIS Semiconductor Co Ltd ML67Q5260 REVISION HISTORY Page Document No Date Previous Current Description a PEDL67Q5260 01 Aug 18 2009 ia edont edition 1 PEDL67Q5260 02 Jul 15 2010 Preliminaryediion2 edition 2 FEDL67Q5260 01 Sep 15 2010 Final edition 1 Corrected Power dissipation to 450mW Changed IIL of Pull Up pin to 140 30uA Changed IIH of Pull Down pin to 30 140uA FEDL67Q5260 02 Jul 1 2011 1 1 Applicable fingerprint sensor AES1711 is deleted 21122 FEDL67Q5260 02 LAPIS Semiconductor Co Ltd ML67Q5260 NOTICE No copying or reproduction of this document in part or in whole is permitted without the consent of LAPIS Semiconductor Co Ltd The content specified herein is subject to change for improvement without notice The content spe
9. 5 V tolerant pins 3 Input ports VDD IO or0 V yt a wsio D S C420 jA ee pr O A A bwo 3 6 5 1 ESTO Do Other ports No load excluding the current flowing in pull up pull down resistors 4 LSI supply current when going into LSI stop mode by stopping clock oscillation PLL operation and random number generator operation and setting USB power down mode 5 The current supplied to the LSI when fingerprint authentication is executed without USB operation under the conditions that the programs are stored in the built in Flash ROM and no external memory are connected 6 Clock pulse is driven to XI clock input pin 9122 FEDL67Q5260 02 DC characteristics USB VDD coRE 1 62 to 1 98V VDD USB 3 0 to 3 6V Ta 40 to 85 C Parameter Symbol Max Unit Absolute value of the Differential input sensitivity Vo difference between the DP 0 2 and DM pins Differential common mode range jon cludes VOI range Includes VDI range 08 25 V Single end input threshold voltage 08 20 V ra W RL is connected Low level output voltage 15K W RL to 3 6 V a V Driver output resistance Steady state 28 44 O 10 22 FEDL67Q5260 02 AC Characteristics Reset Timing VDD coRE 1 62 to 1 98 V Vpn 10 3 0 to 3 6 V Ta 40 to 85 C Parameter Symbol Unit Reset pulse width Ll tesw 60 ms tRsTWw A S RESETN When power on release the reset after
10. An PBm input timing n 12 to 0 m 11 to 0 Torio Tg PIOIL PAn PBm 17 22 FEDL67Q5260 02 LAPIS Semiconductor Co Ltd ML67Q5260 Clock Output Secondary Function of PB11 Pin Timing VDD coRE 1 62 to 1 98 V Vpp_10 3 0 to 3 6 V Ta 40 to 85 C Parameter Symbol Unit o o 0 tcLKOUT tcLKOUT tcLKOUT o o o tcLKOUT tcLKOUT tcLKOUT torxout 1S the cycle time of the 6 MHz or 12 MHz clock generated by 2 clock sources and the frequency divide ratio Clock output secondary function of PB11 pin timing gg KA K K K K A AAAX2 gt tcLKOUT_H toLKOUT_L i i i i tcLkouT 18 22 FEDL67Q5260 02 LAPIS Semiconductor Co Ltd ML67Q5260 POWER ON OFF SEQUENCE Power ON sequence Core VDDCORE VDDPLL and IO VDDIO VDDUSB power should be on at the same time or IO VDDIO VDDUSB power should be on after Core VDDCORE VDDPLL on Power ON Sequence ad VDDIO VDDUSB Power On 1 8 V VDDCORE VDDPLL 0V rm Power OFF sequence Core VDDCORE VDDPLL and IO VDDIO VDDUSB power should be off at the same time or Core VDDCORE VDDPLL power should be off after IO VDDIO VDDUSB off Power OFF Sequence Power OFF 3 3 V VDDIO VDDUSB 19 22 FEDL67Q5260 02 LAPIS Semiconductor Co Ltd ML67Q5260 PACKAGE DIMENSIONS 000o OOOO OOOO DOODO 0 O O O O O D O O O e O C LAPIS Semiconductor Co Ltd S UFLGAG3 4 0
11. Data 4ma G6 PAtO VO General Purpose Port A10 __ 1 O SSIO Communication Clock 4ma 1 H6 PAO VO General Purpose PortAg9 1 SSIO Receive Data 4m 1 H7 PA08 1O General Purpose Port A8 O SSIO Transmit Data ss 4ma VO General Purpose Port A7 O SPI Clock forchi 4mA 1 E1 Paos VO General Purpose Port A6__ _ _ N SPISlaveSelectforcHt 4m 1 SPI Data for CH1 ia General Purpose Portas a le Master Receive Slave Transmit ny SMA BDS SPI Data for CH1 ve General Purpose Potaa ue A Master Transmit Slave Receive na SMA BOA C2 _PA03 VO General Purpose Port A3 WO SPI Clock for cho 4maj i A3 PA02 1O General Purpose Port A2 N SPI Slave Selectfor cHo 4ma 1 SPI Data for CHO ve General Purpose Porat n B Master Receive Slave Transmit a MA Ana SPI Data for CHO ds General Purpose Port AO n la Master Transmit Slave Receive AN sia Bng H4 PB11__ VO General Purpose Port B11 O Clock Output for sensor 4mA 1 gt 0 semanas premsa F3 PBo9 O General Purpose PortB09 External Interrupt Input for IRQ 28 S 4mA 1 E4 PBo8 _ 1 O General Purpose PortB08_ External Interrupt Input for IRQ 30 S 4mA 1 G1 PB07_ 1O General Purpose PortB07__
12. F E O A ns SPINSSN SPINSCK lead time El A ne SPInSCK SPINSSN lag time tac teusak 15 ns Slave data invalid time tois 25 ns SPI slave mode timing CPHA 0 SPINSSN Input ia tLean tsck ALA gt SPINSCK CPOL 0 Input K SZ S SPInSCK twsck fwsck CPOL 1 Input P VL 1 tis K top SPINMISO USB MSB Output H tso tb SPInMOSI input j LSB y MSB n 0 1 SPI slave mode timing CPHA 1 SPInSSN Input EE ta Lean tsek Ctac SPInSCK xs a CPOL 0 Input K twsck twsck SPInSCK CPOL 1 Input E CA No top SPInMISO Output LSB MSB EA tso tuo SPInMOSI Input LSB MSB n 0 1 77 15 22 FEDL67Q5260 02 LAPIS Semiconductor Co Ltd ML67Q5260 Synchronous SIO Access Timing Switching between master mode and slave mode can be set for this synchronous SIO by the software register setting Serial clock polarity can be switched When clock polarity is set to positive data is transmitted shifted out on the falling edge of the clock and is received shifted in on the rising edge of the clock At completion of 8 bit data transmission reception the clock stops at a high level and the last data is retained for data output When clock polarity is set to negative data is transmitted shifted out on the rising edge of the clock and is received shif
13. IS Semiconductor Co Ltd BLOCK DIAGRAM Built in Flash ROM 128 KB AHB I O Interrupt controller Fingerprint Accelerator APB I O Clock Reset Power Saving control Memory Management GPIO 2 ch 25 bits FEDL67Q5260 02 ML67Q5260 Working RAM Built in ROM 16KB 8KB DMA controller 2ch Built in FlashROM controller LSI controller Figure 1 Block Diagram 4 22 FEDL67Q5260 02 LAPIS Semiconductor Co Ltd ML67Q5260 PIN LAYOUT a ae Beith eel 2 ta elm fom mm a a oe ee ees ae En es ee G B A H F E D C S UFLGA61 4 03x4 01 0 50 W Bottom View 5 22 FEDL67Q5260 02 LAPIS Semiconductor Co Ltd ML6705260 PIN LIST gt Cc 2 S 2 52 iq a c rod A Q D4 j x I OscilationPin fT fe y beel bu D3 xo o OscillaionPin T fe E3 RESETN N SystemReset J l SS PU 1 D7 PRO P Buitin ROM Porto 2 Pu fil B6 RTCK O JTAGRetunClock ama J B7 Tok 1 JTAGTestCiock f Sd PY P 1 5 TMS 1 P JTAG Test Mode State sf bul ce TDI 1 JTAGTestDataln sf gt j i jC7 TDO_ O JTAGTestDataQut ma OH C8 NTRST N JTAGTestReset PU gt j i B5 PA12 1O General Purpose Port A12 _ SIO Receive Data 4mA 1 VO General Purpose Port A11 O SIO Transmit
14. L A P S FEDL67Q5260 02 SEMICONDUCTOR Issue Date Jul 2011 ML67Q5260 DFT Based Fingerprint Authentication LSI GENERAL DESCRIPTION The ML67Q5260 is a single chip LSI that executes fingerprint authentication without external memory by using the embedded fingerprint authentication accelerator This fingerprint authentication accelerator uses DFT Discrete Fourier Transform based algorithm licensed from Precise Biometrics and supports AuthenTec s slide sensors and certain touch sensors from several sensor manufacturers Besides the ML67Q5260 has the secure circuit to protect enrolled fingerprint data from unauthorized access Thus this LSI helps customers quickly design new products that offer convenient security as far as high performance fingerprint authentication low cost small size and high level of security FEATURES e Fingerprint authentication DFT Discrete Fourier Transform based algorithm licensed from Precise Biometrics This DFT based algorithm achieves a lower FTE False To Enrollment rate and a higher authentication accuracy especially when a slide sensor is used as compared to the minutiae algorithm Easy to use The fingerprint authentication is performed by the fingerprint authentication accelerator which does not ask customers for so complicated control No external memory Customer s application program and up to 45 fingerprint data can be stored in the embedded Flash memory on the ML67Q5260 No external memory
15. cified herein is for the purpose of introducing LAPIS Semiconductor s products hereinafter Products If you wish to use any such Product please be sure to refer to the specifications which can be obtained from LAPIS Semiconductor upon request Examples of application circuits circuit constants and any other information contained herein illustrate the standard usage and operations of the Products The peripheral conditions must be taken into account when designing circuits for mass production Great care was taken in ensuring the accuracy of the information specified in this document However should you incur any damage arising from any inaccuracy or misprint of such information LAPIS Semiconductor shall bear no responsibility for such damage The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products LAPIS Semiconductor does not grant you explicitly or implicitly any license to use or exercise intellectual property or other rights held by LAPIS Semiconductor and other parties LAPIS Semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such technical information The Products specified in this document are intended to be used with general use electronic equipment or devices such as audio visual equipment office automation equipment communication devices electronic appliances and amusement devices The Products
16. ller DMAC 2 channels Enable to allocate multiple DMA transfer request sources for each channel Channel priority fixed mode round robin mode DMA transfer mode cycle steal mode burst mode DMA request type software requests hardware requests Maximum transfer count 65 536 Data transfer size 8 bits 16 bits 32 bits Transfer request source CPU SPI Synchronous SIO Smartcard IF e GPIO 13 bits x 1 channel 12 bits x 1 channel Enable to setting input mode or output mode for each bit Enable to setting as interruption source for each bit Interruption mode level edge and positive logic negative logic e Timer 16 bit auto reload timer x 4 channel e Watch dog timer WDT 16 bit timer 8 389 seconds max when CPU operating frequency is 32 MHz Enables generation of interrupt or reset by setting e SIO UART Full duplex asynchronous mode Built in baud rate generator e SPI 2 channels of full duplex serial peripheral interfaces Operating mode master mode slave mode Data transfer size 8 bits byte 16 bits word Built in 16 byte 16 word FIFO on the transmission side and the reception side Supports DMA transfer master slave mode e Synchronous SIO SSIO clock synchronous serial port x 1 channel Data transfer size 8 bits byte Selectable clock polarity Selectable LSB first or MSB first Operation mode master mode slave mode Supports DMAC transfer in master mode only e
17. round for CORE 3 3V Power Supply for IO Ground for lO VDDPLL GNDPLL H2 VDDUSB 3 3V Power Supply for USB _ H1 GNDUSB GroundforPLL 1 PU PD column PU Pulled up with a built in resistor PD Pulled down with a built in resistor 2 This pin is used in the Built in ROM for an update function of the Built in FlashROM For details see the User s manual for USB firmware update function e ee Polary 0 oO VDDPLL _ GNDPLL eee Schmitt PB pprpo po poro Polarity PB Prop poro po eye TAE Sere rr TL 1 Termination of Pins Not Used DM DP PUCTL PA00 12 PBOO 11 Pulled down TDO RTCK TCK TMS TDI NTRST Pulled up TESTF Must be used as open 1122 LAPIS Semiconductor Co Ltd ABSOLUTE MAXIMUM RATINGS Parameter Digital power supply voltage CORE 1 8 V PLL power supply voltage 1 8 V Digital power supply voltage I O 3 3 V USB power supply voltage I O 3 3 V Input voltage normal buffer Input voltage 5 V tolerant Output voltage Input allowable current H output allowable current L output allowable current Power dissipation Storage temperature GUARANTEED OPERATING RANGES FEDL67Q5260 02 ML67Q5260 Symbol VDD PLL Rating Unit 0 3 to 2 5 Ui 0 3 to 4 6 ooo i ce Vi obo 10 to 10 pw fot a oo ee ee pe u Dts ETT GND 0 V Parameter Digital power supply voltage CORE 1 PLL power s
18. ted in on the falling edge of the clock At completion of 8 bit data transmission reception the clock stops at a low level and the last data 1s retained for data output The following waveforms show the cases where the clock polarity is positive Master mode Von _CORE 1 62 to 1 98 V Vop_ io 3 0 to 3 6 V Ta 40 to 85 C Parameter Unit Output data delay time 2 2 Input data setting time CL 30 pF BO ns Input data retained time D O Note 11 clock outputs for transferring 1s selectable from 2 synchronous SIO clock sources and the frequency divide ratios SSIOCLK SSIOTX SSIORX Serial clock Positive polarity Slave mode Von _CORE 1 62 to 1 98 V Vop_ io 3 0 to 3 6 V Ta 40 to 85 C Parameter Symbol Condition Min Typ Max Unit Serial clock cycle T 65s Output data delay time Kee a9 f 0 Input data setting time les Input data retained time 2 SSIOCLK tsssop lt gt tsssis sssiH lt gt lt gt SSIORX Serial clock Positive polarity 16 22 FEDL67Q5260 02 LAPIS Semiconductor Co Ltd ML67Q5260 GPIO PA PB Access Timing VDD coRE 1 62 to 1 98 V Vpop i0 3 0 to 3 6 V Ta 40 to 85 C Parameter Symbol Unit PAn PBm input H duration Teon tesaxkx2 ns PAn PBm input L duration Temon tuso ns Note 1 n 12 to 0 m 11 to 0 O P
19. upply voltage 1 Digital power supply voltage I O USB power supply voltage CPU operating frequency Ambient temperature Flash read Flash write Flash write count Unit Yeru PLL 7 Vwo Von uss pess NES 32 ve 40 235 85 a fread 40 25 8 c im fwrite 40 25 85 10 000 cycle 1 Please supply from same power source to both fom pins and Vpp pr pin 8 22 FEDL67Q5260 02 LAPIS Semiconductor Co Ltd ML67Q5260 ELECTRICAL CHARACTERISTICS DC Characteristics DC characteristics Core IO Parameter H input voltage L input voltage Schmitt trigger input threshold voltage 3 3 V Schmitt trigger input threshold voltage 5 V tolerant H output voltage Voo core 1 62 to 1 98 V Von 10 3 0 to 3 6 V Ta 40 to 85 C Max Unit Va o o 20 Vonio 03 Yao 03 A Ee oe V os Tie geste fae NU L output voltage lo 4 mA II os A SA High level input t 41 lA e Mir down 30 140 PVE Vppio High level t t 2 ee Vin 5 5 V A Low level input t 1 1 oler a uf 7w Low level input current 2 VEY 0V a e S o aE OZH 3 state output leakage current pulldown down o uA NS COAH lalo 1 EN pull up 140 30 Supply current during STOP Supply current during operation 5 Pins other than 5 V tolerant pins 2
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