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TITAN user manual - Eurotech Support Forums Topic Index

1. He 25 26 jg C 27 po 28 POG WAS w 29 ep E a EC a RP 36 42 Touchscreen controller 42 f M 43 id T HORE 45 Senla COMS BONS nn eee 46 pom M 50 Quick Capture camera interface 240 51 CSS FS a COSC yO 1 52 Temperature Sens OT asseris 52 JAG ana debug ACCESS EO 53 Power and power 54 mov ag be 54 Processor power 57 Peripheral devices power management 1 59 Connectors LEDs and 64 IP 65 AUS os De ee ee 78 T PUDE 78 Appendix A Board version 5
2. 82 Appendix B SDS Cll CARON PERTINET 84 Appendix C Mechanical 86 Appendix D Reference information 87 Appendix E ZEUS FPIF detalls 88 Appendix F ZEUS FPIF CRT 93 Issue D 3 TITAN user manual 3 EUROTECH Appendix G Ethernet Breakout 5 96 Appendix Acronyms and 98 Appendix RoHS 6 Compliance Materials Declaration Form 100 Eurotech Group Worldwide 101 eiat tere Introduction introduction Issue D The TITAN is an ultra low power PC 104 compatible single board computer based on the Intel 520MHz PXA270 XScale processor The PXA270 is an implementation of the Intel XScale micro architecture combined with a comprehensive set of integrated peripherals including e Flat panel graphics controller e Interrupt controller e Real time clock e Various serial interfaces The TITAN board offers a wide range of features making it ideal for power sensitive embedded communications and multimedia applications The board is available in two standard variants TITAN TITAN Lite TITANL The TITAN is available with a choice CPU frequency and memory configurations options as
3. As viewed from the connector pins 66 Issue D 3 EUROTECH J2 Camera interface connector Connector Neltron 2417SJ 20 PHD LEAD FREE 20 way 2mm 0 079 header Mating connector JST PHDR 20VS Mating crimps JST SPHD 002T P0 5 O N WO gt 11 13 15 17 19 Signal name 3V3 CIF_MCLK CIF_LV CIF_DDO CIF_DD2 CIF_DD4 CIF_DD6 I2C_SCL CIF DD8 GND J3 GPIO connector Connector Neltron 2417SJ 20 PHD LEAD FREE 20 way 2mm 0 079 header Mating connector JST PHDR 20VS Mating crimps JST SPHD 002T P0 5 Pin Signal name 1 3 5 7 9 11 13 15 17 19 Issue D Pin Signal name PER 45V 2 PO P2 P4 P6 GND P8 P10 P12 P14 4 6 8 Signal name 2V8 CIF_PCLK CIF_FV CIF DD1 CIF DD3 CIF DD5 CIF DD7 2 SDA CIF DD9 GND VCC PER 5V P1 P3 P5 P7 GND P9 P11 P13 P15 Connectors LEDs and jumpers 1 19 2 20 Do NOT attempt to power the TITAN using the VCC_PER pins VCC_PER is an isolated 5V supply switched under hardware control from the VCC input on J15 pin 1 ALWAYS provide 5V to VCC on J15 pin 1 67 TITAN user manual 3 EUROTECH LCD connector Connector Oupiin 3214 40COORBA SN 40 way 1 27mm 0 05 x 2 54mm 0 1 right angled boxed header Mating connector Oupiin 1203 40GB SN available from Eurotech on request Pin Signal name Pin Signal name 1 BLKEN Z 2 BLKSAFE 3 GPIO 16 PWMO
4. Connector Function PL1 10 100BaseTX Ethernet signals PL2 Ethernet LEDs PL3 RJ45 connector 7 o 504 8 2 2 1 8 1 Ethernet breakout PL1 Ethernet breakout PL2 Ethernet breakout PL3 96 Issue D 3 EUROTECH Appendix Ethernet Breakout details Ethernet signal mapping between TITAN and Ethernet breakout connectors Ethernet breakout PL3 Ethernet breakout PL1 TITAN J11 10 100BaseTX RJ45 2x4 way header Ethernet connector Signal name Signal name Pin Signal name 1 TX 1 1 2 TX 2 TX 2 TX 3 RX 3 RX 3 RX 4 4 Bob Smith 4 4 6 RX 6 RX 6 RX Bob Smith 7 NC 7 NC 8 Termination 8 LANGND 8 LANGND Ethernet LED signal mapping between TITAN and Ethernet breakout connectors Ethernet breakout PL2 TITAN J12 Ethernet status 1x 4 way header LED s connector Pin Signal name Pin Signal name 1 LINK LED 1 3 3V 2 LINK LED 2 LINK Green 3 SPEED LED 3 3 3V 4 SPEED LED 4 SPEED Yellow 5 3 3V 6 NC Issue D 97 TITAN user manual 3 EUROTECH Appendix H Acronyms and abbreviations 98 Amp API BTUART CCCR CODEC COM CPLD CPU CMOS CRT DMA DUART EEPROM EMC FFUART FIFO FLASH FPIF GPIO IEEE lO ISA JTAG kbps LED LCD LVDS Mbps NA NC NU OS PC 104 PCB PROM PWM RAM Reg RTC RX Amplifier Application Program ming Interface Bluetooth Universal As
5. Issue D The TITAN board is based on a PXA270 processor www intel com design pca prodbref 253820 htm The PXA270 processor is an integrated system on a chip microprocessor for high performance low power portable handheld and handset devices It incorporates on the fly voltage and frequency scaling and sophisticated power management The PXA270 processor complies with the Architecture V5TE instruction set excluding floating point instructions and follows the ARM programmer s model The 270 processor also supports Intel Wireless MMX integer instructions in applications such as those that accelerate audio and video processing The features of the PXA270 processor include e Intel XScale core e Power management e Internal memory 256KB of on chip RAM e Interrupt controller e Operating system timers Pulse width modulation unit PWM e Real time clock RTC General purpose GPIO e Memory controller DMA controller e Serial ports 3x UART Fast infrared port bus port AC97 Codec interface 5 Codec interface USB host controller 2 ports USB client controller 3x synchronous serial ports SSP e LCD panel controller 17 TITAN user manual 3 EUROTECH e Multimedia card SD memory card and SDIO card controller e Memory stick host controller e Mobile scalable link MSL interface e Keypad interface e Universal subscriber iden
6. LCD FCLK LCD LCLK LCD PCLK LCD BIAS DUART_ HDCNTL CB PSKTSEL CPLD_CS4 SEL_485 BIAS EN REDUCED _ SLEW DUART_ CLKSEL CB 1 LCD D16 LCD D17 USB_OC1 USB_PWE1 Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Active NA NA NA NA NA NA NA NA NA NA NA NA Low NA NA Low NA Low NA NA Function LCD data bit 10 LCD data bit 11 LCD data bit 12 LCD data bit 13 LCD data bit 14 LCD data bit 15 LCD frame clock STN vertical sync TFT LCD line clock STN horizontal sync TFT LCD pixel clock STN clock TFT LCD bias STN date enable TFT COM4 amp 5 0 RS485 half duplex control 1 Normal RTS function default 0 Socket 0 select 1 Socket 1 select Chip select 4 COM5 0 RS485 1 RS422 default 0 STN BIAS voltage off default 17 STN BIAS voltage on COM5 0 reduced slew 1 normal default DUART COM4 amp 5 clock pre scaler 0 divide by 4 1 divide by 1 default Socket 0 amp 1 low byte enable LCD data bit 16 LCD data bit 17 USB channel 1 over current detection USB channel 1 power enable 3 EUROTECH Sleep source See section 0 0 0 0 0 0 Flat panel 0 _ display support 0 0 0 1 Serial COMs g ports 1 1 E 1
7. 15 7 32 GND 16 8 33 GND 17 FPD9 Issue D 91 TITAN user manual Backlight inverter connector Connector 76384 407LF Mating connector FCI 65240 007LF Mating connector crimps FCI 76357 401LF Pin Signal name BKLSAFE BKLSAFE GND BKLEN BRT CTRL 2 3 4 GND 5 6 7 GND J5 STN bias connector Connector 76384 404LF Mating connector FCI 65240 004LF Mating connector crimps FCI 76357 401LF Pin Signal name 1 POSBIAS 2 GND 3 GND A NEGBIAS 3 EUROTECH Issue D SU Noises Appendix F ZEUS FPIF CRT details Appendix F ZEUS FPIF CRT details The ZEUS FPIF CRT allows the TITAN to drive a CRT monitor or an analogue LCD flat panel Sync on green and composite sync monitors are not supported 2 D a D J74 7 Ai 0 6 A III A I n o ME e 1 t F a BU Bul n r NW pn i rl is cw n em te C H The connectors the following pages shown in the same orientation as the picture above Connector Function J1 TITAN LCD cable connector J2 CRT connector Issue D 93 TITAN user manual 3 EUROTECH J1 TITAN LCD cable connector Connector Oupiin 3215 40CSB SN 40 way 1 27mm 0 05 x 2 54mm 0 1 straight boxed header
8. GPIO 889 Selected LVDS function 0 USB VBUS 1 over current 1 USB VBUS1 normal USB_OC2 GPIO 114 Selected LVDS function 0 USB VBUS2 over current 1 USB VBUS2 normal 43 TITAN user manual 3 EUROTECH VBUS power supplies are derived from PER 5V which is an isolated 5V supply switched under hardware control from the VCC input on J15 pin 1 GPIO 89 and GPIO 22 control the power to VBUS1 and VBUS2 respectively This is shown in the following tables USB PWE1 GPIO 89 Selected LVDS function 0 USB VBUS1 power off default 1 USB VBUS1 power on USB_PWE2 GPIO 22 Selected LVDS function 0 USB VBUS2 power off default 1 USB VBUS2 power on More information about the USB bus and the availability of particular USB peripherals can be found at www usb org USB client The TITAN USB host port 2 can be configured under software to be a client The following diagram shows the connection between PL 17 and a USB type A connector J10 USB connector type A 2 DATA 2 m DATA 2 lt M gt GND E 4 10 SHIELD 1 Do NOT attempt to power the TITAN using the VBUS 1 or VBUS 2 pins VBUS 1 and VBUS 2 are isolated 5 supplies switched under hardware control from VCC PER A ALWAYS use the USB client cable provided with the development kit This cable does not provide power down the cabl
9. Mating connector Oupiin 1203 40GB SN available from Eurotech on request Signal name Signal name 40 GND 39 CLOCK 38 GND 37 HSYNC 36 GND 35 VSYNC 34 GND 33 DE 32 GND 31 GND 30 NC 29 NC 28 14 27 FPD15 B a 26 12 25 FPD13 3 24 GND 23 GND 3 22 FPD10 21 FPD11 E 20 FPD8 19 FPD9 3 18 6 17 FPD7 HE 16 GND 15 GND 3 14 FPD4 13 FPD5 m 12 FPD2 11 FPD3 10 FPDO 9 FPD1 8 GND 6 5 NC 4 NC NC 2 BKLSAFE 1 94 Issue D eiat Appendix ZEUS FPIF CRT details J2 CRT connector Connector Oupiin 7916 15FA SN 15 way female high density right angled D Sub Signal name Pin Signal name Signal name 1 RED 6 RED GND 11 2 GREEN 7 GREEN GND 12 NC 3 BLUE 8 BLUE GND 13 HSYNC 4 NC 9 oV VGASAFE 14 VSYNC 5 TTL GND 10 SYNC GND 15 NC 5 1 2 it 20099 6 15 11 As viewed from the connector pins Issue D 95 TITAN user manual 3 EUROTECH Appendix G Ethernet Breakout details Eurotech can provide an Ethernet breakout board with an RJ45 connector to interface to the TITAN Ethernet connectors J11 and J12 The Ethernet breakout board features brackets for panel mounting ease It also features easy connection between the TITAN and a 10 100base T Ethernet connection as shown below PL1 PL2 PL3 picture above oh The connectors on the following pages are shown in the same orientation as the
10. e 128MB SDRAM may be available in the future Fixed on board memory e 16MB Flash TITAN Lite only e 32 64MB Flash 256KB of SRAM battery backed on board 256KB of SRAM internal to PXA270 Five UART 16550 compatible fast serial ports 921 6Kbaud e RS232 on COM1 COM2 COM3 and COMA e RS422 485 on COM5 software selectable Two USB 1 1 host controller ports One USB 1 1 client controller port software selectable on Host 2 One IEEE 802 3u 10 100Base T NIC port Option for external PoE SDIO socket to support MMC SD SDIO cards 16 bit PC 104 interface Real time clock battery backed on board Accuracy 1min month 18 bit flat panel interface for STN and TFT displays Supported resolutions e 320 x 240 8 16 18 bpp e 640 x 480 8 16 18 bpp e 800 x 600 8 16 18 bpp Optional LVDS interface AC 97 compatible CODEC stereo 20Hz to 20kHz in out frequency response Touchscreen support 4 5 wire analogue resistive Intel amp Quick Capture technology Multi master serial bus 128 byte I C configuration EEPROM Issue D 3 EUROTECH Watchdog timer Real time clock General I O Temperature sensor Test support Power requirements Mechanical Environmental Issue D Appendix Specification Internal to PXA270 causes reset on timeout timeout range 307ns 1321s Accuracy 1 minute month 16 x general purpose I O 2 temperature sensor JTAG interface 5V 5 Co
11. speed mode 3 4Mbps or CBUS compatibility You must keep bus loads added by the Quick Capture camera and any other devices added to the serial communications connector below 140pF Ensure any other devices added to the I C interface do not have the same addresses as detailed in the table above 50 Issue D 3 EUROTECH Detailed hardware description Quick Capture camera interface Issue D The Quick Capture interface is a component of Intel Quick Capture technology which provides a connection between the PXA270 processor and a camera image sensor The Quick Capture interface is designed to work primarily with CMOS type image sensors and supports resolutions up to 4 mega pixels However it may be possible to connect some CCD type image sensors to the PXA27x processor depending on the specific CCD sensor s interface requirements The Quick Capture interface acquires data and control signals from the image sensor and performs the appropriate data formatting prior to routing the data to memory using direct memory access DMA A broad range of interface and signalling options provides direct connection The image sensor can provide raw data through a variety of parallel and serial formats For sensors that provide pre processing capabilities the Quick Capture interface supports several formats for RGB and YCbCr colour space The Quick Capture interface signals are connected to the header J2 An C interface is available on the s
12. 2 GND mnm 76 Issue G EUROTECH Connectors LEDs and jumpers JP6 JTAG enable Connector Oupiin 2011 1x2GSB SN 2 way 2 54mm 0 1 single row through hole header Pin Signal name 1 1 VCC 5V 2 VCC JTAG This jumper is used to enable debug of PXA270 using JTAG interface JP6 Description JTAG Enable Normal Operation Default Only insert jumper for JTAG access to PXA270 The A jumper MUST be removed when the JTAG interface is not in use Issue D 77 TITAN user manual 3 EUROTECH Status LEDs There is a single status LED on the TITAN which indicates FLASH access to the FLASH memory silicon disk Jumpers There are nine user selectable jumpers on the TITAN the use of each one is explained below Default settings The factory default positions of the jumpers are shown below Jumper functions described in silkscreen on the board are shown in blue 2 2 JP1 JP2 JP3 JP4 JP5 JPG LCD Voltage RST gt 3l c Eg o o as 23 LK1 LK3 4A0 NO 4 2 Battery connect jumper LK1 on JP1 EISE ESE This jumper connects the battery to the battery back up circuit LK1 Description Battery supply connected NN Battery supply disconnected factory default 50500 If SRAM and or data is to be used jumper LK1 must be fitted to JP1 to provide battery power to these devices The jumper is l
13. 4 LCDSAFE 5 NEGBIAS 6 POSBIAS 7 GND 8 GND 9 FPD1 10 FPDO 11 FPD3 12 FPD2 13 FPD5 14 FPD4 17 18 FPD6 40 2 19 20 As viewed from the connector pins 21 FPD11 22 FPD10 23 GND 24 GND 25 FPD13 26 FPD12 27 FPD15 28 FPD14 29 FPD17 30 FPD16 31 GND 32 GND 33 BIAS DE 34 GND 35 FCLK VSYNC 36 GND 37 LCLK HSYNC 38 GND 39 PCLK CLOCK 40 GND 68 Issue D G EUROTECH Connectors LEDs and jumpers J5 Touchscreen connector Connector Neltron 2417SJ 05 F4 5 way 2mm 079 Pitch Wire to Board Header D Mating connector Molex 87369 0500 2mm 079 Pitch Crimp Housing Mating crimps Molex 50212 Pin Signal name 1 TSRY TR 2 TSRY BL 3 TSRX BR 4 TSRX TL 5 TSW J6 Audio connector Connector Neltron 2417SJ 12 PHD 12 way 2mm header Mating connector JST PHDR 12VS Mating crimps JST SPHD 002T P0 5 Pin Signal name Pin Signal name 1 LEFT IN 2 LEFT OUT 3 GND 4 GND 5 RIGHT IN 6 RIGHT OUT rg GND 8 AMP LEFT OUT 49 14 9 MIC VREF OUT 10 MIC IN 11 AMP RIGHT OUT 12 GND Issue D 69 TITAN user manual 3 EUROTECH J7 SDIO socket Connector Molex 67840 8001 2 50mm 098 pitch SD memory card connector Pin Signal name 1 2 MMCMD GND 4 313 5 6 7 MMDATO 8 MMDAT1 9 MMDAT2 10 WP 1
14. GPIO 81 and SEL TERM on GPIO 115 This is shown in the following table SEL 485 GPIO 81 Selected 5 function 0 RS485 half duplex 1 RS422 full duplex default co SEL _RS485 is at logic 1 upon reset The control signal SEL_TERM is used to enable disable the RS422 485 line termination and must be enabled if the TITAN board is at the end of the network This is shown in the following table SEL_TERM GPIO 115 COM5 termination resistors 120Q 0 Disconnected 1 Connected default ED SEL_TERM is at logic 1 upon reset The RS485 422 driver LTC2859 on the TITAN features a logic selectable reduced slew mode which softens the driver output edges to control the high frequency EMI emissions from equipment and data cables The reduced slew rate mode is entered by taking the SLO pin low where the data rate is limited to about 250kbps Slew limiting also mitigates the adverse effects of imperfect transmission line termination caused by stubs or mismatched cables The following table illustrates the selectable slew rates REDUCED _SLEW GPIO 83 Slew rate 0 Reduced 1 Issue 47 TITAN user manual 3 EUROTECH RS422 RS485 48 The RS422 interface provides full duplex communication The signals available are TXA TXB RXA RXB and Ground The maximum cable length for an RS422 system is 4000ft 1200m and supports 1 transmitter and up to 10 receivers This is a half duplex interface
15. Interface of the PXA270 processor The tables below detail the pins connections between the TITAN and Macraigor Wiggler or EPI Majic debug tools Of the Wiggler and Majic debug tools the Wiggler provides the best low cost solution TITAN JTAG connections TITAN J9 Debug tools pin names Pin Name Description Majic Wiggler 1 VCC3 Supply pin to JTAG debug VTRef VSupply Vref VTarget 3 GND Ground reference GND GND 4 nT RST PXA270 JTAG interface reset nT RST nT RST JTAG test data input to the 6 TDI PXA270 TDI TDI JTAG test data output from the 7 TDO PXA270 TDO TDO 8 TMS PXA270 JTAG test mode select TMS TMS 9 TCK PXA270 JTAG test clock TCK TCK 10 SRST System reset nSRST nSRST 2 5 NC No Connect Not required on TITAN RTCLK RTCK Not required on TITAN DBGREQ DBGRQ Not supported by TITAN DBGACK DBGACK In order to access the PXA270 your JTAG software needs to know the details of the two CPLDs on the TITAN The latest version of the XC9536XL and XC9572XL BSDL files for the 48 ball chip scale package can be found on the Xilinx web site Issue D 53 TITAN user manual Power and power management Power supplies The TITAN is designed to operate from a single 5V 5 4 75V to 5 25V supply The power connector J15 has a 12V connection defined but is not required for the TITAN under normal operation It can be used to supply 12V to the PC 104 stack if required For details of the power connect
16. POINT RS422 MULTI DROP RS485 MULTI DROP hae s Ic VS Number of wires Number of wires 5 Number of wires Transmitters enabled Transmitters enabled active RTS Transmitters enabled active RTS Receivers enabled Receivers enabled always Receivers enabled always Duplex mode Duplex mode full Duplex mode half SEL_485 SEL_485 HIGH SEL_485 LOW d Only set SEL_TERM to logic high if the TITAN is at the end of the network Issue D 49 TITAN user manual 3 EUROTECH PXA270 FC interface is brought out to the COMs connector J1 See the section J1 COMS ports page 66 for connection details The bus is also used with the Quick Capture interface See the section Quick Capture camera interface page 51 for more information The following table lists the on board l C devices Device name address External GPIO MAX7313 0x20 Temperature sensor LM75A 0x48 RTC ISL 1208 Ox6F Config PROM 24AA01 0x50 0x57 The PC unit supports a fast mode operation of 400kbps and a standard mode of 100kbps Fast mode devices are downward compatible and can communicate with standard mode devices in a 0 to 100kbps l C bus system However standard mode devices are not upward compatible so they should not be incorporated a fast mode bus system as they cannot follow the higher transfer rate and unpredictable states would occur The FC unit does not support the hardware general call 10 bit addressing high
17. SDIO data 2 SDIO data 3 SDIO command User configurable USB channel 2 over current detection RS422 485 COM5 0 No termination 1 1200 termination default GPIO interrupt l C clock Input Input Input Input Input Input Input 1 Input Input Input Input Input Input Input Input Input Input Input Input Quick Capture camera interface Quick Capture camera interface Audio Watchdog timer Watchdog timer Quick Capture camera interface Watchdog timer Serial COMs ports Flat panel display support Watchdog timer Quick Capture camera interface External interrupts USB Serial COMs ports General purpose I O 23 TITAN user manual Interrupt assignments Internal interrupts For details of the PXA270 interrupt controller and internal peripheral interrupts please refer to the PXA270 Developer s Manual on the Development Kit CD External interrupts The following table lists the PXA270 signal pins used for external interrupts 24 3 EUROTECH 270 GPIO 0 GPIO 1 GPIO 9 GPIO 11 GPIO 12 GPIO 13 GPIO 14 GPIO 17 GPIO 35 GPIO 53 GPIO 113 GPIO 116 Signal name AC97_IRQ DS_WAKEUP Peripheral Audio CPU COM10R4_WAKEUP COMS 5 IRQ OVERTEMP USER_LINKA ETH IRO PC104 IRQ USER LINKB MMC CD USER LINKC GPIO_IRQ COMS Temperature sensor User Ethernet PC 104 User SDIO
18. and modem control signals The maximum baud rate on this channel is 921 6kbps A factory fit option configures COM1 as TTL Level signals to interface to a modem Please contact Eurotech for details Contact details are provided in Eurotech Group Worldwide Presence page 101 CON RS232 interface Uses the Bluetooth UART in the PXA270 BTUART The port is buffered to RS232 levels with 15kV ESD protection and supports full handshaking and modem control signals The maximum baud rate on this channel is 921 6kbps COM3 RS232 interface 46 Uses the Standard UART in the PXA270 STUART The port is buffered to RS232 levels with 15kV ESD protection and supports full handshaking and modem control signals The maximum baud rate on this channel is 921 6kbps Issue D G EUROTECH Detailed hardware description COM4 RS232 interface The COM4 RS232 interface is supported on channel 0 of an Exar XR16C2850 with 128 bytes of Tx and Rx FIFOs and buffered to RS232 levels with 15kV ESD protection The maximum baud rate on this channel is 921 6kbps COM5 RS422 485 interface The COM5 RS422 485 interface is supported on channel 1 of an Exar XR16C2850 with 128 bytes of Tx and Rx FIFOs and buffered to RS422 485 levels with x15kV ESD protection The maximum baud rate on this channel is 921 6kbps Two GPIOs from the PXA270 provide RS422 RS485 selection and termination resistor selection options The two control signals are SEL 485 on
19. bit ISA bus style peripherals Eurotech has a wide range of PC 104 modules that are compatible with the TITAN These include modules for digital I O analogue I O motion control video capture CAN bus serial interfaces etc Please contact the Eurotech sales team if a particular interface you require does not appear to be available as these modules are in continuous development Contact details are provided in Eurotech Group Worldwide Presence page 101 To use a PC 104 board with the TITAN plug it into J13 for 8 bit cards and J13 J14 for 8 16 bit cards See the sections PC 104 interface page 29 and J14 amp J15 PC 104 connectors page 74 for further details The ISA interface on the TITAN does not support DMA shared interrupts and some access modes See the section PC 104 interrupts page 30 for details about PC 104 interrupt use The TITAN provides 5V to a PC 104 add on board via the J13 and J14 connectors If a PC 104 add on board requires a 12V supply then 12V must be supplied to the TITAN power connector J15 pin 4 If 12V or 5V are required these must be supplied directly to the PC 104 add on board The TITAN is available with non stack through connectors by special order Contact Eurotech for more details see Eurotech Group Worldwide Presence page 101 14 Issue D 3 EUROTECH Detailed hardware description Detailed hardware description The following section provides a detailed description of the
20. internal 256KByte static RAM and RTC 12 connection is defined but is not required for the TITAN under normal operation It can be used to supply 12V to the PC 104 stack if required A momentary switch push to make may be connected across Reset and GND Do NOT connect the switch across Reset and VCC or 12V JP1 Battery disconnect Connector Oupiin 2011 1x2GSB SN 2 way 2 54mm 0 1 single row through hole header Pin Signal name 2 Battery backup 1 nes o switch input 2 Battery terminal 1 Issue D 75 TITAN user manual 3 EUROTECH JP2 LCD logic supply selection Connector Oupiin 2011 1x3GSB SN 3 way 2 54mm 0 1 single row through hole header Pin Signal name 1 VCC PER 5V 2 LCD logic supply 4 3 3V3 LVDS MSL selection y Connector Oupiin 2011 1x2GSB SN 2 way 2 54mm 0 1 single row through hole header 1 Pin Signal name 1 MSL 2 3V3 4 User Recovery link selection Connector Oupiin 2015 2x4GDB SN 8 way 2 54mm 0 1 dual row surface mount header Pin Signal name Pin Signal name 1 GND 2 USER LINKA 7 1 3 GND 4 USER LINKB 5 GND 6 USER LINKC 8 2 7 GND 8 RECOVERY JP5 External reset Connector Oupiin 2011 1x2GSB SN 2 way 2 54mm 0 1 single row through hole header Pin Signal 1 Reset 2 5 1
21. link is made and the speed LED illuminates when 100Mbps speed is selected The Ethernet Breakout interface board provides the user with an RJ45 connector with LEDs to connect an Ethernet cable to the TITAN see page 96 Contact Eurotech see Eurotech Group Worldwide Presence page 101 for purchasing information for the Ethernet Breakout 45 TITAN user manual 3 EUROTECH Serial COMs ports There are five high speed fully functionally compatible 16550 serial UARTs on the TITAN Four of these channels can be used as RS232 serial interfaces and the remaining one COMS can be configured as RS422 or RS485 Connection to the TITAN COMs ports is via header J1 See section J1 COMS ports page 66 for connector and mating connector details FIFO depth Port Address IRQ RX TX 5 1 0 40100000 Internal 64 64 RS232 Rx Tx CTS RTS RI 0x4010002C DSR DCD DTR COM2 0 40200000 Internal 64 64 RS232 Rx Tx RTS CTS 0x4020002C 0 40700000 Internal 64 64 RS232 Rx Tx 0x4070002C COM4 0x10000010 GPIO 10 128 128 RS232 Rx Tx CTS RTS RI 0x1000001E DSR DCD DTR 5 0 10000000 11 128 128 RS422 RS485 Tx Rx 0x1000000E Please see the Developer s Manual for details of internal interrupts COM1 RS232 interface Uses the Full Function UART in the PXA270 FFUART The port is buffered to RS232 levels with x15kV ESD protection and supports full handshaking
22. only be used as a wake up source from deep sleep 25 TITAN user manual 3 EUROTECH Watchdog timer The TITAN uses an external watchdog timer MAX6369 which can be used to protect against erroneous software The watchdog timer can be programmed using WD SETO 2 for timeout periods between 1ms and 60s When the timeout occurs the TITAN is reset The watchdog timeout period is summarized in the following table WD SET2 WD SET1 WD SETO GPIO 99 GPIO 97 GPIO 96 Timeout period 0 0 0 1ms 0 0 1 10ms 0 1 0 30ms 0 1 1 Disabled default 1 0 0 100ms 1 0 1 15 1 1 0 105 1 1 1 605 Once the timeout period is set the WD_WDI GPIO102 watchdog input signal must be toggled within the timeout period If WD WDI remains either high or low for the duration of the watchdog timeout period the watchdog timer triggers a reset pulse The watchdog timer clears whenever a reset pulse is asserted or whenever WDI sees a rising or falling edge For further details see the Eurotech operating system Technical Manual and the PXA270 Developer s Manual on the Development Kit CD 26 Issue D 2 EUROTECH Detailed hardware description Memory The TITAN has four types of memory fitted A16MB TITAN LITE only 32MB or 64MB resident FLASH disk containing Boot loader Redboot to boot embedded Linux or Eboot to boot Windows CE Embedded Linux or Windows CE Application images 64MB or 128MB 64MB for TITAN LITE of SDRA
23. power operation The processor requires a number of power supply rails All voltage levels are generated on board from the 5V power input The TITAN uses a specialised power management IC to support Intel SpeedStep technology The PXA270 processor is a low power device and does not require a heat sink for temperatures up to 70 C 85 C for the industrial variant 18 Issue D 3 EUROTECH Detailed hardware description PXA270 GPIO pin assignments The table below summarizes the use of the 118 PXA270 GPIO pins their direction alternate function and active level For embedded Linux the GPIO pins are setup by Redboot For Windows CE D they are setup by the OS and not by the boot loader For details of pin states during reset see the Pin Usage table in the PXA27x Processor Family Electrical Mechanical and Thermal Specification Key AF Alternate function Dir Pin direction Active X Function active level or edge Sleep Pin state during sleep mode Hi Z states are set to 1 during sleep Last states are whatever the last state was before going to sleep Signal name Dir Active Function source See section G2 0 0 AC97IRQ Input _f AC97 interrupt Input VY Audio 1 0 DS WAKEUP Input Deep sleep wakeup Input v 2 0 SYS EN Output High Enable 3 3V supplies 1 3 0 Output NA Control PXA270 supplies 1 4 0 PWR SDA Bidir Input Power and power 5 0 PWR CAPO Power management
24. registered trademark of Linus Torvalds RedBoot and Red Hat is a registered trademark of Red Hat Inc Bluetooth is a registered trademark of Bluetooth SIG Inc All other trademarks recognised REVISION HISTORY Issue no Date Comments A VO Issue 2 30 August 2007 Draft release of manual for TITAN and TITAN Lite B VO Issue 2 1 October 2007 Moved ZEUS FPIF and Ethernet Breakout details to Appendices and added details of ZEUS FPIF CRT Eurotech rebranding C V1 Issue 1 16 April 2008 Release for TITAN V111 D V1 Issue 1 274 April 2009 Minor updates and new branding 2009 Eurotech All rights reserved For contact details see page 101 eiat tere Contents Contents MOGUCU Bm 5 THAN TAa aC e E E EE EE EERS 6 THANT AUGS S f EAN S RON 10 Product handling and environmental compliance 11 SS OS 12 TT 13 RPV WI TTAN 13 Detailed hardware description 2000010 0 15 THAN Block diagram MN 15 THAN adar eS MAD cara E EE EEE 16 Translations made by the 17 PAAZ O TL 17 270 GPIO pin 19 Interrupt assignments 24 anre
25. the operating voltage and frequency peripherals enabled external switching activity and external loading and other factors The tables below contain the power consumption information at room temperature for several operating modes active idle and low power modes For active power consumption data no PXA270 peripherals are enabled except for Conditions VCC_SRAM 1 1V VCC_PLL 1 3V VCC MEM VCC BB VCC_USIM VCC_LCD 1 8V VCC_1O VCC_BATT VCC_USB 3 0V Active power consumption Idle power consumption System bus frequency typ typ Frequency Issue D 520 MHz 208 MHz 747 mW 222 mW VCC_CORE 1 45V 416 MHz 208 MHz 570 mW 186 mW VCC_CORE 1 35V 312 MHz 208 MHz 390 mW 154 mW VCC_CORE 1 25V 312 MHz 104 MHz 375 mW 109 mW VCC_CORE 1 1V 208 MHz 208 MHz 279 mW 129 mW VCC_CORE 1 15V 104 MHz 104 MHz 116 mW 64 mW VCC_CORE 0 9V 13 MHz CCCR CPDIS 1 44 2 mW VCC_CORE 0 85V 57 TITAN user manual 3 EUROTECH Power consumption Conditions PXA270 low power modes typ Vae Eun 13MHz idle mode LCD on 15 4mW VCC CORE VCC SRAM VCC PLL 0 85V 13MHz idle mode LCD 8 5mW VCC CORE VCC SRAM VCC PLL 0 85V Deep sleep mode 0 1mW VCC CORE SRAM PLL 0V Sleep mode 0 16mW VCC CORE SRAM OV Standby mode 1 2mW VCC CORE VCC SRAM VCC PLL 3 0V Wake up sources The PXA270 offers two sleep modes e Sleep mode offers lower power consumption by switching of
26. 0 003mW Standby 1 at 3 3V Total 2774 6mW 135 6mW External peripheral devices include two USB devices SW max add on PC 104 cards SW max LCD and inverter 4W max SDIO 350mW max and Quick Capture camera 50mW max Issue D 59 TITAN user manual 3 EUROTECH The table below gives examples of the power drawn by specific external peripheral devices Device Part number Condition Power mW Socket WiFi 802 11b WL6200 480 Idle listening 50 SDIO us Transmitting 925 64MB FlashDio USB FDU100A Inserted no access 375 memory stick Reading consistently 605 NEC 5 5 LCD NL3224BC35 20 LCD and backlight on 3250 inverter 55PW131 LCD on and backlight off 825 VGA CMOS sensor Dialog DA3520 Active 50 module COMs power management 60 GPIO 20 on the PXA270 can be used to power down the RS232 transceivers on COM1 2 3 and 4 The following table shows the effect of GPIO 20 on the RS232 transceivers RS232_SHDN GPIO 20 Operation status Transmitters Receivers 0 Normal operation Active Active 1 Shutdown High Z High Z Shut can reduce the consumption of the RS232 transceivers down to near zero 3yuW and COM5 are generated from an external Exar XR16C2850 DUART This device supports a sleep mode with an auto wake up By enabling this feature the DUART enters sleep mode when there are no interrupts pending The device resumes normal operation when any of the following occur e Receive data start
27. 1 3V3 12 MMC CD 70 Issue D G EUROTECH Connectors LEDs and jumpers J8 LVDS connector Connector Hirose DF13 20DP 1 25V 55 20 way 1 27mm 0 05 double row straight pin header LVDS mating connector Hirose DF13 20DS 1 25C LVDS mating connector crimps Hirose DF13 2630SCFA Eurotech recommended cable Amphenol 165 2899 945 Signal name Signal name 1 3V3 2 3V3 3 GND 4 GND 5 LVDS_DO 6 LVDS_DO 7 GND 8 LVDS_D1 20 2 9 LVDS_D1 10 GND wi NENNEN Z 11 LVDS_D2 12 LVDS D2 19 1 13 14 LVDS CLK 15 LVDS 16 GND 17 NC 18 NC 19 GND 20 MSL J9 JTAG connector Connector Oupiin 2015 2X5GDB SN 10 way 2 54mm 0 1 x 2 54mm 0 1 dual row header Mating connector FCI 71600 010LF Signal name Signal name 1 3V3 2 NC 1 2 3 GND 4 nTRST ap 5 6 TDI 7 8 TMS 9 n n t0 9 TCLK 10 SRST Issue D T1 TITAN user manual 3 EUROTECH J10 USB connector y Connector Oupiin 2015 2X5GDB SN 10 way 2 54mm 0 1 x 2 54mm 0 1 dual row header Mating connector FCI 71600 010LF Signal name Signal name 1 VBUS 1 2 VBUS 2 2 10 3 DATA 1 4 DATA 2 5 DATA 1 6 DATA 2 BR GND 8 GND 1 9 9 SHIELD 10 SHIELD Do NOT attempt to power the TITAN using the VBUS 1 or VBUS 2 pins VBUS 1 and VBUS 2 are isolated 5V supplies switched under hardware control from VCC_PER ALWAYS use the U
28. 26 2 CIF PCLK Input Camera interface pixel clock Input 25 1 CIF LV Input NA Input 0 LVDS falling edge strobe G2 27 0 LVDS_FES Output Low 1 LVDS interface 1 LVDS rising edge strobe default 28 1 AC97 BITCLK Input AC97 BITCLK Input G2 29 1 AC97 DIN Input AC97 SDATA_INO Input Audio G2 30 2 AC97 DOUT Output NA AC97 SDATA OUT 0 G2 31 2 AC97 SYNC Output SYNC 0 32 2 MMCLK Output NA SDIO clock 0 G2 33 2 SRAM_CS5 Output Low Chip select 5 1 J Memory 34 1 RXD1 Input COMI receive data Input Serial COMs ports 35 0 USER LINKB Input Userconfigurable Input v External interrupts 20 Issue D 3 EUROTECH 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 5 58 59 60 61 62 63 64 65 66 67 N N N O OJIN N N N N MO N MN NM MN Signal name DCD1 DSR1 RI1 TXD1 DTR1 RTS1 RXD2 TXD2 CTS2 RTS2 RXD3 TXD3 CB_PWE CB_PIOR CB_PIOW MMC_WP MMC_CD CB 2 DUART_ CLK8 16 CB_PWAIT CB PIOIS16 LCD DO LCD D1 LCD D2 LCD D3 LCD D4 LCD D5 LCD D6 LCD D7 LCD D8 LCD D9 Input Input Input Output Output Output Input Output Input Output Input Output Output Output Output Output Input Input Output Output Input Input Output Output Output Output Output Output Output Output Output Output Act
29. 4 This jumper can be used to recover a damaged software image Description Fetch working image from BOOTP server and execute Normal software run mode factory default Please contact Eurotech for details Contact details are provided in Eurotech Group Worldwide Presence page 101 Reset LK8 on JP5 A momentary switch push to make may be connected to LK1 When pressed the board goes into a full hardware reset When the switch is released open circuit the board reboots 80 Issue D 3 Connectors LEDs and jumpers JTAG enable jumper LK9 on JP6 This jumper is used to enable debug of PXA270 using the JTAG interface Description JTAG enable Normal operation factory default Only insert jumper LK9 for JTAG access to the PXA270 LK9 MUST be removed before putting the TITAN into deep sleep Issue D 81 TITAN user manual 3 EUROTECH Appendix A Board version issue 82 Where it is possible to see the TITAN the board version and issue are indicated on the top side in the upper right hand corner and on the bottom side in the lower left corner as shown below TITAN version issue on top side TITAN version issue on bottom side CHARS TS J703 V012 AN METTE TIC If it is not possible to physically look at the TITAN the board version and issue can be read from the CPLD board version issue register BV REG at the address 0x11000000 The board
30. 6 0 PWR_CAP1 Power To achieve low power 7 0 PWR_CAP2 Power during sleep 8 0 PWR CAP3 Power COM10R4 __ 9 0 WAKEUP Input COM1 to activity Input Serial COMs ports G2 10 0 IRQ Input _f COM 4 interrupt Input CUNE ports G2 11 COM5IRQ Input _f COMB5 interrupt Input 4 12 0 OVERTEMP Input qo Temperature sensor over ipu temperature IRQ 13 0 USER LINKA Input User configurable Input v External interrupts 14 0 ETH Input EM Ethernet interrupt Input v Ethernet 15 2 ETH 51 Output Low Chip select 1 1 Issue D 19 TITAN user manual 3 EUROTECH GPIO No AF Signal Active Function Sleep source See section ah Backlight on off or variable Flat panel displa Flat pane display 16 2 PWMO Output inverter brightness if PWM 0 SE datasheet G2 17 0 PC104 IRQ Input OR ofPC 104interrupts Input v 104 interface 18 0 SHDNZ Output Low Shutdown clocks 0 Flat panel display 19 0 BKLEN Output High LCD backlight enable 0 sano 20 0 RS232_SHDN Output Low Shutdown COM 1 2 3 amp 4 0 Serial COMs ports 0 LVDS power down 21 0 LVDS_EN Output High default 0 LVDS interface 1 LVDS enable USB channel 2 power USB enable j G2 22 0 USB_PWE2 Output High 23 1 CIF MCLK Output NA 24 1 CIF FV inet Quick Capture sync vertical camera interface Camera interface line sync horizontal
31. M for system memory e Static RAM 256KB of SRAM internal to PXA270 256KB of SRAM external to PXA270 battery backed 128 bytes of configuration EEPROM on the C bus FLASH memory silicon disk The TITAN supports 16MB TITAN LITE only 32MB or 64MB of AMD Mirrorbit Flash memory for the boot loader OS and application images The Flash memory is arranged as 64Mbit x 16 bits 16MB device 128Mbit x 16 bits 32MB device or 256Mbit x 16 bits 64MB device respectively The FLASH memory array is divided into equally sized symmetrical blocks that are 64 Kword in size 128KB sectors A 128Mbit device contains 128 blocks a 256Mbit device contains 256 blocks and a 512Mbit device contains 512 blocks Whenever the FLASH memory is accessed the FLASH access LED is illuminated SDRAM interface Issue D There are two standard memory configurations supported by the TITAN 64MB or 128MB of SDRAM located in bank 0 The 128MB option is not available for the standard TITAN Lite variants The SDRAM is configured as 16MB x 32 bits 64MB or 32MB x 32 bits 128MB by 2 devices each with 4 internal banks of 4MB or 8MB x 16 bits These are surface mount devices soldered to the board and cannot be upgraded The size of memory fitted to the board is detected by software to configure the SDRAM controller accordingly The SDRAM memory controller is set to run at 104MHz 27 TITAN user manual 3 EUROTECH Static RAM The PXA270 pr
32. RAM Static Random Access Memory STN Super Twisted Nematic technology of passive matrix liquid crystal STUART Standard Universal Asynchronous Receiver Transmitter TFT Thin Film Transistor a type of LCD flat panel display screen TX Transmit UART Universal Asynchronous Receiver Transmitter USB Universal Serial Bus VGA Video Graphics Adapter display resolution 640 x 480 pixels TITAN ICE TITAN Industrial Compact Enclosure Issue D 99 TITAN user manual 3 EUROTECH Appendix I ROHS 6 Compliance Materials Declaration Form 3 EUROTECH Confirmation of Environmental Compatibility for Supplied Products Substance Maximum concentration Lead 0 1 by weight in homogeneous materials Mercury 0 1 by weight in homogeneous materials Hexavalent chromium 0 1 by weight in homogeneous materials Polybrominated biphenyls PBBs 0 1 by weight in homogeneous materials Polybrominated diphenyl ethers PBDEs 0 1 by weight in homogeneous materials Cadmium 0 01 by weight in homogeneous materials The products covered by this certificate include Product Name Eurotech Part Number TITAN 520 Eurotech has based its material content knowledge on combination of information provided by third parties and auditing our suppliers and sub contractor s operational activities and arrangements This information is archived within the associated Technical Construction File Eurotech has taken reasonable steps to provide r
33. S FPIF board provides a low pass filter for this function see page 88 Contact Eurotech see Eurotech Group Worldwide Presence page 101 for purchasing information for the ZEUS FPIF STN BIAS voltage The TITAN can provide a negative and a positive bias voltage for STN type displays The negative and positive bias voltages are set to 22V and 22V respectively Pin connections for these can be found in section J4 LCD connector page 68 BIAS EN GPIO 82 Selected backlight function 0 NEGBIAS amp POSBIAS power off default 1 NEGBIAS amp POSBIAS power on Please contact Eurotech for details of other bias voltages Contact details are provided in Eurotech Group Worldwide Presence page 101 A Do not exceed a 20mA load current 40 Issue D G EUROTECH Detailed hardware description LVDS interface There is an optional Low Voltage Differential Signalling LVDS interface available on the D TITAN LVDS combines high data rates with low power consumption The benefits of LVDS include low voltage power supply compatibility low noise generation high noise rejection and robust transmission signals The National Semiconductor transmitter DS90C363 is used to convert 16 bits of LCD data signals into three LVDS data streams A phase locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link The LVDS signals are routed to the connector J8 For connector details see the section J8 LVDS c
34. SB client cable provided with the development kit This cable does not provide power down the cable and avoids reverse powering the TITAN from a USB host when the TITAN has no power on the VCC input on J15 pin 1 Reverse powering the TITAN from the VBUSn pins can make the TITAN operate erratically and may cause serious damage to the TITAN J11 10 100BaseTX Ethernet connector Connector Oupiin 2015 2X4GDB SN 8 way 2 54mm 0 1 x 2 54mm 0 1 dual row header Mating connector FCI 71600 008LF Signal name Signal name 1 TX 2 TX DEED 5 6 RX 2 7 8 LANGND 72 Issue D eiat tere Connectors LEDs and jumpers J12 Ethernet status LEDs connector Connector Neltron 2417SJ 06 PHD 6 way 2mm 0 079 x 2mm 0 079 pin housing Mating connector Neltron 2418HJ 06 PHD Mating connector crimps x4 Neltron 2418TJ PHD Signal name Signal name 1 3V3 2 LINK 3 3V3 4 SPEED 5 3V3 6 NC 6 2 Issue D 73 TITAN user manual 3 EUROTECH J13 amp J14 PC 104 connectors Connectors e Astron 25 1201 232 2G R 64 way 2 54mm 0 1 x 2 54mm 0 1 stackthrough PC 104 compatible connector row A amp B e Astron 25 1201 220 2G R 40 way 2 54mm 0 1 x 2 54mm 0 1 stackthrough PC 104 compatible connector row C amp D 1 GND 2 D7 R
35. STDRV 3 D6 VCC_PER 5V 4 D5 IRQ9 5 D4 NC 6 D3 NU DRQ2 7 D2 NC 8 D1 NC 0 GND GND 9 DO 12V 1 MEMCS16 SBHE 10 IOCHRDY KEY 2 IOCS16 LA23 11 AEN SMEMW 3 IRQ10 LA22 12 A19 SMEMR 4 IRQ11 LA21 13 A18 5 IRQ12 LA20 14 17 6 IRQ15 LA19 15 A16 NU DACK3 7 IRQ14 LA18 16 A15 NU DRQ3 8 NU DACKO LA17 17 A14 NU DACK1 9 NU DRQO MEMR 18 A13 NU DRQ1 10 DACK5 MEMW 19 A12 NU REFSH 11 NU DRQ5 D8 20 A11 8MHz CLK 12 NU DACK6 D9 21 10 IRQ7 13 NU DRQ6 D10 22 AQ IRQ6 14 NU DACK7 D11 23 A8 IRQ5 15 NU DRQ7 D12 24 A7 IRQ4 16 VCC_PER 5V D13 25 A6 IRQ3 17 NC Master D14 26 A5 NU DACK2 18 GND D15 27 A4 NU TC 19 GND KEY 28 A3 BALE 29 A2 VCC_PER 5V 30 1 OSC 31 AO GND 32 GND GND Do NOT attempt to power the TITAN using the VCC_PER pins VCC_PER is an isolated A 5V supply switched under hardware control from the VCC input on J15 pin 1 ALWAYS provide 5V to VCC on J15 pin 1 74 Issue D G EUROTECH Connectors LEDs and jumpers J15 Power connector Connector Molex 22 05 7058 5 way 2 54mm 0 1 Pitch KK header right angle friction lock 7395 series connector Mating connector Molex 22 01 2055 5 way 2 54mm 0 1 Pitch KK crimp terminal housing 2695 series connector Pin Signal name 1 VCC 5V 2 GND 3 VBAT_E 4 12V 5 Reset VBAT_E provides the facility to fit an external battery for the backup supply of the external 256KByte static RAM and RTC and
36. SYNC 38 GND 39 PCLK CLOCK 40 GND Issue D 89 TITAN user manual 3 EUROTECH J2 Generic LCD connector Connector Oupiin 3012 34GSB SN 34 way 2 54mm 0 1 x 2 54mm 0 1 straight boxed header Mating connector Fujitsu FCN 723 B034 2 Mating connector crimps Fujitsu FCN 723J AU Q as it is possible to connect a crimp type connector to PL2 a wide range of LCD displays can be connected with a custom cable Signal name i Signal name 1 GND 2 FPD 0 3 FPD 1 4 FPD 2 34 33 5 GND 6 FPD 3 7 FPD 4 8 FPD 5 9 FPD 6 10 GND LE 11 FPD7 12 FPD8 13 FPD9 14 10 15 GND 16 GND 17 FPD 11 18 12 19 FPD 13 20 GND 21 FPD 14 22 FPD 15 7 23 GND 24 PCLK CLOCK 25 26 LCDSAFE 27 LCDSAFE 28 LCLK HSYNC 29 FCLK VSYNC 30 GND 31 BKLSAFE 32 BIAS DE 33 NC 34 BKLEN 90 Issue D G EUROTECH Appendix E ZEUS FPIF details J3 Direct connection to a NL3224BC35 20 5 5inch 320x240 TFT display Connector Oupiin 2345 33TD2 SN Mating cable Eunsung 0 5x33x190xAx0 035x0 3x5x5x10x10 Signal name Signal name 1 GND 18 FPD10 2 PCLK 19 GND 3 LCLK HSYNC 20 GND 4 FCLK VSYNC 21 FPDO 5 GND 22 FPD1 6 GND 23 FPD2 7 FPD 11 24 FPD3 8 FPD 12 25 FPD4 9 FPD 13 26 GND 10 FPD 14 27 LBIAS 11 FPD 15 28 LCDSAFE 12 GND 29 LCDSAFE 13 FPD5 30 14 FPD6 31
37. Serial COMs ports Flat panel display 0 support 1 Serial COMs ports 1 1 0 Flat panel 0 display support Input USB 0 Issue D 3 EUROTECH Detailed hardware description GPIO No AF Signal name Active Function source See section 90 3 CIF DD4 91 0 RECOVER 92 1 MMDATO 93 2 CIF DD6 94 2 CIF DD5 G2 95 1 AC97_RST 96 0 WD SETO 97 0 WD SET N N 98 2 CIF DDO 99 0 WD SET2 100 1 CTS1 101 0 LCDEN 102 0 WD WDI 103 1 CIF DD3 104 1 CIF DD2 105 1 CIF DD1 106 1 CIF DD9 107 1 CIF DD8 108 1 CIF DD7 109 1 MMDAT1 110 1 MMDAT2 111 1 MMDAT3 112 1 MMCMD 2 113 0 USER LINKC 114 0 USB OC2 e 115 0 SEL TERM 116 0 GPIO IRQ SCL SDA Issue D Input Input Bidir Input Input Output Output Output Input Output Input Output Output Input Input Input Input Input Input Bidir Bidir Bidir Bidir Input Input Output Input Output Bidir NA NA NA NA Low NA NA NA NA High Camera interface data 4 Factory SW Recovery SDIO data 0 Camera interface data 6 Camera interface data 5 97 reset Watchdog timeout Watchdog timeout Camera interface data O Watchdog timeout COM 1 clear to send LCD logic supply enable Watchdog input Camera interface data 3 Camera interface data 2 Camera interface data 1 Camera interface data 9 Camera interface data 8 Camera interface data 7 SDIO data 1
38. UROTECH Finland tel 358 9 477 888 0 fax 358 9 477 888 99 e mail sales fi eurotech com e mail support fi eurotech com www eurotech com ASIA Japan ADVANET tel 81 86 245 2861 fax 81 86 245 2860 e mail sales advanet co jp www advanet co jp China VANTRON tel 86 28 85 12 39 30 fax 86 28 85 12 39 35 e mail sales vantrontech com cn e mail support cn eurotech com www vantrontech com cn 3 EUROTECH www eurotech com
39. USER MANUAL TITAN 270 RISC based 104 Single Board Computer Rev 4 0 April 2009 ETH_TITAN_USM DIGITAL TECHNOLOGIES FOR A BETTER WORLD www eurotech com EU ROTECH 3 EUROTECH DISCLAIMER The information in this document is subject to change without notice and should not be construed as a commitment by any Eurotech company While reasonable precautions have been taken Eurotech assumes no responsibility for any error that may appear in this document WARRANTY This product is supplied with a 3 year limited warranty The product warranty covers failure of any Eurotech manufactured product caused by manufacturing defects The warranty on all third party manufactured products utilised by Eurotech is limited to 1 year Eurotech will make all reasonable effort to repair the product or replace it with an identical variant Eurotech reserves the right to replace the returned product with an alternative variant or an equivalent fit form and functional product Delivery charges will apply to all returned products Please check www eurotech com for information about Product Return Forms TRADEMARKS ARM and StrongARM are registered trademarks of ARM Ltd Intel and XScale are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries Windows CE is a trademark of the Microsoft Corporation CompactFlash is the registered trademark of SanDisk Corp Linux is a
40. User External GPIO Jr d pg hd tt Active Issue D 3 EUROTECH Detailed hardware description Real time clock Issue D The TITAN uses an external real time clock RTC Intersil ISL1208 to store the date and time and provide power management events The RTC is connected to the bus of the 270 processor and is accessible through bus address Ox6F The RTC is battery backed for the TITAN but is not battery backed for the TITAN Lite The accuracy of the internal RTC is based on the operation of the 32 768KHz watch crystal Its calibration tolerance is 20 which provides an accuracy of 1 minute per month when the board is operated at an ambient temperature of 25 C 77 F When the board is operated outside this temperature the accuracy may be degraded by 0 035ppm C 10 typical The watch crystal s accuracy will age by max in the first year then 1 max the year after and logarithmically decreasing in subsequent years The Intersil ISL1208 RTC provides the following basic functions e Real time clock calendar Tracks time in hours minutes and seconds Day of the week day month and year e Single alarm Settable to the second minute hour day of the week day or month Single event or pulse interrupt mode 2 bytes battery backed user SRAM e C interface PXA270 has an internal real time clock which doesn t keep time after hardware reset and should
41. ace PC 104 8 bit memory write access cycle VALID VALID A lt 0 23 gt IOCHRDY 332 5 PC 104 16 bit memory read access cycle VALID VALID __ 163ns Oons 7 241ns a 187ns 340ns ii lt 0 23 gt IOCHRDY Issue D 32 3 EUROTECH Detailed hardware description PC 104 16 bit memory write access cycles SMEMW 0 44s 61ns lt 167ns Gans lt P 183ns 336ns 153ns 104 add on board dependant Issue D 33 TITAN user manual 3 EUROTECH PC 104 interrupts 2 34 The PC 104 interrupts are combined together in the TITAN hardware When an interrupt is received on the PC 104 interface the hardware generates an interrupt on pin GPIO 17 active high of the PXA270 processor The PC 104 interrupting source can be identified by reading the PC104 IRQ registers I1 REG and 12 REG located at addresses 0x12800000 and 0x01800000 respectively The registers indicate the status of the interrupt lines at the time the register is read The relevant interrupt has its corresponding bit set to 1 The PXA270 is not designed to interface to 8 bit peripherals so only the least significant byte from the word contains the data PC 104 interrupt register 1 I REG Byte lane Most significant byte Least significant byte ress orto ET Gok PC 104 interrupt register 2 I2 REG not available under Windows Byte lane Most
42. ailable in the PXA270 processor wireless Intel SpeedStep technology dynamically adjusts the power and performance of the processor based on CPU demand This can result in a significant decrease in power consumption In addition to the capabilities of Intel Dynamic Voltage Management the Intel XScale micro architecture of the PXA27x family incorporates three new low power states These are deep idle standby and deep sleep It is possible to change both voltage and frequency on the fly by intelligently switching the processor into the various low power modes This saves additional power while still providing the necessary performance to run rich applications Wireless Intel SpeedStep technology includes the following features e Five reset sources power on hardware watchdog GPIO and exit from sleep and deep sleep modes sleep exit e Multiple clock speed controls to adjust frequency including frequency change turbo mode half turbo mode fast bus mode memory clock 13M mode A bit mode and 97 Switchable clock source e Functional unit clock gating e Programmable frequency change capability One normal operation power mode run mode and five low power modes to control power consumption idle deep idle standby sleep and deep sleep modes e Programmable l C based external regulator interface to support changing dynamic core voltage frequency change and power mode coupling 270 power consumption depends on
43. ame header since most of the camera image sensors require an ke control interface For connector details see the section J2 Camera interface connecior page 67 51 TITAN user manual eiat tere General purpose A Maxim MAX7313 lC I O expander provides sixteen general purpose input output lines on header J3 Each I O port can be individually configured as either an open drain current sinking output rated at 50mA with a 10K pull up to 5V VCC PER or a logic input with transition detection The MAX7313 supports hot insertion and all inputs are 5V tolerant The MAX7313 can configure outputs for PWM current drive The MAX7313 includes an internal oscillator nominally 32kHz to generate PWM timing for LED intensity control PWM intensity control can be enabled on an output by output basis allowing the MAX7313 to provide any mix of PWM LED drives and glitch free logic outputs PWM can be disabled entirely in which case all output ports are static and the MAX7313 operating current is the lowest because the internal oscillator is turned off The I O Expander is addressable at l C serial bus address 0x20 and is accessed in fast mode operation at 400kbps On power up all control registers are reset and the MAX7313 enters standby mode Power up status makes all ports into inputs so the state of all 17 ports PO P16 is logic high through 10K pull up to 5V See the section J3 GPIO connector page 67 for connector pinout and ma
44. bit e Change of state on CTS DSR CD RI e Data is being loaded into transmit FIFO If the device is awoke by one of the above conditions it returns to the sleep mode automatically after the condition has cleared In sleep mode the XR16C2850 consumes 0 1mW Please see the XR16C 2850 datasheet on the Development Kit CD for information on enabling the sleep mode 115 on the PXA270 is used to connect or disconnect the 1200 termination resistors on COMB SEL_TERM GPIO 115 COM5 termination resistors 120Q 0 Disconnected 1 Connected default Issue D 3 EUROTECH Power and power management Ethernet power management The Ethernet controller Davicom DM9000A incorporates a number of features to maintain the lowest power possible The device can be put into a power reduced mode by setting the PHY control register bit 16 4 In power reduced mode the device transmits the fast link pulses with minimum power consumption It also monitors the media for the presence of a valid signal and if detected the device automatically wakes up and resumes normal operation The power consumption in power reduced mode without cable is 31mA 102 3mW The PHY can be put into a sleep mode by setting the PHY control register bit 16 1 which powers down all the circuits except the oscillator and clock generator circuit The PHY can be put into a power down mode by setting the PHY control register bit 0 11 which disables all trans
45. cription 16 bit 16 bit TT 16 bit ot 16 bit 16 bit 16 bit 16 bit 16 bit 8 16 bit 8 16 bit 32 bit 32 bit 32 bit 32 bit 32 bit 32 bit 32 bit 32 bit 32 bit 32 bit 32 bit FLASH memory Silicon disk Ethernet controller Reserved COMA Reserved COM5 Reserved BV Board version issue Reserved I2 REG PC104 IRQ status Reserved CV REG CPLD version issue Reserved 1 REG PC104 IRQ status Reserved C REG PC104 reset Reserved SRAM Reserved PC 104 I O space Reserved PC 104 memory space Reserved PXA270 peripherals LCD control registers Memory controller registers USB host registers Capture Interface registers Reserved Internal memory control Internal SRAM bank 0 Internal SRAM bank 1 Internal SRAM bank 2 Internal SRAM bank 3 Reserved SDRAM Reserved Details of the internal registers are in the Intel Developer s Manual on the Development Kit CD 16 Issue D 3 EUROTECH Detailed hardware description Translations made by the MMU For details of translations made by the MMU by Redboot for embedded Linux please refer to the TITAN Embedded Linux Quickstart Manual For details of translations made by the MMU for Windows please check the Windows CE documentation for information about memory mapping One source of this information is on the MSDN web site www msdn microsoft com under Windows CE Memory Architecture PXA270 processor
46. ction TITAN features Microprocessor PXA270 312MHz TITAN Lite only 416 520MHz XScale processor 520MHz as standard option Cache e 32K data cache 32K instruction cache 2K mini data cache System memory e Fixed on board memory 64 128MB SDRAM 32 bit wide SDRAM data bus Silicon disk e Fixed on board memory 16MB Flash TITAN Lite only or 32 64MB Flash SRAM 256 of SRAM battery backed on board Serial ports e Five UART fast serial ports 16550 compatible 921 6Kbaud One RS422 485 interface software selectable Four RS232 interfaces e Two channels with 128 byte Tx Rx FIFO 40 boxed header USB support o wo USB 1 1 host controller ports supporting 12Mbps and 1 5Mbps speeds One USB 1 1 client controller port supporting 12Mbps and 1 5Mbps speeds software selectable on Host 2 Ge e Short circuit protection with 500mA current limit protection 10 header Network support e IEEE 802 3u 10 100 Base T Ethernet controller e One 10 100BaseTX NIC port on 8 pin header e Factory build option for external Power over Ethernet PoE Expansion interfaces e SDIO socket to support MMC SD SDIO cards e PC 104 expansion bus 8 16 bit ISA bus compatible interface Issue D 7 TITAN user manual 3 EUROTECH Date time support e Real time clock battery backed on board external to PXA270 1 minute month accuracy Video e 18 bit fla
47. e LVDS interface provides useful when displays need to be located more than 300mm 12 from the TITAN The following tables provide a cross reference between the flat panel data signals and their function when configured for different displays Issue D 3 EUROTECH Detailed hardware description TFT panel data bit mapping to the TITAN The PXA270 can directly interface to 18 bit displays but from a performance point of view it is better to use 16 bits only 18 bit operation requires twice the bandwidth of 16 bit operation The following table shows TFT panel data bit mapping to the TITAN Panel data bus bit 18 bit TFT 12 bit TFT 9 bit TFT FPD 15 R5 R3 R2 FPD 14 R4 R2 R1 FPD 13 R3 R1 RO FPD 12 R2 RO FPD 11 R1 GND RO FPD 10 G5 G3 G2 FPD 9 G4 G2 G1 FPD 8 G3 G1 GO FPD 7 G2 GO FPD 6 G1 FPD 5 GO FPD 4 5 B3 B2 FPD 3 B4 B2 B1 FPD 2 B3 B1 BO FPD 1 B2 BO FPD 0 B1 GND BO Issue D 37 TITAN user manual 3 EUROTECH STN panel data bit mapping to the TITAN Panel data bus bit Dual scan colour STN Single scan colour STN Dual scan mono STN FPD 15 DL7 G FPD 14 DL6 R FPD 13 DL5 B FPD 12 DL4 G FPD 11 DL3 R FPD 10 DL2 B FPD 9 DL1 G FPD 8 DLO R 7 DU7 G D7 G DL3 FPD 6 DU6 R D6 R DL2 FPD 5 DU5 B D5 B DL1 FPD 4 DU4 G D4 G DLO FPD 3 DU3 R D3 R DU3 FPD 2 DU2 B D2 B DU2 FPD 1 DU1 G D1 G DU1 FPDO DUO R DO R DUO T
48. e and avoids reverse powering the TITAN from a USB host when the TITAN has no power on the VCC input on J15 pin 1 Reverse powering the TITAN from the VBUSn pins can make the TITAN operate erratically and may cause serious damage to the TITAN 44 Issue D 3 EUROTECH Detailed hardware description Ethernet Issue D The TITAN SBC provides a single 10 100 BaseTX interface with MAC and complies with both the IEEE802 3u 10 100 BaseTX and the IEEE 802 3x full duplex flow control specifications A single Davicom DM9000A Ethernet controller is used to implement the Ethernet interface on the TITAN The 9000 device provides an embedded PHY and MAC and connects to the 10 100 BaseT X magnetics The DM9000A also supports the AUTO MDIX feature Configuration data and MAC information are stored in an external serial EEPROM 93LC46 The DM9000A device is connected to the PXA270 data bus 16 bit and is memory mapped Connection to the TITAN Ethernet port is via header J11 See J11 10 100BaseTX Ethernet connector page 72 for pin assignment and connector details A second header J12 provides the speed and link status LED signals See J12 Ethernet status LEDs connector page 73 for pin assignment and connector details The output lines sink current when switched on therefore the anode of each LED should be connected to pins 1 and 3 of J12 and the cathode to the appropriate status line The link LED illuminates when a 10 or 100base T
49. ected to a PXA270 MMC SD SDIO controller interface The TITAN supports hot swap changeover of the cards and notification of card insertion See the sections SDIO page 28 and J7 SDIO socket page 70 for further details Using the serial interfaces RS232 422 485 27 The five serial port interfaces on the TITAN are fully 16550 compatible Connection to the serial ports is made via a 40 way boxed header The pin assignment of this header has been arranged to enable 9 way IDC D Sub plugs to be connected directly to the cable See the sections Serial COMs ports page 46 and J1 COMS ports page 66 for further details A suitable cable for COM1 is provided as part of the Development Kit The D Sub connector on this cable is compatible with the standard 9 way connector on a desktop computer COMA RS232 and COM5 RS422 485 are not available on the standard TITAN Lite configuration Eurotech can provide custom configurations subject to a minimum order quantity for the TITAN Lite populated with this feature Please contact our Sales team to discuss your requirements see Eurotech Group Worldwide Presence page 101 Using the audio features 2 Issue D There are four audio interfaces supported on the TITAN amp out line out line in and microphone The line in line out and amp interfaces support stereo signals and the microphone provides a mono input The amplified output is suitable for driving an 8Q load with a maximum
50. educe WM9712L consumption down to near zero 1 65yW For more information about power management refer to the WM9712L datasheet contained on the Development Kit CD LVDS power management 2 If the LVDS transmitter is not required it can be placed in power down mode by applying a high level to the PXA270 GPIO 21 LVDS EN signal The power consumption in power down mode is 180uW This is shown in the following table LVDS EN GPIO 21 LVDS operation status 0 LVDS power down default 1 LVDS enable Clock generator power management 62 Two clock synthesizer ICs Cypress CY22381 can be placed in low power mode by shutting down the clock outputs when the corresponding interfaces are not used To put these into low power mode apply a low level to GPIO 18 pin on the PXA270 signal CLK_SHDN CLK_SHDN GPIO 18 Clock operation status 0 Shutdown clocks 1 Clocks running Once shutdown the following clocks are affected aMHz and 14 318MHz PC 104 clocks e 14 7456MHz DUART clock 24 5 6MHz audio clock 25MHz Ethernet PHY clock This reduces the power consumption of the clock generators down to 33W Issue D 3 EUROTECH Power and power management Temperature sensor power management The LM75A device can be set to operate in two modes normal or shut down In normal operation mode the temp to digital conversion is executed every 100ms and the Temp register is updated at the end of each conversion In shu
51. eft unconnected at the factory to conserve battery power 78 Issue D eiat Connectors LEDs and jumpers LCD supply voltage jumper LK2 on JP2 This jumper selects the supply voltage for the LCD logic supply Description Supply LCD logic with 5V Supply LCD logic with 3 3V factory default If the LCD requires a 5V supply please refer to the LCD eh datasheet to ensure that the display is compatible with 3 3V logic LVDS mode select MSL jumper LK3 on JP3 y This jumper sets the MSL signal on the Hirose LVDS connector J8 to either high or low Description 3V3 Pulled to GND factory default This jumper is only applicable if using the Hirose LVDS connector J8 Please refer to LVDS LCD datasheet for details of the signal level that is required to set it up to receive LVDS signal mapping for a National Semiconductor DS90C363 LVDS transceiver Issue D 79 TITAN user manual ya 926 User configurable jumpers A to C LK4 LK6 on JP4 These jumpers can be used to signify a configuration setting for your own application program LK4 LK6 Description Read as 0 Read as 1 factory default X USER LINKA to C LK4 5 and 6 respectively GPIO 13 35 and t J 113 respectively may be used to wake the TITAN from sleep One way of doing this is to connect a momentary push to make switch across the USER LINK and GND Recovery jumper LK7 on JP
52. ep sleep mode VBUS 1 and VBUS 2 are controlled by the PXA270 software controlled signals USB PWE 1 and USB PWE2 respectively They are switched off on power on reset sleep or deep sleep Issue D 3 EUROTECH Power and power management LCD_SAFE and BKLSAFE are controlled by the PXA270 software controlled signals LCDEN and BKLEN respectively They are switched off on power on reset sleep or deep sleep Do NOT attempt to power the TITAN using the VCC_PER VBUS 1 or VBUS 2 pins VCC_PER is an isolated 5V supply switched under hardware control from the VCC input on J15 pin 1 ALWAYS provide 5V to VCC on J15 pin 1 VBUS 1 and VBUS 2 are isolated 5V supplies switched under hardware control from VCC PER If J15 pin 4 is used to supply 12V to the PC 104 connector J13 pin B4 Do NOT exceed 700mA supply current at 70 C 158 F ambient or 600mA at 85 185 F ambient If an LCD display is used ensure the total current requirement on 3 3V does not exceed 1 4A Please check the datasheets of the devices you are using as this supply is not protected A Power management IC Issue D The Linear Technology LTC3445 is used to provide the power supply for PXA270 It is specifically designed for the PXA27x family of microprocessors The LTC3445 contains a high efficiency buck regulator VCC CORE two LDO regulators VCC_PLL VCC_SRAM a PowerPath controller and an interface The buck regulator has a 6 bit program
53. epresentative and accurate information though may not have conducted destructive testing or chemical analysis on incoming components and materials Additionally packaging used by Eurotech for its products complies with the EU Directive 2004 12 EC in that the total concentration of the heavy metals cadmium hexavalent chromium lead and mercury do not exceed 100 ppm 100 Issue D Eurotech Group Worldwide Presence 3 EUROTECH P UNITED KINGDOM FRANCE AMERICAS North America EUROTECH USA US toll free 1 800 541 2003 tel 1 301 490 4007 fax 1 301 490 4582 e mail sales us eurotech com e mail support us eurotech com www eurotech inc com PARVUS CORPORATION US toll free 1 800 483 3152 tel 1 801 483 1533 fax 1 801 483 1523 e mail sales parvus com e mail tsupport parvus com WWW parvus com JAPAN Advanet CHINA EUROPE Central amp Southern Europe EUROTECH Italy tel 39 0433 485 411 fax 39 0433 485 499 e mail sales it eurotech com e mail support it eurotech com www eurotech com Western Europe EUROTECH UK tel 44 0 1223 403410 fax 44 0 1223 410457 e mail sales uk eurotech com e mail support uk eurotech com www eurotech com EUROTECH France tel 33 04 72 89 00 90 fax 33 04 78 70 08 24 e mail sales fr eurotech com e mail support fr eurotech com www eurotech com Northern amp Eastern Europe E
54. f most internal units There is no activity inside the processor except for the units programmed to retain their state in the PSLR register the real time clock and the clocks and power manager Because internal activity has stopped recovery from sleep mode must occur through an external or internal real time clock event External wake up sources are GPIO lt n gt edge detects they are listed in the section PXA270 GPIO assignments page 19 Deep sleep mode offers the lowest power consumption by powering most units off There is no activity inside the processor except for the real time clock RTC and the clocks and power manager Because internal activity has stopped recovery from deep sleep mode must be through an external event or an RTC event In deep sleep mode all the PXA270 power supplies VCC CORE VCC SRAM VCC PLL VCC IO excluding VCC_BATT are powered off for minimized power consumption On the TITAN the main 3 3V rail supplies the power domain of the PXA270 Since the 3 3V supply is switched off in deep sleep mode all the on board peripherals are powered off and it is not possible to use external wake up sources In this situation recovery from deep sleep mode must be through an internal RTC event For more information on PXA270 power management see section 3 6 in the PXA2 x Processor Family Developer s Manual included on the Development Kit CD 58 Issue D 3 EUROTECH Power and power manage
55. functions provided by the TITAN This information may be required during development after you have started adding extra peripherals or are starting to use some of the embedded features TITAN block diagram The diagram below illustrates the functional organization of the TITAN and TITAN Lite PC 104 SBC CORE VCC_BATT SRAM v TITAN amp TITAN Lite R L LINE IN R L 7 LINE OUT MIC IN Touch Screen 5V 12V Ben 04 J13 J14 3V3 ISA JP4 POSBIAS User Config Jumpers NEGBIAS 3V3 BLKSAFE COM 1 RS232 FFUART Transceiver LCDSAFE 3V3 LCD COM2 BTUART LVDS Mode Select Jumper Oe LVDS cows COM 3 Transceiver STUART OPTIONAL 3V3 Lvps Transmitter USB B 1 1 Host USB A 1 1 Host USB A 1 1 Client 2V5 TRANS 2V5 TRANS 3V3 Transformer RESET SW Ethernet Headers J11 J12 Manual pe Quick Capture Camera umper 2 VBAT_E 3V3 IN 0 7 OUT 0 7 GvBAT Battery Disconnect Jumper Expander VBAT 3V3 VBAT Power Management I2C 12C CPU_CORE 0 85V 1 55V VCC_SRAM 1 1V VCC_PLL 1 3V 2V8_CIF 2 8V VCC BATT 3V 3 3V 3V3 RAM 3V 3 3V 3V3 3 3V LCDSAFE 3 3V 5V BLKSAFE 5V USBVCC1 5V USBVCC2 5V POSBIAS 22V NEGBIAS 22V RTC 32 768kHz PXA270 3V3 69 8MHz PC 104 62 14 318MHz PC 104 lock 62 14 7456MH
56. ge for the backlight inverter BKLEN GPIO 19 Selected backlight function 0 BKLSAFE power off default 1 BKLSAFE 5V power on The BLKEN signal is routed un buffered to connector J4 See the section J4 LCD connector page 68 for J4 pin assignment and connector details If you want to use a 12V backlight inverter then the switched 5V supply on BLKSAFE or the control signal BLKEN can be used to control an external 12V supply to the inverter 1 Issue D 39 TITAN user manual 3 EUROTECH Typically the following power up sequence is as follows please check the datasheet for the particular panel in use 1 Enable display VCC 2 Enable flat panel interface 3 Enable backlight Power down is in reverse order LCD backlight brightness control GPIO 16 of the PXA270 processor is used for backlight brightness control signal PWMO on J4 connector The control of the backlight brightness is dependant upon the type of backlight inverter used in the display Some inverters have a DIM function which uses a logic level to choose between two levels of intensity If this is the case then GPIO 16 alternative function 0 is used to set this Other inverters have an input suitable for a pulse width modulated signal or analogue voltage control In this case GPIO 16 should be configured as PWMO alternative function 2 When a PWM signal is required the PWMO signal must be passed through a low pass filter The ZEU
57. he Eurotech web site at www eurotech Itd co uK RoHS and WEEE Issue D 11 TITAN user manual Qs Noises Conventions The following symbols are used in this guide Symbol Explanation h Note information that requires your attention Caution proceeding with a course of action may damage your equipment or result in loss of data Jumper is fitted Jumper provided but not fitted Jumper is not fitted Tables With tables such as that shown below the white cells show information relevant to the subject being discussed Grey cells are not relevant in the current context Byte lane Most significant byte Least significant byte R DIS 2 Issue 3 EUROTECH Getting started Getting started Depending on the Development Kit purchased a Quickstart Manual is provided for Windows CE or embedded Linux to enable users to set up and start using the board Please read the relevant manual and follow the steps for setting up the board Once you have completed this task and have a working TITAN system you can start adding further peripherals enabling development to begin Using the TITAN This section provides a guide to setting up and using of some of the features of the TITAN For more detailed information on any aspect of the board see Detailed hardware description page 15 Using the SDIO socket The TITAN is fitted with a SDIO socket mounted on the top side of the board The socket is conn
58. he WM9712L are a stereo line in and a mono microphone input The WM9712L provides a stereo line out that can also be amplified by the National Semiconductor LM4880 250mW per channel power amplifier This amplifier is suitable for driving an 8Q load The WM9712L AC 97 CODEC may be turned off if it is not required See the section Audio power management page 62 for details Connection to the TITAN audio features is via header J6 See the table below for pin assignments and section J6 Audio connector page 69 for connector and mating connector details Frequency Function Signal levels max response Hz 10 MIC input Microphone 9 MIC voltage reference output 1Vrms 20 20k Audio ground reference 1 Line input left Line in 5 Line input right 1Vrms 20 20k 3 Audio ground reference 2 Line output left Line out 6 Line output right 1Vrms 20 20k 4 Audio ground reference 8 Amp output left 1 79V peak Amp out 11 Amp output right 1 26Vrms 20 20k 12 Audio ground reference Touchscreen controller W 42 The TITAN supports 4 wire and 5 wire resistive touchscreens using the touchscreen controller available on the Wolfson WM9712L audio CODEC The touchscreen controller supports the following functions co ordinate measurement Y co ordinate measurement e down detection with programmable sensitivity e Touch pressure measurement 4 wire touchscreen only A touchscreen can be used as a
59. he table below explains the clock signals required for passive and active type displays Active display signal Passive display signal TFT STN PCLK Clock Pixel clock LCLK Horizontal sync Line clock FCLK Vertical sync Frame clock BIAS DE Data Enable Bias 38 Issue 3 EUROTECH Detailed hardware description LCD logic and backlight power The display signals are 3 3V compatible The TITAN contains power control circuitry for the flat panel logic supply and backlight supply The flat panel logic is supplied with a switched 3 3V default or 5V supply see the section LCD supply voltage jumper LK2 on JP2 page 79 for details The backlight is supplied with a switched 5V supply for the inverter There is no on board protection for these switched supplies Care must be taken during power up down to ensure the panel is not damaged due to the input signals being incorrectly configured The PXA270 GPIO 101 pin controls the supply voltage for the LCD display LCDEN GPIO 101 Selected LCD function 0 LCDSAFE power off default 1 LCDSAFE 3 3V 5V power on The LCD supply may be changed to 5V by moving the jumper position of JP2 see section LCD supply voltage jumper LK2 on JP2 page 79 for details If the flat panel logic is powered from 5V it must be compatible with 3 3V signalling please check the LCD panel datasheet for details The PXA270 GPIO 19 pin BKLEN signal controls the supply volta
60. ide 5V to VCC on J15 pin 1 If J15 pin 4 is used to supply 12V to the PC 104 connector J13 pin B4 Do NOT exceed 700mA supply current at 70 C ambient or 600mA at 85 C ambient 29 3 EUROTECH 6 5 i lt 104 8 bit I O read access cycle VALID VALID 345ns AEN BALE IOR A lt 0 15 gt IOCHRDY PC 104 8 bit I O write access cycles A lt 0 15 gt VALID VALID MM 144ns AME CEN 180ns 341ns 19 nS IOCHRDY AEN PC 104 add on board dependant Issue D 30 c O Q u gt e 3 EUROTECH PC 104 16 bit I O read access cycle VALID VALID a gt gt 1 Igi 143ns 65ns 245ns __191 5 340ns A lt 0 15 gt IOCHRDY PC 104 16 bit I O write access cycles a ce ET _ C J LO o o co 2 lt SE C lt gt V 59 4 o v 77 o gt 2 Se lt 0m lt lt x 104 add on board dependant 31 Issue D 3 EUROTECH 6 5 i lt 104 8 bit memory read access cycle 8 bit memory read access cycles are not supported by the PXA270 PCMCIA controller for common memory sp
61. ive NA NA NA NA NA NA Low Low Low Low High Low NA Low Low NA NA NA NA NA NA NA NA NA NA Function COM data carrier detect COM data sender ready COM ring indicator COM transmit data COM data terminal ready request to send receive data transmit data clear to send request to send CONG receive data CONS transmit data Socket 0 amp 1 output enable Socket 0 amp 1 write enable Socket 0 amp 1 I O read Socket 0 amp 1 I O write SDIO write protect status SDIO card detect Socket 0 amp 1 high byte enable 0 8 x sampling double standard baud rates 1 16 x sampling standard baud rates default PWAIT 01516 LCD data bit 0 LCD data bit 1 LCD data bit 2 LCD data bit 3 LCD data bit 4 LCD data bit 5 LCD data bit 6 LCD data bit 7 LCD data bit 8 LCD data bit 9 Detailed hardware description Sleep Input Input Input Input Input Input Input Input Input 5 r O O O O O O O O O O source See section Serial COMs ports Serial COMs ports Flat panel display Su Issue D ort continued 21 TITAN user manual 9 6 22 GPIO No AF 68 2 69 2 70 2 71 2 72 2 2 73 74 2 75 2 76 2 77 2 78 0 79 1 80 2 81 0 82 0 83 0 84 0 86 2 87 2 88 1 Signal name LCD D10 LCD D11 LCD D12 LCD D13 LCD D14 LCD D15
62. logic level low 0 5mA 2 5mW amA 40mW no further pull ups at termination Output logic level high loaded and no 0 5mA 2 5mW max 8mA 40mW max further pull ups at termination Output logic level high no load OmA OmW OmW Set up the IO expander 15 signals accordingly to your application to achieve the optimum power savings during sleep If none of the IO expander 15 signals are used set them all to be inputs Configuration PROM power management When the serial l C interface is idle the 24AA01 automatically enters standby mode The power consumption in standby mode is near zero 3 3uW Issue D 63 TITAN user manual eiat tere Connectors LEDs and jumpers The following diagram shows the location of the connectors LEDs and jumpers on the TITAN J Ql IS O J2 J3 J15 JP6 45 J12 J1 J9 JP1 JP2 J13 amp J14 JP4 JP3 J10 picture above unless otherwise stated The connectors on the following pages are shown in the same orientation as the 64 Issue D eiat tere Connectors LEDs and jumpers Connectors There are 12 connectors on the TITAN for accessing external devices Connector Function Connector details in section J1 Serial ports J1 COMS ports page 66 J2 Camera J2 Camera interface connector page 67 J3 GPIO J3 GPIO connector page 67 J4 LCD panel interface J4 LCD connector page 68 o J5 Touchscreen J5 Touchscreen connecto
63. m the global TITAN board reset set the PC104 RST bit to 1 in the REG register located at the address 0x13000000 To clear the PC 104 reset write a O to the PC104 RST bit PC 104 reset register C REG Byte lane Most ms Least m X X X X X RIK X X X X X X Address 0x13000000 Issue D 35 TITAN user manual Unsupported PC 104 interface features The TITAN does not support the following PC 104 bus features e DMAis not supported Therefore AEN signal is set to a constant logical zero e Bus mastering is not supported Therefore do not connect any other master add on board to the TITAN PC 104 interface e Shared interrupts are not supported Therefore do not connect more than one add on board to the same interrupt signal line e BALE signal is set to a constant logical one as the address is valid over the entire bus cycle Only add on PC 104 boards that implement transparent latch on address lines LA17 LA23 are compatible with the TITAN implementation of BALE e he PXA270 PCMCIA memory controller does not support 8 bit memory read accesses for common memory space he PXA270 PCMCIA memory controller does not support PC 104 MEMCSZ signal so there is no support for dynamic bus sizing e PC 104 9 IRQ14 and IRQ15 are not available under Windows CE Flat panel display support 36 The PXA270 processor contains an integrated LCD display controller It is capable of su
64. mable output range of 0 85V to 1 55V The buck regulator uses either a constant frequency of 1 5MHz or a spread spectrum switching frequency Using the spread spectrum option default set to 22 496 gives a lower noise regulated output as well as low noise at the input In addition the regulated output voltage slew rate is programmable via the Power Management I C interface of the PXA270 55 TITAN user manual 3 EUROTECH Battery backup An on board non rechargeable battery CR2032 provides battery backup supply for the ISL1208 RTC and SRAM An external battery CR2032 or similar may also be fitted To use an external battery see the section J15 Power connector page 75 for connection details The table below shows the typical and maximum current load on the external battery Device load on battery Typical Maximum G2 On board SRAM 0 5 3 ISL1208 RTC with clock out off 0 4 0 95 Supply supervisor 0 5 0 5 Total 1 4 4 45 Based on the worst case figures of 4 45 current consumption a 220mAh CR2032 battery cell will backup the TITAN whilst in continuous deep sleep for gt 5 years CD The TITAN does not provide a battery charging circuit If the TITAN is to be used at operating temperature extremes please be aware that if the battery cell is fitted they are typically rated at 30 C to 60 C 56 Issue D 3 EUROTECH Power and power management Processor power management First av
65. memory e Debug and connection to In Circuit Emulator ICE Power requirements e Typically 1 5W from a single 5V supply e Power management features allow current requirements to be as low as 20mA 100mW in sleep mode and 2mA 10mW in deep sleep mode Mechanical PC 104 compatible footprint 3 8 x 3 6 96mm x 91mm www pc104 org Environmental e Operating temperature Commercial 20 C 4 F to 70 158 F for speed variants up to 520 2 Industrial 40 C 40 F to 85 C 185 F for speed variants up to 416MHz RoHS Directive Compliant 2002 95 EC Issue D 9 TITAN user manual 3 EUROTECH TITAN support products 10 The following products support the TITAN ZEUS FPIF Flat Panel Interface The ZEUS FPIF is a simple board that enables easy connection between the TITAN and a variety of LCD flat panel displays See Appendix E ZEUS FPIF details page 88 for further details ZEUS FPIF CRT a board that allows the TITAN to drive a CRT monitor or an analogue LCD flat panel Sync on green and composite sync monitors are not supported See Appendix F ZEUS FPIF CRT details page 93 for further details ETHER BREAKOUT The ETHER BREAKOUT is a simple board that converts the TITAN Ethernet 8 pin header and Ethernet LEDs 6 pin header to a standard RJ45 connector with LEDs See Appendix G Ethernet Breakout details page 96 for further details Contact Eurotech see Eurotech Group Wo
66. ment Peripheral devices power management The following table gives the estimated power consumption of on board peripherals On board Low power mode peripheral Maximum power consumption Minimum consumption Operating mode Ethernet 303 6mW 92mA at 3 3V 23 1mW Power down DM9000A 7mA at 3 3V Eth config 6 6mW 2mA at 3 3V 0 003mW Idle EEPROM 1 at 3 3V AC 97 Codec 80mW 0 001mW OFF WM9712L Boomer 250mW 50mA at 5V 0 025mW Shut down LM4880 5 at 5V SDRAM x2 1188mW 2 180mA at 3 3V 13 2 Power down 2 x 2mA at 3 3V Flash 297mW 90mA at 3 3V 0 015mW Standby at 3 3V o SRAM 49 5mW 15 at 3 3V 0 0033mW Standby 10pA at 3 3V o DUART 13 9mW 1 2mA at 3 3V 0 1mW Idle 30pA at 3 3V RS232 x 2 2 x 1 5mA at 3 3V unloaded 2uW Shut down 2 x 0 3pA at 3 3V 9 RS232 5mW 1 5mA at 3 3V 1uW Shut down unloaded at 3 3V RS485 422 188 1mW 2mA at 3 3V 0 003mW Disable unloaded 1pA at 3 3V 27 5mA x 2 at 3 3V 1200 1200 disabled enabled CPLDs 75 9mW 23mA at 3 3V 33mW Idle 10mA at 3 3V LVDS 148 5mW 45mA at 3 3V 0 17mW Power down Transceiver at 3V Clock 121 1mW 37mA at 3 3V 33pW Shut down Generators 10 at 3 3V expander 40 4mW 120pA at 3 3V 11 90W Idle 8mA at 5V 3 6pA at 3 3V RTC 0 4mW 120pA at 3 3V 0 013mW Idle ApA at 3 3V Temperature 3 3mW 1mA at 3 3V 0 012mW Shut down Sensor 3 5pA at 3 3V Config PROM 3 3mW 3mA at 3 3V
67. mit and receive functions but not the access to PHY registers The power consumption in power down mode is 21mA 69 3mW The lowest power consumption is achieved when the system clock is turned off by setting bit 0 in the SCCR register to reduce power consumption down to 7mA 23 1mW For more information about power management refer to the DM9000A datasheet the Development Kit CD USB power management 2 Issue D A USB power control switch controls the power and protects against short circuit and over current conditions on USB host ports If the USB voltage VBUSx is short circuited or more than 500mA is drawn from any VBUSx supply the switch turns off the power supply and protects the device and board automatically The VBUSx power supplies are derived from the TITAN 5V supply The following table shows the PXA270 assignments for power enable and over current signals GPIO Host 1 2 functions Active GPIO 89 USB PWE 1 High GPIO 88 USB 1 uw GPIO 22 USB PWE2 High GPIO 114 USB 2 mu 61 TITAN user manual 3 EUROTECH Audio power management 2 The audio CODEC Wolfson WM9712L supports the standard power down control register defined by AC 97 standard 26h In addition the individual sections of the chip can be powered down through register 24h Significant power savings can be achieved by disabling parts of WM9712L that are not used Shutting down all the clocks and digital and analogue sections can r
68. n 3 2 The SD controller supports one SD or SDIO card based on the standards outlined in the SD Memory Card Specification Version 1 01 and SDIO Card Specification Version 1 0 Draft 4 The MMC SD SDIO controller features e Data transfer rates up to 19 5Mbps for MMC 1 bit SD SDIO and SPI mode data transfers e Data transfer rates up to 78Mbps for 4 bit SD SDIO data transfers e Support for all valid MMC and SD SDIO protocol data transfer modes This is a hot swappable 3 3V interface controlled by the detection of a falling edge on GPIO 53 MMC CD when an SD card has been inserted and a rising edge when an SD card is removed SD card write protection is connected to the PXA270 s GPIO 52 MMC WP and card detect to GPIO 53 MMC CD A variety of SDIO cards are available such as a Camera Bluetooth GPS and 802 11b More information can be found here www sdcard org sdio index html 28 Issue D 3 EUROTECH Detailed hardware description PC 104 interface 2 The TITAN PC 104 interface is emulated from the PXA270 card interface to support 8 16 bit ISA bus style signals As the interface is an emulation the TITAN does not support some PC 104 features Please refer to the section Unsupported PC 104 interface features on page 36 for specific details Add on boards can be stacked via the PC 104 interface to enhance the functionality of the TITAN Eurotech has an extensive range of PC 104 compliant modules and these can be
69. nsumption 1 5W typical no LCD PC 104 USB SDIO devices fitted Sleep mode 20mA 100mW typical Deep sleep mode 2mA 10mW typical PC 104 compatible format 3 775 x 3 550 96mm x 91mm see www pc104 org 90 grams Operating temperature e Commercial 20 C 4 F to 70 C 158 F Industrial 40 C 40 F to 85 C 185 F Humidity 10 to 90 RH non condensing RoHS Directive 2002 95 EC compliant 85 TITAN user manual EUROTECH Appendix Mechanical diagram st Unit of measure mm 1 25 4mm o N N Q N N N 90 80 X3 87 25 557 4 80 01 J2 J3 66 55 J5 63 50 62 36 63 37 6223 0 53 98 47 37 46 52 07 JP4 J8 36 43 16 00 1 3 20 FOUR A HOLES 0 00 otro o co N Y N O N ODO 0 NH ONW N co O N O O oc v N LO N o LO O st N co ot N co NOTES 1 ALL CONNECTOR DIMENSIONS ARE TAKEN FROM PIN 1 When mounting the TITAN use only M3 metric or 4 40 US screws The mounting pad is 6 35mm 0 25 and the hole is 3 175mm 0 125 so ensure any washers fitted are smaller than the pad A Using oversized screws and washe
70. ocessor provides 256KB of internal memory mapped SRAM The SRAM o is divided into four banks each consisting of 64KB The TITAN also has a 256KB SRAM device fitted arranged as 256Kbit x 8 bits Access to the device is on 16 bit boundaries whereby the least significant byte is the SRAM data and the 8 bits of the most significant byte are don t care bits The reason for this is that the PXA270 is not designed to interface to 8 bit peripherals This arrangement is summarized in the following data bus table Most significant byte Least significant byte D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO SRAM data The SRAM is non volatile whilst the on board battery is fitted Don t care Configuration EEPROM The configuration EEPROM is interfaced directly to the PXA270 s controller It is Microchip 24AA01 1Kbit EEPROM organized as one block of 128 x 8 bit memory The configuration EEPROM is addressable at lC serial bus address 0x50 0x057 and is accessed in fast mode operation at 400kbps SDIO The SD card socket J7 is interfaced directly to the PXA270 s MMC SD SDIO controller The MMC SD SDIO controller supports multimedia card secure digital and secure digital I O communications protocols The MMC controller supports the MMC system a low cost data storage and communications system The MMC controller in the PXA270 processor is based on the standards outlined in the MultiMediaCard System Specification Versio
71. of the ZEUS FPIF are shown below i NO JP1 j J1 E t 4 b T 2008 ZEUS FPIF Vill 3732 921 ieget e The connectors on the following pages are shown in the same orientation as the picture above Connector Function JP1 TFT clock delay selection J1 TITAN LCD cable connector J2 Generic LCD connector J3 Direct connection to a NEC NL3224BC35 20 5 5inch 320x240 TFT display J4 Backlight inverter connector J5 STN bias connector JP1 TFT clock delay selection It has been found that some TFT displays require a delay on the clock If this is required fit the jumper in position A if not then fit in position B This is illustrated below B 22 88 Issue eiat Appendix ZEUS FPIF details 1 TITAN LCD cable connector Connector Oupiin 3215 40CSB SN 40 way 1 27mm 0 05 x 2 54mm 0 1 straight boxed header Mating connector Oupiin 1203 40GB SN available from Eurotech on request Pin Signal name Pin Signal name 1 BLKENZ 2 BLKSAFE 3 GPIO 16 PWMO 4 LCDSAFE Hos 5 NEGBIAS 6 BB 7 GND 8 9 1 10 FPDO 3 11 FPD3 12 FPD2 E 13 FPD5 14 FPD4 a 15 16 GND 3 3 17 FPD7 18 6 s 19 FPD9 20 8 Jm 21 FPD11 22 FPD10 23 GND 24 GND 25 FPD13 26 FPD12 27 FPD15 28 FPD14 29 NC 30 NC 31 32 33 BIAS DE 34 GND 35 FCLK VSYNC 36 GND 37 LCLK H
72. onnector page 71 The LVDS transmitter is enabled using the signal LVDS EN GPIO 21 Details are shown in the following table LVDS EN GPIO 21 Selected LVDS function 0 LVDS power down default 1 LVDS enable The LVDS transmitter can be programmed for rising edge strobe or falling edge strobe operation through a signal LVDS_FES GPIO 27 This is shown below LVDS_FES 27 Selected LVDS function 0 Falling edge strobe 1 Rising edge strobe default If the FPIF LVDS TX is to be connected directly to an LVDS display via the Hirose connector J2 then this link selects the displays LVDS Receiver input map Fitting or not fitting a jumper to JP3 sets J2 pin 20 MSL to 3 3V or GND default respectively When the LVDS interface is used connector LK3 on JP3 should be set to the correct setting for the display See section LVDS mode select MSL jumper on page 79 for details Please consult the manual of your LVDS display for which setting to use for the National Semiconductor DS90C383 LVDS Transceiver Connector J4 should be used to supply the power and brightness control for the backlight inverter when the LVDS interface is used See the section J4 LCD connector page 68 for J4 pin assignment and connector details Issue D 41 TITAN user manual 3 EUROTECH Audio The Wolfson WM9712L AC 97audio CODEC is used to support the audio features of the TITAN Audio inputs supported by t
73. or please see the section J15 Power connector page 75 On board supplies There are eleven on board supply voltages derived from the VCC 5V supply They are listed in the following table 54 Supply rail Power domains Voltage 3 EUROTECH Reset threshold VCC_BATT 270 sleep control subsystem oscillators and real time clock VCC_CORE PXA270 core and other internal units VCC PLL PXA270 phase locked loops VCC_SRAM PXA270 internal SRAM units 3V3 VCC PER VBUS 1 VBUS 2 LCD SAFE BKLSAFE 2V8 CIF PXA270 I O PXA270 internal units on board peripherals PC 104 Audio amp USB power switch Video supplies BKLSAFE LCDSAFE STN bias circuit External GPIO USB port 1 power USB port 2 power LCD logic supply LCD backlight supply CIF Camera interface 3 3V or 3 0V 0 85V 1 55V 1 3V 1 1V 3 3V 5V VCC 5V VCC_PER 5V 3 3V or 5V VCC PER 5V PER 2 8V 2 25V 92 of nominal 1 2V 1V 3 05V NA NA NA NA NA NA The TITAN shall be reset if the supplies fall below the thresholds shown in the table VCC CORE VCC PLL and VCC SRAM rails are controlled by the PXA270 hardware control signal PWR EN They are switched off when PXA270 is in sleep or deep sleep mode PER 3V3 2V8 CIF supply rails are controlled by the PXA270 hardware control signal SYS EN They are switched off when PXA270 is in de
74. power output of 250mW per channel Connections are routed to J6 see the sections Audio page 41 and J7 Audio connector page 69 for further details 13 TITAN user manual eiat tere Using the USB host The standard USB connector is a 4 way socket which provides power and data signals y to the USB peripheral The 10 way header J10 has been designed to be compatible with PC expansion brackets that support two USB sockets See the sections USB page 43 and J10 USB connector page 72 for further details Using the USB client The TITAN USB host port 2 can be configured under software to be a client and connected to a PC via a USB cable This feature is standard for the TITAN Lite The USB cable should be plugged into the 10 way header J10 See the sections USB page 43 and J10 USB connector page 72 for further details Using the Ethernet interface The Davicom DM9000A 10 100BaseTX Ethernet controller is configured by the RedBoot boot loader for embedded Linux and by Windows CE once it has booted Connection is made via connector J11 A second connector J12 provides link and speed status outputs for control LEDs See the sections Ethernet page 45 J11 10 100BaseTX Ethernet connector page 72 and J12 Ethernet status LEDs connector page 73 for further details Using the PC 104 expansion bus PC 104 modules can be used with the TITAN to add extra functionality to the system This interface supports 8 16
75. pporting both colour and monochrome single and dual scan display modules It supports active TFT and passive STN LCD displays up to 800x600 pixels The PXA270 can drive displays with a resolution up to 800x600 but as the PXA270 has a unified memory structure the bandwidth to the application decreases significantly If the application makes significant use of memory such as when video is on screen you may also experience FIFO under runs causing the frame rates to drop or display image disruption Reducing the frame rate to the slowest speed possible gives the maximum bandwidth to the application The display quality for an 800x600 resolution LCD is dependant on the compromises that can be made between the LCD refresh rate and the application The PXA270 is optimized for a 640x480 display resolution A full explanation of the graphics controller operation can be found in the ntel PXA27x Processor Family Developer s Manual included on the support CD The flat panel data and control signals are routed to J4 See the section J4 LCD connector page 68 for pin assignment and part number details The ZEUS FPIF interface board allows the user to easily wire up a panel using pin and crimp style connectors see page 88 Contact Eurotech see Eurotech Group Worldwide Presence page 101 for purchasing information for the ZEUS FPIF Alternatively the display interface is connected to an LVDS interface see the section LVDS interface page 41 Th
76. r page 69 J6 Audio J6 Audio connector page 69 J7 SDIO J7 SDIO socket page 70 J8 LVDS interface J8 LVDS connector page 71 J9 JTAG J9 JTAG connector page 71 J10 USB J10 USB connector page 72 J11 10 100BaseTX Ethernet J11 10 100BaseTX Ethernet connector interface page 72 J12 Ethernet controller status 12 Ethernet status LEDs connector page 73 LEDs J13 64 way PC 104 J13 amp J14 PC 104 connectors page 74 expansion 14 40 PC 104 J13 amp J14 PC 104 connectors 74 expansion J15 Power battery external J15 Power connector page 75 reset JP1 Battery disconnect JP1 Battery disconnect page 75 JP2 LCD logic supply selection JP2 LCD logic supply selection page 76 JP3 LVDS MSL selection LVDS MSL selection page 76 JP4 User Recovery link JP4 User Recovery link selection page 76 selection JP5 External reset JP5 External reset page 76 JP6 JTAG enable JP6 JTAG enable page 77 Issue D 65 TITAN user manual 3 EUROTECH J1 COMS ports Connector Oupiin 3014 40GRB SN 40 way 2 54mm 0 1 x 2 54mm 0 1 dual row IDC boxed header Mating connector FCI 71600 040LF Signal name Signal name SCL FC SDA FC GND 3V3 FC TX5 RS422 TX5 RS422 TX5 RX5 RS485 TX5 RX5 RS485 RX5 RS422 RX5 RS422 GND 0 0 0 O O O 0 0 0 0 O O
77. rldwide Presence page 101 for further information about any of these products Issue D G EUROTECH Introduction Product handling and environmental compliance Anti static handling This board contains CMOS devices that could be damaged in the event of static electricity being discharged through them At all times please observe anti static precautions when handling the board This includes storing the board in appropriate anti static packaging and wearing a wrist strap when handling the board Packaging Please ensure that should a board need to be returned to Eurotech it is adequately packed preferably in the original packing material Electromagnetic compatibility EMC The TITAN is classified as a component with regard to the European Community EMC regulations and it is the user s responsibility to ensure that systems using the board are compliant with the appropriate EMC standards RoHS compliance The European RoHS Directive Restriction on the Use of Certain Hazardous Substances Directive 2002 95 EC limits the amount of six specific substances within the composition of the product The ZEUS and associated accessory products are available as ROHS 6 compliant options and are identified by an R6 suffix in the product order code A full ROHS Compliance Materials Declaration Form is included in Appendix RoHS 6 Compliance Materials Declaration Form Further information about ROHS compliance is available on t
78. rs or tooth locking washers can cause short circuits and over voltage conditions Eurotech recommend that you use a Loctite screw thread lock or a similar product over tooth locking washers 86 Issue D 3 EUROTECH Appendix D Reference information Appendix D Reference information Product information Product notices updated drivers support material 24hr online ordering www eurotech ltd co uk PC 104 consortium PC 104 specifications vendor information and available add on products www PC 104 org USB information Universal Serial Bus USB specification and product information www usb org SDIO card information SD Card Association and product information www sdcard org www sdcard com www sandisk com oem manuals asp Intel Intel XScale PXA270 processor documentation www intel com www intel com design embeddedpca prodbref 302302pb htm Davicom Semiconductor Inc Davicom DM9000A Ethernet Controller documentation www davicom com tw eng index htm Exar Corporation Exar XR16C2850 DUART with 128 byte FIFO documentation WWW exar com Wolfson Microelectronics Wolfson WM9712L AC 97Codec documentation www wolfson co uk NXP Semiconductors NXP PCA9535 FC I O expander documentation WWW nxp com Issue D 87 TITAN user manual 3 EUROTECH Appendix E ZEUS FPIF details The ZEUS FPIF allows easy connection between the TITAN and a TFT or STN LCD flat panel display Details
79. shown below Variant Memory configuration Details TITAN TITAN FRx Mx Fx R6 PXA270 FRx 520 416MHz microprocessor Mx 64 128MB SDRAM Fx 32 64MB Flash Commercial temperature range TITAN FRx Mx Fx I R6 PXA270 FRx 520 416MHz microprocessor Mx 64 128MB SDRAM Fx 32 64MB Flash Industrial temperature range TITAN Lite TITANL 312 M64 F 16 R6 PXA270 312MHz CPU 64MB SDRAM 16MB Flash No SRAM PC 104 Audio or COM 4 amp 5 Commercial temperature range TITANL 312 M64 F16 I R6 270 312MHz CPU 64MB SDRAM 16MB Flash No SRAM PC 104 Audio or COM 4 amp 5 Industrial temperature range The TITAN board is RoHS compliant For alternative memory configurations please contact Eurotech see Eurotech Group Worldwide Presence page 101 for details Eurotech can provide custom configurations subject to a minimum order quantity for the TITAN TITAN Lite Please contact our Sales team to discuss your requirements TITAN user manual 3 EUROTECH TITAN at a glance SDIO socket 10 100 Base T Ethernet Audio In Out MIC AMP Jumpers Y g Quick Capture Mo camera AM Digital Power NOEL Amm inc battery input Touchscreen Five serial ports Ethernet LEDs JTAG Intel PXA270 Banery XScale 520MHz processor AMD Mirrorbit Flash Jumpers 8 16 bit PC 104 interface USB hosts client LVDS optional TFT STN panel 6 Issue D SU Introdu
80. significant byte Least significant byte 0 11800000 PC 104 9 IRQ14 and IRQ15 are not available under Windows as all interrupt sources are fully utilised Once the PXA270 microprocessor has serviced a PC 104 interrupt the corresponding add on board clears the interrupt by driving the IRQ signal low When the TITAN hardware sees the interrupt go low the corresponding bit is automatically cleared from the 11 REG or 12 REG register If no further interrupts are pending the TITAN hardware drives GPIO 17 low once the interrupt has been cleared at the source Issue D 3 EUROTECH Detailed hardware description In cases where other PC 104 IRQs are asserted while the driver is processing a PC 104 IRQ the TITAN drives GPIO 17 low for 375ns to 500ns once this interrupt has been cleared This short low pulse indicates to the PXA270 that there is another pending interrupt This situation is shown in the following diagram Delay 375 500ns GPIO17 Driver processing IRQ4 Driver processing IRQ3 due to priority over IRQ6 PC104 IRQ3 Driver clears IRQ3 at source Bit 0 IRQ3 cleared 11 automatically on falling edge PC104 IRQ6 PC104 IRQ4 PC 104 reset The reset generated to the PC 104 add on board is a combination of the nRESET OUT Z pin of the PXA270 and the status of the PC104 RST bit of the control register C REG To reset PC 104 add on boards independently fro
81. t down mode the device becomes idle data conversion is disabled and the Temp register holds the latest result however the device interface is still active and register write read operation can be performed The device operation mode is controllable by programming bit BO of the configuration register The temperature conversion is initiated when the device is powered up or put back into normal mode from shut down The power consumption in shut down mode is near zero 11 5uW For more information about power management refer to the LM75A datasheet contained on the Development Kit CD I O expander power management When the serial interface is idle and the PWM intensity control is unused the MAX7313 automatically enters standby mode If the PWM intensity control is used the operating current is slightly higher because the internal PWM oscillator is running The power consumption in standby mode with PWM disabled is near zero 3 6uW The IO expander has 10kQ pull up resistors on PO 15 Dependant on which of these signals are configured as input or output or what logic level each output is configured at during sleep determines the current attributed by these resistors during sleep 0 15 direction Current Watts each Current Watts all Input floating OmA 0mW OmA 0mW Input high VCC_PER 0mW 0mW Input high 3 3V 0 17mA 0 29 2 2mA 4 62mW Input low OV 0 5mA 2 5mW 40mW Output
82. t panel interface for STN and TFT displays on 40 pin boxed connector e Up to 800x600 resolution 8 16bpp e Backlight control o e Optional LVDS interface e LCD voltage 3 3V 5V selection jumper o e LVDS encoding mode selector jumper for signalling decoding LVDS display receiver Audio and touchscreen o e Wolfson WM9712L AC 97 compatible CODEC Line line out microphone stereo amp out on 12 pin boxed header o e Touchscreen support 4 5 wire analogue resistive on 5 pin boxed header Quick Capture camera interface e Intel Quick Capture technology 20 pin boxed header connector to a camera image sensor bus e Multi master serial bus header connection Configuration PROM e l C PROM for storing configuration data Watchdog timer e External to PXA270 generates reset on timeout Timeout range 1ms 60s User configuration e Three user configurable jumpers on 8 pin header General I O Sixteen user configurable general purpose I O 20 pin boxed header e 5V tolerant inputs e 3 3V outputs pulled up to 5V e PWM outputs for LED intensity control 8 Issue D eiat Introduction Temperature sensor e IC temperature sensor Battery backup On board battery holder containing lithium ion non rechargeable 2032 3V 220mAn battery e Battery disconnect jumper Test support JTAG interface 10 pin header e Download data to FLASH
83. that provides combined TX and RX signals On J1 pin 5 provides TXB RXB and pin 6 provides TXA RXA A ground connection is also required for this interface The maximum cable length for this interface is the same as for RS422 4000ft but RS485 supports up to 32 transmitters and receivers on a single network Only one transmitter should be switched on at a time The TITAN uses the RTS signal to control transmission When this signal is at logic 1 the driver is switched off and data can be received from other devices When the RTS line is at logic 0 the driver is on Any data that is transmitted from the TITAN is automatically echoed back to the receiver This enables the serial communications software to detect that all data has been sent and disable the transmitter when required The UART used on the TITAN for COM5 has extended features including auto RTS control for RS485 This forces the RTS signal to change state and therefore the direction of the RS485 transceivers when the last bit of a character has been sent onto the wire Please refer to the XR16C2850 datasheet on the Development Kit CD for more information The RS422 485 cable shield MUST be connected between TITAN J1 pin 9 GND and the ground connection of the connecting equipment Failure to do so can result in TITAN RS422 485 transceiver being permanently damaged Issue D 3 EUROTECH Detailed hardware description Typical RS422 and RS485 connection RS422 POINT TO
84. ting connector details The signals on J3 correspond to the pin names of the MAX7313 PO P15 3 3V P16 GPIO116 Port 16 of the MAX7313 is configured as an interrupt so that any I O Expander GPIO pin configured as an input can cause the PXA270 to be interrupted on GPIO116 These can also be used as PXA270 wake up sources from sleep mode Temperature sensor There is a Philips LM75A temperature sensor on the TITAN The LM75A is a temperature to digital converter using an on chip band gap temperature sensor and Sigma delta A to D conversion technique The device is also a thermal detector providing an over temperature detection output OVERTEMP signal on GPIO 12 which can be used to wake the PXA270 up from sleep The accuracy of LM75A is 2 at 25 C to 100 C and 3 C at 55 C to 125 C The LM75A is connected to the bus of the 270 processor and is accessible at 2 bus address 0x48 52 Issue G EUROTECH Detailed hardware description JTAG and debug access Debug access to the PXA270 processor is via the JTAG connector J9 See J9 JTAG connector page 71 for details Jumper JP6 needs to be inserted to enable the JTAG interface for PXA270 debug See section JP6 JTAG enable page 77 for details The Macraigor Wiggler and EPI Majic probe have been used to debug the PXA270 processor on the TITAN There are many other debug tools that can be interfaced to the TITAN for access to the JTAG
85. tity module USIM interface e Quick Capture camera interface JTAG interface 356 pin VF BGA packaging The design supports 520MHz 416MHz and 312MHz speed variants of the PXA270 processor The standard variant of the TITAN board includes the 520MHz version of the PXA270 The TITAN LITE board is fitted with the a 312MHz version of the PXA270 The maximum speed available for extended temperature versions of the TITAN is 416MHz A 13MHz external crystal is used to run the PXA270 processor All other clocks generated internally in the processor The PXA270 processor family provides multimedia performance low power capabilities and rich peripheral integration Designed for wireless clients it incorporates the latest Intel advances in mobile technology over its predecessor the PXA255 processor The 270 processor features scalability by operating from 104MHz up to 520MHz providing enough performance for the most demanding control and monitoring applications PXA270 is the first Intel Personal Internet Client Architecture PCA processor to include Intel Wireless MMX technology enabling high performance low power multimedia acceleration with a general purpose instruction set Intel Quick Capture technology provides a flexible and powerful camera interface for capturing digital images and video Power consumption is also a critical component Wireless Intel SpeedStep technology provides the new capabilities in low
86. used to quickly add digital I O analogue I O serial ports video capture devices PC card interfaces etc The ISA bus is based on the x86 architecture and is not normally associated with RISC processors You would need to modify the standard drivers to support any third party PC 104 modules Any PC 104 add on board attached to the TITAN is accessible from the PC card memory space socket 1 The memory map is shown in the following table Address Region size Region name 0x30000000 0x300003FF 1KB PC 104 I O space 8 16 bit 0x30000400 Ox3BFFFFFF Reserved PC 104 memory space 16 bit or 8 bit write only 0x3C200000 Ox3FFFFFFF Reserved 0x3C000000 Ox3C1FFFFF 16MB PC 104 interface details Issue D The PC 104 bus signals are compatible with the ISA bus electrical timing definitions All signals between the PXA270 and the PC 104 are buffered When the PC 104 bus is not in use all output signals with the exception of the clock signals are set to their inactive state The TITAN provides 5V VCC PER to the PC 104 connectors J13 and J14 If a PC 104 add on board requires a 12V supply then 12V can be supplied via the TITAN power connector J15 pin 4 If 12V or 5V are required these must be supplied directly to the PC 104 add on board Do NOT attempt to power the TITAN using the VCC PER pins PER is an isolated supply switched under hardware control from the A VCC input on J15 pin 1 ALWAYS prov
87. version and issue bit assignments are detailed in the table below Board version issue register BV REG Bytelane Most significant byte Least significant byte VERSION BCD ISSUE BCD X X X X X X X X Current version Current issue Address 0x11000000 Issue D 3 EUROTECH Appendix A Board version issue Mod box The mod box indicates the ECO level that the TITAN is at for a particular version issue of the board The mod box is located on the bottom side behind the video connector J4 as shown below ull i he CPLD versions The TITAN CPLD versions can be read out of the CPLD versions register CV_ REG at the address 0x12000000 The CPLD versions bit assignments are detailed in the table below CPLD versions register CV_REG Byte lane Most significant byte Least significant byte BED e n CPLD 1 version Address 0x12000000 Issue D 83 TITAN user manual 3 EUROTECH Appendix B Specification 84 Microprocessor Cache System memory Silicon disk SRAM o Serial ports USB support Network support Expansion interfaces Date time support Video o Audio and touchscreen Quick Capture camera interface l C bus Configuration PROM PXA270 312MHz TITAN Lite only 416 520MHz XScale processor 520MHz as standard option 32K data cache 32K instruction cache 2K mini data cache Fixed on board memory 64MB SDRAM 32 bit wide SDRAM data bus
88. wake up source for PXA270 from sleep mode The touchscreen interface is broken out on the header J5 See J5 Touchscreen connector page 69 for connector and mating connector details Issue D 3 EUROTECH Detailed hardware description USB USB host 2 Issue D There are two USB host interfaces on the TITAN These comply with the Universal Serial Bus Specification Rev 1 1 supporting data transfer at full speed 12Mbps and low speed 1 5Mbps There are four signal lines associated with each USB channel VBUS DATA DATA and GND Their arrangement is summarized in the illustration below USB connector 1 J10 USB connector 2 VBUS 1 VBUS 2 1 gt CES 24 DATA 1 DATA 2 ERI uos DATA 1 DATA 2 DEA uou GND GND 224 5 2 s SHIELD 9 o 10 SHIELD A USB power control switch controls the power and protects against short circuit conditions If the USB voltage is short circuited or more than 500mA is drawn from either supply the switch turns the power supply off and automatically protects the device and board If an over current condition occurs on a USB channel the over current condition is flagged to GPIO 88 and GPIO 114 for USB channel 1 and channel 2 respectively This is shown in the following tables USB OC1
89. ynchronous Receiver Transmitter Core Clock Configuration Register Coder Decoder Communication Port Complex Programmable Logic Device Central Processing Unit PXA270 Complementary Metal Oxide Semiconductor Cathode Ray Tube Direct Memory Access Dual Universal Asynchronous Receiver Transmitter Electrically Erasable and Programmable Read Only Memory Electromagnetic Compatibility Full Function Universal Asynchronous Receiver Transmitter First In First Out A non volatile memory that is preserved even if the power is lost Flat Panel Interface General Purpose Input Output IIC Intra Integrated Circuit bus In Circuit Emulator Institute of Electrical and Electronics Engineers Input Output Industry Standard Architecture Bus in the IBM PC Joint Test Action Group of IEEE kilo bits per second Light Emitting Diode Liquid Crystal Display Low Voltage Differential Signalling mega bits per second Not Applicable No Connect Not Used Operating System Offers full architecture hardware and software compatibility with the PC ISA bus but in ultra compact 96mm x 91mm 3 775 x 3 550 stackable modules Printed Circuit Board Programmable Read Only Memory Pulse Width Modulation Random Access Memory Regulator Real Time Clock Receive Issue D 3 EUROTECH Appendix Acronyms abbreviations SBC Single Board Computer SDIO Secure Digital Input Output SDRAM Synchronous Dynamic Random Access Memory S
90. z DUART Generation 24 576MHz AC 97 Codec 25MHz Ethernet Controler TITAN LITE only 3V3 5V LCD Logic Supply Jumper Issue D 3V3 LVDS Conn J8 2xUSB Header J10 3V3 JTAG Header J9 3V3 SD Socket J7 3V3 2V8 CIF Camera Header J2 5V GPIO Header J3 32 768kHz Z Not avaliable for standard TITAN LITE 15 TITAN user manual TITAN address map 9 PXA270 chip select SDCSOf Physical address 0x00000000 OxO3FFFFFE 0x04000000 OxO7FFFFFE 0x08000000 OxOFFFFFFF 0x10000000 0x1000000E 0x10000010 Ox107FFFFF 0x10800000 0x1080000E 0x10800010 Ox10FFFFFF 0x11000000 0x11000001 0x11000002 Ox117FFFFF 0x11800000 0x11800001 0x11800002 Ox11FFFFFF 0x12000000 0x12000001 0x12000002 Ox127FFFFF 0x12800000 0x12800001 0x12800002 Ox12FFFFFF 0x13000000 0x13000001 0x13000002 Ox13FFFFFF 0x14000000 Ox17FFFFFE 0x18000000 Ox1FFFFFFF 0x30000000 0x300003FF 0x30000400 Ox3BFFFFFF 0x3C000000 Ox3C1FFFFF 0x3C200000 Ox3FFFFFFF 0x40000000 OxA3FFFFFF 0x44000000 OxA7FFFFFC 0x48000000 Ox4BFFFFFC 0x4C000000 Ox4FFFFFFC 0x50000000 Ox53FFFFFC 0x54000000 Ox57FFFFFC 0x58000000 OxSBFFFFFC 0x5C000000 0x5COOFFFC 0x5C010000 0x5C0O1FFFC 0x5C020000 0x5CO2FFFC 0x5C030000 0x5CO3FFFC 0x5C040000 OX7FFFFFFF 0x80000000 Ox8FFFFFFF 0x90000000 OxFFFFFFFF 3 EUROTECH Bus width Des

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