EXC-H009VME/M: User`s Manual, Rev A-3, April 1997
Contents
1. aaa aa Aaaa aana 30 GONTROEWORB ie ene eaae a daha eei E 30 Memory Location Sequence a nece Rae 32 MESSAGE BLOCK FORMATS nette denne siae deeds desea dene 33 CONTINUOUS OR ONE SHOT MESSAGE TRANSFERS 37 CONTROL REGISTER 5 2 0 38 INSTRUCTION COUNTER 7 38 FRAME TIME REGISTERS amp LO 4 gt 7 6 38 WORD COUNT REGISTER 7 8 39 COUNT REGISTER _ 7 iare eee e Ee 39 PERIOD DATA GAP REGISTER 2 0444 2 1 0 0 0000 00 00 nennen nnne nne aia nnne 40 LOOP COUNT REGISTER 7EBE H 40 FIRMWARE DATE CODE 7 40 FIRMWARE REVISION REGISTER 7 2 40 STACK POINTER 41 VARIABLE AMPLITUDE DATA REGISTER 7 6 41 EXC H009VME M VARIABLE AMPLITUDE CLOCK REGISTER 7 8 41 INTERRUPT CONDITION REGISTER 7 41 ME2. 9 Vector 0 Vector 1 Register amp VME BASE 20 22 H Read Write 10 DIVIDER VXI amp VME BASE 24 H 11 Reserved Register VXI amp VME BASE 26 to 30 H 11 MEMORY REGISTERS ADDRESS MAPPING 22 2 2 11 GENERAL MEMORY 13 009 MEMORY 13 ordre 14 MEMORY MAP m 15 DATA WORDS LOOK UP TABLE 6600 gt 75 16 HOW TO CREATE THE ADDRESS TO THE sss nnns 16 MESSAGE STACK 7600 2 ZDFE H itai cr ee e Ea eee dede eae oue 17 TABLE 7 00 gt 7ETE H tease te rep tede iei HR gen 18 ERROR INJECTION TABLE 7 20 gt 7 19 WORD COUNT ERROR TABLE 7E40 gt 7 5 19 EXC H009VME M BIT COUNT ERROR TABLE 7E60 gt 7 7 19 PERIOD DATA TIME TABLE 7 80 gt 7 9 20 COMMAND RESPONSE TABLE 7 0 gt 7
3. 20 FIRMWARE DATE CODE 7 21 FIRMWARE REVISION REGISTER 7 2 21 MESSAGE STACK POINTER 7ECA H aiat tea ete 21 VARIABLE DATA AMPLITUDE REGISTER 7EC6 H sse nennen 21 MESSAGE STATUS REGISTER 7 eene 22 STARE REGISTER YEDO LI 4 eee eeu 22 BOARD STATUS REGISTER YEB2 Hy a i eter tette rid t er e ee eds 22 BOARD ID REGISTER YED4 EH itin e m m d P epar n dae eda es 23 BOARD CONFIGURATION REGISTER 7 06 23 CLOCK SKEW REGISTER 7ED8 H c cecceceeeeeceseeeeeeeaeeeceeceecaeeaecaceecaecaesacseseesaeeassasesaesaesaseeseeeanetes 23 SOFTWARE RESET REGISTER 7 80 sss 23 TIME TAG RESET REGISTER 7F84 H WRITE ssssssssssssseeeeeennennnn tenentes 23 TIME TAG COUNTER 7F86 7F88 H READ 24 TIME TAG OPTIONS REGISTER 7F8A H 24 CCC CONCURRENT PU 25 CCC CONCURRENT PU MEMORY 00 26 INSTRUCTION STACK eec 27 Message Status da Wy Hi e ee ee ee Wai ee 28 Intermessage Gap Time Hi and Low Written by 29 Message Block Pointer Written by 0 teens 29 55 2 lt
4. 51 FIRMWARE REVISION REGISTER 7EC2 H 4 52 CURRENT BLOCK INDEX 7 52 MESSAGE STATUS REGISTER 52 START REGISTER 7EDO H FEDO H sess nnne nnne trennen nnns 52 BOARD STATUS REGISTER 7 02 2 53 BOARD ID REGISTER 7EDA H 40244 42 2 011200600 10 1010300 53 BOARD CONFIGURATION REGISTER 7 06 sss 53 SOFTWARE RESET REGISTER 7 80 54 GLOBAL REGISTERS 55 BOARD RESET REGISTER 7 90 WRITE 55 CONCURRENT START REGISTER 7F94 H FF94 H WRITE 55 LAV OUT peces 56 Sr PTY na 56 DIPSWITCH SETTINGS 57 Card Logical Address Dip Switch Setting 5 57 H009 Coupling Mode Select 5 1 SW2 SW3 54 enne 57 FACTORY DEFAULT DIP SWITCH 5 5 2 4 022 4 1111 58 EXC H009VME M JUMPERS t ge ORC ES 59 VME Address Space Select Jumper JP1 ssssssseeeeeeeeene nennen 59 VXI MODID Connect Jumper nnt ntn tne nnns 59 Transformers Cen
5. 1553 CONNECTORS The EXC H009VME M card contains 4 Twinax Connectors P3 P4 P5 P6 They connect the card to the 009 Bus The connectors pinouts are described below P3 P4 P5 P4 DATAA DATAA CLKA DATAB CLKB IN SYSTEM PROGRAMMABLE CONNECTORS The connectors CON2 and CON3 are used for down loading the In System Programmable chips on the board They are used for future Updating of the boards VME INTERFACE CONNECTORS The connectors and P2 are used for connecting the board to the VME bus Their descriptions are on the following pages 61 EXC H009VME M Connector P1 Pinout The following VME signals are used by the EXC H009VME M A9 5V 62 m Be Bs BG20uT Bia Bs 1 jv 5V EXC H009VME M Connector P2 Pinout The following VME signals are used by the EXC H009VME M NOTE VXI signals each of them is unconnected unless the specific jumper is shorted See Jumpers section 63 EXC H009VME M POWER REQUIREMENTS The following table shows the Power Requirements of the Full Board EXC H009VME M including the Conc Monitor SIGNAL QUIESCENT 50 DUTY CYCLE 1 75 Amp 1 75 Amp 0 085 Amp 0 185 Amp 0 155 Amp 0 255 Amp ORDERING INFORMATION Part Number Description EXC H009VME BASE H009 VME B size 6 x9 card Supports
6. Error message stops CCC operation The user can restart by writing to the Instruction Count and Start bit Selects Even parity in 009 word 1 Halt stops CCC transfer operation This bit must be reset to 0 to Run or Continue Transmits fewer or more words than are indicated by the Word Count field This function is valid for CCC to PU messages only Transmits invalid number of bits within 009 words Set to 0 First H009 data word is transmitted with invalid gap time between select and data word For Parity and Bit Count error injection this bit chooses whether to insert t he error in the select word or the data words 0 in Select word 1 in Data words Selects active 009 channel logical 1 selects channel logical 0 selects channel B On error the CCC will retry message transfer on alternate bus auto retry must be selected On error selects the number of retries before transferring the next message Retries are executed with a short intermessage gap _1 _0 meaning 0 0 no retry 0 1 1 retry 1 0 2 retries 1 1 3 retries 0000 Send Message 0001 Skip Message 0010 Jump Command 0011 RESERVED 1111 RESERVED 31 EXC H009VME M HALT Operation The user normally sets this bit to a logic 0 before writing to the Start Register The user may in real time during execution set this bit to a logic 1 The board when operating on that particular Message Block s Control Word will HA
7. VXI MODID Connect Jumper JP4 This jumper connects the card to the VXI MODID signal located at P2 A30 Jumper shorted MODID connected ready for VXI environment Jumper open MODID disconnected pin P2 A30 free for VME user defined Transformers Central Tap Gnd Connection 5 8 These jumpers connect the Central tap of the 1553 Transformers to gnd They should be left OPEN 59 EXC H009VME M FACTORY DEFAULT JUMPER SETTINGS Factory Jumpers Setup for VME JP1 Set to A24 Address Space Shorted JP2 JP3 Set to High Address Space A15 A14 Open JP4 Set to MODID disconnected Open 5 8 Set to Not GND Middle Tapped Open Factory Jumpers Setup for VXI JP1 Set to A24 Address Space Shorted JP4 Set to MODID connected Shorted TERMINATION RESISTORS Because the 009 Spec does not clarify how the 009 bus should exactly behave Excalibur added an option on the board to add parallel Resistors on the two taps of the DATA and CLOCK lines BUS A and B Their description are as following R11 A termination resistor for the DATA A lines R14 A termination resistor for the CLOCK A lines R17 A termination resistor for the DATA B lines R20 termination resistor for the CLOCK lines The boards come with a default Resistor with a value of 68 ohm on all of the lines It is recommended to have a total resistance of 34 ohm on each one of the lines 60 EXC H009VME M CONNECTORS
8. 39 3A 3D 3E or XXXX XXXX A32 mode with ADDRESS MODIFIER CODES 09 OD OE The Memory is divided into two distinct blocks 1 VME VXI Configuration Registers 2 009 Storage Area and Control Registers The VME VXI Configuration Registers are used for setting up the card within the user s VME or VXI system The 009 Storage Area and Control Registers are used to control the operation of the card the 009 busses VME VXI CONFIGURATION REGISTERS The VME VXI Configuration registers are located within a 64 byte block in the A16 address space between the addresses 49152 dec CO00H and 65472 dec FFCOH The base address of the Configuration registers is determined by the following equation Base Address dec V 64 49152 dec the Logical Address of the card is an integer which varies between and 255 and is defined by the user via the 8 pole dip switch SW5 see Dip Switch Settings section In order to ensure correct operation of the card within the user s VME or VXI system the Configuration registers must be reinitialized after power up or after assertion of SYSRESET For a full explanation of the VXI Configuration registers and other topics relating to operation of the V XI bus refer to the VXI Bus System Specification section Configuration Register Memory Map REGISTER ADDRESS TTAG DIVIDER BASE 24 READ WRITE VECTOR REGISTER BASE 22
9. BIT COUNT ERROR TABLE 7 60 gt 7E7E H The Bit Count Error is selected by writing to the Bit Count Error Table This table contains 16 WORDS one per Peripheral Unit The first word relates to PU 0 the second to PU 1 while the last location relates to PU 15 This register sets the number of total bits within the 009 DATA word including Parity This register is utilized by the board only if the Bit Count Error bit is set within the Error Injection Register of this particular PU If the bit is not set then a valid 17 bit word 16 data bits 1 parity bit is transmitted regardless of the contents of this register 19 EXC H009VME M BIT COUNT ERROR WORD DEFINITION mem 0 _ eem 5 _ mem Lm emm pm jm PERIOD DATA TIME TABLE 7E80 7E9E H This table contains registers which set the DEAD TIME between Data Words sent from the different Peripheral Units The resolution of these registers is microsecond per bit This time is measured as the DEAD TIME on the H009 bus The default time is equal to 5 0 usec if no error injection is requested A value greater than 7 is not recommended as it will cause each data word to be interpreted as a select word by other PU s on the bus and may crash into new select words from the CCC PU 15 7E9E H PU 0 7E60 H COMMAND RESPONSE TABLE 7EAO0 7EBE H Upon receiving a Select Word with the Command Indicator set to 1 the PU r
10. If no PUs are activated the board will act as a CCC only For CCC to PU commands the user sets up the select word and all the data words to be sent For PU to CCC commands for which the user is simulating only the CCC the user sets up the select word and leaves space for the data words to be read into If the user is simulating both the CCC and the PU in a CCC to PU command the user must fill in both the select word and the data words NOTE The user should use the following sequence to determine whether the board is installed AND ready to operate Check the Board ID register test for value 2 4939 Hex Check Board Status Register test for Board Ready bit 1 The board is installed and ready when BOTH of these registers contain the correct values as written above This sequence should be used after power on and software reset operations For Software Reset operations these values should be set to ZERO by the user immediately prior to writing to the software Board Reset Register 25 EXC H009VME M CCC CONCURRENT PU MEMORY MAP FRAME COUNTER HIGH 7F88 H TEDA t zn zn rece M TECA TECC M recs rece rece H H CS TEs H ree ZI TERE M INSTRUCTION STACK 0000 H 7E8F H AND MESSAGE BLOCK AREA 26 EXC H009VME M INSTRUCTION STACK The user programs the EXC H009 VME M the Instruction Sta
11. see Control Register Definitions sections NOTE 1 The user can also read the counter s value any time at the Time Tag Counter addresses see Control Register Definitions section 2 The counter can also be clocked and or reset from external source see Connectors section 009 Select This location contains the 009 Select Word associated with the message Only ACTIVE PU H009 Select Words are stored ACTIVE PU TABLE 7 00 gt 7 These 16 locations words contain the list of Active Peripheral Units and their Interrupt Enables Each PU which is to be simulated is selected by setting bit O within the Active Peripheral Unit Word to a logic 1 This register also allows the user to enable an interrupt trigger Writing a logic l to bit 1 enables the interrupt condition An interrupt will be generated at the end of processing for every message directed to a PU being simulated by the board for which the Interrupt Bit is set The first Active PU word relates to PU 0 the next to PU 1 while the last location relates to PU 15 Active PU 15 Active Peripheral Unit WORD 7E1E H 16th WORD Peripheral Unit Table PU 0 Active PU 0 Active Peripheral Unit WORD Unit WORD 7 00 1st WORD ACTIVE Peripheral Unit WORD DEFINITION FUNCTION 182 RESERVED set to 0 i 0 NO INTERRUPT 1 INTERRUPT oo 0 INACTIVE 1 ACTIVE 18 EXC H009VME M ERROR INJECTION FEATURES The EX
12. 002 CONCURRENT PU SEQUENTIAL BLOCK MODE OTHERS RESERVED CLOCK SKEW REGISTER 7ED8 H Writing to this location will alter the synchronization of the data sent by the PU with respect to the clock signal received from the CCC The default value of 4 results in complete synchronization Higher numbers delay the data by approximately 25 nanoseconds per bit Lower numbers cause the data to be sent earlier Valid values are from 0 to 15 This register takes effect only when the board is turned off To alter the value write 0 to the START register check the Board Status Register to make sure it is off alter the value of the Clock Skew Register and then write a 1 to the START register SOFTWARE RESET REGISTER 7F80 H Writing to this location will RESET the board The board will act as if POWER had been switched off then on The data field is ignored NOTE RESET ERASES ALL MEMORY LOCATIONS WITHIN THE DUAL PORT RAM The Board Status the Board ID Firmware Revision and Variable Amplitude registers are written by the board after the reset operation has been completed TIME TAG RESET REGISTER 7F84 H WRITE Writing to this location data field don t care will reset the current bank s Time Tag Counter The counter will start to count from 0 immediately after the reset 23 EXC H009VME M TIME TAG COUNTER 7F86 7F88 H READ These two words contain the current bank s free running 32 bit Time Tag Counter
13. 2 to OFF or OPEN and ALL other positions to ON or CLOSED H009 Coupling Mode Select SW1 SW2 SW3 SW4 These switches select the coupling mode to the 009 Bus The following list describes the difference Dip Switches SWI BUS A of the CCC PU and Concurrent Monitor SW2 CLK A of the CCC PU and Concurrent Monitor SW3 BUS B of the CCC PU and Concurrent Monitor SWA CLK B of the CCC PU and Concurrent Monitor All the switches on Dip Switches SW1 SW4 should be in the following situation Switches 1 amp 2 ON CLOSED and Switches 3 amp 4 OFF OPEN In this position the Series Resisters are connected on the 009 line 57 EXC H009VME M FACTORY DEFAULT DIP SWITCH SETTINGS SWS Set to Logical Address 80H 1 off 2 8 on 2 A16 address E000 H SWI SW4 Set as following Switches 1 amp 2 ON CLOSED Switches 3 amp 4 OFF OPEN 58 EXC H009VME M JUMPERS Few Jumper Headers are provided on the card for various user selectable functions These headers are mounted with shorting blocks according to the default card setup see Factory Default Jumper Settings section below In high vibration environments these jumpers can be soldered or Wire Wrapped Jumpers not appearing on the Card Layout are factory set and should not be used VME Address Space Select Jumper JP1 This jumper selects the VME Address Space that the card s memory will be located at Jumper shorted 24 address space Jumper open A32 address space
14. 22 10 95 write 16A5 H to the register FIRMWARE REVISION REGISTER 7EC2 H This register indicates the revision level of the on board firmware The value 0100 H would be read as revision level 1 00 40 EXC H009VME M STACK POINTER 7EC4 H The Stack Pointer points to the Instruction Stack The Instruction Stack can reside anywhere within locations 0000 H and 7E8F H This register must be set before issuing a START to the board To modify this register issue a STOP modify and then re issue a START see START Register VARIABLE AMPLITUDE DATA REGISTER 7EC6 H This register specifies the amplitude of the H009 output data signal The signal can be programmed from 0 volts up to 7 5 volts measured on H009 bus with specified H009 coupling and 35 ohm load two 70 ohm termination resistors were used A higher Transmit output amplitude will appear on the H009 bus if 78 ohm termination resistors are used The register has a resolution of 30mv bit p p on the bus This register must be set before issuing a START to the board To modify this register issue a STOP modify and then re issue a START see START Register The Register defaults to FFH after Reset providing maximum amplitude VARIABLE AMPLITUDE CLOCK REGISTER 7EC8 H This register has the same function as the Variable Data Amplitude Register This register controls the amplitude of the clock extracting out of the board INTERRUPT CONDITION REGISTER 7EC
15. CCC PU Non Concurrent Monitor EXC H009VME M FULL H009 VME B size 6 x9 card Supports CCC PU Non Concurrent Monitor Concurrent Monitor 64 EXC H009VME M The information contained in this document is believed to be accurate However no responsibility is assumed by Excalibur Systems Inc for its use and no license or rights are granted by implication or otherwise in connection therewith Specifications are subject to change without notice April 1997 Rev A 3 65
16. Error Injection functions SOFTWARE RESET REGISTER 7F80 H Writing to this location will RESET the CCC PU MON section only This section will act as if POWER had been switched off and then on The data field is ignored NOTE RESET ERASES ALL MEMORY LOCATIONS WITHIN THE DUAL PORT RAM The Board Status the Board ID Firmware Revision and Variable Amplitude registers are written by the board after the reset operation has been completed 44 EXC H009VME M BUS MONITOR OPERATION non concurrent concurrent The EXC H009VME M can be configured as a passive monitor It will store all traffic on the 009 bus associating a 32 bit time tag and a status word with each 009 message The user may selectively monitor messages based on the unit address Command indicator control filed and T R bit fields of the select word and may choose to generate an interrupt or halt transmission based on those same criteria A running count of all messages recorded is maintained There are 586 data blocks which are filled in sequentially When the last data block is filled in the buffer wraps around and the following block is place in block number 0 The Non Concurrent Mode and the Concurrent Mode have exactly the same descriptions and addresses therefore the manual will show them together The Concurrent Monitor has an offset of 8000 Hex from the Non Concurrent Monitor see Memory Maps below The Non Concurrent Monitor will be refered at the remainder of thi
17. H VECTOR 0 REGISTER BASE 20 OFFSET REGISTER BASE 06 STATUS CONTROL BASE 04 REGISTER DEVICE TYPE REGISTER BASE 02 H ID REGISTER BASE 4 00 H EXC H009VME M ID Register VXI only 00 READ ONLY The contents of this 16 bit register provides the following information about the card s configuration BIT SET TO FUNCTION 11 0 F54 Hex MANUFACTURER ID 3924 Dec 01 A32 ADD SPACE JP1 UNCONNECTED ADDRESS SPACE 00 A24 ADD SPACE JP1 CONNECTED 1544 11 DEVICE CLASS REGISTER BASED NOTE This register contains the same value whether set up for VME or VXI installation The VXI specification requires all V XI devices to identify themselves via an ID register This location is not defined under the VME specification Device Type Register only BASE 02 READ ONLY This 16 bit register contains a fixed Device Type Identifier as well as a four bit field which reflects the Required Memory usage of the card BIT amp SETTO FUNCTION 41 0 Hex MODEL CODE A32 ADD SPACE JP1 UNCONNECTED REQUIRED MEMORY m 4 Hex A24 ADD SPACE JP1 CONNECTED NOTE This register contains the same value whether set up for VME or VXI installation The VXI specifications requires the user to let the system know how much memory the device requires This is known as the m value in VXI parlance This location is not defined under
18. has been completed Set to 0 Indicates that the PU responded to a select word with the command indicator set with a bad data word Indicates that the PU data from a PU gt CCC message was received on the wrong bus Indicates that more words were received than were described within the select word s word count Indicates that fewer words were received than were described within the select word s word count Indicates that two words were received with a gap between them different from 5 microseconds Indicates that a bit with illegal Manchester coding was received Indicates that a data word with even parity was received Indicates that a word with greater than 16 bits 1 parity bit was received Indicates that a word with fewer than 16 bits 1 parity bit was received Indicates the occurrence of an error defined within one of the other message status bit locations NOTE logic 1 indicates occurrence of status flag 28 EXC H009VME M Intermessage Gap Time Hi and Low Written by user The Intermessage Gap Time is a 24 bit value indicating the time between the end of this message and the beginning of the following message The minimum intermessage gap time permitted by the 009 specification is 8 microseconds The intermessage gap time is given in units of 1 microsecond per bit The actual intermessage gap will be 4 microseconds greater than the number written to this field To request an intermessage gap of 8 microsecond
19. the VME specification EXC H009VME M Status Register amp BASE 04 READ ONLY A read of this 16 bit register provides information as defined below reser recae te sae aithe RESET btia the Corat 771 SML nds tre sate ofthe SYSFAL INHIBIT bitin the Cone Reger fesso meem 7 READY A 1 indicates that the power up sequence has completed and that the card is ready to accept commands This bit is a logical AND with the Conc Monitor s READY bit ums s esw es roseo macacs tme see RASEL Obis ire Comot Regeer esw o O voo raano meranom van WOOT Ine nance ATIVE nets me site fe ENABLE Dine Corral Reges NOTE MODID READY PASSED SYSFAIL INHIBIT and RESET functions are included to maintain compliance with the VXI specification It is recommended that VME users make use of the software reset described in the main body of this manual Control Register VXI amp BASE 04 WRITE ONLY Writing to this 16 bit register causes the actions listed below to be executed by the card Note that all bits in this register are set to 0 after assertion of VME bus SYSRESET RESET Writing a 1 to this bit forces the card into the RESET state BEN SYSFAIL INH This bit has no effect IRQSEL2 0 Writing to these bits selects which one of the VME bus Interrupt Request lines IRQ1 IRQ7 will b
20. value The user may read this value at any time The counter is reset upon power up or software reset and stays reset until the board has been started After the board is started in PU or Bus Monitor modes the counter starts counting up and may be re initialized to 0 by writing to the Time Tag Reset Register When reaching the value FFFFFFFFH the counter will wrap around to 0 and continue counting The user must first read the 16 bit value in address 7F86H and then read the 16 bit value in 7F88H The address location 7F86H contains the LSW while the address location 7F88H contains the MSW In CCC mode this value represents the Frame Time remaining When this value goes to 0 a new frame will be sent out if running in loop mode The resolution of this counter is 4 microseconds per bit TIME TAG OPTIONS REGISTER 7F8A H WRITE Writing to this register bit will select CCC PU MON s Time Tag Counter clock source This register is set to 0 after power up or software reset In this card the External Clock is a clock generated from the 16Mhz System Clock and divided by one of the Configuration Registers BIT FUNCTION NOT USE SET TO 0 0 Time Tag clock Internal 1 Time Tag clock External see TTAG CLOCK DIVIDER in Configuration Registers 24 EXC H009VME M CCC CONCURRENT PU OPERATION The EXC H009VME M can operate as the Central Computer Complex and up to 16 Peripheral Units
21. 2 SW3 and SW4 must be closed in order to obtain the correct ratio of the transformers and provide series resisters to the load line The user must make certain that the cable connecting the two devices is properly terminated with 68 Ohm resistors to insure data integrity The board has an option of inserting a resistor between the two taps of the DATA and CLOCK lines The board s default is a resistor of 68 ohm between each two taps When only one board has a Termination Resistor two resistors should be maintained in parallel to achieve a total resistance of 34 ohm See Termination Resistors section The EXC H009VME M complies with the following VME V XI parameters VME PARAMETERS Board type SLAVE Addressing A16 and A24 A32 Data D16 Interrupts 1 7 D08 O ROAK VXI PARAMETERS Device Class Register Based Manufacturer ID 3924dec F54H Address Space A16 A24 or A16 A32 Required Memory 64K m 0100 A24 1100 A32 Model Code 999 Hex The card interfaces to the VME via a 16 bit data bus Note that all accesses to the card must accesses 16 bits All byte accesses will be ignored The card may be accessed by using addresses in the following form accessing VME VXI Configuration Registers XXXX H A16 mode with ADDRESS MODIFIER CODES 29 2D Accessing Data Storage Area and Control Registers XX XXXX H A24 mode with ADDRESS MODIFIER CODES
22. C H This register allows the user to set different interrupt triggers When a condition that has been enabled within this register occurs an interrupt will be generated The user may check the Message Status Register to determine which condition caused the interrupt A logic 1 enables the interrupt condition Bit Function 15 4 Not used Set to 0 Message Error 2 End of Frame 1 Message Complete 0 0 NOTE For all Interrupt conditions the interrupt will be sent at the end of the message 41 MESSAGE STATUS REGISTER 7ECE H This register indicates the status of the card The figure below illustrates the definition of each Status bit A logic 1 indicates active condition Bit Function 15 4 Not used Set to 0 3 Message Error End of Frame 1 Message Complete 0 Wait for Continue WAIT FOR CONTINUE A message with the halt bit set has been encountered The user must reset the halt bit in the Control word to continue MESSAGE COMPLETE The last word of a message has been sent END OF FRAME The last word of the last message in a frame has been sent MESSAGE ERROR A message has been sent resulting in the error bit being set in the Message Status Word Starred Bits are NOT reset by the board and should be reset by the user after the user reads them START REGISTER 7EDO H This register controls the START STOP operation of the EXC H009VME M Writing to this register
23. C H009VME M card allows a variety of error injection options The error injection table is used to select which errors are to be associated with each PU Separate table are used to determine the precise nature of the error to be injected e g how many words to send if a word count error is to be injected ERROR INJECTION TABLE 7 20 7ES3E H The type of error to be injected within a transmitted message is selected by writing to the Error Injection Table This table contains 16 Words one per Peripheral Unit The first word relates to PU 0 the second to PU 1 while the last location relates to PU 15 BIT FUNCTION 15 4 RESERVED set to 0 o Data Word Parity Error Data Words Sent With Even Parity See Command Paes Dia Gap Eror See Peroa Data 0 Wor aun Err Sse Word WORD COUNT ERROR TABLE 7 40 gt 7 The Word Count error is selected by writing to the Word Count Error Table This table contains 16 WORDS one per Peripheral Unit The first word relates to PU 0 the second to PU 1 while the last location relates to PU 15 The contents of each location controls the number of H009 words to be sent within the message regardless of the contents of the word count field within the select word This table is defaulted to 00 by the board upon power on or software reset
24. Data Error Table The board will respond properly to messages received at the minimum rate permitted by the 009 specification 1 e it will respond properly to messages received with an intermessage gap of 8 0 usec measured as dead time on the bus NOTE The user should use the following sequence to determine whether the board is installed AND ready to operate Check the Board ID register test for value 2 4939 Hex Check Board Status Register test for Board Ready bit 1 The board is installed and ready when BOTH of these registers contain the correct values as written above This sequence should be used after power on and software reset operations For Software Reset operations these values should be set to ZERO by the user immediately prior to writing to the software Board Reset Register 14 reo rece reco COMMAND RESPONSE TABLE 7 0 to 7EBE 16 WORDS PERIOD DATA ERROR TABLE 7 80 to 7E9E H 16 WORDS BIT COUNT ERROR TABLE 7E60 to 7E7E H 16 WORDS WORD COUNT ERROR TABLE 7E40 to 7E5E H 16 WORDS ERROR INJECTION TABLE 7 20 to 7E3E H 16 WORDS ACTIVE PU TABLE 7E00 to 7E1E H MESSAGE STACK 256 BLOCKS 7600 to 7DFE H DATA WORDS LOOK UP TABLE 2K 6600 to 75FE H WORDS 009 DATA WORDS 0000 to 65FE H 15 DATA WORDS LOOK UP TABLE 6600 gt 75FE H The received Select word s PU Address Control Fiel
25. EXCALIBUR EXC H009VME M H009 Test and Simulation Board for VME and VXI Systems User s Manual 277 XCALISTE EXCALIBUR SYSTEMS 311 Meacham Avenue Elmont 11003 Tel 516 327 0000 Fax 516 327 4645 e mail excalibur mil 1553 com website www mil 1553 com EXC H009VME M TABLE OF CONTENTS hamis stieje PmM 1 INS FAL LATION e 2 009 05 2 3 Mmi 3 65 E 3 Accessing VME VXI Configuration 3 Accessing Data Storage Area and Control Registers sese 3 The Memoty Map zii reete eter enr Cea dn de ed e et avant Gielen 4 VME VXI CONFIGURATION 5 5 2 4 Configuration Register Memory 4 ID Register VXI only BASE 00 nennen nnns 5 Device Type Register VXI only 02 READ ONLY sse 5 Status Register VXI amp VME 04 6 Control Register VXI amp VME BASE 04 7 Offset Register amp VME BASE 06
26. LOCK INDEX 7ECA H FECA H The Current Block Index register contains the block number of the last block to have been filled in by the board It circulates between and 585 On start it contains FFFF to indicate no messages have been received by the board MESSAGE STATUS REGISTER 7ECE H FECE H This register indicates the status of the EXC HO09 VME M card The figure below illustrates the definition of each Status bit A logic 1 indicates active condition BIT FUNCTION DESCRIPTION A A message with an error has been received by the board MESSAGE COMPLETE A message has been received by the board NOTE Status Bits are NOT reset by the board and should be reset by the user after the user reads them START REGISTER 7EDO H FEDO H This register controls the START STOP operation of the EXC H009VME M Writing to this register with the appropriate bit set begins the Bus Monitor operation See the related bit data bit 04 within the Board Status Register which indicates when the board has been halted BIT FUNCTION 15101 RESERVED set to 0 1 START 0 STOP 52 EXC H009VME M BOARD STATUS REGISTER 7ED2 H FED2 H This register indicates the status of the EXC HO09VME M card In addition this register indicates option selection as defined below Status bits are active 1 The upper bits 615 65 should be set to 0 BIT FUNCTION 1505 RESER
27. LT transfer operations until the bit is reset to a logic 0 When the board detects that the HALT bit is set it sets the WAIT FOR CONTINUE bit within the Message Status Register see Control Register Section This bit can be used by the user in order to know when the board has arrived at this Instruction block When the board detects that the Halt bit has been reset continue mode the board will then reset the WAIT FOR CONTINUE bit within the Message Status Register NOTE This operation can be used in conjunction with the JUMP feature described below Skip Message Operation The SKIP MESSAGE command allows the user to easily skip a message defined in a certain Message Block by only modifying the Command field within the Control Word This allows the user to selectively send a message within the current frame The Intermessage Gap Time associated with the SKIP Message has no effect JUMP Command Operation The EXC H009VME M allows the user to modify the CCC transfer cycle by setting the JUMP command within the CCC Control Word The Jump command instructs the board to operate on a New instruction stack or New stack entry within the same stack This Control word is followed by a Stack Pointer word instead of the usual 009 SELECT Word In addition the Stack Pointer is followed by an Instruction Count value The Jump command is tested AFTER the board has tested the HALT CONTINUE bit within the Control Word The Intermessage Gap Time associat
28. ME M The user can Start then Stop the PU operation modify PU parameters and then re issue a new Start in real time See note on the Board Status Register Board Halted Running Bit 04 BIT FUNCTION NOT USE SET 0 t START 0 STOP BOARD STATUS REGISTER 7ED2 H This register indicates the status of the EXC H009VME M card BIT FUNCTION 155 NOT IN USE SET TO 0 1 BOARD HALTED 0 BOARD RUNNING 3 fems 3 wsmm 74 NOTE Bit 04 Board Halted is set by the board after the user stops the current operation by resetting the START bit within the Start Register The user must check this bit first before modifying registers which first require a STOP operation The board resets this bit after receiving a subsequent START command by writing to the Start Register The condition of this bit after power on or software reset is a logic 1 22 EXC H009VME M BOARD ID REGISTER 7EDA H This register contains a fixed value which can be read by a user s initialization routine to detect the presence of the EXC HO09VME M card The one word value of this register is 4939 Hex ASCII BOARD CONFIGURATION REGISTER 7ED6 H The operating mode of the board is set via this register This register must be set before issuing a START to the board To modify this register issue a STOP modify and then re issue a START see START Register
29. Message Status word are shown below BIT FUNCTION DESCRIPTION 15 End of Message Indicates that the message transfer has been completed EIL B A Indicates on which bus the message was transferred 1 B 0 BUSA Message Pending Set to logic 1 following reception of the select reset to 0 when End of Message is set ECHES Word Count Error Indicates that more words were received than were described within the select word s word count 7 Low Word Count Error Indicates that fewer words were received than were Lo Error described within the select word s word count Inter Word Gap Time Error Indicates that two words were received with a gap Error between them different from 5 microseconds Clock Response Indicates that no clock signal was detected on the Response active bus Manchester Error Indicates that a bit with illegal Manchester coding Error was received Parity Error Indicates that a data word with even parity Error received High Bit Count Error Indicates that a word with greater than 16 bits 1 parity bit was received Low Bit Count Error Indicates that a word with fewer than 16 bits 1 parity bit was received Error Indicates the occurrence of an error defined within one of the other message status bit locations Time Tag Read by user The Time Tag value is 32 bit word which may be used to determine the time elapsed since START or to determine the time between the 009 messages Th
30. SSAGE STATUS REGISTER 7ECE H 42 START REGISTER ee hed e f Pagine dedi eina a e dee dr cs 42 BOARD STATUS REGISTER 7 0 nnman 43 BOARD ID REGISTER corri efte ate aa eae 43 BOARD CONFIGURATION REGISTER 7 6 22 20 0 244 00000 43 CLOCK SKEW REGISTER 7 44 SOFTWARE RESET REGISTER 7 80 sss nter nnne trennen nnne 44 BUS MONITOR OPERATION NON CONCURRENT CONCURRENT 45 MONITOR MEMORY Lan canna SUR ma dmn 46 CONCURRENT MONITOR MEMORY 44 etna nn snnm etna than 47 BUS MONITOR MESSAGE BLOCK eene Ee dcn te i eet es 48 FILTER FUNCTION TABLE 6E00 H gt 7DFF H gt FDFF H 50 HOW TO CREATE THE ADDRESS TO THE 0 204 4 411000 00000000 1 000000 50 CONTROL REGISTERS DEFINITIONS eee eise esseseeesmenn etna tn smetnetn atn a nsn natn 51 MESSAGE COUNTER 7EBC 7EBE 51 FIRMWARE DATE CODE 7ECO H 2
31. VED set to 0 BOARD HALTED 0 BOARD RUNNING SCS 779 Bit 04 Board Halted is set by the board after the user stops the current operation by resetting the START bit within the Start Register The user should check this bit first before modifying registers which first require a STOP operation The board resets this bit after receiving a subsequent START command by writing to the Start Register BOARD ID REGISTER 7ED4 H FEDA H This register contains a fixed value which can be read by a user s initialization routine to detect the presence of the 09 card The one word value of this register is 4939 Hex ASCII BOARD CONFIGURATION REGISTER 7ED6 H FED6 H The operating mode of the board is set via this register This register must be set before issuing a START to the board To modify this register issue a STOP modify and then re issue a START see START Register 002 CONCURRENT PU BM SEQUENTIAL BLOCK MODE OTHERS RESERVED 53 EXC H009VME M SOFTWARE RESET REGISTER 7F80 H FF80 H Writing to this location will RESET the CCC PU MON or the Conc Monitor section The section that is been reset will act as if POWER had been switched off and then on The data field is ignored NOTE RESET ERASES ALL MEMORY LOCATIONS WITHIN THE DUAL PORT RAM The Board Status the Board ID Firmware Revision and V
32. ariable Amplitude registers are written by the board after the reset operation has been completed 54 GLOBAL REGISTERS These registers may be accessed at all times regardless of the current MODE BOARD RESET REGISTER 7 90 WRITE ONLY Writing to this register will reset the both sections of the board CCC PU MON and CONC MON at the same time CONCURRENT START REGISTER 7F94 H FF94 H WRITE ONLY These registers allow the user to start the operation of the PU CCC Concurrent PU or Non Concurrent Monitor at the SAME TIME as the Concurrent Monitor This allows for synchronization of these two sections of the board The dual port RAM s normal Start Registers must have their START bits set to a logic 0 when using this register To stop the selected operation s follow the normal procedure as described in the Start Register sections Writing to one of these registers starts the Concurrent Start operation SWITCHING MODES OF OPERATION The user can switch between modes of operation e g between CCC and Peripheral Unit by HALTING the operation of the board VIA THE START REGISTER modify the Configuration Register setup the memory as required and then set the START bit within the Start Register 55 EXC H009VME M CARD LAYOUT T B D LEDS The individual functions of the front panel leds are listed below MODID LD1 Reflects the state of the MODID pin on the VXI bus JP4 must be ins
33. ck The Instruction Stack is divided into instruction blocks each containing four words Each instruction block corresponds to a single H009 message The block contains control information written by the user and status information written by the board The figure below illustrates one instruction block The user may define several Instruction Stacks simultaneously The Instruction Stack Pointer is used to select the current stack 1 the stack that will be run upon issuing Start command Jump instructions allow the user to jump from stack to stack in real time 27 EXC H009VME M Message Status The Message Status Word indicates the status of the message transfer This word is created by the board and written at the end of each message The contents of the message status word become valid when the End of Message bit is set The user should zero out this bit after reading the message status word or set one of the 0 bits in order to recognize the next time a message comes in All error values refer to data received in a PU to CCC transfer Message Status Word Definitions Bit 15 14 09 10 09 08 07 06 05 04 03 02 01 00 Message Message Complete RESERVED Bad Mode Error Wrong Bus Error Word Cnt Hi Error Word Cnt Lo Error Gap Time Error RESERVED Manchester Error Parity Error Bit Count Hi Error Bit Count Lo Error ERROR Meaning Indicates that the message transfer
34. d and T R bit are used to index into the user programmed look up table Each entry in the table represents the address of the buffer from to which data is to be sent stored UNIT ADDRESS CONTROL FIELD 11 bits of the 009 Select Word top 6600 1111 111111 1 LOOK UP TABLE 2K x 16 POINTER DATA WORD 1 POINTER DATA BLOCK bottom 6600 0000 000000 0 HOW CREATE THE ADDRESS THE TABLE 1 Isolate the ELEVEN relevant bits of the 009 Select Word PU Address Control Field and T R Field Example Allocate a data block for 009 Receive message to PU 5 CF 3 PU Address 5 Control field 3 T R field 0 2 Add this value to the base address of the Look Up Table 6600H 6600 H 50C H 6BOC H 3 Write the Data Pointer to this location NOTE The Command indicator bit is not used in this calculation Since each entry in the table takes up two bytes an additional 0 is added to the end of the address 16 EXC H009VME M MESSAGE STACK 7600 7DFE H The EXC H009VME M generates a Message Stack within the dual port memory This stack contains information which can be utilized by the user for post processing of the Peripheral Unit messages The stack is divided into 256 blocks each containing four 16 bit words The stack operates as a Circular Buffer The Message Stack Pointer points to the beginning of the next unused block Only ACTIVE PU messages are stored The figure below illustrat
35. e CCC When NO error is selected see Control Word this register is ignored The resolution of the register 1 microsecond per bit This time is measured as the DEAD TIME on the H009 bus The default period gap is 5 microseconds The actual gap will be 4 microseconds greater than the number written to this field To request an gap of 6 microseconds write a 2 to this field Gaps less than 5 microseconds are not supported Gaps greater than 8 microseconds will be interpreted as separate messages by a PU LOOP COUNT REGISTER 7EBE H This register is used in conjunction with the Loop Bit in the Start Register If that bit is set the user sets this register to specify the number of times 1 to 65535 the Message Frame will be transmitted A value of zero is interpreted as a request for continuous looping This register must be set before issuing a START to the board To modify this register issue a STOP modify and then re issue a START see START Register FIRMWARE DATE CODE 7ECO H This register indicates the date of release of the firmware revision level written in the Firmware Revision Code The lower nibble is the year The offset is year 1990 The value written in this field is added to the offset This field can reach year 2005 The next higher nibble is the month It s value is written in HEX The upper Byte is the day of the month It s value is also in HEX Bit Function 15 8 Day 7 4 Month 3 0 Year Example For a revision date of
36. e Frame Time Counter is 4usec After the execution of all instructions 1 frame the EXC H009VME M will wait until the internal Frame Time Counter reaches ZERO before re transmitting the next frame NOTE Ifthe Frame time is less than the time required to transmit all messages within 1 frame the subsequent frames will be transmitted with a minimal delay between them 37 EXC H009VME M CONTROL REGISTER DEFINITIONS INSTRUCTION COUNTER 7EB2 H The Instruction Counter is loaded with the number of instructions HO09 Messages to execute in the current frame The value must be greater than 0 before beginning transmission by writing to the START REGISTER Load 1 for one message 2 for two messages etc The EXC H009VME M updates this register by decrementing the value and writing it back to the memory This register must be set before issuing a START to the board This register is decremented and updated by the board at the end of each message transfer To modify this register issue a STOP modify and then re issue a START see START Register When in the loop mode this register cycles from the initial value to 0 Following the transmission of the last message in the loop the Instruction counter is set to O for the duration of the frame time Just prior to transmitting the first message of the next loop the Instruction Counter is set to its initial value FRAME TIME REGISTERS HI amp LO 7EB4 gt 7EB6 H These register
37. e Time Tag implementation utilizes a 32 bit free running counter with a resolution of 4 msec per bit The Time Tag counter can be reset by the user to 0 any time by writing to the Time Tag Reset Register see Control Register Definitions sections NOTE 1 The user can read the counter s value any time at the Time Tag Counter addresses see Control Register Definitions section 2 The counter can also be clocked and or reset from an external source see Connectors section 49 EXC H009VME M FILTER FUNCTION TABLE 6EO00 H gt 7DFF H gt FDFF H The Filter Function table is a byte wide table indexed by the upper 12 bits of the select word UNIT ADDRESS CONTROL FIELD 12 hi bits of the 009 Select Word 6 00 1111 1 111111 1 ENTRY 4095 FILTER TABLE 4k x8 6E00 0000 000000 1 ENTRY 1 6E00 0000 0 000000 0 ENTRY 0 bottom HOW TO CREATE THE ADDRESS TO THE TABLE 1 Isolate the twelve relevant bits of the 009 Select Word PU Address CI Control Field and T R Field Example Select filter entry for a H009 Receive message to PU 5 CF 3 PU Address 5 cl 0 Control field 3 T R field 0 The Hex representation 506 H 2 Add this value to the base address of the Filter Function Table 6E00H 6E00 H 506 H 7306 50 EXC H009VME M FILTER FUNCTION TABLE ENTRY BIT FUNCTION DESCRIPTION ON ERROR 1 Stop Monitoring if message contains an
38. e driven active when the card generates an interrupt Refer to section Using Interrupts on VME in following MODID Indicates the inverted value of the VXI bus MODID line A24 A32 ENABLE Writing a 1 to this bit enables access to the card s H009 Storage Area and Control Registers residing in A24 or A32 VME address space If this bit is set to 0 none of the on card registers and memory which are resident in the 24 or A32 address space may be accessed The Configuration registers of course remain accessible regardless of the state of this bit as they reside in the A16 address space of the card NOTE 1 The user must not write 0 into the RESET bit for at least 100 usec after writing a 1 into it While in the RESET state the card is completely inactive and will not respond to any commands Upon releasing the card from the RESET state write 0 to this bit the card will perform its self test routines The card may also be reset via the Software Reset Registers defined within the main body of this manual This second method is the preferred mechanism for resetting the card 2 The following table shows the relationship between IRQSEL2 0 and IRQT 1 SELECTED IRQ LINE IRQSEL2 IRQSEL1 IRQSELO NONE o 4 e IRQ1 IRQ2 IRQ3 IRQ5 IRQe IRQ7 IRQ4 EXC H009VME M Using Interrupts on VME The Interrupt generated on the selected IRQ line is the logical OR of all interrupt generating sources on
39. ed with the JUMP command has no effect The Memory Location Sequence is illustrated below INSTRUCTION COUNT 3rd word STACK POINTER 2nd word CONTROL WORD 1st word 32 EXC H009VME M MESSAGE BLOCK FORMATS The Message Block contains or will contain the entire 009 message as it appears on the 009 bus including Select Word s and Data Word s where applicable EXAMPLE 1 Before executing Transmit command operating as CCC only 009 Transit command Control word First location of block After executing Transmit command operating as CCC only H009 Data word From transmitting peripheral unit not simulated H009 Data word H009 Data word From transmitting peripheral unit not simulated 009 Transmit command Control word First location in block 33 EXC H009VME M EXAMPLE NO 2 Before executing Receive command H009 Data word First location of block After executing Transmit command H009 Data word First location of block Since all traffic in CCC gt PU commands is in one direction The before and after are the same 34 EXC H009VME M EXAMPLE NO 3 PERIPHERAL UNIT SIMULATION In the case where the board is simulating both the Bus Controller and one or more Peripheral Units the user must write into the Message Block the simulated Peripheral Unit 009 DATA word s in the sequence in which they are to appear over the 009 bus see MESSAGE BLOCK FORMATS The user
40. error ERROR 0 Continue even following error INTERRUPT NO INTERRUPT 1 Generate interrupt when message is received STOP NO STOP 1 Stop monitoring following receipt of message STORE NO STORE 1 Don t store this EN 0 Store this message NOTE 1 Interrupts are generated at the end of the message 2 If the NO STORE bit is set the other bits are ignored CONTROL REGISTERS DEFINITIONS MESSAGE COUNTER FEBC This register is set to 0 following START It is incremented by one every time a message is recorded by the monitor Messages which are not stored due to NO STORE entries in the Filter Function table are not included in the count FIRMWARE DATE CODE 7 FECO H This register indicates the date of release of the firmware revision level written in the Firmware Revision Code The lower nibble is the year The offset is year 1990 The value written in this field is added to the offset This field can reach year 2005 The next higher nibble is the month It s value is written in HEX The upper Byte is the day of the month It s value is also in HEX se ow MONTH EXAMPLE For a revision date of 22 10 95 30 YEAR Write 16A5 H to the register 51 EXC H009VME M FIRMWARE REVISION REGISTER 7EC2 H FEC2 H This register indicates the revision level of the on board firmware The value 0100 H would be read as revision level 1 00 CURRENT B
41. es one instruction block Message Status Word Definitions The Message Status Word indicates the status of the message transfer This word is created by the Board The contents of the Message Status word are shown below BIT FUNCTION DESCRIPTION 15 End of Message Indicates that the message transfer has been completed Indicates on which bus the message was transferred 1 BUS B 0 BUS A 9 13 RESERVED Set to logic 0 Word Count Error Indicates that more words were received than were described within the select word s word count 7 Low Word Count Error Indicates that fewer words were received than were described within the select word s word count a Error from 5 microseconds 775 e ccc Response cates no cock signal was deeded onthe 774 MancestrEror cates thata bitwin egat Manchester e Peme rcas ata data wora wih even party was caved Indicates the occurrence of an error defined within one of the other message status bit locations 17 EXC H009VME M TIME TAG Read by user The Time Tag value is 32 bit word which may be used to determine the time elapsed since START or to determine the time between the H009 messages The Time Tag implementation utilizes a 32 bit free running counter with a resolution of 4 usec per bit The Time Tag counter can be reset by the user to 0 any time by writing to the Time Tag Reset Register
42. esponses by returning the Select Word back to the CCC When the Command Response Error Bit is set in the appropriate register in the Error Injection Table the specific PU does not send back the last SELECT word but the word written in the COMMAND RESPONSE TABLE This table contains 16 WORDS one per Peripheral Unit The first word relates to PU 0 the second to PU 1 while the last location relates to PU 15 PU 15 7EBE H PU 0 7E60 H eo EXC H009VME M FIRMWARE DATE CODE 7ECO H This register indicates the date of release of the firmware revision level written in the Firmware Revision Code The lower nibble is the year The offset is year 1990 The value written in this field is added to the offset This field can reach year 2005 The next higher nibble is the month It s value is written in HEX The upper Byte is the day of the month It s value is also in HEX we ow pes Example For a revision date of 22 10 95 the register will contain 16A5 H FIRMWARE REVISION REGISTER 7EC2 H This register indicates the revision level of the on board firmware The value 0100 H would be read as revision level 1 00 MESSAGE STACK POINTER 7EC4 H The Stack Pointer indicates the position within the Message Stack area where the next message is to be recorded This pointer is updated incremented by 8 after an entire message has been received This word circulates within the Message Stack between 7600 H to 7DF8 H It is in
43. gister within the VME V XI Configuration Registers The 32K Words occupied by the H009VME V XI are divided into two blocks of 16K Words the first one 0000H to 7FFFH for the main CCC PU Monitor section and the other one 8000H to FFFFH for the Concurrent Monitor section 009 MEMORY MAP RESERVED FF96 H to FFFE H CONCURRENT MON RESET FF80 H REGISTER MEMORY AND CONTROL 8000H to FF7E H REGISTERS 16K x 16 RESERVED 7F96 H to 7FFE H 7F82 CCC PU MON RESET REGISTER 7F80 H MEMORY AND CONTROL 0000 to 7F7E H REGISTERS 16K x 16 13 EXC H009VME M PU OPERATION The EXC H009VME M can be configured to simulate up to 16 Peripheral Units The user selects which terminal s are operating ACTIVE The EXC H009VME M handles all message transfers subsequent to receiving a START command see Control Registers In addition errors can be injected into the message responses The PU data transfers operates via 2Kx16 Look Up Table which points to the exact data words The user loads the H009 data blocks with transmit data and reads the received H009 data from the pre assigned memory The user can specify whether or not the Peripheral Unit should retransmit the select word upon receiving a select word with the command indicator set or send a different user selectable word in its place The Peripheral Unit transmits its data words in 5 usec measured as dead time on the bus a value which can be altered via the PU Period
44. ility Slave Address A16 amp A24 A32 Bit Count Data D16 Word Count Interrupt D08 O ROAK Period Dat E Parity Memory Mapped Dual Port Error Detection Capability No Clock on Active Bus Manchester Error Parity Error Bit Count High Bit Count Low Word Count High Word Count Low 16k x 16 32k x 16 with Concurrent Monitor Option Easy to Install and Operate C Software Library Included Extensive Interrupt Features Real Time Operation 32 Bit Time Tagging in PU Mode EXC H009VME M INSTALLATION Before installing the card it is very important to determine which 64 byte section of A16 address space is available for the card s VME VXI Configuration Registers When this is determined the SW5 dip switch should be set accordingly see Dip Switch Settings section The user should also decide if A24 or A32 address space is to be used and set the appropriate jumper JP1 see Jumpers section Once all the jumpers are set properly make certain the computer is turned off and insert the card into any available slot Once the card is installed the 009 twinax cables should be attached to the card and to the bus The cables may be connected and disconnected to the card while power to the computer is turned on but not while the card is transmitting over the bus H009 BUS CONNECTIONS Direct coupling must be used to connect the EXC H009VME M to another H009 device Switches 1 amp 2 in dip switches SW1 SW
45. instructs the board as to which Peripheral Units are to be simulated by writing to the 16 word Active Peripheral Unit Table Each entry within the 16 word table relates to a specific Peripheral Unit The first location relates to PU 00 while the last location relates to PU 15 for a total of 16 locations Writing a value 0001 to the table entry ENABLES the Peripheral Unit simulation by the board A value of 0000 written to the table disables the simulation by the board 15 ACTIVE PU WORD 7EAE H PU 14 ACTIVE PU WORD 0 ACTIVE PU WORD 7E90 H ACTIVE Peripheral Unit WORD DEFINITION Bit Function 15 1 Not in use set to 0 0 1 Enabled 0 Disabled 35 EXC HOO9VME M Before executing Transmit command operating as both CCC and PU 009 Data word Peripheral Unit Data Simulated by the 009 009 Data word 009 Data word 009 Transmit command First location of block After executing Transmit command operating as both CCC and PU 009 Data word 009 Data word 009 Data word 009 Receive command First location of block In this example all data is being sent by the board From a system point of view the select word is sent as part of the CCC function and the data is sent as part of the PU function 36 EXC H009VME M CONTINUOUS OR ONE SHOT MESSAGE TRANSFERS The EXC H009VME M offers the capability of transferring all programmed messages once in a continuous lo
46. is 16 bit read write register defines the base address of the card s A24 or A32 memory and registers If A24 addressing is used the 8 most significant bits of the Offset register are the values of the 8 most significant bits of the card s memory and register addresses and the 8 least significant bits of the register are not used If A32 addressing is used the Offset register represents the 16 most significant bits of the card s memory and register addresses Thus the Offset register bits 15 through 8 map to the address lines A23 through 16 for the A24 Address Space and the Offset register bits 15 trough 0 map to address lines A31 through A16 for the A32 Address Space A24 ADDRESSING EXAMPLE Required base address 18 0000 H Write 18XX H to Offset register OFFSET BIT VALUE ADDRESS LINE FUNCTION re emm EXC H009VME M A32 ADDRESSING EXAMPLE Required base address FF38 0000 Write FF38 H to Offset register OFFSET BIT VALUE ADDRESS LINE FUNCTION Vector 0 Vector 1 Register amp VME BASE 20 H 22 H Read Write In the case of an interrupt generated by CCC PU or the Con Monitor section the 8 least significant bits of this 16 bit register known as the STATUS ID are used as the interrupt vector during the ensuing interrupt acknowledge cycle The is D08 O INTERRUPTER and as a result will place these 8 bits on lines DOO D07 of the VME bus during the interrupt acknowledge cycle Refer
47. itialized to 7600 VARIABLE DATA AMPLITUDE REGISTER 7EC6 H This register specifies the amplitude of the 009 data output signal The signal can be programmed from 0 volts up to 15 volts p p measured on the 009 bus with 175 ohm load A higher Transmit output amplitude will appear on the 009 bus if 68 ohm termination resistors are used The register has a resolution of 60mv bit p p on the bus In general the accuracy of the measured signal depends on the accuracy of the components involved termination and isolation resistors transformers transceivers etc Therefore a difference may be encountered between two different boards or the same board on two different buses This register must be set before issuing a START to the board To modify this register issue a STOP modify and then re issue a START see START Register This Register defaults to FFH after Reset providing maximum amplitude 21 EXC H009VME M MESSAGE STATUS REGISTER 7ECE H This register indicates that a 009 message has been received The figure below illustrates the placement of the status bit A logic 1 indicates active condition bit is also set for messages with errors BIT FUNCTION 154 NOT IN USE SET TO 0 MESSAGE COMPLETE NOTE Message Complete bit is NOT reset by the board and should be reset by the user after reading it START REGISTER 7EDO H This register controls the START STOP operation of the EXC H009V
48. op or for N number of times In the One Shot mode the board transfers all messages after receipt of a START command sets the Message Complete Bit within the Message Status Register issues an Interrupt if programmed and waits for a new START This mode is selected via the Start Register see Start Register definition In the N Times Mode the user loads the Loop Count Register with the number of times to transmit the messages frame and sets the LOOP and START bits within the Start Register The user can select to transmit from one to 255 times see Start and Loop Count Registers The time between frames is predetermined via Frame Time Register see below In the Continuous mode the EXC H009VME M will re transmit the message frame at a predetermined user programmable rate This mode is selected via the Start Register and the Loop Count Register see Register definitions In this mode all messages relating to the active Stack Pointer and Instruction Counter are continuously looped until the user halts the board s operation see Start Register definition The loop time or Frame Time is a function of the two Word Frame Time Registers Hi and Lo The internal Frame Time counter is loaded upon receipt of a START command with the 32 bit value found within the Frame Time Registers Hi and Lo The Frame Time counter is decremented every N x 4 usec where N is the value of Frame Time Registers Hi and Lo The resolution of th
49. perfect solution for developing and testing H009 interfaces and for performing system simulation of the MIL STD H009 bus The user has direct access to all control registers and data blocks and can modify various parameters and data in Real Time The user controls the operation of the card by accessing the memory mapped control registers The EXC H009VMB M contains a 16k X 16 true dual ported RAM for data blocks control registers and look up tables and another 16k X 16 Dual Port Ram for a Concurrent Monitor option The base board has three modes of operation Peripheral Unit Multiple up to 16 PU s CCC with Concurrent PU operation 0 up to 16 PU s and Bus Monitor Mode The Monitor section contains a Concurrent Bus Monitor that works separately from the other section Error injection capability exists in both the PU and CCC Concurrent PU modes e VME interrupts are available e Variable amplitude transceiver for both data and clock outputs e 32 bit Hardware Time Tag circuit for use within PU and Monitor modes The 9 board features include Operates as Separately Selectable Variable Amplitude for CCC Central Control Complex Clock and Data PU Peripheral Unit Compatible with VME amp VXI Systems Concurrent Monitor Option and C Size Cards Multiple PU Simulation e 16 Bit Data Transfers Up to 16 Peripheral Units VME VXI Compliance e Error Injection Capab
50. s contain the 32 bit Frame Time Value for Continuous and N times Modes Operation The resolution of this register is 1 usec This register must be set before issuing a START to the board To modify this register issue a STOP modify and then re issue a START see START Register 38 EXC H009VME M WORD COUNT REGISTER 7EB8 H This register controls the number of H009 data words within the message When NO error is selected see Control Word this register is ignored and the number of words sent is determined by the select word When a word count error is selected the number of words sent is the number of words in the select word the number written to this register WORD COUNT ERROR WORD DEFINITION Offset Table Value 3 words FFFD H 2 words FFFE H 1 word FFFF H no error injection 0000 H 1 word 0001 H 2 words 0002 H 3 words 0003 H BIT COUNT REGISTER 7EBA H Sets the number of total bits within the 009 Data words including parity When NO error is selected see Control Word this register is ignored 17 bit word including parity is selected BIT COUNT ERROR WORD DEFINITION No Bits Sent Offset Table Value 14 3 bits 0006 H 15 2 bits 0005 H 16 1 bit 0004 H 17 no error injection 0003 H 18 1 bit 0002 H 19 2 bits 0001 H 20 3 bits 0000 H 39 PERIOD DATA GAP REGISTER 7EBC H This register sets the DEAD TIME between Data Words sent from th
51. s manual as Monitor NOTE The user should use the following sequence to determine whether the board is installed AND ready to operate Check the Board ID register test for value 4939 Hex Check Board Status Register test for Board Ready bit 1 The board is installed and ready when BOTH of these registers contain the correct values as written above This sequence should be used after power on and software reset operations For Software Reset operations these values should be set to ZERO by the user immediately prior to writing to the software Board Reset Register 45 EXC H009VME M MONITOR MEMORY MAP TIME TAG OPTIONS 7F8A rece reco MESSAGE BLOCK AREA 0000 to 65FE H 586 BLOCKS 46 CONCURRENT MONITOR MEMORY MAP TIME TAG OPTIONS FF8A H recat 2 MESSAGE BLOCK AREA 8000 to ESFE 586 BLOCKS 47 BUS MONITOR MESSAGE BLOCK The figure below illustrates the contents of a Message Block Each block takes up 24 words 48 bytes so that the first block begins at address 0 the second at 0030 H and so on with the final block beginning at 6DBO H In Conc Mon 8000 H for the first and EDBO H for the final block WORD 23 RESERVED 9 DATA WORD 15 48 EXC H009VME M MESSAGE STATUS WORD The Message Status Word indicates the status of the message transfer This word is created by the Board The contents of the
52. s write a 4 to this field Message Block Pointer Written by user The Message Block Pointer is a sixteen bit word which points to the beginning of a H009 Message Block Like all on board pointers it is actually a byte index into the board The Message Block may be located anywhere within the Instruction Stack and Message Block Area section of the board Instruction Stack 29 EXC H009VME M MESSAGE BLOCK The user loads the Message Block anywhere within the Instruction Stack Message Block Area see Memory Map Message Blocks do NOT have to be stored in sequential locations within the memory since the Message Block Pointers point to the Message Blocks in sequence CONTROL WORD Each block contains a 009 message plus its Control Word This Control Word is written into the FIRST word of each block The Control Word provides the EXC H009VME M with additional information about the message to be transmitted The size of the message block is not fixed and is dependent upon the size of the message itself The description of each bit within the Control Word follows 30 Control Word Definitions Bit 15 14 13 12 11 10 09 08 07 06 05 04 03 00 Message Stop on Error Parity Error Halt Continue Word Count Error Bit Count Error RESERVED Period Data Gap Error Placement Channel Auto Bus Switch Auto Retry Code Code Command Code EXC H009VME M Meaning
53. t first before modifying registers which first require a STOP operation The board resets this bit after receiving a subsequent START command by writing to the Start Register BOARD ID REGISTER 7ED4 H This register contains a fixed value which can be read by a user s initialization routine to detect the presence of the EXC HO09VME M card The one word value of this register is 4939 Hex ASCII H9 BOARD CONFIGURATION REGISTER 7ED6 H The operating mode of the board is set via this register This register must be set before issuing a START to the board To modify this register issue a STOP modify and then re issue a START see START Register 002 CONCURRENT PU SEQUENTIAL BLOCK MODE OTHERS RESERVED 43 EXC H009VME M CLOCK SKEW REGISTER 7EDA H Writing to this location will alter the synchronization of the data sent by the CCC with respect to the clock signal that is also sent from the CCC The default value of 6 results in complete synchronization Higher numbers delay the data by approximately 25 nanoseconds per bit Lower numbers cause the data to be sent earlier Valid values are from to 15 This register takes effect only when the board is turned off To alter the value write a 0 to the START register check the Board Status Register to make sure it is off alter the value of the Clock Skew Register and then write 1 to the START register This feature can be used in the CCC Mode for
54. talled This LED has no function in a VME system READY LD2 Indicates that the card is ready to receive commands Reflects the state of the bit of the same name in the Configuration Status Register CCC LD3 Reflects that the CCC mode is active at this moment PU LD4 Reflects that the PU mode is active at this moment MON LD5 Reflects that the Non Concurrent Monitor mode is active at this moment BUSA LD2 Reflects that the H009 Bus A is active at this moment BUSB LD3 Reflects that the 009 Bus B is active at this moment CMON LD4 Reflects that the Concurrent Monitor mode is active at this moment 56 EXC H009VME M DIP SWITCH SETTINGS The EXC H009VME VXI card contains 1 Dip Switch which controls the Logical Address of the card The lines A15 amp A14 are set by default to 1 logic The 2 Factory Jumpers A14 and JP2 15 disconnected Card Logical Address Dip Switch Setting SW5 Dip switch SWS is used to select the card s Logical Address as described in the section VME VXI Configuration Registers The Logical Address is set as shown below MSB LSB o swan swsa suse suus sus swse A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 Switch ON or Closed logic 0 at bit position Switch OFF or OPEN logic 1 at bit position NOTE Address lines 15 A14 are always decoded as 1 Example For a Logical Address of CO H A16 address F000H set positions l and
55. the card An interrupt which was generated by the CCC PU section of the card will result in the interrupt routine whose vector resides in VECTOR O0 register to be executed The card will place the value in the VECTOR 0 register called the STATUS ID onto the VME data lines when issuing the interrupt acknowledge cycle The user s processor will use this value to determine which entry in the user s interrupt vector table to jump to Within this interrupt routine the actual source of the interrupt can be determined by polling the Pending Interrupt Register Likewise an interrupt which was generated by the Concurrent Bus Monitor will result in the interrupt routine whose vector resides in register to be executed If case of multiple pending interrupt requests the highest priority request STATUS ID will appear first After the user services this interrupt a second interrupt will be generated for the next pending interrupt The priorities are defined as follows Request name Priority Module 0 Request Highest Module 1 Request Module 2 Request Module 3 Request Module 4 Request Module 5 Request Module 6 Request Module 7 Request Lowest For all interrupts the serviced interrupt request is cleared automatically at the end of the interrupt acknowledge cycle This method is referred to within the VME specification as ROAK Release On AcKnowledge EXC H009VME M Offset Register amp VME BASE 06 Read Write Th
56. to section Using Interrupts on VME The 8 most significant bits of this register are don t care OFFSET BIT FUNCTION 7 0 STATUS ID 10 EXC H009VME M DIVIDER VXI amp BASE 24 H Read Write This register allows the user to input an external Clock to the 32 Bit Time Tag This register contains a divider of the 16Mhz VME System Clock The clock generated can be the source of the Time Tag Clock See Time Tag Options Register The description of this register is as following BIT FUNCTION 7 0 TTAG DIVIDER The divider s equation is as following 16M hz 2n 2 nis the current DIVIDER value Example For Div Value of 4 16Mhz 10 1 6 Mhz Reserved Register VXI amp VME BASE 26 H to 30 H Read Write These registers are reserved for future uses MEMORY REGISTERS ADDRESS MAPPING DIAGRAM Area and Control Registers On Board FFFF CARD CONFIGURATION REGISTERS Memory and Registers BLOCK RESERVED REGISTERS 24 to 0000 H 30H VECTOR 1 REGISTER 22H A24 A32 ADDRESS SPACE 16 ADDRESS SPACE I O Logical Address Dip Switch SW5 11 EXC H009VME M A16 ADDRESSING EXAMPLE Given Required configuration registers base address E000 H Then Set dip switch SW5 to LOGICAL ADDRESS 80 H 12 EXC H009VME M GENERAL MEMORY MAP The board occupies 32Kx16 of the VME A24 or A32 address space which are mapped via the Offset Re
57. tral Tap Gnd Connection 59 8 59 FACTORY DEFAULT JUMPER 60 Factory Jumpers Setup for 60 Factory Jumpers Setup for i aa aa 60 TERMINATION RBESISTORIS cunc reagent aucun ot casae 60 CONNECT ORS c 61 1553 CONNECTORS ssis ieissar 61 IN SYSTEM PROGRAMMABLE 5 2 0 1111111 tns 61 VME INTERFACE CONNECTOORG cc cccceceesseeseenseneesseceneensesseeneeneenseaeseeneeneenssaeneeneenesaeseeneeneeassaeseeanend 61 PI 2 62 Connector R2 PIDOUbs sn ont Silesia te pte nente 63 POWER REQUIREMENTS 5 conscia 64 ORDERING INFORMAT I ON 52 52 2 01 45 cruda nca n acra eus nicus cu cad acaxz auos cuan ceat 64 EXC H009VME M INTRODUCTION The EXC H009VME M is a memory mapped H009 interface card which operates for VME VXI systems The H009 is the
58. with the appropriate bit set begins the Bus Controller transfer operation When operating in the Loop or N Times mode the user must set the Start and Loop bits within this register The loop and N times number is selected via the Loop Count Register In the One Shot and N Times modes the board RESETS the Start bit within the register after ALL messages have been transferred The board does not reset any bit while in the Continuous Loop mode Write 0 to bit 0 to halt the LOOP operation between messages Write instead a 0 to bit 1 in order to halt the operation at the end of the entire frame this bit is not tested between message transfers See the related bit data bit 04 within the Board Status Register which indicates when the board has been halted Bit Function 15 2 Not used Set to 0 1 1 Loop mode 0 One shot mode 0 1 Start 0 Stop 42 EXC H009VME M BOARD STATUS REGISTER 7ED2 H This register indicates the status of the EXC HO09VME M card In addition this register indicates option selection as defined below Status bits are active 1 The upper bits b15 b5 should be set to O Bit Function 15 5 Not used Set to 0 4 1 Board halted 0 Board running Self test ok 2 RESERVED 1 RAM ok 0 Board ready Bit 04 Board Halted is set by the board after the user stops the current operation by resetting the START bit within the Start Register The user should check this bi
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