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ATCA-9305 User`s Manual - Artesyn Embedded Technologies

1. 0000 BER Polar K Al al O m m 8800 BE Em mrs fr m 5 24 pin ATCA g Bo 000 m 0 0 SUL conecto SPI XAUI 9 m A Bridge of 00 0 1 00 Som D m m 38888 591 B 3555 80 015 8585 Zone 3 Brid 5 5585 ege hemes g 80 AERE E 888 2 8 J3 E J4 E 25 856 Connector 280 soe 8 E BE 8853 5
2. 54 ATCA 9305 User s Manual 10009109 07 Setup Figure 2 6 Component Map Bottom PCB Rev 2 x E p pa a D e e e 5 E 8 o o 0 5 E 5 0 o O 082 081 00 000000000 Ag 8 143 P s BE e e po 18 IM 7 a e 000 00000 0000 m Fi E 8 8 poo 0 E p ai E 0 moog gooo u U79 078 of B rg f E tn obm 0000 won www BL mmo og se H B eon e all mise Voss 0 9 0 E B o 158 Ve o 5 rs 4 pum 077 ure H 8 E E 2 B8 E ow trataFlas 88 mom 8 158 fe ose 075 0000 ifi E 8 E NAND PES Bomegpen 074 1073 2 i
3. 105 5 1 1 Product en Rn 106 5 1 2 Hardware 4 24 24 42 107 5 1 3 PLD Version ee 108 5 1 4 2 2 24 24 24 4 2 108 5 1 5 Hardware Configuration 0 2 24 2 109 5 1 6 Jamper bik ee a u 109 5 1 7 MS 110 5 1 8 Reset Weft Eee 111 5 1 9 Reset COMMAN 1 2 4 4 112 5 1 10 Reset Command 2 2 2 4 24 4 112 5 1 11 Reset Command 3 u 113 5 1 12 4 2 4 4 2 114 5 1 13 Reset Command 5 an e e 114 5 1 14 Reset Command Sticky 1 2 4 115 5 1 15 Reset Command Sticky 2 116 5 1 16 Boot Device Redirection 116 5 1 17 Miscellaneous 0 117 5 1 18 Low Frequency Timer 1 2 2 118 5 1 19 RTM GPlO State ss a ERE T Pu 119 5 1 20
4. 24 2 72 3 2 2 ON ee 73 2 3 75 3 4 76 3 4 1 Start up Display 76 3 4 2 Power up Reset Sequence 7 77 3 4 3 Diagnostic Tests During Power up and 79 3 4 31 POST Diagnostic Results 79 3 4 4 Environment Variables 2 79 85 ol Cr BR Sk ee De 81 3 51 IDDR2 SDRAM ea 81 3 5 2 RLDRAM en bau 82 3 5 3 82 3 5 4 Flash 512 82 3 5 5 Flash MBX 16 weenie ee E ee eR e ene 82 3 6 StratixGX Intereonnedt ee ee ER RENE cen 83 3 6 1 PED Registers ae ame ke ed ie re 83 3 6 1 1 Data Redgisters 83 3 6 1 2 Address Registers 85 3 6 1 3 Control Register 2 24 2 2 86 3 6 1 4 Version Registern 87 3 6
5. 176 Table 7 23 Set Hardware Address Command 176 Table 7 24 Get Handle Switch Command 177 Table 7 25 Set Handle Switch 177 Table 7 26 Get Payload Communication Time Out Command 178 Table 7 27 Set Payload Communication Time Out Command 179 Table 7 28 Enable Payload Control Command 179 Table 7 29 Disable Payload Control 180 Table 7 30 Reset Command 4 180 Table 7 31 Hang IPMC Command 2 2 22 181 Table 7 32 Bused Resource 2 182 Table 7 33 Bused Resource Status 184 Table 7 34 Graceful Reset Command 2 2 185 Table 7 35 Diagnostic Interrupt 186 Table 7 36 Get Payload Shutdown Time Out Command 187 Table 7 37 Set Payload Shutdown
6. 40 Figure 1 2 Declaration 43 Figure 2 1 9305 Front Panel PCB Rev 1 49 Figure 2 2 ATCA 9305 Front Panel 2 50 Figure 2 3 Component Top Rev 1 52 Figure 2 4 Component Top PCB Rev 2 53 Figure 2 5 Component Map Bottom PCB 1 54 Figure 2 6 Component Map Bottom PCB 2 55 Figure 2 7 LED Fuse and Switch Locations PCB Rev 1 x 56 Figure 2 8 LED Fuse and Switch Locations Top PCB Rev 2 57 Figure 2 9 LED and Switch Locations Bottom PCB Rev 1 58 Figure 2 10 LED and Switch Locations Bottom PCB Rev 2 59 Figure 2 11 Configuration 9 2 2 2 61 Figure 2 12 Air Flow Graph erre hu rr CERE oo uae RYAN EUER 64 Figure 2 13 Critical Temperature Spots 65 Figure 2 14 Serial Number and Product ID on 68 Figure 3 1 Processor Complex Block Diagram
7. 154 7 9 5 Set Watchdog Timer Command 154 7 9 6 Get Watchdog Timer 2 2 157 7 10 een 159 7 10 1 Get FRU LED Properties 160 7 10 2 Get LED Color Capabilities 161 7 10 3 Set FRU LED State 163 7 10 4 Get FRU LED State 164 411 Vendor Commands 167 7151 PE 168 7 11 2 Get Serial Interface Properties 172 7 11 3 Set Serial Interface 0 173 7 11 4 Get Debug 0 hh e 174 11 5 Set Debug LOVE er per a EN EM Ad 175 7 11 6 Get Hardware 4 5 2 22 176 7 11 7 Set Hardware Address 176 7 11 8 Get Handle Switch 2 177 7 11 9 Set Handle Switch een en 177 7 11 10Get Payload Communication eee ene nennen 178 7 11 11Set Payload Communication
8. m SWI IPMC Reset ES 75 Amp Fuse IPMP State CR35 STATE_LED8 CR36 STATE _LED7 CR37 STATE_LED6 CR38 STATE LED5 CR39 STATE LED4 STATE LED3 942 STATE LED2 CR42 STATE LEDT CR43 STATE LEDO CR8 MIP4_LED4_R Fee 2 75 Amp Fuse 2 CR9 MIP3_LED1_R CRIO MIP3_LED2_R CR11 MIP3_LED3_R po CR12 MIP3_LED4_R 0 Q MPC8548 CR13 PQ GREENLED CR14 PQ CKSTP OUT R CR16 PQ REDLED R Debug CR18 DEBUG_LED1_R Ethernet CR19 DEBUG LED2 R CRIS TSEC2 DEBUG_LED3_R o CRI7 TSEC2 LINKSPD1 2 19 CR22 DEBUG LED43 R m CR20 TSEC2_LINKSPD1 2 Boot Device Ethernet CR44 BC1_LINKSPD1 2 CR45 BC1_LINKSPD1 2 CR46 BCI_ACT CR47 BC2 LINKSPD1 2 CR48 BC2 LINKSPD1 2 CR49 BC2 gt lt FA 1 Amp Fuse F5 1 Amp Fuse F6 10 Amp Fuse F7 8 Amp Fuse F8 10 Amp Fuse F9 8 Amp Fuse F4 F5 F6 F7 F8 F9 F10 75 Amp Fuse ATCA 9305 User s Manual 10009109 07 E AN NITCH LOCATI 57 Setup Figure 2 9 LED and Switch Locations Bottom PCB Rev 1 x Hot Swap CR57 BLUE LED CONN FWA SW2 FrontPanelReset Front Panel CR54 Red LEDIR_CONN Amber LEDIA_CONN CR55 LED2_CONN CR56 LED3_CONN
9. 90 Table 4 1 8548 Features ite na era nn 93 Table 4 2 MPC8548 Address Summary 24 2 2 95 Table 4 3 Device Chip Selects ers ce seen 97 Table 4 4 PCI Device Interrupts and ID Assignments 101 Table 4 5 I2C Device Addresses race pe ee RE wee rper eo SAI EE 101 Table 4 6 MPC8548 Memory 102 Table 4 7 Serial Debug Connector P2 103 Table 4 8 Serial Debug Connector P7 2 2 104 Table 5 1 PLD Register SUMMALY rrr erre een 105 Table 5 2 Product 00 00 ves a eripe PUN RE RR RR D E RR dcs 106 Table 5 3 Hardware Version 0 04 2 24 42 107 Table 5 4 PLD Version 0X08 225 ea a 108 Table 5 5 PLL Reset Configuration OxXOC 2 2 108 Table 5 6 Hardware Configuration 0 0x10 109 ATCA 9305 User s Manual 10009109 07 15 List of Tables Table 5 7 Jumper Settings 0x18 2 24 109 Table 5 8 LED u dy a De ee edad eee hes 110 Table 5 9 Reset Event 0x20 zn an De ae ba 111 Table 5
10. 69 Figure 3 2 CN5860 Reset Diagram 74 Figure 3 3 Example CN5860 Monitor Start up Display 77 Figure 3 4 Power up Reset CN5860 Boot Sequence Flowchart 78 Figure 4 1 MPC8548 Management Processor Complex Block Diagram 92 Figure 4 2 MPC8548 Memory 94 Figure 4 3 MPC8548 Reset 98 Figure 6 1 Ethernet Switching Interface Diagram 131 Figure 7 1 IPMC Connections Block Diagram 138 Figure 7 2 Extension Command Request Example 144 Figure 7 3 Extension Command Response Example 145 Figure 7 4 Boot Device Diagra u ea 195 Figure 7 5 Boot Redirection Control 196 Figure 7 6 IPMB Entity Structure 222 5 stad aoe eher ana 203 Figure 8 1 Zone 1 Connector PTO iced erre eee eene end EHI 213 Figure 8 2 Zone 2 and 3 Connectors 23 30 31 215 Figure 8 3 Zone 3 Connector 33 anne ee ne 218 Figure 9 1 Example MPC8548 Monitor Start up 221 Figure 9 2 Power up Reset Sequence Flowchart
11. ana aka 119 5 121 Status occ 120 5 1 22 1 C Clock Divisor 120 5 1 23 2 C_MUL Clock Divisor 121 5 1 24 TAGs an ae een a nn 122 ATCA 9305 User s Manual 10009109 07 7 Contents 5 1 25 GPIO 2 2 2 24 4 2 123 5 1 26 GPIO Data 2 42 24 123 5 127 GPIO Data ee ess cece a neben a ann 124 5 1 28 1 GPIO 24 24 2 4 125 5 1 29 LPC Bus Control ann ae ta ade vee 125 5 130 EPC M 126 5 1 31 Serial 1 126 5 1 32 Serial IRQ Interrupt 2 2 2 24 4 4 127 NER 129 6 1 Broadcom BCM56802 Switch 2 2 24 129 6 2 EthernetSwitching una anna ann 129 6 2 1 2 132 6 2 2 Ethernet Switch 2 132 6 2
12. we xxv xe Flash Commands The flash commands affect the StrataFlash devices on the ATCA 9305 circuit board There are four flash banks on the ATCA 9305 board see Flash on page 4 7 They can be accessed by e theindividual bank 1 2 3 or 4 or the address where both banks are regarded as one contiguous address space The following flash commands access the individual flash bank as flash bank 1 To access the individual sectors within each flash bank the sector numbers start at 0 and end at one less than the total number of sectors in the bank For a flash bank with 128 sectors the following flash commands access the individual sectors as 0 through 127 cp The cp command can be used to copy data into the flash device For the cp command syntax refer to Memory Commands on Memory Commands on 234 erase The erase command erases the specified area of flash memory Definition Erase all of the sectors in the address range from start to end erase start end Erase all of the sectors SF first sector to SL last sector in flash bank 4 N erase N SF SL Erase all of the sectors in flash bank erase bank N ATCA 9305 User s Manual 10009109 07 239 Management Processor Monitor 9 9 3 9 9 4 240 Erase all of the sectors in all of the flash banks erase all flinfo The flinfo command prints out the flash device s manufacturer part number size number of sectors and
13. 24 2 2 2 2 4 2 24 41 1 3 1 Product Certification 41 1 3 2 ROHS Compliance ccc cect ee een nr a 42 1 3 3 Terminology and Notation 2 44 2 47 2 1 Electrostatic Discharge 2 24 24 47 2 2 9305 Circuit Board 2 48 221 COMMGGUOMS 60 2 2 2 Configuration Header 4 61 2 3 9305 Setup une eu 62 2 3 1 Power Requirements RESAS 62 2 3 2 Environmental 2 63 2 3 3 HOLS Wap nee aim 66 2 4 Troubleshooting 2 2 2 2 2 2 2 4 22 24 4 67 ZAM Technical Support uses cereo are nee RUE RS redd 67 2 4 2 55 gt 5 5522 2 0 en CIE E 68 3 Processor QUE ODER Eu Ras bd 69 3 1 CN5860 PrOCesSOF ea 69 3 1 1 Cavium 2 2 2 4 70 32 Polski T epson 72 ATCA 9305 User s Manual 10009109 07 5 Contents 3 2 1 CN5860 Boot
14. 24 42 123 Table 5 27 GPIO Data Out 0x84 24 42 123 Table 5 28 GPIO Data In 0x88 124 Table 5 29 IPMP IPMC GPIO Control 125 Table 5 30 LPC Bus 0xD0 iecore Se SI RR cal Ree V e ew nn 125 Table 5 31 LPC Data 4 u 2 2 ee ea e rh eher eee en 126 Table 5 32 Serial IRQ Interrupts 1 0 08 2 126 Table 5 33 Serial IRQ Interrupts 2 0 2 2 127 Table 6 1 Ethernet Switch 2 132 Table 6 2 VLAN Configuration uou ke eb ag 133 Table 6 3 Ethernet Port Address 24 2 134 6 4 Front Panel Ethernet 134 Table 7 1 Network Function Codes 2 4 139 Table 7 2 Completion Codes u ae EEEE 140 Table 7 3 Format for IPMI Request Message 142 Table 7 4 Format for Response Message 143 Table 7 5 IPMCIPMIComnmarnds eee em rer bres es 147 16 ATCA 9305 User s Manual 100091
15. 179 7 11 12 Payload 1 2 22 4 2 179 7 11 13Disable Payload Control 2 2 180 711 anne ee aba 180 7 11 13Hang er 181 7 11 16Bused Resource u ee eo ieee 182 7 11 17Bused Resource Status 183 7 11 1 8Graceful vx waving reet e Mabie p ears 185 7 11 19Diagnostic Interrupt 2 186 7 11 20Get Payload Shutdown 186 7 11 21Set Payload Shutdown 2 2 187 7 11 22Set Local FRU LED State ee na 188 7 11 23Get Local FRU LED State 189 7 11 24Update Discrete 5 191 7 11 25Update Threshold Sensor 0 192 7 12 ASYNCHRONOUS EVENT NOTIFICATION 192 7 13 BOOT BANK SUPERVISION SENSOR 2 193 ATCA 9305 User s Manual 10009109 07 9 Contents 7 14 BOOT FIRMWARE BOOT OPTIONS 2 2 2 22 193 7 15 BOOT DEVICE REDIRECTION BDR
16. 62 Table 2 3 Environmental Requirements 63 3 1 CN5860 Features 22225252 m da 70 Table 3 2 Cavium Address Summary 2 2 2 70 Table 3 3 Memory anne ee nn 71 Table 3 4 Ethernet Port Address Eee nes 75 Table 3 5 POST Diagnostic Results Bit 79 Table 3 6 Standard Environment Variables 79 Table 3 7 Memory Map 2 2 22 82 Table 3 8 Data 31 24 0 0 edie tU e PR en 83 Table 3 9 23 7160 1 eset eco eoe SUL ei e 84 Table 3 10 Data 15 8 0 2 EURO RE RULES oen iR PARE PUR DIU erue 84 Table 3 11 Data 7 0 0X3 84 Table 3 12 Address 9 8 0x4 22 2 2 85 Table 3 13 Addr ss 720 0xb aussen een ee EEE ke Beh br 85 Table 3 14 Control ORKO d ed 86 Table 3 15 Version OXZ are ee e eee POP RE er eee 87 Table 3 16 Scratch 0 8 Zensur Vaud ews sa tte UR Xe bare Rr nee 87 Table 3 17 CN5860 Processor COP JTAG Headers 89 Table 3 18 CN5860 Processor Debug Headers
17. Port 1 Yellow 100 Mbps Green 1000Mbps Ethernet Link Activity bottom LED Port 2 Off No y On Link No Activity Blink Link Activity 49 Setup eee Figure 2 2 9305 Front Panel PCB Rev 2 x Ethernet Speed top LED Off 10Mbps Yellow 100Mbps PO Green 1000Mbps Red Amber Out of Service 00S Green In Service 2 Amber user Defined 3 Ethernet Link Activity bottom LED Off No Link On Link No Activity Blink Link Activity Port 2 Management Console Octeon1 Console Octeon2 Console Blue Hot Swap i 50 ATCA 9305 User s Manual 10009109 07 Setup Theelectromagnetic compatibility EMC tests used an ATCA 9305 model that includes a oj front panel assembly from Artesyn Embedded Technologies Embedded Computing For applications where the ATCA 9305 is provided without a front panel or where the front panel has been removed your system chassis enclosure must provide the required electromagnetic interference EMI shielding to maintain CE compliance ATCA 9305 User s Manual 10009109 07 51 Setup Figure 2 3 Component Map Top PCB Rev 1 x LOPTE mem TRU ae n 52 ATCA 9305 User s Manual 10009109 07 Setup Figure 2 4 Component PCB Rev 2 x
18. Asset Tag Not Used FRU File ID MultiRecord Area E Keying records Maximum Internal Current Variable for example fru info inf See E Keying 12 5 Amps E Keying This section details the interfaces governed by E keying and the protocols they support Specifically this includes the interfaces implemented by this product and the E keying definition that corresponds to each interface The IPMC supports E keying for the ATCA 9305 per PICMG ATCA 3 0 Revision 2 0 and PICMG 3 1 Revision 1 0 specifications The E keying information is stored in the ATCA Point to Point Connectivity Record located in the Multi Record area of the FRU Inventory Information see FRU Inventory on page 207 The ATCA Point to Point Connectivity Record contains a Channel Descriptor list where each Link Descriptor details one type of point to point protocol supported by the referenced channels ATCA 9305 User s Manual 10009109 07 System Management The ATCA channel descriptors define the ATCA channels implemented on a module Each channel has an arbitrary set of up to four ports Channel descriptors map physical ports to logical entities known as lanes see Table 7 51 vty Certain Ethernet core switch and fat pipe switch module GbE switch ports are disabled due to 7 lack of e keying support the monitor 7 21 1 Base Point to Point Connectivity The ATCA 9305 supports two 10 100 1000BASE T ports on Base
19. 5 1 11 Reset Command 3 The write only Reset Command 3 register forces one of several types of Cavium 1 resets as shown below A reset sequence is first initiated by writing a one to a single valid bit then the PLD performs that particular reset and the bit is automatically cleared Table 5 12 Reset Command 3 0x2C Function Description CAVIR Cavium 1 Reset CAV1PR Cavium 1 PCI Reset CAVIDR Cavium 1 DDR SDRAM Reset CAVIF 1 4 MB Flash local bus reset CAV1M1 Cavium 1 MIP1 reset 1 2 1 2 reset reserved 0 reserved ATCA 9305 User s Manual 10009109 07 113 Management Processor CPLD 5 1 12 Reset Command 4 The write only Reset Command 4 register forces one of several types of Cavium 2 resets as shown below A reset sequence is first initiated by writing a one to a single valid bit then the PLD performs that particular reset and the bit is automatically cleared Table 5 13 Reset Command 4 0x30 Bits Function Description CAV2R Cavium 2 Reset CAV2PR Cavium 2 PCI Reset CAV2DR Cavium 2 DDR SDRAM Reset CAV2F Cavium 2 4 MB Flash Cavium local bus reset CAV2M3 Cavium 2 MIP3 reset CAV2M4 Cavium 2 MIP4 reset reserved reserved 5 1 13 Reset Command 5 The write only Reset Command 5 register forces one of several types of BCM5680x Ethernet switch resets as shown below A reset sequence is first initiated by
20. Se eat ee 255 er 256 xA E 256 9 14 225 ee IL la 257 14 235 EE 257 9 14 25 6 MERE 257 9 14 25 ee 257 D VA oit eter ee eier us EREMO eet dre aue ce EP NUR 258 9 14 27 ERU nase d s d 258 9 15 8548 Environment Variables 260 9 16 Troubleshooting ne ee 263 9 17 Download Formats 2 2 2 2 2 2242 263 264 9 17 2 Motorola 5 2 264 A Related 265 Embedded Technologies Embedded Computing Documentation 265 A2 Technical References nn na sr ER ER E E RA FR RE 265 ATCA 9305 User s Manual 10009109 07 13 Contents m 14 ATCA 9305 User s Manual 10009109 07 List of Tables EN Table 1 1 Standard Compliance u EU Er E Rr Ep Rd RR ER 41 Table 2 1 Circuit Board Dimensions 2 48 Table 2 2 Typical Power
21. 24 24 4 194 7 16 MESSAGE LISTENERS ee tai et Lae 198 7 16 1 Add Message Listener 2 24 4 2 198 7 16 2 Remove Message 199 7 16 3 Get Message Listener List eee eee erect Ie 200 7 17 System Firmware Progress Sensor 201 7 18 Entities and Entity 202 7 19 Sensors and Sensor Data 204 7 20 FRUMENTO 2 nen een m in Anke ober 207 7 21 een een 208 7 21 1 Base Point to Point 209 7 22 HPM 1 Firmware Upgrade 2 210 7 22 1 1 Reliable Upgrade 210 7 23 IPMC Headers 05460 iener ni abe a ena ew ede 211 Back Panel Connectols HE ERN RUPEE CEN 213 8 1 OVEIVIBW en 213 8 2 ZONE ie ee esse Braun 213 8 3 LONE ra een 215 8 4 ZONES CC 216 9 Management Processor 219 OVEN TON cei an E 219 9
22. T_RXO_P 1_ RxD3_P RXD3N 2 2_RXO_N TxD3_P RTM_10G RTM_10G PCIE RTM_10G RTM_10G 1_RX1_P 1_RX1_N RXD2 P RXD2 N 2 2_RX1_N TXD2 P TXD2 N RTM_10G RTM_10G RTM_10G RTM_10G PQ_PCIE_ PQ_PCIE_ 1_RX2_P 1_RX2_N RXD1 P RXD1 N 2 RX2 P 2 2 TXD1 P TXD1 RTM 10G RTM 10G PCIE PCIE 10G RTM 10G 1_RG_P 1_RX3_N gxpo pP 2 2_RX3_N TxDo_P TXDO_N RTM_10G RTM_10G PCIE_ PCIE_ RTM_10G RTM_10G no no 1_ _ 1_ _ REFCLKF REFCLKF 2 TXO P 2 TXO connect connect N RTM 10G RTM 10G no no RTM 10G RTM 10G no no 1 1 TX1 N connect connect 2_TX1_P 2_TX1_N connect connect RTM_10G RTM_10G no no RTM_10G RTM_10G no no 1 TX2 P 1 TX2 N connect connect 2 2 P 2 2 connect connect 216 ATCA 9305 User s Manual 10009109 07 Table 8 3 Zone 3 Connector 30 Assignments continued Back Panel Connectors A B D E RTM 10G RTM_10G no RTM 10G 1 TX3 P 1 TX3 connect connect 2 TX3 P RTM ID3 RTM ID2 er nen GPIO3 RTM ID1 RTM IDO SW MDC SW MDIO GPIO1 RTM 10G 2 TIX3 RTM_ GPIO2 RTM_ GPIOO G H no no connect connect RTM_ RTM_ GPIO7 GPIO6 RTM_ RTM_ GPIO5 GPIOA Table 8 4 Zone 3 Connector 31 Pin Assignments 1063 __ _ 2
23. 9305 User s Manual P N 10009109 07 May 2014 SSS Copyright 2014 Artesyn Embedded Technologies Inc All rights reserved Trademarks Artesyn Embedded Technologies Artesyn and the Artesyn Embedded Technologies logo are trademarks and service marks of Artesyn Embedded Technologies Inc 2014 Artesyn Embedded Technologies Inc All other product or service names are the property of their respective owners Intel is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries Java and all other Java based marks are trademarks or registered trademarks of Oracle America Inc in the U S and other countries Microsoft Windows and Windows Me are registered trademarks of Microsoft Corporation and Windows is a trademark of Microsoft Corporation PICMG CompactPCI AdvancedTCA and the PICMG CompactPCI and AdvancedTCA logos are registered trademarks of the PCI Industrial Computer Manufacturers Group UNIX is a registered trademark of The Open Group in the United States and other countries Notice While reasonable efforts have been made to assure the accuracy of this document Artesyn assumes no liability resulting from any omissions in this document or from the use of the information obtained therein Artesyn reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Ar
24. 187 Table 7 38 Set Local FRU LED State Command 188 Table 7 39 Get Local FRU LED State 189 Table 7 40 Update Discrete Sensor Command 191 Table 7 41 Update Threshold Sensor Command 192 ATCA 9305 User s Manual 10009109 07 17 List of Tables Table 7 42 Boot Options Format 2 2 2 194 Table 7 43 Add Message Listener 198 Table 7 44 Remove Message Listener Command 199 Table 7 45 Get Message Listener List 200 Table 7 46 Update System Firmware Progress Sensor Command 201 Table 7 47 Threshold Sensors 2 4 2 2 204 Table 7 48 IPMI Discrete SefiSOrs 4 oe eee che ERR eran IRR e n tn en nn 204 Table 7 49 Event Message Format ree eto kauen 206 Table 7 50 TP V T 207 Table 7 51 Link Description E 209 Table 7 52 CPLD JP1 Pin Assignments 211 Table 7 53 IPMP EIA 232 Pin Assignments
25. 223 ATCA 9305 User s Manual 10009109 07 19 List of Figures 20 9305 User s Manual 10009109 07 Safety Notes EMC This section provides warnings that precede potentially dangerous procedures throughout this manual Instructions contained in the warnings must be followed during all phases of operation service and repair of this equipment You should also employ all other safety precautions necessary for the operation of the equipment in your operating environment Failure to comply with these precautions or with specific warnings elsewhere in this manual could result in personal injury or damage to the equipment Artesyn Embedded Technologies intends to provide all necessary information to install and handle the product in this manual Because of the complexity of this product and its various uses we do not guarantee that the given information is complete If you need additional information ask your Artesyn Embedded Technologies representative The product has been designed to meet the standard industrial safety requirements It must not be used except in its specific area of office telecommunication industry and industrial control Only personnel trained by Artesyn Embedded Technologies or persons qualified in electronics or electrical engineering are authorized to install remove or maintain the product The information given in this manual is meant to complete the knowledge of a specialist and must not be us
26. 5 1 30 5 1 31 126 Table 5 30 LPC Bus 0 continued Bits Function Description LPC State internal use only LPCIOE LPC I O Error SYNCE SYNC Error SYNCT SYNC Time out LPC Data This is the data register for the 4 bit LPC bus It allows for communication with the IPMC controller from the management CPU This register provides the data to be sent or received depending upon the commands given in the control register Table 5 31 LPC Data 0xD4 7 0 LPC Data Serial IRQ Interrupt 1 This is interrupt register1 for the LPC bus Table 5 32 Serial IRQ Interrupts 1 OxD8 ATCA 9305 User s Manual 10009109 07 Management Processor CPLD eee 5 1 32 Serial IRQ Interrupt 2 This is interrupt register2 for the LPC bus Table 5 33 Serial IRQ Interrupts 2 OxDC Bits Function Description ATCA 9305 User s Manual 10009109 07 127 Management Processor CPLD eee 128 ATCA 9305 User s Manual 10009109 07 Chapter 6 Ethernet Interface 6 1 6 2 Broadcom BCM56802 Switch The ATCA 9305 supports multiple Ethernet interfaces This chapter describes the Broadcom BCM56802 switch PHYS BCM5482 and 54615 Ethernet address LEDs and connectors The BCM56802 is 16 port 10 GbE multi layer switch based on the StrataXGS architecture The switch operates at 66 MHz with a 32 bit PCI bus for processor communication SERDES fun
27. Request Data PICMG Identifier indicates that this is a PICMG defined group extension command Use value 00h FRU Device ID 164 ATCA 9305 User s Manual 10009109 07 System Management Table 7 15 Get FRU LED State Command continued Type Byte Data Field 3 LED ID 00h Blue LED Hot Swap 01h LED 1 OOS 02h LED 2 03h LED 3 04h FEh OEM defined LEDs FFh reserved 1 Completion Code 2 PICMG Identifier indicates that this is a PICMG defined group extension command Use value 00h Response Data 3 LED States Bits 7 3 reserved set to 0 Bit 2 1b if Lamp Test has been enabled Bit 1 1b if override state has been enabled Bit 2 1b if IPMC has a Local control state 4 Local Control LED Function 00h LED is off default if Local Control not supported 01h FAh LED is blinking Off duration specified by this byte on duration specified by byte 5 in tens of milliseconds FBh FEh reserved FFh LED is on 5 On Duration LED on time is measured in tens of milliseconds Lamp Test time in hundreds of milliseconds if byte 4 FBh time value must be less than 128 Other values when Byte 4 FBh are reserved Otherwise this field is ignored and shall be set to Oh ATCA 9305 User s Manual 10009109 07 165 System Management Table 7 15 Get FRU LED State Command continued Type Byte Data Field Response Data Local Control Color Bits 7 4 reserved set to 0 Bits 3 0 Oh reser
28. TSEC1_TRD3_P FP1_TRD3_P TSEC1_TRD3_N FP1_TRD3_N TSEC1_ACTIVITY green LED 1 FP1_ACTIVITY green LED1 2_5V yellow LED 1 TSEC1_LINKSPD1 green LED 2 2_5V yellow LED 1 FP1_LINKSPD1 green LED 2 TSEC1_LINKSPD2 yellow LED 2 FP1_LINKSPD2 yellow LED 2 TSEC1_CHSGND FP1_CHSGND TSEC1_CHSGND ATCA 9305 User s Manual 10009109 07 FP1_CHSGND 135 Ethernet Interface eee EEE 136 ATCA 9305 User s Manual 10009109 07 Chapter 7 System Management eee 7 1 7 2 Overview The ATCA 9305 provides an intelligent hardware management system as defined in the AdvancedTCA Base Specification PICMG 3 0 This system implements an Intelligent Platform Management Controller based on the BMR H8S AMCc reference design from Pigeon Point Systems It also has an inter integrated circuit 120 controller to support an Intelligent Platform Management Bus IPMB that routes to the ATCA backplane The IPMCimplements all the standard Intelligent Platform Management Interface IPMI commands and provides hardware interfaces for other system management features such as Hot Swap control LED control power negotiation and temperature and voltage monitoring also supports an 232 interface for serial communications via the Serial Interface Protocol Lite SIPL commands IPMC Overview The basic features for the IPMC implementation include e Conformance with
29. gatewayip Gateway IP address Ensure that each MAC address on the network is unique bootv The bootv command checks the checksum on the primary image in flash and boots it if valid If it is not valid it checks the checksum on the secondary image in flash and boots it if valid If neither checksum is valid the command returns back to the monitor prompt Definition Verify bootup bootv Write image to flash and update NVRAM ATCA 9305 User s Manual 10009109 07 9 6 6 9 6 7 Management Processor Monitor bootv lt primary secondary gt write lt source gt lt dest gt lt size gt Update NVRAM based on image already in flash bootv lt primary secondary gt update lt source gt lt size gt Check validity of images in flash bootv lt primary secondary gt check bootvx The bootvx command boots VxWorks from an ELF image where address is the load address of the VxWorks ELF image To use this command the environment variables listed in Table 9 4 must be configured Definition bootvx address dhcp The dhcp command invokes Dynamic Host Configuration Protocol DHCP client to obtain and boot parameters by sending out a DHCP request and waiting for a response from a server Definition dhcp loadaddress bootfilename To use the dhcp command your DHCP server must be configured with the variables designated in Table 9 5 Table 9 5 DHCP Ethernet Configuration ipaddr Local IP a
30. gt EB Zone3 m 105 0 coo DI 5 g B B BO a Tine 3 8548 a 0 cum SO CDIMM Processor 0 02 00 oof ae Polar K Ae 7 Eos moo E u il M B E HE T 1 0235 Pn 00000 3 ne CPLD o amp B Domes 0000 m 8 T E E Q OL Zw oe 5680 2 Ud B um 8 Switch SPI XAUI SPI XAUI m m nn E xi 2 al 010002520 o UU ge 0 oc oo 0 of m 88 9 EB od 0 Ue 000000000 E ps Mini B USB um 0 th Ih ug J23 1 sg 80 pin D D nmn U55 Zone 2 056 Je n 12V CN58x0 E Power Supply onnector lt Processor 1 84118912 194014 55 EET DUET EN z n nn 20 0090 d 2 Oo Aia 7 ar p P10 30 B L are Connector Slo 10000 D 8 1000 ATCA 9305 User s Manual 10009109 07 53 Setup Figure 2 5 Component Map Bottom PCB Rev 1 x 54 082 081 U79 U78
31. 80 ATCA 9305 User s Manual 10009109 07 Processor Complex 3 5 3 5 1 Table 3 6 Standard Cavium Environment Variables continued Variable Default Value Description spi_num_ports undefined Defines the number logical ports per SPI interface Possible values are 1 default and 16 If set to 16 additional logical network interfaces are generated named octspi0 1 octspi0 2 octspi0 15 and octspi1 1 octspi1 2 octspi1 15 for logical ports 1 15 on SPI interface 0 and 1 respectively 0 1 use port number 0 The commands eth_eg_map eth_ig_map and eth_map_show are available in the 16 port configuration for mapping ports to ethernet VLANs and vice versa Memory The processor complex supports DDR2 Synchronous DRAM SDRAM and Reduced Latency DRAM RLDRAM memory devices SCP variants do not support RLDRAM DDR2 SDRAM The ATCA 9305 supports up to 16 gigabytes of 144 bit wide DDR2 SDRAM per processor complex The SDRAM interface clock speed frequency is up to 400 MHz The four low profile dual inline memory modules buffered DIMM are installed in 240 pin very low profile VLP sockets to reduce board density and routing constraints A 2 KB EEPROM on the DIMM provides the serial presence detection SPD On card SDRAM occupies physical addresses from 0 0000 0000 0000 5 to 0 0003 FFFF FFFF Each processor memory bus is operating in 144 bit mode Error correcting Code
32. RJ 45 Stecker 28 Die RJ 45 Stecker auf der Frontblende d rfen nur f r Twisted Pair Ethernet TPE Verbindungen verwendet werden Beachten Sie dass ein versehentliches Anschlie en einer Telefonleitung an einen solchen TPE Stecker sowohl das Telefon als auch das Board zerst ren kann Beachten Sie deshalb die folgenden Hinweise e Kennzeichnen Sie TPE Anschl sse in der N he Ihres Arbeitsplatzes deutlich als Netzwerkanschl sse e Schlie en Sie an TPE Buchsen ausschlie lich SELV Kreise Sicherheitskleinspannungsstromkreise an e DieL nge des mit dem Board verbundenen Twisted Pair Ethernet Kabels darf 100 m nicht berschreiten Falls Sie Fragen haben wenden Sie sich bitte an Ihren Systemadministrator ATCA 9305 User s Manual 10009109 07 Sicherheitshinweise Austausch Erweiterung Verwenden Sie bei Austausch oder Erweiterung nur von Artesyn Embedded Technologies empfohlene Komponenten und Systemteile Andernfalls sind Sie f r m gliche Auswirkungen auf EMV oder Fehlfunktionen des Produktes voll verantwortlich berpr fen Sie die gesamte aufgenomme Leistung aller eingebauten Komponenten siehe die technischen Daten der entsprechenden Komponente Stellen Sie sicher dass die Stromaufnahme jedes Verbrauchers innerhalb der zul ssigen Grenzwerte liegt siehe die technischen Daten des entsprechenden Verbrauchers Umweltschutz Entsorgen Sie alte Batterien und oder Produkte stets gem der in Ihrem Land g ltigen
33. 000 0000 R W 8000 0000 R W PCI Express I O space 16 MB PCI Express 256 PCI 1 5 GB ATCA 9305 User s Manual 10009109 07 Management Complex 4 1 2 Table 4 2 MPC8548 Address Summary continued Hex Physical Address Access Mode Register Description See Page 0000 0000 R W SDRAM DDR2 2 GB 9 Chip Selects The MPC8548 memory controller functions as a chip select CS generator to access on board memory devices In order to select one device over another the following chip selects have been established Table 4 3 Device Chip Selects Boot bank Soldered flash boot bank 1 default Soldered flash boot bank 2 Socketed flash optional 4 KSL CPLD registers NAND flash 6 Soldered NOR flash boot banks 3 and 4 7 LPC interface Boot bank can be either socketed flash flash 1 or flash 2 depending on the jumper setting see Figure 2 11 ATCA 9305 User s Manual 10009109 07 97 Management Complex u Figure 4 3 8548 Reset Diagram 3_3V_MP PQ_HRESET PQ_SRESET alit 3 PWRGD Management 2_5V_PWRGD a MI 1 8 PWRGD 12V PWRGD 1 PWRGD CORE PWRGD RESET INDICATION P1 CORE PWRGD Dci P2 CORE PWRGD FLASH_RST Reset PO RST TSECT_RST PAYLOAD 857 pog perg a 3_3V_MP IPMC_PO_RST PRIV_IZC_SDA 98 ATCA 9305 User s Manual 10009
34. 0x18 register Figure 2 11 Configuration Header 9 BTFLASH RIC proc 2O STAND BOOT On REDIREN u IGROM BT SKT N 5 Ashunt pins 1 2 selects the 512 socketed ROM as the boot device for the MPC8548 IG SROM If the serial ROM configuration jumper is installed pins 3 4 the ATCA 9305 will not try to configure IGNORE SROM from the MPC8548 serial ROM REDIR EN A shunt installed on pins 5 6 disables the boot redirection see Page 194 for more information BOOT A shunt on pins 7 8 causes both CN5860s to boot from their local bus and not boot over PCI STAND A shunt on pins 9 10 IPMC stand alone mode allows the board to boot without management control PROG Installing a shunt on pins 11 12 puts the IPMC controller into programming mode This is only used in the factory to configure the IPMC ATCA 9305 User s Manual 10009109 07 61 Setup 2 3 2 3 1 62 BT FLASH If BOOT shunt is installed booting from local bus this shunt determines whether the boot is from local flash or socket When this BT FLASH shunt is installed the ATCA 9305 boots from flash Otherwise it boots from the socket ATCA 9305 Setup You need the following items to set up and check the operation of the Artesyn ATCA 9305 ATCA chassis and power supply e MPC8548 Console cable for EIA 232 port Artesyn part C0007662 00 e Computer terminal Save
35. 211 Table 8 1 Zone 1 Connector P10 Pin Assignments 213 Table 8 2 Zone 2 Connector 23 Pin Assignments 215 Table 8 3 Zone 3 Connector 30 Pin Assignments 216 Table 8 4 Zone 3 Connector 31 Pin Assignments 217 Table 8 5 Zone 3 Connector 33 Pin Assignments 218 Table 9 1 Debug LED Codes 24 24 2 2 222 Table 9 2 POST Diagnostic Results Bit 224 Table 9 3 Monitor Address per Flash Device 226 Table 9 4 Static IP Ethernet Configuration 230 Table 9 5 DHCP Ethernet 231 Table 9 6 Standard Environment Variables 260 Table 9 7 Optional Environment 262 Table A 1 Artesyn Embedded Technologies Embedded Computing Publications 265 Table A 2 Technical References 265 18 ATCA 9305 User s Manual 10009109 07 List of Figures EN Figure 1 1 General System Block Diagram
36. 5 1 15 5 1 16 116 Reset Command Sticky 2 The read write Reset Command Sticky 2 register forces one of several types of the PHY reset command as shown below A reset sequence is first initiated by writing a one to one or more bits then the PLD performs that particular reset The bit will persist until cleared Table 5 16 Reset Command Sticky 2 0x3C Bits Function Description TSECIR TSEC1 Ethernet to front panel PHY Reset TSEC2R TSEC2 Ethernet to switch PHY Reset FPIR FPI Ethernet from switch to front panel PHY Reset BCR Ethernet dual PHY to backplane Base Channel Reset SPI to XAUI bridge 1 on Cavium 1 SPI to XAUI bridge 2 on Cavium 1 SPI to XAUI bridge 3 on Cavium 2 SPI to XAUI bridge 4 on Cavium 2 Boot Device Redirection The read write Boot Device Redirection register BDRR allows the user to determine which of three boot devices the MPC8548 CPU is using as the boot device Several bits also indicate which device was set as the initial boot device The Boot Redirected bit is set to a 1 when the current boot device does not match the initial default boot device This indicates to the user that the image in the default device was bad the MPC8548 watch dog timer expired and the next device was tried The boot device redirection order is determined by IPMC Reference the Boot Device Diagram Table 5 17 Boot Device Redirection 0x50 Bits Function Description 7 SELFRS Self Refresh St
37. 58 ATCA 9305 User s Manual 10009109 07 Setup Figure 2 10 LED and Switch Locations Bottom PCB Rev 2 x 2 4 0 o E SW 4700 Hot Swap CR57 BLUE_LED_CONN_K g Front Panel CR54 Red LEDIR_C I Amber LEDTA CR55 LED2 CR56 LED3 CON O L 9 Q are o AND SWITCH LOCATIONS ATCA 9305 User s Manual 10009109 07 59 Setup 2 2 1 Connectors The ATCA 9305 circuit board has various connectors and headers see the figures beginning on Page 52 summarized as follows J1 This 14 pin JTAG header is used for debugging CN5860 processor 2 See Table 3 17 3 6 These 240 pin sockets are installed for the CN5860 processor 1 DDR2 SDRAM memory J9 This 14 pin configuration header allows selection of boot device and MPC8548 configuration for the configuration SROM See Figure 2 11 11 14 These 240 sockets are installed for the CN5860 processor 2 DDR2 SDRAM memory This 14 JTAG header is used for debugging CN5860 processor 1 See Table 3 17 123 The 80 pin Zone 2 connector provides 1 GB and 10 GB Et
38. ATCA 9305 soldered flash bank 1 Jumper 11 1 2 Flash bank 2 Flash bank 1 shunt installed fail fail Secondary boot Boot device is 512 attempt is from ATCA KB socketed flash Boot 9305 soldered Boot from BDR Watchdog flash bank 2 EM flash bank 1 disabled ATCA 9305 User s Manual 10009109 07 195 System Management 196 The Boot Device Redirection mechanism is disabled when booting the 512 socketed flash Figure 7 5 Boot Redirection Control Diagram Payload Reset Monitor Booted Management Controller Power Good Force Boot Socket Payload Payload Reset Indication I C Port Boot Select Expander m gt n Payload Reset Indication Clear Management Controller The controller provides a signals to reset the payload Payload This provides signals to the controller indicating when the payload has reset for any reason that the payload is powered and that the payload has finished its monitor booting sequence By default a powered payload enables the watchdog and disables when the payload is not powered ATCA 9305 User s Manual 10009109 07 System Management Port Expander The port expander provides signals to the payload to define the boot device selection boot select 1 and 2 and to clear the payload reset indication The 12 port expander communicates with the controller via a private I C
39. PCI Express Single x4 PCle high speed interconnect complies with PCI Express Base Specification Revision 1 0 Complies with IEEE Std 1149 1 For more detailed information reference the Freescale MPC8548E PowerQUICC III Integrated Processor Family Reference Manual MPC8548 Memory Map The monitor can boot from either the soldered flash Bank 1 default or the socketed PLCC device Based on the configuration header see Configuration Header on page 61 either the socketed device or soldered flash is mapped to the boot bank at FFF8 000016 see Figure 4 2 Information on particular portions of the memory map can be found in later sections of this manual see Table 4 2 ATCA 9305 User s Manual 10009109 07 93 Management Complex Figure 4 2 8548 Memory Hex Address Serial IRQ Interrupt 2 Serial IRQ Interrupt 1 Address Range 40 0008 Pen 40 0004 FFFF F FFF Boot Window 512 KB 40 0000 LPC Bus Control FFFO 0000 SFO Comro FFEF F FFF 4 0088 Cavium Data Input FF80 0000 0084 GPIO Data Output FF7EFFFF l GPIO Control FF70 0000 FC40 0078 _Altera JTAG Software Control FF6F F FFF FC40 0074 Cavium 2 Clock Divisor Control FC88 0000 Fete 1 Clock Divisor Control FC87 FFFF RTM Contro GPIO
40. Pigeon Point Systems Hardware Address If set to 00 the ability to override the hardware address is disabled NOTE A hardware address change only takes effect after an IPMC reset See Reset on page 7 34 1 Completion Code 176 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems ATCA 9305 User s Manual 10009109 07 System Management 7 11 8 Get Handle Switch The Get Handle Switch command reads the state of the Hot Swap handle of the IPMC Overriding of the handle switch state is allowed only if the IPMC operates in Manual Standalone mode Table 7 24 Get Handle Switch Command Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems Response Data 1 Completion Code PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems Handle Switch Status 0x00 The handle switch is open 0x01 The handle switch is closed 0x02 The handle switch state is read from hardware 7 11 9 Set Handle Switch The Set Handle Switch command sets the state of the Hot Swap handle switch in Manual Standalone mode Table 7 25 Set Handle Switch Command Type Byte Data Field Request Data ATCA 9305 User s Manual 10009109 07 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems Handle Switch Status 0x00 The
41. RTM_10G3 _RX1_P RTM_10G3 RXO_N RTM_10G3 _RXI_N RTM_10G5 __ _ _1005 _RX1_P RTM_10G5 _RXO_N RTM_10G5 _RXI_N RTM_10G4 __ _ RTM_10G4 _RX1_P RTM_10G4 RTM_10G6 10G6 RXO P _ RXO 10G6 10G6 1003 _RX2_P RTM_10G3 _RX3_P RTM_10G3 _ _ RTM_10G3 _RX2_N RTM_10G3 _RX3_N RTM_10G3 _ TXO_N RTM_10G5 _RX2_P RTM_10G5 __ _ _1005 _ _ _1005 _RX2_N _1005 _RX3_N RTM_10G5 _ TXO_N RTM_10G4 _RX2_P RTM_10G4 __ _ RTM_10G4 _ _ RTM_10G4 _ TXO_N RTM_10G6 RTM_10G6 RTM_10G6 RTM_10G6 _RX3_P _ _ RTM_10G6 RTM_10G6 RTM_10G3 RTM_10G3 _ TX3_P RTM_10G3 _TXI_N RTM_10G3 2 RTM_10G3 _TX3_N RTM_10G5 _ TX1_P RTM_10G5 2 1065 __ _ _1005 _TXI_N RTM_10G5 _ TX2_N RTM_10G5 _ TX3_N RTM_10G4 _ TX1_P RTM_10G4 _ TX2_P RTM_10G4 _ TX3_P RTM_10G4 _TXI_N RTM_10G4 _TX2_N RTM_10G4 _TX3_N RTM_10G6 RTM_10G6 RTM_10G6 RTM_10G6 _ 2_ _TX2_N RTM_10G6 RTM_10G6 _TX3_P _TX3_N no connect no connect no connect no connect no connect no connect no connect no connect no connect no connect no connect ATCA 9305 User s Manual 10009109 07 no connect no connect no con
42. hexadecimal The ATCA 9305 has been assigned the Ethernet address range 00 80 F9 97 00 00 to 00 80 F9 98 FF FF The format is shown in Table 6 3 Table 6 3 Ethernet Port Address Offset MAC Description Ethernet Identifier hex 15 0 LSB of serial number in hex MSB of serial number in hex 23 16 Port 1 TSEC 1 0x97 Port 2 TSEC_2 0x98 47 24 Assigned to Artesyn by IEEE OxF9 0x80 Byte 0 0x00 The last two bytes MAC 15 0 correspond to the following formula n 21000 where n is the unique serial number assigned to each board So if an ATCA 9305 serial number is 1032 the calculated value is 32 2046 and the default Ethernet port addresses are e 5 1 MAC address is 0x00 0x80 OxF9 0x97 0x00 0x20 e 2 MAC address is 0x00 0x80 OxF9 0x98 0x00 0x20 Front Panel Ethernet Ports One MPC8548 PHY TSEC1 routes to front panel RJ45 connector The BCM56802 switch PHY port3 routes to front panel RJ45 connector P3 The Ethernet port LEDs green or yellow indicate link and activity status see front panel Figure 2 1 Table 6 4 Front Panel Ethernet Ports Pin P1 Signal P3 Signal 5 TRDO P FP1 TRDO P ATCA 9305 User s Manual 10009109 07 Table 6 4 Front Panel Ethernet Ports continued Ethernet Interface Pin P1 Signal P3 Signal TSEC1_TRDO_N FP1_TRDO_N TSEC1_TRD1_P FP1_TRD1_P TSEC1_TRD2_P FP1_TRD2_P TSEC1_TRD2_N FP1_TRD2_N TSE1C_TRD1_N FP1_TRD1_N
43. 2 Command Line Features 22 2 2 219 9 3 Basic Operation ae ee eee eee neue 222 9 3 1 Power up ResetSequence 223 9 3 2 POST Diagnostic Results 4 224 9 3 3 Monitor SDRAM 05 1 225 9 4 Monitor Recovery and 24 2 225 9 4 1 Resetting Environment 226 9 4 2 Updating the Monitor via 24 2 227 9 5 Monitor Command 4 24 228 9 5 1 Command 228 10 ATCA 9305 User s Manual 10009109 07 Contents 9 5 2 Command in 228 9 5 3 Typographic 229 9 6 BootComimalids an ee hen 229 9 6 1 Mmm 229 9 6 2 nenne _____ _ _ 229 9 63 a aden es 229 9 5 4 Raa 230 9 65 DOO ee ET 230 9 6 6 entrer i ge Ee Ren reca eren erar ERU RR ER NUR 231 Sv 231
44. 2 MAC address is 0x00 0x80 OxF9 0x9A 0x00 0x20 Cavium 2 SPI 1 MAC address is 0x00 0x80 OxF9 0 9 0x00 0x20 e Cavium 2 SPI 2 MAC address is 0x00 0x80 OxF9 Ox9C 0x00 0x20 Cavium Monitor The primary function of the monitor software is to transfer control of the hardware to the user s application Secondary responsibilities include e low level initialization of the hardware diagnostic tests e low level monitor commands functions to aid in debug Start up Display At power up or after a reset the monitor runs diagnostics and reports the results in the start up display see an example in Figure 3 3 During the power up sequence the monitor configures the board according to the environment variables see MPC8548 Environment Variables on page 260 If the configuration indicates that autoboot is enabled the monitor ATCA 9305 User s Manual 10009109 07 Processor Complex 1 3 4 2 9305 User s Manual 10009109 07 attempts to load the application from the specified device If the monitor is not configured for autoboot or a failure occurs during power up the monitor enters normal command line mode The monitor command prompt in Figure 3 3 is the result of a successful hardware boot of the ATCA 9305 Figure 3 3 Example CN5860 Monitor Start up Display Hardware initialization gt Monitor command prompt gt U Boot 1 1 1 Jan 16 2009 14 26 14 0 9 OCTE
45. 3 4 4 Processor Complex Diagnostic Tests During Power up and Reset The Cavium monitor diagnostic tests can be executed during power up or invoked from the monitor s command prompt This is accomplished by changing the state of the monitor configuration parameters that define power up and reset diagnostics mode If the powerondiags parameter is set to on the monitor invokes the diagnostic tests after a reset of the hardware Results are displayed to the console including whether the test passed or failed POST Diagnostic Results The ATCA 9305 Power On Self Test POST diagnostic results are stored as a 32 bit value in memory accessible by the management console at location 0x80080A6C where 0x80080A6C is 8548 or an Octeon address Each bit indicates the result of a specific test so this field can store the results of up to 32 diagnostic tests Table 3 5 assigns the bits to specific tests Table 3 5 POST Diagnostic Results Bit Assignments Diagnostic Test Description Value Reserved DRAM Verify address and data lines are intact 9 Passed the test 1 Failure detected Cavium BIST Pc Verify all local I C devices are connected to the bus Reserved Cavium Environment Variables The following table lists the standard Cavium environment variables Table 3 6 Standard Cavium Environment Variables Variable Default Value Description baudrate 115200 Console port baud rate Va
46. 65 byte 4 00 Network function for listener 0 Command for listener 0 5 6 7 Network function for listener 1 8 Command for listener 1 9 Network function for listener 2 10 Command for listener 2 11 Network function for listener 3 12 Command for listener 3 13 Network function for listener 4 14 Command for listener 4 15 Network function for listener 5 16 Command for listener 5 17 Network function for listener 6 18 Command for listener 6 200 ATCA 9305 User s Manual 10009109 07 System Management Table 7 45 Get Message Listener List Command continued Type Byte Data Field 19 Network function for listener 7 Command for listener 7 7 17 System Firmware Progress Sensor The Update System Firmware Progress Sensor command sets the values for the Firmware Progress Sensor using sensor codes from the IPMI Intelligent Platform Management Interface Specification specifically System Firmware Progress within Table 42 3 in Section 42 2 Sensor Type Codes and Data The command returns 0xCO when the IPMC is busy and will retry until the command is successful If this command returns OxCC the sensor ID is invalid There is only one sensor on the board so the sensor ID should always 0 When updated the shelf manager is notified Table 7 46 Update System Firmware Progress Sensor Command Type Byte Data Field Request Data 1 3 Artesyn Embedded Technolog
47. 80000 20 00080000 EEEE EEFE EEEE oa 00080010 fttt fttt fttt me 00080020 ffff wee eww ewes 00080030 ffff voie b ws ATCA 9305 User s Manual 10009109 07 Management Processor Monitor 9 8 5 mm The mm command modifies memory one object at a time Once started the command line prompts for a new value at the starting address After a new value is entered pressing ENTER auto increments the address to the next location Pressing ENTER without entering a new value leaves the original value for that address unchanged To exit the mm command enter a non valid hexadecimal value such as x followed by ENTER Definition mm b w 1 address Example In this example the mm command is used to write random 8 bit data starting at the physical address 0x80000 mm b 80000 00080000 ff 12 00080001 ff 23 00080002 ff 34 00080003 ff 45 00080004 ff 00080005 ff x md b 80000 6 00080000 12 23 34 45 ff ff 4E gt 9305 User s Manual 10009109 07 237 Management Processor Monitor 9 8 6 nm The nm command modifies a single object repeatedly Once started the command line prompts for a new value at the selected address After a new value is entered pressing ENTER modifies th
48. 9 14 9 14 1 9 14 2 9 14 3 250 um b w 1 base_addr top_addr Other Commands This section describes all the remaining commands supported by the ATCA 9305 monitor autoscr The autoscr command runs a script starting at address addr from memory A valid autoscr header must be present Definition autoscr addr base The base command prints or sets the address offset for memory commands Definition Displays the address offset for the memory commands base Sets the address offset for the memory commands to off base off bdinfo The bdinfo command displays the Board Information Structure Definition bdinfo ATCA 9305 User s Manual 10009109 07 Management Processor Monitor 9 14 4 9 14 5 9 14 6 9 14 7 coninfo The coninfo command displays the information for all available console devices Definition coninfo crc32 The crc32 command computes a CRC32 checksum on count bytes starting at address Definition crc32 address count date The date command will set or get the date and time and reset the RTC device Definition Set the date and time date MMDDhhmm CC YY ss Display the date and time date Reset the RTC device date reset echo The echo command echoes args to console Definition echo args ATCA 9305 User s Manual 10009109 07 251 Management Processor Monitor 9 14 8 9 14 9 9 14 10 9 14 11 252 enumpci
49. 9 6 8 232 9 69 He 233 9 7 FileLoad GCommands art cos cided an en 233 OFA NAD er Eure 233 9 7 2 Oddset 234 9 8 Memory Commands ssc cor ed n be baren 234 9 8 1 rU 235 9 82 e o 235 983 235 FEE MEG 236 9 8 3 DM 237 238 9 8 77 Wine 238 9 9 Flash Commands nn nn 239 9 01 CD debs hata 239 9 9 2 o ERE 239 9 9 37 ILE 240 9 9 4 protect nern 240 9 10 EEPROM I2C Commands 2 4 241 9 10 1 ee ke be 241 9 10 2182 area RR 241 MIU LR 242 242 9 105 IMM ETT 242 2 E 242 910 7 A 243 ATCA 9305 User s Manual 10009109 07 11 Contents 9 10 8 1 243 9 11 oS este ves e SES 243 9 1151 eee ide 243 9 11 2 bparams get os neu ne erben 244 9 11 23 bparatmrs set nn ___ a 244 EST 245 RE e De ehe 246 SM ler 246 9 11 7 nee ne 247 1 1 8
50. AdvancedTCA Base Specification PICMG 3 0 Geographical addressing according to PICMG 3 0 Ability to read and write Field Replaceable Unit FRU data e Ability to reset from IPMB Ability to read inlet and outlet airflow temperature sensors e Ability to read payload voltage current levels Ability to send event messages to a specified receiver All sensors generate assertion and or de assertion event messages e Support for fault tolerant HPM 1 firmware upgrades e Support for field updates of firmware via 0 or the payload interface Redundant boot bank capability ATCA 9305 User s Manual 10009109 07 137 System Management e Graceful Shutdown Timeout Asynchronous event notification Figure 7 1 Connections Block Diagram Payload Processor Interface Payload Boot Power Enables and Payload Device Management Reset Select Temperature Sensors CPU Inlet CPU Outlet Temp Sensor Temp Sensor 0x90 0x92 CPU Present Bus RTM Present Pigeon Point RTM Payload Power Enable R f D RTM Management Power Enable Design IPMC Debug roprieta Console p p Front ShMC Present Fane from JP7 LEDs IPMC Reset Switch Hot Swap Switch 318VN3 v aWdl Isolation Isolation 138 ATCA 9305 User s Manual 10009109 07 System Management 7 3 IPMI Messa
51. CR35 STATE LED8 CR36 STATE LED7 7 STATE LEDG _ CR38 STATE LED5 CR39 STATE_LED4 _ STATE_LED3 STATE_LED2 42 STATE CR43 STATE_LEDO F4 1 Amp Fuse 5 1 Amp Fuse 6 10 Amp Fuse F7 8 Amp Fuse F8 10 Amp Fuse F9 8 Amp Fuse CKSTP_OUT_R F4 F5 F6 F7 F8 F9 Ethernet CR44 BC1_LINKSPD1 2 CR45 BC1_LINKSPD1 2 CR46 BC1_ACT CR47 BC2 LINKSPD1 2 CR48 BC2 LINKSPD1 2 CR49 BC2 j 56 ATCA 9305 User s Manual 10009109 07 Setup Figure 2 8 LED Fuse and Switch Locations Top PCB Rev 2 x RI P2_LED_GPIOT2 R Q 2 P2_LED_GPIO13 R c CR3 P2 LED GPIO14 R P2_LED_GPIO15 R F1 75 Amp CR5 MIP4_LED1_R CR6 MIPA_LED2_R CR7 MIP4_LED3_R CR23 MIPI_LEDI_R CR24 MIP1_LED2_R CR25 LED3 R CR26 MIP1_LED4_R 00 CR27 MIP2_LED1_R CR28 MIP2_LED2_R CR29 MIP2_LED3_R m CR31 FLO LED CR32 FLT LED R CR33 SKT LED R CR30 MIP2_LED4_R CR50 P1 LED 12 R CR51 P1 LED GPIO13 a G d 52 1 LED GPIO14 CR53 P1 LED GPIO15
52. ECC is performed on the memory bus so that the CN5860 detects all double bit errors multi bit errors within a nibble and corrects all single bit errors ATCA 9305 User s Manual 10009109 07 81 Cavium Processor Complex 3 5 2 3 5 3 3 5 4 3 5 5 82 RLDRAM Each CN5860 supports 256 MB Common I O CIO RLDRAM operating up to 400 MHz depends on the processor speed The Micron RLDRAM is organized as 32 18 8 internal banks The DDR I O interface transfers two data words per clock cycle Output data is referenced to the free running output data clock Read and write accesses to the RLDRAM are burst oriented RLDRAM is accessed by using Cavium specific instructions which operate on MIPS Coprocessor 2 SCP variants of the ATCA 9305 do not support RLDRAM EEPROM Each Cavium processor complex has one user EEPROM device for parameter storage located on the 2 bus address The I C bus for each processor is completely independent from the other CN5860 processor and MPC8548 processor I C buses The Atmel two wire serial EEPROM on each CN5860 processor interface consists of the Serial Clock SCL input and the Serial Data SDA bidirectional lines Table 3 7 Cavium NVRAM Memory Map Address Offset hex Description Window Size bytes 0x0000 0x1D36 User defined 79F Flash 512 KBx8 The 512 KB of 32 pin PLCC socketed flash starts at physical address 1D46 0000 is used for Engineering co
53. Ethernet Interface eee Two 10 GbE ports to the fabric interface Two 1 GbE ports to the base interface e Six 10 GbE ports to the Zone 3 connector optional RTM 130 ATCA 9305 User s Manual 10009109 07 Ethernet Interface eee Figure6 1 Ethernet Switching Interface Diagram 8548 Management Processor Cavium 56802 Cavium 10 Gb Octeon CN5860 Switch Ports CN5860 Processor 1 Processor 2 ATCA 9305 User s Manual 10009109 07 131 Ethernet Interface tz Thephysical port numbering starts at 1 as indicated in the figure However the software NN port numbering starts at 0 Therefore to issue a command to a port you must subtract 1 from the port numbers shown in the figure 6 2 1 Ethernet Transceivers The 54615 is a 10 100 1000BASE T GbE Ethernet transceiver using the SGMII interface The BCM5482 consists of two complete 10 100 1000BASE T GbE transceivers supporting both voice and data simultaneously 6 2 2 Ethernet Switch Ports Table 6 1 Ethernet Switch Ports Port Interface Connection SGMII 1 GB PHY to backplane BASE SGMII 1 GB PHY to backplane BASE SGMII 1 GB Switch PHY to front panel RJA5 connector SGMII 1 GB Management processor PHYs to front panel RJ45 connector XAUI 10 GB Stratix Il GX bridge 2 3 4 5 6 XAUI 10 GB Stratix GX bridge 1 Back plane Fabric 8 ____ _____ Back plane Fabric 9 not
54. Gesetzgebung und den Empfehlungen des Herstellers ATCA 9305 User s Manual 10009109 07 29 Sicherheitshinweise 30 9305 User s Manual 10009109 07 About this Manual EN Overview of Contents This manual is divided into the following chapters and appendix e Chapter 1 Overview on page 37 Chapter 2 Setup on 47 e Chapter 3 Processor Complex on page 69 Chapter 4 Management Complex on page 91 Chapter 5 Management Processor CPLD on page 105 e chapter 6 Ethernet Interface on page 129 Chapter 7 System Management on page 137 e Chapter 8 Back Panel Connectors page 213 Chapter 9 Management Processor Monitor on page 219 Appendix A Related Documentation on page 265 Abbreviations This document uses the following abbreviations Abbreviation Definition AMC Advanced Mezzanine Card ASCII American Standard Code for Information Interchange ATCA Advanced Telecom Computing Architecture or AdvancedTCA BMC Baseboard Management Controller CIO Common 1 RLDRAM Cmd Command code CPU Central Processing Unit CRC Cyclic Redundancy Code CSA Canadian Standards Association DDR Double Data Rate ATCA 9305 User s Manual 10009109 07 31 About this Manual Abbreviation Definition European Community Error correcting Code Electronic Industries Alliance Electromagnetic Compatibility Elect
55. IPMC GPIO Control Low Pin Count LPC Bus Control 125 LPCD LPC Data 126 0 08 SIRQIT Serial IRQ Interrupt 1 15 8 126 OxDC SIRQI2 Serial IRQ Interrupt 2 7 0 127 Scratch 1 0x40 is a read write register for storage only 5 1 1 Product ID This read only register identifies the board as ATCA 9305 and is used for PLD coding Table 5 2 Product ID 0x00 Function Description Cavium Frequency 1 6 CAVFO Cavium Frequency 0 106 ATCA 9305 User s Manual 10009109 07 Management Processor CPLD Table 5 2 Product ID 0x00 continued Function Description Product ID Hardware Configuration 1 Hardware Configuration 0 5 1 2 Hardware Version This read only register tracks hardware revisions Table 5 3 Hardware Version 0x04 Function Description 3 3 Hardware Version Number is hard coded in the PLD and changes gt HVN 2 with every major PCB artwork version Version starts at 0046 1 HVN 1 0 HVN 0 ATCA 9305 User s Manual 10009109 07 107 Management Processor CPLD 5 1 3 5 1 4 108 PLD Version This read only register tracks PLD revisions Table 5 4 PLD Version 0x08 Bits Function Description This is hard coded in the PLD and changes with every released code change Version starts at 0016 PLL Reset Configuration Write to this register to reconfigure the SYSC
56. Interface Channels 0 and 1 and two 10 GbE XAUI ports to the Fabric channels Depending on the board configuration either two or six 10 GbE XAUI ports route to the optional rear transition module RTM see Table 7 51 shows the Point to point Connectivity Record Link Descriptors for the ATCA 9305 YE For actual Point to Point connectivity Records for your configuration query the IPMI 7 controller Table 7 51 Link Description Value Description Link Descriptor 000100000000b Link Type 01h Port 0 Enabled Base Interface Channel 1 PICMG 3 0 Base Interface 10 100 1000BASE T Link Type Extension 000b Link Grouping ID 00h Independent Channel Link Designator 000100000001b Link Type 01h Port 0 Enabled Base Interface Channel 2 PCIMG 3 0 Base Interface 10 100 1000BASE T Link Type Extension 0000b h hexadecimal b binary ATCA 9305 User s Manual 10009109 07 209 System Management 7 22 7 22 1 210 Table 7 51 Link Description continued Field Value Description Link Grouping ID 00h Independent Channel Link Designator 000110000001b Port 0 Enabled Update Channel Interface Channel 1 Link Type 01h PICMG 3 1 Ethernet Fabric Interface Link Type Extension 0000b Fixed 1000BASE BX Link GroupingID 00h Independent Channel h hexadecimal b binary HPM 1 Firmware Upgrade The ATCA 9305 IPMC firmware supports field upgrade procedure com
57. P1 and P5 processor P2 access the CN5860 processors for Engineering debug use only The supported baud rates for these ports operate at 9600 14400 19200 38400 57600 and 115200 bps The default rate is 115200 bps Table 3 18 CN5860 Processor Debug Headers 1 no connect no connect 2 P1_SER1_RXD P2_SER1_RXD P1_SER1_TXD P2_SER1_TXD signal ground signal ground 5 6 7 shield signal ground 90 ATCA 9305 User s Manual 10009109 07 Chapter 4 Management Complex 4 1 MPC8548 Processor The ATCA 9305 management complex is comprised of the Freescale MPC8548 processor CPLD SDRAM flash EEPROM Real time Clock and PCI bus interface Board power up booting and monitoring the Cavium processors PCI bus arbitration interrupt servicing memory persistence functionality and other board level management tasks are implemented using the MPC8548 processor The MPC8548 stores the operating system and monitor code in its local memory and then uses the boot over PCI functionality to bring up the Cavium processor complexes The CPLD registers are described in Chapter 5 Management Processor CPLD See Chapter 9 Management Processor Monitor for the Management Processor Monitor The management complex connects to the Broadcom Ethernet switch via a 1000 5 Ethernet port This connection uses the TSEC2 interface operating in SGMII mode See Chapter 6 Ethernet Interface on page 129 ATCA 9305 User s M
58. Specification v1 0 PICMG 1 R1 0 May 4 2007 http www picmg org RTC Serial Access Real Time Clock Data Sheet M41T00S STMicroelectronics December 2004 Switch BCM56800 Series 20 Port 10 Gigabit Ethernet Multilayer Switch Preliminary Data BCM56802 Sheet Broadcom Corporation Document 56800 DS03 R 12 28 07 http www broadcom com YE Frequently the most current information regarding addenda errata for specific documents may be found on the corresponding web site ATCA 9305 User s Manual 10009109 07 267 Related Documentation u 268 ATCA 9305 User s Manual 10009109 07 A mS S Eu EMBEDDED TECHNOLOGIES Artesyn Embedded Technologies Artesyn and the Artesyn Embedded Technologies logo are trademarks and service marks of Artesyn Embedded Technologies Inc All other product or service names are the property of their respective owners 2014 Artesyn Embedded Technologies Inc
59. Swap Hot Swap FO Sensor specific 0 60 Yes discrete 6F RTM Hot Swap Hot Swap FO Sensor specific 0xCO 0x61 Yes discrete 6F IPMB Physical IPMB Link F1 Sensor specific 0 60 Yes discrete 6F BMC Watchdog Watchdog2 23 Sensor specific 0 60 Yes discrete 6F 204 ATCA 9305 User s Manual 10009109 07 System Management Table 7 48 Discrete Sensors continued Entity Event Name Sensor Type Event Reading Type Instance Gen F W Progress System Firmware Sensor specific 0 60 Progress OF discrete 6F SDRAM POST Memory Sensor specific 0x60 discrete 6F Bus POST Processor 07 Predictive failure 0 60 Yes Discrete 04 Flash POST Memory 0C Sensor specific 0 60 Yes discrete 6F EthSwitch POST Chip Set Predictive failure 0 60 Yes Discrete 04 Cav1 SDRAM POST Memory Sensor specific 0x03 0x60 Yes discrete 6F 1 IIC POST Processor 07 Predictive failure 0x03 0x60 Yes Discrete 04 Cav1 Boot Processor 07 Predictive failure 0x03 0x60 Yes Discrete 04 Cav2 SDRAM POST Memory Sensor specific 0x03 0x61 Yes discrete 6F Cav2 IIC POST Processor 07 Predictive failure 0x03 0x61 Yes Discrete 04 Cav2 Boot Processor 07 Predictive failure 0x03 0x61 Yes Discrete 04 Version change Version Change Sensor specific 0 60 Yes discrete 6F Async Pld Rst Po
60. ability to communicate via PCI bus with Cavium 2 9 31 Reserved 224 ATCA 9305 User s Manual 10009109 07 Management Processor Monitor 9 3 3 Monitor SDRAM Usage Monitor SDRAM usageis typically around 1 MB for monitor code and stack support Please note that the monitor stack grows downward from below where the monitor code resides in the upper 512 KB The monitor C stack will typically not grow beyond 512 KB therefore the upper 1 MB of SDRAM is reserved for monitor use Themonitor has the ability to preserve not overwrite areas of memory defined by the pram environment variable Any writes to these areas can cause unpredictable operation of the monitor 9 4 Monitor Recovery and Updates This section describes how to recover and or update the monitor given one or more of the following conditions e console output the monitor may be corrupted and need recovering see the Recovering the Monitor section e ifthe monitor still functions but is not operating properly then you may need to reset the environment variables see the Resetting Environment Variables section e Ifyou are having Ethernet problems in the monitor you may need to set the serial number since the MAC address is calculated from the serial number variable ATCA 9305 User s Manual 10009109 07 225 Management Processor Monitor 9 4 1 226 Recovering the Monitor 1 Make sure that a
61. accessible via PCI from management processor 71 Processor Complex 3 2 3 2 1 72 PCI The Cavium is a slave device on the PCI bus The Cavium U boot monitor image is provided by the MPC8548 management processor via PCI The MPC8548 monitors the boot status and has the ability to try alternate boot images if the current one fails The CN5860 processor is designed such that another PCI device can initialize its memory interface copy code over PCI into its local memory space and then write a boot release register CN5860 Boot Over PCI The PCI bus is configured to run at 66 MHz in 64 bit conventional PCI mode On power up the CN5860 processor s 16 internal cores are held in reset The MPC8548 management processor performs the following steps 1 Initialize the CN5860 RAM 2 Copy the CN5860 U boot to the CN5860 RAM 3 Copy boot code to the reset vector to jump to the U boot code in RAM 4 Release the CN5860 processor cores from reset 5 Receive return codes from the CN5860 that indicate any boot or POST errors and take the appropriate action The management processor MPC8548 monitor implements a utility to load non volatile memory redundant U boot images for the CN5860 processors The utility tags each copy as primary or secondary The U boot command oct_moninit can used to program a binary boot image for the Octeon processors into the boot flash device of the management CPU The
62. ag BE optional og ye o Boston 00002 mama 072 Bin E mon amm 5 B omw Y m 070 098 8 3 n 5 8 i co IE ig Sa y DE Em m fe E Bg a 8 EB BB memor Umm m mmm BB 13 om U68 d o PM d us7 066 E a Ee 0 0 oo n 0 mm c B m 0 zu 7 n a 0000 ATCA 9305 User s Manual 10009109 07 55 Setup eee Figure 2 7 P2 F1 75 Amp Fuse self resetting m F2 75 Amp Fuse self resetting _ Ethernet CR15 TSEC2 ACTIVITY CR23 MIP1_LED1_R CR24 1 1 02 CR25 MIP1_LED3_R CR26 MIP1_LED4_R CR50 P1_LED_GPIO12_R1 CR51 P1 LED GPIO13 R1 52 1 LED GPIO14 R1 CR53 P1 LED 15 R1 F10 75 Amp Fuse self resetting LED Fuse and Switch Locations Top PCB Rev 1 x CR1 P2 LED GPIO12 R CR2 P2_LED_GPIO13 R CR3 P2_LED_GPIO14 R CR4 P2_LED_GPIO15 R MPC8548 CR13 PQ GREENLED R CR14 PQ OUT CR16 PQ REDLED R Debug CR18 DEBUG_LED1_R CR19 DEBUG_LED2_R CR21 DEBUG_LED3_R _ 22 DEBUG_LED43_R Boot Device CR31 FLO LED R CR32 FL1 LED R CR33 SKT LED R FA SW1 IPMC Reset F3 75 Amp Fuse self resetting IPMP State
63. board should not have been given control of the resource optional 2 Deny carrier controller denies control of resource by the board 184 ATCA 9305 User s Manual 10009109 07 System Management Table 7 33 Bused Resource Status Command continued Type Byte Data Field Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems 7 11 18 Graceful Reset The IPMC supports the Graceful Reboot option of the FRU Control command On receiving such a command the IPMC sets the Graceful Reboot Request bit of IPMC status sends status update notification to the payload and waits for the Graceful Reset command from the payload If the IPMC receives such a command before the payload communication time out time it sends the 0x00 completion code Success to the carrier controller Otherwise the 0xC3 completion code Time Out is sent The IPMC does not reset the payload on receiving the Graceful Reset command or time out If the IPMC participation is necessary the payload must request the IPMC to perform a payload reset The Graceful Reset command is also used to notify the IPMC about the completion of the payload shutdown sequence Table 7 34 Graceful Reset Command Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems Response Data Completion Code PPS IANA Private Enterpr
64. defined by the IPMI specification 08 command request 09 response firmware transfer messages match the format of application messages as determined by the particular device command request response may be present on any node that provides nonvolatile storage and retrieval services reserved 30 network functions 15 pairs 139 System Management Table 7 1 Network Function Codes continued Hex Code Value s Name Type Name 30 3F OEM 30 command request 3F response vendor specific 16 network functions 8 pairs The vendor defines functional semantics for cmd and data fields The cmd field must hold the same value in requests and responses for a given operation to support IPMI message handling and transport mechanisms The controller s Manufacturer ID value identifies the vendor or group 7 3 1 IPMI Completion Codes All IPMI response messages contain a hexadecimal Completion Code field that indicates the status of the operation Table 7 2 Completion Codes Code Description Generic Completion Codes 00 CO FF Command completed normally Node busy command could not be processed because command processing resources are temporarily unavailable Invalid command indicates an unrecognized or unsupported command Command invalid for given LUN Time out while processing command response unavailable Out of space command could not be completed because of a lac
65. enumpci command enumerates the PCI bus when the hardware is the PCI Root Complex in the system Definition enumpci go The go command runs an application at address addr passing the optional argument arg to the called application Definition go addr arg help The help or command displays the online help Without arguments all commands are displayed with a short usage message for each To obtain more detailed information for a specific command enter the desired command as an argument Definition help command iminfo The iminfo command displays the header information for an application image that is loaded into memory at address addr Verification of the image contents magic number header and payload checksums are also performed Definition iminfo addr addr ATCA 9305 User s Manual 10009109 07 Management Processor Monitor 9 14 12 9 14 13 9 14 14 9 14 15 isdram The isdram command displays the SDRAM configuration information valid chip values range from 50 to 57 Definition isdram addr loop The loop command executes an infinite loop on address range Definition loop b w 1 address number_of_objects memmap The memmap command displays the board s memory map layout Definition memmap moninit The moninit command resets the NVRAM and serial number and writes the monitor to flash The ATCA 9305 can be booted from the boot socket for this command to
66. is already stopped itwillremain stopped Ifthe pretime outinterrupt bitis set it will get cleared 1 Ob timer stops automatically when Set Watchdog Timer command and is received 5 3 reserved 2 0 timer use logged on expiration when don t log bit 000b reserved 001b Monitor FRB 2 010b Monitor POST 011b OS Load 100b SMS OS 101b OEM 110b 111b reserved 155 System Management Table 7 9 Set Watchdog Timer Command continued Type Byte Data Field Timer Actions 7 reserved 6 4 pretime out interrupt logged on expiration when don t log bit 0b 000b none 001b SMI 011b Messaging Interrupt this is the same interrupt as allocated to the messaging interface 010b NMI Diagnostic Interrupt 100b 111b reserved 3 reserved 2 0 time out action 000b no action 001b Hard Reset 010b Power Down 011b Power Cycle 100b 111b reserved 3 Pretime out interval in seconds 1 based Request Data continued Timer Use Expiration flags clear Ob leave alone 1b clear timer use expiration bit 7 reserved 6 reserved 5 OEM 4 SMS OS 3 OS Load 2 Monitor POST 1 Monitor FRB 2 0 reserved Initial countdown value Isbyte 100 ms count Initial countdown value msbyte Response Data 156 Completion Code ATCA 9305 User s Manual 10009109 07 System Management ML 7 9 6 Potential race conditions exist with implementation of
67. line See Fig Figure 3 4 for the Cavium CN5860 processor boot sequence See Table 9 6 for default environment variables settings Power up or Reset U Boot Monitor Default Board Initialization U Boot Monitor PCI Monarch Enumerate U Boot Monitor Configure Ethernet Switch Initialize IPMC Execute POST Boot Caviums Boot Cavium processor according to configuration parameters U Boot Monitor Start Autoboot Sequence Boot Operating System Operating System Boot Boot OS image according to configuration parameters ATCA 9305 User s Manual 10009109 07 223 Management Processor Monitor 9 3 2 POST Diagnostic Results The ATCA 9305 Power On Self Test POST diagnostic results are stored as a 32 bit value in I2C NVRAM at the offset 0x07F0 0x07FF Each bit indicates the result of a specific test therefore this field can store the results of up to 32 diagnostic tests Table 9 2 assigns the bits to specific tests Table 9 2 POST Diagnostic Results Bit Assignments Verify address and data lines are intact Verify size and initialization of soldered flash Verify all local I2C devices are connected to the I2C bus 0 Passed the test Reserved 1 Failure detected PCle Time out PCle enumeration skipped by user DOC Embedded Flash Verify presence and ability to access Drive EFD configuration space of DOC 8 Cavium 2 Presence Verify presence and
68. management processor will use this image to start up the Octeon processors Syntax oct_moninit lt image number gt lt octeon processor gt lt image address gt ATCA 9305 User s Manual 10009109 07 Processor Complex Parameters image number 1 or 2 Specifies whether to program the primary or backup image If omitted both images will be updated octeon processor 1 or 2 Specifies which Octeon processor s image is to be updated image address Address of the binary image after loading it in memory e g via TFTP 3 2 2 Reset Each CN5860 can be reset independently of the other processor without affecting its operation This task is performed by the MPC8548 management processor ATCA 9305 User s Manual 10009109 07 73 Cavium Processor Complex Figure 3 2 CN5860 Reset Diagram 3 3V MP PAYLD EN P1 RESET 3 3V PWRGD 4 CN5860 2_5V_PWRGD 1 1 8V PWRGD Processor 1 1 2V PWRGD Pi PWRGD 1 0 PWRGD PQ CORE PWRGD P1 CORE PWRGD P2_RESET PORGE 2 5 Cavium P2 PWRGD Processor 2 RST MIP3_RST 74 ATCA 9305 User s Manual 10009109 07 Processor Complex 3 3 Cavium Ethernet The Ethernet address for your board is a unique identifier on a network The address consists of 48 bits MAC 47 0 divided into two equal parts The upper 24 bits define a unique identifier that has been assigned to Artesyn
69. names this command sets an untagged port based VLAN and the VLAN table entry with the port s default VID In this configuration each port is assigned to one VLAN By default ports are untagged members of the VLAN To add a port as a tagged VLAN member append a t to the port number for example vlan core add 11 3t 4t 7 13t Adding a t suffix to the port name causes the switch to send out packets containing the VLAN tag to be sent out from this port The command applies either to the core switch on the blade specified by the identifier or by the switch on the RTM if present specified by the identifier rtm Definition vlan core rtm add vidl portlistl1 lt vid2 gt lt portlist2 gt vlan core rtm delete lt vidl gt lt vid2 gt vlan core rtm show Example ATCA 9305 User s Manual 10009109 07 Management Processor Monitor To create VLAN 1 on the core switch vlan core add 1 14 15 To add VLAN 11 to the core switch including ports 3 4 7 and 13 Ports 3 4 and 13 shall transmit frames as 802 1q tagged frames Port 7 shall transmit frames untagged ATCA 9305 Mon 1 1 2 gt vlan core add 11 3t 4t 7 13t ATCA 9305 Mon 1 1 2 gt vlan core show VLAN Number 1 Port Numbers 5 6 VLAN Number 2 Port Numbers 7 12 VLAN Number 3 Port Numbers 4 10 VLAN Number 4 Port Numbers 11 13 VLAN Number 5 Port Numbers 0 2 3 VLAN Number 11 Port Numbers 4t 7 139 To de
70. of memory and be reserved not to be cleared on start up or reset Default size of the protected memory region is 0 pram is defined in kilobytes and is a base 10 number The smallest allowable size is 4 4 KB and the largest recommended size is 32768 32 MB pram should be 4 KB aligned otherwise U Boot will round pram to the next 4 KB size sec_bootargs Sets the boot arguments that are passed into the secondary application images when using the bootv command If not defined bootv will pass the bootargs configuration parameters into both the primary and secondary application images shelf_addr ATCA chassis shelf address provided by shelf manager Not defined in default configuration reported at bootup from the IPMC The moninit command does not initialize these variables Each parameter is only defined if a change from the default setting is desired and is not defined after initialization of the environment variables 9 16 Troubleshooting To bypass the full board initialization sequence attach a terminal to the console located on the front of the ATCA 9305 Configure the terminal parameters to be 9600 bps no parity 8 data bits 1 stop bit Reset the ATCA 9305 while holding down the s key Pressing the s key forces a configuration based on default environment variables 9 17 Download Formats The ATCA 9305 monitor supports binary and Motorola S Record download formats as described in the following se
71. packet processing applications in the wireless and transport market segments These markets include data plane packet processor security co processor video compression and pattern matching The ATCA 9305 complies with the SCOPE recommended profile for central office ATCA systems PICMG 3 0 ATCA mechanical specifications E keying and Hot Swap Components and Features The following is a brief summary of the ATCA 9305 hardware components and features Processor The CN5860 processor 15 a highly programmable high performance 16 core architecture operating up to 800 MHz Management Processor The Freescale PowerQUICC MPC8548 processor is a 32 bit enhanced e500 core operating at 1 GHz Ethernet Switch The Broadcom BCM56802 is a sixteen port 10 GbE switch which interconnects the processors using SPI to XAUI bridges The functionality includes both 10 Gbps and 1 Gbps SGMII PHY interfaces Stratix GX Bridge There are two packet routing Altera SPI 4 2 high speed interconnect to XAUI bridges per CN5860 processor Ethernet 10 100 1000BASE T Ethernet ports are accessible via the front panel RJ45 connectors and through the base channel on the back panel The 10 GbE ports route to the back panel through the fabric and RTM connectors ATCA 9305 User s Manual 10009109 07 37 Serial Port The front panel serial port MGT CSL connects to the MPC8548 management proces
72. read 53 100000 1800 100 reads 100 bytes from offset 0x1800 in serial EEPROM 0x53 right shifted 7 bit address and places it in memory at address 0x100000 Definition Read write cnt bytes from devaddr EEPROM at offset off eeprom read devaddr addr off cnt eeprom write devaddr addr off cnt icrc32 The icrc32 computes a CRC32 checksum ATCA 9305 User s Manual 10009109 07 241 Management Processor Monitor 9 10 3 9 10 4 9 10 5 9 10 6 242 Definition icrc32 chip address 0 1 2 count iloop The iloop command reads in an infinite loop on the specified address range Definition iloop chip address 0 1 2 of objects imd The imd command displays the primary bus memory For example imd 53 1800 2 100 displays 100 bytes from offset 0x1800 of IC device 0x53 right shifted 7 bit address The 2 atthe end of the offset is the length in bytes of the offset information sent to the device The serial all have two byte offset lengths The Real Time Clock RTC has a one byte offset length The temperature sensors have zero byte offset lengths Definition imd chip address 0 1 2 of objects imm The imm command modifies the primary memory and automatically increments the address Definition imm chip address 0 1 2 imw The imw command writes fills memory ATCA 9305 User s Manual 10009109 07 Management Processor Monitor 9 10 7 9 10 8 9 11
73. region prior to copying the data The flash region must be manually erased using the erase command prior to using the cp command Definition b w 1 source target count Example Inthis example the command is used to copy 0x1000 32 bit values from address 0x100000 to address 0x80000 gt cp 100000 80000 1000 find The find command searches from base_addr to top_addr looking for pattern For the find command to work properly the size of pattern must match the size of the object flag The a option searches for the absence of the specified pattern Definition find b w 1 a base_addr top_addr pattern ATCA 9305 User s Manual 10009109 07 235 Management Processor Monitor 9 8 4 236 Example In this example the find command is used to search for the 32 bit pattern 0x12345678 in the address range starting at 0x40000 and ending at 0x80000 gt find 1 40000 80000 12345678 Searching from 0 00040000 to 0 00080000 Match found data 0x12345678 Adrs 0x00050a6c gt md The command md displays the contents of memory starting at address The number of objects displayed can be defined by an optional third argument of objects The memory s numerical value and its ASCII equivalent is displayed Definition md b w 1 address of objects Example In this example the md command is used to display thirty two 16 bit words starting at the physical address 0x80000 gt md w
74. starting address of each sector Definition Print information for all flash memory banks flinfo Print information for the flash memory in bank flinfo N protect The protect command enables or disables the flash sector protection for the specified flash sector Protection is implemented using software only The protection mechanism inside the physical flash part is not being used Definition Protect all of the flash sectors in the address range from start to end protect on start end Protect all of the sectors SF first sector to SL last sector in flash bank N protect on N SF SL Protect all of the sectors in flash bank protect on bank N Protect all of the sectors in all of the flash banks protect on all ATCA 9305 User s Manual 10009109 07 Management Processor Monitor 9 10 9 10 1 9 10 2 Remove protection on all of the flash sectors in the address range from start to end protect off start end Remove protection on all of the sectors SF first sector to SL last sector in flash bank protect off N SF SL Remove protection on all of the sectors in flash bank N protect off bank N Remove protection on all of the sectors in all of the flash banks protect off all EEPROM I C Commands This section describes commands that allow you to read and write memory on the serial EEPROMs and I C devices eeprom The eeprom command reads and writes from the EEPROM For example eeprom
75. the TFTP protocol to load application images via Ethernet into the ATCA 9305 s memory Auto Boot You can store specific boot commands in the environment to be executed automatically after reset Flash Programming You can write application images into flash via the U Boot command line The upper 1 MB at the base of flash and 128 KB of each flash bank is reserved for the monitor and environment variables see 8548 Memory Map One megabyte is reserved at the second bank of flash The moninit command will load both banks of flash with the monitor and default environment variables ATCA 9305 User s Manual 10009109 07 219 Management Processor Monitor At power up or after a reset the monitor runs diagnostics and reports the results in the start up display see Figure 9 1 During the power up sequence the monitor configures the board according to the environment variables see MPC8548 Environment Variables on 8548 Environment Variables on page 260 Ifthe configuration indicates that autoboot is enabled the monitor attempts to load the application from the specified device If the monitor is not configured for autoboot or a failure occurs during power up the monitor enters normal command line mode Also the optional e keying environment variable enables connections at power up for debug purposes only to the Update Channel and payload ports that go the ATCA 9305 See Table 9 7 for more information The mo
76. this option If the Set Watchdog Timer command is sent just before a pretime out interrupt or time out is set to occur the time out could occur before the command is executed To avoid this condition itis recommended that software set this value no closer than three counts before the pretime out or time out value is reached Get Watchdog Timer Command This command retrieves the current settings and present countdown of the watchdog timer The Timer Use Expiration flags in byte 5 retain their states across system resets and system power cycles With the exception of bit 6 in the Timer Use byte the Timer Use Expiration flags are cleared using the Set Watchdog Timer command They may also become cleared because of a loss of IPMC power firmware update or other cause of IPMC hard reset Bit 6 of the Timer Use byte is automatically cleared to Ob whenever the timer times out is stopped when the system is powered down enters a sleep state or is reset Table 7 10 Get Watchdog Timer Command Byte Data Field Request Data Response Data 1 Completion Code Response Data 2 Timer Use 7 1b don t log 6 1b timer is started running Ob timer is stopped 5 3 reserved 2 0 timer use logged on expiration if don t log bit 0 000b reserved 001b Monitor FRB 2 010b Monitor POST 011b OS Load 100b SMS OS 101b OEM 110b 111b reserved ATCA 9305 User s Manual 10009109 07 157 System Management Table 7
77. used 10 not used 11 XAUI 10 GB BCM56802 to J30 to optional RTM Stratix II GX bridge 3 Stratix II GX bridge 4 132 ATCA 9305 User s Manual 10009109 07 Ethernet Interface Table 6 1 Ethernet Switch Ports continued Interface Connection XAUI 10 GB BCM56802 to 31 to optional RTM 6 2 3 VLAN Setup The default VLAN configuration is defined in Table 6 2 See vlan on page 258 for the monitor vlan command Table 6 2 VLAN Configuration VLAN Ports 1 1 3 4 2 6 7 3 8 13 4 5 11 5 12 14 6 3 8548 Management Processor Ethernet Address The Ethernet address for your board is a unique identifier on a network The address consists of 48 bits MAC 47 0 divided into two equal parts The upper 24 bits define a unique identifier that has been assigned to Artesyn Embedded Technologies Embedded Computing by IEEE The lower 24 bits are defined by Artesyn for identification of each of our products The Ethernet address for the ATCA 9305 is a binary number referenced as 12 hexadecimal digits separated into pairs with each pair representing eight bits The address assigned to the ATCA 9305 has the following form ATCA 9305 User s Manual 10009109 07 133 Ethernet Interface 6 3 1 134 00 80 xx yy zz 00 80 F9 is Artesyn s identifier The last three bytes of the Ethernet address consist of the port one byte 0x97 port 1 or 0x98 port 2 followed by the serial number two byte
78. 009109 07 System Management 7 13 7 14 If the payload application has registered to these commands via the OpenIPMI library it gets informed and can take all necessary actions before the payload is gracefully rebooted shut down BOOT BANK SUPERVISION SENSOR The Boot Bank Supervision Sensor is intended to provide information on the boot bank from which the payload has booted last The boot bank information received from this sensor may differ from the boot bank information received with the IPMI command Get System Boot Options BOOT FIRMWARE BOOT OPTIONS The ATCA 9305 provides a non volatile memory managed by the IPMC for storing a second set of u boot environment variables Those if present are parsed and interpreted by the monitor during power up Note that the boot parameters in the IPMC storage area have higher priority than the same environment variables which may be configured in the firmware itself Furthermore the u boot environment variables are not overwritten with the values stored in the IPMC memory The boot firmware boot options can be stored read with the IPMI commands Set System Boot Options and Get System Boot Options together with the OEM boot parameter 100 These are defined in OEM Boot Options on page 150 The boot firmware boot options can be modified by the ShMM or across HPI applications The system manager may decide from which boot device the ATCA 9305 shall boot from bparam set and bparam
79. 09 07 List of Tables Table 7 6 Artesyn Boot Option lt 150 Table 7 7 IPMC Watchdog Timer 5 151 Table 7 8 Reset Watchdog Timer Command 154 Table 7 9 Set Watchdog Timer Command 155 Table 7 10 Get Watchdog Timer Command 157 Table 7 11 6 rmm 159 Table 7 12 Get FRU LED Properties Command 160 Table 7 13 Get LED Color Capabilities 161 Table 7 14 Set FRU LED State Command 163 Table 7 15 Get FRU LED State 164 Table 7 16 Vendor Command Summary 2 2 167 Table 7 17 Get Status Command 168 Table 7 18 Get Serial Interface Properties Command 172 Table 7 19 Set Serial Interface Properties Command 173 Table 7 20 Get Debug Level Command 174 Table 7 21 Set Debug Level Command 175 Table 7 22 Get Hardware Address
80. 1 5 Scratch Register 87 3 7 Headersand Connectors 4 89 3 7 1 COP TAGHeaders nee a 89 3 1 2 Console Po tS RE 90 4 Management Complex 91 ATI sIMPC8548 Processor pe tete on ee Ne oe 91 4 1 1 MPC8548 Memory Map ince boss EY n 93 41 2 ChipsSelects nen a er ey re 97 4 2 MEMON cer ernennen e Ro aeri 99 4 21 SDRAM c cents a ee ea eae Rhee 99 4 2 2 wes eben 99 4 2 2 1 512 anne ade rer nn 99 4 222 Em 100 6 ATCA 9305 User s Manual 10009109 07 Contents 4 2 2 3 1 ee 100 4 2 2 4 reete e xac oe 100 43 whee es 100 2 31 UU 101 4 4 2 u cada 101 4 5 Management Processor Header and Serial 103 4 51 JTAG COP Interface 2 103 4 5 2 Serial Debug Port 2 4 4 104 gt Management Processor 105 5 1 MPC8548 PLD 5
81. 10 Get Watchdog Timer Command continued Type Response Data Byte Data Field Timer Actions 7 reserved 6 4 pretime out interrupt 000b none 001b SMI 010b NMI Diagnostic Interrupt 011b Messaging Interrupt this would be the same interrupt as allocated to the messaging interface 100b 111b reserved 3 reserved 2 0 time out action 000b no action 001b Hard Reset 010b Power Down 011b Power Cycle 100b 111b reserved Pretime out interval in seconds 1 based Timer Use Expiration flags 1b timer expired while associated use was selected 7 reserved 6 reserved 5 OEM 4 SMS OS 3 OS Load 2 Monitor POST 1 Monitor FRB 2 0 reserved Initial countdown value Isbyte 100 ms count Initial countdown msbyte 158 ATCA 9305 User s Manual 10009109 07 System Management Table 7 10 Get Watchdog Timer Command continued Type Byte Data Field Response Data 8 Present countdown value Isbyte The initial countdown value and present countdown values should match immediately after the countdown is initialized Set Watchdog Timer command and after a Reset Watchdog Timer has been executed Note that internal delays in the IPMC may require software to delay up to 100 ms before seeing the countdown value change and be reflected in the Get Watchdog Timer command Present countdown value msbyte 7 10 FRULEDs This section describ
82. 10 Reset Command 1 0X24 2 2 2 24 24 2 112 Table 5 11 Reset Command 2 0x28 une pe ere ee rer EX NATRI ann 112 Table 5 12 Reset Command 3 0 2 0 0 2 113 Table 5 13 Reset Command 4 0x30 2 114 Table 5 14 Reset Command 5 0x34 22 2 114 Table 5 15 Reset Command Sticky 1 0x38 115 Table 5 16 Reset Command Sticky 2 030 2 116 Table 5 17 Boot Device Redirection 0x50 2 2 116 Table 5 18 Miscellaneous Control 0 54 117 Table 5 19 Low Frequency Timer Settings 118 Table 5 20 RTM State 0 60 119 Table 5 21 RTM GPIO Control 0 4 0 02 7 2 2 119 Table 5 22 RTM Control 0XbB an conden ue u DONE E EN 120 Table 5 23 1 Clock Divisor Control 0x70 121 Table 5 24 2 Clock Divisor Control 0x74 121 Table 5 25 0X78 T 122 Table 5 26 GPIO 1 0 80
83. 109 07 Management Complex 4 2 4 2 1 4 2 2 4 2 2 1 Memory The memory devices in the management complex consist of 1 GB DDR2 SDRAM e 512 KB socketed flash MB soldered NOR flash two redundant banks of 4 MB each 1 GB soldered NAND flash optional 512 Mb or 64 MB soldered NOR flash SDRAM This is a specialized socketed 200 pin small outline clocked dual in line memory module SO CDIMM It provides Error correcting Code ECC on the SDRAM memory bus operating at 200 MHz The MPC8548 detects all double bit errors multi bit errors within a nibble and corrects all single bit errors The 128M X 72 DDR2 SDRAM is a high density un buffered SO CDIMM This module consists of nine 128x8 bit with eight banks DDR2 SDRAMs zero delay phase lock loop PLL clock and 2 serial presence detect SPD EEPROM The SDRAM starts at physical address 0000 00001 Flash There are several flash devices on the local bus interfacing the CPLD and MPC8548 processor The four soldered flash banks are labeled 1 through 4 e Banks 1 and 2 are the MPC8548 U boot banks see 4M These boot banks are used in the boot redirection scheme see BOOT DEVICE REDIRECTION BDR Banks 3 and 4 are physically one device but appear in the software as two banks of 32 MB see 64 These for general purpose storage 512 KB The 512 KB of 32 pin PLCC socketed flash starts at physical address
84. 3 VLAN ee in ash 133 6 3 8548 Management Processor Ethernet Address 133 6 3 1 Front Panel 134 7 SystemiManagement se 0 nenn 137 7 1 OVEIVIEW ER 137 7 2 Overview 137 7 3 55 ee aree ee 139 7 3 1 Completion 2 2 140 7 4 IPMB Protocol ua nina 142 7 5 SIBEPrOEtOCOL 143 7 6 Message Bridging une ne eo 145 7 7 Standard Commands 2 2 2222 4 147 7 8 OEM 4 2452 he p RE IO shi 150 7 9 Watchdog Timer Commands 2 151 7 9 1 Watchdog Timer 5 2 152 7 9 2 Watchdog Timer Use Field and Expiration 152 7 9 2 1 Using the Timer Use Field and Expiration 153 7 9 3 Watchdog Timer 153 7 9 3 1 Monitor Support for Watchdog Timer 153 8 ATCA 9305 User s Manual 10009109 07 Contents 7 9 4 Reset Watchdog Timer Command
85. 7 Sicherheitshinweise Betrieb Datenverlust Ziehen Sie das Board im laufenden Betrieb heraus obwohl die Hot Swap LED noch nicht leuchtet f hrt das zu Datenverlust Warten Sie deshalb bis die Hot Swap LED blau leuchtet bevor Sie das Board herausziehen Besch digung von Schaltkreisen Elektrostatische Entladung und unsachgem er Ein und Ausbau des Produktes kann Schaltkreise besch digen oder ihre Lebensdauer verk rzen Bevor Sie das Produkt oder elektronische Komponenten ber hren vergewissern Sie sich dass Sie in einem ESD gesch tzten Bereich arbeiten Fehlfunktion des Produktes Fehlerhafter Ein und Ausbau des Produktes kann zur Besch digung des Produktes f hren Stellen Sie deshalb sicher dass das Produkt mit allen Steckern mit der Systembackplane verbunden ist und ber alle Zone 1 Anschl sse mit Spannung versorgt wird Besch digung des Produktes Fehlerhafte Installation des Produktes kann zu einer Besch digung des Produktes f hren Verwenden Sie die Handles um das Produkt zu installieren deinstallieren Auf diese Weise vermeiden Sie dass das Face Plate oder die Platine deformiert oder zerst rt wird Besch digung des Produktes und von Zusatzmodulen Fehlerhafte Installation von Zusatzmodulen kann zur Besch digung des Produktes und der Zusatzmodule f hren Lesen Sie daher vor der Installation von Zusatzmodulen die zugeh rige Dokumentation Besch digung des Boards Hohe Luftfeuchtigkeit und Kondensat
86. 80 00001 6 and is used for Engineering code The StrataFlash P33 features high performance fast asynchronous access times low power and flexible security options ATCA 9305 User s Manual 10009109 07 99 Management Complex 4 2 2 2 4 2 2 3 4 2 2 4 4 3 100 4M The two 4 MB soldered flash devices are used for MPC8548 boot code This redundant bank configuration allows booting from either bank in case of corruption in one bank See BOOT DEVICE REDIRECTION BDR on page 194 The SST NOR flash devices are organized as 4Mx8 ina dual bank architecture for concurrent read write operation with hardware and software data protection schemes These devices start at physical addresses 380 0000 6 boot bank 1 and F3C0 000046 boot bank 2 1 GB optional The ATCA 9305 uses 1 GB of M Systems DiskOnChip mDOC H3 NAND flash starting at physical address 00 0000 6 for non volatile RAM storage and True Flash File System TFFS This memory incorporates an embedded flash controller and memory and includes hardware protection and security enabling features an enhanced programmable boot block enabling eXecution In Place XIP functionality using 16 bit access user controlled One Time Programmable OTP partitions and 6 bit Error Detection Code Error Correction Code EDC ECC 64 MB The 64 MB soldered NOR flash starts at physical address 400 000015 bank 3 The 64 Mbit P33 device provides CN5860 code storage and non volatile mem
87. 9 11 1 Definition imw chip address 0 1 2 value count inm The inm command modifies 2 memory reads it and keeps the address Definition inm chip address 0 1 2 iprobe The iprobe command probes to discover valid primary bus chip addresses Definition iprobe IPMC Commands IPMI Baseboard Management Controller BMC watchdog is supported and serviced throughout the monitor boot process The BMC watchdog is disabled if the monitor goes to the monitor prompt bootdev The bootdev command gets or sets the initial boot bank Get prints out the flash bank set as initial boot device Definition bootdev get The sets the hardware strapping for the initial boot device bootdev set bank ATCA 9305 User s Manual 10009109 07 243 Management Processor Monitor 9 11 2 9 11 3 244 Where lt gt is either or b1 for the corresponding flash bank b3 to boot from socket and if a shunt is installed on 9 1 2 bparams_get This command lists all name value pairs stored in the IPMC storage Definition bparams_get bparams_set This command stores u boot environment settings into a non volatile storage in the IPMC see Artesyn Boot Option Parameters on page 150 parameter 100 These settings are read during startup after the u boot environment settings have been initialized from flash They have therefore higher precedence than the settings stored in flash Definition T
88. A could result in death or serious injury III III ISI IIT LI IIA Indicates hazardous situation which if not avoided may result in minor or moderate injury XOCCOUCCCROUX KIAK KAKKA AKK OUS MK OU XIOOCCOGQUCCQOUGOGOUUOGQUUOQQCCC Indicates a property damage message No danger encountered Pay attention to important information ATCA 9305 User s Manual 10009109 07 35 About this Manual Summary of Changes This manual has been revised and replaces all prior editions 10009109 00 January 2009 10009109 01 April 2009 10009109 02 July 2009 Original release Ad
89. Control FC7F FFFF 40 0060 RTM GPIO State FC48 0000 40 0064 Miscellaneous Control FC47 FFFF FC40 0050 Boot Device Redirection FC40 0000 FC40 0040 Semin 1 FC40 003c _ Reset Command Sticky 2 FC40 0038 __ Reset Command Sticky 1 40 0034 Reset Command 5 FC40 0030 Reset Command 4 FC40 002C Reset Command 3 FC40 0028 Reset Command 2 40 0024 Reset Command 1 40 0020 Dont FC40001C LED FC40 0018 40 0014 FC40 0010 Hardware Configuration 0 FC40 000C PLL Configuration FC40 0008 PLD Version FC40 0004 Hardware Version Product ID PCI 1 5 GB SDRAM DDR2 2 GB 0000 0000 94 ATCA 9305 User s Manual 10009109 07 Management Complex Table 4 2 MPC8548 Address Summary Hex Physical Address Access Mode Register Description See Page FFF8 0000 R W Boot window 512 KB FF80 0000 reserved 7 5 MB FF70 0000 MPC8548 CCSRBAR 1MB FC88 0000 reserved 46 MB FC80 0000 Socketed flash optional 512 KB 99 FC48 0000 reserved 3 5 MB FC40 00DCO Serial IRQ Interrupt 2 127 FC40 00D8 R W Serial IRQ Interrupt 1 126 FC40 00D0 Low Pin Count LPC Bus Control 125 FC40 008C IPMP IPMC GPIO Control 125 FC40 0088 GPIO Data Input 124 FC40 0084 Cavium GPIO Data Output 123 FC40 0080 R W GPIO Control 123 FC40 0078 Altera JTAG Chain Software Control 122 FC40 0074 Cavium 2 C_MUL Clock Divisor 121 Control Caviu
90. Core Frequency 1 PQCFO MPC8548 Core Frequency 0 PQDDRF MPC8548 DDR SDRAM Fast Jumper Settings These read only bits may be read by software to determine the current jumper settings See the jumper descriptions on Page No 61 Table 5 7 Jumper Settings 0x18 Bits Function Description ATCA 9305 User s Manual 10009109 07 109 Management Processor CPLD Table 5 7 Jumper Settings 0x18 continued Bits Function Description 4 SJ Cavium Boot Flash Jumper 0 Installed processors boot from soldered flash 1 Not installed Cavium processors boot from socket 3 BOOT Boot PCI Jumper 0 Installed boot from flash socket or soldered per bit 4 1 Not installed boot over PCI from the MPC8548 2 REDIR Boot Redirect Jumper 0 Installed disables boot redirection 1 Not installed enables boot redirection 1 IG ROM Ignore SROM 0 Not installed SROM is used for initialization default 1 Installed disables SROM uses default values in monitor code 0 BT SKT Boot from Socket 0 Not installed enables MPC8548 to boot from soldered flash default 1 Installed enables MPC8548 to boot from socketed flash 5 1 7 LED Writing a one to an LED bit lights that LED During monitor power up the debug LEDs are used to display the software progress Table 5 8 LED 0x1C Bits Function Description MPC8548 red LED Lit on power up and turned off when the monitor finishes boot up
91. Embedded Technologies Embedded Computing by IEEE The lower 24 bits are defined by Artesyn for identification of each of our products The Ethernet address for the ATCA 9305 is a binary number referenced as 12 hexadecimal digits separated into pairs with each pair representing eight bits The address assigned to the ATCA 9305 has the following form 00 80 F9 xx yy zz 00 80 F9 is Artesyn s identifier The last three bytes of the Ethernet address consist of the port one byte Ox99 SPI 1 0x9A SPI 2 Ox9B SPI 3 or 0x9C SPI 4 followed by the serial number two byte hexadecimal The ATCA 9305 Cavium has been assigned the Ethernet address range 00 80 F9 99 00 00 to 00 80 F9 9C FF FF The format is shown in Table 3 4 Table 3 4 Ethernet Port Address MAC Description Ethernet Identifier hex Byte 5 LSB of serial number in hex MSB of serial number in hex SPI 1 SPI2 SPI 3 SPI 4 Assigned to Artesyn by IEEE ATCA 9305 User s Manual 10009109 07 75 Cavium Processor Complex 3 4 3 4 1 76 The last two bytes MAC 15 0 are calculated from the serial number stored in the Cavium EEPROM This corresponds to the following formula 1000 where is the unique serial number assigned to each board So if an ATCA 9305 serial number is 1032 the calculated value is 32 2016 and the default Ethernet port addresses Cavium 1 SPI 1 MAC address is 0x00 0x80 OxF9 0x99 0x00 0x20 e Cavium 1 SPI
92. IPMI Definition sensor probe read dump Sensor probe prints out each sensor number and name sensor probe sensor number Sensor read prints out the sensor reading for sensor sensor read sensor number Sensor dump prints out the raw Sensor Data Record SDR information for sensor Sensor dump sensor number Environment Parameter Commands The monitor uses on board non volatile memory for the storage of environment parameters Environment parameters are stored as ASCII strings with the following format Parameter Name Parameter Value Some environment variables are used for board configuration and identification by the monitor The environment parameter commands deal with the reading and writing of these parameters Refer to MPC8548 Environment Variables on page 260 for a list of monitor environment variables ATCA 9305 User s Manual 10009109 07 247 Management Processor Monitor 9 12 1 9 12 2 9 12 3 248 Redundant environment parameters allow you to store a backup copy of environment parameters should they ever become corrupt The redundant environment parameters are only used if the main parameters are corrupt To save environment variables 1 Use moninit to save default environment variables to both primary and secondary environment parameters 2 Use saveenv to save to the primary environment variables 3 Set next save to the secondary image printenv The printenv comman
93. LK to CCB clock ratio and the CCB to CORE clock ratio using valid values from the MPC8548E PowerQUICC III Integrated Processor Family Reference Manual The changes take affect when the processor is reset for example the software hard reset command or watchdog timer expires Default values are restored when the board is power cycled front panel reset is pressed or receives a PCI reset that was not the result of the MPC8548 software initiating a PCI RSTOUT command Table 5 5 PLL Reset Configuration 0 0 Function Description reserved CCCB2 CCB2 to CORE clock ratio 1 CCB1 to CORE clock ratio CCCBO CCBO to CORE clock ratio CCBSYS3 SYSCLOCK3 to CCB clock ratio CCBSYS2 SYSCLOCK2 to CCB clock ratio ATCA 9305 User s Manual 10009109 07 Management Processor CPLD 5 1 5 5 1 6 Table 5 5 PLL Reset Configuration 0 0 continued Bits Function Description 5 51 SYSCLOCK1 to CCB clock ratio CCBSYSO SYSCLOCKO to CCB clock ratio Hardware Configuration 0 The read only HCRO allows the MPC8548 monitor software to easily determine specific hardware configurations such as the processor clock and MPC8548 DDR memory Table 5 6 Hardware Configuration 0 0x10 Bits Function Description 7 0 6 P33P P33 StrataFlash is Present 5 RST_IND_CLR Clear the Reset Indication to the IPMC controller 4 Frequency 1 Frequency 0 MPC8548
94. NA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems Response Data Completion Code PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems Bits 7 5 reserved Bit 4 IPMB Dump Enable If setto 1 the IPMC provides a trace of IPMB messages that are arriving to going from the via 0 or IPMB L Bit 3 Payload Logging Enable If set to 1 the IPMC provides a trace of SIPL activity on the Payload interface onto the Serial Debug interface Bit 2 Alert Logging Enable If set to 1 the IPMC outputs important alert messages onto the Serial Debug interface Bit 1 Low level Error Logging Enable If set to 1 the IPMC outputs low level error diagnostic messages onto the Serial Debug interface Bit 0 Error Logging Enable If set to 1 the IPMC outputs error diagnostic messages onto the Serial Debug interface 174 ATCA 9305 User s Manual 10009109 07 System Management 7 11 5 Set Debug Level The Set Debug Level command sets the current debug level of the IPMC firmware Table 7 21 Set Debug Level Command Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems Request Data 4 Bits 7 5 reserved Bit 4 IPMB Dump Enable If set to 1 the IPMC provides a trace of IPMB messages that are arriving to going from the IPMC 0 or IPMB L Bit 3 Payload Logging Ena
95. ON CN58XX NSP revision 1 Core clock 750 MHz DDR clock 266 MHz 533 Mhz data rate DRAM 4096 MB Flash 4 MB Clearing DRAM done PCI console init succeeded 1 consoles Net octspi0 octspil RLDRAM not present Octeon BIST Passed POST i2c PASSED POST memory PASSED 2 ATCA 9305 Mon 0 9 gt 1024 bytes each There will be either a 1 or 2 in front of the monitor prompt indicating which Cavium processor is prompting Power up Reset Sequence The Cavium CN5860 processor follows the boot sequence in Figure 3 4 before auto booting the operating system or application software At power up or board reset the monitor performs hardware initialization diagnostic routines autoboot procedures and if necessary invokes the command line See Table 3 6 for default Cavium environment variables settings 77 Cavium Processor Complex Figure 3 4 Power up Reset CN5860 Boot Sequence Flowchart P Power up or Reset U Boot Monitor Default Board Initialization U Boot Monitor PCI Monarch Enumerate U Boot Monitor Configure Ethernet Switch Initialize IPMC Execute POST Boot Caviums Boot Cavium processor according to configuration parameters U Boot Monitor Start Autoboot Sequence Boot Operating System Operating System Boot Boot OS image according to configuration parameters 78 ATCA 9305 User s Manual 10009109 07 3 4 3 3 4 3 1
96. Payload Reset This signal is used by the management controller to resetthe payload Monitor Booted This signal indicates to the management controller that a valid monitor image has finished booting and the watchdog can be disabled Power Good This signal indicates to the management controller that the payload is powered When payload power is applied the BMC watchdog will start Force Boot Socket If a shunt is present on J9 1 2 the controller sets the boot location to socket flash with this signal Payload Reset Indication When reset this signal is held high by the payload until itis cleared by the IPMC using the payload reset indication clear signal Boot Select These signals select the boot device Payload Reset Indication Clear This signal clears the payload reset indication ATCA 9305 User s Manual 10009109 07 197 System Management 7 16 u 7 16 1 198 MESSAGE LISTENERS Payload port dynamic control can be implemented via message listeners The payload can add itself as a message listener to any message destined for the IPMC target either over IPMB 0 the payload serial interface When the IPMC receives a subscribed message the IPMC firmware copies the message into the payload s LUN 10 Receive Message Queue and notifies the payload an unprintable character ASCII 07 BELL The payload receives the message as described in Message Bridging The message listener list is only eight e
97. ROM 2 User NVRAM EEPROM 1 DDR2 SDRAM SO CDIMM M41T00 RTC ATCA 9305 User s Manual 10009109 07 101 Management Complex The two 5 store non volatile information such as board monitor and operating system configurations as well as customer specific items Table 4 6 MPC8548 NVRAM Memory Map Window EEPROM Address Offset hex Description Size bytes EEPROM 1 Ox1FFO Ox1 FFF Boot verify secondary area monitor 16 OxA2 Ox1FEO Ox1 FEF Boot verify primary area monitor 16 write Ox1EEO Ox1FDF Operating system parameters monitor 256 0x0000 x1EDF User defined 7903 EEPROM 2 0x0900 0x1FFF Artesyn reserved area 5887 0x0800 0x08FF Miscellaneous 256 inte 0x07F0 0x07FF Power on Self test POST 16 0x0000 0x07EF User defined 2032 protected protected Both write protected Protection can be enabled or disabled the Management Processor CPLD See also Miscellaneous Control page 117 102 ATCA 9305 User s Manual 10009109 07 Management Complex 45 Management Processor Header and Serial Port 4 5 1 Interface optional The management complex uses header P2 for debug purposes Table 4 7 Serial Debug Connector P2 Pin Signal Description PQ_TDO Test Data Output is the serial data output as well as test and programming data no connect PQ_TDI Test Data Input is the serial input pin for in
98. System Management 7 11 22 Set Local FRU LED State The Set Local FRU LED State command is used to change the local state of a FRU LED Table 7 38 Set Local FRU LED State Command Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems intel 4 FRU Device ID 5 LED ID 00h Blue LED Hot Swap 01h LED 1 OOS 02h LED 2 03h LED 3 04h FEh OEM defined LEDs FFh Lamp Test all LEDs under management control are addressed 6 LED Function 00h LED off override O1h FAh LED blinking override FBh Lamp Test state Turn on LED specified in byte 3 for the duration specified in byte 5 then return to the highest priority state FCh LED state restored to Local Control state FDh FEh reserved FFh LED on override 7 On Duration LED on time is measured in tens of milliseconds Lamp Test time in hundreds of milliseconds if byte 4 FBh time value must be less than 128 Other values when Byte 4 FBh are reserved Otherwise this field is ignored and shall be set to Oh multi color LEDs 8 Color parameter specifies the color of the LED in the local state for 9 If the off first flag parameter is 0 the on part of the blink cycle of the LED precedes the off part of the cycle Otherwise the off part of the blink cycle precedes the on part of the cycle 188 ATCA 9305 User s Manual 10009109 07 System Management Table 7 38 Set Local FRU LED State Command
99. Systems ATCA 9305 User s Manual 10009109 07 191 System Management 7 11 25 Update Threshold Sensor The Update Threshold Sensor command is used to change the state of a threshold sensor controlled by the payload Table 7 41 Update Threshold Sensor Command Type Byte Data Field Request Data PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems Sensor ID parameter identifies the payload controlled threshold sensor that has to be updated Request Data Update flags 0 0 sensor initialization is complete 1 sensor is in the initial update state 1 2 reserved set to 0 3 0 globally disable events from the sensor 1 leave the global event enable bit intact 4 0 globally enable events from the sensor 1 leave the global event enable bit intact 5 0 globally disable sensor scanning 1 leave the global scanning enable bit intact 6 0 globally enable sensor scanning 1 leave the global scanning enable bit intact 7 reserved set to 0 6 New raw reading of the sensor Response Data Completion Code PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems 7 12 ASYNCHRONOUS EVENT NOTIFICATION To enable payload applications to be informed about graceful shutdown reboot requests the FRU Activate Deactivate and FRU Control Graceful Reboot command message is routed as a LUN2 message to the payload interface 192 ATCA 9305 User s Manual 10
100. _get is supported with the latest u boot version ATCA 9305 User s Manual 10009109 07 193 System Management 7 15 194 The boot options need to be stored as a sequence of zero terminated strings The following table describes in detail the format of the boot options to be used when setting or reading the System Boot Options parameter 100 Table 7 42 Boot Options Format Byte Description Number of bytes used for boot parameters LSB first The number of bytes must be calculated and written into these two bytes by the software which writes into the storage area The values 0x0000 and OxFFFF indicate that not data has been written to the storage area If you are reading from the storage area and you find any of these two values your software should assume that no boot firmware boot options have previously been written to the storage area Boot parameters data The boot parameters are stored as 5 text with the following general format name value where all name value pairs are separated by a zero byte The end of the boot parameter data is indicated by two zero bytes Allowed and supported name value pairs are blade specific n 1 n 2 16 bit checksum over the boot parameters data section LSB first When writing to or reading from the storage area you can only read ore write chunks of 16 bytes at a time For this reason the IPMC memory is divided into numbered blocks of 16 bytes which need
101. accepts three different argument formats string numeric and symbolic All command arguments must be separated by spaces with the exception of argument flags which are described below e Monitor commands that expect numeric arguments assume a hexadecimal base e All monitor commands are case sensitive Somecommands accept flag arguments A flag argument is a single character that begins with a period There is no white space between an argument flag and a command For example md b 80000 is a valid monitor command while md b 80000 is not Some commands may be abbreviated by typing only the first few characters that uniquely identify the command For example you can type h instead of help However commands cannot be abbreviated when accessing online help You must type help and the full command name Command Help Access all available monitor commands by pressing the key or entering help Access the monitor online help for individual commands by typing help lt command gt The full command name must be entered to access the online help ATCA 9305 User s Manual 10009109 07 Management Processor Monitor 9 5 3 9 6 9 6 1 9 6 2 9 6 3 Typographic Conventions In the following command descriptions text Courier shows the command format Square brackets enclose optional arguments and angled brackets lt gt enclose required arguments Italic type indicates a variable or field that requires input Boo
102. age of the Product and Additional Devices and Modules Incorrect installation or removal of additional devices or modules may damage the product or the additional devices or modules Before installing or removing additional devices or modules read the respective documentation Operation Board Damage Board surface High humidity and condensation on the board surface causes short circuits Do not operate the board outside the specified environmental limits Make sure the board is completely dry and there is no moisture on any surface before applying power Board Overheating and Board Damage Operating the board without forced air cooling may lead to board overheating and thus board damage When operating the board make sure that forced air cooling is available in the shelf Injuries or Short Circuits Board or power supply In case the ORing diodes of the board fail the board may trigger a short circuit between input line A and input line B so that line A remains powered even if it is disconnected from the power supply circuit and vice versa To avoid damage or injuries always check that there is no more voltage on the line that has been disconnected before continuing your work Hot Swap Installing the board into or removing it from a powered system not supporting hot swap or high availability causes board damage and data loss Therefore only install it in or remove it from a powered system if the system itself supports hot swap
103. and Power on Self Testing POST PQGREEN MPC8548 green LED 5 SWLEDCLK Ethernet Switch LED Clock 4 SWLEDDAT Ethernet Switch LED Data 110 ATCA 9305 User s Manual 10009109 07 Management Processor CPLD Table 5 8 LED 0x1C continued Bits Function Description 3 DEBUGLED3 LED CR22 2 1 0 DEBUGLEDO DEBUGLED2 LED CR21 DEBUGLED1 LED CR19 LED CR18 5 1 8 Reset Event This read only register contains the bit corresponding to the most recent event which caused reset When power is first applied the FP_PSH_BUTTN reset event is not latched into the Reset Event register this is the Power on Reset POR event Front panel reset events which occur after power up will be latched M N At power up the FRST_PWR_UP defaults to 1 Table 5 9 Reset Event 0x20 Bits Function Description RTM push button CPUHRR Software Hard Reset Set to 1 when the last reset was caused by a write to the Reset Command register CPU Hard Reset Request Setto 1 when a COP header or software issued Soft Reset SRESET has occurred Set to 1 when a COP header Hard Reset HRESET has occurred SBR Setto 1 when a Payload Reset from the IPMC has occurred Software Board Reset Setto 1 when the IPMC software issued the board payload reset ATCA 9305 User s Manual 10009109 07 111 Management Processor CPLD 5 1 9 5 1 10 112 Table 5 9 Reset Event 0
104. anual 10009109 07 91 Management Complex eee Figure 4 1 8548 Management Processor Complex Block Diagram 1 Ad s Data Management Processor Complex CORJTAG Management Processor PQDDR2 SDRAM P PCle x4 PCIBus ToCavium Processor 2 amp Ethernet Switch 8548 5 1 __ BCM56802 XAUI 10 Gb Switch 92 ATCA 9305 User s Manual 10009109 07 4 1 1 Management Complex The MPC8548 processor has the following features Table 4 1 MPC8548 Features L1 Cache Description 32 kilobyte data and instruction caches with parity protection 32 byte line eight way set associative L2 Cache 512 kilobytes eight way set associative CPU Core Speed 1 GHz with a 400 MHz DDR2 bus DDR2 Memory Controller Dual I2C Controllers Boot Sequencer 64 bit data interface four banks of memory supported each up to 4 GB full ECC support Two wire interface master or slave 2 support Loads configuration data from serial ROM at reset via the I C interface Ethernet Four 10 100 1000 enhanced three speed controllers eTSECs full half duplex support MAC address recognition Local Bus Controller LBC PCI DDR2 SDRAM memory controller General Purpose Chip Select Machine GPCM three User Programmable Machines UPM eight chip selects support eight external slaves 64 bit PCI 2 2 compatible
105. ardware Reference Manual for more detailed information on the memory map Table 3 2 Cavium Address Summary Hex Physical Address Register Description 1 2000 0000 0000 reserved 1 1 00 0000 0000 Hardware registers 1 1 00 0000 0000 PCI Memory Space 6 1 1000 0000 0000 PCI Memory Space 5 This depends on how much memory is installed ATCA 9305 User s Manual 10009109 07 Table 3 2 Address Summary continued Cavium Processor Complex Hex Physical Address 1 1C00 0000 0000 1 1800 0000 0000 1 1400 0000 0000 1 1910 0000 0000 Register Description PCI Memory Space 4 PCI Memory Space 3 PCI I O Space reserved 1 1900 0000 0000 PCI Special Space 1 0700 0000 0000 CN58xx Registers 1 0001 0000 0000 1 0000 0000 0000 0 0004 1000 0000 0 0004 0000 0000 reserved Local Boot Bus reserved DDR2 SDRAM middle block 256 512 MB 0 0000 2000 0000 DDR2 SDRAM upper block 512 MB 2 0 0000 1000 0000 reserved 0 0000 0000 0000 This depends on how much memory is installed Table 3 3 Memory Map DDR2 SDRAM bottom block 256 MB Address Range on Address on Octeon Management Processor Processor Description 0x88000000 Ox88ffffff 0x20000000 Local memory of Octeon 1 accessible via PCI from management processor 0x98000000 0x98ffffff ATCA 9305 User s Manual 10009109 07 0x20000000 Local memory of Octeon 3
106. are on ATCA 9305 6806800 36 Programmer s Reference A 2 Technical References Further information on basic operation and programming of the ATCA 9305 components can be found in documents listed in Table A 2 Table A 2 Technical References Device Interface ATCA Document AdvancedTCA Base Specification PICMG 3 0 Revision 2 0 March 18 2005 Engineering Change Notice 3 0 1 0 001 PICMG 3 0 R2 0 ECN 3 0 2 0 001 June 15 2005 Ethernet Fibre Channel for AdvancedTCA Systems PICMG 3 1 Revision 1 0 January 22 2003 http www picmg org ATCA 9305 User s Manual 10009109 07 265 Related Documentation Table A 2 Technical References continued Device Interface Document CPU Networks OCTEON Plus CN58XX Hardware Reference Manual CN5860 Cavium Networks CN58XX HM 1 2 Sept 2008 MPC8548 http www caviumnetworks com MPC8548E PowerQUICC III Integrated Processor Family Reference Manual Freescale Semiconductor Inc MPC8548ERM Rev 2 02 2007 http www freescale com DRAM 576Mb x9 x18 x36 2 5V VEXT 1 8C VDD HSTL CIO RLDRAM Il Data Sheet Micron Technology Inc 576Mb_RLDRAM_II_CIO_D1 fm Rev C 9 07 EN http www micron com EEPROM Atmel 2 Wire Serial EEPROM 64K 8192 x 8 Preliminary Data Sheet Atmel Corporation 5174 5 6 07 http www atmel com Ethernet 10 100 1000BASE T Gigabit Ethernet Transceiver Data Sheet 54615 Broad
107. arted 6 BOOTSEL1 IPMC successful boot indication BOARD_BOOTED 5 reserved ATCA 9305 User s Manual 10009109 07 Management Processor CPLD Table 5 17 Boot Device Redirection 0x50 continued Bits Function Description 3 NFBS Nand Flash Busy Signal 2 B 4 BSJ Boot from Socket Jumper A shunt on J9 1 2 selects the 512KB socketed ROM as the boot device see Figure 2 11 DS Active boo t device is socket BDF1 Active boot device is flash 2 BDFO Active boot device is flash 1 5 1 17 Miscellaneous Control This register includes two bits for manually toggling the MPC8548 I C bus Table 5 18 Miscellaneous Control 0x54 Function P33WP SROM1WP SROMOWP FLASH1WP Description 0 Write Protect disabled default until the monitor boots 1 Write Protect enabled 0 Write Protect disabled 1 Write Protect enabled default 0 Write Protect disabled 1 Write Protect enabled default 0 Write Protect disabled default until the monitor boots 1 Write Protect enabled FLASHOWP 0 Write Protect disabled default until the monitor boots 1 Write Protect enabled NANDWP 0 Write Protect disabled 1 Write Protect enabled default ATCA 9305 User s Manual 10009109 07 I2CSDA Data line 0 Drive a 0 onto the I2C SDA line 1 Drive a 1 onto the I2C SDA line 117 Management Processor CPLD Table 5 18 Miscellaneous Control 0x54 c
108. ases the region in the flash memory where the component image will be written Component Upload This step is designed to upload the component image via IPMB or payload interface and write it into the flash memory Component Activation This step activates the previously upgraded component This step can be deferred and performed later For more details refer to the HPM 1 specification listed in Table A 2 IPMC Headers This JTAG header JP1 is available for in system programming of the CPLD Table 7 52 CPLD JP1 Pin Assignments Pin Signal Direction Pin Signal out 6 ground 3_3V fused 5 CPLD_TMS no connect 7 no connect 8 no connect 9 CPLD_TDO out 10 ground The 232 debug serial port is accessible via the mini B USB connector Default port settings are 115200 baud optional 9600 8 data bits 1 stop bit no parity no flow control Table 7 53 IPMP EIA 232 P4 Pin Assignments Signal Pin Signal no connect 2 RS 232 Rx IPMP RS 232 Tx 4 no connect ground 6 ground ATCA 9305 User s Manual 10009109 07 211 System Management eee Table 7 53 IPMP 232 Assignments continued Pin Signal Pin Signal Hp mm 212 ATCA 9305 User s Manual 10009109 07 Chapter 8 Back Panel Connectors 8 1 8 2 Overview There are multiple connectors on the ATCA 9305 reference Figure 2 3 for their location The back panel connec
109. ation listed in Table A 2 for details about each command s request and response data The IPMC also implements ATCA commands see the ATCA Base Specification PICMG 3 0 ATCA 9305 User s Manual 10009109 07 149 System Management 7 8 Boot Options The Set System Boot Options and Get System Boot Options commands provide a means to set retrieve the boot options The IPMI specification defines a set of standard boot option parameters In addition the specification includes a range of numbers 96 127 for OEM extensions Artesyn utilizes this area for OEM function extensions such as boot bank selection POST configuration Graceful Shutdown Timeout and Boot Firmware Boot Options The following table describes these extensions Table 7 6 Artesyn Boot Option Parameters Parameter Boot Bank non volatile Parameter Data data 1 Set Selector This is the processor ID for which the boot option is to be set data 2 Boot Bank Selector This parameter is used to indicate the boot bank from which the payload will boot 00h Primary i e default Boot Bank is selected 01h Secondary Boot Bank is selected 02h PLCC32 Socket is selected 03h FFh unused POST Type non volatile data 1 Set Selector This is the processor ID for which the boot option is to be set data 2 POST Type Selector This parameteris used to specify the POST type that the payload boot firmware will execute 00h Sh
110. ation Time Out Enable Payload Control Disable Payload Control Reset IPMC Hang IPMC Bused Resource Control Bused Resource Status Graceful Reset ATCA 9305 User s Manual 10009109 07 167 System Management 7 11 1 168 Table 7 16 Vendor Command Summary continued Command netFn LUN Cmd Diagnostic Interrupt Results OEM 2E 2F Get Payload Shutdown Time Out 2E 2F Set Payload Shutdown Time Out 2E 2F Set Local FRU LED State Get Local FRU LED State Update Discrete Sensor Update Threshold Sensor Reserved for Message Listeners 2E 2F Add Message Listener 2E 2F Remove Message Listener 2E 2F Get Message Listener List OEM 2E 2F 1A Update Firmware Progress Sensor OEM 2E 2F FO Get Status The IPMC firmware notifies the payload about changes of all status bits except for bits 0 2 by sending an unprintable character ASCII 07 BELL over the Payload Interface The payload is expected to use the Get Status command to identify pending events and other SIPL commands to provide a response if necessary The event notification character is sent in a synchronous manner and does not appear in the contents of SIPL messages sent to the payload Table 7 17 Get Status Command Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems Response Data 1 Completion Code 2 4 PPS IANA Private Enterp
111. auf der Oberfl che des Boards k nnen zu Kurzschl ssen f hren Betreiben Sie das Board nur innerhalb der angegebenen Grenzwerte f r die relative Luftfeuchtigkeit und Temperatur Stellen Sie vor dem Einschalten des Stroms sicher dass sich auf dem Board kein Kondensat befindet ATCA 9305 User s Manual 10009109 07 27 Sicherheitshinweise Uberhitzung und Beschadigung des Boards Betreiben Sie das Board ohne Zwangsbel ftung kann das Board berhitzt und schlie lich besch digt werden Bevor Sie das Board betreiben m ssen Sie sicher stellen dass das Shelf ber eine Zwangsk hlung verf gt Verletzungen oder Kurzschl sse Board oder Stromversorgung Falls die ORing Dioden des Boards durchbrennen kann das Board einen Kurzschluss zwischen den Eingangsleitungen A und B verursachen In diesem Fall ist Leitung A immer noch unter Spannung auch wenn sie vom Versorgungskreislauf getrennt ist und umgekehrt Pr fen Sie deshalb immer ob die Leitung spannungsfrei ist bevor Sie Ihre Arbeit fortsetzen um 5 oder Verletzungen zu vermeiden Hot Swap Wenn Sie das Board im laufenden Betrieb in ein System das weder Hot Swap noch High Availability unterst tzt installieren bzw herausziehen wird das Board besch digt und es gehen Daten verloren Installieren entfernen Sie das Board nur im laufenden Betrieb wenn das System Hot Swap oder High Availability unterst tzt und wenn die Systembeschreibung dies ausdr cklich erlaubt
112. ayload communication time out may vary from 0 1 to 25 5 seconds Response Data Completion Code 2 4 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems 7 11 12 Enable Payload Control The Enable Payload Control command enables payload control from the Serial Debug interface Table 7 28 Enable Payload Control Command Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems Response Data Completion Code PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems ATCA 9305 User s Manual 10009109 07 179 System Management 7 11 13 Disable Payload Control The Disable Payload Control command disables payload control from the Serial Debug interface Table 7 29 Disable Payload Control Command Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems 7 11 14 Reset IPMC The Reset IPMC command allows the payload to reset the IPMC over the SIPL Table 7 30 Reset Command Data Field Request Data PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems 4 Reset Type Code 0x00 Cold IPMC reset to the current mode 0x01 Cold IPMC re
113. being used by System Management Software SMS During run time SMS starts the timer then periodically resets it to keep it from expiring This periodic action serves as a heartbeat that indicates that the OS or at least the SMS task is still functioning If SMS hangs the timer expires and the IPMC generates a system reset When SMS enables the timer it should make sure the SMS bit is set to indicate that the timer is being used in its OS Watchdog role OEM This indicates that the timer was being used for an OEM specific function 7 9 2 1 Using the Timer Use Field and Expiration Flags The software that sets the Timer Use field is responsible for managing the associated Timer Use Expiration flag For example if System Management Software SMS sets the timer use to SMS OS Watchdog then that same SMS is responsible for acting on and clearing the associated Timer Use Expiration flag In addition software should only interpret or manage the expiration flags for watchdog timer uses that it set For example the monitor should not report watchdog timer expirations or clear the expiration flags for non monitor uses of the timer This is to allow the software that did set the Timer Use to see that a matching expiration occurred 7 9 3 Watchdog Timer Event Logging By default the IPMC will automatically log the corresponding sensor specific watchdog sensor event when a timer expiration occurs A don t log bitis provid
114. ble If set to 1 the IPMC provides a trace of SIPL activity on the Payload interface onto the Serial Debug interface Bit 2 Alert Logging Enable If set to 1 the IPMC outputs important alert messages onto the Serial Debug interface Bit 1 Low level Error Logging Enable If set to 1 the IPMC outputs low level error diagnostic messages onto the Serial Debug interface Bit 0 Error Logging Enable If set to 1 the IPMC outputs error diagnostic messages onto the Serial Debug interface Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems ATCA 9305 User s Manual 10009109 07 175 System Management 7 11 6 Get Hardware Address The Get Hardware Address command reads the hardware address of the IPMC Table 7 22 Get Hardware Address Command Type Request Data Byte Data Field PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems Response Data Completion Code PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems Hardware Address 7 11 7 Set Hardware Address The Set Hardware Address command allows overriding of the hardware address read from hardware when the IPMC operates in Manual Standalone mode Table 7 23 Set Hardware Address Command Byte Data Field Type Request Data 1 3 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394
115. byte contains the Network Function Code netFn and the responder s Logical Unit Number rsLUN The third byte contains the two s complement checksum for the first two bytes The fourth byte contains the requester s Slave Address rqSA e The fifth byte contains the requester s Sequence Number rqSeq and requester s Logical Unit Number rqLUN The Sequence number be used to associate a specific response to a specific request The sixth byte contains the Command Number The seventh byte and beyond contain parameters for specific commands if required The final byte is the two s complement checksum of all of the message data after the first checksum 142 ATCA 9305 User s Manual 10009109 07 System Management An response message see Table 7 4 is similar to an request message The main difference is that the seventh byte contains the Completion Code and the eighth byte and beyond hold data received from the controller rather than data to send to the controller Also the Slave Address and Logical Unit Number for the requester and responder are swapped Table 7 4 Format for Response Message Byte Bits 7 6 5 4 3 2 1 0 Network Function netFn rqLUN Checksum 4 rsSA 5 rsSeq rsLUN 6 Command 7 Completion Code Data N 1 Checksum 7 5 SIPLProtocol The IPMC supports the Serial Interface Protocol Lite SIPL protocol It supports raw IPMI message
116. com Corporation Document 54615 0517 5 12 08 BCM5482 10 100 1000BASE T Gigabit Ethernet Transceiver Data Sheet Broadcom Corporation Document 5482 DS04 R 10 18 07 http www broadcom com Flash optional 32 Mbit x8 x16 Concurrent SuperFlash Data Sheet Silicon Storage Technology Inc 571270 01 000 9 05 http www sst com mDOC H3 Embedded Flash Drive EFD featuring Embedded TrueFFS Flash Management Software Preliminary Data Sheet msystems 92 DS 1205 10 Rev 0 2 June 2006 http www m systems com mobile StrataFlash Embedded Memory P33 Data Sheet Intel Order Number 314749 004 November 2007 http www intel com 4 Serial Configuration Devices EPCS1 EPCA4 EPCS16 amp EPCS64 Altera Corporation CS1014 2 0 April 2007 http www altera com 266 ATCA 9305 User s Manual 10009109 07 Related Documentation Table A 2 Technical References continued Device Interface Document IPMI Intelligent Platform Management Interface Specification v2 0 Intel Hewlett Packard NEC Dell Rev 1 0 Feb 12 2004 IPMI Intelligent Platform Management Bus Communications Protocol Specification v1 0 Intel Hewlett Packard NEC Dell Rev 1 0 November 15 1999 IPMI Platform Management FRU Storage Definition v1 0 Intel Hewlett Packard NEC Dell Rev 1 1 September 27 1999 http www intel com design servers ipmij Hardware Platform Management IPM Controller Firmware Upgrade
117. command scans the PCI bus and lists the base address of the devices Description showpci sleep The sleep command executes a delay of N seconds Definition Delay execution for N seconds N is a decimal value sleep N switch_reg The switch_reg command reads or writes to the Ethernet core switch registers The values changed via this command are not persistent and clear after hard or soft reset Option values are as follows switch core or fp port 0 25 block 1 7 and sub block 0 15 R reads the register contents at the address specified W writes the address value to the register address specified Definition switch_reg switch port op block sub block op R W address value Example ATCA 9305 User s Manual 10009109 07 257 Management Processor Monitor 9 14 26 9 14 27 258 The following is an example of a read of register address Ox1a switch_reg core 0 r Oxla The following is an example of a write to register address 0x1a where 0 is the data to write switch reg core 0 Oxla 0 version The version command displays the monitor s current version number Definition version vian The vlan command creates one or more new VLANs using vid as the VLAN identification VID value and deletes one or more existing VLANs whose VLAN ID matches the VLAN ID value vid These variables are set using a comma separated list of port names By specifying a port number in the list of port
118. continued Data Field Completion Code Response Data PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems 7 11 23 Get Local FRU LED State The Get Local FRU LED State command is used to read the local state of a FRU LED Table 7 39 Get Local FRU LED State Command Type Byte Data Field PPS IANA Private Enterprise ID MS Byte first Request Data 0x00400A 16394 Pigeon Point Systems 4 FRU Device ID 5 LED ID 00h Blue LED Hot Swap 01h LED 1 005 02h LED 2 03h LED 3 04h FEh OEM defined LEDs FFh reserved all LEDs under management control are addressed ATCA 9305 User s Manual 10009109 07 189 System Management Table 7 39 Get Local FRU LED State Command continued Type Response Data Byte Data Field Completion Code PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems Local Control LED Function 00h LED is off default if Local Control not supported 01h FAh LED is blinking Off duration specified by this byte on duration specified by byte 5 in tens of milliseconds FBh FEh reserved FFh LED is on Local Control On Duration LED on time is measured in tens of milliseconds Lamp Test time in hundreds of milliseconds if byte 4 FBh time value must be less than 128 Other values when Byte 4 FBh are reserved Otherwise this field is ignored and shall be set to Oh Color parame
119. ctionality includes 10 Gbps and 1 Gbps SGMII PHY interfaces One 10 100 1000BASE T Ethernet SGMII port is routed to a front panel RJ45 connector see Figure 6 1 one is routed to the MPC8548 management processor TSEC2 port and two are routed to the base channel backplane see Figure 8 2 Two 10 GbE XAUI ports connect to the back panel via the fabric channel see Figure 8 2 Two XAUI ports process packets to and from each CN5860 processor Six 10 GbE XAUI ports route to the optional rear transition module RTM See Table 8 3 and Table 8 4 for pin assignments Proprietary information on the Broadcom switch is not available in this user s manual Refer to their web site for available documentation Ethernet Switching The base interface Ethernet ports are provided by the Broadcom BCM56802 16 port 10 gigabit GbE switch The SerDes functionality includes 10 Gbps XAUI and 1 Gbps SGMII PHY interfaces The integrated SerDes complies with the CX 4 standard and PICMG 3 1 standard The Fabric interface is compliant with PICMG 3 1 Revision 1 0 specifically link option 9 one 10GBASE BX4 Switch connectivity consists of the following devices e Two 10GbE ports to CN5860 processor complex 1 e Two 10GbE ports to CN5860 processor complex 2 e One GbE port to the front panel R 45 connector e One GbE port to the MPC8548 management processor complex then out the front panel RJ45 connector ATCA 9305 User s Manual 10009109 07 129
120. ctions ATCA 9305 User s Manual 10009109 07 263 Management Processor Monitor 9 17 1 Binary The binary formats and associated commands include Executable binary files go e VxWorks and QNX ELF bootm bootvx or bootelf Compressed gzipped VxWorks and QNX ELF bootm Linux kernel images bootm e Compressed gzipped Linux kernel images bootm 9 17 2 Motorola S Record S Record download uses the standard Motorola S Record format This includes load address section size and checksum all embedded in an ASCII file 264 ATCA 9305 User s Manual 10009109 07 Related Documentation Appendix Artesyn Embedded Technologies Embedded Computing Documentation The publications listed below are referenced in this manual You can obtain electronic copies of Artesyn Embedded Technologies Embedded Computing publications by contacting your local Artesyn sales office For released products you can also visit our Web site for the latest copies of our product documentation 1 Goto www artesyn com computing 2 Under SUPPORT click TECHNICAL DOCUMENTATION 3 Under FILTER OPTIONS click the Document types drop down list box to select the type of document you are looking for 4 Inthe Search text box type the product name and click Table A 1 Artesyn Embedded Technologies Embedded Computing Publications Document Title and Source Publication Number Basic Blade Services Softw
121. d displays all of the environment variables and their current values to the display Definition Print the values of all environment variables printenv Print the values of all environment variable exact match name printenv name Saveenv The saveenv command writes the environment variables to non volatile memory Definition Saveenv setenv The setenv command adds new environment variables sets the values of existing environment variables and deletes unwanted environment variables ATCA 9305 User s Manual 10009109 07 Management Processor Monitor 9 13 9 13 1 9 13 2 9 13 3 Definition Set the environment variable name to value or adds the new variable name and value to the environment setenv name value Removes the environment variable name from the environment setenv name Test Commands The commands described in this section perform diagnostic and memory tests diags The diags command runs the Power on Self test POST Definition diags mtest The mtest command performs a simple SDRAM read write test Definition mtest start end pattern 11 um The command is a destructive memory test Press the q key to quit this test the monitor completes running the most recent iteration and exits to the default prompt after displaying cumulative results for the completed iterations Definition ATCA 9305 User s Manual 10009109 07 249 Management Processor Monitor
122. d of the Cavium CN5860 processor 2 core Do not over clock the Cavium frequency bits 6 7 hard strapped Table 5 24 2 Clock Divisor Control 0x74 Bits Function Description Cavium 1 Frequency resistor set bit read only see Table 5 23 6 0 Frequency resistor set bit read only 5 CMULOE C_MUL Output Enable ATCA 9305 User s Manual 10009109 07 121 Management Processor CPLD Table 5 24 Cavium 2 C_MULL Clock Divisor Control 0x74 continued Bits Function Description P1CMUL4 These bits drive directly to the Cavium 2 The core clock PICMUL3 speed is the number multiplied by 50 MHz For example the 800 MHz core is to 16 0x10 P1CMUL2 P1CMUL1 P1CMULO 5 1 24 This register allows for manual reprogramming of the PLDs on the board Changes to this register do not take effect until after a full board reset Table 5 25 0x78 reserved reserved Output Enable JTAGTCKSEL JTAG Test Clock Select changes from headerto PLD as the TCK source JTAGTCK JTAG Test Clock JTAGTMS JTAG Test Mode Select JTAGTDO JTAG Test Data Output JTAGTDI JTAG Test Data Input read only 122 ATCA 9305 User s Manual 10009109 07 Management Processor CPLD 5 1 25 GPIO Control Each Cavium processor has three GPIO control bits connected to the PLD This register d
123. ddress Registers Table 3 12 Address 9 8 0 4 Bits R W Function Reserved me w eem _ 7 Address 7 Address 6 Address 5 2 Address 2 m Address 1 ATCA 9305 User s Manual 10009109 07 85 Processor Complex 3 6 1 3 86 Table 3 13 Address 7 0 0x5 continued Bits R W Function DEN R W Address 0 Control Register The write only Control register performs two functions e Writing a value of 0x01 causes the contents of the Data registers to be written to the FPGA bridge at the location specified by the Address registers e Writing a value of 0x02 causes the contents of the Data registers to be overwritten the contents of the FPGA bridge at the location specified by the Address registers Writing any other value to the Control register will be ignored Table 3 14 Control 0x6 ATCA 9305 User s Manual 10009109 07 Processor Complex 3 6 1 4 Version Register This read only register tracks the PLD versions The version is hard coded in the PLD and changes with every released code change Version starts at 0146 Table 3 15 Version 0x7 m qe eem _ 3 6 1 5 Scratch Register All registers in this range act as the same register Table 3 16 Scratch 0x8 Ox3F R W R W R W ATCA 9305 User s Manual 10009109 07 87 Cavium Processor Complex Read Example To read the FPGA bri
124. ddress for the board configured by e g 192 168 1 1 DHCP serverip TFTP NFS server address value must be e g 192 168 1 2 configured after the DHCP IP address is acquired ATCA 9305 User s Manual 10009109 07 231 Management Processor Monitor MU 9 6 8 232 Table 9 5 DHCP Ethernet Configuration continued Environment Variable Description Value ethaddr MAC address 00 80 9 autoload Boot image from TFTP server after DHCP no acquisition e Values for ethaddr netdev and autoloadare set by the user e Thevalue obtained by the DHCP server may not be applicable to your development application e Ensure that each MAC address on the network is unique lfautoloadis not set or configured to yes ensure that the DHCP provides proper information for autoboot If proper autoboot information is not provided an error may occur rarpboot The rarpboot command boots an image via a network connection using the RARP TFTP protocol If loadaddress or bootfilename is not specified the environment variables loadaddr and bootfile are used as the default To use this command the environment variables listed in Table 9 4 must be configured Definition rarpboot loadaddress bootfilename ATCA 9305 User s Manual 10009109 07 Management Processor Monitor 9 6 9 9 7 9 7 1 tftpboot Thetftpboot command loads an image via a network connection using the TFTP protocol The
125. de The StrataFlash features high performance fast asynchronous access times low power and flexible security options Flash 4 MB x 16 The 4 MB soldered NOR flash starts at physical address 1005 0000 6 The 32 Mbit device provides CN5860 code storage and non volatile memory ATCA 9305 User s Manual 10009109 07 Cavium Processor Complex 3 66 StratixGX Interconnect The Altera StratixGX FPGA provides the high speed SPI 4 2 interconnect Each complex has dual SPI to XAUI bridges connected to the XAUI Ethernet switch ports 3 6 1 PLD Registers The FPGA bridge is located at address 0x1D030000 Use the following registers to access the XAUI to SPI bridge configuration registers N i PLD registers information can be requested via sales marketing office 3 611 Data Registers Table 3 8 Data 31 24 0 0 Function Data 31 R W R W R W Data 27 R W R W R W Bits Data 26 Data 25 Data 24 7 3 2 1 0 ATCA 9305 User s Manual 10009109 07 83 Processor Complex 84 Table 3 9 Data 23 16 0 1 Bits R W Function s fw E Data 20 Data 19 Data 18 Data 17 oss Table 3 10 Data 15 8 0x2 Data 15 Data 14 Data 13 Data 12 1 Data 9 0 s Data 8 ATCA 9305 User s Manual 10009109 07 Processor Complex Table 3 11 Data 7 0 0x3 continued Bits R W Function 3 6 1 2 A
126. ded GR 1089 CORE Standard on page i Updated Product Certification on page 1 4 Updated Declaration of Conformity Updated section Product Certification on page 1 4 Updated table Circuit Board Dimensions on page 2 1 Updated table Typical Power Requirements on page 2 14 Updated table Environmental Requirements on page 2 14 Added Critical Temperature Spots on page 2 17 Updated chapter System Management on page 7 1 Added IPMI commands bparams_get on page 9 17 and bparams_set on page 9 17 Updated vlan on page 9 26 Added inicmd to table Standard Environment Variables on page 9 27 Added chapters Safety Notes on page 11 1 and Sicherheitshinweise on page 12 1 10009109 03 February 2010 10009109 04 August 2010 Updated Boot Firmware Boot Options on page 7 42 Updated vlan on page 9 26 Added support for PCB Rev 2 x 10009109 05 September 2010 Updated Declaration of Conformity 10009109 06 January 2013 Updated RoHS Compliance on page 42 10009109 07 May 2014 36 Re branded to Artesyn template ATCA 9305 User s Manual 10009109 07 Chapter 1 Overview 1 1 The ATCA 9305 is an Advanced Telecom Computing Architecture AdvancedTCA blade based on dual Cavium CN5860 processors and the Freescale Semiconductor MPC8548 management processor This blade is targeted at security and
127. dered hazardous Make sure that the external power supply meets the relevant safety standards Make sure that TNV 2 is separated from dangerous voltages mains through double or reinforced insulation 66 Insert a board 1 Insert the ATCA 9305 into an available slot 2 Push in the front panel handle tab The blue Hot Swap LED on the front panel see Figure 2 1 flashes a long blink to indicate that board insertion is in progress and system management software is activating the slot Then the blue LED turns off indicating the insertion process is complete and payload power is present ATCA 9305 User s Manual 10009109 07 Setup Remove a board 1 Pull out the handle tab on the ATCA 9305 front panel one click A short blink indicates the board is requesting permission for extraction 2 Remove the board when the blue LED on the front panel is on no payload power Do not remove the ATCA 9305 while the blue LED is blinking 2 4 Troubleshooting In case of difficulty use the following checklist Be sure the ATCA 9305 circuit board is seated firmly in the carrier e Besurethe system is not overheating e Check the cables and connectors to be certain they are secure e Check that your terminal is connected to a console port 2 4 1 Technical Support If you need help resolving a problem with your ATCA 9305 visit www artesyn com Please have the following information handy ATCA 9305 serial n
128. dge SPI COMMAND register at 0x204 use the following commands Set address bits 9 8 gt write64b 1d030004 02 Set address bits 7 0 gt write64b 14030005 04 Perform read gt write64b 1d030006 02 Display the results gt read641 14030000 Write Example To write to the FPGA bridge MAC_CMD_CFG register at 0 00 use the following commands Set data bits 31 24 gt write64b 1d030000 a9 Set data bits 23 16 gt write64b 1d030001 b8 Set data bits 15 8 gt write64b 14030002 c7 Set databits 7 0 gt write64b 14030003 d Set address bits 9 8 gt write64b 14030004 00 Set address bits 7 0 88 ATCA 9305 User s Manual 10009109 07 Cavium Processor Complex gt write64b 1d030005 Oc Perform a write gt write64b 14030006 01 3 7 Headers and Connectors 3 7 1 COP JTAG Headers The CN5860 processor complex uses headers 1 and 15 for debug Table 3 17 CN5860 Processor Headers processor 2 115 processor 1 Pin 1 P2_ETRST P1 ETRST i eem em mm mm 4 2 P2_ETDO P1_ETDO wj ground ground P2_TMS P1_TMS ground P2 RST P1 RST key pin not installed key pin not installed P2 DINT P1 DINT P2 COP 3 3 P1 COP PWR 3 3V ATCA 9305 User s Manual 10009109 07 89 Cavium Processor Complex 3 7 2 Console Serial Ports Connectors P6 processor
129. e acceleration for certain security protocols RTM optional This blade supports custom Rear Transition Module RTM with the following 1 0 Upto six 10GbE connections One x4 PCI Express port from the MPC8548 38 ATCA 9305 User s Manual 10009109 07 Overview eee Connections for an MMC to control Hot Swap e MPC8548 console port For more detailed information see the ATCA 9305 Rear Transition Module User s Manual ATCA 9305 User s Manual 10009109 07 39 1 2 Functional Overview The following block diagram provides a functional overview for the ATCA 9305 Figure 1 1 General System Block Diagram Managementi punanata Processor PQ DDR2 SDRAM Jin 2 DDR2 SDRAM 2 Octeon Octeon CN5860 BCM56802 CN5860 Processor 1 XAUI 10 Gb Processor 2 Switch 10G 4 PORTS 1 106 2PORTS 40 ATCA 9305 User s Manual 10009109 07 Overview Eg R1 boards interface is available as PCB connector only 7 1 3 Additional Information This section lists the ATCA 9305 hardware s regulatory certifications and briefly discusses the terminology and notation conventions used in this manual It also lists general technical references Mean time between failures MTBF has been calculated at 439 924 hours using the Telcordia SR 332 Issue 1 Reliability Prediction fo
130. e bus is available Command Types for Board to Carrier Controller 0 Request to seize control of the bus 1 Relinquish control of the bus carrier controller can reassign control of bus 2 Notify carrier controller that control of the bused resource has been transferred to this board from another authorized board Bused Resource ID 0 Metallic Test Bus pair 1 1 Metallic Test Bus pair 2 2 Synch clock group 1 CLK1A and CLK1B pairs 3 Synch clock group 2 CLK2A and CLK2B pairs 3 Synch clock group 3 CLK3A and CLK3B pairs Response Data Completion Code PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems Status 0 Ack carrier controller acknowledges that board has control 1 Error same as Ack but carrier controller believes board should not have been given control of the resource optional 2 Deny carrier controller denies control of resource by the board 182 ATCA 9305 User s Manual 10009109 07 System Management 7 11 17 Bused Resource Status If the receives Bused Resource command from 0 it asserts an appropriate event and notifies the payload which uses the Bused Resource Status command over the SIPL When the IPMC receives a Bused Resource Status command the respective bit in the IPMC status is cleared The payload must issue a Bused Resource Status command before the payload communication time out time If the payload does not issue such a command before the
131. e forwards the command composed in the previous step to the shelf manager using the Send Message command The Send Get Message in SIPL format is 18 xx 34 40 20 BO 30 72 00 01 00 8D 5 The BMR H8S AMCc firmware sends the Get Address Info request to the shelf manager waits for a reply to this request and sends this reply to the payload software in the Send Get Message response 1 00 34 00 72 B4 20 00 01 00 00 41 82 FF 00 FF 00 1E 6 The payload software extracts the Get Address info reply from the Send Get Message response and retrieves the physical address of the board from it The second message bridging implementation bridging via LUN 10 allows the payload to receive responses to requests sent to IPMB 0 via the Send Message command with request tracking disabled as well as receive requests from 0 To provide this functionality the ATCA 9305 IPMC places all messages coming to LUN 10 from IPMB 0 in a dedicated Receive Message Queue and those messages are processed by the payload instead of the IPMC firmware To read messages from the Receive Message Queue the payload software uses the standard Get Message command The payload software is notified about messages coming to LUN 10 via the Get Status command of the SIPL protocol and the payload notification mechanism or if the LPC KCS based Payload Interface is used using the KCS interrupt The Receive Message Queue of the ATCA 9305 IPMC is limited to 128 bytes which is suff
132. e tested in a representative system to show compliance with the above mentioned requirements A proper installation in a compliant system will maintain the required performance Use only shielded cables when connecting peripherals to assure that appropriate radio frequency emissions compliance is maintained Installation 22 Before installing the board make sure the requirements listed in section Board Exchange are met Restricted access area This board is only to be installed in a restricted access area Data Loss Removing the board with the blue LED still blinking causes data loss Wait until the blue LED is permanently illuminated before removing the board Damage of Circuits Electrostatic discharge and incorrect board installation and removal can damage circuits or shorten their life Before touching the board or electronic components make sure that you are working in an ESD safe environment or wear ESD wrist straps Board Malfunctioning Incorrect board installation and removal can result in board malfunctioning Make sure that the board is connected to the system backplane via all assembled connectors and that power is available on all zone 1 power pins Damage of the Product Incorrect installation of the product can cause damage of the product Only use handles when installing removing the product to avoid damage deformation to the face plate and or PCB ATCA 9305 User s Manual 10009109 07 Safety Notes Dam
133. e value in memory and then the new value is displayed The command line then prompts for a new value to be written at the same address Pressing ENTER without entering a new value leaves the original value unchanged To exit the nm command enter a non valid hexadecimal value such as x followed by ENTER Definition nm b w 1 address 9 87 mw The command mw writes value to memory starting at address The number of objects modified can be defined by an optional fourth argument count Definition mw b 1 address value count Example In this example the mw command is used to write the value Oxabba three times starting at the physical address 0x80000 gt mw w 80000 abba 3 gt md 80000 00080000 abbaabba abbaffff ffffffff ffffffff 00080010 ffffffff ffffffff ffffffff ffffffff 00080020 ffffffff ne 00080030 o anew ae 20080040 00080050 e 3d e Rs 238 ATCA 9305 User s Manual 10009109 07 Management Processor Monitor 9 9 9 9 1 9 9 2 00080060 ffffffff ffffffff Fffffffff ffffffff 00080070
134. ector array supports four interfaces to the AdvancedTCA backplane e Base Node Interface J23 supports two Base channels 10 100 1000 BASE T Fabric Interface 23 supports two Fabric channels 10GbE Figure 8 2 Zone 2and 3 Connectors 23 30 31 ete NE 10 6 pg Row Row G Row F Row E Row D Row C Row Row A mail Table 8 2 Zone 2 Connector 23 Assignments Row Interface Fabric Channel 2 Fabric Channel 1 ATCA 9305 User s Manual 10009109 07 215 Back Panel Connectors Table 8 2 Zone 2 Connector 23 Pin Assignments continued Row Interface AB CD EF GH 5 Base TRDO TRDO TRD1 TRD1 TRD2 TRD2 TRD3 TRD3 Channel 1 6 Base TRDO TRDO TRD1 TRD1 TRD2 TRD2 TRD3 TRD3 Channel 2 7 10 na no connect 84 Zone3 These optional Zone 3 type A connectors 30 J31 and 33 support a Rear Transition Module RTM I O signals are routed through Zone 3 connectors to the RTM to allow servicing the ATCA 9305 without using cable assemblies Connectors 30 and J31 use the same 20 connector as Zone 2 See Figure 8 3 for the J33 connector Table 8 3 Zone 3 Connector 30 Pin Assignments H RTM_10G RTM_10G RTM_10G RTM_10G
135. ed after moninit However it can clear all optional variables Table 9 7 Optional Environment Variables app_lock_base Assigns where to start block lock protection at the base of NOR soldered flash If assigned region does not fall within the NOR flash area no user application locking will occur except for the monitor block locking protection Size of user NOR soldered flash protection area bootverifycmd Sets the U Boot boot command that is used to execute the primary and secondary application images when using the bootv command If not defined bootv uses the U Boot go command as the default carrier_num This is a slot within a shelf defined by the zone 1 hardware address corresponding to the logical slot address Determines whether switch ports should be configured The moninit command does not initialize these variables Each parameter is only defined if a change from the default setting is desired and is not defined after initialization of the environment variables ATCA 9305 User s Manual 10009109 07 Management Processor Monitor Table 9 7 Optional Environment Variables continued Variable Description pci_memsize Sets the amount of SDRAM memory made available on the PCI bus The minimum setting is 16 megabytes If not set 128 MB of SDRAM are available over PCI This parameter takes a hex value Valid options all size in hex 0 8000000 128 MB This memory region is at the very top
136. ed as replacement for qualified personnel Keep away from live circuits inside the equipment Operating personnel must not remove equipment covers Only factory authorized service personnel or other qualified service personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment Do not install substitute parts or perform any unauthorized modification of the equipment or the warranty may be voided Contact your local Artesyn Embedded Technologies representative for service and repair to make sure that all safety features are maintained This equipment has been tested and found to comply with the limits for a Class A digital device pursuant to Part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instruction manual may cause harmful interference to radio communications ATCA 9305 User s Manual 10009109 07 21 Safety Notes Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense Changes or modifications not expressly approved by Artesyn Embedded Technologies could void the user s authority to operate the equipment Board products ar
137. ed to temporarily disable the automatic logging The don t log bitis automatically cleared logging re enabled whenever a timer expiration occurs 7 9 3 4 Monitor Support for Watchdog Timer If a system Warm Reset occurs the watchdog timer may still be running while the monitor executes POST Therefore the monitor should take steps to stop or restart the watchdog timer early in POST Otherwise the timer may expire later during POST or after the OS has booted ATCA 9305 User s Manual 10009109 07 153 System Management 7 9 4 7 9 5 154 Reset Watchdog Timer Command The Reset Watchdog Timer command is used for starting and restarting the Watchdog Timer from the initial countdown value that was specified in the Set Watchdog Timer command pretime out interrupt has been configured the Reset Watchdog Timer command will not restart the timer once the pretime out interval has been reached The only way to stop the timer once it has reached this point is via the Set Watchdog Timer command Table 7 8 Reset Watchdog Timer Command Type Byte Data Field Request Data Set Watchdog Timer Command The Set Watchdog Timer command is used for initializing and configuring the watchdog timer The command is also used for stopping the timer If the timer is already running the Set Watchdog Timer command stops the timer unless the don t stop bit is set and clears the Watchdog pretime out interrupt flag see G
138. elease 2 Metallic Bus 1 Force 3 Metallic Bus 1 Free 170 ATCA 9305 User s Manual 10009109 07 System Management Table 7 17 Get Status Command continued Type Byte Data Field 7 Bits 4 7 Clock Bus 2 Events These bits indicate pending Clock Bus 2 requests arrived from the carrier controller Response Data 0 Clock Bus 2 Query 1 Clock Bus 2 Release 2 Clock Bus 2 Force 3 Clock Bus 2 Free Bits 0 3 Clock Bus 1 Events These bits indicate pending Clock Bus 1 requests arrived from the carrier controller 0 Clock Bus 1 Query 1 Clock Bus 1 Release 2 Clock Bus 1 Force 3 Clock Bus 1 Free 8 Bits 4 7 reserved Bits 0 3 Clock Bus 3 Events These bits indicate pending Clock Bus 3 requests arrived from the carrier controller 0 Clock Bus 3 Query 1 Clock Bus 3 Release 2 Clock Bus 3 Force 3 Clock Bus 3 Free ATCA 9305 User s Manual 10009109 07 171 System Management 7 11 2 Get Serial Interface Properties The Get Serial Interface Properties command is used to get the properties of a particular serial interface Table 7 18 Get Serial Interface Properties Command Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems Interface ID 0 Serial Debug Interface 1 Payload Interface Response Data Completion Code Repone e 2 4 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems Res
139. environment variable s ipaddr and serverip are used as additional parameters to this command If loadaddress or boot filename is not specified the environment variables loadaddr and boot file are used as the default To use this command the environment variables listed in Table 9 4 must be configured The port used is defined by the ethport environment variable If a11 is selected for ethport the TFTP process will cycle through each port until a connection is found or all ports have failed Definition tftpboot loadaddress bootfilename File Load Commands The file load commands load files over the serial port loadb The loadb command loads a binary file over the serial port The command takes two optional parameters offset The address offset parameter allows the file to be stored in a location different than what is indicated within the binary file by adding the value off to the file s absolute address baudrate The baudrate parameter allows the file to be loaded at baud instead of the monitor s console baudrate The file is not automatically executed the loadb command only loads the file into memory Definition loadb off baud ATCA 9305 User s Manual 10009109 07 233 Management Processor Monitor 9 7 2 9 8 234 loads Theloads command loads an S Record file over the serial port The command takes two optional parameters offset The address offset parameter allows the file to be stored i
140. erated the message Sensor Number A unique number indicating the sensor that generated the message Event Dir Event Upper bit indicates direction 0 Assert 1 Deassert Lower 7 bits Type indicate type of threshold crossing or state transition Event Data 0 Data for sensor and event type Event Data 1 Optional Data for sensor and event type 12 Event Data 2 Optional Data for sensor and event type 13 Chk2 Checksum 2 Each byte has eight bits Event generating sensors with a Threshold Event Reading 0x01 initiate an event message when a sensor reading crosses the defined threshold The default thresholds for a particular sensor are retrieved by sending the IPMC a Get Sensor Thresholds command The system management controller must send the IPMC a Get Sensor Reading command to retrieve the current sensor reading Refer to the IPMI specification listed in Table A 2 for complete details on using these commands ATCA 9305 User s Manual 10009109 07 System Management 7 20 FRU Inventory The stores Field Replaceable Unit FRU information in its boot memory SROM The data structure contains information such as the product name part number serial number manufacturing date and E keying information Refer to the IPMI specification for complete details on the FRU data structure Table 7 50 lists the general contents of the ATCA 9305 s FRU information Table 7 50 FRU Definition Item De
141. erride O1h FAh LED blinking override FBh Lamp Test state Turn on LED specified in byte 3 for the duration specified in byte 5 then return to the highest priority state FCh LED state restored to Local Control state FDh FEh reserved FFh LED on override On Duration LED on time is measured in tens of milliseconds Lamp Test time in hundreds of milliseconds if byte 4 FBh time value must be less than 128 Other values when Byte 4 FBh are reserved Otherwise this field is ignored and shall be set to Oh ATCA 9305 User s Manual 10009109 07 163 System Management Table 7 14 Set FRU LED State Command continued Type Byte Data Field Request Data Color When Illuminated sets the override color when LED Function is 01h FAh and FFh This byte sets the Local Control color when LED Function is FCh This byte may be ignored during Lamp Test or may be used to control the color during the lamp test when LED Function is FBh Bits 7 4 reserved set to 0 Bits 3 0 Oh reserved 1h Use Blue 2h Use Red 3h Use Green 4h Use Amber 5h Use Orange 6h Use White 7h Dh reserved Eh Do not change Fh Use default color Response Data Completion Code PICMG Identifier indicates that this is a PICMG defined group extension command Use value 00h 7 10 4 Get FRU LED State Command The Get FRU LED State command allows the state of the FRU LEDs to be controlled by the management system Table 7 15 Get FRU LED State Command
142. es Command Type Byte Data Field Request 1 PICMG Identifier indicates that this is a PICMG defined group extension command Use value 00h FRU Device ID Completion Code PICMG Identifier indicates that this is a PICMG defined group extension command Use value 00h General Status LED Properties indicates the FRU s ability to control the four general status LEDs When a bit is set the FRU can control the associated LED Bits 7 4 reserved set to 0 Bit 3 LED3 Bit 2 LED2 Bit 1 LED1 Bit 0 Blue LED Application Specific LED Count is the number of application specific LEDs under IPMC control 00h FBh Number of application specific LEDs under IPMC control If none are present this field is 00h FCh FFh reserved Response Data 2 3 4 ATCA 9305 User s Manual 10009109 07 System Management 7 10 2 Get LED Color Capabilities Command LED 1 can be either red or amber this command is used to determine the valid color prior to issuing a Set FRU LED State command Table 7 13 Get LED Color Capabilities Command Type Request Data Response Data Byte Data Field PICMG Identifier indicates that this is a PICMG defined group extension command Use value 00h FRU Device ID LED ID FFh reserved Completion Code CCh If the LED ID contained in the Request data is not present on the FRU PICMG Identifier indicates that this is a PICMG defined group extensi
143. es the front panel LEDs controlled by the IPMC and documents how to control each LED with the standard FRU LED commands Reference the PICMG 3 0 Revision 2 0 AdvancedTCA Base Specification for more detailed information The ATCA 9305 has four L their location Table 7 11 FRU LEDs 2 02 55 ight Emitting Diodes LEDs on the front panel See Figure 2 1 for ID hex Reference Designator Description The blue Hot Swap LED displays four states On the board can be safely extracted Off the board is operating and not safe for extraction Long blink insertion is in progress Short blink requesting permission for extraction The Out Of Service programmable LED controlled by the IPMI controller is either red North America or amber Europe When lit this LED indicates out of service By default this LED is on during power up until the system management software switches it off The green LED is user defined but frequently is used as an In Service indicator When used as an In Service indicator a lit LED indicates that the ATCA 9305 is functioning properly ATCA 9305 User s Manual 10009109 07 159 System Management 7 10 1 160 Table 7 11 FRU LEDs LEDs ID hex Reference Designator Description CR56 The amber LED is user defined Get FRU LED Properties Command This command allows software to determine which LEDs are under IPMC control Table 7 12 Get FRU LED Properti
144. essage Bridging facility is responsible for bridging messages between various interfaces ofthe ATCA 9305 IPMI The message bridging is implemented via the standard Send Message command The ATCA 9305 IPMC also supports message bridging between the Payload Interface and 0 which allows the payload to send custom messages to and receive them from other shelf entities such as the shelf manager Message bridging is implemented using the Send Get Message commands and also via LUN 10 of the ATCA 9305 IPMC Thefollowing example illustrates how the Send Get Message and Get Address Info commands can be used by the payload software to get the physical location of the board in the shelf 1 The payload software sends the Get Address Info command to the BMR H8S AMCc requesting address information for FRU device 0 Using the SIPL protocol BO xx 01 00 ATCA 9305 User s Manual 10009109 07 145 System Management 2 TheBMR H8S AMCc returns its IPMB address in the Get Address Info reply In this example 7216 is the 0 address of the IPMC B4 00 01 00 00 FF 72 FF 00 01 07 3 Thepayload software composes a Get Address Info command requesting the responder to provide its addressing information for FRU device 0 The request is composed in the IPMB format The responder address is set to 2019 for the shelf manager The requester address is set to the value obtained in the previous step 20 BO 30 72 00 01 00 8D 4 The payload softwar
145. essor complexes The major devices on each complex consist of the CN5860 processor two StratixGX bridges SDRAM RLDRAM an I C EEPROM socketed ROM Flash and the PCI bus interface Figure 3 1 Processor Complex Block Diagram P1 DDR SDRAM JTAG PCI Bus Vi ci ACUI wu 00 C Processor 2 Processor 1 ATCA 9305 User s Manual 10009109 07 69 Cavium Processor Complex 3 1 1 70 The main features of the CN5860 include Table 3 1 CN5860 Features Core Speed up to 800 MHz processing up to 30 million packets per second Network Services Processor NSP System Packet Interface Two SPI 4 2 ports L2 Cache 2 MB eight way set associative DRAM 144 bit DDR2 DRAM interface RLDRAM 18 bit RLDRAM low latency memory direct access PCI 64 bit PCI 2 3 compatible The CN5860 and switch route packets using SPI 4 2 and control information flow using PCI The CN5860 has two SPI 4 2 interfaces with each one supporting up to 16 ports Two high speed SPI 4 2 Altera Stratix GX FPGAs function as the SPI to XAUI bridge for each processor to switch complex The PCI interface supports up to four ports consequently a total of 36 ports can be supported internally by each CN5860 Cavium Memory Map Although the Cavium processors are 64 bit the ATCA 9305 uses a 49 bit implementation Refer to the Cavium Networks OCTEON Plus CN58xx H
146. et Message Flags command in the IPMI specification v1 5 IPMC hard resets system hard resets and the Cold Reset command also stop the timer and clear the flag Byte 1 This selects the timer use and configures whether an event will be logged on expiration Byte 2 This selects the time out action and pretime out interrupt type Byte 3 This sets the pretime out interval If the interval is set to zero the pretime out action occurs concurrently with the time out action Byte 4 ATCA 9305 User s Manual 10009109 07 System Management This clears the Timer Use Expiration flags A bit set in byte 4 of this command clears the corresponding bit in byte 5 of the Get Watchdog Timer command Bytes 5 and6 These hold the least significant and most significant bytes respectfully of the countdown value The Watchdog Timer decrement is one count 100 ms The counter expires when the count reaches zero If the counter is loaded with zero and the Reset Watchdog command is issued to start the timer the associated timer events occur immediately Table 7 9 Set Watchdog Timer Command Request Data ATCA 9305 User s Manual 10009109 07 Byte Data Timer Use 7 1b don t log 6 1b the don t stop timer on Set Watchdog Timer command new for IPMI v1 5 new parameters take effect immediately If timer is already running countdown value will get set to given value and countdown will continue from that point Iftimer
147. eten Wird das Produkt in einem Wohngebiet betrieben so kann dies mit gro er Wahrscheinlichkeit zu starken St rungen f hren welche dann auf Kosten des Produktanwenders beseitigt werden m ssen nderungen oder Modifikationen am Produkt welche ohne ausdr ckliche Genehmigung von Artesyn Embedded Technologies durchgef hrt werden k nnen dazu f hren dass der Anwender die Genehmigung zum Betrieb des Produktes verliert Boardprodukte werden in einem repr sentativen System getestet um zu zeigen dass das Board den oben aufgef hrten EMV Richtlinien entspricht Eine ordnungsgem e Installation in einem System welches die EMV Richtlinien erf llt stellt sicher dass das Produkt gem den EMV Richtlinien betrieben wird Verwenden Sie nur abgeschirmte Kabel zum Anschluss von Zusatzmodulen So ist sichergestellt dass sich die Aussendung von Hochfrequenzstrahlung im Rahmen der erlaubten Grenzwerte bewegt Warnung Dies ist eine Einrichtung der Klasse A Diese Einrichtung kann im Wohnbereich Funkst rungen verursachen In diesem Fall kann vom Betreiber verlangt werden angemessene Ma nahmen durchzuf hren Board Installation 26 Bevor Sie das Board in einem System installieren berpr fen Sie ob die im Kapitel Board Exchange aufgef hrten Anforderungen erf llt werden Bereich mit eingeschranktem Zugang Installieren Sie das Board ein System nur in Bereichen mit eingeschr nktem Zugang ATCA 9305 User s Manual 10009109 0
148. etermines whether the PLD is driving or receiving on these lines Setting a bit to 1 causes the PLD to drive the corresponding line Table 5 26 Cavium GPIO Control 0x80 P2GPIO5OE Processor 2 GPIO5 Output Enable enabled is the default Output enable is set for the TIC timer output to the Cavium 2 Processor 2 GPIO4 Output Enable This is an input from the Cavium to reset the MIP4 2 Processor 2 GPIO3 Output Enable This is an input from the Cavium to reset the MIP3 PTGPIO5OE Processor 1 GPIO5 Output Enable enabled is the default Output enable is set for the TIC timer output to the Cavium 1 P1GPIO40E Processor 1 GPIO4 Output Enable This is an input from the Cavium to reset the MIP2 P1GPIO3OE Processor 1 GPIO3 Output Enable This is an input from the to reset the MIP1 5 1 26 Cavium GPIO Data Out This register is the data that will be driven on the GPIO line when the Output enable is set Table 5 27 Cavium GPIO Data Out 0x84 Bits Function Description reserved reserved 5 reserved ATCA 9305 User s Manual 10009109 07 123 Management Processor CPLD Table 5 27 Cavium GPIO Data Out 0x84 continued Bits Function Description Ro eme 1 P1GPIO4 Set the value of the Cavium 1 GPIO bit 4 0 P1GPIO3 Set the value of the Cavium 1 GPIO bit 3 5 1 27 GPIO Data In This register reads the value on the GPIO lines connected to each Ca
149. function in the default state The proper region of flash memory will be unlocked and erased prior to copying the monitor software into it command flags 1 or 2 force the monitor to be programmed to a single 1 bank of flash or dual 2 banks of flash If the command flags are not used then moninit checks for the number of banks of flash If there are two banks of flash then moninit automatically programs both banks for redundancy Also the serial number can be obtained from the fru data if fru is used as a parameter Definition ATCA 9305 User s Manual 10009109 07 253 Management Processor Monitor 9 14 16 254 Initialize environment variables and serial number in NVRAM and copy the monitor from the socket to NOR soldered flash moninit 1 2 lt serial or fru Initialize environment variables and serial number in NVRAM but do not update the monitor in NOR flash moninit 1 2 lt serial or fru gt noburn Initialize environment variables and serial number in NVRAM and copy the monitor from lt src_address gt into NOR flash moninit 1 2 lt serial or fru gt lt src_address gt pci The pci command enumerates the PCI bus It displays enumeration information about each detected device The pci command allows you to display values for and access the PCI Configuration Space Definition Display a short or long list of PCI devices on the bus specified by bus pei bus l
150. g F W Progress SDRAM POST Bus POST Flash POST EthSwitch POST Version change Async Pld Rst Payload Power r 82 0 03 0 Cavium 1 Cavium 1 Temp 1 SDRAM POST 1 POST 1 Boot 82 0 03 1 2 2 Cav2 SDRAM POST Cav2 POST Cav2 Boot r 82 0 14 0 Power Module 48V 48V Curr 48V Src A 48V Src 3 3V Mgmt 12V Payload 12V Curr FRU 1 r 82 0 CO 1 RTM RTM Hot Swap ATCA 9305 User s Manual 10009109 07 203 System Management 7 19 Sensors and Sensor Data Records The ATCA 9305 implements a number of sensors as described in the following tables All values are hexadecimal Table 7 47 IPMI Threshold Sensors Entity Name Sensor Type Event Reading Type EntityID Instance Event Gen Inflow Temp Temperature 01 Threshold 01 0x60 Yes Outflow Temp Temperature 01 Threshold 01 0x60 Yes Cavium 1 Temp Temperature 01 Threshold 01 0x60 Yes Cavium2Temp Temperature 01 Threshold 01 0x03 Yes 48V Voltage 02 Threshold 01 0x14 Yes 48V Curr Current 03 Threshold 01 Yes 48V Src Voltage 02 Threshold 01 Yes 48V Src Voltage 02 Threshold 01 Yes 3 3V Mgmt Voltage 02 Threshold 01 Yes 12V Payload Voltage 02 Threshold 01 0x14 Yes 12V Curr Current 03 Threshold 01 0x14 Yes Table 7 48 Discrete Sensors Entity Entity Event Name Sensor Type Event Reading Type ID Instance Gen Hot
151. g word refers to 32 bits double long word refers to 64 bits PLD This manual uses the acronym PLD as a generic term for programmable logic device also known as FPGA CPLD EPLD etc 44 ATCA 9305 User s Manual 10009109 07 Overview EN Radix 2 and 16 Hexadecimal numbers end with a subscript 16 Binary numbers are shown with a subscript 2 ATCA 9305 User s Manual 10009109 07 45 46 ATCA 9305 User s Manual 10009109 07 Setup This chapter describes the physical layout of the boards the setup process and how to check for proper operation once the boards have been installed This chapter also includes troubleshooting service and warranty information 2 1 Electrostatic Discharge Before you begin the setup process please remember that electrostatic discharge ESD can easily damage the components on the ATCA 9305 hardware Electronic devices especially those with programmable parts are susceptible to ESD which can result in operational failure Unless you ground yourself properly static charges can accumulate in your body and cause ESD damage when you touch the board Use proper static protection and handle ATCA 9305 boards only when absolutely necessary Always wear a wriststrap to ground your body before touching a board Keep your body grounded while handling the board Hold the board by its edges do not touch any components or circuits When the board is
152. ge 11 Write FRU Data Storage 1 2 Get PICMG Properties PICMG 2C 2D 00 Get Address Info PICMG 2C 2D 01 148 ATCA 9305 User s Manual 10009109 07 System Management Table 7 5 IPMC IPMI Commands continued Command netFn LUN FRU Control PICMG 2C 2D Get LED Color Capabilities PICMG 2C 2D Set FRU LED State Cmd 04 06 07 Get FRU LED State Set IPMB State Set FRU Activation Policy 0 Get FRU Activation Policy PICMG 2C 2D 0 0 Set FRU Activation Get Device Locator Record ID PICMG 2C 2D 00 Set Port State Get Port State Compute Power Properties Set Power Level Get Power Level PICMG Bused Resource Release Query Force Bus Free 10 PICMG 2C 2D 11 2C 2D 12 PICMG 2C 2D 17 The IPMC implements many standard IPMI commands For example software can use the watchdog timer commands to monitor the system s health Normally the software resets the watchdog timer periodically to prevent it from expiring The IPMI specification allows for different actions such as reset power off and power cycle to occur if the timer expires The watchdog s timer use fields can keep track of which software Operating System System Management etc started the timer Also thetime out action and timer use information can be logged automatically to the System Event Log SEL when the time out occurs Refer to the IPMI specific
153. ging All IPMI messages contain a Network Function Code field which defines the category for a particular command Each category has two codes assigned to it one for requests and one for responses The code for a request has the least significant bit of the field set to zero while the code for aresponse has the least significant bit of the field set to one Table 7 1 lists the network function codes as defined in the IPMI specification used by the IPMC Table 7 1 Network Function Codes Hex Code Value s Name 00 01 Chassis Type chassis device requests responses bridge requests responses Name 00 command request 01 response common chassis control and status functions 02 request 03 response message contains data for bridging to the next bus Typically the data is another message which also may be a bridging message This function is only present on bridge nodes Sensor Event sensor and event requests responses 04 command request 05 response for configuration and transmission of Event Messages and system Sensors This function may be present on any node Firmware 08 09 OB Storage 2 reserved ATCA 9305 User s Manual 10009109 07 application requests responses firmware transfer requests responses non volatile storage requests responses 06 command request 07 response message is implementation specific for a particular device as
154. handle switch is open 0x01 The handle switch is closed 0x02 The handle switch state is read from hardware 177 System Management Table 7 25 Set Handle Switch Command continued Type Byte Data Field Response Data Completion Code 2 4 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems 7 11 10 Get Payload Communication Time Out The Get Payload Communication Time Out command reads the payload communication time out value Table 7 26 Get Payload Communication Time Out Command Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems 5 Payload Time out Payload communication time out measured in hundreds of milliseconds Thus the payload communication time out may vary from 0 1 to 25 5 seconds 178 ATCA 9305 User s Manual 10009109 07 System Management 7 11 11 Set Payload Communication Time Out The Set Payload Communication Time Out command sets the payload communication time out value Table 7 27 Set Payload Communication Time Out Command Type Byte Data Field Request Data PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems Payload Time out Payload communication time out measured in hundreds of milliseconds Thus the p
155. he list it returns OxCD and IANA Table 7 44 Remove Message Listener Command Type Byte Data Field Request Data 1 3 Artesyn Embedded Technologies Embedded Computing Inc IANA Private Enterprise ID 0x0065CD 26061 Artesyn Embedded Technologies Embedded Computing Inc LSB Byte first byte 1 CD byte 2 65 byte 3 00 Network function to add Command to remove Response Response Data Completion Code 2 4 Artesyn Embedded Technologies Embedded Computing Inc IANA Private Enterprise ID 0x0065CD 26061 Artesyn Embedded Technologies Embedded Computing Inc LSB Byte first byte 2 CD byte 3 65 byte 4 00 ATCA 9305 User s Manual 10009109 07 199 System Management 7 16 3 Get Message Listener List The Get Message Listener List command returns the entire list of subscribed Message Listeners The command returns completion code 0x00 and IANA Table 7 45 Get Message Listener List Command Type Byte DataField Request Data 1 3 Artesyn Embedded Technologies Embedded Computing Inc IANA Private Enterprise ID 0x0065CD 26061 Artesyn Embedded Technologies Embedded Computing Inc LSB Byte first byte 1 CD byte 2 65 byte 3 00 Response Data 1 Completion Code 2 4 Artesyn Embedded Technologies Embedded Computing Inc IANA Private Enterprise ID 0x0065CD 26061 Artesyn Embedded Technologies Embedded Computing Inc LSB Byte first byte 2 CD byte 3
156. hernet access to the backplane See Table 8 2 30 31 The 80 pin Zone 3 connectors route PCle and XAUI 100 to the optional RTM See Table 8 3 and Table 8 4 for pin assignments 133 The 24 pin Zone 3 connector routes the reset Hot Swap MPC8548 console power and IPMC I2C to the optional RTM see Table 8 5 JP1 This is the 10 pin programming header for the IPMP CPLD and SPI 10G 1 4 devices See Table 7 52 P1 This 14 pin RJ45 connector with LEDs routes the Three speed Ethernet Controller TSECT between the MPC8548 and the front panel See Table 6 4 for pin assignments P2 This 16 pin TAG debug header accesses the MPC8548 processor see Table 4 7 P3 This 14 pin RJ45 connector with LEDs routes Ethernet FP1 between the switch and the front panel See Table 6 4 for pin assignments P4 The 5 pin vertical mini B USB provides the IPMP EIA 232 console debug see Table 7 53 P7 This 5 pin mini B USB is the console serial port for the MPC8548 management processor see Table 4 8 P10 The 30 pin Zone 1 connector routes IPMB to the backplane see Table 8 1 60 ATCA 9305 User s Manual 10009109 07 Setup P0800 P0801 These 5 pin horizontal mini B USBs are the CN5860 consoles which are valid for PCB Rev 2 x boards 2 2 2 Configuration Header There are total of seven jumper pairs 9 pins 11 14 are spare posts See Figure 2 3 forthe jumper location on the ATCA 9305 Also reference the Jumper Settings
157. hrlichen Prozeduren innerhalb dieses Handbuchs vorangestellt sind Beachten Sie unbedingt in allen Phasen des Betriebs der Wartung und der Reparatur des Systems die Anweisungen die diesen Hinweisen enthalten sind Sie sollten au erdem alle anderen Vorsichtsma nahmen treffen die f r den Betrieb des Produktes innerhalb Ihrer Betriebsumgebung notwendig sind Wenn Sie diese Vorsichtsma nahmen oder Sicherheitshinweise die an anderer Stelle dieses Handbuchs enthalten sind nicht beachten kann das Verletzungen oder Sch den am Produkt zur Folge haben Artesyn Embedded Technologies ist darauf bedacht alle notwendigen Informationen zum Einbau und zum Umgang mit dem Produkt in diesem Handbuch bereit zu stellen Da es sich jedoch um ein komplexes Produkt mit vielfaltigen Einsatzm glichkeiten handelt k nnen wir die Vollst ndigkeit der im Handbuch enthaltenen Informationen nicht garantieren Falls Sie weitere Informationen ben tigen sollten wenden Sie sich bitte an die f r Sie zustandige Gesch ftsstelle von Artesyn Embedded Technologies Das System erf llt die f r die Industrie geforderten Sicherheitsvorschriften und darf ausschlie lich f r Anwendungen in der Telekommunikationsindustrie und im Zusammenhang mit Industriesteuerungen verwendet werden Einbau Wartung und Betrieb d rfen nur von durch Artesyn Embedded Technologies ausgebildetem oder im Bereich Elektronik oder Elektrotechnik qualifiziertem Personal durchgef hrt werden Die in die
158. ibility EMC tests used an ATCA 9305 model that includes a front panel assembly from Artesyn Embedded Technologies ATCA 9305 User s Manual 10009109 07 3 Regulatory Agency Warnings amp Notices GR 1089 CORE STANDARD The intra building port s of the equipment or subassembly is suitable for connection to intrabuilding or unexposed wiring or cabling only The intra building port s of the equipment or subassembly MUST NOT be metallically connected to interfaces that connect to the OSP or its wiring These interfaces are designed for use as intra building interfaces only Type 2 or Type 4 ports as described in GR 1089 CORE Issue 4 and require isolation from the exposed OSP cabling The addition of Primary Protectors is not sufficient protection in order to connect these interfaces metallically to OSP wiring 4 ATCA 9305 User s Manual 10009109 07 Contents Regulatory Agency Warnings amp Notices 3 Safety aaa INDICE PNEU Pp hee 21 Sicherheits himel e 25 About this Manual rrr hh nenne 31 7 QUVORMVIOW pochi OPI ur 37 1 1 Components Features 4 4 37 1 2 Overview eee ee OP CREE EE E RR 40 1 3 Additional Information
159. ical with regards to the maximum temperature during blade operation To guarantee proper blade operation and to ensure safety you have to make sure that the temperatures at the locations specified in the following are not exceeded If not stated otherwise the temperatures should be measured by placing a sensor exactly at the given locations For your convenience all temperature spots are shown in the figure below that provides a detailed view of the blade 64 ATCA 9305 User s Manual 10009109 07 Setup Figure 2 13 Critical Temperature Spots 15216 ANT TLA 7001108 2026 Ww 9305 User s Manual 10009109 07 65 Setup 2 3 3 Hot Swap The ATCA 9305 can be Hot Swapped as defined in the AdvancedTCA specification see reference Table A 2 This section describes how to insert and extract ATCA 9305 module a typical AdvancedTCA system These procedures assume the system is using a shelf manager The ATCA 9305 Rear Transition Module RTM has its own Hot Swap LED and switch and it can be Hot Swapped in out independently of the front board Ifthe front board is not present then the RTM will not be powered If the front board is Hot Swapped out the RTM s blue LED will illuminate In either case the RTM can be safely removed Personal Injury or Product Damage The product is supplied by a TNV 2 voltage This voltage is consi
160. icient for storing at least three IPMB messages but may be not enough for a larger number of messages Taking this into account the payload software must read messages from the queue as fast as possible caching them on the on carrier payload side for further handling if it is necessary If the Receive Message Queue is full the ATCA 9305 IPMC rejects all requests coming to LUN 10 with the COh Node Busy completion code and discards all responses coming to this LUN 146 ATCA 9305 User s Manual 10009109 07 System Management 7 7 Standard Commands The Intelligent Peripheral Management Controller IPMC supports standard IPMI commands to query board information and to control the behavior of the board These commands provide means to identify the controller e resetthe controller e return the controller s self test results read and write the controller s SROMs e read the temperature voltage and watchdog sensors get specific information such as thresholds for each sensor read and write the Field Replaceable Unit FRU data reserve and read the Sensor Data Record SDR repository e configure event broadcasts bridge an IPMI request to the public IPMB and return the response Table 7 5 lists the IPMI commands supported by the IPMC along with the hexadecimal values for each command s Network Function Code netFn Logical Unit Number LUN and Command Code Cmd Table 7 5 IPMC IPMI Commands Comma
161. ies Embedded Computing Inc IANA Private Enterprise ID 0x0065CD 26061 Artesyn Embedded Technologies Embedded Computing Inc LSB Byte first byte 1 CD byte 2 65 byte 3 00 0 The sensor ID Flags reserved to 0 Offset in specification Valid offsets 0 1 2 N DoJ nj A Event Data 2 content to be added into the second byte of event data per the IPMI specification Response Data Completion Code 2 4 Artesyn Embedded Technologies Embedded Computing Inc IANA Private Enterprise ID 0x0065CD 26061 Artesyn Embedded Technologies Embedded Computing Inc LSB Byte first byte 2 CD byte 3 65 byte 4 00 ATCA 9305 User s Manual 10009109 07 201 System Management eee ite 7 18 202 Entities and Entity Associations The AdvancedTCA specification see PICMG Engineering Change Notice 3 0 listed in Table A 2 uses Entity IDs and Instances to describe physical components associated with FRUs Device relative Entities are unique to a specific IPMC and are referenced as follows in the specification r lt ipmb gt lt lun gt lt Entity ID gt lt Entity Instance 60 gt ATCA 9305 User s Manual 10009109 07 System Management Using this terminology a ATCA 9305 installed in Logical Slot 1 has the following description in Figure 7 6 Figure 7 6 Entity Structure FRU 0 r 82 0 AO 0 Inflow Temp Outflow Temp Hot Swap Physical BMC Watchdo
162. is sequence the payload should send the Graceful Reset command to the IPMC over the Payload interface to notify the IPMC that the payload shutdown is complete 186 ATCA 9305 User s Manual 10009109 07 System Management To avoid deadlocks that may occur ifthe payload software does not respond the IPMC provides a special time out for the payload shutdown sequence If the payload does not send the Graceful Reset command within a definite period of time the IPMC assumes that the payload shutdown sequence is finished and sends a Module Quiesced Hot Swap event to the ATCA 9305 controller Table 7 36 Get Payload Shutdown Time Out Command Request Data 1 3 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems 5 6 Time Out measured in hundreds of milliseconds LSB first 7 11 21 Set Payload Shutdown Time Out The Set Payload Shutdown Time Out command is defined as follows Table 7 37 Set Payload Shutdown Time Out Command Data Field Request Data PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems Time Out measured in hundreds of milliseconds LSB first Response Data Completion Code PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems ATCA 9305 User s Manual 10009109 07 187
163. ise ID MS Byte first 0x00400A 16394 Pigeon Point Systems ATCA 9305 User s Manual 10009109 07 185 System Management 7 11 19 Diagnostic Interrupt Results The IPMC supports the Issue Diagnostic Interrupt feature of the FRU Control command The payload is notified about a diagnostic interrupt over the SIPL The payload is expected to return diagnostic interrupt results before the payload communication time out using the Diagnostic Interrupt Results command of the SIPL Table 7 35 Diagnostic Interrupt Command Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems 4 If the payload responds before the payload communication time out the diagnostic interrupt return code is forwarded to the carrier controller as the completion code of the FRU Control command response Otherwise the 0xC3 completion code Time Out is returned Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems 7 11 20 Get Payload Shutdown Time Out When the carrier controller commands the IPMC to shut down the payload i e sends the Set Power Level 0 command the IPMC notifies the payload by asserting an appropriate alert and sending an alert notification to the payload Upon receiving this notification the payload software is expected to initiate the payload shutdown sequence After performing th
164. ization agent in progress Destination unavailable cannot deliver request to selected destination This code can be returned if a request message is targeted to SMS but receive message queue reception is disabled for the particular channel Cannot execute command insufficient privilege level Cannot execute command parameter s not supported in present state Unspecified error Device Specific OEM Codes 01 7E Device specific OEM completion codes command specific codes also specific for a particular device and version Interpretation of these codes requires prior knowledge of the device command set Command Specific Codes 80 BE 80 BE Standard command specific codes reserved for command specific completion codes described in this chapter ATCA 9305 User s Manual 10009109 07 141 System Management 7 4 IPMB Protocol The IPMB message protocol is designed to be robust and support many different physical interfaces The IPMC supports messages over the IPMB interface Messages are defined as either a request or a response as indicated by the least significant bit in the Network Function Code of the message Table 7 3 Format for Request Message Byte Bits rsSA 2 Network Function netFn rsLUN 3 Checksum 4 rqSA 5 rqSeq rqLUN 6 Data N 1 Checksum The first byte contains the responder s Slave Address rsSA The second
165. k of storage space required to execute the given command operation Reservation canceled or invalid Reservation ID Request data truncated Request data length invalid Request data field length limit exceeded 140 ATCA 9305 User s Manual 10009109 07 System Management Table 7 2 Completion Codes continued Code Description Parameter out of range one or more parameters in the data field of the Request are out of range This is different from Invalid data field code CC because it indicates that the erroneous field s has a contiguous range of possible values Cannot return number of requested data bytes Requested sensor data or record not present Invalid data field in Request Command illegal for specified sensor or record type Command response could not be provided Cannot execute duplicated request for devices that cannot return the response returned for the original instance of the request These devices should provide separate commands that allow the completion status of the original request to be determined An Event Receiver does not use this completion code but returns the 00 completion code in the response to valid duplicated requests Command response could not be provided SDR Repository in update mode Command response could not be provided device in firmware update mode Command response could not be provided Baseboard Management Controller BMC initialization or initial
166. l ports have failed Definition ping host reset The reset command performs a hard reset of the CPU by writing to the reset register on the board Without any arguments the ATCA 9305 CPU is reset ATCA 9305 User s Manual 10009109 07 255 Management Processor Monitor 9 14 20 9 14 21 MU 256 Definition reset run The run command runs the commands in an environment variable var Definition run var Use for variable substitution the syntax variable name should be used for variable expansion Example gt setenv cons opts console tty0 console ttyS0 baudrate gt printenv cons_opts cons_opts console tty0 console ttyS0 baudrate Use the character to escape execution of the as seen in the setenv command above In this example the value for baudrate will be inserted when cons_opts is executed script The script command runs list of monitor commands out of memory The list is an ASCII string of commands separated by the character and terminated with the characters script address gt is the starting location of the script A script is limited to 1000 characters Description script lt script address gt ATCA 9305 User s Manual 10009109 07 Management Processor Monitor 9 14 22 9 14 23 9 14 24 9 14 25 showmac The showmac command displays the Processor MAC addresses assigned to each Ethernet port Description showmac showpci The showpci
167. lete VLAN 1 on the core switch vlan core delete 1 ATCA 9305 User s Manual 10009109 07 259 Management Processor Monitor 9 15 MPC8548 Environment Variables Press the s key on the keyboard during reset to force the default monitor environment variables to be loaded during hardware initialization but before diagnostic testing Table 9 6 Standard Environment Variables Default Variable Value Description baudrate 9600Bd Console port baud rate Valid rates 9600 14400 19200 38400 57600 115200 Note The older firmware used the default baud rate as 115kBd and also the Octeon console stays with 115kBd bmc_wd_timeou This sets the time out in seconds for the BMC watchdog before t booting the OS If set to 1 then the BMC watchdog is disabled before booting the OS Valid options 1 1 65535 bootcmd Command to execute when auto booting or executing the bootd command bootdelay Choose the number of seconds the Monitor counts down before booting user application code Valid options time in seconds 1 to disable autoboot boot file Path to boot file on server used with TFTP set this to path file bin to specify filename and location of the file to load bootretry Set the number of seconds the Monitor counts down before booting user application code used only with autoboot If the boot commands fails it will try again after bootretry seconds Valid options time in seconds 1 to disable bootre
168. lid rates 9600 14400 19200 38400 57600 115200 ATCA 9305 User s Manual 10009109 07 79 Processor Complex Table 3 6 Standard Cavium Environment Variables continued Variable Default Value Description bootcmd Command to execute when auto booting or executing the bootd command bootdelay Choose the number of seconds the Monitor counts down before booting user application code Valid options time in seconds 1 to disable autoboot boot file Path to boot file on server used with TFTP set this to path file bin to specify filename and location of the file to load ethaddr undefined SPI 1 MAC address ethladdr undefined SPI 2 MAC address Specifies Ethernet port to use 0 0 0 0 Select the network gateway machine IP address hostname none Target hostname ipaddr 0 0 0 0 Board IP address loadaddr 0x20000000 Define the address to download user application code used with TFTP 0 0 0 0 Board sub network mask powerondiags off Turns POST diagnostics on or off after power on reset Valid options on off Path name of the NFS server root file system serverip 0 0 0 0 Boot server IP address stderr serial Sets the standard destination for console error reporting Valid options serial pci stdin serial Sets the standard source for console input Valid options serial pci stdout serial Sets the standard destination for console output Valid options serial pci
169. m 1 C_MUL Clock Divisor 120 Control FC40 0068 R W RTM Control 120 FC40 0064 R W RTM GPIO Control 119 FC40 0060 RTM GPIO State 119 FC40 0054 Miscellaneous Control SIO I2C Test Clock FC40 0070 Boot Device Redirection 116 FC40 0050 FC40 0040 R W Scratch 1 FC40 003C FC40 0038 R W Reset Command Sticky 2 116 Reset Command Sticky 1 115 ATCA 9305 User s Manual 10009109 07 95 Management Complex Table 4 2 MPC8548 Address Summary continued 96 Hex Physical Address Access Mode FC40 0034 FC40 0030 FC40 002C FC40 0028 Register Description Reset Command 5 Reset Command 4 Reset Command 3 Reset Command 2 See Page FC40 0024 Reset Command 1 FC40 0020 Reset Event FC40 001C FC40 0018 R W FC40 0014 FC40 0010 LED Jumper Setting Hardware Configuration 0 FC40 000C PLL Configuration FC40 0008 PLD Version FC40 0004 FC40 0000 R W 11 0000 10 0000 R W Hardware Version Product ID CPLD 512 KB reserved 2 9 MB LPC Interface 64 KB 00 8000 reserved 992 00 0000 R W NAND flash 32 KB F800 0000 F600 0000 R W F400 0000 R W 080 0000 reserved 64 Soldered flash bank 4 32 MB Soldered flash bank 3 32 MB reserved 56 MB F3C0 0000 Soldered flash bank 2 4 MB F380 0000 Soldered flash bank 1 4 MB 000 0000
170. monitor ROM device is installed in the PLCC socket on the ATCA 9305 2 Verify there is a shunt on J9 across pins 1 and 2 3 Issue the following command where serial numberis the board s serial number at the monitor prompt ATCA 9305 1 0 gt moninit serial_number moninit will also reset environment variables to the default state 4 To boot from soldered flash power down the board and remove the shunt from 9 pins 1 and 2 The monitor always resides in the top 1MB block of NOR flash banks 1 and 2 as shown in Table 9 3 Table 9 3 Monitor Address per Flash Device Address Range hex Device F3F8 0000 F400 0000 Monitor Location in Flash Bank2 F3B8 0000 F3C0 0000 Monitor Location in Flash Bank1 F3B7 0000 F3B7 1000 Environment Variables F3F7 0000 F3F7 1000 Redundant Environment Variables Resetting Environment Variables To restore the monitor s standard environment variables execute the following commands and insert the appropriate data in the italicized fields ATCA 9305 User s Manual 10009109 07 Management Processor Monitor 9 4 2 ATCA 9305 1 0 gt moninit serial_number noburn Press the s key on the keyboard during reset to force the default environment variables to be loaded See MPC8548 Environment Variables for more information Optionally save your settings ATCA 9305 1 0 gt saveenv Updating the Monitor via TFTP To update the monitor via TFTP ensure that an a
171. mp Notices eee The Artesyn ATCA 9305 meets the requirements set forth by the Federal Communications Commission FCC in Title 47 of the Code of Federal Regulations The following information is provided as required by this agency This device complies with part 15 of the FCC Rules Operation is subject to the following two conditions 1 This device may not cause harmful interference and 2 this device must accept any interference received including interference that may cause undesired operation FCC Rules and Regulations Part 15 This equipment has been tested and found to comply with the limits for a Class AClass B digital device pursuant to part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environmentin a residential installation This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications Operation of this equipment in a residential areais likely to cause harmful interference in which case the user will be required to correct the interference at his own expense Making changes or modifications to the ATCA 9305 hardware without the explicit consent of Artesyn Embedded Technologies could invalidate the user s authority to operate this equipment EMC Compliance The electromagnetic compat
172. n a location different than what is indicated within the S Record file by adding the value off to the file s absolute address baudrate The baudrate parameter allows the file to be loaded at baud instead of the monitor s console baudrate The file is not automatically executed the loads command only loads the file into memory Definition loads off baud Memory Commands The memory commands allow you to manipulate specific regions of memory For some memory commandis the data size is determined by the following flags Definition The b is for data in 8 bit bytes Definition The is for data in 16 bit words Definition The l is for data in 32 bit long words These flags are optional arguments and describe the objects on which the command operates If you do not specify a flag memory commands default to 32 bit long words Numeric arguments are in hexadecimal ATCA 9305 User s Manual 10009109 07 Management Processor Monitor 9 8 1 9 8 2 9 8 3 cmp The cmp command compares count objects between 1 and addr2 Any differences displayed on the console display Definition cmp b w 1 addrl addr2 count cp The cp command copies count objects located at the source address to the target address If the target address is located in the range of the flash device it will program the flash with count objects from the source address The cp command does not erase the flash
173. nd Set System Boot Options Chassis Get System Boot Options Chassis Set Event Receiver Sensor Event Get Event Receiver Sensor Event Platform Event Event Message Sensor Event Get Device SDR Information Sensor Event 04 05 20 Get Device SDR Sensor Event 04 05 21 Reserve Device SDR Repository Sensor Event 04 05 22 ATCA 9305 User s Manual 10009109 07 147 System Management Table 7 5 IPMC IPMI Commands continued Command netFn LUN Cmd Get Sensor Reading Factors Sensor Event 04 05 23 24 Set Sensor Hysteresis Sensor Event 04 05 Get Sensor Hysteresis Sensor Event 04 05 25 Set Sensor Thresholds Sensor Event 26 Get Sensor Thresholds Sensor Event 27 Set Sensor Event Enable Sensor Event 28 Get Sensor Event Enable Sensor Event 29 Rearm Sensor Events Sensor Event 04 05 2A Get Sensor Event Status Sensor Event 04 05 2B 2D Get Sensor Reading Sensor Event Set Sensor Type Sensor Event 2E Get Sensor Type Sensor Event 2F Get Device ID Application 0 Broadcast Get Device Application 06 07 1 01 Cold Reset Application 06 07 02 03 Warm Reset Application Get Self Test Results Application 04 Get Device GUID Application 08 Reset Watchdog Timer Application 2 2 Set Watchdog Timer Application 06 07 24 Get Watchdog Timer Application 06 07 25 34 Send Message Application Get FRU Inventory Area Info Storage 10 Read FRU Data Stora
174. nect no connect no connect 217 Back Panel Connectors Figure 8 3 Zone 3 Connector m Table 8 5 Zone 3 Connector 33 Assignments RTM_ENABLE RTM_PS1_CONN CONSOLE RX RTM_PB_RST M RTM PP RTM HS LED PQ CONSOLE _ RTM E HANDLE M RTM MP PWRGD IPMB RTM SCL BU no connect RTM RST FF no connect IPMB_RTM_SDA_BU 3 MP 3 MP RTM FF ground ground ground ground 12V RTM 12V RTM 12V RTM 12V RTM 218 ATCA 9305 User s Manual 10009109 07 Chapter 9 Management Processor Monitor eee 9 1 9 2 Overview The ATCA 9305 monitor is based on the Embedded PowerPC Linux Universal Boot U Boot Project program available under the GNU General Public License GPL For instructions on how to obtain the source code for this GPL program please visit www artesyn com This chapter describes the monitor s basic features operation and configuration sequences This chapter also serves as a reference for the monitor commands and functions Command Line Features The ATCA 9305 monitor uses a command line interface with the following features Auto Repeat After entering a command you can re execute it simply by pressing the ENTER or RETURN key Command History Recall previously entered commands using the up and down arrow keys TFTP Boot You can use
175. nitor command prompt in Figure 9 1 is the result of a successful hardware boot of the ATCA 9305 220 ATCA 9305 User s Manual 10009109 07 Management Processor Monitor Figure 9 1 Example MPC8548 Monitor Start up Display U Boot 1 1 4 Jan 8 2007 16 07 48 1 0 Hardware initialization gt CPU 8548_E Version 2 0 0x80390020 Core E500 Version 2 0 0x80210020 Clock Configuration CPU 999 MHz CCB 399 MHz DDR 199 MHz LBC 49 MHz Board ATCA 9305 ATCA Blade Emerson Network Power Embedded Computing Inc cPLD Ver 2 120 ready Clearing ALL of memory DRAM 512 MB Testing Top 1M Area of DRAM PASSED Relocating code to RAM FLASH 4 0000000 4MB e1000000 8 MB L2 cache enabled In serial Out serial Err serial Ser 1096 Diags Mem PASSED Diags I2C PASSED Diags Flash PASSED BootDev Socket I cache enabled D cache enabled write through L2 cache enabled L2CTL 0xa0000000 write through v0 1 1 DOC Turbo Mode Monitor command prompt Net eTSEC1 eTSEC2 gt ATCA 9305 Mon 1 0 gt 9305 User s Manual 10009109 07 221 Management Processor Monitor 2 3 222 This prompt is also displayed as indication that the monitor has finished executing command or function invoked at the command prompt except when the command loads and jumps to a user application The hardware product name ATCA 9305 and curre
176. not in an enclosure store it in a staticshielding bag To ground yourself wear a grounding wriststrap Simply placing the board on top of a static shielding bag does not provide any protection place it on a grounded dissipative mat Do not place the board on metal or other conductive surfaces ATCA 9305 User s Manual 10009109 07 47 Setup 2 2 ATCA 9305 Circuit Board The ATCA 9305 circuit board is an ATCA blade assembly and complies with the PICMG 3 0 mechanical specification It uses a 16 layer printed circuit board with the following dimensions Table 2 1 Circuit Board Dimensions weight pi 12 687 in 11 024 in lt 84 in 4 52 b 322 25 mm 280 01 mm lt 21 33 mm 2 05 This is the typical weight for the ATCA 9305 Board weight varies slightly per configuration contact Technical Support if you require a specific configuration weight 48 ATCA 9305 User s Manual 10009109 07 Setup eee The following figures show the front panel component maps and LED locations for both old ATCA 9305 PCB Rev 1 x board and the new ATCA 9305 PCB Rev 2 x board Figure 2 1 9305 Front Panel PCB Rev 1 x Red Amber Out of Service OOS Green In Service 2 Amber User Defined 3 55 Management Console Reset Blue Hot Swap 1 ATCA 9305 User s Manual 10009109 07 Ethernet Speed top LED
177. nt software version number are displayed in the prompt Prior to the console port being available the monitor will display a four bit hexadecimal value on LED1 through LED4 to indicate the power up status see Table 9 1 See Figure 2 7 for the debug LED locations In the event of a specific initialization error the LED pattern will be displayed and the board initialization will halt Table 9 1 Debug LED Codes BOARD_PRE_INIT start booting setup BATs done SERIAL_INIT console init done CHECKBOARD get processor and bus speeds done SDRAM_INIT RAM ECC init done AFTER_RELOC U Boot relocated to RAM done MISC_R final init including Ethernet done 0x06 GONE_TO_PROMPT 0 00 Basic Operation The monitor performs various configuration tasks upon power up or reset This section describes the monitor operation during initialization of the ATCA 9305 board The flowchart see Figure 9 2 illustrates the power up and global reset sequence bold text indicates environment variables ATCA 9305 User s Manual 10009109 07 Management Processor Monitor 9 3 1 Power up Reset Sequence Power up Reset Sequence Flowchart The ATCA 9305 monitor follows the boot sequence in Figure 9 2 before auto booting the operating system or application software At power up or board reset the monitor performs hardware initialization diagnostic routines autoboot procedures free memory initialization and if necessary invokes the command
178. ntries long The payload can add remove get list at any time The message listener list is not persistent across IPMC reboots Add Message Listener The Add Message Listener command adds a specified Network Function and Command to the Message Listener List The command returns completion code 0x00 and IANA If this command does not complete successfully e g due to a full list it returns OxCD and IANA Table 7 43 Add Message Listener Command Type Byte Data Field Artesyn Embedded Technologies Embedded Computing Inc IANA Private Enterprise ID 0x0065CD 26061 Artesyn Embedded Technologies Embedded Computing Inc LSB Byte first byte 1 CD byte 2 65 byte 3 00 Network function to add Command to add Response Data Completion Code ATCA 9305 User s Manual 10009109 07 System Management 7 16 2 Table 7 43 Add Message Listener Command continued Type Byte Data Field 2 4 Artesyn Embedded Technologies Embedded Computing Inc IANA Private Enterprise ID 0x0065CD 26061 Artesyn Embedded Technologies Embedded Computing Inc LSB Byte first byte 2 CD byte 3 65 byte 4 00 Remove Message Listener The Remove Message Listener command removes a specified Network Function and Command from the Message Listener List The command returns completion code 0x00 and IANA If this command does not complete successfully e g if the Network Function and Command are not in t
179. o nn sede ee 247 9 12 Environment Parameter Commands 247 9 12 1 EX ERE PRESE EXE Y P XO 248 9 1252 EIER 248 9 12 3 S LENV ee een eh ihn 248 9 13 Test Commands une ee RE EE E Ea met eos 249 9 13 E 249 GOS Ecos ose operta er 249 ee ae 249 9 14 Other Commands 2 sa caked wee Peake ees eis gawd had Ah EE pgs 250 9 14 17QUEOSsch 1 4 ai rp 250 9 14 2 s 250 914 3 gt anda 250 9 144 coninfo keins La 251 9 14 5 CFC32 4 cerro SERRE rre TERRE t PR a re e pides 251 914 6 daten RERO T 251 951427 251 9 14 8 sa Renee 252 9 14 9 GO eek re 252 SNB m 252 esa 252 9 14 12ISdFaImi zi RR Rte ies 253 22 na 253 914 Bu 253 1 IE ost eed er ce dee 253 9 14 GDC UT 254 ee 255 12 9305 User s Manual 10009109 07 Contents 9 14 sees TT sed 255 9 14 19 un oh Siva Sie
180. o clear all parameters stored in the IPMC storage bparams_set 0 To add aname value to the storage omitting the value deletes the element from the storage bparams set lt name gt lt value gt To clear all parameters before adding a new name value pair bparams_set 2 lt name gt lt value gt Example To redefine the boot delay bparams_set 1 bootdelay 1 9305 User s Manual 10009109 07 9 11 4 Management Processor Monitor fru The fru command opens closes saves sets shows dumps and loads fru data to and from the IPMC Definition fru lt command gt argl arg2 1 command open close save set show dump load create fru open lt id gt fru close fru save fru set lt section chassis board product gt lt field gt lt value gt fru set lt section gt lt field gt lt value gt section chassis board product fru set chassis lt field gt lt value gt field type part serial fru set board lt field gt lt value gt field date maker name serial part file fru set product lt field gt lt value gt field maker name part version serial asset file fru show fru dump lt address gt fru load lt address gt lt size gt Set data in the internal use area fru set internal lt source addr gt lt internal use offset gt lt count gt ATCA 9305 User s Manual 10009109 07 245 Management P
181. o provide control logic for the local bus The PLD implements various registers for reset hardware and LPC bus communication between the processors The PLD registers start at address FC40 000016 As a rule registers retain their values through all resets except for power on and front panel reset Table 5 1 lists the 8 bit PLD registers followed by the register bit descriptions Table 5 1 PLD Register Summary Address Offset hex Mnemonic Register Name See Page Product ID Hardware Version PLD Version PLL Configuration HCROO Hardware 0 109 Reset Event Reset Command 1 Reset Command 2 RCR3 Reset Command 3 113 RCR4 Reset Command 4 114 Reset Command 5 Reset Command Sticky 1 Reset Command Sticky 2 Scratch 1 BDRR Boot Device Redirection 116 MISC Miscellaneous Control SIO I2C Test Clock 117 Scratch 1 0x40 is a read write register for storage only ATCA 9305 User s Manual 10009109 07 105 Management Processor CPLD Table 5 1 PLD Register Summary continued Address Offset hex Mnemonic Register Name See Page LFTRI Low Frequency Timer 1 118 LFTR2 Low Frequency Timer 2 118 RTM GPIO State RTM GPIO Control RTM Control Cavium 1 C_MUL Clock Divisor Control CMUL2 2 C_MUL Clock Divisor Control 121 JTAG Altera JTAG Chain Software Control 122 GPIO Control GPIO Data Out Cavium GPIO Data In IPMP
182. of six substances cadmium Cd mercury Hg hexavalent chromium Cr VI polybrominated biphenyls PBBs polybrominated diphenyl ethers PBDEs and lead Pb Configurations that are ROHS compliant are built with lead free solder 42 ATCA 9305 User s Manual 10009109 07 Overview Following is the Declaration of Conformity Figure 1 2 Declaration of Conformity Declaration of Conformity DoC According to EN 17050 1 2004 Manufacturer s Name Artesyn Embedded Technologies Manufacturer s Address Artesyn Embedded Technologies GmbH Lilienthalstrasse 17 19 85579 Neubiberg Germany Declares that the following product Product ATCA Blade with Rear Transition Modules Model Names Numbers ATCA 9305 ARTM 9305 6X10GE ARTM 9305 FLASH in accordance with the requirements of 2004 108 EC 2006 95 EC amp 2011 65 EU and their amending directives has been designed and manufactured to the following specifications EN 60950 1 2006 A12 2011 EN 55022 2010 Class A EN 55024 2010 ETSI EN 300 386 V1 6 1 2012 09 2011 65 EU RoHS Directive Cu Kai Holz Director Engineering Issue Date 30 May 2014 sep EMBEDDED TECHNOLOGIES ATCA 9305 User s Manual 10009109 07 43 1 3 3 Terminology and Notation Active low signals An active low signal is indicated with an asterisk after the signal name Byte word Throughout this manual byte refers to 8 bits word refers to 16 bits and lon
183. on RTM GPIO 7 Not used RTM GPIO 6 RTM GPIO 5 RTM GPIO 4 RTM GPIO 3 RTM GPIO 2 RTM GPIO 1 RTM GPIO 0 Do not use if ARTM 9305 6X10GE is connected ATCA 9305 User s Manual 10009109 07 119 Management Processor CPLD 5 1 21 RTM Status The RTM identification ID is determined by factory installed configuration resistors Table 5 22 RTM Control 0x68 Function Description RTMP RTM is Present RTMIDO RTM Identification bits 0 3 RTMID1 0000 Test RTM factory only 1000 18GbE I O RTM 1100 12GbE and 2x10GbE I O RTM 0111 ARTM 9305 6X10GB 1001 ARTM 9305 Flash RTMID2 5 1 22 Cavium 1 C MUL Clock Divisor Control Use the C MUL1 register to reduce the speed of the CN5860 processor 1 core Do not over clock the Cavium frequency bits 6 7 hard strapped 120 ATCA 9305 User s Manual 10009109 07 Management Processor CPLD Table 5 23 1 C Clock Divisor Control 0x70 Function Description CAVF Cavium Frequency resistor set bit read only 00 600 01 750 10 800 11 CMULOE C_MUL Output Enable P1CMUL4 These bits drive directly to the 1 The core clock PICMUL3 speed is the number multiplied by 50 MHz For example the 800 MHz core is set to 16 0x10 P1CMUL2 P1CMUL1 0 P1CMULO 5 1 23 Cavium 2 C MUL Clock Divisor Control Use the C MUL2 register to reduce the spee
184. on command Use value 00h LED Color Capabilities when a bit is set the LED supports the color Bit 7 reserved set to 0 Bit 6 LED supports white Bit 5 LED supports orange Bit 4 LED supports amber Bit 3 LED supports green Bit 2 LED supports red Bit 1 LED supports blue Bit 0 reserved set to 0 ATCA 9305 User s Manual 10009109 07 161 System Management Table 7 13 Get LED Color Capabilities Command continued Type Byte Data Field 4 Default LED Color in Local Control State Bit 7 reserved set to 0 Bits 3 0 Oh reserved 1h Blue 2h Red 3h Green 4h Amber 5h Orange 6h White 7h Fh reserved 5 Default LED Color in Override State Bit 7 reserved set to 0 Bits 3 0 Oh reserved 1h Blue 2h Red 3h Green 4h Amber 5h Orange 6h White 7h Fh reserved 162 ATCA 9305 User s Manual 10009109 07 System Management 7 10 3 Set FRU LED State Command The Set FRU LED State command allows the state of the FRU LEDs to be controlled by the management system Table 7 14 Set FRU LED State Command Type Byte Data Request Data PICMG Identifier indicates that this is a PICMG defined group extension command Use value 2 FRU Device ID 3 LED ID 00h Blue LED Hot Swap LED 1 005 02h LED 2 03h LED 3 04h FEh OEM defined LEDs FFh Lamp Test all LEDs under management control are addressed LED Function LED off ov
185. on Network Voltage UART Universal Asynchronous Receiver transmitter UL Underwriters Laboratories USB Universal Serial Bus VLP Very Low Profile XAUI 10 Gigabit Attachment Unit Interface ATCA 9305 User s Manual 10009109 07 33 About this Manual Conventions The following table describes the conventions used throughout this manual Notation 0x00000000 Description Typical notation for hexadecimal numbers digits are 0 through F for example used for addresses and offsets 050000 Same for binary numbers digits 0 and 1 bold Courier Bold Used to emphasize a word Used for on screen output and code related elements or commands in body text Used to characterize user input and to separate it from system output Reference Used for references and for table and figure descriptions File gt Exit Notation for selecting a submenu lt text gt Notation for variables and keys Notation for software buttons to click on the screen and parameter description Repeated item for example node 1 node 2 node 12 Omission of information from example command that is not necessary at the time being Ranges for example 0 4 means one of the integers 0 1 2 3 and 4 used in registers 34 Logical OR ATCA 9305 User s Manual 10009109 07 About this Manual Notation Description A Indicates a hazardous situation which if not avoided
186. ong Show the header of PCI device bus device function pci header b d f Display the PCI configuration space CFG pci display b w 1 b d f address of objects Modify read and keep the CFG address pci next b w 1 b d f address Modify automatically increment the CFG address pci modify b w 1 b d f address ATCA 9305 User s Manual 10009109 07 Management Processor Monitor 9 14 17 9 14 18 9 14 19 Write to the CFG address pci write b 1 b d f address value phy The phy command reads or writes to the contents of the PHY registers The values changed via this command are not persistent and clear after a hard or soft reset The port options are all eTSEC1 eTSEC2 and and base2 via the switch reads the register contents at the address specified W writes the address value to the register address specified A reads the contents of all registers Definition phy port RIW A address value Example The following is an example of a read from register address Ox1a phy eTSEC2 r Oxla The following is an example of a write to register address 0x1a where 0 is the data to write phy eTSEC2 w Oxla 0 ping The ping command sends a ping over Ethernet to check if the host can be reached The port used is defined by the ethport environment variable If all is selected for ethport the ping process cycles through each port until a connection is found or al
187. ontinued Bits Function Description I2CSCL I C Clock line 0 Drive a 0 onto the I2C SCL line 1 Drive a 1 onto the I2C SCL line 5 1 18 Low Frequency Timer 1 and 2 Registers LFTR1 0x58 and LFTR2 0x5C are timers They determine how many 50 us intervals you want before the next interrupt on Cavium GPIO5 Unless the frequency is set to 0 there is always one 50 us interval This is the reason for the NN register setting being 1 less than an even hundred for example 199 rather than 200 Table 5 19 Low Frequency Timer Settings Frequency Set Register Comments ____ Off Never interrupts 19999 Ox4E1F These frequencies require the use of both registers 1999 0x7CF 100 Hz 199 0xC7 1 KHz 19 0x13 10 KHz 1 This equals two 50 is time units default 118 ATCA 9305 User s Manual 10009109 07 Management Processor CPLD 5 1 19 RTM GPIO State This read only register reads the current state of the GPIO pins Table 5 20 RTM GPIO State 0x60 Function Description GPIO 7 Not used RTM GPIO 6 RTM GPIO 5 RTM GPIO 4 RTM GPIO 3 RTM GPIO 2 1 GPIO 0 Reflects status of the Link Alarm Status Interrupt signal if ARTM 9305 6X10GE is connected 5 1 20 RTM GPIO Control This register sets the state of the GPIO pins These signals are implemented as open collector signals Table 5 21 RTM GPIO Control 0x64 Function Descripti
188. or high availability and if the system documentation explicitly includes guidelines ATCA 9305 User s Manual 10009109 07 23 Safety Notes RJ 45 Connectors The RJ 45 connectors on the face plate must only be used for twisted pair Ethernet connections Connecting a telephone to such a connector may destroy your telephone as well as your board Therefore Clearly mark TPE connectors near your working area as network connectors e Only connect TPE bushing of the system to safety extra low voltage SELV circuits e Make sure that the length of the electric cable connected to a TPE bushing does not exceed 100 If you have further questions ask your system administrator Replacement Expansion Only replace or expand components or system parts with those recommended by Artesyn Embedded Technologies Otherwise you are fully responsible for the impact on EMC or any possible malfunction of the product Check the total power consumption of all components installed see the technical specification of the respective components Ensure that any individual output current of any source stays within its acceptable limits see the technical specification of the respective source Environment Always dispose of used products according to your country s legislation and manufacturer s instructions 24 ATCA 9305 User s Manual 10009109 07 Sicherheitshinweise EN Dieses Kapitel enth lt Hinweise die potentiell gef
189. ort POST 01h Short POST 02h FFh unused Graceful Shutdown nonvolatile 150 The value of Graceful Shutdown Timeout specifies a timer to be used by the IPMC to know how long it has to wait for the payload to shut down gracefully If payload software does not configure its OpenIPMI library to be notified for graceful shutdown requests the IPMC shuts down the payload when the timer expires data 1 LSB of graceful shutdown timeout value in 100 ms data 2 MSB of graceful shutdown timeout value in 100 ms ATCA 9305 User s Manual 10009109 07 System Management 7 9 Table 7 6 Artesyn Boot Option Parameters continued Parameter Parameter Data Boot Firmware 100 The IPMI system boot options command allows controlling the boot Boot Options non process of a blade by storing boot parameters in IPMC non volatile volatile storage The boot firmware interprets the boot parameters during power up and executes the boot process accordingly For detailed information see BOOT FIRMWARE BOOT OPTIONS on page 193 Data 1 Set Selector Must be set to 0 user area You can only write to the user area therefore no other values are supported Data 2 Block Selector Zero based index of the 16 byte block which you want to write to Index 0 refers to the first block of 16 bytes which includes the first two bytes which indicate the boot parameter data size Depending on the total length of the boot firmware data you
190. ory PCI The 8548 performs the functions of a PCI host and monarch and handles all arbitration and enumeration functions PCI starts at physical address 8000 0000 The PCI bus connects to both processors the MPC8548 processor and the Broadcom Ethernet switch see Table 4 4 All of the devices on the PCI bus can operate at 66 MHz and perform 64 bit transactions in conventional PCI mode except for the Broadcom switch The switch has a 32 bit PCI bus ATCA 9305 User s Manual 10009109 07 Management Complex 4 3 1 4 4 The MPC8548 stores the CN5860 operating system and monitor code local memory and then uses the boot over PCI functionality to bring up the CN5860 processor complexes Table 4 4 PCI Device Interrupts and ID Assignments PCI Device Interrupt IDSEL Cavium processor 1 PCI_AD11 Ethernet switch IRQ4 PCI_AD13 MPC8548 PCI_AD14 PCI Express The four lane PCle routes between the MPC8548 and the optional rear transition module zone 3 connector PCle starts at physical address 00 0000 6 INTERFACE The interface consists of the MPC8548 initialization EEPROM user storage NVRAM SO CDIMM and the Real time Clock RTC The two Atmel two wire serial EEPROMs on the I C interface consist of the Serial Clock SCL input and the Serial Data SDA bidirectional lines Table 4 5 Device Addresses Device Address MPC8548 Initialization EEP
191. payload communication time out time the IPMC sends the 0xC3 completion code Time Out in the appropriate Bused Resource command reply ATCA 9305 User s Manual 10009109 07 183 System Management Table 7 33 Bused Resource Status Command Byte Data Field Request Data PPS IANA Private Enterprise MS Byte first 0x00400A 16394 Pigeon Point Systems Command Types for Carrier Controller to Board 0 Query if board has control of the bus 0 In control 1 No control 1 Release request a board to release control of the bus 0 1 Refused 2 No control 2 Force board to release control of bus immediately 0 1 No control 3 Bus Free informs board that the bus is available 0 1 Not needed Command Types for Board to Carrier Controller 0 Request to seize control of the bus 0 Grant 1 Busy 2 Defer 3 Deny 1 Relinquish control of the bus carrier controller can reassign control of bus 0 1 Error 2 Notify carrier controller that control of the bused resource has been transferred to this board from another authorized board 0 1 Error 2 Deny Bused Resource ID 0 Metallic Test Bus pair 1 1 Metallic Test Bus pair 2 2 Synch clock group 1 CLK1A and CLK1B pairs 3 Synch clock group 2 CLK2A and CLK2B pairs 4 Synch clock group 3 CLK3A and CLK3B pairs 6 Status 0 Ack carrier controller acknowledges that board has control 1 Error same as Ack but carrier controller believes
192. peration according to NEBS Standard GR 63 CORE 5 C 23 F to 55 C 131 F exceptional operation according to NEBS Standard GR 63 CORE The blade is designed to operate ina chassis that provides 35 CFM across the blade for the stated temperature range Non Operating 40 C 40 F to 70 C 158 F may be further limited by installed accessories Temp change Rel humidity 0 5 C min according to NEBS Standard GR 63 CORE 5 to 90 non condensing according to Artesyn internal environmental requirements 0 5 C min 5 to 95 non condensing according to Artesyn internal environmental requirements Vibration Shock from 5 to 100 Hz and back to 5 Hz at of 0 1 octave minute 2 Half sine 11 m Sec 30 mSec sec 5 20 Hz at 0 1 g2 Hz 20 200 Hz at 3 0 dB octave Random 20 200 Hz at 3 m Sec Blade level packaging Half sine 6 mSec at 180 m Sec Free fall ATCA 9305 User s Manual 10009109 07 1 200 mm all edges and corners 1 0 m packaged 100 mm unpacked 63 Setup Figure 2 12 Air Flow Graph Module Airflow Impedance Volumetric Flow Rate 3 5 0 01 0 015 4 Pressure Drop Pa o o Qa a o 2 a a o a 20 00 30 00 40 00 Volumetric Flow Rate CFM During the safety qualification of this blade the following on board locations were identified as crit
193. pliant with the HPM 1 specification The prominent features of the firmware upgrade procedure are The upgrade can be performed either over the payload serial interface or IPMB 0 The upgrade procedure is performed while the ATCA 9305 is online and operating normally The upgrades are reliable A failure the download error or interruption does not disturb the ATCA 9305 s ability to continue using the old firmware or its ability to restart the download process The upgrades are reversible The ATCA 9305 IPMC automatically reverts back to the previous firmware if there is a problem when first running the new code and can be reverted manually using the HPM 1 defined Manual Rollback command HPM 1 Reliable Field Upgrade Procedure The HPM 1 upgrade procedure is managed by a utility called the Upgrade Agent The Impitool utility is used as an Upgrade Agent for upgrading the ATCA 9305 IPMC firmware The Upgrade Agent communicates with the IPMC firmware via the payload serial interface or IPMC 0 and uses the AdvancedTCA commands that are described in the HPM 1 specification for upgrading the firmware Updated firmware is packed into an image formatted in compliance with the HPM 1 specification That image is used by Upgrade Agent to prepare and upgrade the IPMC firmware The HPM 1 upgrade procedure includes the following steps ATCA 9305 User s Manual 10009109 07 System Management 7 23 Preparation This step er
194. ponse Data 5 Bit 7 Echo On If this bit is set the IPMC enables echo for the given serial interface Bits 6 4 reserved Bits 3 0 Baud Rate ID The baud rate ID defines the interface baud rate as follows 0 9600 bps 1 19200 bps 2 38400 bps 3 57600 bps unsupported 4 115200 bps unsupported 172 ATCA 9305 User s Manual 10009109 07 System Management 7 11 3 Set Serial Interface Properties The Set Serial Interface Properties command is used to set the properties of a particular serial interface Table 7 19 Set Serial Interface Properties Command Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems Interface ID 0 Serial Debug Interface 1 Payload Interface Bit 7 Echo On If this bit is set the IPMC enables echo for the given serial interface Bits 6 4 reserved Bits 3 0 Baud Rate ID The baud rate ID defines the interface baud rate as follows 0 9600 bps 119200 bps 2 38400 bps 3 57600 bps unsupported 4115200 bps unsupported Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems ATCA 9305 User s Manual 10009109 07 173 System Management 7 11 4 Get Debug Level The Get Debug Level command gets the current debug level of the IPMC firmware Table 7 20 Get Debug Level Command Type Byte Data Field Request Data PPS IA
195. ppropriate VLAN is set up in the Ethernet switch see the ATCA 9305 Quick Start Guide 100091 10 xx and execute the following commands inserting the appropriate data in the italicized fields If necessary edit your network settings ATCA 9305 1 0 gt setenv ipaddr 192 168 1 100 ATCA 9305 1 0 gt setenv gatewayip 192 168 1 1 ATCA 9305 1 0 gt setenv netmask 255 255 255 0 9305 1 0 gt setenv serverip 10 64 16 168 9305 1 0 gt setenv ethport eTSECI Optionally save your settings ATCA 9305 1 0 gt saveenv TFTP the new monitor binary image to memory location 0x100000 ATCA 9305 1 0 gt tftpboot 100000 path_to_file_on_tftp_server Update the monitor ATCA 9305 1 0 gt moninit serial_number 100000 ATCA 9305 User s Manual 10009109 07 227 Management Processor Monitor 9 5 9 5 1 9 5 2 228 If moninit fails burn the new monitor to ROM and follow the recovery steps in the Recovering the Monitor section Monitor Command Reference This section describes the syntax and typographic conventions for the ATCA 9305 monitor commands Subsequent sections in this chapter describe individual commands which fall into the following categories boot memory flash environment variables test and other commands Command Syntax The monitor uses the following basic command syntax Command argument 1 argument 2 argument 3 e Thecommand line
196. r Electronic Equipment method 2 at 30 C 1 3 1 Product Certification The ATCA 9305 has been tested to comply with various standards Table 1 1 Standard Compliance Standard Description UL 60950 1 Legal safety requirements EN 60950 1 IEC 60950 1 CAN CSA C22 2 No 60950 1 CISPR 22 EMC requirements legal on system level predefined CISPR 24 Artesyn system EN 55022 EN 55024 FCC Part 15 Industry Canada ICES 003 AS NZS CISPR 22 EN 300 386 ATCA 9305 User s Manual 10009109 07 41 The product has been partially tested to comply with NEBS Standard GR 1089 CORE NEBS Standard GR 63 CORE ETSI EN 300019 series and PICMG 3 0 Artesyn maintains test reports that provide specific information regarding the methods and equipment used in compliance testing Unshielded external I O cables loose screws or a poorly grounded chassis may adversely affect the ATCA 9305 hardware s ability to comply with any of the stated specifications The Ethernet connection of the equipment or subassembly must be connected with shielded cables that are grounded at both ends 1 3 2 RoHS Compliance The ATCA 9305 is compliant with the European Union s RoHS Restriction of use of Hazardous Substances directive created to limit harm to the environment and human health by restricting the use of harmful substances in electrical and electronic equipment Effective July 1 2006 RoHS restricts the use
197. r software may need to write several blocks of 16 bytes in a row each individually addressed via the block selector Data 3 lt 18 Data which you want to write into the addressed block This will be a chunk of the boot firmware data If less than 16 bytes are written only the provided data is written the remaining bytes in the addressed storage area block are left unchanged IPMC Watchdog Timer Commands The IPMC implements a standardized Watchdog Timer that can be used for a number of system time out functions by System Management Software SMS or by the monitor Setting a time out value of zero allows the selected time out action to occur immediately This provides a standardized means for devices on the IPMB to perform emergency recovery actions Table 7 7 IPMC Watchdog Timer Commands Command See Page Optional Mandatory Reset Watchdog Timer 154 Set Watchdog Timer 154 M Get Watchdog Timer 157 9305 User s Manual 10009109 07 151 System Management 7 9 1 7 9 2 152 Watchdog Timer Actions The following actions are available on expiration of the Watchdog Timer System Reset e System Power Off The System Reset and System Power Off on time out selections are mutually exclusive The watchdog timer is stopped whenever the system is powered down Acommand must be sent to start the timer after the system powers up Watchdog Timer Use Field and Expiration Flags The
198. ress inicmd undefined Command to be executed immediately before jumping to the monitor prompt or executing the boot command 12 Enables the 12 cache Valid options on off loadaddr 0x100000 Define the address to download user application code used with TFTP model 9305 Board model number undefined Sets the IP address and the destination port format is lt ip_addr gt lt port gt netmask Board sub network mask powerondiags Turns POST diagnostics on or off after power on reset Valid options on off ATCA 9305 User s Manual 10009109 07 261 Management Processor Monitor 262 Table 9 6 Standard Environment Variables continued Default Variable Value preboot undefined Description Command to execute immediately before starting the CONFIG_BOOTDELAY countdown and or running the auto boot command entering the interactive mode rootpath eng emerson Path name of the NFS server root file system serial XXXXX Board serial number serverip 0 0 0 0 Boot server IP address tftp_port eTSEC_1 Selects which Ethernet port will be used for tftp Valid options eTSEC_1 eTSEC_2 The monitor supports optional environment variables that enable additional functionality The moninit command see moninit clears all environment variables and sets the standard environment variables to the default values All optional environment variables are remov
199. rise ID MS Byte first 0x00400A 16394 Pigeon Point Systems ATCA 9305 User s Manual 10009109 07 System Management Table 7 17 Get Status Command continued Type Byte Data Field Response Data 5 Bit 7 Graceful Reboot Request If set to 1 indicates that the payload is requested to initiate the graceful reboot sequence Bit 6 Diagnostic Interrupt Request If set to 1 indicates that a payload diagnostic interrupt request has arrived Bit 5 Shutdown Alert If set to 1 indicates that the payload is going to be shutdown Bit 4 Reset Alert If set to 1 indicates that the payload is going to be reset Bit 3 Sensor Alert If set to 1 indicates that at least one of the IPMC sensors detects threshold crossing Bits 2 1 Mode The current IPMC modes are defined as 0 Normal 1 Standalone 2 Manual Standalone Bit 0 Control If set to 0 the IPMC control over the payload is disabled ATCA 9305 User s Manual 10009109 07 169 System Management Table 7 17 Get Status Command continued Type Byte Data Field Response Data 6 Bits 4 7 Metallic Bus 2 Events These bits indicate pending Metallic Bus 2 requests arrived from the carrier controller 0 Metallic Bus 2 Query 1 Metallic Bus 2 Release 2 Metallic Bus 2 Force 3 Metallic Bus 2 Free Bits 0 3 Metallic Bus 1 Events These bits indicate pending Metallic Bus 1 requests arrived from the carrier controller 0 Metallic Bus 1 Query 1 Metallic Bus 1 R
200. rocessor Monitor 9 11 5 9 11 6 246 The fru create command loads a default fru image to a blank fru device fru create lt id gt default lt product name gt fru create lt id gt lt address gt lt size gt lt product name gt fruinit The fruinit command initializes the following fru data fields part number build date and serial number in the board and product sections Definition fruinit lt fru id gt lt part number gt lt build date gt serial number fruled The fruled command allows the application programmer to get the status of the red out of service LED or to turn the LED on or off when an application fails to load Definition fruled get fru id led id led state led function on off gt on time color fruled set fru id led id led function on off on time color Example Turns the red out of service LED on fruled set 0 1 Oxff 02 Turns the red out of service LED off fruled set 0 1 0 02 ATCA 9305 User s Manual 10009109 07 Management Processor Monitor 9 11 7 9 11 8 9 12 ipmchpmfw The ipmchpmfw command restores the previous IPMC firmware from the backup IPMC firmware stored in the controller The upgrade argument upgrades the IPMC firmware with the upgrade image held in memory Definition ipmchpmfw restore upgrade lt source address gt sensor The sensor command probes reads and prints the sensor information from the
201. rostatic Discharge European Telecommunications Standards Institute Extreme Processor FCC Federal Communications Commission FRU Field Replaceable Unit GbE Gigabit Ethernet GNU GNU s Not Unix GPL General Public License Pc Inter integrated Circuit IEC International Electrotechnical Commission IPMB Intelligent Platform Management Bus Intelligent Platform Management Interface In system Programmable In target Probe Joint Test Action Group Keyboard Controller Style Light emitting Diode Low Pin Count Logical Unit Number Medium media Access Control controller Network Equipment Building System NSP Network Services Processor OEM Original Equipment Manufacturer 32 ATCA 9305 User s Manual 10009109 07 About this Manual Abbreviation Definition PCI Peripheral Component Interconnect PCle PCI Express PHY Physical Interface PLD Programmable Logic Device POST Power on Self Test RLDRAM Reduced Latency Dynamic Random Access Memory RMA Return Merchandise Authorization SCP Secure Communications Processor SDR Sensor Data Record SDRAM Synchronous Dynamic Random Access Memory SEL System Event Log SERDES Serializer deserializer 510 Separate I O RLDRAM SO CDIMM Small outline Clocked Dual In line Memory 5 1 4 2 System Packet Interface level 4 phase 2 SROM Serial Read Only Memory TBD To Be Determined TNV Telecommunicati
202. s in and handles these messages the same way as it handles IPMI messages from the 0 bus except that the replies route to either the payload or serial debug interface Messages are entered as case insensitive hex ASCII pairs separated optionally by a space as shown in the following examples 18 00 22 lt newline gt 180022 lt newline gt The does not however support SIPL ASCII text commands as defined by the specification ATCA 9305 User s Manual 10009109 07 143 System Management The IPMC does support Pigeon Point Systems extension commands implemented as OEM commands These commands use Network Function Codes 2E 2F hex and the message body is transferred similarly to raw IPMI messages as described previously The following figures show an example of an extension command request and response respectively Figure 7 2 Extension Command Request Example B8 00 01 40 00 12 Data Pigeon Point IANA Command Code rqSeq 00 Bridge 00 NetFn Code 2E LUN 00 144 ATCA 9305 User s Manual 10009109 07 System Management Figure 7 3 _ Extension Command Response Example y BC 00 01 00 0A 40 00 34 Data Pigeon Point IANA Completion Code Command Code rqSeq 00 Bridge 00 NetFn Code 2 LUN 00 7 6 Message Bridging The M
203. scription Common Header Version Version number of the overall FRU data structure defined by the IPMI FRU specification Internal Use Area Version Version number of the Internal Use Area data structure defined by the IPMI FRU specification Internal Use Size 0x100 bytes are allocated for customer use in this area Board Information Area Version Version number of the Board Information Area data structure defined by the IPMI FRU specification Language Code 0x01 English Manufacturing Date Time Variable expressed as the number of minutes since 12 00 AM on January 1 1996 Board Manufacturer Emerson Board Product Name ATCA 9305 Board Serial Number Variable formatted as 730 XXXX Board Part Number Variable formatted as 10 2 FRU File ID Variable for example fru info inf Product Information Area Version Version number of the Product Information Area data structure defined by the IPMI FRU specification Language Code 0x01 English ATCA 9305 User s Manual 10009109 07 207 System Management 7 21 208 Table 7 50 FRU Definition continued Item Manufacturer Name Product Name Product Part Model Number Product Version Description Emerson ATCA 9305 Variable formatted as 10XXXXXX YY Z Not used same information is provided by the part number Product Serial Number Variable formatted as 730
204. sem Handbuch enthaltenen Informationen dienen ausschlie lich dazu das Wissen von Fachpersonal zu erg nzen k nnen dieses jedoch nicht ersetzen Halten Sie sich von stromf hrenden Leitungen innerhalb des Produktes fern Entfernen Sie auf keinen Fall Abdeckungen am Produkt Nur werksseitig zugelassenes Wartungspersonal oder anderweitig qualifiziertes Wartungspersonal darf Abdeckungen entfernen um Komponenten zu ersetzen oder andere Anpassungen vorzunehmen Installieren Sie keine Ersatzteile oder f hren Sie keine unerlaubten Ver nderungen am Produkt durch sonst verfallt die Garantie Wenden Sie sich f r Wartung oder Reparatur bitte an die f r Sie zust ndige Gesch ftsstelle von Artesyn Embedded Technologies So stellen Sie sicher dass alle sicherheitsrelevanten Aspekte beachtet werden ATCA 9305 User s Manual 10009109 07 25 Sicherheitshinweise EMV Das Produkt wurde in einem Artesyn Embedded Technologies Standardsystem getestet Es erf llt die f r digitale Ger te der Klasse A g ltigen Grenzwerte in einem solchen System gem den FCGRichtlinien Abschnitt 15 bzw EN 55022 Klasse A Diese Grenzwerte sollen einen angemessenen Schutz vor St rstrahlung beim Betrieb des Produktes in Gewerbe sowie Industriegebieten gew hrleisten Das Produkt arbeitet im Hochfrequenzbereich und erzeugt St rstrahlung Bei unsachgem em Einbau und anderem als in diesem Handbuch beschriebenen Betrieb k nnen St rungen im Hochfrequenzbereich auftr
205. set to the Normal mode 0x02 Cold IPMC reset to the Standalone mode 0x03 Cold IPMC reset to the Manual Standalone mode 0x04 Reset the IPMC and enter Upgrade mode Response Data Completion Code 2 4 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems 180 ATCA 9305 User s Manual 10009109 07 System Management 7 11 15 Hang IPMC The IPMC provides a means to test the watchdog timer support by implementing the Hang IPMC command which simulates firmware hanging by entering an endless loop Table 7 31 Hang IPMC Command Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems ATCA 9305 User s Manual 10009109 07 181 System Management 7 11 16 Bused Resource To send a Bused Resource command to the carrier controller the payload uses the Bused Resource command of the SIPL Table 7 32 Bused Resource Command Type Byte Data Field Request Data PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems Command Types for Carrier Controller to Board 0 Query if board has control of the bus 1 Release requests a board to release control of the bus 2 Force board to release control of bus immediately 3 Bus Free informs board that th
206. sor The front panel serial port OCT1 CSL connects to the Cavium 1 Processor The front panel serial port OCT2 CSL connects to the Cavium 2 Processor System Management This product supports an Intelligent Platform Management Controller based on a proprietary BMR H8S AMCc reference design from Pigeon Point Systems The IPMC has an inter integrated circuit 120 controller to support an Intelligent Management Platform Bus IPMB that routes to the AdvancedTCA connector The IPMB allows for features such as remote shutdown remote reset payload voltage monitoring temperature monitoring and access to Field Replaceable Unit FRU data PCI PCle The PCI bus allows for read write memory access between the MPC8548 processor Ethernet switch and processors The four lane PCI Express routes between the MPC8548 and the optional RTM Real time Clock The STMicroelectronics 41 005 RTC provides counters for seconds minutes hours day date month years and century The M41T00S serial interface supports bus and has a super cap backup capable of maintaining the clock for a minimum of two hours Software The Cavium CN5860 processor provides a GNU compiler that implements the MIPS64 Rel 2 instruction set in addition to the specialized instructions and a Linux Board Specific Package BSP including the IP stack optimization The CN5860 also provides libraries that take advantage of the chip s hardwar
207. structions as well as test and programming data DEBUG_TRST Test Reset input signal resets the test access port no connect 3 3 volt power PQ_TCK_R Test Clock Input is the clock input to the boundary scan test BST circuitry no connect PQ_TMS Test Mode Select input pin provides the control signal to determine the transitions of the TAP controller state machine 11 DEBUG_SRESET Soft Reset input signal indicates that the MPC8548 must initiate a System Reset interrupt ground DEBUG_HRESET Hard Reset input signal indicates that complete Power on Reset must be initiated by the MPC8548 12 13 15 PQ CKSTP OUT Checkstop Out indicates the MPC8548 has detected a checkstop condition and has ceased operation 16 ground ATCA 9305 User s Manual 10009109 07 103 Management Complex 4 5 2 Serial Debug Port The console port for the management processor is accessible via the front panel mini B USB connector P7 The supported baud rates for these ports operate at 9600 14400 19200 38400 57600 and 115200 bps Table 4 8 Serial Debug Connector P7 Pin Signal 1 no connect 2 PQ CONSOLE RX C 3 PQ CONSOLE TX C 4 no connect signal ground chassis ground OD chassis ground 104 ATCA 9305 User s Manual 10009109 07 Management Processor CPLD 5 1 MPC8548 PLD Register Summary The ATCA 9305 uses a Programmable Logic Device PLD t
208. t Commands The boot commands provide facilities for booting application programs and operating systems from various devices bootd Execute the command stored in the bootcmd environment variable Definition bootd bootelf The bootelf command boots from an ELF image in memory where address is the load address of the ELF image Definition bootelf address bootm The bootm command boots an application image stored in memory passing any entered arguments to the called application When booting a Linux kernel arg can be the address of an initrd image If addr is not specified the environment variable 10adaddr is used as the default Definition bootm addr arg ATCA 9305 User s Manual 10009109 07 229 Management Processor Monitor 9 6 4 9 6 5 230 bootp The bootp command boots image a network connection using the BootP TFTP protocol If loadaddress or boot filename is not specified the environment variables loadaddr and boot file used as the default Definition bootp loadAddress bootfilename To use network download commands e g bootp bootvx rarpboot tftpboot the environment variables listed in Table 9 4 must be configured To set a static IP these environment variables must be specified through the command line interface Table 9 4 Static IP Ethernet Configuration ipaddr Local IP address for the board serverip TFTP NFS server address netmask Net mask
209. ter specifies the color of the LED in the local state for multi color LEDs If the off first flag parameter is 0 the on part of the blink cycle of the LED precedes the off part of the cycle Otherwise the off part of the blink cycle precedes the on part of the cycle 190 ATCA 9305 User s Manual 10009109 07 System Management 7 11 24 Update Discrete Sensor The Update Discrete Sensor command is used to change the state of a discrete sensor controlled by the payload Table 7 40 Update Discrete Sensor Command Type Byte Data Field Request Data PPS IANA Private Enterprise ID MS Byte first 0 00400 16394 Pigeon Point Systems Sensor ID identifies the payload controlled discrete sensor that has to be updated Update flags 0 0 sensor initialization is complete 1 sensor is in the initial update state 1 2 reserved set to 0 3 0 globally disable events from the sensor 1 leave the global event enable bit intact 4 0 globally enable events from the sensor 1 leave the global event enable bit intact 5 0 globally disable sensor scanning 1 leave the global scanning enable bit intact 6 0 globally enable sensor scanning 1 leave the global scanning enable bit intact 7 reserved set to 0 6 7 New status LSB and new status MSB are the least and most significant bytes of the new sensor state Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point
210. tesyn to notify any person of such revision or changes Electronic versions of this material may be read online downloaded for personal use or referenced in another document as a URL to an Artesyn website The text itself may not be published commercially in print or electronic form edited translated or otherwise altered without the permission of Artesyn It is possible that this publication may contain reference to or information about Artesyn products machines and programs programming or services that are not available in your country Such references or information must not be construed to mean that Artesyn intends to announce such Artesyn products programming or services in your country Limited and Restricted Rights Legend If the documentation contained herein is supplied directly or indirectly to the U S Government the following notice shall apply unless otherwise agreed to in writing by Artesyn Use duplication or disclosure by the Government is subject to restrictions as set forth in subparagraph b 3 of the Rights in Technical Data clause at DFARS 252 227 7013 Nov 1995 and of the Rights in Noncommercial Computer Software and Documentation clause at DFARS 252 227 7014 Jun 1995 Contact Address Artesyn Embedded Technologies Artesyn Embedded Technologies Marketing Communications Lilienthalstr 17 19 2900 S Diablo Way Suite 190 85579 Neubiberg Munich Tempe Arizona 85282 Germany Regulatory Agency Warnings a
211. the antistatic bag and box for future shipping or storage Power Requirements Make sure that the blade is used in an AdvancedTCA shelf connected to 48 VDC up to 60 VDC according to Telecommunication Network Voltage TNV 2 A TNV 2 circuit is a circuit whose normal operating voltages exceed the limits for a safety extra low voltage SELV under normal operating conditions and which is not subject to over voltages from telecommunication networks Table 2 2 Typical Power Requirements Configuration Power 1 0 GHz MPC8548 and 800 MHz Cavium processors board runningat 165 W room temperature with all processors at U Boot prompt xw US and Canada 48 VDC US and Canada 48 VDC ATCA 9305 User s Manual 10009109 07 Setup The exact power requirements for the ATCA 9305 circuit board depend upon the specific configuration of the board including the CPU frequency and amount of memory installed on the board Please contact Artesyn Technical Support at 1 888 412 7832 if you have specific questions regarding the board s power requirements 2 3 2 Environmental Considerations As with any printed circuit board be sure that air flow to the board is adequate Chassis constraints and other factors greatly affect the air flow rate The environmental requirements are as follows Table 2 3 Environmental Requirements Requirement Temperature Airflow Operating 5 C 41 F to 40 C 104 F normal o
212. to be addressed individually For this purpose the block selector field in the request data field is used BOOT DEVICE REDIRECTION BDR The IPMC enables the ATCA 9305 to recover from monitor corruption by booting from a redundant copy in another flash device The mechanism relies on IPMC software internal watchdog to expire when corrupted code fails to reset the timer This watchdog begins counting down as soon as the payload is power cycled or reset If the timer expires approximately 30 seconds the boot redirection will activate and the board will reset Following this automatic reset IPMC will attempt to boot from the next flash device according to Figure 7 4 This sequence will continue until a valid boot image clears the watchdog ATCA 9305 User s Manual 10009109 07 System Management eee The boot redirection order is configurable the bootdev command If ashunt is present 9 1 2 the ATCA 9305 boots from socket When forcing boot from the socket use bootdev and reset from the command line to test boot from a flash device If shunt is not installed on J9 1 2 the ATCA 9305 follows the default boot redirection shown in Figure 7 4 Also reference the Boot Device Redirection register E The System Management IPMC can override the BDFR and swap the flash banks from 1 to 2 7 or2to1 Figure 7 4 Boot Device Diagram 512 socketed flash installed on ATCA 9305 Initial boot attempt is from
213. tors Zones 1 through 3 are described in this chapter Whether individual back panel connectors are populated on the ATCA 9305 depends on the specific product configuration ZONE 1 Connector P10 provides the AdvancedTCA Zone 1 power dual redundant 48 VDC and system management connections Four levels of sequential mating provide proper functionality during live insertion or extraction see Table 8 1 Figure 8 1 Zone 1 Connector P10 33 30 28 25 nC Ou OO oooe 32 27 oO OF Table 8 1 Zone 1 Connector P10 Pin Assignments Pin Signal Insertion Sequence 1 reserved NA 2 reserved NA HAO third HA1 third ATCA 9305 User s Manual 10009109 07 213 Back Panel Connectors Table 8 1 Zone 1 Connector P10 Pin Assignments continued Pin Signal Insertion Sequence HA5 HA6 HA7 odd parity bit IPMBA_SCL IPMBB_SDA no connect no connect no connect no connect no connect no connect no connect no connect P10_CHS_GND 48RTNA 48RTNB no connect no connect 214 ATCA 9305 User s Manual 10009109 07 Back Panel Connectors 8 3 Table 8 1 Zone 1 Connector P10 Pin Assignments continued Pin Signal Insertion Sequence Zone 2 Zone 2 ZD defines backplane connector J23 which supports the data transport interface The Zone 2 conn
214. try boot stopkey Press during power up reset initialization to terminate the monitor autoboot sequence and go to the monitor prompt clearmem Select whether to clear unused SDRAM memory used by monitor is excluded on power up and reset Valid options on off dcache Enables the processor L1 data cache Valid options on off ecc Enable ECC initialization all of memory is cleared during ECC initialization Valid options on off 260 ATCA 9305 User s Manual 10009109 07 Management Processor Monitor Table 9 6 Standard Environment Variables continued Default Variable Value Description ecc_lbit_repo Select the reporting of single bit correctable ECC errors to the rt console errors of 2 or more bits are always reported Valid options on off ethaddr 00 80 F9 9 ATCA 9305 board Ethernet address for TSEC_1 port the last 7 00 00 digits are the board serial number in hex 00 80 F9 9 7 ethladdr 00 80 F9 9 ATCA 9305 board Ethernet address for TSEC_2 port the last 8 00 00 digits are the board serial number in hex 00 80 F9 9 8 FF FF undefined Corresponds to ATCA 9305 processing resources Valid options Not defined in default configuration reported at bootup from the IPMC gatewayip Select the network gateway machine IP address hostname EMERSON_ Target hostname ATCA 9305 icache on Enables the processor L1 instruction cache Valid options on off ipaddr 0 0 0 0 Board IP add
215. umber identification see Figure 2 14 e MPC8548 monitor version number see Figure 9 1 e monitor version number see Figure 3 3 e Version and part number of the operating system if applicable ATCA 9305 User s Manual 10009109 07 67 Setup Whether your board has been customized for options such as a higher processor speed or additional memory License agreements if applicable Figure 2 14 Serial Number and Product ID on Top Side Serial Number Product ID Ned 28 X N lt T m i il lin 2 4 2 Product Repair If you plan to return the board to Artesyn Embedded Technologies for service visit www artesyn com to obtain a Return Merchandise Authorization RMA number We will ask you to list which items you are returning and the board serial number plus your purchase order number and billing information if your ATCA 9305 hardware is out of warranty Contact our Test and Repair Services Department for any warranty questions If you return the board be sure to enclose it in an antistatic bag such as the one in which it was originally shipped Please put the RMA number on the outside of the package so we can handle your problem efficiently Our service department cannot accept material received without an RMA number 68 ATCA 9305 User s Manual 10009109 07 Chapter 3 Cavium Processor Complex 25 3 1 Cavium CN5860 Processor The ATCA 9305 provides two Cavium proc
216. ved 1h Blue 2h Red 3h Green 4h Amber 5h Orange 6h White 7h Fh reserved Override State LED Function is required if either override state or Lamp Test is in effect LED override state is off O1h FAh LED override state is blinking Off duration is specified by this byte on duration specified by byte 8 in tens of milliseconds FBh FEh reserved FFh LED override state is on Override State On Duration is required if either override state or Lamp Test is in effect in tens of milliseconds Override State Color Bits 7 4 reserved set to 0 Bits 3 0 Oh reserved 1h Blue 2h Red 3h Green 4h Amber 5h Orange 6h White 7h Fh reserved 166 ATCA 9305 User s Manual 10009109 07 System Management 7 11 Table 7 15 Get FRU LED State Command continued Type Byte Data Field Response Data 10 Lamp Test Duration is optional if Lamp Test is not in effect hundreds of milliseconds Vendor Commands The IPMC supports additional commands that are specific to Pigeon Point and or Artesyn This section provides detailed descriptions of those extension or SIPL commands Table 7 16 Vendor Command Summary Command netFn LUN Cmd Get Status Get Serial Interface Properties Set Serial Interface Properties Get Debug Level Set Debug Level Get Hardware Address Set Hardware Address Get Handle Switch Set Handle Switch Get Payload Communication Time Out Set Payload Communic
217. vium Table 5 28 Cavium GPIO Data In 0x88 reserved reserved reserved P2GPIO4 Read the value of the Cavium 2 GPIO bit 4 eS P2GPIO3 Read the value ofthe Cavium 2 GPIO bit 3 renee 1 P1GPIOA Read the value of the Cavium 1 GPIO bit 4 0 P1GPIO3 Read the value of the Cavium 1 GPIO bit 3 124 ATCA 9305 User s Manual 10009109 07 5 1 28 5 1 29 Management Processor CPLD IPMP IPMC GPIO Control This register provides access if required to signals between the KSLCPLD and the IPMP as well as to signals between the KSL CPLD and the IPMC The lower two bits can request request the power down of a Cavium core from the sticky reset register Table 5 29 IPMP IPMC GPIO Control 0x8C Bits Function Description IPMC2KSL4 Input only IPMC2KSL3 IPMC2KSL2 IPMC2KSL1 3 IPMP2KSL4 Output only 2 IPMP2KSL3 Output only 1 IPMP2KSL2 Power down signal 2 output Assert high to shut down the core The sticky Cavium reset also causes this to be asserted 0 IPMP2KSL1 Power down signal for Cavium 1 output Assert high to shut down the core The sticky Cavium reset also causes this to be asserted LPC Bus Control This is the control register for the 4 bit LPC bus It allows for communication with the IPMC controller from the management CPU Table 5 30 LPC Bus 0 LPCIE LPC Interrupt Enable ATCA 9305 User s Manual 10009109 07 125 Management Processor CPLD
218. watchdog timer provides a timer use field that indicates the current use assigned to the watchdog timer The watchdog timer provides a corresponding set of timer use expiration flags that are used to track the type of time out s that had occurred The time out use expiration flags retain their state across system resets and power cycles as long as the IPMC remains powered The flags are normally cleared solely by the Set Watchdog Timer command with the exception of the don t log flag which is cleared after every system hard reset or timer time out The Timer Use fields indicate Monitor FRB 2 Time out A Fault resilient Booting level 2 FRB 2 time out has occurred This indicates that the last system reset or power cycle was due to the system time out during POST presumed to be caused by a failure or hang related to the bootstrap processor Monitor POST Time out In this mode the time out occurred while the watchdog timer was being used by the monitor for some purpose other than FRB 2 or OS Load Watchdog OS Load Time out The last reset or power cycle was caused by the timer being used to watchdog the interval from boot to OS up and running This mode requires system management software or OS support The monitor should clear this flag if it starts this timer during POST ATCA 9305 User s Manual 10009109 07 System Management SMS OS Watchdog Time out This indicates that the timer was
219. wer Supply 08 Digital Discrete 03 Payload Power Power Supply 08 Digital Discrete 03 The IPMC implements a Device Sensor Data Record SDR Repository that contains SDRs forthe IPMC the FRU device and each sensor A system management controller may use the Get Device SDR command to read the repository and dynamically discover the capabilities of the board Refer to the IPMI specification listed in Table A 2 for more information on using Sensor Data Records and the Device SDR Repository ATCA 9305 User s Manual 10009109 07 205 System Management 206 Under certain circumstances some sensors connected to the IPMC can generate Event Messages for the system management controller To enable these messages the system management controller must send a Set Event Receiver command to the IPMC along with the address of the Event Receiver Table 7 49 shows the format of an Event Message Table 7 49 Event Message Format Byte Field Description 0 RsSA Responder s Slave Address Address of Event Receiver NetFn RsLUN Net Function Code 0x04 in upper 6 bits Responder s LUN in lower 2 bits Chk 1 Checksum 1 RqSA Requester s Slave Address Address of our board RqSeq RqLUN en Sequence number in upper 6 bits Requester s LUN in lower 2 its Cmd Command Always 0x02 for event message EvMRev Event Message Revision 0x04 for IPMI 1 5 Sensor Type Indicates event class or type of sensor that gen
220. writing a one to a single valid bit then the PLD performs that particular reset and the bit is automatically cleared Table 5 14 Reset Command 5 0x34 Function Description 7 SWIR Switch Reset 6 TSECIR TSEC1 Ethernet to front panel PHY Reset 5 TSEC2R TSEC2 Ethernet to switch PHY Reset 4 3 FPIR FPI Ethernet to front panel PHY Reset BCR Ethernet dual PHY to backplane Base Channel reset 114 ATCA 9305 User s Manual 10009109 07 Management Processor CPLD 5 1 14 M Table 5 14 Reset Command 5 0x34 continued Bits Function Description Reset Command Sticky 1 The read write Reset Command Sticky 1 register forces one of several types of the group complex resets as shown below A reset sequence is first initiated by writing a one to one or more bits then the PLD performs that particular reset The bit will persist until cleared The board powers down and powers back up when the Cavium processors power is back up bits 0 or 1 are cleared Table 5 15 Reset Command Sticky 1 0x38 Function Description Cavium 1 Complex reset Cavium 2 Complex reset 7 6 5 Switch Complex reset 4 CAV1CF Cavium 1 Complex 4MB Flash reset 3 CAV2CF Cavium 2 Complex 4MB Flash reset 2 NANDF NAND Flash reset 1 CAV2RPD Reset and power down the Cavium 2 core 0 CAV1RPD Reset and power down the Cavium 1 core ATCA 9305 User s Manual 10009109 07 115 Management Processor CPLD
221. x20 continued Bits Function Description ___ Front Panel Push Button FP_PSH_BUTTN POR_RST Reset Command 1 The write only Reset Command 1 register forces one of several types of resets as shown below A reset sequence is first initiated by writing a one to a single valid bit then the PLD performs that particular reset and the bit is automatically cleared Table 5 10 Reset Command 1 0x24 Bits Function Description WBR Reset the Whole Board PQCR Reset the MPC8548 Complex CAVICR Reset the Cavium CN5860 1 Complex CAV2CR Reset the Cavium CN5860 2 Complex Reset the switch BCM5680x Complex Reset the I2C on the MPC8548 1 RTMR Reset the optional RTM 0 reserved Reset Command 2 The write only Reset Command 2 register forces one of several types of MPC8548 resets as shown below A reset sequence is first initiated by writing a one to a single valid bit then the PLD performs that particular reset and the bit is automatically cleared Table 5 11 Reset Command 2 0x28 Bits Function Description PQHR MPC8548 Hardware Reset 6 MPC8548 Software Reset ATCA 9305 User s Manual 10009109 07 Management Processor CPLD Table 5 11 Reset Command 2 0x28 continued Bits Function Description 5 PQDR MPC8548 DDR SDRAM Reset 4 PQF MPC8548 Flash reset 3 NANDR MPC8548 NAND flash Reset 2 NANDWR MPC8548 NAND flash Warm Reset 1 reserved 0 reserved

ATCA-9305 User`s Manual - Artesyn Embedded Technologies

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