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MPC755 RISC Microprocessor Hardware Specifications

1. I ale al NOTES EIER 4 DIMENSIONING AND TOLERANCING PER ASME Y14 5M 1994 2 DIMENSIONS IN MILLIMETERS 3 TOP SIDE A1 CORNER INDEX IS A E E METALIZED FEATURE WITH VARIOUS p SHAPES BOTTOM SIDE A1 CORNER IS p DESIGNATED WITH A BALL MISSING l FROM THE ARRAY Millimeters v SSE eee eae DIM Min Max B 1234567 8 910111213141516 171819 LIII W A 2 22 2 77 00000000 OCCOCCOCCCC 0000000000000000000 U D A1 0 50 0 70 TTT TTT V A2 100 120 TTT b TTT TTT A3 0 60 ZZ f b ITZIG p b 0 60 0 90 EES e Seeeeeeeeeeeeeeeeee D 25 00 BSC COCOOOOOOOOOOOCOOOOO ITT Silo AB D1 6 75 TTT A2 CITT E 25 00 BSC TTT ES i TTTTTITTTTTITTTT A 787 gt A lt S e 0 3 C AIB e 1 27 BSC ee 0 15 C 360X Figure 20 Mechanical Dimensions and Bottom Surface Nomenclature for the MPC755 360 PBGA Package MPC755 RISC Microprocessor Hardware Specifications Rev 8 Freescale Semiconductor 35 System Design Information 8 System Design Information This section provides electrical and thermal design recommendations for successful application of the MPC755 8 1 PLL Configuration The MPC755 PLL is configured by the PLL_CFG 0 3 signals For a given SYSCLK bus frequency the PLL configuration signals set the internal CPU and VCO frequency of operation These must be chosen such that they comply
2. 1 21 2005 Updated document template Removed 450 MHz speed grade throughout document These devices are no longer supported for new designs see Section 1 10 2 for more information Relaxed voltage sequencing requirements in Notes 3 and 4 of Table 1 Corrected Note 2 of Table 7 Changed processor descriptor from B to C for 400 MHz devices and increased power specifications for full power mode in Table 7 XPC755Bxx400LE devices are no longer produced and are documented in a separate part number specification see Section 1 10 2 for more information Increased power specifications for sleep mode for all speed grades in Table 7 Removed Sleep Mode PLL and DLL Disabled Typical specification from Table 7 this is no longer tested or characterized Added Note 4 to Table 7 Revised L2 clock duty cycle specification in Table 11 and changed Note 7 Corrected Note 3 in Table 20 Replaced Table 21 and added Tables 22 and 23 Added Note 6 to Table 10 clarification only as this information is already documented in the MPC750 RISC Microprocessor Family User s Manual Revised Figure 24 and Section 1 8 7 Corrected Process Identifier for 450 MHz part in Table 20 Added XPC755BRXnnnTx series to Table 21 MPC755 RISC Microprocessor Hardware Specifications Rev 8 50 Freescale Semiconductor Document Revision History Table 19 Document Revision
3. T is the air temperature rise within the computer cabinet Qj is the junction to case thermal resistance Oint is the adhesive or interface material thermal resistance O a is the heat sink base to ambient thermal resistance P is the power dissipated by the device During operation the die junction temperatures Tj should be maintained less than the value specified in Table 3 The temperature of air cooling the component greatly depends on the ambient inlet air temperature and the air temperature rise within the electronic cabinet An electronic cabinet inlet air temperature T may range from 30 to 40 C The air temperature rise within a cabinet T may be in the range of 5 to 10 C The thermal resistance of the thermal interface material Dal is typically about 1 C W Assuming a T of 30 C a T of 5 C a CBGA package Ro lt 0 1 and a power consumption Pq of 5 0 W the following expression for T is obtained Die junction temperature Tj 30 C 5 C 0 1 C W 1 0 C W Osa x 5 0 W For a Thermalloy heat sink 2328B the heat sink to ambient thermal resistance 0 versus airflow velocity is shown in Figure 28 Assuming an air velocity of 0 5 m s we have an effective R of 7 C W thus T 30 C 5 C 0 1 C W 1 0 C W 7 C W x 5 0 W resulting in a die junction temperature of approximately 76 C which is well within the maximum operating temperature of the component Other heat sinks offered by Aavid
4. 11 3 7 Output hold times tlecHox ns 3 All outputs when L2CR 14 15 00 0 5 All outputs when L2CR 14 15 01 0 7 All outputs when L2CR 14 15 10 0 9 All outputs when L2CR 14 15 11 1 1 MPC755 RISC Microprocessor Hardware Specifications Rev 8 Freescale Semiconductor 19 Electrical and Thermal Characteristics Table 12 L2 Bus Interface AC Timing Specifications continued At recommended operating conditions see Table 3 All Speed Grades Parameter Symbol Unit Notes Min Max L2SYNC_IN to high impedance tLocHoz ns 3 5 All outputs when L2CR 14 15 00 2 4 All outputs when L2CR 14 15 01 2 6 All outputs when L2CR 14 15 10 2 8 All outputs when L2CR 14 15 11 3 0 Notes 1 2 Rise and fall times for the L2ESYNC_IN input are measured from 20 to 80 of L2OVpp All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising edge of the input L2ESYNC_IN see Figure 8 Input timings are measured at the pins All output specifications are measured from the midpoint voltage of the rising edge of L2ESYNC_IN to the midpoint of the signal in question The output timings are measured at the pins All output timings assume a purely resistive 50 Q load see Figure 10 The outputs are valid for both single ended and differential L2CLK modes For pipelined registered synchrono
5. L2CLK frequency flock 80 450 MHz 1 4 L2CLK cycle time tL2CLK 2 5 12 5 ns L2CLK duty cycle teHcer tL2cLK 45 55 2 7 Internal DLL relock time 640 L2CLK 3 7 DLL capture window 0 10 ns 5 7 L2CLK_OUT output to output skew tlocskw 50 ps 6 7 L2CLK_OUT output jitter 150 ps 6 7 Notes 1 L2CLK outputs are L2CLK_OUTA L2CLK_OUTB L2CLK_OUT and L2SYNC_OUT pins The L2CLK frequency to core frequency settings must be chosen such that the resulting L2CLK frequency and core frequency do not exceed their respective maximum or minimum operating frequencies The maximum L2LCK frequency will be system dependent L2CLK_OUTA and L2CLK_OUTB must have equal loading 2 The nominal duty cycle of the L2CLK is 50 measured at midpoint voltage 3 The DLL relock time is specified in terms of L2CLK periods The number in the table must be multiplied by the period of L2CLK to compute the actual time duration in ns Relock timing is guaranteed by design and characterization 4 The L2CR L2SL bit should be set for L2CLK frequencies less than 110 MHz This adds more delay to each tap of the DLL 5 Allowable skew between L2SYNC_OUT and L2SYNC_IN 6 This output jitter number represents the maximum delay of one tap forward or one tap back from the current DLL tap as the phase comparator seeks to minimize the phase difference between L2SYNC_IN and the internal L2CLK This number must be comprehended in the L2 timing analysis The input jitter on SYSC
6. tkHoz Le Except TS ABB ARTRY DBB lt tkHaBpz mg cl KHOV Le el tkHoz SE F KHOX SCH gt Le tkHov lt TS ABB DBB X I tkHarpz gt t gt a tkHOV gt KHOV tkHARP gt ARTRV gt p ARTRY S VM Midpoint Voltage OVpp 2 or V 2 Figure 6 Input Output Timing Diagram 4 2 3 L2 Clock AC Specifications The L2CLK frequency is programmed by the L2 configuration register L2CR 4 6 core to L2 divisor ratio See Table 17 for example core and L2 frequencies at various divisors Table 11 provides the potential range of L2CLK output AC timing specifications as defined in Figure 7 The minimum L2CLK frequency of Table 11 is specified by the maximum delay of the internal DLL The variable tap DLL introduces up to a full clock period delay in the L2CLK_OUTA L2CLK_OUTB and L2SYNC_OUT signals so that the returning L2SYNC_IN signal is phase aligned with the next core clock divided by the L2 divisor ratio Do not choose a core to L2 divisor which results in an L2 frequency below this minimum or the L2CLK_OUT signals provided for SRAM clocking will not be phase aligned with the MPC755 core clock at the SRAMs The maximum L2CLK frequency shown in Table 11 is the core frequency divided by one Very few L2 SRAM designs will be able to operate in this mode especially at higher core frequencies Therefore most designs will select a greater core to L2 divisor to provide a longer L2C
7. History continued Revision Date Substantive Change s 4 Added 450 MHz speed bin Changed Table 16 to show 450 MHz part in example Added row for 433 and 450 MHz core frequencies to Table 17 In Section 1 8 8 revised the heat sink vendor list In Section 1 8 8 2 revised the interface vendor list 3 Ee Updated format and thermal resistance specifications of Table 4 Reformatted Tables 9 10 11 and 12 Added dimensions A3 D1 and E1 to Figures 18 19 and 20 Revised Section 1 8 7 and Figure 25 removed Figure 26 and Table 19 information now included in Figure 25 Reformatted Section 1 10 Clarified address bus and address attribute pull up recommendations in Section 1 8 7 Clarified Table 2 Updated voltage sequencing requirements in Table 1 and removed Section 1 8 3 2 1 8 V 2 0 V mode no longer supported added 2 5 V support Removed 1 8 V 2 0 V mode data from Tables 2 3 and 6 Added 2 5 V mode data to Tables 2 3 and 6 Extended recommended operating voltage down to 1 8 V for Vpp AVpp and L2AVpp for 300 and 350 MHz parts in Table 3 Updated Table 7 and test conditions for power consumption specifications Corrected Note 6 of Table 9 to include TLBISYNC as a mode select signal Updated AC timing specifications in Table 10 Updated AC timing specifications in Table 12 Corrected AC timing specifications in Table 13 Added L1_TST
8. Thermalloy Alpha Novatech The Bergquist Company IERC Chip Coolers and Wakefield Engineering offer different heat sink to ambient thermal resistances and may or may not need airflow MPC755 RISC Microprocessor Hardware Specifications Rev 8 48 Freescale Semiconductor System Design Information a g LL O 1 f o 11 4 A Heat Sink Thermal Resistance C W t t 0 5 1 1 5 2 2 5 3 3 5 Approach Air Velocity m s Figure 28 Thermalloy 2328B Heat Sink to Ambient Thermal Resistance Versus Airflow Velocity Though the die junction to ambient and the heat sink to ambient thermal resistances are a common figure of merit used for comparing the thermal performance of various microelectronic packaging technologies one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three dimensional heat flow The final die junction operating temperature is not only a function of the component level thermal resistance but the system level design and its operating conditions In addition to the component s power consumption a number of factors affect the final operating die junction temperature airflow board population local heat flux of adjacent components heat sink efficiency heat sink attach heat sink placement next level interconnect technology system air temperature rise altitude etc Due to the complexity and the
9. This Document Note that the individual part numbers correspond to a maximum processor core frequency For available frequencies contact your local Freescale sales office In addition to the processor frequency the part numbering scheme also includes an application modifier which may specify special application conditions Each part number also contains a revision code which refers to the die mask revision number Section 10 2 Part Numbers Not Fully Addressed by This Document lists the part numbers which do not fully conform to the specifications of this document These special part numbers require an additional document called a hardware specifications addendum 10 1 Part Numbers Fully Addressed by This Document Table 20 provides the Freescale part numbering nomenclature for the MPC755 and MPC745 devices fully addressed by this document Table 20 Part Numbering Nomenclature MPC XXX x XX nnn x x Product Part Process 1 Processor fet Gei gn Cade Identifier Descriptor Package Frequency Application Modifier Revision Level XPC 755 B HiP4DP PX PBGA 300 L 2 0 V 100 mV E 2 8 PVR 0008 3203 745 RX CBGA 350 0 to 105 C 755 C HiP4DP 400 MPC 755 B HiP4DP 300 350 C HiP4DP 350 400 745 B HiP4DP PX PBGA 300 350 745 C HiP4DP PX PBGA 350 VT PBGAPb free BGA 755 B HiP4DP_ VT PBGAPb 300 745 free BGA 350 755 C HiP4DP 350 400 Notes 1 See Sec
10. devices When data is held low SW2 is closed SW1 is open and Ry is trimmed until the voltage at the pad equals L2 OVpp 2 Ry then becomes the resistance of the pull down devices When data is held high SW1 is closed SW2 is open and Rp is trimmed until the voltage at the pad equals L2 OVpp 2 Rp then becomes the resistance of the pull up devices MPC755 RISC Microprocessor Hardware Specifications Rev 8 Freescale Semiconductor 39 System Design Information Figure 22 describes the driver impedance measurement circuit described above L2 OVpp L2 OVpp Rn SW2 Pad Data Swi Rp OGND Figure 22 Driver Impedance Measurement Circuit Alternately the following is another method to determine the output impedance of the MPC755 A voltage source Vforce 18 connected to the output of the MPC755 as shown in Figure 23 Data is held low the voltage source is set to a value that is equal to L2 OVpp 2 and the current sourced by Vforce 18 measured The voltage drop across the pull down device which is equal to L2 OVpp 2 is divided by the measured current to determine the output impedance of the pull down device Ry Similarly the impedance of the pull up device is determined by dividing the voltage drop of the pull up L2 OVpp 2 by the current sank by the pull up when the data is high and V force 18 equal to L2 OV pp 2 This method can be employed with either empirical data from a test setup or with data from simulation models s
11. entry two way set associative instruction TLB 128 entry two way set associative data TLB Hardware reload for TLBs Hardware or optional software tablewalk support Eight instruction BATs and eight data BATs Eight SPRGs for assistance with software tablewalks Virtual memory support for up to 4 exabytes 2 of virtual memory Real memory support for up to 4 gigabytes 232 of physical memory Bus interface Compatible with 60x processor interface 32 bit address bus 64 bit data bus 32 bit mode selectable Bus to core frequency multipliers of 2x 3x 3 5x 4x 4 5x 5x 5 5x 6x 6 5x 7x 7 5x 8x 10x supported Selectable interface voltages of 2 5 and 3 3 V Parity checking on both address and data buses Power management Low power design with thermal requirements very similar to MPC740 MPC750 Three static power saving modes doze nap and sleep Dynamic power management Integrated thermal management assist unit On chip thermal sensor and control logic Thermal management interrupt for software regulation of junction temperature Testability LSSD scan design IEEE 1149 1 JTAG interface General Parameters The following list provides a summary of the general parameters of the MPC755 Technology 0 22 um CMOS six layer metal Die size 6 61 mm x 7 73 mm 51 mm Transistor count 6 75 million Logic design Fully static MPC755 RISC Microprocessor Har
12. many variations of system level boundary conditions for today s microelectronic equipment the combined effects of the heat transfer mechanisms radiation convection and conduction may vary widely For these reasons we recommend using conjugate heat transfer models for the board as well as system level designs MPC755 RISC Microprocessor Hardware Specifications Rev 8 Freescale Semiconductor 49 Document Revision History 9 Document Revision History Table 19 provides a revision history for this hardware specification Table 19 Document Revision History Revision Date Substantive Change s 8 2 8 2006 Changed processor descriptor from B to C for 350 MHz devices and increased power specifications for full power mode in Table 7 4 05 2005 Removed phrase for the ceramic ball grid array CBGA package from Section 8 8 this information applies to devices in both CBGA and PBGA packages Figure 24 updated COP Connector Diagram to recommend a weak pull up resistor on TCK Table 20 added MPC745BPXLE MPC755BRXLE MPC755BPXLE MPC755CVTLE MPC755BVTLE and MPC745BVTLE part numbers These devices are fully addressed by this document Corrected Revision Level in Table 23 Rev E devices are Rev 2 8 not 2 7 Added MPC755CRX400LE and MPC755CPX400LE to devices supported by this specification in Table 20 Removed Advance Information from title block on page 1 6 1
13. register and memory examination modification and other standard debugger features are possible through this interface and can be as inexpensive as an unpopulated footprint for a header to be added when needed The COP interface has a standard header for connection to the target system based on the 0 025 square post 0 100 centered header assembly often called a Berg header The connector typically has pin 14 removed as a connector key MPC755 RISC Microprocessor Hardware Specifications Rev 8 42 Freescale Semiconductor System Design Information SRESET From Target Board Sources lt HRESET if any SE HRESET sl Dk k a Z OS E A Eea A N a COP Connector Physical Pin Out pN O o I Q O O Notes 1 RUN STOP normally found on pin 5 of the COP header is not implemented on the MPC755 Connect pin 5 of the COP header to OVpp with a 10 kQ pull up resistor 2 Key location pin 14 is not physically present on the COP header 3 Component not populated Populate only if debug tool does not drive QACK 4 Populate only if debug tool uses an open drain type output and does not actively deassert QACK 5 If the JTAG interface is implemented connect HRESET from the target source to TRST from the COP header though an AND gate to TRST of the part If the JTAG interface is not implemented connect HRESET from the target source to TRST of the part through a 0 Q isolation resistor 6 T
14. top surface Part B shows the side profile of the PBGA package to indicate the direction of the top surface view Part A Part B Substrate Assembly View Encapsulant Die A 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Not to Scale Pin Assignments Figure 16 Pinout of the MPC745 255 PBGA Package as Viewed from the Top Surface MPC755 RISC Microprocessor Hardware Specifications Rev 8 Freescale Semiconductor 25 Pin Assignments Figure 17 in Part A shows the pinout of the MPC755 360 PBGA and 360 CBGA packages as viewed from the top surface Part B shows the side profile of the PBGA and CBGA package to indicate the direction of the top surface view Part A 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Not to Scale es E elt 7D Ue Ser Ae et on mM oO DS Part B Substrate Assembly View Encapsulant ch el AAA AA AA A AAA AAA AA A A J Figure 17 Pinout of the MPC755 360 PBGA and CBGA Packages as Viewed from the Top Surface MPC755 RISC Microprocessor Hardware Specifications Rev 8 26 Freescale Semiconductor 6 Pinout Listings Table 14 provides the pinout listing for the MPC745 255 PBGA package Table 14 Pinout Listing for the MPC745 255 PBGA Package Pinout Listings Signal Name Pin Number Active HO I F Voltage Notes A 0 31 C16 E4 D13 F2 D14 G1 D15 E2 D16 D4 E13 G2 High
15. 03 400 40 to 105 C E 2 8 PVR 0008 3203 MPC 755 C HiP4DP RX CBGA 350 T 20V 100mV E 2 8 PVR 0008 3203 40 to 105 C Table 22 Part Numbers Addressed by XPC755BxxnnnLD Series Part Numbers Document No MPC755ECSO2AD XPC xxx B XX nnn L D Product Part Process Processor nae Ga CC Code Identifier Descriptor Package Frequency Application Modifier Revision Level XPC 755 B HiP4DP PX PBGA 300 L 2 0 V 100 mV D 2 7 PVR 0008 3203 745 RX CBGA 350 0 to 105 C 400 Table 23 Part Numbers Addressed by XPC755xxxnnnLE Series Part Numbers Document No MPC755ECSO3AD XPC 755 Xx XX nnn L E Product Part Process Processor TO ve CA Code Identifier Descriptor Package Frequency Application Modifier Revision Level XPC 755 B HiP4DP RX CBGA 400 L 2 0 V 100 mV E 2 8 PVR 0008 3203 0 to 105 C PX PBGA C HiP4DP RX CBGA 450 MPC755 RISC Microprocessor Hardware Specifications Rev 8 54 Freescale Semiconductor Ordering Information 10 3 Part Marking Parts are marked as the example shown in Figure 29 e Coo Sq w Ps Pa XPC745B MPC755C PX350LE RX400LE MMMMMM MMMMMM ATWLYYWWA ATWLYYWWA 745 755 BGA BGA Notes MMMMM M is the 6 digit mask number ATWLYYWWA is the traceability code CCCCC is the country of assembly This space is left blank if parts are assembled in the United States Figure 29 Part Marking for BGA Device MPC755 RI
16. 100 Q 1 KQO These pins are L1_TSTCLK L2_TSTCLK and LSSD_MODE These signals are for factory use only and must be pulled up to OVpp for normal machine operation In addition CKSTP_OUT is an open drain style output that requires a pull up resistor 1 5 KQO if it is used by the system During inactive periods on the bus the address and transfer attributes may not be driven by any master and may therefore float in the high impedance state for relatively long periods of time Since the MPC755 must continually monitor these signals for snooping this float condition may cause additional power draw by the input receivers on the MPC755 or by other receivers in the system These signals can be pulled up through weak 10 kQ pull up resistors by the system or may be otherwise driven by the system during inactive periods of the bus to avoid this additional power draw but address bus pull up resistors are not necessary for proper device operation The snooped address and transfer attribute inputs are A 0 31 AP 0 3 TT 0 4 TBST and GBL The data bus input receivers are normally turned off when no read operation is in progress and therefore do not require pull up resistors on the bus Other data bus receivers in the system however may require pull ups or that those signals be otherwise driven by the system during inactive periods by the system The data bus signals are DH 0 31 DL 0 31 and DP 0 7 If 32 bit data bus mo
17. 755 Figure 11 AC Test Load for the JTAG Interface MPC755 RISC Microprocessor Hardware Specifications Rev 8 22 Freescale Semiconductor Electrical and Thermal Characteristics Figure 12 provides the JTAG clock input timing diagram TCLK VM Midpoint Voltage OVpp 2 Figure 12 JTAG Clock Input Timing Diagram Figure 13 provides the TRST timing diagram TRST VM VM gd ttRst beem i VM Midpoint Voltage OVpp 2 Figure 13 TRST Timing Diagram Figure 14 provides the boundary scan timing diagram TCK tpvuH Joan lt lt Boundary Input Ke Data Inputs TE NT Data Valid gt Lu pw Be Wgd lt ty D gt Boundary Output Data Outputs Valid Le JLDZ gt Boundary Data Outputs Output Data Valid VM Midpoint Voltage OVpp 2 Figure 14 Boundary Scan Timing Diagram MPC755 RISC Microprocessor Hardware Specifications Rev 8 Freescale Semiconductor 23 Electrical and Thermal Characteristics Figure 15 provides the test access port timing diagram TCK TDI TMS Hay Data Valid E gt tiov lt tJLOH TDO Valid N S o lt tyLoz TDO Output Data Valid VM Midpoint Voltage OVpp 2 Figure 15 Test Access Port Timing Diagram MPC755 RISC Microprocessor Hardware Specifications Rev 8 24 Freescale Semiconductor 5 Pin Assignments Figure 16 in Part A shows the pinout of the MPC745 255 PBGA package as viewed from the
18. CLK L2_TSTCLK and LSSD_MODE pull up requirements to Section 1 8 6 Corrected Figure 22 MPC755 RISC Microprocessor Hardware Specifications Rev 8 Freescale Semiconductor 51 Document Revision History Table 19 Document Revision History continued Revision 1 Date Substantive Change s Corrected errors in Section 1 2 Removed references to MPC745 CBGA package in Sections 1 3 and 1 4 Added airflow values for O j to Table 5 Corrected Vu maximum for 1 8 V mode in Table 6 Power consumption values added to Table 7 Corrected tyyxRH in Table 9 deleted Note 2 application note reference Added Max flack and Min Hack values to Table 11 Updated timing values in Table 12 Corrected Note 2 of Table 13 Changed Table 14 to reflect I F voltages supported Removed 133 and 150 MHz columns from Table 16 Added document reference to Section 1 7 Added DBB to list of signals requiring pull ups in Section 1 8 7 Removed log entries from Table 20 for revisions prior to public release Product announced Documentation made publicly available MPC755 RISC Microprocessor Hardware Specifications Rev 8 52 Freescale Semiconductor Ordering Information 10 Ordering Information Ordering information for the devices fully covered by this specification document is provided in Section 10 1 Part Numbers Fully Addressed by
19. ELELEELEEEEEEEEEEEEE LELELELELEEEEEEEEEEL LELEEELEEEEEELEEEEEL LELELEELEEEEEEEEEEU KELLELLEEEELEEKEKEEU KEKKELKEKEKEEEKEEEKE gt voomnorecarazzvv c lt lt Al i t e 0 3 C A B H 0 15 C 360x b 2 3 D A NOTES L DIMENSIONING AND TOLERANCING PER ASME Y14 5M 1994 DIMENSIONS IN MILLIMETERS TOP SIDE A1 CORNER INDEX IS A METALIZED FEATURE WITH VARIOUS SHAPES BOTTOM SIDE A1 CORNER IS DESIGNATED WITH A BALL MISSING FROM THE ARRAY Millimeters DIM Min Max A 2 65 3 20 Al 0 79 0 99 A2 1 10 1 30 A3 0 60 b 0 82 0 93 D 25 00 BSC D1 6 75 E 25 00 BSC E1 7 87 e 1 27 BSC Figure 19 Mechanical Dimensions and Bottom Surface Nomenclature for the MPC755 360 CBGA Package MPC755 RISC Microprocessor Hardware Specifications Rev 8 34 Freescale Semiconductor cke Description 7 5 Package Parameters for the MPC755 PBGA The package parameters are as provided in the following list The package type is 25 x 25 mm 360 lead plastic ball grid array PBGA Package outline 25 x 25 mm Interconnects 360 19 x 19 ball array 1 Pitch 1 27 mm 50 mil Minimum module height 2 22 mm Maximum module height 2 77 mm Ball diameter 0 75 mm 29 5 mil 7 6 Mechanical Dimensions for the MPC755 Figure 20 provides the mechanical dimensions and bottom surface nomenclature for the MPC755 360 PBGA package 2X lt D A A1
20. ES BOTTOM SIDE A1 CORNER IS DESIGNATED WITH A BALL MISSING FROM THE ARRAY CAPACITOR PADS MAY BE UNPOPULATED Millimeters DIM Min Max A 2 25 2 80 Al 0 50 0 70 A2 1 00 1 20 A3 0 60 0 60 0 90 D 21 00 BSC D1 6 75 E 21 00 BSC E1 7 87 e 1 27 BSC Figure 18 Mechanical Dimensions and Bottom Surface Nomenclature for the MPC745 255 PBGA Package MPC755 RISC Microprocessor Hardware Specifications Rev 8 Freescale Semiconductor 33 Package Description 7 3 Package Parameters for the MPC755 CBGA The package parameters are as provided in the following list The package type is 25 x 25 mm 360 lead ceramic ball grid array CBGA Package outline 25 x 25 mm Interconnects 360 19 x 19 ball array 1 Pitch 1 27 mm 50 mil Minimum module height 2 65 mm Maximum module height 3 20 mm Ball diameter 0 89 mm 35 mil 7 4 Mechanical Dimensions for the MPC755 CBGA Figure 19 provides the mechanical dimensions and bottom surface nomenclature for the MPC755 360 CBGA package ee A l D t 2x y ze 10 111213141516 171819 gt l EE wm a PEAS 2 WE Www Www WE www LELEEKLELELELEIUIUE KELEEKELEEELELEIIUR LELEEKELELELELEUUUE KLELEEKLELELELELELIIIUE H z LELEEKELELELELEUUUE gt N 0000 00000000088C08 KELLER LELLLLELELELELLELELEELELEILE LELLELELELELELELEEEELEIELE KELELELEEEEEEEEEEEEE K
21. Freescale Semiconductor Technical Data MPC755 RISC Microprocessor Hardware Specifications This document is primarily concerned with the MPC755 however unless otherwise noted all information here also applies to the MPC745 The MPC755 and MPC745 are reduced instruction set computing RISC microprocessors that implement the PowerPC instruction set architecture This document describes pertinent physical characteristics of the MPC755 For information on specific MPC755 part numbers covered by this or other specifications see Section 10 Ordering Information For functional characteristics of the processor refer to the MPC750 RISC Microprocessor Family User s Manual To locate any published errata or updates for this document refer to the website listed on the back cover of this document 1 Overview The MPC755 is targeted for low cost low power systems and supports the following power management features doze nap sleep and dynamic power management The MPC755 consists of a processor core and an internal L2 tag combined with a dedicated L2 cache interface and a 60x bus The MPC745 is identical to the MPC755 except it does not support the L2 cache interface Figure shows a block diagram of the MPC755 Freescale Semiconductor Inc 2006 All rights reserved a Oo oO VD D A Ch Un PWN ra Document Number MPC755EC Rev 8 02 2006 Contents EE 1 EE EE 3 s Gemera PAV ANCES A Cutt ee Batons aces e
22. G AC Timing Specifications Independent of SYSCLK At recommended operating conditions see Table 3 Parameter Symbol Min Max Unit Notes TCK frequency of operation Freck 0 16 MHz TCK cycle time ttcLk 62 5 ns TCK clock pulse width measured at 1 4 V tJHJL 31 ns TCK rise and fall times tur tur 0 2 ns TRST assert time ttrst 25 Gg ns 2 Input setup times Boundary scan data tovuH 4 ns 3 TMS TDI Wun 0 ES Input hold times Boundary scan data toxJH 15 ns 3 TMS TDI Wan 12 Valid times Boundary scan data Ly 4 ns 4 TDO Lou ES 4 Output hold times Boundary scan data tyLDH 25 ns 4 TDO LOH 12 TCK to output high impedance Boundary scan data ty_pz 3 19 ns 4 5 TDO Los 3 9 Notes 1 All outputs are measured from the midpoint voltage of the falling rising edge of TCLK to the midpoint of the signal in question The output timings are measured at the pins All output timings assume a purely resistive 50 Q load see Figure 11 Time of flight delays must be added for trace lengths vias and connectors in the system ak Co PY Guaranteed by design and characterization TRST is an asynchronous level sensitive signal which must be asserted for this minimum time to be recognized Non JTAG signal input timing with respect to TCK Non JTAG signal output timing with respect to TCK Figure 11 provides the AC test load for TDO and the boundary scan outputs of the MPC
23. INT B15 Low Input OVpp L1_TSTCLK D11 High Input 2 L2_TSTCLK D12 High Input 2 LSSD_MODE B10 Low Input 2 MCP C13 Low Input OVpp NC No Connect B7 B8 C3 C6 C8 D5 D6 H4 J16 A4 A5 A2 A3 B5 OVpp C7 E5 E7 E10 E12 G3 G5 G12 G14 K3 K5 K12 2 5 V 3 3 V K14 M5 M7 M10 M12 P7 P10 PLL_CFG 0 3 A8 B9 A9 D9 High Input OVpp QACK D3 Low Input OVpp QREQ J3 Low Output OVpp RSRV D1 Low Output OVpp SMI A16 Low Input OVpp SRESET B14 Low Input OVpp SYSCLK c9 Input OVpp TA H14 Low Input OVpp TBEN C2 High Input OVpp TBST A14 Low UO OVpp TCK C11 High Input OVpp TDI A11 High Input OVpp 5 TDO A12 High Output OVpp TEA H13 Low Input OVpp TLBISYNC C4 Low Input OVpp TMS B11 High Input OVpp 5 TRST C10 Low Input OVpp 5 TS J13 Low UO OVpp TSIZ 0 2 A13 D10 B12 High Output OVpp TT 0 4 B13 A15 B16 C14 C15 High O OVpp WT D2 Low Output OVpp Vrp F6 F8 F9 F11 G7 G10 H6 H8 H9 H11 J6 J8 J9 E 2 0 V J11 K7 K10 L6 L8 L9 L11 MPC755 RISC Microprocessor Hardware Specifications Rev 8 28 Freescale Semiconductor Pinout Listings Table 14 Pinout Listing for the MPC745 255 PBGA Package continued Signal Name Pin Number Active HO UE Voltage Notes VOLTDET F3 High Output 6 Notes 1 OVpp supplies power to the processor bus JTAG and all control signals and Vpp supplies power to the processor core and the PLL after filtering to b
24. Input OVpp TBEN A2 High Input OVpp TBST A11 Low UO OVpp TCK B10 High Input OVpp TDI B7 High Input OVpp 6 TDO D9 High Output OVpp TEA J1 Low Input OVpp TLBISYNC A3 Low Input OVpp TMS C8 High Input OVpp 6 TRST A10 Low Input OVpp 6 TS K7 Low UO OVpp TSIZ 0 2 AQ B9 C9 High Output OVpp TT 0 4 C10 D11 B12 C12 F11 High UO OVpp WT C3 Low Output OVpp Vrp G8 G10 G12 J8 J10 J12 L8 L10 L12 N8 N10 N12 em 2 0 V MPC755 RISC Microprocessor Hardware Specifications Rev 8 Freescale Semiconductor 31 Package Description Table 15 Pinout Listing for the MPC755 360 BGA Package continued Signal Name Pin Number Active HO UE Voltage Notes VOLTDET K13 High Output L2OVpp 8 Notes 1 OVpp supplies power to the processor bus JTAG and all control signals except the L2 cache controls L2CE L2WE and L2ZZ L2OVpp supplies power to the L2 cache interface L2EADDR 0 16 L2DATA 0 63 L2DP 0 7 and LASYNC_OUT and the L2 control signals and Vpp supplies power to the processor core and the PLL and DLL after filtering to become AVpp and L2AVpp respectively These columns serve as a reference for the nominal voltage supported on a given signal as selected by the BVSEL L2VSEL pin configurations of Table 2 and the voltage supplied For actual recommended value of Vin or supply voltages see Table 3 2 These are test signals for factory use only and must be pulled up to OVpp for normal machine operat
25. LK affects L2CLK_OUT and the L2 address data control signals equally and therefore is already comprehended in the AC timing and does not have to be considered in the L2 timing analysis 7 Guaranteed by design MPC755 RISC Microprocessor Hardware Specifications Rev 8 18 Freescale Semiconductor Electrical and Thermal Characteristics The L2CLK_OUT timing diagram is shown in Figure 7 L2 Single Ended Clock Mode Leaks Le CHL tLocr gt gt lt tlocr L2CLK_OUTA L2CLK_OUTB VM VM VM VM tlocskw gt lt L2SYNC_OUT VM VM VM VM L2 Differential Clock Mode L2CLK_OUTB L2CLK_OUTA L2SYNC_OUT VM Midpoint Voltage L2OVpp 2 Figure 7 L2ACLK_OUT Output Timing Diagram 4 2 4 L2 Bus AC Specifications Table 12 provides the L2 bus interface AC timing specifications for the MPC755 as defined in Figure 8 and Figure 9 for the loading conditions described in Figure 10 Table 12 L2 Bus Interface AC Timing Specifications At recommended operating conditions see Table 3 All Speed Grades Parameter Symbol Unit Notes Min Max L2SYNC_IN rise and fall time haen L2CF 1 0 ns 1 Setup times Data and parity tDVL2CH 1 2 ns 2 Input hold times Data and parity tpxL2cH 0 ns 2 Valid times tL CHOV ns 3 4 All outputs when L2CR 14 15 00 3 1 All outputs when L2CR 14 15 01 3 2 All outputs when L2CR 14 15 10 3 3 All outputs when L2CR 14 15
26. LK period for read and write access to the L2 SRAMs The maximum L2CLK frequency for any application of the MPC755 will be a function of the AC timings of the MPC755 the AC timings for the SRAM bus loading and printed circuit board trace length The current AC timing of the MPC755 supports up to 200 MHz with typical similarly rated SRAM parts provided careful design practices are observed Clock trace lengths must be matched and all trace lengths should be as short as possible Higher frequencies can be achieved by using better performing MPC755 RISC Microprocessor Hardware Specifications Rev 8 16 Freescale Semiconductor Electrical and Thermal Characteristics SRAM Note that revisions of the MPC755 prior to Rev 2 8 Rev E were limited in performance and were typically limited to 175 MHz with similarly rated SRAM For more information see Section 10 2 Part Numbers Not Fully Addressed by This Document Freescale is similarly limited by system constraints and cannot perform tests of the L2 interface on a socketed part on a functional tester at the maximum frequencies of Table 11 Therefore functional operation and AC timing information are tested at core to L2 divisors of 2 or greater Functionality of core to L2 divisors of 1 or 1 5 is verified at less than maximum rated frequencies L2 input and output signals are latched or enabled respectively by the internal L2CLK which is SYSCLK multiplied up to the core frequency and
27. MCP SMI tixkH 0 2 bes ns 6 Valid times All outputs tkHov 4 1 ns Output hold times All outputs tkHox 1 0 ns SYSCLK to output enable kHOE 0 5 ns 2 SYSCLK to output high impedance all except ABB ARTRY DBB tkHoz E 6 0 ns 2 SYSCLK to ABB DBB high impedance after precharge txHABPZ 1 0 tsysclk 2 3 4 Maximum delay to ARTRY precharge tkHARP 1 Losch 2 3 5 SYSCLK to ARTRY high impedance after precharge tkHARPZ 2 tsysak 2 3 5 Notes 1 2 3 Revisions prior to Rev 2 8 Rev E were limited in performance and did not conform to this specification For more information refer to Section 10 2 Part Numbers Not Fully Addressed by This Document Guaranteed by design and characterization tsyscik iS the period of the external clock SYSCLK in ns The numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration in ns of the parameter in question Per the 60x bus protocol TS ABB and DBB are driven only by the currently active bus master They are asserted low then precharged high before returning to high Z as shown in Figure 6 The nominal precharge width for TS ABB or DBB is 0 5 x tsyscik that is less than the minimum Lech period to ensure that another master asserting TS ABB or DBB on the following clock will not contend with the precharge Output valid and output hold timing is tested for the signal asserted Output valid time
28. SC Microprocessor Hardware Specifications Rev 8 Freescale Semiconductor 55 How to Reach Us Home Page www freescale com email support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Document Number MPC755EC Rev 8 02 2006 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no
29. Table 3 Nominal Characteristic Bus Symbol Min Max Unit Notes Voltage Capacitance Vin 0 V f 1 MHz Cin 5 0 pF 3 4 Notes 1 Nominal voltages see Table 3 for recommended operating conditions 2 For processor bus signals the reference is OVpp while L2OVpp is the reference for the L2 bus signals 3 Excludes test signals LSSD_MODE L1_TSTCLK L2_TSTCLK and IEEE 1149 1 boundary scan JTAG signals 4 Capacitance is periodically sampled rather than 100 tested 5 The leakage is measured for nominal OVpp and Vpp or both OVpp and Vpp must vary in the same direction for example both OVpp and Vpp vary by either 5 or 5 Table 7 provides the power consumption for the MPC755 Table 7 Power Consumption for MPC755 Processor CPU Frequency Unit Notes 300 MHz 350 MHz 400 MHz Full Power Mode Typical 3 1 3 6 5 4 Ww 1 3 4 Maximum 4 5 6 0 8 0 W 1 2 Doze Mode Maximum 1 8 2 0 2 3 W 1 2 4 Nap Mode Maximum 1 0 1 0 1 0 W 1 2 4 Sleep Mode Maximum 550 550 550 mW 1 2 4 Sleep Mode PLL and DLL Disabled Maximum 510 510 510 mW 1 2 Notes 1 These values apply for all valid processor bus and L2 bus ratios The values do not include I O supply power OVpp and L2OVpp or PLL DLL supply power AVpp and L2AVpp OVpp and L2OVpp power is system dependent but is typically lt 10 of Vpp power Worst case power consumption for AVpp 15 m
30. Thermalloy 603 224 9988 80 Commercial St Concord NH 03301 Internet www aavidthermalloy com Alpha Novatech 408 749 7601 473 Sapena Ct 15 Santa Clara CA 95054 Internet www alphanovatech com International Electronic Research Corporation IERC 818 842 7277 413 North Moss St Burbank CA 91502 Internet www ctscorp com Tyco Electronics 800 522 6752 Chip Coolers P O Box 3668 Harrisburg PA 17105 3668 Internet www chipcoolers com Wakefield Engineering 603 635 5102 33 Bridge St Pelham NH 03076 Internet www wakefield com Ultimately the final selection of an appropriate heat sink depends on many factors such as thermal performance at a given air velocity spatial volume mass attachment method assembly and cost 8 8 1 Internal Package Conduction Resistance For the exposed die packaging technology shown in Table 4 the intrinsic conduction thermal resistance paths are as follows e The die junction to case or top of die for exposed silicon thermal resistance e The die junction to ball thermal resistance Figure 26 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed circuit board Heat generated on the active side of the chip is conducted through the silicon then through the heat sink attach material or thermal interface material and finally to the heat sink where it is removed by forced air convection Since the silicon thermal resistance is quite sm
31. UO OVpp E15 H1 E16 H2 F13 J1 F14 J2 F15 H3 F16 F4 G13 K1 G15 K2 H16 M1 J15 P1 AACK L2 Low Input OVpp ABB K4 Low 1 0 OVpp AP 0 3 C1 B4 B3 B2 High UO OVpp ARTRY J4 Low 1 0 OVpp AVpp A10 2 0 V BG L1 Low Input OVpp BR B6 Low Output OVpp BVSEL B1 High Input OVpp 3 4 5 Cl E1 Low Output OVpp CKSTP_IN D8 Low Input OVpp CKSTP_OUT A6 Low Output OVpp CLK_OUT D7 Output OVpp DBB J14 Low 1 0 OVpp DBG N1 Low Input OVpp DBDIS H15 Low Input OVpp DBWO G4 Low Input OVpp DH 0 31 P14 T16 R15 T15 R13 R12 P11 N11 R11 T12 High UO OVpp T11 R10 P9 N9 T10 R9 T9 P8 N8 R8 T8 N7 R7 T7 P6 N6 R6 T6 R5 N5 T5 T4 DL 0 31 K13 K15 K16 L16 L15 L13 L14 M16 M15 M13 High UO OVpp N16 N15 N13 N14 P16 P15 R16 R14 T14 N10 P13 N12 T13 P3 N3 N4 R3 T1 T2 P4 T3 R4 DP 0 7 M2 L3 N2 L4 R1 P2 M4 R2 High UO OVpp DRTRY G16 Low Input OVpp GBL F1 Low VO OVpp GND C5 C12 E3 E6 E8 E9 E11 E14 F5 F7 F10 F12 GND G6 G8 G9 G11 H5 H7 H10 H12 J5 J7 J10 J12 K6 K8 K9 K11 L5 L7 L10 L12 M3 M6 M8 M9 M11 M14 P5 P12 HRESET A7 Low Input OVpp MPC755 RISC Microprocessor Hardware Specifications Rev 8 Freescale Semiconductor 27 Pinout Listings Table 14 Pinout Listing for the MPC745 255 PBGA Package continued Signal Name Pin Number Active HO I F Voltage Notes
32. W and L2AVpp 15 mW 2 Maximum power is measured at nominal Vpp see Table 3 while running an entirely cache resident contrived sequence of instructions which keep the execution units maximally busy 3 Typical power is an average value measured at the nominal recommended Vpp see Table 3 and 65 C in a system while running a typical code sequence 4 Not 100 tested Characterized and periodically sampled MPC755 RISC Microprocessor Hardware Specifications Rev 8 Freescale Semiconductor 11 Electrical and Thermal Characteristics 4 2 AC Electrical Characteristics This section provides the AC electrical characteristics for the MPC755 After fabrication functional parts are sorted by maximum processor core frequency as shown in Section 4 2 1 Clock AC Specifications and tested for conformance to the AC specifications for that frequency The processor core frequency is determined by the bus SYSCLK frequency and the settings of the PLL_CFG 0 3 signals Parts are sold by maximum processor core frequency see Section 10 Ordering Information 4 2 1 Clock AC Specifications Table 8 provides the clock AC timing specifications as defined in Figure 3 Table 8 Clock AC Timing Specifications At recommended operating conditions see Table 3 Maximum Processor Core Frequency Characteristic Symbol 300 MHz 350 MHz 400 MHz Unit Notes Min Max Min Max M
33. all for a first order analysis the temperature drop in the silicon may be neglected Thus the heat sink attach material and the heat sink conduction convective thermal resistances are the dominant terms MPC755 RISC Microprocessor Hardware Specifications Rev 8 Freescale Semiconductor 45 System Design Information External Resistance Radiation Convection Heat Sink gt lt lt Thermal Interface Material Resistance lt Die Package Die Junction Package Leads Printed Circuit Board gt External Resistance Radiation Convection Note the internal versus external package resistance Figure 26 C4 Package with Heat Sink Mounted to a Printed Circuit Board 8 8 2 Adhesives and Thermal Interface Materials A thermal interface material is recommended at the package lid to heat sink interface to minimize the thermal contact resistance For those applications where the heat sink is attached by spring clip mechanism Figure 27 shows the thermal performance of three thin sheet thermal interface materials silicone graphite oil floroether oil a bare joint and a joint with thermal grease as a function of contact pressure As shown the performance of these thermal interface materials improves with increasing contact pressure The use of thermal grease significantly reduces the interface thermal resistance That is the bare joint results in a thermal resistance approximately seven times greate
34. are currently provided in both a CBGA and a PBGA package Because of the better long term device to board interconnect reliability of the PBGA package Freescale recommends use of a PBGA package except where circumstances dictate use of a CBGA package MPC755 RISC Microprocessor Hardware Specifications Rev 8 32 Freescale Semiconductor 7 1 Package Description Package Parameters for the MPC745 PBGA The package parameters are as provided in the following list The package type is 21 x 21 mm 255 lead plastic ball grid array PBGA Package outline Interconnects Pitch Minimum module height Maximum module height Ball diameter typical 21x 21mm 255 16 x 16 ball array 1 1 27 mm 50 mil 2 25 mm 2 80 mm 0 75 mm 29 5 mil 7 2 2X Mechanical Dimensions for the MPC745 PBGA Figure 18 provides the mechanical dimensions and bottom surface nomenclature for the MPC745 255 PBGA package Al a A D lt D1 gt gt 0 2 1234567 8 910111213141516 POONOUOMNDICATESEZVIVGA gt l 0 2 i A mm SE SE WEE E WEE E WE WEE E 4 A3 H T IW Ob 0 3 Cc A lt Al 0 15 C eg gt A L NOTES 1 2 3 DIMENSIONING AND TOLERANCING PER ASME Y14 5M 1994 DIMENSIONS IN MILLIMETERS TOP SIDE A1 CORNER INDEX IS A METALIZED FEATURE WITH VARIOUS SHAP
35. being driven by the tool Note that the pull up and pull down resistors on the QACK signal are mutually exclusive and it is never necessary to populate both in a system To preserve correct power down operation QACK should be merged via logic so that it also can be driven by the PCI bridge 8 8 Thermal Management Information This section provides thermal management information for air cooled applications Proper thermal control design is primarily dependent on the system level design the heat sink airflow and thermal interface material To reduce the die junction temperature heat sinks may be attached to the package by several methods adhesive spring clip to holes in the printed circuit board or package and mounting clip and screw assembly see Figure 25 This spring force should not exceed 5 5 pounds 2 5 kg of force Figure 25 describes the package exploded cross sectional view with several heat sink options Heat Sink CBGA Package Heat Sink Clip Adhesive or Thermal Interface Material Printed Circuit Board Option Figure 25 Package Exploded Cross Sectional View with Several Heat Sink Options MPC755 RISC Microprocessor Hardware Specifications Rev 8 44 Freescale Semiconductor System Design Information The board designer can choose between several types of heat sinks to place on the MPC755 There are several commercially available heat sinks for the MPC755 provided by the following vendors Aavid
36. cale Semiconductor 2 Features Features This section summarizes features of the MPC755 implementation of the PowerPC architecture Major features of the MPC755 are as follows Branch processing unit Four instructions fetched per clock One branch processed per cycle plus resolving two speculations Upto one speculative stream in execution one additional speculative stream in fetch 512 entry branch history table BHT for dynamic prediction 64 entry four way set associative branch target instruction cache BTIC for eliminating branch delay slots Dispatch unit Full hardware detection of dependencies resolved in the execution units Dispatch two instructions to six independent units system branch load store fixed point unit 1 fixed point unit 2 floating point Serialization control predispatch postdispatch execution serialization Decode Register file access Forwarding control Partial instruction decode Completion Six entry completion buffer Instruction tracking and peak completion of two instructions per cycle Completion of instructions in program order while supporting out of order instruction execution completion serialization and all instruction flow changes Fixed point units FXUs that share 32 GPRs for integer operands Fixed Point Unit 1 FXU1 multiply divide shift rotate arithmetic logical Fixed Point Unit 2 FXU2 shift ro
37. cale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc The described product contains a PowerPC processor core The PowerPC name is a trademark of IBM Corp and used under license All other product or service names are the property of their respective owners Freescale Semiconductor Inc 2006 e E oF 2 freescale semiconductor
38. de is selected the input receivers of the unused data and parity bits will be disabled and their outputs will drive logic zeros when they would otherwise normally be driven For this mode these pins do not require pull up resistors and should be left unconnected by the system to minimize possible output switching If address or data parity is not used by the system and the respective parity checking is disabled through HIDO the input receivers for those pins are disabled and those pins do not require pull up resistors and MPC755 RISC Microprocessor Hardware Specifications Rev 8 Freescale Semiconductor 41 System Design Information should be left unconnected by the system If all parity generation is disabled through HIDO then all parity checking should also be disabled through HIDO and all parity pins may be left unconnected by the system The L2 interface does not require pull up resistors 8 7 JTAG Configuration Signals Boundary scan testing is enabled through the JTAG interface signals The TRST signal is optional in the IEEE 1149 1 specification but is provided on all processors that implement the PowerPC architecture While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals more reliable power on reset performance will be obtained if the TRST signal is asserted during power on reset Because the JTAG interface is also used for accessing the common on chip processor COP functio
39. divided down to the L2CLK frequency In other words the AC timings of Table 12 and Table 13 are entirely independent of L2SYNC_IN Ina closed loop system where L2SYNC_IN is driven through the board trace by LAS YNC_OUT L2SYNC_IN only controls the output phase of L2CLK_OUTA and L2CLK_OUTB which are used to latch or enable data at the SRAMs However since in a closed loop system L2S YNC_IN is held in phase alignment with the internal L2CLK the signals of Table 12 and Table 13 are referenced to this signal rather than the not externally visible internal L2CLK During manufacturing test these times are actually measured relative to SYSCLK The L2SYNC_OUT signal is intended to be routed halfway out to the SRAMs and then returned to the L2SYNC_IN input of the MPC755 to synchronize L2ZCLK_OUT at the SRAM with the processor s internal clock L2CLK_OUT at the SRAM can be offset forward or backward in time by shortening or lengthening the routing of LAS YNC_OUT to L2SYNC_IN See Freescale Application Note AN1794 D Backside L2 Timing Analysis for PCB Design Engineers The L2CLK_OUTA and L2CLK_OUTB signals should not have more than two loads MPC755 RISC Microprocessor Hardware Specifications Rev 8 Freescale Semiconductor 17 Electrical and Thermal Characteristics Table 11 L2CLK Output AC Timing Specification At recommended operating conditions see Table 3 All Speed Grades Parameter Symbol Unit Notes Min Max
40. dware Specifications Rev 8 Freescale Semiconductor Electrical and Thermal Characteristics 4 Packages MPC745 Surface mount 255 plastic ball grid array PBGA MPC755 Surface mount 360 ceramic ball grid array CBGA Surface mount 360 plastic ball grid array PBGA Core power supply 2 0 V 100 mV DC nominal some parts support core voltages down to 1 8 V see Table 3 for recommended operating conditions I O power supply 2 5 V 100 mV DC or 3 3 V 165 mV DC input thresholds are configuration pin selectable Electrical and Thermal Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC755 4 1 DC Electrical Characteristics Table 1 through Table 7 describe the MPC755 DC electrical characteristics Table 1 provides the absolute maximum ratings Table 1 Absolute Maximum Ratings Characteristic Symbol Maximum Value Unit Notes Core supply voltage Vpp 0 3 to 2 5 V 4 PLL supply voltage AVpp 0 3 to 2 5 V 4 L2 DLL supply voltage L2AVpp 0 3 to 2 5 V 4 Processor bus supply voltage OVpp 0 3 to 3 6 V 3 L2 bus supply voltage L2OVpp 0 3 to 3 6 V 3 Input voltage Processor bus Vin 0 3 to OVpp 0 3 V V 2 5 L2 bus Vin 0 3 to L2OVpp 0 3 V V 2 5 JTAG signals Vin 0 3 to 3 6 V Storage temperature range Tstg 55 to 150 C Notes k on Functional and tested operating conditions a
41. e examples may represent core or L2 frequencies which are not useful not supported or not tested for by the MPC755 see Section 4 2 3 L2 Clock AC Specifications for valid L2CLK frequencies The L2CR L2SL bit should be set for L2CLK frequencies less than 110 MHz 8 2 PLL Power Supply Filtering The AVpp and L2AVpp power signals are provided on the MPC755 to provide power to the clock generation PLL and L2 cache DLL respectively To ensure stability of the internal clock the power supplied to the AVpp input signal should be filtered of any noise in the 500 kHz to 10 MHz resonant frequency range of the PLL A circuit similar to the one shown in Figure 21 using surface mount capacitors with minimum Effective Series Inductance ESL is recommended Consistent with the recommendations of Dr Howard Johnson in High Speed Digital Design A Handbook of Black Magic Prentice Hall 1993 multiple small capacitors of equal value are recommended over a single large value capacitor The circuit should be placed as close as possible to the AVpp pin to minimize noise coupled from nearby circuits An identical but separate circuit should be placed as close as possible to the L2AV pp pin It is often possible to route directly from the capacitors to the AVpp pin which is on the periphery of the 360 BGA footprint without the inductance of vias The L2ZAVpp pin may be more difficult to route but is proportionately less critical Figure 21 shows the PLL p
42. ecome AVpp These columns serve as a reference for the nominal voltage supported on a given signal as selected by the BVSEL pin configuration of Table 2 and the voltage supplied For actual recommended value of Vin or supply voltages see Table 3 These are test signals for factory use only and must be pulled up to OVpp for normal machine operation This pin must be pulled up to OVpp for proper operation of the processor interface To allow for future I O voltage changes provide the option to connect BVSEL independently to either OVpp or GND Uses 1 of 15 existing no connects in the MPC740 255 BGA package Internal pull up on die Internally tied to GND in the MPC745 255 BGA package to indicate to the power supply that a low voltage processor is present This signal is not a power supply input Caution This differs from the MPC755 360 BGA package Table 15 provides the pinout listing for the MPC755 360 PBGA and CBGA packages Table 15 Pinout Listing for the MPC755 360 BGA Package Signal Name Pin Number Active HO UE Voltage Notes A 0 31 A13 D2 H11 C1 B13 F2 C13 E5 D13 G7 F12 G3 High UO OVpp G6 H2 E2 L3 G5 L4 G4 J4 H7 E1 G2 F3 J7 M3 H3 J2 J6 K3 K2 L2 AACK N3 Low Input OVpp ABB L7 Low UO OVpp AP 0 3 C4 C5 C6 C7 High uo OVpp ARTRY L6 Low UO OVpp AVpp A8 2 0 V BG H1 Low Input OVpp BR E7 Low Output OVpp BVSEL WI High Input OVpp 3 5 6 C
43. eewaobs a Electrical and Thermal Characteristics 6 e PIN Agen pices nooo NEE EE A 25 e Jentgen 8 EE Gases aaa 27 Packets Descriptio tre IER EE ier 32 System Design Information 36 Document Revision History 0 50 L Ordering Information 3 viasnardaccacceas 53 d Treescale semiconductor Overview sng 2ed z1 a 79 1 Sng SS IPPY CT Wa Zb 3 SVLOdIN y U ION sng eq Wa v9 ce 3 sng sseJppy IZ aupe q sus anend peoT 2e a PE a 1vga anand inolseo LI reuiBuo wun oa SUS Aju 9 gOOpUaul sng CT aneny yo e4 UOnOpnISU 1g SUE JoTg JEplOoy s6el zI 4 04UOD Z7 n ny Ino sed gzl c HOSdS anand 2101S ex uonejnojeo V3 wun D qulog Buryeo 4 4g ug p9 HUN a10 S peo7 9 9 Sang eweuey slaying eweuey Aug uonels UO HEIS uoles olla Ydd Toners ji sha Ado UOUEAISSeL uoneAlesey uoneAJesey UuoHeIS UOHeAJESeY suononasul zZ ug v9 yun Yoyedsiq SUOI ONAISU Z ou JOHUON SOUELUUOUS e juswebeuey Jomo LIEUUSUL e eyoed akaze SEL SSC 1Hg a0eLOIU dOD 9YLr Ea S EIERE SUS HI Anug y9 Ton uolons su 1 u w 199q 19 UNO N eseg Sul YLO WIES 6 nun Jee uISS 201d youelg g yun HOLOn DsSu Ii EE s n e y euo ppy suononasu p Wa 8eb yun Spa sng x09 yun uop ajdwog iagram MPC755 Block D 1 igure F MPC755 RISC Microprocessor Hardware Specifications Rev 8 Frees
44. eight way set associative instruction cache iL1 32K 32 byte line eight way set associative data cache dL1 Cache locking for both instruction and data caches selectable by group of ways Single cycle cache access Pseudo least recently used PLRU replacement Copy back or write through data cache on a page per page basis MEI data cache coherency maintained in hardware Nonblocking instruction and data cache one outstanding miss under hits No snooping of instruction cache e Level 2 L2 cache interface not implemented on MPC745 Internal L2 cache controller and tags external data SRAMs 256K 512K and 1 Mbyte two way set associative L2 cache support Copy back or write through data cache on a page basis or for all L2 Instruction only mode and data only mode 64 byte 256K 512K or 128 byte 1M sectored line size Supports flow through register buffer synchronous BurstRAMs pipelined register register synchronous BurstRAMs 3 1 1 1 or strobeless 4 1 1 1 and pipelined register register late write synchronous BurstRAMs L2 configurable to cache private memory or split cache private memory Core to L2 frequency divisors of 1 1 5 2 2 5 and 3 supported 64 bit data bus MPC755 RISC Microprocessor Hardware Specifications Rev 8 Freescale Semiconductor 3 General Parameters Selectable interface voltages of 2 5 and 3 3 V Parity checking on both L2 address and data Memory management unit 128
45. er in question Mode select signals are BVSEL L2VSEL PLL_CFG 0 3 and TLBISYNC Guaranteed by design and characterization Bus mode select pins must remain stable during operation Changing the logic states of BVSEL or L2VSEL during operation will cause the bus mode voltage selection to change Changing the logic states of the PLL_CFG pins during operation will cause the PLL division ratio selection to change Both of these conditions are considered outside the specification and are not supported Once HRESET is negated the states of the bus mode selection pins must remain stable MPC755 RISC Microprocessor Hardware Specifications Rev 8 Freescale Semiconductor 13 Electrical and Thermal Characteristics Figure 4 provides the mode select input timing diagram for the MPC755 HRESET Mode Signals VM Midpoint Voltage OVpp 2 Figure 4 Mode Input Timing Diagram Figure 5 provides the AC test load for the MPC755 Figure 5 AC Test Load MPC755 RISC Microprocessor Hardware Specifications Rev 8 14 Freescale Semiconductor Electrical and Thermal Characteristics Table 10 Processor Bus AC Timing Specifications 1 At recommended operating conditions see Table 3 All Speed Grades Parameter Symbol Unit Notes Min Max Setup times All inputs tivkH 2 5 ns Input hold times TLBISYNC MCP SMI tIXKH 0 6 ns 6 Input hold times All inputs except TLBISYNC
46. express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Frees
47. f the signal in question All output timings assume a purely resistive 50 Q load see Figure 5 Input and output timings are measured at the pin time of flight delays must be added for trace lengths vias and connectors in the system The symbology used for timing specifications herein follows the pattern of t signaly state reference state for inputs and t reference state signal state for outputs For example but symbolizes the time input signals I reach the valid state V relative to the SYSCLK reference K going to the high H state or input setup time And tkpoy symbolizes the time from SYSCLK K going high H until outputs O are valid V or output valid time Input hold time can be read as the time that the input signal I went invalid X with respect to the rising clock edge KH note the position of the reference and its state for inputs and output hold time can be read as the time from the rising edge KH until the output went invalid OX The setup and hold time is with respect to the rising edge of HRESET see Figure 4 This specification is for configuration mode select only Also note that the HRESET must be held asserted for a minimum of 255 bus clocks after the PLL relock time during the power on reset sequence tsyscik is the period of the external clock SYSCLK in ns The numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration in ns of the paramet
48. harging of the smaller chip capacitors These bulk capacitors should have a low ESR equivalent series resistance rating to ensure the quick response time necessary They should also be connected to the power and ground planes through two vias to minimize inductance Suggested bulk capacitors 100 330 uF AVX TPS tantalum or Sanyo OSCON 8 4 Connection Recommendations To ensure reliable operation it is highly recommended to connect unused inputs to an appropriate signal level through a resistor Unused active low inputs should be tied to OVpp Unused active high inputs should be connected to GND All NC no connect signals must remain unconnected Power and ground connections must be made to all external Vpp OVpp L2OVpp and GND pins of the MPC755 Note that power must be supplied to L2OVpp even if the L2 interface of the MPC755 will not be used it is recommended to connect L2OVpp to OVpp and L2VSEL to BVSEL if the L2 interface is unused This requirement does not apply to the MPC745 since it has neither an L2 interface nor LAOVpp pins 8 5 Output Buffer DC Impedance The MPC755 60x and L2 I O drivers are characterized over process voltage and temperature To measure Zo an external resistor is connected from the chip pad to L2 OVpp or GND Then the value of each resistor is varied until the pad voltage is L2 OVpp 2 see Figure 22 The output impedance is the average of two components the resistances of the pull up and pull down
49. he COP port and target board should be able to independently assert HRESET and TRST to the processor in order to fully control the processor as shown above Figure 24 JTAG Interface Connection MPC755 RISC Microprocessor Hardware Specifications Rev 8 Freescale Semiconductor 43 System Design Information There is no standardized way to number the COP header shown in Figure 24 consequently many different pin numbers have been observed from emulator vendors Some are numbered top to bottom then left to right while others use left to right then top to bottom while still others number the pins counter clockwise from pin 1 as with an IC Regardless of the numbering the signal placement recommended in Figure 25 is common to all known emulators The QACK signal shown in Figure 24 is usually connected to the PCI bridge chip in a system and is an input to the MPC755 informing it that it can go into the quiescent state Under normal operation this occurs during a low power mode selection In order for COP to work the MPC755 must see this signal asserted pulled down While shown on the COP header not all emulator products drive this signal If the product does not a pull down resistor can be populated to assert this signal Additionally some emulator products implement open drain type outputs and can only drive QACK asserted for these tools a pull up resistor can be implemented to ensure this signal is deasserted when it is not
50. hermal Characteristics Table 3 provides the recommended operating conditions for the MPC755 Table 3 Recommended Operating Conditions Recommended Value Characteristic Symbol 300 MHz 350 MHz 400 MHz Unit Notes Min Max Min Max Core supply voltage Vpp 1 80 2 10 1 90 2 10 V 3 PLL supply voltage AVpp 1 80 2 10 1 90 2 10 V 3 L2 DLL supply voltage L2AVpp 1 80 2 10 1 90 2 10 V 3 Processor bus supply BVSEL 1 OVpp 2 375 2 625 2 375 2 625 V 2 4 eee 3 135 3 465 3 135 3 465 5 L2 bus supply voltage L2VSEL 1 L2OVpp 2 375 2 625 2 375 2 625 V 2 4 3 135 3 465 3 135 3 465 5 Input voltage Processor bus Vin GND OVpp GND OVpp L2 bus Vin GND L2OVpp GND L2OVpp JTAG signals Vin GND OVpp GND OVpp Die junction temperature Tj 0 105 0 105 C Notes 1 These are the recommended and tested operating conditions Proper device operation outside of these conditions is not guaranteed 2 Revisions prior to Rev 2 8 Rev E offered different I O voltage support For more information refer to Section 10 2 Part Numbers Not Fully Addressed by This Document 3 2 0 V nominal 4 2 5 V nominal 5 3 3 V nominal Table 4 provides the package thermal characteristics for the MPC755 and MPC745 The MPC755 was initially sampled in a CBGA package but production units are currently provided in both a CBGA and a PBGA package Because of the better long term device to board interconnec
51. in Max Processor frequency foore 200 300 200 350 200 400 MHz 1 VCO frequency fyco 400 600 400 700 400 800 MHz 1 SYSCLK frequency fsyscLk 25 100 25 100 25 100 MHz 1 SYSCLK cycle time tsYSCLK 10 40 10 40 10 40 ns SYSCLK rise and fall time Dep tke EC 2 0 2 0 2 0 ns 2 tke ber 1 4 1 4 1 4 ns 2 SYSCLK duty cycle measured at tkHKL 40 60 40 60 40 60 3 OVpp 2 tsyscLk SYSCLK jitter 150 150 150 ps 3 4 Internal PLL relock time 100 100 100 us 3 5 Notes 1 Caution The SYSCLK frequency and PLL_CFG 0 3 settings must be chosen such that the resulting SYSCLK bus frequency CPU core frequency and PLL VCO frequency do not exceed their respective maximum or minimum operating frequencies Refer to the PLL_CFG 0 3 signal description in Section 8 1 PLL Configuration for valid PLL_CFG 0 3 settings 2 Rise and fall times measurements are now specified in terms of slew rates rather than time to account for selectable I O bus interface levels The minimum slew rate of 1 V ns is equivalent to a 2 ns maximum rise fall time measured at 0 4 and 2 4 V OVpp 3 3 V or a rise fall time of 1 ns measured at 0 4 and 1 8 V OVpp 2 5 V 3 Timing is guaranteed by design and characterization This represents total input jitter short term and long term combined and is guaranteed by design 5 Relock timing is guaranteed by design and characterization PLL relock time is the maximum amount of time required fo
52. information about the use and calibration of the TAU see Freescale Application Note AN1800 D Programming the Thermal Assist Unit in the MPC750 Microprocessor 2 The comparator settling time value must be converted into the number of CPU clocks that need to be written into the THRM3 SPR 3 Guaranteed by design and characterization Table 6 provides the DC electrical characteristics for the MPC755 Table 6 DC Electrical Specifications At recommended operating conditions see Table 3 Nominal Characteristic Bus Symbol Min Max Unit Notes Voltage Input high voltage all inputs except SYSCLK 2 5 Vin 1 6 L2 OVpp 0 3 V 2 3 3 3 Vu 2 0 L2 OVpp 0 3 vV 2 3 Input low voltage all inputs except SYSCLk 2 5 Vu 0 3 0 6 V 2 3 3 Vu 0 3 0 8 V SYSCLK input high voltage 2 5 RV 1 8 OVpp 0 3 V 3 3 KVin 2 4 OVpp 0 3 V SYSCLK input low voltage 2 5 KVIL 0 3 0 4 V 3 3 KVIL 0 3 0 4 V Input leakage current lin 10 pA 2 3 Vin L2OVpp OVpp High Z off state leakage current Its 10 pA 2 3 5 Vin L2OVpp OVpp Output high voltage lop 6 mA 2 5 VoH 1 7 V 3 3 Vou 2 4 V Output low voltage lop 6 mA 2 5 VoL 0 45 V 3 3 VoL 0 4 V MPC755 RISC Microprocessor Hardware Specifications Rev 8 10 Freescale Semiconductor Electrical and Thermal Characteristics Table 6 DC Electrical Specifications continued At recommended operating conditions see
53. ion This pin must be pulled up to OVpp for proper operation of the processor interface To allow for future I O voltage changes provide the option to connect BVSEL independently to either OVpp or GND These pins are reserved for potential future use as additional L2 address pins Uses one of nine existing no connects in the MPC750 360 BGA package Internal pull up on die This pin must be pulled up to L2OVpp for proper operation of the processor interface To allow for future I O voltage changes provide the option to connect L2VSEL independently to either L2OVpp or GND 8 Internally tied to L2OVpp in the MPC755 360 BGA package to indicate the power present at the L2 cache interface This signal is not a power supply input Caution This differs from the MPC745 255 BGA package wo NOAA 7 Package Description The following sections provide the package parameters and mechanical dimensions for the MPC745 255 PBGA package as well as the MPC755 360 CBGA and PBGA packages While both the MPC755 plastic and ceramic packages are described here both packages are not guaranteed to be available at the same time All new designs should allow for either ceramic or plastic BGA packages for this device For more information on designing a common footprint for both plastic and ceramic package types see the Freescale Flip Chip Plastic Ball Grid Array Presentation The MPC755 was initially sampled in a CBGA package but production units
54. is tested for precharge The high Z behavior is guaranteed by design Per the 60x bus protocol ARTRY can be driven by multiple bus masters through the clock period immediately following AACK Bus contention is not an issue since any master asserting ARTRY will be driving it low Any master asserting it low in the first clock following AACK will then go to high Z for one clock before precharging it high during the second cycle after the assertion of AACK The nominal precharge width for ARTRY is 1 0 tyy c that is it should be high Z as shown in Figure 6 before the first opportunity for another master to assert ARTRY Output valid and output hold timing is tested for the signal asserted Output valid time is tested for precharge The high Z and precharge behavior is guaranteed by design MCP and SRESET must be held asserted for a minimum of two bus clock cycles INT and SMI should be held asserted until the exception is taken CKSTP_IN must be held asserted until the system has been reset See the MPC750 RISC Microprocessor Family User s Manual for more information MPC755 RISC Microprocessor Hardware Specifications Rev 8 Freescale Semiconductor 15 Electrical and Thermal Characteristics Figure 6 provides the input output timing diagram for the MPC755 SYSCLK VM VM VM gt lt ixkH tivKH gt lt All Inputs gt e tkHOE All Outputs gt tkov Si tKHOX gt
55. l C2 Low Output OVpp CKSTP_IN B8 Low Input OVpp CKSTP_OUT D7 Low Output OVpp CLK_OUT E3 Output OVpp DBB K5 Low UO OVpp DBDIS Gi Low Input OVpp DBG K1 Low Input OVpp DBWO D1 Low Input OVpp MPC755 RISC Microprocessor Hardware Specifications Rev 8 Freescale Semiconductor 29 Pinout Listings Table 15 Pinout Listing for the MPC755 360 BGA Package continued Signal Name Pin Number Active HO I F Voltage Notes DH 0 31 W12 W11 V11 T9 W10 U9 U10 M11 M9 P8 W7 High UO OVpp P9 W9 R10 W6 V7 V6 U8 V9 T7 U7 R7 U6 W5 U5 W4 P7 V5 V4 W3 U4 R5 DL 0 31 M6 P3 N4 N5 R3 M7 T2 N6 U2 N7 P11 V13 High UO OVpp U12 P12 T13 W13 U13 V10 W8 T11 U11 V12 V8 T1 P1 V1 U1 N1 R2 V3 U3 W2 DP 0 7 L1 P2 M2 V2 M1 N2 T3 R1 High UO OVpp DRTRY H6 Low Input OVpp GBL B1 Low 1 0 OVpp GND D10 D14 D16 D4 D6 E12 E8 F4 F6 F10 F14 GND F16 G9 G11 H5 H8 H10 H12 H15 J9 J11 K4 K6 K8 K10 K12 K14 K16 L9 L11 M5 M8 M10 M12 M15 N9 N11 P4 P6 P10 P14 P16 R8 R12 T4 T6 T10 T14 T16 HRESET B6 Low Input OVpp INT C11 Low Input OVpp L1_TSTCLK F8 High Input 2 L2ADDR 16 0 G18 H19 J13 J14 H17 H18 J16 J17 J18 J19 K15 High Output L2OVpp K17 K18 M19 L19 L18 L17 L2AVpp L13 2 0 V L2CE P17 Low Output L2OVpp L2CLK_OUTA N15 Output L2OV
56. n simply tying TRST to HRESET is not practical The COP function of these processors allows a remote computer system typically a PC with dedicated hardware and debugging software to access and control the internal operations of the processor The COP interface connects primarily through the JTAG port of the processor with some additional status monitoring signals The COP port requires the ability to independently assert HRESET or TRST in order to fully control the processor If the target system has independent reset sources such as voltage monitors watchdog timers power supply failures or push button switches then the COP reset signals must be merged into these signals with logic The arrangement shown in Figure 24 allows the COP port to independently assert HRESET or TRST while ensuring that the target can drive HRESET as well If the JTAG interface and COP header will not be used TRST should be tied to HRESET through a 0 Q isolation resistor so that it is asserted when the system reset signal HRESET is asserted ensuring that the JTAG scan chain is initialized during power on While Freescale recommends that the COP header be designed into the system as shown in Figure 24 if this is not possible the isolation resistor will allow future access to TRST in the case where a JTAG interface may need to be wired onto the system in debug situations The COP header shown in Figure 24 adds many benefits breakpoints watchpoints
57. ower supply filter circuit 109 VDD WWW 7 7 9 AVpp or L2AVpp 2 2 UF 2 2 UF Low ESL Surface Mount Capacitors GND Figure 21 PLL Power Supply Filter Circuit 8 3 Decoupling Recommendations Due to the MPC755 dynamic power management feature large address and data buses and high operating frequencies the MPC755 can generate transient power surges and high frequency noise in its power supply especially while driving large capacitive loads This noise must be prevented from reaching other components in the MPC755 system and the MPC755 itself requires a clean tightly regulated source of power Therefore it is recommended that the system designer place at least one decoupling capacitor at each Vpp OVpp and L2OVpp pin of the MPC755 It is also recommended that these decoupling capacitors receive their power from separate Vpp L2 OVpp and GND power planes in the PCB utilizing short traces to minimize inductance MPC755 RISC Microprocessor Hardware Specifications Rev 8 38 Freescale Semiconductor System Design Information These capacitors should have a value of 0 01 or 0 1 uF Only ceramic SMT surface mount technology capacitors should be used to minimize lead inductance preferably 0508 or 0603 orientations where connections are made along the length of the part In addition it is recommended that there be several bulk storage capacitors distributed around the PCB feeding the Vpp L2OVpp and OVpp planes to enable quick rec
58. pp L2CLK_OUTB L16 Output L2OVpp L2DATA 0 63 U14 R13 W14 W15 V15 U15 W16 V16 W17 V17 High IO L2OVpp U17 W18 V18 U18 V19 U19 T18 T17 R19 R18 R17 R15 P19 P18 P13 N14 N13 N19 N17 M17 M13 M18 H13 G19 G16 G15 G14 G13 F19 F18 F13 E19 E18 E17 E15 D19 D18 D17 C18 C17 B19 B18 B17 A18 A17 A16 B16 C16 A14 A15 C15 B14 C14 E13 L2DP 0 7 V14 U16 T19 N18 H14 F17 C19 B15 High IO L2OVpp L2OVpp D15 E14 E16 H16 J15 L15 M16 P15 R14 R16 L2OVpp T15 F15 L2SYNC_IN L14 Input L2OVpp L2SYNC_OUT M14 Output L2OVpp L2_TSTCLK F7 High Input _ 2 L2VSEL A19 High Input L2OVpp 1 5 6 7 L2WE N16 Low Output L2OVpp MPC755 RISC Microprocessor Hardware Specifications Rev 8 30 Freescale Semiconductor Pinout Listings Table 15 Pinout Listing for the MPC755 360 BGA Package continued Signal Name Pin Number Active HO I F Voltage Notes L2ZZ G17 High Output L2OVpp LSSD_MODE F9 Low Input 2 MCP B11 Low Input OVpp NC No Connect B3 B4 B5 W19 K9 K11 4 K19 4 OVpp D5 D8 D12 E4 E6 E9 E11 F5 H4 J5 L5 M4 P5 OVpp R4 R6 R9 R11 T5 T8 T12 PLL_CFG 0 3 A4 A5 A6 A7 High Input OVpp QACK B2 Low Input OVpp QREQ J3 Low Output OVpp RSRV D3 Low Output OVpp SMI A12 Low Input OVpp SRESET E10 Low Input OVpp SYSCLK H9 Input OVpp TA F1 Low
59. r PLL lock after a stable Vpp and SYSCLK are reached during the power on reset sequence This specification also applies when the PLL has been disabled and subsequently re enabled during sleep mode Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL relock time during the power on reset sequence A MPC755 RISC Microprocessor Hardware Specifications Rev 8 12 Freescale Semiconductor Electrical and Thermal Characteristics Figure 3 provides the SYSCLK input timing diagram SYSCLK VM Midpoint Voltage OVpp 2 Figure 3 SYSCLK Input Timing Diagram 4 2 2 Processor Bus AC Specifications Table 9 provides the processor bus AC timing specifications for the MPC755 as defined in Figure 4 and Figure 6 Timing specifications for the L2 bus are provided in Section 4 2 3 L2 Clock AC Specifications Table 9 Processor Bus Mode Selection AC Timing Specifications 1 At recommended operating conditions see Table 3 All Speed Grades Parameter Symbol 2 Unit Notes Min Max Mode select input setup to HRESET MVRH 8 Bier 3 4 5 6 7 HRESET to mode select input hold tuxRH 0 ns 3 4 6 7 8 Notes N All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input SYSCLK All output specifications are measured from the midpoint of the rising edge of SYSCLK to the midpoint o
60. r than the thermal grease joint Heat sinks are attached to the package by means of a spring clip to holes in the printed circuit board see Figure 25 This spring force should not exceed 5 5 pounds of force Therefore the synthetic grease offers the best thermal performance considering the low interface pressure Of course the selection of any thermal interface material depends on many factors thermal performance requirements manufacturability service temperature dielectric properties cost etc Figure 27 describes the thermal performance of select thermal interface materials MPC755 RISC Microprocessor Hardware Specifications Rev 8 46 Freescale Semiconductor System Design Information 2 e Silicone Sheet 0 006 in F l r j j Bare Joint L D Floroether Oil Sheet 0 007 in O Graphite Oil Sheet 0 005 in E E Synthetic Grease Zoo acest ee E E Deeg ee L N D 1 H 1 7 l 1 H E FC H 1 H 1 Tee d 1 1 4 S L Een E 1 H 1 H 1 H e wl D oO 1 1 1 Fe e cod S 1 1 1 S ZS e Rn 8 1t DEEG T EE DEER DEER or EE E i ia as ee E L ee D b i H 1 1 ped oO L e fr _ ven H 1 1 H 1 Sa ES i 1 SA aa iere i 1 i 95 LI Tera e ees Ge Ne et Sek RS A a MLR AER et Ihe Soy Ne ee Ti tel opel A i 1 1 1 oe EES 1 os 1 o a E 0 4 f t t H t t t 0 10 20 30 40 50 60 70 80 Contact Pressure psi Figu
61. re 27 Thermal Performance of Select Thermal Interface Materials The board designer can choose between several types of thermal interface Heat sink adhesive materials should be selected based on high conductivity yet adequate mechanical strength to meet equipment shock vibration requirements There are several commercially available thermal interfaces and adhesive materials provided by the following vendors The Bergquist Company 18930 West 78 St Chanhassen MN 55317 Internet www bergquistcompany com Chomerics Inc 77 Dragon Ct Woburn MA 01888 4014 Internet www chomerics com Dow Corning Corporation Dow Corning Electronic Materials 2200 W Salzburg Rd Midland MI 48686 0997 Internet www dow com 800 347 4572 781 935 4850 800 248 2481 MPC755 RISC Microprocessor Hardware Specifications Rev 8 Freescale Semiconductor 47 System Design Information Shin Etsu MicroSi Inc 888 642 7674 10028 S 51st St Phoenix AZ 85044 Internet www microsi com Thermagon Inc 888 246 9050 4707 Detroit Ave Cleveland OH 44102 Internet www thermagon com 8 8 3 Heat Sink Selection Example This section provides a heat sink selection example using one of the commercially available heat sinks For preliminary heat sink sizing the die junction temperature can be expressed as follows T Ta T el Oint Osa x Pa where Tj is the die junction temperature T 1s the inlet cabinet ambient temperature
62. re given in Table 3 Absolute maximum ratings are stress ratings only and functional operation at the maximums is not guaranteed Stresses beyond those listed may affect device reliability or cause permanent damage to the device Caution Vin must not exceed OVpp or L2OVpp by more than 0 3 V at any time including during power on reset Caution L2OVpp OVpp must not exceed Vpp AVpp L2AVpp by more than 1 6 V during normal operation During power on reset and power down sequences L2OVpp OVpp may exceed Vpp AVpp L2AVpp by up to 3 3 V for up to 20 ms or by 2 5 V for up to 40 ms Excursions beyond 3 3 V or 40 ms are not supported Caution Vpp AVpp L2AVpp must not exceed L2OVpp OVpp by more than 0 4 V during normal operation During power on reset and power down sequences Vpp AVpp L2AVpp may exceed L2OVpp OVpp by up to 1 0 V for up to 20 ms or by 0 7 V for up to 40 ms Excursions beyond 1 0 V or 40 ms are not supported This is a DC specifications only Vin may overshoot undershoot to a voltage and for a maximum duration as shown in Figure 2 MPC755 RISC Microprocessor Hardware Specifications Rev 8 Freescale Semiconductor Electrical and Thermal Characteristics Figure 2 shows the allowable undershoot and overshoot voltage on the MPC755 L2 OVpp 20 L2 OVpp 5 EE Nec Nes es ViH ViL GND 2227 22 eet cee ee cee eee es oo ol GND 0 3 V GND 0 7 V Le gt Le Not to Exceed 10 g
63. scale Semiconductor System Design Information Table 16 MPC755 Microprocessor PLL Configuration Example for 400 MHz Parts continued Example Bus to Core Frequency in MHz VCO Frequency in MHz PLL_CFG Ge oe 0 3 phe Erem Bus Bus Bus Bus Bus Bus SEH SR 33 MHz 50 MHz 66 MHz 75 MHz 80 MHz 100 MHz Multiplier Multiplier 0011 PLL off bypass PLL off SYSCLK clocks core circuitry directly 1x bus to core implied 1111 PLL off PLL off no core clocking occurs Notes i PLL_CFG 0 3 settings not listed are reserved 2 The sample bus to core frequencies shown are for reference only Some PLL configurations may select bus core or VCO frequencies which are not useful not supported or not tested for by the MPC755 see Section 4 2 1 Clock AC Specifications for valid SYSCLK core and VCO frequencies 3 In PLL bypass mode the SYSCLK input signal clocks the internal processor directly the PLL is disabled and the bus mode is set for 1 1 mode operation This mode is intended for factory use and emulator tool use only Note The AC timing specifications given in this document do not apply in PLL bypass mode 4 In PLL off mode no clocking occurs inside the MPC755 regardless of the SYSCLK input The MPC755 generates the clock for the external L2 synchronous data SRAMs by dividing the core clock frequency of the MPC755 The divided down clock is then phase adjusted by an on chip delay lock loop DLL circui
64. t of tsyscLk Figure 2 Overshoot Undershoot Voltage The MPC755 provides several I O voltages to support both compatibility with existing systems and migration to future systems The MPC755 core voltage must always be provided at nominal 2 0 V see Table 3 for actual recommended core voltage Voltage to the L2 I Os and processor interface I Os are provided through separate sets of supply pins and may be provided at the voltages shown in Table 2 The input voltage threshold for each bus is selected by sampling the state of the voltage select pins BVSEL and L2VSEL during operation These signals must remain stable during part operation and cannot change The output voltage will swing from GND to the maximum voltage applied to the OVpp or L2OV pp power pins Table 2 describes the input threshold voltage setting Table 2 Input Threshold Voltage Setting Part P Processor Bus A L2 Bus Revision BVSEL Signal Interface Voltage L2VSEL Signal Interface Voltage E 0 Not Available 0 Not Available 1 2 5 V 3 3 V 1 2 5 V 3 3 V Caution The input threshold selection must agree with the OVpp L2OVpp voltages supplied Note The input threshold settings above are different for all revisions prior to Rev 2 8 Rev E For more information refer to Section 10 2 Part Numbers Not Fully Addressed by This Document MPC755 RISC Microprocessor Hardware Specifications Rev 8 Freescale Semiconductor 7 Electrical and T
65. t and should be routed from the MPC755 to the external RAMs A separate clock output L2SYNC_OUT is sent out half the distance to the SRAMs and then returned as an input to the DLL on pin L2SYNC_IN so that the rising edge of the clock as seen at the external RAMs can be aligned to the clocking of the internal latches in the L2 bus interface The core to L2 frequency divisor for the L2 PLL is selected through the L2CLK bits of the L2CR register Generally the divisor must be chosen according to the frequency supported by the external RAMs the frequency of the MPC755 core and the phase adjustment range that the L2 DLL supports Table 17 shows various example L2 clock frequencies that can be obtained for a given set of core frequencies The minimum L2 frequency target is 80 MHz Table 17 Sample Core to L2 Frequencies Core Frequency MHz 1 1 5 2 2 5 3 250 250 166 125 100 83 266 266 177 133 106 89 275 275 183 138 110 92 300 300 200 150 120 100 325 325 217 163 130 108 333 333 222 167 133 111 350 350 233 175 140 117 366 366 244 183 146 122 MPC755 RISC Microprocessor Hardware Specifications Rev 8 Freescale Semiconductor 37 System Design Information Table 17 Sample Core to L2 Frequencies continued Core Frequency MHz 1 1 5 2 2 5 3 375 375 250 188 150 125 400 400 266 200 160 133 Note The core and L2 frequencies are for reference only Som
66. t board per JEDEC JESD51 8 Board temperature is measured on the top surface of the board near the package 5 Thermal resistance between the die and the case top surface as measured by the cold plate method MIL SPEC 883 Method 1012 1 with the calculated case temperature The actual value of Bac for the part is less than 0 1 C W 6 Refer to Section 8 8 Thermal Management Information for more details about thermal management wo The MPC755 incorporates a thermal management assist unit TAU composed of a thermal sensor digital to analog converter comparator control logic and dedicated special purpose registers SPRs See the MPC750 RISC Microprocessor Family User s Manual for more information on the use of this feature Specifications for the thermal sensor portion of the TAU are found in Table 5 MPC755 RISC Microprocessor Hardware Specifications Rev 8 Freescale Semiconductor 9 Electrical and Thermal Characteristics Table 5 Thermal Sensor Specifications At recommended operating conditions see Table 3 Characteristic Min Max Unit Notes Temperature range 0 127 C 1 Comparator settling time 20 Gees US 2 3 Resolution 4 C 3 Accuracy 12 12 C 3 Notes 1 The temperature is the junction temperature of the die The thermal assist units raw output does not indicate an absolute temperature but must be interpreted by software to derive the absolute junction temperature For
67. t reliability of the PBGA package Freescale recommends use of a PBGA package except where circumstances dictate use of a CBGA package The MPC745 is offered in a PBGA package only MPC755 RISC Microprocessor Hardware Specifications Rev 8 8 Freescale Semiconductor Electrical and Thermal Characteristics Table 4 Package Thermal Characteristics 6 Value Characteristic Symbol MPC755 MPC755 MPC745 Unit Notes CBGA PBGA PBGA Junction to ambient thermal resistance natural Roya 24 31 34 C W 1 2 convection Junction to ambient thermal resistance natural Rogma 17 25 26 C W 1 3 convection four layer 2s2p board Junction to ambient thermal resistance 200 ft min Rogma 18 25 27 C W 1 3 airflow single layer 1s board Junction to ambient thermal resistance 200 ft min Roma 14 21 22 C W 1 3 airflow four layer 2s2p board Junction to board thermal resistance Rous 8 17 17 C W 4 Junction to case thermal resistance Doc lt 0 1 lt 0 1 lt 0 1 C W 5 Notes 1 Junction temperature is a function of on chip power dissipation package thermal resistance mounting site board temperature ambient temperature air flow power dissipation of other components on the board and board thermal resistance 2 Per SEMI G38 87 and JEDEC JESD51 2 with the single layer board horizontal Per JEDEC JESD51 6 with the board horizontal 4 Thermal resistance between the die and the printed circui
68. tate arithmetic logical Single cycle arithmetic shifts rotates logical Multiply and divide support multi cycle Early out multiply Floating point unit and a 32 entry FPR file Support for IEEE standard 754 single and double precision floating point arithmetic Hardware support for divide Hardware support for denormalized numbers Single entry reservation station Supports non IEEE mode for time critical operations Three cycle latency one cycle throughput single precision multiply add MPC755 RISC Microprocessor Hardware Specifications Rev 8 Freescale Semiconductor 3 Features Three cycle latency one cycle throughput double precision add Four cycle latency two cycle throughput double precision multiply add e System unit Executes CR logical instructions and miscellaneous system instructions Special register transfer instructions e Load store unit One cycle load or store cache access byte half word word double word Effective address generation Hits under misses one outstanding miss Single cycle unaligned access within double word boundary Alignment zero padding sign extend for integer register file Floating point internal format conversion alignment normalization Sequencing for load store multiples and string operations Store gathering Cache and TLB instructions Big and little endian byte addressing supported e Level 1 cache structure 32K 32 byte line
69. tion 7 Package Description for more information on available package types 2 The X prefix in a Freescale part number designates a Pilot Production Prototype as defined by Freescale SOP 3 13 These are from a limited production volume of prototypes manufactured tested and Q A inspected on a qualified technology to simulate normal production These parts have only preliminary reliability and characterization data Before pilot production prototypes may be shipped written authorization from the customer must be on file in the applicable sales office acknowledging the qualification status and the fact that product changes may still occur while shipping pilot production prototypes MPC755 RISC Microprocessor Hardware Specifications Rev 8 Freescale Semiconductor 53 Ordering Information 10 2 Part Numbers Not Fully Addressed by This Document Devices not fully addressed in this document are described in separate hardware specification addendums which supplement and supersede this document as described in the following tables Table 21 Part Numbers Addressed by XPC755BxxnnnTx Series Part Numbers Document No MPC755ECSO1AD XPC 755 B XX nnn T x Product Part Process Processor ots Re AC Code Identifier Descriptor Package Frequency Application Modifier Revision Level XPC 755 B HiP4DP RX CBGA 350 T 2 0 V 100 mV D 2 7 PVR 0008 32
70. uch as IBIS Rp and Ry are designed to be close to each other in value Then Zp Rp Ry 2 Figure 23 describes the alternate driver impedance measurement circuit L2 OVpp BGA Pin Data Viorce OGND Figure 23 Alternate Driver Impedance Measurement Circuit MPC755 RISC Microprocessor Hardware Specifications Rev 8 40 Freescale Semiconductor System Design Information Table 18 summarizes the signal impedance results The driver impedance values were characterized at 0 65 and 105 C The impedance increases with junction temperature and is relatively unaffected by bus voltage Table 18 Impedance Characteristics Von 2 0 V OVop 3 3 V Tj 0 1 05 C Impedance Processor Bus L2 Bus Symbol Unit Rn 25 36 25 36 Zo Q Rp 26 39 26 39 Zo Q 8 6 Pull Up Resistor Requirements The MPC755 requires pull up resistors 1 5 KQ on several control pins of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the MPC755 or other bus masters These pins are TS ABB AACK ARTRY DBB DBWO TA TEA and DBDIS DRTRY should also be connected to a pull up resistor 1 5 KQ if it will be used by the system otherwise this signal should be connected to HRESET to select NO DRTRY mode see the MPC750 RISC Microprocessor Family User s Manual for more information on this mode Three test pins also require pull up resistors
71. us BurstRAMs L2CR 14 15 01 or 10 is recommended For pipelined late write synchronous BurstRAMs L2CR 14 15 11 is recommended Guaranteed by design and characterization Revisions prior to Rev 2 8 Rev E were limited in performance and did not conform to this specification For more information refer to Section 10 2 Part Numbers Not Fully Addressed by This Document Figure 8 shows the L2 bus input timing diagrams for the MPC755 tLocr gt lt gt lt tLocr L2SYNC_IN tpvL2ecH gt Le tpxL2cH L2 Data and Data Parity Inputs VM Midpoint Voltage L2OVpp 2 Figure 8 L2 Bus Input Timing Diagrams MPC755 RISC Microprocessor Hardware Specifications Rev 8 20 Freescale Semiconductor Electrical and Thermal Characteristics Figure 9 shows the L2 bus output timing diagrams for the MPC755 L2SYNC_IN gt All Outputs L2DATA BUS e tL2cHox lt _tL2cHoz VM Midpoint Voltage L2OVpp 2 Figure 9 L2 Bus Output Timing Diagrams Figure 10 provides the AC test load for L2 interface of the MPC755 Figure 10 AC Test Load for the L2 Interface MPC755 RISC Microprocessor Hardware Specifications Rev 8 Freescale Semiconductor 21 Electrical and Thermal Characteristics 4 2 5 IEEE 1149 1 AC Timing Specifications Table 13 provides the IEEE 1149 1 JTAG AC timing specifications as defined in Figure 12 through Figure 15 Table 13 JTA
72. with Table 8 Table 16 shows the valid configurations of these signals and an example illustrating the core and VCO frequencies resulting from various PLL configurations and example bus frequencies In this example shaded cells represent settings that for a given SYSCLK frequency result in core and or VCO frequencies that do not comply with the 400 MHz column in Table 8 Table 16 MPC755 Microprocessor PLL Configuration Example for 400 MHz Parts Example Bus to Core Frequency in MHz VCO Frequency in MHz PLL_CFG 0 3 ge ssl Bus Bus Bus Bus Bus Bus ae a 33 MHz 50 MHz 66 MHz 75 MHz 80 MHz 100 MHz Multiplier Multiplier 0100 2x 2x 200 400 1000 3x 2x 200 225 240 300 400 450 480 600 1110 3 5x 2x 233 263 280 350 466 525 560 700 1010 4x 2x 200 266 300 320 400 400 533 600 640 800 0111 4 5x 2x 225 300 338 360 450 600 675 720 1011 5x 2x 250 333 375 400 500 666 750 800 1001 5 5x 2x 275 366 550 733 1101 6x 2x 200 300 400 400 600 800 0101 6 5x 2x 216 325 433 650 0010 7x 2x 233 350 466 700 0001 7 5x 2x 250 375 500 750 1100 8x 2x 266 400 533 800 0110 10x 2x 333 666 MPC755 RISC Microprocessor Hardware Specifications Rev 8 36 Free

MPC755 RISC Microprocessor Hardware Specifications

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