Usage Notes on A/D Conversion Delaying Function of MTU2 and
Contents
1. Count TRG4AN Enable Enables or disables A D converter start requests TRG4AN during TCNT 4 up count operation 0 A D converter start requests TRG4AN disabled during TCNT 4 up count operation 1 A D converter start requests TRG4AN enabled during TCNT 4 up count operation Down Count TRGAAN Enable Enables or disables A D converter start requests TRG4AN during TCNT 4 down count operation 0 A D converter start requests TRG4AN disabled during TCNT 4 down count operation 1 A D converter start requests TRG4AN enabled during TCNT 4 down count operation Up Count TRG4BN Enable Enables or disables A D converter start requests TRG4BN during TCNT 4 up count operation 0 A D converter start requests TRG4BN disabled during TCNT 4 up count operation 1 A D converter start requests TRG4BN enabled during TCNT 4 up count operation Down Count TRGABN Enable Enables or disables A D converter start requests TRG4BN during TCNT_4 down count operation 0 A D converter start requests TRG4BN disabled during TCNT 4 down count operation 1 A D converter start requests TRG4BN enabled during TCNT 4 down count operation i i TCIV 4 Interrupt Skipping Link Enable Select whether to link A D converter start requests TRG4AN with TCIV_4 interrupt skipping operation 0 Does not link with TCIV 4 interrupt skipping 1 Links with TCIV 4 interrupt skipping TGIA 3 Interrupt Skipping Link Enable Select whether to link A D converter start requests T2. Mode When TADCOBRA 4 TADCOBRB 4 is set to 0 and the UT4AE or UTABE bit in TADCR is set to 1 and then buffer transfer takes place at the trough of TCNT 4 no A D converter start request occurs during the up counting interval immediately after the transfer figure 2 1 When the value of TADCOBRA 4 TADCOBRB 4 is the same as that of TCDR and the DT4AE or DT4BE bit in TADCR is set to 1 and then buffer transfer takes place at the crest of TCNT 4 no A D converter start request occurs during the down counting interval immediately after the transfer figure 2 2 When A D converter start requests are linked to the interrupt skipping function set TADCORA A4 TADCORB 4 such that the condition of 2 lt TADCORA 4 TADCORB 4 x TCDR 2 is met c 2014 Renesas Electronics Corporation All rights reserved Page 1 of 12 24 IN ESAS RENESAS TECHNICAL UPDATE TN SH7 A884A E Date August 22 2014 O written to TADCOBRA_4 TADCOBRB _ 4 TADCORA_4 TADCORB_4 e TADCOBRA B_4 N I I A D converter start request TRG4AN No A D converter start request occurs during the up counting Complementary PWM mode interval immediately after the buffer transfer trough UT4AE 1 DT4AE 0 Note When a value of 1 x TADCOBRA_4 TADCOBRB_4 lt BF 1 0 B 10 transfer at trough TCDR 1 is written an A D converter start request is issued Figure 2 1 A D Converter Start Request Operation when 0 Is Written to TADCOBRA 4 TADCOBRB
3. 4 Same Value as TCDR written to TADCOBRA A TADCOBRB 4 V TADCOBRA B_4 TADCORA A4 TADCORB 4 A D converter start request TRG4AN No A D converter start request occurs during the up counting Complementary PWM mode interval immediately after the buffer transfer crest UT4AE 0 DT4AE 1 Note When a value of TCDR 1 gt TADCOBRA 4 BF 1 0 B 10 transfer at crest TADCOBRB 4 1 is written an A D converter start request is issued Figure 2 2 A D Converter Start Request Operation when Same Value as TCDR Is Written to TADCOBRA A4 TADCOBRB 4 Corrections in the User s Manual Corrections of the User s Manual are described below using the SH7214 Group SH7216 Group User s Manual Hardware as an example Re Page 2 of 12 sKLKENESAS RENESAS TECHNICAL UPDATE TN SH7 A884A E Date August 22 2014 11 3 10 Timer A D Converter Start Request Control Register TADCR Before correction p 506 to 508 Bit 15 14 13 12 11 10 9 8 T 6 5 4 3 2 1 0 Lema Teese orase rose sore renee rene Initial value O 0 0 0 0 0 0 0 0 oF 0 O 0 OF OF O RAV RW RAW R R R R R R RAV RW RW RW RN RW RW RAN Notes Do not set to 1 when complementary PWM mode is not selected Bit Initial Name Value R W Description 15 14 BF 1 0 R W TADCOBRA A4 TADCOBRB 4 Transfer Timing Select Select the timing for transferring data from TADCOBRA 4 and TADCOBRB 4 to TADCORA 4 and TADCORB 4 For details see table 11 29 Up
4. 4BE bits delaying function y to 0 when complementary PWM mode is not selected 4 Clear the ITA3AE ITAAVE ITB3AE or ITBAVE bit to 0 to disable interrupt skipping Figure 11 79 Example of Procedure for Specifying A D Converter Start Request Delaying Function Re Page 7 of 12 sKLKENESAS RENESAS TECHNICAL UPDATE TN SH7 A884A E Date August 22 2014 e Basic Operation Example of A D Converter Start Request Delaying Function Before correction p 616 Transfer from cycle buffer Transfer from cycle buffer Transfer from cycle buffer register to cycle register register to cycle register register to cycle register TADCORA 4 H TADCOBRA 4 were eee eee 7 URRRRRRRERRERREENE ee T A D converter start request i TRG4AN Complementary PWM mode Figure 11 80 Basic Example of A D Converter Start Request Signal TRG4AN Operation After Correction A D converter A D converter Transfer from cycle buffer Transfer from cycle buffer start request start request register to cycle register register to cycle register enabled interval enabled interval DT4AE UT4AE TADCORA 4 H TADCOBRA 4 Serer Serre M T T A D converter start request TRG4AN Complementary PWM mode UT4AE 0 DT4AE 1 A D converter start request enabled interval UT4AE O lt TCNT 4 1CDR 1 BF 1 0 B 10 A D converter start request enabled interval DT4AE TCDR g
5. B 4 is the same as that of TCDR and the DT4AE or DTABE bit in TADCR is set to 1 and then buffer transfer takes place at the crest of TCNT 4 no A D converter start request occurs during the down counting interval immediately after the transfer figure 11 140 When A D converter start requests are linked to the interrupt skipping function set TADCORA A4 TADCORB 4 such that the condition of 2 lt TADCORA A TADCORB 4 x TCDR 2 is met O written to TADCOBRA A TADCOBRB 4 TADCORA A4 TADCORB 4 A D converter start request TRG4AN No A D converter start request occurs during the up counting Complementary PWM mode interval immediately after the buffer transfer trough UT4AE 1 DT4AE 0 Note When a value of 1 lt TADCOBRA_4 TADCOBRB_4 lt BF 1 0 B 10 transfer at trough TCDR 1 is written an A D converter start request is issued Figure 11 139 A D Converter Start Request Operation when 0 Is Written to TADCOBRA_4 TADCOBRB 4 Same Value as TCDR written to TADCOBRA A4 TADCOBRB 4 V TADCOBRA B 4 TADCORA A4 TADCORB 4 A D converter start request TRG4AN No A D converter start request occurs during the up counting Complementary PWM mode interval immediately after the buffer transfer crest UT4AE 0 DT4AE 1 Note When a value of TCDR 1 gt TADCOBRA 4 BF 1 0 B 10 transfer at crest TADCOBRB 4 1 is written an A D converter start request is issued Figure 11 140 A D Converter Start Requ
6. Date August 22 2014 RENESAS TECHNICAL UPDATE 1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan Renesas Electronics Corporation Product MPU MCU Document Category No TN SH7 A884A E Rev 1 00 Usage Notes on A D Conversion Delaying Information Title Technical Notification Function of MTU2 and MTU2S Category Lot No No Applicable Sas belon Reference Scbol Product All lots Document Usage notes on A D conversion delaying function of the multi function timer pulse unit 2 MTU2 and MTU2S for the products listed below are as follows Usage Notes 1 A D Converter Start Request Enabled Interval Ifthe UTAAE or UTABE bit is set to 1 in complementary PWM mode A D converter start requests are enabled during the TCNT 4 up counting interval The A D converter start request enabled interval is 0 TCNT 4 TCDR 1 e Ifthe DT4AE or DT4BE bit is set to 1 in complementary PWM mode A D converter start requests are enabled during the TCNT 4 down counting interval The A D converter start request enabled interval is TCDR gt TCNT 4 1 Clear the DTAAE and DT4BE bits to 0 when not in complementary PWM mode Setting the UT4AE or UTABE bit to 1 causes an A D converter start request to be generated at a compare match between TCNT 4 and TADCORA A TADCORB 4 regardless of whether TCNT 4 is counting up or down 2 Notes on Using the A D Converter Start Request Delaying Function in Complementary PWM
7. M Mode Reset Synchronized PWM Mode Does not transfer data from the cycle set Does not transfer data from the cycle set buffer register buffer register TADCOBRA 4 TADCOBRB 4 to the TADCOBRA_4 TADCOBRB 4 to the cycle set register cycle set register TADCORA A4 TADCORB 4 TADCORA A4 TADCORB 4 Transfers data from the cycle set buffer Transfers data from the cycle set buffer register TADCOBRA 4 TADCOBRB 4 to register T ADCOBRA A4 TADCOBRB 4 to the cycle set register the cycle set register TADCORA A TADCORB 4 at the crest of TCADCORA 4 TADCORB 4 when a TCNT 4 compare match occurs between TCNT 3 and TGRA 3 Transfers data from the cycle set buffer Setting prohibited register TADCOBRA 4 TADCOBRB 4 to the cycle set register TADCORA A4 TADCORB 4 at the trough of TCNT 4 Transfers data from the cycle set buffer Setting prohibited register TADCOBRA 4 TADCOBRB 4 to the cycle set register TADCORA 4 TADCORB 4 at the crest and trough of TCNT 4 Bit 15 Bit 14 Description BF1 BFO PWM Mode 1 Normal Mode Does not transfer data from the cycle set Does not transfer data from the cycle set buffer register buffer register TADCOBRA 4 TADCOBRB 4 to the TADCOBRA 4 TADCOBRB 4 to the cycle set register cycle set register TADCORA 4 TADCORB 4 TADCORA A4 TADCORB 4 1 Transfers data from the cycle set buffer Transfers data from the cycle set buffer register TADCOBRA 4 TADCOBRB 4 to register the cyc
8. RG4BN with TGIA 3 interrupt skipping operation 0 Does not link with TGIA 3 interrupt skipping 1 Links with TGIA 3 interrupt skipping TCIV 4A Interrupt Skipping Link Enable Select whether to link A D converter start requests TRG4BN with TCIV 4 interrupt skipping operation 0 Does not link with TCIV 4 interrupt skipping 1 Links with TCIV 4 interrupt skipping i i ITBAVE Notes 1 TADCR must not be accessed in eight bits it should always be accessed in 16 bits 3 ITASAE 0 TGIA 3 Interrupt Skipping Link Enable Select whether to link A D converter start requests TRG4AN with TGIA 3 interrupt skipping operation 0 Does not link with TGIA 3 interrupt skipping 1 Links with TGIA 3 interrupt skipping 2 When interrupt skipping is disabled the T3AEN and TAVEN bits in the timer interrupt skipping set register TITCR are cleared to 0 or the skipping count set bits 3ACOR and 4VCOR in TITCR are cleared to 0 do not link A D converter start requests with interrupt skipping operation clear the ITA3AE ITAAVE Re Page 3 of 12 sKENESAS RENESAS TECHNICAL UPDATE TN SH7 A884A E ITB3AE and ITB4VE bits in the timer A D converter start request control register TADCR to 0 3 If link with interrupt skipping is enabled while interrupt skipping is disabled A D converter start requests will not be issued Do not set to 1 when complementary PWM mode is not selected After Correction Bit 15 14 13 12 11 10 9 Lema T T
9. T T T T Teeepros ves ovas rne saevo 0 0 Initial value 0 0 0 0 0 0 0 0 0 R W RAW R W R R R R R z RU EN RM RUN RU R W EU RU Notes Accessing TADCR in 8 bit units is prohibited Always access TADCR in 16 bit units Set to 0 when complementary PWM mode is not selected Bit Initial Name Value R W Description 15 14 BF 1 0 0 Q R W TADCOBRA 4 TADCOBRB 4 Transfer Timing Select Select the timing for transferring data from TADCOBRA 4 and TADCOBRB 4 to TADCORA 4 and TADCORB 4 For details see table 11 29 Up Count TRG4AN Enable Enables or disables A D converter start requests TRG4AN during TCNT_4 up count operation 0 A D converter start requests TRG4AN are disabled during TCNT_4 up count operation 1 A D converter start requests TRG4AN are enabled during TCNT_4 up count operation Down Count TRG4AN Enable Enables or disables A D converter start requests TRG4AN during TCNT_4 down count operation 0 A D converter start requests TRG4AN are disabled during TCNT 4 down count operation 1 A D converter start requests TRG4AN are enabled during TCNT 4 down count operation UTABE R W Up Count TRG4BN Enable Enables or disables A D converter start requests TRG4BN during TCNT 4 up count operation 0 A D converter start requests TRG4BN are disabled during TCNT 4 up count operation 1 A D converter start requests TRG4BN are enabled during TCNT_4 up count operation 4 DT4BE Ox R W Down Count TRG4BN Enable Ena
10. bles or disables A D converter start requests TRG4BN during TCNT 4 down count operation 0 A D converter start requests TRG4BN are disabled during TCNT 4 down count operation 1 A D converter start requests TRG4BN are enabled during TCNT 4 down count operation 3 ITA3AE opm TGIA_3 Interrupt Skipping Link Enable Selects whether to link A D converter start requests TRG4AN with TGIA_3 interrupt skipping operation 0 Does not link with TGIA_3 interrupt skipping operation 1 Links with TGIA 3 interrupt skipping operation 24 NE SAS Date August 22 2014 Page 4 of 12 RENESAS TECHNICAL UPDATE TN SH7 A884A E Date August 22 2014 Initial Name Value R W Description ITA4VE OBSS TCIV 4 Interrupt Skipping Link Enable Selects whether to link A D converter start requests TRG4AN with TCIV 4 interrupt skipping operation 0 Does not link with TCIV 4 interrupt skipping operation 1 Links with TCIV 4 interrupt skipping operation ITB3AE 0 1 2x3 TGIA_3 Interrupt Skipping Link Enable Selects whether to link A D converter start requests TRG4BN with TGIA_3 interrupt skipping operation 0 Does not link with TGIA 3 interrupt skipping operation 1 Links with TGIA 3 interrupt skipping operation ITBAVE Qi 233 TCIV 4 Interrupt Skipping Link Enable Selects whether to link A D converter start requests TRG4BN with TCIV 4 interrupt skipping operation 0 Does not link with TCIV 4 interrupt skipping operation 1 Links with TCIV 4 interrupt ski
11. est Operation when Same Value as TCDR Is Written to TADCOBRA A4 TADCOBRB 4 Re Page 11 of 12 sKLKENESAS RENESAS TECHNICAL UPDATE TN SH7 A884A E Date August 22 2014 Applicable Products and Reference Documents Reference Document SH7080 SH7083 SH7084 SH7080 Group User s Manual Hardware 5 00 RO1UHO0198EJ0500 SH7085 SH7086 SH7137 SH7131 SH7132 SH7137 Group Hardware Manual 3 00 REJO9B0402 0300 SH7136 SH7137 SH7200 SH7211 SH7216 SH7214 SH7216 SH7214 Group SH7216 Group User s Manual RO1UHO0230EJ0400 Hardware SH7231 SH7231 SH7231 Group User s Manual Hardware RO1UHO0073EJ0200 SH7239 Group SH7237 Group User s Manual Hardware SH7243 SH7280 Group SH7243 Group User s Manual Hardware SH7260 SH7261 SH7261 Group User s Manual Hardware R01UHO0025EJ0300 SH7262 SH7264 SH7262 Group SH7264 Group User s Manual 3 00 Hardware RO1UH0134EJ0300 SH7265 SH7265 Group Hardware Manual REJ09B0351 0200 SH7266 Group SH7267 Group User s Manual M onem Hardware R01UH0412EJ0200 SH7268 Group SH7269 Group User s Manual 20 pure Hardware RO1UHO0048EJ0200 SH726A Group SH726B Group User s Manual Pm uestem Hardware R01UH0202EbJ0100 3 00 SH7280 H7285 SH7286 SH7280 Group SH7243 Group User s Manual R801UH0229EJ0300 Hardware SH Tiny SH7124 SH7125 SH7125 Group SH7124 Group Hardware REJ09B0243 0500 Manual End of Document Re Page 12 of 12 sKLKENESAS
12. le set register TADCOBRA 4 TADCOBRB 4 to the TADCORA A4 TADCORB 4 when a cycle set register compare match occurs between TCNT 4 TADCORA A4 TADCORB 4 when a and TGRA 4 compare match occurs between TCNT 4 and TGRA 4 LEES Setting prohibited Setting prohibited Setting prohibited Setting prohibited Re Page 6 of 12 sKENESAS RENESAS TECHNICAL UPDATE TN SH7 A884A E Date August 22 2014 11 4 9 A D Converter Start Request Delaying Function e Example of Procedure for Specifying A D Converter Start Request Delaying Function Before correction p 615 1 Set the cycle in the timer A D converter start request cycle buffer register TADCOBRA 4 or TADCOBRB 4 and timer A D delaying function converter start request cycle register TADCORA_4 or TADCORB 4 The same initial value must be specified in the cycle buffer register and cycle register the timer A D converter start request cycle buffer register to A D converter start request cycle register e Set the timing of transfer e Specify whether to link with interrupt skipping through bits from cycle set buffer register ITA3AE ITAAVE ITB3AE and ITBAVE e Set linkage with interrupt skipping e Use bits TU4AE DT4AE UT4BE and DT4BE to enable A D ERR APA a conversion start requests TRG4AN or TRG4BN request delaying function Use bits BF1 and BF2 in the timer A D converter start request control register TADCR to specify the timing of transfer from kl Notes 1 Perfor
13. m TADCR setting while TCNT_4 is stopped 2 Do not set BF1 to 1 when complementary PWM mode is not selected A D converter start request 3 Do not set ITA3AE ITA4VE ITB3AE ITB4VE DT4AE or delaying function X DT4BE to 1when complementary PWM mode is not selected Figure 11 79 Example of Procedure for Specifying A D Converter Start Request Delaying Function After correction 1 Set the cycle in the timer A D converter start request cycle buffer register TADCOBRA_4 or TADCOBRB_4 and timer A D delaying function converter start request cycle register TADCORA_4 or TADCORB_4 The same initial value must be specified in the cycle buffer register and cycle register A D converter start request cycle buffer register to A D converter start request cycle register e Set the timing of transfer e Specify whether to link with interrupt skipping through bits from cycle set buffer register ITA3AE ITA4VE ITB3AE and ITBAVE e Set linkage with interrupt skipping e Use bits TU4AE DT4AE UT4BE and DT4BE to enable A D ee oe aa conversion start requests TRG4AN or TRG4BN request delaying function Use bits BF 1 0 in the timer A D converter start request control register TADCR to specify the timing of transfer from the timer kl Notes 1 Perform TADCR setting while TCNT_4 is stopped 2 Set BF1 bit to 0 when complementary PWM mode is not selected A D converter start request 3 Set ITA3AE ITAAVE ITB3AE ITBAVE DT4AE or DT
14. pping operation Notes 1 Setto 0 when complementary PWM mode is not selected 2 Clear this bit to O when interrupt skipping is disabled when the T3AEN or T4VEN bit in the timer interrupt skipping set register TITCR is cleared to O or when the skipping count set bit 3ACOR or 4VCOR in TITCR is cleared to O 3 If link with interrupt skipping is enabled while interrupt skipping is disabled A D converter start requests will not be issued Before correction p 508 Table 11 29 Setting of Transfer Timing by Bits BF1 and BFO m me Does not transfer data from the cycle set buffer register to the cycle set register ee ener crest of the TCNT 4 count fs sougnohe ONT dente nee trough of the TCNT_4 count crest and trough of the TCNT 4 count Notes 1 Data is transferred from the cycle set buffer register to the cycle set register when the crest of the TCNT 4 count is reached in complementary PWM mode when compare match occurs between TCNT 3 and TGRA 3 in reset synchronized PWM mode or when compare match occurs between TCNT 4 and TGRA 4 in PWM mode 1 or normal operation mode 2 These settings are prohibited when complementary PWM mode is not selected Re Page 5 of 12 lt ENESAS RENESAS TECHNICAL UPDATE TN SH7 A884A E Date August 22 2014 After correction Table 11 29 Setting of Transfer Timing by BF 1 0 Bits mus mu Description OCSCSC CSCSC CS S C CS S BF1 BFO Complementary PW
15. ransferred from the buffer registers to the respective cycle set registers at the timing selected with the BF1 and BFO bits in the timer A D converter start request control register TADCR 4 After Correction The data in the timer A D converter start request cycle set registers TADCORA 4 and TADCORB 4 is updated by writing data to the timer A D converter start request cycle set buffer registers TADCOBRA 4 and TADCOBRB 4 Data is transferred from the buffer registers to the respective cycle set registers at the timing selected with the BF 1 0 bits in the timer A D converter start request control register TADCR When using buffer transfer in complementary PWM mode exercise care regarding the buffer transfer timing For details see 11 7 24 Notes on Using the A D Converter Start Request Delaying Function in Complementary PWM Mode Also clear the BF1 bit to 0 when not in complementary PWM mode Re Page 9 of 12 lt ENESAS RENESAS TECHNICAL UPDATE TN SH7 A884A E Date August 22 2014 e A D Converter Start Request Delaying Function Linked with Interrupt Skipping Before correction p 616 to 617 A D converter start requests TRG4AN and TRG4BN can be issued in coordination with interrupt skipping by making settings in the ITA3AE ITA4VE ITB3AE and ITB4VE bits in the timer A D converter start request control register TADCR Figure 11 81 shows an example of A D converter start request signal TRG4AN operation when TRG4AN outpu
16. ring TCNT 4 up counting and A D converter start requests are linked with interrupt skipping The A D converter start request delaying function linked to the interrupt skipping function cannot be used when not in complementary PWM mode In this case clear the ITA3AE ITA4VE ITB3AE and ITB4VE bits in TADCR to 0 Note This function must be used in combination with interrupt skipping When interrupt skipping is disabled the T3AEN and T4VEN bits in the timer interrupt skipping set register TITCR are cleared to 0 or the skipping count set bits 3 ACOR and 4VCOR in TITCR are cleared to 0 make sure that A D converter start requests are not linked with interrupt skipping clear the ITA3AE ITA4VE ITB3AE and ITBAVE bits in the timer A D converter start request control register TADCR to 0 Furthermore when this function is to be used set TADCORA 4 and TADCORB 4 to a value between H 0002 and the TCDR setting minus two Re Page 10 of 12 lt ENESAS RENESAS TECHNICAL UPDATE TN SH7 A884A E Date August 22 2014 Addition p 629 11 7 24 Notes on Using the A D Converter Start Request Delaying Function in Complementary PWM Mode When TADCOBRA A TADCOBRB 4 is set to 0 and the UT4AE or UT4BE bit in TADCR is set to 1 and then buffer transfer takes place at the trough of TCNT 4 no A D converter start request occurs during the up counting interval immediately after the transfer figure 11 139 When the value of TADCOBRA 4 TADCOBR
17. t TCNT 42 1 Figure 11 80 Basic Example of A D Converter Start Request Signal TRG4AN Operation Re Page 8 of 12 lt ENESAS RENESAS TECHNICAL UPDATE TN SH7 A884A E Date August 22 2014 Addition p 616 to be added after the section of Basic Operation Example of A D Converter Start Request Delaying Function e A D Converter Start Request Enabled Interval When TCNT 4 and TADCORA 4 TADCORB 4 match during the interval enabled by the UT4AE DT4AE UTABE or DT4BE bit in TADCR a start request is issued for the corresponding A D converter TRG4AN or TRGABN If the UT4AE or UT4BE bit is set to 1 in complementary PWM mode A D converter start requests are enabled during the TCNT 4 up counting interval 0 lt TCNT 4 lt TCDR 1 A D converter start requests are enabled during the TCNT 4 down counting interval TCDR gt TCNT 4 gt 1 if the DTAAE or DT4BE bit is set to 1 figure 11 80 Clear the DT4AE and DT4BE bits to 0 when not in complementary PWM mode Setting the UT4AE or UT4BE bit to 1 causes an A D converter start request to be generated at a compare match between TCNT 4 and TADCORA 4 TADCORB 4 regardless of whether TCNT 4 is counting up or down e Buffer Transfer Before correction p 616 The data in the timer A D converter start request cycle set registers TADCORA 4 and TADCORB 4 is updated by writing data to the timer A D converter start request cycle set buffer registers TADCOBRA 4 and TADCOBRB 4 Data is t
18. t is enabled during TCNT 4 up counting and down counting and A D converter start requests are linked with interrupt skipping Figure 11 82 shows another example of A D converter start request signal TRG4AN operation when TRG4AN output is enabled during TCNT 4 up counting and A D converter start requests are linked with interrupt skipping Note This function must be used in combination with interrupt skipping When interrupt skipping is disabled the T3AEN and TAVEN bits in the timer interrupt skipping set register TITCR are cleared to 0 or the skipping count set bits GACOR and 4VCOR in TITCR are cleared to 0 make sure that A D converter start requests are not linked with interrupt skipping clear the ITA3AE ITA4VE ITB3AE and ITBAVE bits in the timer A D converter start request control register TADCR to 0 After Correction In complementary PWM mode A D converter start requests TRG4AN and TRG4BN can be issued in coordination with interrupt skipping by making settings in the ITA3AE ITAAVE ITB3AE and ITB4VE bits in the timer A D converter start request control register TADCR Figure 11 81 shows an example of A D converter start request signal TRG4AN operation when TRG4AN output is enabled during TCNT 4 up counting and down counting and A D converter start requests are linked with interrupt skipping Figure 11 82 shows another example of A D converter start request signal TRG4AN operation when TRG4AN output is enabled du
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