CML Microcircuits CMX7045L4 Datasheet
Contents
1. Y Wait for ACT flag to go high or interrupt Y Write next data word to C8 Y Wait for ACT flag to go high or interrupt Y Write Start Block 3 Address ACTIVATE ptr to B6 Write Block 3 Length ACTIVATE len to B7 Y Write 0001 to C8 Y Wait for ACT flag to go high or interrupt Y Read and verify checksum values in register pair A9 and AA B8 and B9 Y Send Activation Code hi to C8 Y Wait for ACT flag to go high or interrupt Y Send Activation Code lo to C8 Y Wait for ACT flag to go high or interrupt y CMX7045 is now ready for use Figure 5 Fl Loading from Host CMX7045 2011 CML Microsystems Plc 13 D 7045FI 1 x 1 Marine AIS SART Processor CMX7045 7 4 System Description and Tasks This section describes the operation of main sections of the CMX7045 and the task oriented logical interface provided to the external host device 7 4 1 Signal Routing The Tx Modulation output signals may be configured to be suitable for two point modulation circuits Signal levels on both output pins MOD1 and MOD2 can be set to within 0 2dB using a Configuration Mode task 7 4 2 Operating Modes The CMX7045 operates in either o Deep Sleep Mode o Configuration mode o Normal mode Deep Sleep mode puts the device into a low power standby mode to min2. DataBitWriteN Tx Copy N bits 1 to 15 from Write Data register O to Tx data buffer Increment data buffer pointer DataBitResetN Tx Reset Tx data buffer pointer Copy N bits 1 to 15 from Write Data register O to Txdata buffer e Increment data buffer pointer DAC Write Interprets each of the first 1 to 4 words in the Write Data registers as a write command for the Auxiliary DACs 7 5 5 Modem Tasks and Codes Modem tasks transmit data on the MOD1 and MOD2 output pins Modem tasks also coordinate data transfer between the Data Buffer and the modem Note that for receive tasks a 1 or 2 at the end of the task name refers to the Rx channel which is being addressed Table 4 Modem Tasks Name Description NULL No command takes no action AbortTx ECM Enter Configuration mode Tx Tasks Tx Raw bit 0 Tx Raw bit 7 1 TXB Code and transmit AIS message using contents TDBS Transmit contents of data buffer Start on of data buffer Start on next SLOTCLK next SLOTCLK TDB Transmit N data bits from the Tx mod buffer Start as soon as modulator is free PRBS Transmit pseudorandom bit sequence TRW Repeatedly transmit one word HCT Hardware Control 7 6 Transmission Format The CMX7045 is capable of transmitting AIS data in either raw mode or burst mode In AIS raw mode data is passed directly from the Tx Data Buffer to the GMSK modulator so the uC will be responsible for s
3. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register A7 Data write from host uC to device word 1 MSB sent first Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register A8 Data write from host uC to device word 2 MSB sent first Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register B6 Data write from host uC to device word 3 MSB sent first Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register B7 Data write from host uC to device word 4 MSB sent first Bit format Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register A7 Data write from host uC to device bits 0 15 bit 15 transmitted first 7 5 4 Data Tasks Data tasks are used to e Load data from the Write Data registers into Data Buffers while in normal or configuration modes e Load data from the Data Buffers to the DACs e Write or operate subsystems by passing data using the Write Data registers 2011 CML Microsystems Plc 17 D 7045FI 1 x 1 Marine AIS SART Processor CMX7045 Table 3 Data Tasks Name Description NULL Null system task takes no action DataWordResetN Tx e Reset Tx data buffer pointer e Copy N words 1 to 4 from Write Data registers to Tx data buffer e Increment the data buffer pointer DataBitReadN Rx1 e Copy N bits 1 to 15 from Rx1 data buffer to Read Data register 0 e Increment the data buffer pointer DataBitReadN Rx2 e Copy N bits 1 to 15 from Rx2 data buffer to Read Data register 0 e Increment data buffer pointer
4. 25kHz channel Bit rate accuracy BT Storage time filter delay Tx Buffer size SLOT CLOCK Rise Fall time Notes 30 Min Typ 0 4 CMX7045 Unit ppm bits bytes Us Notes 30 Through a GMSK GFSK transmit filter 2011 CML Microsystems Plc 31 D 7045FI 1 x 1 Marine AIS SART Processor CMX7045 8 2 C BUS Timing If 1 byte of data If 2 bytes of data CSN tese HD tc gt tur gt losa n tesorr i tesu gt tesorr sek gt INNNNNNNO NONE 1 HUNT ED CDATA 7 6 5 4 3 2 1 0 A AE sve 7 6 5 4 3 2 1 0 tioz gt ee taz gt a taz RDATA Hi 7 6 514 3 2 1 0 7 6 5 4 3 2 1 0 Level not important or undefined toy tex 70 Vdd N SCLK 30 Vdd to tops t teos RDH teon CDATA RDATA Figure 10 C BUS Timing C BUS Timing Notes Min Typ Max Unit tese CSN enable to SCLK high time 100 ns tcsu Last SCLK high to CSN high time 100 ns tLoz SCLK low to RDATA output enable time 0 0 ns tuiz CSN high to RDATA high impedance 1 0 us tesorr CSN high time between transactions 1 0 us tnxt Inter byte time 200 ns tek SCLK cycle time 200 ns tcu SCLK high time 100 ns teL SCLK low time 100 ns teps CDATA se
5. 1 The IRQN pin is an open collector output that requires an external pull up resistor 1 If the host supplies a 0 5Hz signal this should be aligned to the even UTC second and the selection of X1 should be chosen to maintain correct timing between SLOTCLK pulses 2011 CML Microsystems Plc 15 D 7045FI 1 x 1 Marine AIS SART Processor CMX7045 7 4 9 Deep Sleep Mode Deep Sleep mode entered through Configuration mode or after the activation codes have been successfully loaded puts the device into static state where all signal processing and clocks are stopped and only the C BUS remains active In this mode the Ipp drops to the lowest level as specified in section 8 1 3 and is thus suitable for use in AIS SART where it is feasible for the host uC to switch off the CMX7045 at known times See User Manual section 9 12 6 7 5 Operation of Tasks This section describes modem and data tasks Understanding their operation requires knowledge of the internal buffering of the CMX7045 Tx data is double buffered Each Tx channel has a Data Buffer The host uC accesses the C BUS registers and the modulator demodulator directly accesses the Data Buffers Tasks transfer data between the buffers and the C BUS registers 7 5 1 Tx Task Operation Typical stages of Tx task operation are depicted in Figure 7 and occur as follows 1 The host writes up to 4 words of data for transmission into the Write Data C BUS registers 2 The host writes the C
6. 3 D 7045FI 1 x 1 Marine AIS SART Processor 2 Block Diagram Transmit Functions HDLC Encode GMSK Modulation Auxiliary 10 bit DACs Ramp Profile RAM DAC1 DAC 1 DAC2 DAC2 DAC3 DAC 3 DAC4 DAC 4 Multiplexed 10 bit ADC ADC1 ADC2 System Control AVDD VBIAS AVSS DVDD VDEC DVSS Auxiliary Functions Configurable GPIO Programmable System Clocks System Clock 1 System Clock 2 Main Clock Digital PLL Crystal Oscillator Registers Power Control C BUS Interface Internal Systems Control Figure 1 Block Diagram CMX7045 MOD1 MOD2 TXENA SLOTCLK CS SYNC SLTCLKOP SYSCLK1 SYSCLK2 XTAL CLK XTALN IRQN RDATA CSN CDATA SCLK 2011 CML Microsystems Plc D 7045FI 1 x 1 Marine AIS SART Processor CMX7045 3 Signal Pin List CMX7045 Pin u P reserved do not connect reserved do not connect reserved do not connect reserved do not connect Connect to DVpp Connect to DVpp Oo oO fF WO ND a I Digital Ground C BUS A wire ORable output for connection to the Interrupt Request input of the host Pulled down to DVss when active and is high impedance when inactive An external pull up resistor R1 is requir
7. Clock Figure 9 System Clock Generation 2011 CML Microsystems Plc 24 D 7045FI 1 x 1 Marine AIS SART Processor CMX7045 The CMX7045 includes a two pin crystal oscillator circuit This can either be configured as a 9 6MHz xtal oscillator or the XTAL CLK input can be driven by an externally generated 19 2MHz clock Note that at power on the CMX7045 will inhibit both outputs are until they are enabled by a host command over the C BUS 7 9 Powersave The CMX7045 implements a comprehensive powersaving scheme which will automatically enable the sections of the device that are required and return them to their powersaved state when no longer needed A Deep Sleep mode is also available through the Configuration mode which halts all signal processing activity and allows the analogue functions to be disabled so reducing power consumption to the lowest level see section 7 4 9 This mode is entered automatically following successful activation of the device 2011 CML Microsystems Plc 25 D 7045FI 1 x 1 Marine AIS SART Processor CMX7045 7 10 C BUS Register Summary Table 10 C BUS Registers ADDR Word Size hex REGISTER bits 01 W w CBUSREET 0 o AAA GG lt A A _ _ __ 2222 a9 R jCheksum2hi 1 1 1 1 1 16 SAA R jCheksm2l 2360 k SAD 16 AE 16 SAF reserved BO reserved B1 Input Output Gain and Routing 16 reserved
8. SYSCLK2 are available to drive additional circuits as required These are phase locked loop PLL clocks that can be programmed via the System Clock registers with suitable values chosen by the user The System Clock PLL Configuration registers 5AB and AD control the values of the VCO Output divider and Main Divide registers while the System Clock Ref Configuration registers SAC and AE control the values of the Reference Divider and signal routing configurations The PLLs are designed for a reference frequency of 96kHz The System Clock output divider stages are designed so that they have a 1 1 Mark to Space ratio when an even divide number is selected to RF Synthesiser p M N Ref CLK selection SysCLK1 VCO gt LPF VCO 24 576 98 304MHz 49 152MHz typ Ref CLK div PLL div ey 1to512 1to 1024 4 e AC b0 8 AB b0 9 Ref 4s 192k DW 96kHz typ VCO op div re 1 to 64 e SysCLK1 AB b10 15 SysCLK1 Pre CLK Output AC b11 15 384kHz 50MHz SysCLK2 VCO LPF VCO 24 576 98 304MHz 49 152MHz typ Ref CLK div PLL div oy 1110512 PD 1to 1024 4 o AE b0 8 SysCLK2 SysCLK2 AD b0 9 Ref 4s 192K DY 96kHz typ VCO op div PER Mtoe4 gt 4 ee SysCLK2 AD b10 15 SysCLK2 Pre CLK Output AEb11 15 384kHz 50MHz OSC 9 6MHz Xtal or MainCLK 19 2MHZ
9. Table 7 the order of events and delay timings shown are for illustrative purposes only 2011 CML Microsystems Plc 21 D 7045FI 1 x 1 Marine AIS SART Processor CMX7045 Table 7 Example Tx Event Sequence Setup mw o o o omma O Start feeding data to the transmit modulator and filters this allows for the 20 tick storage delay in the Tx filters so that modulated data appears at the end of the RAMDAC ramp up period tick 57 my o TA C eenn 3 o CN ECT RAMDAC UP 4 3 4 Insert 3 tick delay then initiate the RAMDAC ramp up for AIS the m transmitted signal will be carrier only at this point At this point during a transmission the CMX7045 feeds the entire message to the transmit modulator bit by bit All subsequent transmit events are timed relative to the end of the last message bit indicated by the MODULATE END event RAMDAC DOWN 7 2 o _ Initiate the RAMDAC ramp down immediately MODULATE START Tx endo 7 Insert 7 tick delay to allow RAMDAC to fully ramp down then set rtu the TXENA line low MODULATE END 6 5 14 Allows for process delays Notes 1 MODULATE START must appear in the first group of timed events table entries 1 5 MODULATE END must appear in the final group table entries 6 8 2 Itis feasible to place the RAMDAC DOWN task before the MODULATE END task if it is desired to continue modulation during the Ramp down period Assuming that the timing start va
10. uC to issue a AbortTx task e Tx Aborted buffer not ready This occurs in burst mode if the internal data coding has not completed before the timing_start value expires 2011 CML Microsystems Plc 19 D 7045FI 1 x 1 Marine AIS SART Processor CMX7045 7 6 8 Transmit Example The following detailed example describes the process of loading and transmitting an AIS message in Burst mode Table 5 AIS Burst Transmit Example Description Cmd Data TBFREE TxDONE Reg Task Free 1 The host should ensure that the TBFREE Data Task and 1 1 1 1 CmdReg Free bits are set 2 The host loads the first N typically 4 data words into the write data 1 1 1 1 registers 3 The host issues a DataWordResetN Tx Data Task 0 1 1 1 4 Device reads the Command register amp notes task types 1 0 1 1 5 Device carries out the data task by copying the N data words as 1 1 1 1 the first N data words of the data buffer 6 The steps above may be repeated Using DataWordWriteN Tx tasks to load many words until the data buffer contains enough data to carry out the desired modem task 7 The host writes a TXB task to the Command register to start the 0 1 1 1 Tx process 8 Device reads the Command register 1 1 1 9 Device codes the data Tx state changes from Idle to Tx Pending 1 1 1 0 10 When the transmit point arrives SLOTCLK the Tx State changes to Tx in progress and the TxSequence is activate
11. 045 4 Recommended External Components DVop C20 C21 C22 C1 DVss EX C2 DVss C3 x lt lt 9 zig x2 2 alel g 8lojeaja 2 e 8 a x kl Sl a La NC i 48 47 46 45 44 43 42 41 40 39 38 37 AUXDAC4 DVop Nc f AUXDAC3 pI ba nc_ AVSS i i NC 4 AUXDAC2 5 AUXDAC1 AVss AVop LC CMX704503 Ape DVSS 7 AUXADC2 C17 C18 C19 DVss IRON AUXADC1 VDEC 9 NC AV c24 c2s SLOTCLK 49 NC CS SYNC NC DVss SLTCLKOP VBIAS cx 9 lt ol ololololo 9 A a I 3 3 d 222222 z Q e En gt E Cs DVss AVss R4 AVss E CS AVss Figure 2 Recommended External Components Table 2 Component Values R1 100kQ C2 18pF C17 10uF C22 10nF R2 220kO C3 10nF C18 10nF C23 10nF R3 100kQ C7 100nF C19 10nF C24 10uF RA 100kQ C8 100pF C20 10uF X1 9 6MHz C1 18pF C9 100pF C21 10nF See note 1 Resistors 5 capacitors and inductors 20 unless otherwise stated Notes 1 X1 can be a 9 6MHz crystal or a 19 2MHz external clock generator The tracks between the crystal and the device pins should be as short as possible to achieve maximum stability and best start up performance 2 A single 10uF electrolytic capacitor C24 fitted as shown may be used for smoothing the power supply to both VDEC pins providing they are connected together on the pcb with an adequate width power supply trace Alternatively separate smoothing capacitors should be connected to each VDEC pin High frequency decoupling capacitors C3 and C23 must always be fitted as close as possibl
12. CML Microcircuits C MX7045 COMMUNICATION semiconDucrors AIS SART Processor D 7045Fl 1 x 1 October 2011 DATAS HEET Advance Information 7045FI 1 x Marine AIS SART Processor Features e Tx AIS GMSK Modem e Conforms to IEC 61097 14 e AIS SART Formatted Data e Integration Roadmap e Battery Monitor e Low Power 3 0V to 3 6V Operation e Flexible Tx Interface e Low Profile 48 pin LQFP or VQFN e Configurable by Function Image e Two Auxiliary Clock Generators Applications e Two Input Auxiliary 10 bit ADC e Automatic Identification System AIS e Four Auxiliary 10 bit DACs Search And Rescue SART for Marine Safety Low Power PLL e RTC 3 3V 4 GPS vco ES yo Switched T E la PA Ramp mode PSU CMX7045 Monitor M Battery md SART Processor SART Test p Y This document contains SART Acti pcEnable Datasheet GPS Lock Slot Clock Strobe 1 Brief Description The CMX7045 is a dedicated processor for marine Automatic Identification System AIS Search and Rescue Transmitter SART operation fully meeting the requirements of IEC 61097 14 This highly integrated and flexible device includes a 9600 baud GMSK modem for transmission of formatted data Additional auxiliary functions are also provided to further support the system host these include a two input 10 bit ADC four 10 bit DACs two system clock
13. Exposed q Angles are in degrees C 5 Metal Pad G d Index Area 1 Index Area 2 H Ee mr T Br 3L i i f n gt BLA qi a E BR Ene l anan nannnar E gt Bottom View A s A Dot i Dot Chamfer Index Area 2 Index Area 1 is located directly above Index Area 2 Depending on the method of lead termination at the edge of the package pull back L1 may be present L minus L1 to be equal to or greater than 0 3mm The underside of the package has an exposed metal pad which should ideally be soldered to the pcb to enhance the thermal conductivity and mechanical strength of the package fixing Where advised an electrical connection to this metal pad may also be required Figure 11 Mechanical Outline for 48 pad VQFN Package Q3 Order as CMX7045Q3 h D i IDENT C En lt gt PIN 1 A PEEE 3 A DIM MIN TYP MAX o 4 A 6 91 741 ul B 6 91 7 11 C 1 40 1 60 B E D 8 74 9 25 4 H E 8 74 9 25 J H 0 05 0 15 T J 0 10 0 28 E L 0 35 0 76 Y P 0 50 T 0 13 X o 7 Y 44 13 NOTE Y A amp B are reference data and do not include mold deflash or protrusions All dimensions in mm Angles are in degrees Co Planarity of leads within 0 1mm SES xe Figure 12 Mechanical Outline for 48 pin LQFP Package L4 Order as CMX7045L4 2011 CML Microsystems Plc 33 D 7045FI 1 x 1 Marine AIS SART Processor CMX7045 7 FITmASIC CML s proprietary FirmASIC component technology reduces cost time to marke
14. US register C5 2 the Fl version code is reported in C BUS register C9 3 the two 32 bit FI checksums are reported in C BUS register pairs A9 AA and B8 B9 4 the device waits for the host to load the 32 bit Device Activation Code to C BUS register C8 5 once activated the device initialises fully enters Deep Sleep mode mode and becomes ready for use and the Activation Register Ready ACT flag bit O of the Status register will be set 6 Once the Deep Sleep bit Status2 b 13 has been set the host may then power down the Analogue sections of the device to minimise power consumption typically while the host is waiting for the external GPS to output a valid position fix 7 When the host decides that the device should be returned to active mode in order to configure the device or transmit an AIS burst it should first power up the Analogue sections and then send the exit Deep Sleep command The checksums should be verified against the published values to ensure that the Fl has loaded correctly Once the Fl has been activated the checksum product identification and version code registers are cleared and these values are no longer available If an invalid activation code is loaded the device will report the value DEAD in register A9 and become unresponsive to all further host commands including General Reset A power on reset is required to recover from this state Both the Device Activation Code and the checksum values a
15. al RF transmit circuits is performed using the TXENA pin and the DAC1 ramping function RF Power si OTCLK SLOTCLK 100 d Modulation gt Ip Time Figure 8 Typical AIS Transmission 2011 CML Microsystems Plc 20 D 7045FI 1 x 1 Marine AIS SART Processor CMX7045 A typical AIS transmission is shown in Figure 8 The CMX7045 starts timing relative to the rising edge of SLOTCLK At the end of a transmission a sequence of power down actions is performed which are timed relative to the last message bit having been modulated shown as point B in Figure 8 In this way differences in message length due to bit stuffing are automatically accommodated The relative timings of the transmit sequence events are configured as a table of values that are loaded into the CMX7045 using a Config Task operation User Manual section 9 12 3 this operation must be performed before any transmissions are attempted Typically this will only need to be done once as part of an initialization routine All timings are measured in units of ticks each of which lasts for 1 24000Hz 41 666ps The transmit sequence consists of two initial setting values followed by a number of different event types These are e Initial delay from the SLOTCLK edge e Initial state of the TXENA pin e Changes to the external hardware via the TXENA pin typically used to turn the Tx on off and the DAC1 ramp up down e Timing triggers for the
16. ance Clock frequency Clock stability accuracy Clock start up from powersave Veras Start up time from powersave Modulator Outputs MOD 1 MOD 2 Power up to output stable 21 Modulator Attenuators Attenuation at OdB 23 Cumulative attenuation error wrt attenuation at OdB J Output impedance Enabled 22 Disabled 22 Output current range AVpp 3 3V Output voltage range 24 Load resistance ADC 1 and 2 Inputs Source output impedance 25 ADC Resolution Input Range Conversion time Input impedance Resistance Capacitance Zero error input offset to give ADC output 0 J Integral non linearity Differential non linearity 27 DACs Resolution Settling time to 0 5 LSB Output range 26 Integral non linearity Differential non linearity 27 Resistive load Noise output voltage in 30kHz bandwidth Min 19 19 1 0 0 6 125 0 5 20 oO Typ 150 20 300 19 2 20 30 50 600 500 Max 100 1 0 0 6 125 CMX7045 Unit ns ns kQ pF kQ pF MHz ppm ms ms us dB dB Q kQ yA AVpp 0 5 V 24 10 to 90 10 4 3 10 to 90 4 1 KQ kQ Bits 96AV pp us MO pF mV LSB LSB Bits us 96AV pp LSB LSB kQ uVrms 2011 CML Microsystems Plc 29 D 7045FI 1 x 1 Marine AIS SART Processor CMX7045 20 21 22 23 24 25 26 27 Tamb 25 C not including any current drawn from the device pins by external circuitry Charac
17. ansaction oriented command response protocol with addressing to access specific registers within the CMX7045 Each C BUS transaction consists of a single Register Address Command byte A C byte sent from the uC which may be followed by one or more data byte s sent from the uC to be written into one of the CMX7045 s Write Only registers or one or more data byte s read out from one of the CMX7045 s Read Only registers as illustrated in Figure 4 Data sent from the uC on the CDATA line is clocked into the CMX7045 on the rising edge of the SCLK input RDATA sent from the CMX7045 to the uC is valid when the SCLK is high The CSN line must be held low during a data transfer and kept high between transfers The C BUS interface is compatible with most common pC serial interfaces and may also be easily implemented with general purpose uC I O pins controlled by a simple software routine The number of data bytes following an A C byte is dependent on the value of the A C byte The most significant bit of the address or data is sent first For detailed timings see section 8 2 C BUS Write See Note 1 See Note 2 CSN SCLK ARE NINE PAE os CDATA 7 6 5 4 3 2 1 0 7 6 0 7 0 MSB LSB MSB LSB MSB LSB Addr
18. d 11 The Tx Modem Buffer will gradually empty as the Tx Modulator 1 1 1 1 continues transmitting 12 When the transmission ends the TxDone bit in the Status register 1 1 1 1 will be set generating an interrupt if enabled The host should then check the Tx state bits in the Status2 register to see if transmission was successful 7 6 4 AIS Raw Mode Transmit In AIS raw mode transmit data is passed directly from the Tx Data Buffer to the GMSK modulator The uC must calculate the entire transmitted message including the training sequence HDLC processing start stop flags bit stuffing and CRC insertion and NRZI coding Note In AIS raw mode data words written to the CMX7045 are transmitted most significant bit first The AIS message structure however requires each message byte to be output least significant bit first The uC must therefore ensure that during the process of HDLC processing and NRZI coding that the resulting data bytes are correctly reversed 7 6 5 Transmitter Timing Control The CMX7045 can be configured to control the timing of transmission events whenever a Tx Burst Modem task is executed This includes the enabling of external RF circuits e g synthesisers and power amplifier as well as the time at which internal data modulation begins The flexibility of this timing control allows the CMX7045 to be simply adapted to the characteristics of the RF transmit circuits The control of the extern
19. e to both VDEC pins 2011 CML Microsystems Plc D 7045FI 1 x 1 Marine AIS SART Processor CMX7045 5 PCB Layout Guidelines and Power Supply Decoupling Notes Digital Ground Plane 48 47 46 45 44 43 42 41 40 39 38 377 J 36 CMX7045Q3 25 16 17 18 19 20 21 22 23 24 AVss AVpp oO o Oo OC R Q M E o s AVss Analogue Ground Plane Figure 3 Power Supply Connections and De coupling Component values as per Table 2 The supply decoupling capacitors should be as close as possible to the CMX7045 It is therefore recommended that the printed circuit board is laid out with separate ground planes for the AVss and DVss supplies in the area of the CMX7045 with provision to make links between them close to the CMX7045 Use of a multi layer printed circuit board will facilitate the provision of ground planes on separate layers The central metal pad on the Q3 package may be electrically unconnected or alternatively may be connected to Analogue Ground AVss No other electrical connection is permitted Vias is used as an internal reference for detecting and generating the various analogue signals It must be carefully decoupled to ensure its integrity so apart from the decoupling capacitor shown no other loads should be connected If Vpias needs to be used to set the discriminator mid point reference it must be buffered with an external high input impedance buffer 2011 CML Microsystems P
20. ed Internally generated 2 5V digital supply voltage Must be 9 VDEC PWR decoupled to DVss by capacitors mounted close to the 8 IRQN device pins No other connections allowed 15 TXENA O Enable for external Tx hardware reserved do not connect 10 SLOTCLK 11 CS SYNC 16 z B Internally generated bias voltage of about AVpp 2 except when the device is in Powersave mode when VplJAS will NC 25 VBIAS discharge to AVss Must be decoupled to AVss by a capacitor mounted close to the device pins No other connections allowed P NC NC NC NC NC NC NC 26 reserved do not connect this pin 2011 CML Microsystems Plc 5 D 7045FI 1 x 1 Marine AIS SART Processor CMX7045 pang ao Type Description 27 NC j reserved do not connect 28 NC j reserved do not connect 29 ADC1 IP ADC input 1 30 ADC2 IP ADC input 2 Analogue 3 3V supply rail Levels and thresholds within ite clc m close to the device pins 32 DAC1 OP Aux DAC output 1 RAMDAC 33 DAC2 OP Aux DAC output 2 34 AVSS PWR Analogue Ground 35 DAC3 OP Aux DAC output 3 36 DAC4 OP Aux DAC output 4 37 DVSS PWR Digital Ground Internally generated 2 5V supply voltage Must be 38 VDEC PWR decoupled to DVss by capacitors mounted close to the device pins 39 XTAL CLK IP Vile input from the external clock source or 9 6MHz 40 XTALN OP bsc pissed bcd Hz Xtal o
21. ending any necessary training sequences and performing HDLC processing and NRZI coding In AIS burst mode the CMX7045 uses an internal message buffer to assemble an entire message up to 5 slots to which it automatically adds the training sequence start stop flags CRC bit stuffing and NRZI coding prior to transmission After setting up the appropriate registers transmission is initiated by issuing a Tx Burst or Tx Raw task 2011 CML Microsystems Plc 18 D 7045FI 1 x 1 Marine AIS SART Processor CMX7045 7 6 1 Transmit Tasks e AbortTx This causes the current task on the Tx channel to abort It also clears the Tx modem buffer e TXB Transmit AIS Burst This task can only be executed if the Tx Raw bit bit 5 in the command register is cleared to 0 This causes the CMX7045 to take the contents of the Tx Data buffer apply AIS data coding and transmit the resulting AIS message The transmit sequence will start on the next SLOTCLK edge The following five transmit tasks can only be executed if the Tx Raw bit is set to 1 e TDBS Transmit Data Buffer on SLOTCLK This causes the CMX7045 to transmit the data buffer contents using AIS modulation No data coding is applied the Transmit Sequence will start on the next SLOTCLK edge at which point the CS SYNC output will become active e TDB Transmit Data Buffer This causes the CMX7045 to transmit the data buffer contents using AIS modulation No data coding is applied The data will be t
22. ennen 22 7 7 Configuration Tasks and Codes ssssssssssssseeenenen nenne eene nennt nens 23 7 8 System Clock Synthesisers csar a a a alae ai A a a a a daa 24 EN CV aeaee aner ds A AA A AE AA ib aa ae Aa 25 7 10 C BUS Register SUMMAN aree r E AATA ATEREA AES 26 8 Performance Specification coomonooncnnecnnnnnnosnccnnncnnnnnnnanncnnn nc nn sees eeaeeeseseee sens nene nn amandae nette sensns 27 9 1 Electrical Performance ico Det eh nte cto ats e ehe lacs 27 8 1 1 Absolute Maximum Ratings oooonnncccnnnnccccnnnocccnnnnonccononorc cnn nc nen een eren 27 8 1 2 Operatirig Eimits 1 icc ttm itc cox it che eie itcr byte t aiit a doct dee 27 8 1 3 Operating Characteristics eese eensesee entree ntn sene ntn 28 2011 CML Microsystems Plc 2 D 7045FI 1 x 1 Marine AIS SART Processor CMX7045 8 1 4 Parametric Performance eese esese Seea nennen tete kennt nk hse tena nana ska antenas 31 8 20 CP BUS MM e EP 32 9 37 Packaglig il io pO te b pta De er n ea o d 33 TABLES Table 1 Definition of Power Supply and Reference Voltages oooononcccconnnicccnnocicccononnncnnnancnc cano eene 7 EAS NA 8 Table 3 Data Task Si A miim 18 Table 4 Modem Tasks uri ito ee india EL 18 Table 5 AIS Burst Transmit Example sss nennen ner ern ninh en nennrer nnne n nnne 20 Table 6 Tx Sequence events oocococccccocccococononccccnnncnn non RRE RR RR RR s ss nn sn nennen tein sinn n
23. ess Command byte Upper 8 bits Lower 8 bits RDATA High Z state C BUS Read See Note 2 po gt CSN SCLK NEC al PSA uo ma CDATA 7 6 5 4 3 2 1 0 MSB LSB Address byte Upper 8 bits Lower 8 bits RDATA 7 6 0 7 0 m High Z state MSB LSB MSB LSB Data value unimportant Repeated cycles Either logic level valid Figure 4 C BUS Transactions Notes 1 For Command byte transfers only the first 8 bits are transferred 2 Forsingle byte data transfers only the first 8 bits of the data are transferred 3 The CDATA and RDATA lines are never active at the same time The Address byte determines the data direction for each C BUS transfer 4 The SCLK input can be high or low at the start and end of each C BUS transaction 5 The gaps shown between each byte on the CDATA and RDATA lines in the above diagram are optional the host may insert gaps or concatenate the data as required 2011 CML Microsystems Plc 11 D 7045FI 1 x 1 Marine AIS SART Processor CMX7045 7 3 Function Image Load and Activation The Function Image FI file which defines the operational capabilities of the device may be obtained from the CML Technical Portal following registration This is in the form of a C header file which can be included into the host controller software The Function Image data file is no more than 24kbytes Once the Fl has been loaded the CMX7045 performs these actions 1 the product identification code 7045 is reported in C B
24. events when a TXB or TDBS task transmit burst is issued The events are start and end of modulation ramping the RAMDAC up and down asserting and releasing a digital output pin intended as a Tx Enable and CSTDMA sensing Each of these can be configured to happen with specified delays from the rising edge of the SLOTCLK The timings are set up with the Config Mode task Tx_Sequence See User Manual section 9 12 3 for details Tx Timing PA Ramp amp Modulation Tx Enable Figure 6 Tx Burst Timing 7 4 6 ADC The ADC is available for user defined functions The ADC runs continuously the input is selected by the ADC Input Select bits in the C BUS Mode register C1 and the results of the conversion are presented in ADC Data C BUS register C9 This register also includes a bit field to indicate which input was selected when this conversion was executed 7 4 7 DACs The four DACs can be updated in any combination using the DAC_Write data task See User Manual 9 12 In addition DAC1 can be configured as a RAMDAC to output a series of values as part of the transmit timing sequence The values and the rate at which they change are set up using a Config mode task 7 4 8 Interrupt Operation The CMX7045 will issue an interrupt on the IRQN line when the IRQ bit bit 15 of the Status register and the IRQ Mask bit bit 15 are both set to 1 User Manual section 9 14 describes the situations which cause the IRQ bit to change from a 0 to a
25. g decre ete a necu ee d pe d n e 14 7 4 2 Operating Modes eee eee ede cet pne n ee uu ue dpa d npe a 14 7 4 3 Modem and Data rits n eto eerte Pr elite dede Picea edens 14 7 4 4 Timing arid SynchronisatlOni is iienaa ra AERE o Edge teda 15 7 4 5 O 15 7 4 6 ADC astas linia 15 7 4 7 DAGS OE 15 7 4 8 Interrupt Operati Me dab eee te iet fee tede xb Ludi bri fabae te dena 15 7 4 9 De p Sleep Mode 2 getan hen egent ede bu tb e boli edens 16 1 5 Operation of Tasks ueste e eta tbe i ee o iot oe oid edens 16 7 5 1 TX TASK Operation a 2 ipe eed iet ebd Moto delata dirt fabulae fe eben 16 7 5 2 Registers and Buffers for Tx Tasks ssssssssssssse eene eene 17 7 5 3 Write Data R6egisters n to ite edge t heo Erbe beret bio DeL pee ett 17 7 5 4 Data asks iet ob eto ttt ieiunare lp bo elite dene 17 7 5 5 Modem Tasks and Codes sss eene nere nnne 18 TO TransmissiOnFOrrlat oreet te eee eed eee EARTH TRE RT uate Rd dP eu di 18 7 6 1 Transmit Tasks duet ts ou d e dat hu n o ener daa 19 7 6 2 AIS Burst Mode Transmitir oea aa aeaaaee a aaia ener nene 19 7 6 3 Transmit Exatmple 22 e it e aet hue laa eder can 20 7 6 4 NDS enne enne 20 7 6 5 Transmitter Timing Control sssssssssesseeene eene enne nennen 20 7 6 6 Modulation Formats sssssssssssssssssseenenen eene ennt nennen nennen n
26. imize power consumption Whilst in this mode the host can switch off un needed analogue functionality Once the device has been activated it will enter deep sleep mode automatically Configuration mode is used to set up various operating parameters of the CMX7045 subsystems e g Transmit format timing parameters etc following a power up or reset The modem section is disabled when the device is in Configuration mode Configuration mode uses dedicated tasks that are not valid whilst in Normal mode Normal mode is used when actively running the CMX7045 modem and other subsystems Normal mode uses dedicated tasks that are not valid whilst in Configuration mode Enter Config Mode ECM is a Normal mode task that switches the device from Normal to Configuration mode Exit Config Mode EXIT CONFIG is a Configuration mode task that switches the device from Configuration to Normal mode 7 4 3 Modem and Data Units The CMX7045 is logically divided into two main units which can accept and perform tasks separately o Modem Unit o Data Unit The Modem Unit is primarily responsible for processing Tx data from the internal Tx data buffer presenting it on the MOD1 and MODZ2 pins The Data Unit is primarily responsible for transferring data between the internal data buffers or subsystems and the C BUS registers from where they can be accessed by the host uC When the device is in Normal mode the Command register C8 is a 16 bit C BUS write regi
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28. lc 9 D 7045FI 1 x 1 Marine AIS SART Processor CMX7045 6 General Description 6 1 Overview Tx Modem Functions e AIS 25kHz channel GMSK 9600bps 2 4kHz deviation BT 0 4 e AIS Burst mode with full AIS frame formatting HDLC type o Bit stuffing o NRZI coding o Training sequence and start stop flag insertion o CRC generation e AIS Raw mode for greater flexibility o Supports arbitrary data streams for user defined protocols e 160 byte equivalent to 5 AIS slots Tx data buffer e Flexible Tx Interface o Two point modulation outputs with independent gain and polarity controls Analogue I O Functions e Auxiliary ADC system o Atwo input 10 bit successive approximation ADC with integrated sample and hold e Auxiliary DAC system o Four general purpose auxiliary 10 bit DACs e Ramping auxiliary DAC using DAC 1 o DAC steps through a user configured sequence of DAC output values to develop a specific rising falling DAC output signal This is useful for ramping an RF PA and can be configured to operate automatically at the start and end of a burst System Functions e All internal subsystems are controlled via a single serial host interface to reduce host uC pin count and simplify external host driver complexity e Transaction oriented command response logical host interface executes tasks supporting normal operation device configuration and functions to assist manufacturing calibration trimming of external circuits e Internal sys
29. lue has been set to 0 see User Manual section 9 12 3 and the RAMDAC is set to its default values 312us this sequence approximates to the SART timing with ideal hardware RAMDAC starts 5bits 12 ticks after SLOTCLK 7 6 6 Modulation Formats The CMX7045 can be configured to drive either a two point VCO and Reference modulator Typical Tx spectrum plots for both modes are shown below generated by modulating a signal generator with the outputs of MOD1 and MOD2 and then analysing the signal on a spectrum analyser Note that these plots represent the steady state transmission and so are shown with the Class A and Class B SOTDMA spectrum mask 70dBc The Class B CSTDMA standard specifies a slotted transmission with a mask at 60dBc 2011 CML Microsystems Plc 22 D 7045FI 1 x 1 Marine AIS SART Processor CMX7045 Table 8 Tx Spectrum Masks M 1 Ti RB 1 kH RF Att 10 dB RBW 1 kHz RF Att O iB o JE E zm m pen m gt la m 1 Q Tx spectrum mask Two point Tx spectrum mask o y E E E E a 1vixw asa aves asa 2MAX 25A 2vIEwW 25A m aroba aalen er 161 975 MHz 50 kHz Span 500 kHz 161 975 MHz 50 kHz Span 500 kHz 1 Q wideband spectrum Two poi
30. ne 21 Table 7 Example Tx Event Sequence Setup sssssssssssssssssssseenenee eene nne tnnt 22 Tabl 8 Toc Spectrum Masks 5 nce de vete D bi 23 Table 9 Configuration Tasks intr gehe et ddr 24 Table 10 C BUS Registers iuc dt dae ne dif eaae Deva ase ei de ead uaa e Data dva 26 FIGURES Figure 1 Block Biagram 2 5 eee e et etnia temet epe e etii eee 4 Figure 2 Recommended External Components sse nnnm nnns 8 Figure 3 Power Supply Connections and De coupling eseeeeenm eme 9 Figure 4 C BUS Transactions ecciesie da ne v n de 11 Figure 5 El Eoadirig from HOSL 5 iio da 13 Figure 6 Tx B rst Timing e eto da Cete RU PRA ure patena AS 15 Figure 7 Ix Task Operation ioi a UR 16 Figure 8 Typical AIS Transmission G a e a eene me a n nennen nennen aS 20 Figure 9 System Clock Generation sssssssssssesseeeeneenen nennen ener ennt nennen 24 Figure 10 C BUS Timing s 1o dre iet A te Oe Cete eie e nene ti dte bed 32 Figure 11 Mechanical Outline for 48 pad VQFN Package Q3 seem 33 Figure 12 Mechanical Outline for 48 pin LQFP Package L4 sese 33 It is always recommended that you check for the latest product datasheet version from the Datasheets page of the CML website www cmlmicro com 1 1 History Version Changes Date 1 Initial release Oct 2011 2011 CML Microsystems Plc
31. nt wideband spectrum Lower trace shows un modulated signal generator 7 7 Configuration Tasks and Codes The device executes Configuration Tasks while in configuration mode See section 7 4 2 for a description of device operating modes and how to change between them and User Manual section 9 12 for more details on a particular task subsystems These tasks and their data are used to configure device Data required for the Configuration Task is loaded into the device using a Data Task which can be executed at the same time as the Configuration Task if it requires less than four words 2011 CML Microsystems Plc 23 D 7045FI 1 x 1 Marine AIS SART Processor Table 9 Configuration Tasks CMX7045 Configuration Task Words Description User Manual section NULL 0 Do nothing EXIT CONFIG 0 Return to Normal mode Tx I Q or 2 point 1 Sets MOD1 and MOD2 output format 2 point or I Q 9 12 1 Tx MOD levels 1 Sets output levels on MOD1 and MOD2 signal pins 9 12 2 Tx sequence 18 Loads Tx sequence commands 9 12 3 RAMDAC load 3or67 Configures RAMDAC and loads data table 9 12 4 Device Ident 2 Reads back the Device Ident and Version number 9 12 5 Enter Deep Sleep 0 Enter Deep Sleep mode 9 12 6 Leave Deep Sleep 0 Leave Deep Sleep mode 9 12 7 Reference clock 1 0 19 2MHz 1 9 6MHz 9 12 8 7 8 System Clock Synthesisers Two System Clock outputs SYSCLK1and
32. ommand register specifying a data task This results in transfer of the data from the Write Data registers into the Tx Data Buffer Steps 1 and 2 can be repeated to load the Tx Data Buffer with a large block of data A Modem task can then be used to instruct the Tx Modulator to transmit the data in the Data Buffer This causes the content of the Tx Data Buffer to be coded and CRC d if in burst mode and transmitted to the MOD1 and MOD2 output pins 5 Once the system is up and running any modem task may potentially take some time to execute as it may have to wait for the previous task to complete T5 Command Register Command Reg Free Data Task Modem Task C Bus registers BIBJAJA Tx Data Buffer Modulator 7 6 8 7 88 words Data Task Complete TBFree 4 TxState gt C TxDone J Figure 7 Tx Task Operation 2011 CML Microsystems Plc 16 D 7045FI 1 x 1 Marine AIS SART Processor CMX7045 7 5 2 Registers and Buffers for Tx Tasks e Command register contains Data and Modem task fields as described above e Status register contains bits that indicate when tasks are complete which can interrupt the host o Command Reg Free o TBFREE o TxDONE o Config Task Complete o Data Task Complete e Interrupt Mask Host write register to specify which status bit can cause an interrupt e Write Data registers 0 3 Contain data written from ho
33. outputs and four GPIOs The CMX7045 offers low power sleep modes to ensure maximum system battery life and is available in a in a small 48 pin LQFP or VOFN package This Datasheet is the first part of a two part document comprising Datasheet and User Manual the User Manual can be obtained by registering your interest in this product with your local CML representative 2011 CML Microsystems Plc Marine AIS SART Processor CMX7045 CONTENTS 1 Brief Description eei ener eae rtis e etcetera 1 EE BIStOE i nt RR TO 3 2 Block Dia Grain x EE RR 4 3 Signal Pin List 5 3 1 Signal Definitions 2 23 a A TATA 7 4 Recommended External Components occccccnnnnnnoonccncncnnnnnanonnnnncnnnnnnnnnnnnnnnnnnnnnnn enn nrn nn arman nnmnnn nnne 8 5 PCB Layout Guidelines and Power Supply Decoupling eene 9 6 General Description me M 10 uEO MI 10 6 2 AlS System Formats sarsii eana deala a eterna eu a d eei ep Pe edo 10 7 Detailed Description eicit rentrer cinese tip 11 it Clock SOURCE ine EN 11 2 Host ntertace uc an ae anit eei ac de ain ee ei ee enn 11 7 3 Function Image Load and Activation sssssssseeeeene enne een 12 7 3 1 Fl Loading from Host Controller sse enne emen 12 7 4 System Description and Tasks sse eene nennen nennen nennen 14 7 4 1 Signal Routin
34. pp or CPVop 0 0 3 V AVpp and CPVpp 0 0 3 V DVss and AVss 0 50 mV L4 Package 48 pin LQFP Min Max Unit Total Allowable Power Dissipation at Tamb 25 C 1600 mW Derating 16 0 mW C Storage Temperature 55 125 C Operating Temperature 40 85 C Q3 Package 48 pad VQFN Min Max Unit Storage Temperature 55 125 C Operating Temperature 40 85 C Total Allowable Power Dissipation at Tamb 25 C 1750 mW Derating 17 5 mW C 8 1 2 Operating Limits Correct operation of the device outside these limits is not implied Notes Min Max Unit Supply Voltage DVpp DVss 3 0 3 6 V AVpp AVss 3 0 3 6 V Vpgc DVss 1 2 25 2 75 V Operating Temperature 40 85 C Clock Frequency 9 6 19 2 MHz Function Image size 24 46 kBytes Notes 1 The Vpgc supply is automatically created from DVpp by the on chip voltage regulator 2011 CML Microsystems Plc 27 D 7045FI 1 x 1 Marine AIS SART Processor 8 1 3 Operating Characteristics For the following conditions unless otherwise specified External components as recommended in Figure 2 Maximum load on digital outputs 30pF Clock Frequency 19 2MHz 20ppm Tamb 40 C to 85 C AVpp DVpp 3 0V to 3 6V Reference signal level 300mV pk pk with AVpp 3 3V Signal levels track with supply voltage so scale accordingly Signal to Noise Ratio SNR in bit rate bandwidth Input stage gain OdB Output stage attenuation OdB DC Parameters Notes Su
35. pply Current 10 All Powersaved Deep Sleep mode Dipp DVpp 9 3V VpEC 2 5V Alpp AVpp 3 3V Tx Mode 11 Dipp DVpp 3 3V VDEC 2 5V Alpp AVpp 3 3V Additional current for each Auxiliary System Clock output running at 4MHz Dipp DVpp 3 3V VpEC 2 5V Albo AVpp 3 3V Additional current for the Auxiliary ADC Dipp DVpp 3 3V VpEc E 2 5V Alpp AVpp 3 3V Additional current for each Auxiliary DAC Dipp DVpp 3 3V VpEC 2 5V Alpp AVpp 3 3V CLK 11 Input Logic 1 Input Logic O Input current Vin DVpp Input current Vin DVss C BUS Interface and Logic Inputs Input Logic 1 Input Logic O Input Leakage Current Logic 1 or 0 Input Capacitance C BUS Interface and Logic Outputs Output Logic 1 lop 1204A Output Logic 1 loH 1mA Output Logic 0 Io 360pA Output Logic 0 lo 1 5mA Off State Leakage Current IRQN Vout DVpp RDATA output HiZ VBIAS 12 Output voltage offset wrt AVpp 2 loi lt 11A Output impedance Min 90 80 1 0 1 0 2 Typ 24 4 20 11 250 300 Max 100 20 30 40 30 1 0 7 5 10 15 10 1 0 1 0 2 CMX7045 Unit yA yA mA mA 2011 CML Microsystems Plc 28 D 7045F1 1 x 1 Marine AIS SART Processor AC Parameters Notes CLK Input High pulse width 20 Low pulse width 20 Input impedance at 19 2MHz Powered up Resistance Capacitance Powered down Resistance Capacit
36. ransmitted as the modulator is available Transmit Sequence is ignored e PRBS Transmit Pseudorandom Bit Sequence This task causes the CMX7045 to transmit an internally generated pseudorandom bit sequence The sequence is 511 bits in length but will repeat indefinitely until aborted using the AbortTx task Transmit Sequence is ignored e TRW Transmit Repeated Word This task causes the CMX7045 to repeatedly transmit the first word currently in the data buffer Transmission will start immediately and will continue until an Abort Tx task is issued Transmit Sequence is ignored e HCT Hardware Control Task Allows manual control of ancillary hardware functions 7 6 2 AIS Burst Mode Transmit In AIS burst mode the CMX7045 responds to a TXB task by performing bit stuffing NRZI encoding and the addition of training sequence start stop flags and CRC checksum as required by AIS Note in AIS burst mode the data words are automatically transmitted least significant bit first as required by the AIS specification A number of error conditions are checked for during AIS burst mode transmit each of which causes transmission to be aborted and a Tx Done interrupt to be generated The associated Tx states are e Tx Aborted message too long This occurs if the internal message buffer is not big enough for the HDLC coded data should not happen in normal operation as the message buffer is big enough for a 5 slot message This condition requires the
37. re available from the CML Technical Portal Following a General Reset reloading of the Fl is required 7 3 4 Fl Loading from Host Controller The FI needs to be included into the host controller software build and downloaded into the CMX7045 at power up over the C BUS interface Wait for the ACT flag to be set Status register C6 bit 0 then the data can then be sent directly over the C BUS to the CMX7045 Each time the device is powered up or reset its Fl must first be loaded and then activated These two steps assign internal device resources and determine all device features The device does not operate until the Fl is loaded and activated The download time is limited by the clock frequency of the C BUS with a 5MHz SCLK it should take less than 500ms to complete 2011 CML Microsystems Plc 12 D 7045FI 1 x 1 Marine AIS SART Processor Power up or write General Reset to CMX7032 CMX7042 Y Poll C6 until bO 1 ACT flag set Y Configure ACT flag interrupt if required Y Write Start Block 1 Address DB1 ptr to B6 Write Block 1 Length DB1 len to B7 Y Write 0001 to C8 Y Wait for ACT flag to go high or interrupt Y Write next data word to C8 Y Wait for ACT flag to go high or interrupt Y Write Start Block 2 Address DB2_ptr to B6 Write Block 2 Length DB2_len to B7 Y Write 0001 to C8
38. reserved reserved i hp 83 84 of ESTA R Checksumihi o R Checksumtlo reserved OO reserved BC Jjresved BD Jjreseved BE Jjreseved Z o JA J gt R R R B9 BA BB BF AAA CO C1 16 All other C BUS addresses including those not listed above are either reserved for future use or allocated for production testing and must not be accessed in normal operation C3 C6 16 C7 16 CA CB zi als A 2 2 2 o o o gt Top o gt Kop 81 B3 B4 89 SBA BB BC BD S BE SBF o CO 01 03 06 07 SCA CB CF CF 2011 CML Microsystems Plc 26 D 7045F1 1 x 1 Marine AIS SART Processor CMX7045 8 Performance Specification 8 1 Electrical Performance 8 1 1 Absolute Maximum Ratings Exceeding these maximum ratings can result in damage to the device Min Max Unit Supply DVpp DVss 0 3 4 5 V AVpp AVss 208 4 5 V Voltage on any pin to DVss 0 3 DVpp 0 3 V Voltage on any pin to AVgs 0 3 AVpp 0 3 V Current into or out of any power supply pin excluding VBIAS 30 30 mA i e VDEC AVDD AVSS DVDD DVSS Current into or out of any other pin 20 20 mA Voltage differential between power supplies DVpp and AV
39. scillator inverter 41 DVDD PWR SS by capactors mounted close lo the device pins 42 CDATA IP C BUS Command Data Serial data input from the uC C BUS Reply Data A 3 state C BUS serial data output to 43 RDATA TS OP the uC This output is high impedance when not sending data to the uC 44 NC _ reserved do not connect this pin 45 DVSS PWR Digital Ground 46 SCLK IP C BUS The C BUS serial clock input from the uC 47 SYSCLK2 OP Synthesised Digital System Clock Output 2 48 CSN IP C BUS The C BUS chip select input from the pC ees The central metal pad may be connected to Analogue Mae DAD SUB 9 Ground AVss or left ungonnecred l No other electrical connection is permitted 2011 CML Microsystems Plc 6 D 7045FI 1 x 1 Marine AIS SART Processor Notes 3 1 Signal Definitions CMX7045 Input PU PD internal pullup pulldown resistor Output 3 state Output Power Supply Connection No Connection Table 1 Definition of Power Supply and Reference Voltages e Pins Usage AVpp AVDD Power supply for analogue circuits DVpp DVDD Power supply for digital circuits Voec VDEC Power supply for core logic derived from DVpp by on chip regulator VBIAS VBIAS Internal analogue reference level derived from AVpp AVss AVSS Ground for all analogue circuits DVss DVSS Ground for all digital circuits 2011 CML Microsystems Plc 7 D 7045FI 1 x 1 Marine AIS SART Processor CMX7
40. st uC to transmit via the Tx Modulator e Tx Data Buffer The Tx Data is double buffered which allows the host uC to write to the Tx Data Buffer while the modulator is simultaneously transmitting data it reads from the Tx Modem Buffer Each buffer is capable of holding one full 5 slot AIS message 7 5 3 Write Data Registers An array of four 16 bit C BUS write registers form the Write Data C BUS registers The device reads and acts upon the content of these data write registers as instructed by the Data Task bits of the Command register while in transmit mode Generally they may be written at any time by the host uC with no effect on internal device operation When a Data task is issued the Data registers will be read by the device and so should not be modified by the host uC until the Data Task complete bit is set in the Status register Data tasks access the registers as a number of words 1 to 4 or as a number of bits 1 to 16 in A7 however if a bit format Data Task is used it must be the final data task issued in a multi data transfer from the host The next data task issued should be a DataWordResetN Tx or DataBitResetN Tx to re initialise the internal data buffer pointers a bit format task is usually used as the last transfer of a data block that is not a complete number of words in length Word format
41. start and end of the data modulation e Adummy event in case any of the above are not required in the application The transmit event sequence is programmed using a Config task see User Manual section 9 12 3 Table 6 Tx Sequence events b3 b2 b1 b0 Event id Description 0 0 0 0 dummy Do nothing 0 0 0 1 reserved 0 0 1 0 reserved 0 0 1 1 Tx en hi Pin TXENA is set high 0 1 0 0 RAMDAC UP AuxDAC1 will start executing a Ramp up 0 1 0 1 MODULATE START Defines the start of data modulation 0 1 1 0 MODULATE END Delay from the end of modulation based on the last data bit loaded into modem includes a 20 tick delay for the internal filters 0 1 1 1 RAMDAC DOWN AuxDAC1 will start executing a Ramp down 1 0 0 0 Tx en lo Pin TXENA is set low 1 0 0 1 dummy Do nothing When calculating the MODULATE START timing value the delay through the CMX7045 s internal transmit filters and any external components must be taken into account to ensure that data bits appear on air at the correct time the filter delays are specified in section 8 1 4 The MODULATE END event has an in built delay of 20 ticks to allow the last bit to make its way out of the transmit filter Allowance must be made for this built in delay as well as for the delay through any external components when calculating the timing of the transmit power down events A working example of how to set up a transmit event sequence is shown in
42. ster that contains task fields for both Data and Modem units A task is invoked by writing its code into the Data Task or Modem Task fields A single C BUS write transaction will change all Command register fields Often the host will only want to issue either a Data or Modem task in which case it should ensure that the other task field is set to all zeroes corresponding to a null idle task Sometimes it is useful to issue Data and Modem tasks simultaneously in which case the Data task will always be completed before the Modem task is started Certain internal subsystems can be directly accessed and controlled via C BUS transactions without issuing a specific task command 2011 CML Microsystems Plc 14 D 7045FI 1 x 1 Marine AIS SART Processor CMX7045 7 4 4 Timing and Synchronisation The CMX7045 requires a Slot Clock SLOTCLK input from the host uC This should be a pulse at least 50us long whose rising edge is aligned to the AIS Slot boundary An edge is required at the start of every AIS slot or frame hence the frequency of this signal is 37 5Hz or 0 5Hz The CMX7045 has several features to assist the host uC with timing which are detailed below All of these features are based on the SLOTCLK signal provided by the host to the CMX7045 s SLOTCLK pin All timings are defined as a number of 24kHz ticks referenced to the rising edge of the SLOTCLK signal 7 4 5 Tx Timing The CMX7045 can be configured to perform a sequence of
43. t and development risk with increased flexibility for the designer and end application FirmASIC combines Analogue Digital Firmware and Memory technologies in a single silicon platform that can be focused to deliver the right feature mix performance and price for a target application family Specific functions of a FirmASIC device are determined by uploading its Function Image during device initialization New Function Images may be later provided to supplement and enhance device functions expanding or modifying end product features without the need for expensive and time consuming design changes FirmASIC devices provide significant time to market and commercial benefits over Custom ASIC Structured ASIC FPGA and DSP solutions They may also be exclusively customised where security or intellectual property issues prevent the use of Application Specific Standard Products ASSP s Handling precautions This product includes input protection however precautions should be taken to prevent device damage from electro static discharge CML does not assume any responsibility for the use of any circuitry described No IPR or circuit patent licences are implied CML reserves the right at any time without notice to change the said circuitry and this product specification CML has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification Specific testing of all circuit parameters
44. tem clock derived from reference oscillator and eliminates the need for additional XTAL or baseband clock oscillator Auxiliary clock synthesisers generate two clocks for external use to support peripheral devices Function Image is loaded directly from the host uC via C BUS Integrated 2 5V regulator can develop 2 5V from required 3 3V supply Powersave facilities minimise total system power 6 2 AIS System Formats The AIS system uses two basic channel access mechanisms Self Organising Time Division Multiple Access SOTDMA and Carrier Sensing Time Division Multiple Access CSTDMA The CMX7045 is compatible with both systems and offers additional features which simplify the implementation of an AIS SART device conforming to IEC 61097 14 The relevant International standards are 0 ITU R M 1371 4 1 IEC 61993 2 Class A 2 IEC 62287 1 Class B CSTDMA 3 IEC 62287 2 Class B SOTDMA 4 IEC 62320 1 Base Station 5 IEC 62320 2 Aids to Navigation 6 IEC 61097 14 AIS SART 2011 CML Microsystems Plc 10 D 7045FI 1 x 1 Marine AIS SART Processor CMX7045 7 Detailed Description 7 1 Clock Source The CMX7045 can be used with either a 9 6MHz xtal or a 19 2MHz oscillator 7 2 Host Interface This section provides a general description of the C BUS serial interface protocol used to transfer data control and status information between the CMX7045 and its host C BUS is a serial interface similar to SPI that uses a simple tr
45. teristics when driving the XTAL CLK pin with an external clock source Applies when utilising VgiAs to provide a reference voltage to other parts of the system When using Vg as as a reference VgiAs must be buffered Veas must always be decoupled with a capacitor as shown in Figure 3 Timing for an external input to the XTAL CLK pin Power up refers to issuing a C BUS command to turn on an output These limits apply only if Veias is on and stable Small signal impedance at AVpp 3 3V and Tamb 25 C With respect to the signal at the feedback pin of the selected input port With the output driving a 20kO load to AVpp 2 Denotes output impedance of the driver of the auxiliary input signal to ensure lt 1 bit additional error under nominal conditions With a load of 5kO to AVpp 2 Guaranteed monotonic with no missing codes 2011 CML Microsystems Plc 30 D 7045FI 1 x 1 Marine AIS SART Processor 8 1 4 Parametric Performance For the following conditions unless otherwise specified External components as recommended in Figure 2 Maximum load on digital outputs 30pF CLK Frequency 19 2MHz 20ppm Tamb 40 C to 85 C AVpp DVpp 3 0V to 3 6V Reference Signal Level 300mV pk pk with AVpp 3 3V Signal levels track with supply voltage so scale accordingly Signal to Noise Ratio SNR in bit rate bandwidth Input stage gain OdB Output stage attenuation OdB Transmit Parameters AIS GMSK 9600bps
46. tup time 75 ns tcon CDATA hold time 25 ns tros RDATA setup time 50 ns tron RDATA hold time 0 ns Notes 1 Depending on the command 1 or 2 bytes of CDATA are transmitted to the peripheral MSB Bit 7 first LSB Bit 0 last RDATA is read from the peripheral MSB Bit 7 first LSB Bit 0 last 2 Data is clocked into the peripheral on the rising SCLK edge 3 Commands are acted upon at the end of each command rising edge of CSN 4 To allow for differing uC serial interface formats C BUS compatible ICs are able to work with SCLK pulses starting and ending at either polarity 5 Maximum 30pF load on IRQN pin and each C BUS interface line These timings are for the latest version of C BUS and allow faster transfers than the original C BUS timing specification The CMX7045 can be used in conjunction with devices that comply with the slower timings subject to system throughput constraints 2011 CML Microsystems Plc 32 D 7045FI 1 x 1 Marine AIS SART Processor CMX7045 8 3 Packaging indexAmedi ER a DIM MIN TYP MAX A 7 00 BSC d B 7 00 BSC P C 0 80 0 90 1 00 i J F 4 60 5 65 B Canes G 4 60 5 65 H 0 00 0 05 J J 0 18 0 25 0 30 E K 0 20 L 0 30 0 40 0 50 Top View L1 0 0 15 P 0 50 T 0 20 J NOTE I d A amp B are reference data and do UUUUUUUUUUUT not include mold deflash or protrusions p er K y B F q All dimensions in mm B
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