Interrupt Response Time of the XC16x Family
Contents
1. 2 interrupt FIOW asschieeseesncucseuscthesnetieusntescabe eater ni RE ean eiai kei eieiei 5 2 2 1 Peripheral External Interrupt cccsccccccseeeeeeeeeeeceeeeeceeeeeseeeeeeeeeeseaees 6 2 2 2 Interrupt Controller cccceeccccseeeeeceeeeeceeeeeeceeeeeeseaeeeeseeeesaaeeeeseeeeeeseeeesaass 7 2 2 3 OPU PEU sprane seeders recess aseee eect cen nh se iaeeeeoemaiese 8 2 3 BS NMA E AE AE E EE saseust E ESS 10 3 Configuration of the Interrupt Handler cccceeeceeeeeeeeeeeeeeeeeeeeeeeeaeeeeees 12 3 1 Potentials to influence the interrupt response tiME ccccsseeeeeeeeeeeeeees 12 3 1 1 Jump Table Cache Fast Interrupt cccscsceecsseeeeeeeeeeeeeeeeeseeeeesaeeeeens 12 3 1 2 Fast Bank SWItChing cccccsscceccsseeeeseeeeecseeeeeeeeeeeeseeeeessaeeeeseeeeeesaneeeeas 13 3 2 C Compiler and configuration of the interrupt handler cccseeeeeeees 13 3 2 1 ae EE E EEE EE E aes caasa caeaent A EA E T 14 3 2 2 TASKIN aa E E EE E EA E 16 4 CONCUSSION eerie e E E Eoi 19 Application Note 3 V 1 0 2004 08 Infineon AP16083 oaia Interrupt Response Time of the XC16x Family Introduction 1 Introduction The architecture of the XC16x supports several mechanisms for fast and flexible response to service requests from various sources internal or external to the microcontroller Different kinds are handled in a similar way e Interrupts generated by the Interrupt Controller ITC e2. 4 a z 1 o o e CD Pi r Figure 7 Jump Table Cache Registers Application Note 12 V 1 0 2004 08 Infineon AP16083 oaia Interrupt Response Time of the XC16x Family Configuration of the Interrupt Handler 3 1 2 Fast Bank Switching The XC16x architecture allows switching the selected physical register bank By updating the bitfield BANK in register PSW the active register bank is switched In case of an interrupt service the bank switch is automatically executed by updating bitfield BANK from BNKSEL x in the interrupt controller For interrupt priority levels 12 15 the target register bank can be pre selected The registers BNKSELx provides a 2 bit field for each possible arbitration priority level The respective bitfield is then copied to bitfield BANK in register PSW to select the register bank as soon as the respective interrupt request is accepted After a switch to a local register bank the new bank is immediately available BNKSELx Register Bank Select Reg x XSFR See Table 5 10 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPRSEL7 GPRSEL6 GPRSEL5 GPRSEL4 GPRSEL3 GPRSEL2 GPRSEL1 GPRSELO rw rw rw rw rw rw rw rw Field Description GPRSELy Register Bank Selection y 7 0 00 Global register bank 01 Reserved 10 Local register bank 1 11 Local register bank 2 Figure 8 Registers BNKSELO 3 for interrupt priority level 12 15 3 2 C Compiler and configuration of t
3. of function CC2_viTmr7 define SEG func unsigned int unsigned long void far void func gt gt 16 define SOF func unsigned int void far void func void CC2 Vint void Initialize fast interrupt register EN 1 ILVL 15 GLVL 0 GPX 0 FINTOCSP SEG CC2_Tmr7 Ox8C00 FINTOADDR SOF CC2_Tmr7 PSW_IEN fT set global interrupt enable Fast Bank switching When using _FAST_BANKx_ or _FAST_ABANKx_ a separate user stack needs to be defined for these ISR s This is done with UST1SZ and UST2SZ in the START_V2 A66 file Be sure to define a range that is big enough to hold the local variables of the ISR UST1SZ EQU 0x20 set User Stack Size to 20H Bytes UST2SZ EQU 0x20 set User Stack Size to 20H Bytes When _FAST_ABANKx_ is used the interrupt controller register BNKSELx needs to be initialized before the interrupt is enabled The following example shows how to do it void CC2_ viCC2 void interrupt CC2_T7INT using _FAST_ABANK2 _ BNKSEL1 0x0300 BNKSEL1 GPRSEL4 11 gt Local register bank 2 PSW_IEN JI set global interrupt enable Application Note 15 V 1 0 2004 08 eo nfineon AP16083 oaia Interrupt Response Time of the XC16x Family Configuration of the Interrupt Handler Fast Bank switching Jump Table Cache void CC1_vicCC1 void interrupt CC2_T7INT CACHED using _FAST_ABANK2 _ BNKSEL1 0x0300 BNKSEL1 GPRSEL4 11 gt Local register bank 2 PSW_IEN 1 s
4. this case no SCXT instruction is executed In the case when the selection of a local register bank is done at the starting point of the interrupt service routine a cancellation of the complete pipeline is caused and an additional minimum delay of 6 clock cycles is added Application Note 8 V 1 0 2004 08 e Infineon AP16083 G Interrupt Response Time of the XC16x Family Interrupt response time In the case of a PEC transfer being processed a part of all the interrupt related process is required PEC transfers are generally a faster method of interrupt services For PEC transfers the arbitration process works in the same manner After the request is accepted by the CPU a special instruction is injected and it passes through the pipeline until the execute stage is reached Figure 5 shows the flow in detail 3 PD clock cycles Figure 5 PEC Transfer An additional delay can be caused if e Interrupt Controller is busy e Pipline stalled e Pipline cancelled Application Note 9 V 1 0 2004 08 _ Infineon AP16083 ee Interrupt Response Time of the XC16x Family Interrupt response time 2 3 Summary Figure 6 summarizes the interrupt response time for interrupts in general and for PEC transfers The numbers of cycles inside the brackets that have been added are dependent of the following reasons Interrupt Controller busy Pipeline stalled Pipeline cancelled Latency of the memory Con
5. Application Note V 1 0 Aug 2004 AP 16083 16 Bit CMOS Microcontroller Product Interrupt Response Time of the XC 16x Family Microcontrollers Never stop thinking 16 Bit CMOS Microcontroller Revision History 2004 08 V 1 0 Previous Version Page Subjects major changes since last revision Controller Area Network CAN License of Robert Bosch GmbH We Listen to Your Comments Any information within this document that you feel is wrong unclear or missing at all Your feedback will help us to continuously improve the quality of this document Please send your proposal including a reference to this document to mcdocu comments infineon com gt lt Edition 2004 08 Published by Infineon Technologies AG 81726 Munchen Germany Infineon Technologies AG 2006 All Rights Reserved LEGAL DISCLAIMER THE INFORMATION GIVEN IN THIS APPLICATION NOTE IS GIVEN AS A HINT FOR THE IMPLEMENTATION OF THE INFINEON TECHNOLOGIES COMPONENT ONLY AND SHALL NOT BE REGARDED AS ANY DESCRIPTION OR WARRANTY OF A CERTAIN FUNCTIONALITY CONDITION OR QUALITY OF THE INFINEON TECHNOLOGIES COMPONENT THE RECIPIENT OF THIS APPLICATION NOTE MUST VERIFY ANY FUNCTION DESCRIBED HEREIN IN THE REAL APPLICATION INFINEON TECHNOLOGIES HEREBY DISCLAIMS ANY AND ALL WARRANTIES AND LIABILITIES OF ANY KIND INCLUDING WITHOUT LIMITATION WARRANTIES OF NON INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS OF ANY THIRD PARTY WITH RESPECT TO AN
6. DMA transfer issued by the Peripheral Event Controller PEC e Traps caused by the Trap instruction or issued by faults or specific system states The XC16x family fits perfectly in embedded applications The target of this application note is to supply detailed information about the real time capabilities of the interrupt architecture For more detailed information about the functionallity of the interrupt architecture please refer to the corresponding user manual 1 1 General Conditions The following calculations are only valid for the conditions below e All memory accesses are done without delay Code and Interrupt Vector Table located in a fast internal Memory PRAM Flash accessed within 1 CPU clock cycle The stack is located in DPRAM e The Peripheral Bus clock speed is the same as CPU clock speed e No previous interrupt request is still processed e No stall or cancellation condition of the pipeline is valid Application Note 4 V 1 0 2004 08 Infineon AP16083 ee Interrupt Response Time of the XC16x Family Interrupt response time 2 Interrupt response time 2 1 Definition of Interrupt Response time In this document the Interrupt Response Time is defined as the time between an active request signal being generated and the first instruction of the associated interrupt process entering the pipline of the CPU 2 2 Interrupt Flow The interrupt flow is divided in the following sections e Peripheral Fast Exter
7. Y AND ALL INFORMATION GIVEN IN THIS APPLICATION NOTE Information For further information on technology delivery terms and conditions and prices please contact your nearest Infineon Technologies Office www infineon com Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact your nearest Infineon Technologies Office Infineon Technologies Components may only be used in life support devices or systems with the express written approval of Infineon Technologies if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system Life support devices or systems are intended to be implanted in the human body or to support and or maintain and sustain and or protect human life If they fail it is reasonable to assume that the health of the user or other persons may be endangered Infineon AP16083 Se Interrupt Response Time of the XC16x Family Introduction Table of Contents Page 1 RP OGUCTION eccirni i a a aia 4 1 1 General Conditions cccccseccccceeeeeceeeeeeceeeeecseeeeeseueeeeseueeesseeeeessuseeeseeeensees 4 2 Interrupt response time ccceeececeecceseeceeececeeseseueeeeaeeenseeesseeeseesensetensesenees 5 2 1 Definition of Interrupt RESPONSE time ccccccseeeeeceeeeeeceeeeeeeeeeeeeseeeeesaaeees 5 2
8. erified in either case Application Note 11 V 1 0 2004 08 eo nfineon AP16083 oaia Interrupt Response Time of the XC16x Family Configuration of the Interrupt Handler 3 Configuration of the Interrupt Handler 3 1 Potentials to influence the interrupt response time The XC16x architecture offers a couple of dedicated registers to configure the interrupt handler The configuration can be divided in two groups e Interrupt jump table cache e Fast bank switching 3 1 1 Jump Table Cache Fast Interrupt The interrupt servicing time can be reduced by the Interrupt Jump Table Cache This feature eliminates the explicit branch to the ISR by directly providing the CPU with the service routine location The two pointers are each stored in a pair of interrupt jump table cache registers which store an 8 bit pointer segment and a 16 bit offset along with the priority level priority level 12 15 These features can be selected for two interrupt sources FINTOCSP Fast Interrupt Control Register 0 XSFR ECOO y Reset value 0000y 15 14 13 12 11 10 g a T 6 5 4 a 2 1 FINTICSP Fast Interrupt Control Register 1 XSFR ECO4 Reset value 0000H 15 14 13 12 11 10 J a T Gi 5 4 a 2 1 0 es e re ree ne re ree FINTOADDR Fast Interrupt Address Register 0 XSFR ECO2Zy Reset value 0000y 15 14 13 12 11 10 g 5 T 6 5 4 a z 1 o nanan rw T FINTIADDR Fast Interrupt Address Register 1 XSFR ECOGy Reset value 0000y 15 14 13 12 11 10 g 5 T 6 5
9. et global interrupt enable 3 2 2 Tasking The Tasking C Compiler supports the XC16x architecture and the enhanced interrupt handling Included are some useful extensions to force fast register bank switching cached interrupts etc For more detailed information please refer to the Tasking C Compiler manual stacksize num specifies the userstack adjustment in byte _localbank num local register bank switching 0 1 2 1 2 0 Global register bank 1 2 local register bank1 2 BNKSELO should be used 1 2 local register bank1 2 PSW is set in the ISR not recommended _cached bypasses the interrupt vector table pragma noframe omit the whole interrupt frame allows you to make your own interrupt frame Should be used carefully General Interrupt using global register bank The Timer T7 overflow interrupt is enabled If a timer T7 overflow occurs the service routine switches the context of the global register bank to get a new set of GPRs interrupt CC2_T7INT void CC2_viTmr7 void Application Note 16 V 1 0 2004 08 Infineon technologies AP16083 Interrupt Response Time of the XC16x Family Configuration of the Interrupt Handler Interrupt Jump Table Cache The Timer T7 overflow interrupt is enabled If a timer T7 overflow occurs the service routine switches the context of the global register bank to get a new set of GPRs Instead of using the vector table the CPU direct
10. he interrupt handler Both Keil and Tasking Compilers support the enhanced interrupt handling of the XC16x architecture DAVE Digital Application Engineer does not currently support the enhanced interrupt handling The following hints may be useful to illustrate how the user may to influence the interrupt response time Application Note 13 V 1 0 2004 08 _ Infineon AP16083 oaia Interrupt Response Time of the XC16x Family Configuration of the Interrupt Handler 3 2 1 Keil The Keil C Compiler supports the XC16x architecture and the enhanced interrupt handling For more detailed information please refer to the Keil C Compiler manual or C166 USING XC16X FAST REGISTER BANK SWITCHING There are different register bank switching methods available They can be controlled with different specifiers for rbank_id Omitting using The compiler generates code to save PUSH and restore POP all registers that are used in this function to the system stack Saving and restoring the register values takes time However if you have a very small interrupt function where only a few registers are used this might be the most effective method Any Name The compiler generates code to save PUSH the current context pointer register CP and loads it with the address of a dedicated register bank At the end of the ISR the CP register is restored The registers RO to R15 don t need to be saved on the system stack in this case Specifiying a reg
11. interrupt frame FINTOCSP 0x8000 unsigned long amp CC2_viTmr7 gt gt 16 FINTOADDR unsigned int amp CC2_viTmr7 BNKSELO 0x0002 Set local register bank 1 for Interr level 12 group o0 PSW_IEN l set global interrupt enable This is the fastest way to process an interrupt call because the extension pragma noframe omits the whole interrupt frame Using this extension makes the user responsible for storing all the controller specific registers like data pointers multiply registers etc Application Note 18 V 1 0 2004 08 Infineon AP16083 oaia Interrupt Response Time of the XC16x Family Conclusion 4 Conclusion The architecture of the XC16x supports several powerful mechanisms for fast and flexible response to service requests from various sources For optimized code and dataflow the customer has to analyze the real time requirements of their application The interrupt architecture of the XC16x together with the different tool chains perfectly supports these requirements Application Note 19 V 1 0 2004 08 http www infineon com Published by Infineon Technologies AG
12. ister bank speeds up the execution of an ISR _FAST_BANK1_ or _FAST_BANK2_ The compiler generates code to switch to a fast register bank by modifying the BANK field of the program status word PSW The registers RO to R15 don t need to be saved on the system stack in this case _FAST_ABANK1_ or _FAST_ABANK2_ The compiler does not generate code to switch to a different register bank or to save the current registers RO R15 The interrupt controller BNKSELx register must be initialized to switch to a fast register bank automatically on entering the ISR by the user application The following C Examples illustrate the configuration and the interrupt handling General Interrupt using global register bank void CC1_vInit void PSW_IEN 1 set global interrupt enable void CC2_viTmr7 void interrupt CC2_T7INT End of function CC2_viTmr7 Application Note 14 V 1 0 2004 08 eo nfineon AP16083 oaia Interrupt Response Time of the XC16x Family Configuration of the Interrupt Handler Interrupt Jump Table Cache An interrupt service routine ISR can be defined with lt Name gt CACHED instead of an interrupt vector number In this case no interrupt vector is generated The application needs to program the interrupt controller registers FINTxCSP and FINTxADDR with the address of the ISR before the interrupt is enabled The following example shows how to do it void CC2_viTmr7 void interrupt CC2_T7INT CACHED End
13. ly takes the addresses of the service routine interrupt CC2_T7INT cached void CC2_viTmr7 void FINTOCSP 0x8000 unsigned long amp CC2_viTmr7 gt gt 16 FINTOADDR unsigned int amp CC2_viTmr7 PSW_IEN 1 set global interrupt enable Fast Bank switching Jump Table Cache The Timer T7 overflow interrupt is enabled If a timer T7 overflow occurs the service routine switches automatically to the local register bank 1 Instead of using the vector table the CPU directly takes the addresses of the service routine interrupt CC2_T7INT _localbank 1 _stacksize 50 _cached void CC2_viTmr7 void FINTOCSP 0x8000 unsigned long amp CC2_viTmr7 gt gt 16 FINTOADDR unsigned int amp CC2_viTmr7 BNKSELO 0x0002 Set local register bank 1 for Interr level 12 group 0 PSW_IEN i set global interrupt enable Fast Bank switching Jump Table Cache advanced The Timer T7 overflow interrupt is enabled If a timer T7 overflow occurs the service routine switches automatically to the local register bank 1 Instead of using the vector table the CPU directly takes the addresses of the service routine Application Note 17 V 1 0 2004 08 Infineon technologies AP16083 Interrupt Response Time of the XC16x Family Configuration of the Interrupt Handler interrupt CC2_T7INT _localbank 1 _stacksize 50 cached void CC2_viTmr7 void pragma noframe omit the whole
14. nal Interrupt e Interrupt Controller Arbitration e CPU Core Interrupt Requests ied Re ques njection Figure 1 Interrupt Flow Application Note 5 V 1 0 2004 08 e Infineon AP16083 Ga Interrupt Response Time of the XC16x Family Interrupt response time 2 2 1 Peripheral External Interrupt Interrupt requests may be triggered either by the on chip peripherals or by external inputs From the point when an interrupt occurs until the interrupt request flag is set takes 2 or 3 peripheral clock cycles 2 PD clock cycles Figure 2 Peripherals Fast external Interrupts Application Note 6 V 1 0 2004 08 e Infineon AP16083 ee Interrupt Response Time of the XC16x Family Interrupt response time 2 2 2 Interrupt Controller The interrupt controller is arbitrating all pending interrupts according to a programmable prioritization schema PEC Interrupt Handler Figure 3 Interrupt Arbitration The interrupt arbitration is done in three stages The first arbitration stage all active requests are compared against their priorities from the respective xxIC registers The second arbitration stage the first stage winner is arbitrated against the OCDS service requests an interrupt injection is requested to the CPU The third arbitration stage the upcoming request is examined inside the CPU against the current value from PSW priority level of the present ta
15. sk and global interrupt enable flag Application Note 7 V 1 0 2004 08 _ Infineon technologies AP16083 Interrupt Response Time of the XC16x Family Interrupt response time 2 2 3 CPU PEC Whenever a request is accepted the ITRAP instruction is injected The preparation and the execution take 5 CPU clock cycles Servicing an interrupt request via the vector table requires two subsequent branches The first one includes the vector location the second one includes the address to the actual service routine The interrupt service time can be reduced by 4 cycles using the Jump Table Cache feature FINTxCSP FINTxADDR BNKSELx Prepares to 3 PD clock cycles inject ITRAP 4 fcpu clock cycles 4 fcpu clock cycles 1 fepu clock cycle Execution of ITRAP 4 fepu clock cycle Figure 4 Interrupt processing Before the first instruction of an interrupt service routine is executed a context switch is mandatory There are two ways to switch the context in the XC16x core e Switching between Global Register Banks One single dedicated instruction SCXT is used to change the Context Pointer Register to save the old and to load the new GPR content to from Dual Ported Memory The execution of the SCXT instruction takes 19 clock cycles e Switching to a local Register Bank For interrupt priority levels 15 12 the two local register banks can be pre selected and can then be switched automatically In
16. text switching neler 1 4 4 4 fcpu Interrupt 2 3 PD cycle 5 3PDcycle gele PEC 2 3 PD cycle 5 3 PD cycle 1 4 fcpu cycle Figure 6 Interrupt Response Time Please refer to the XC16x user manual for detailed information about additional delays The following example visualise the best case interrupt response time The interrupt service routine ISR is executed from the internal program memory PM The jump table cache feature is used The local register bank is initialized before the interrupt is enabled If the general condition as described in chapter 1 1 are valid the interrupt response time take 21 CPU cycles 525ns 40 MHz Application Note 10 V 1 0 2004 08 Infineon AP16083 oaia Interrupt Response Time of the XC16x Family Interrupt response time The following conditions describe some conditions for add on to the existing interrupt response time The interrupt response time is extended by 19 CPU cycles if a global register bank is used The interrupt response time can be extended by up to 9 CPU cycles if another interrupt request is started arbitration The interrupt response time is extended by 7 CPU cycles if the register bank is changed directly in the PSW register The interrupt response time is extended by 5 CPU cycles if a special function register is updated Note These numbers of cycles are only valid for optimized bus timings and should be v
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