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uPD789074 Subseries 8-Bit Single-Chip Microcontrollers UD

1. esee nennen nennen nnns 53 3 3 1 Relative addressing ERR OUR REGN IHRE PEE 53 3 3 2 lmmediate addressing cotton sne aa ia 54 10 User s Manual U14801EJ3V1UD 3 3 3 Table indirectiaddressing 55 3 3 4 Register addressing iaioe e a e 55 3 4 Operand Address Addressinhg iiae eaan aaea anea e e ee eae a aaaea aeaea ea Haaa aa ae deaa aa aaaeei NEE 56 3 4 1 Direct addressing DEE 56 3 4 2 Short direct addressing RE 57 3 4 3 Special function register SFR addressing AA 58 3 4 4 Register addressing rund dags cens dea etl c dede erte 59 3 4 5 Register indirect addressing cccsecceceseeceeeeeceeeeseeeeseseneeeesgecenesenseeeeseeeeseseeseneseeseeseneneeeeneeeees 60 3 4 6 Based addressing eee eU nm deett ie an 61 3 4 7 Stack lee le NEE 61 CHAPTER 4 PORT FUNCTIONS Lee c ccce nece cerne e ca rre rre 62 All uti 62 4 2 Bertptontoutallgtteeug see ee 64 4 2 1 POLO uc ti ee A ebe 64 4 2 2 Pot att tati do 65 4 2 3 lur at eit 66 4 2 4 PO E P 70 4 3 Port Function Control Registers rrrvrrrnvrnnnnvnnnnnnnnnvnnnnnvnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnner 71 4 4 Operation of Port Functions rrrssvrnnnnvnnnnvnnnnnnvnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnner 74 4 4 1 Writing to VO Portrait envie meten eei 74 4 4 2 Reading from l O port ico uu telas Te t it eR elg e edere 74 4 4 3 Arithmetic operation of I O port 74
2. d STOP mode murte Operation mode Data retention mode sr STOP instruction execution Standby release signal interrupt request twarr 220 User s Manual U14801EJ3V1UD CHAPTER 16 ELECTRICAL SPECIFICATIONS CONVENTIONAL PRODUCTS Flash Memory Write Erase Characteristics Ta 10 to 40 C Von 1 8 to 5 5 V Voo 1 8 to 5 5 V Write current loow When Vre supply During fx 5 0 MHz Voo pin voltage Ver operation Note Write current Ver pin Erase current IDDE When Ver supply During fx 5 0 MHz Voo pin voltage Ver operation Ippw When Ver supply voltage Ve Note Erase current Ver pin When Ver supply voltage Ver Unit erase time eee eee DES EIERE aee tett IO E Note The port current including the current that flows to the on chip pull up resistors is not included User s Manual U14801EJ3V1UD 221 CHAPTER 17 PACKAGE DRAWING 30 PIN PLASTIC SSOP 7 62 mm 300 detail of lead end CF G Y Y o T Y c i p f E U NOTE ITEM MILLIMETERS Each lead centerline is located within 0 13 mm of A 9 85 0 15 its true position T P at maximum material condition 0 45 MAX 0 65 T P 0 08 0 2420 07 0 1 0 05 1 3 0 1 1 2 8 1 0 2 6 1 0 2 1 0 0 2 0 17 0 03 0 5 0 13 0 10 0 5 EWECH 0 25
3. APPENDIX A DEVELOPMENT TOOLS Figure A 1 Development Tools Language processing software Assembler package C compiler package Device file C library source fileNote 1 Flash memory writing tools Flash programmer Flash memory writing adapter Flash memory Project manager Windows version only ete 2 Software package Software package Debugging software I Control software Host machine PC or EWS Integrated debugger System emulator Interface adapter Power supply unit In circuit emulator Emulation board Emulation probe Conversion socket or conversion adapter Target system Notes 1 The C library source file is not included in the software package 2 The project manager is included in the assembler package and is available only for Windows 226 Users Manual U14801EJ3V1UD APPENDIX A DEVELOPMENT TOOLS A 1 Software Package SP78K0S Software package Various software tools for 78K 0S development are integrated in one package The following tools are included RA78KOS CC78K0S ID78K0 NS SM78KOS various device files Part number SxxxxSP78K0S Remark xxxx in the part number differs depending on the operating system used USxxxx SP78K0S AB17 PC 9800 series Japanese Windows CD ROM BB17 IBM PC AT and compatibles English Windows Note Also operates und
4. Caution The oscillator constant is a reference value based on evaluation in specific environments by the resonator manufacturer If the oscillator characteristics need to be optimized in the actual application request the resonator manufacturer for evaluation on the implementation circuit Note that the oscillation voltage and oscillation frequency merely indicate the characteristics of the oscillator Use the internal operation conditions of the uPD789071 789072 and 789074 within the specifications of the DC and AC characteristics User s Manual U14801EJ3V1UD 211 CHAPTER 16 ELECTRICAL SPECIFICATIONS CONVENTIONAL PRODUCTS Ceramic resonator Ta 40 to 85 C uPD78F9076 Manufacturer Part Number Frequency Recommended Circuit Oscillation Voltage Range Remarks MHz aa CS Kees x 5 Rd 1 0 kQ Murata Mig CSBLA1M00J58 B0 Co Ltd CSBFB1M00J58 R1 CSTCC2M00G56 RO 19 On chip capacitor CSTLS2M00G56 BO CSTCR4M00G53 RO CSTLS4M00GG53 BO CSTCR4M19G53 RO 4 194 CSTLS4M19GG53 BO CSTCR4M91G53 RO 4 915 2 0 CSTLS4M91GG53 BO CSTCR5M00G53 RO CSTLS5M00GG53 BO Co Ltd low capacitor voltage drive CSTLS4M00GG53093 BO type CSTCR4M19G53093 RO 4 194 CSTLS4M19GG53093 B0 CSTCR4M91G53093 RO 4 915 CSTLS4M91GG53093 B0 CSTCR5M00G53093 RO CSTLS5M00GG53093 BO Note A limiting resistor Rd 1 0 kQ is required when CSBLA1M00J58 BO or CSBFB1M00J58 R1 1 0 MHz manufactured by Murata Mfg Co Ltd
5. Illustration OP code saddr offset NE Short direct memory Effective address When 8 bit immediate data is 20H to FFH When 8 bit immediate data is OOH to 1FH o 0 1 User s Manual U14801EJ3V1UD 57 CHAPTER 3 CPU ARCHITECTURE 3 4 3 Special function register SFR addressing Function A memory mapped special function register SFR is addressed with the 8 bit immediate data in an instruction word This addressing is applied to the 256 byte spaces FFOOH to FFFFH However SFRs mapped at FFOOH to FF1FH can also be accessed with short direct addressing Operand format Special function register name Description example MOV PMO A When selecting PMO for sfr Instruction code 1 1 1 0 0 Illustration OP code sfr offset SFR 7 0 Effective 58 User s Manual U14801EJ3V1UD CHAPTER 3 CPU ARCHITECTURE 3 4 4 Register addressing Function A general purpose register is accessed as an operand The general purpose register to be accessed is specified with the register specify code and functional name in the instruction code Register addressing is carried out when an instruction with the following operand format is executed When an 8 bit register is specified one of the eight registers is specified with 3 bits in the instruction code Operand format r and rp can be described with absolute names RO to R7 and RPO to RP3 as well as functio
6. Remark FL PR3 FL PR4 and the program adapter are products made by Naito Densei Machida Mfg Co Ltd TEL 81 45 475 4191 Programming using flash memory has the following advantages e Software can be modified after the microcontroller is solder mounted on the target system e Distinguishing software facilities small quantity varied model production e Easy data adjustment when starting mass production 13 1 1 Programming environment The following shows the environment required for uPD78F9076 flash memory programming When Flashpro III part no FL PR3 PG FP3 or Flashpro IV part no FL PR4 PG FP4 is used as a dedicated flash programmer a host machine is required to control the dedicated flash programmer Communication between the host machine and flash programmer is performed via RS 232C USB Rev 1 1 For details refer to the manuals for Flashpro III Flashpro IV Remark USB is supported by Flashpro IV only Figure 13 1 Environment for Writing Program to Flash Memory Ver RS 232C 7 Ve E amp 7 LEG Vss KE ar BESET m x RESET 2 3 wire serial I O Dedicated flash UART uPD78F9076 programmer A Host machine or pseudo 3 wire Users Manual U14801EJ3V1UD 175 13 1 2 Com Use the CHAPTER 13 PD78F9076 munication mode communication mode shown in Table 13 2 to perform communication between the dedicated flash programmer and uPD78F9076 Communicatio
7. Serial clock Serial input Serial output Chip select input Timer input Timer output Transmit data Power supply Programming power supply Ground Crystal ceramic oscillator 23 x 1 7 78K 0S Series Lineup 24 CHAPTER 1 GENERAL The products in the 78K 0S Series are listed below The names enclosed in boxes are subseries names 44 pin 42 44 pin 30 pin 30 pin 28 pin 20 pin 20 pin 44 pin 44 pin 30 pin 30 pin 30 pin 30 pin 30 pin 30 pin 144 pin 88 pin 80 pin 80 pin 78K 0S 80 pin Series 80 pin 64 pin 64 pin 64 pin 64 pin 64 pin 64 pin 52 pin 52 pin 44 pin FC 44 pin r 30 pin 30 pin 20 pin 20 pin 52 pin 64 pin EJ Products in mass production gt Products under development Y subseries supports SMB Small scale package general purpose applications LPD789014 HPD789062 HPD789052 HPD789074 with subsystem clock added pPD789014 with enhanced timer function and expanded ROM and RAM p1PD789074 with enhanced timer function and expanded ROM and RAM PD789026 with enhanced timer function On chip UART and capable of low voltage 1 8 V operation RC oscillation version of uPD789052 PD789860 without EEPROM POC and LVI Small scale package general purpose applications and A D function uPD789177Y 1L PD789167 with 10 bit A D LH PD789177 HPD789167 f D789156 Hu LCD drive UP P D789479
8. User s Manual U14801EJ3V1UD CHAPTER 13 PD78F9076 Figure 13 3 Example of Connection with Dedicated Flash Programmer a 3 wire serial UO Dedicated flash programmer HPD78F9076 SO SI CLKNote 1 GND b UART Dedicated flash programmer uPD78F9076 SO SI CL KNetes 1 2 GND c Pseudo 3 wire when PO is used Dedicated flash programmer uPD78F9076 RESET POO serial clock P02 serial input P01 serial output Notes 1 When supplying the system clock from a dedicated flash programmer connect the CLK and X1 pins and cut off the resonator on the board When using the clock oscillated by the on board resonator do not connect the CLK pin 2 When using UART with Flashpro Ill the clock of the resonator connected to the X1 pin must be used so do not connect the CLK pin Caution The Vob pin if already connected to the power supply must be connected to the VDD pin of the dedicated flash programmer When using the power supply connected to the Vpp pin supply voltage before starting programming User s Manual U14801EJ3V1UD If Flashpro Ill part no FL PR3 PG FP3 Flashpro IV part no FL PR4 PG FP4 is used as a dedicated flash programmer the following signals are generated for the uPD78F9076 For details refer to the manual of Flashpro CHAPTER 13 4PD78F9076 III Flashpro IV Table 13 3 Pin Connection List Signal Name 1 0 Pin Function Pin
9. e 8 bit manipulation Describe a symbol reserved by the assembler for the 8 bit manipulation instruction operand sfr This manipulation can also be specified with an address e 16 bit manipulation Describe a symbol reserved by the assembler for the 16 bit manipulation instruction operand When specifying an address describe an even address Table 3 3 lists the special function registers The meanings of the symbols in this table are as follows e Symbol Indicates the addresses of the implemented special function registers The symbols shown in this column are reserved words in the assembler and have already been defined in a header file called sfrbit h in the C compiler Therefore these symbols can be used as instruction operands if an assembler or integrated debugger is used e R W Indicates whether the special function register can be read or written R W Read write H Read only W Write only e Number of bits manipulated simultaneously Indicates the bit units 1 8 and 16 in which the special function register can be manipulated e After reset Indicates the status of the special function register when the RESET signal is input 50 Users Manual U14801EJ3V1UD CHAPTER 3 CPU ARCHITECTURE Table 3 3 Special Function Registers 1 2 Address Special Function Register SFR Name Symbol Number of Bits Manipulated Simultaneously 00H ME FF16H 16 bit compare register 90 creo w Kg Ed FFFFH FF17H FF18H 16 bit timer
10. Block Diagram of P10 to Plis 65 4 4 Block Diagram of P20 eie cioe teer a e de a etant 66 4 5 Block Diagram of P241 uu iti Sans ita Raed eec De Ee EP IE ER re nt Hle ae cos dep duas 67 4 6 Block Diagram of P22 E 68 4 7 Block Diagram OF P27 neo Dee EUR D HR GRE RR GREG 69 4 8 Block Diagram of P30 nd P3 uie a AE ee VIS Lodo py ee Debes 70 4 9 Format of Port Mode Register coccion cde cca d decret rer cd aptid vta ee 71 4 10 Format of Pull up Resistor Option Register 0 72 4 11 Format of Pull up Resistor Option Register Bi 73 5 1 Block Diagram of Clock Generator 75 5 2 Format of Processor Clock Control Hegleter A 76 5 3 X External Circuit of System Clock Oscillator sess nennen 77 5 4 Examples of Incorrect Resonator Connection esses eene enne enne nennen nennen 78 5 5 Switching Between System Clock and CPU Clock eene 81 6 1 Block Diagram of 16 Bit Timer 90 2 iiie Eee RU DD E eR ERR eile Sd eae eae eee 83 6 2 Format of 16 Bit Timer Mode Control Register 90 rrrrnnanvnnnnvnnenvnnnnvenenvnnnnrnnnnrnrrvrnnnnrnervrnnnnenervansrnnnesnrnsrvnnennn 86 6 3 Format of Buzzer Output Control Register 90 87 6 4 Format of Port Mode Register B oooconncccn nnccconnicccnnnnrcnnnnnncnrn nr 88 User s Manual U14801EJ3V1UD 15 LIST OF FIGURES 2 3 Figure No Title Page 6 5 Settings of 16 Bit Timer Mode Control Register 90 for Timer Interrupt Operation 89 6 6 Timing of Timer I
11. CHAPTER 3 CPU ARCHITECTURE 3 2 2 General purpose registers The general purpose registers consist of eight 8 bit registers X A C B E D L and H In addition to each register being used as an 8 bit register two 8 bit registers can be used in pairs as a 16 bit register AX BC DE and HL Registers can be described in terms of function names X A C B E D L H AX BC DE and HL and absolute names RO to R7 and RPO to RP3 Figure 3 14 General Purpose Register Configuration a Absolute names 16 bit processing 8 bit processing RP3 RP1 b Function names 16 bit processing 8 bit processing HL AX User s Manual U14801EJ3V1UD 49 CHAPTER 3 CPU ARCHITECTURE 3 2 3 Special function registers SFRs Unlike the general purpose registers each special function register has a special function The special function registers are allocated to the 256 byte area FFOOH to FFFFH The special function registers can be manipulated like the general purpose registers with operation transfer and bit manipulation instructions Manipulatable bit units 1 8 and 16 differ depending on the special function register type Each manipulation bit unit can be specified as follows e 1 bit manipulation Describe a symbol reserved by the assembler for the 1 bit manipulation instruction operand sfr bit This manipulation can also be specified with an address
12. CHAPTER 9 SERIAL INTERFACE 20 Figure 9 11 3 Wire Serial l O Mode Timing 7 7 xii Slave operation when DAP20 1 CKP20 1 SSE20 1 SS20 D SIO20 Write SCK20 SI20 INTCSI20 T Notes 1 The value of the last bit previously output is output 2 DOO is output until SS20 rises When SS20 is high SO20 is in a high impedance state 3 Transfer start Serial transfer is started by setting transfer data to the transmit shift register TXS20 SIO20 when the following two conditions are satisfied e Serial operation mode register 20 CSIM20 bit 7 CSIE20 1 e Internal serial clock is stopped or SCK20 is high after 8 bit serial transfer Caution If CSIE20 is set to 1 after data is written to TXS20 SIO20 transfer does not start The termination of 8 bit transfer stops the serial transfer automatically and generates the interrupt request signal INTCSI20 User s Manual U14801EJ3V1UD 149 CHAPTER 10 INTERRUPT FUNCTIONS 10 1 Interrupt Function Types The following two types of interrupt functions are used 1 Non maskable interrupt This interrupt is acknowledged unconditionally even if interrupts are disabled It does not undergo interrupt priority control and is given top priority over all other interrupt requests A standby release signal is generated An interrupt from the watchdog timer is the only non maskable interrupt source 2 Maskable interrupt These interrupts undergo mask control If two o
13. CPT90 Input Timing CPT90 218 User s Manual U14801EJ3V1UD CHAPTER 16 ELECTRICAL SPECIFICATIONS CONVENTIONAL PRODUCTS Serial Transfer Timing 3 wire serial UO mode SCK20 SI20 5020 Remark m 1 2 3 wire serial I O mode when using SS20 SS20 tkas2 tkos2 S020 Output data UART mode external clock input ASCK20 219 User s Manual U14801EJ3V1UD CHAPTER 16 ELECTRICAL SPECIFICATIONS CONVENTIONAL PRODUCTS Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics Ta 40 to 85 C Data retention power VoDDR aa voltage Release Release signal set time set time tera Oscillation stabilization twait Release by RESET Lues ee OO H Note 1 Notes 1 Oscillation stabilization wait time is the time in which the CPU operation is stopped to prevent unstable operation when oscillation is started 2 Selection of 2 fx 2 fx and 2 fx is possible using bits 0 to 2 OSTSO to OSTS2 of the oscillation stabilization time select register OSTS Remark fx System clock oscillation frequency Data Retention Timing STOP Mode Release by RESET Internal reset operation HALT mode j5 STOP mode mein Operation mode Data retention mode STOP instruction execution RESET twarr Data Retention Timing Standby Release Signal STOP Mode Release by Interrupt Signal HALT mode
14. Figure 5 4 Examples of Incorrect Resonator Connection 1 2 a Wiring too long c Wiring near high fluctuating current High current b Crossed signal line PORTn n 0 to 3 ZT d Current flowing through ground line of oscillator potential at points A B and C fluctuates VDD 3 Pis MN K A Je lo La High current 78 Users Manual U14801EJ3V1UD CHAPTER 5 CLOCK GENERATOR Figure 5 4 Examples of Incorrect Resonator Connection 2 2 e Signal is fetched 5 4 3 Frequency divider The frequency divider divides the system clock oscillator output fx and generates clocks User s Manual U14801EJ3V1UD 79 CHAPTER 5 CLOCK GENERATOR 5 5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU such as standby mode 80 e System clock fx e CPU clock fcru e Clock to peripheral hardware The operation of the clock generator is determined by the processor clock control register PCC as follows a b c a The slow mode 0 8 us at 10 0 MHz operation 1 6 us at 5 0 MHz operation of the system clock is selected when the RESET signal is generated PCC 02H While a low level is input to the RESET pin oscillation of the system clock is stopped Two types of minimum instruction execution time 0 2 us 0 8 us at 10 0 MHz operation 0 4 us 1 6 us at 5 0
15. Instruction code 0 0 1 0 1 1 0 1 3 4 7 Stack addressing Function The stack area is indirectly addressed with the stack pointer SP contents This addressing method is automatically employed when the PUSH POP subroutine call and RETURN instructions are executed or the register is saved restored upon interrupt request generation Stack addressing can be used to access the internal high speed RAM area only Description example In the case of PUSH DE Instruction code 1 0 1 0 1 0 1 0 User s Manual U14801EJ3V1UD 61 CHAPTER 4 PORT FUNCTIONS 4 1 Port Functions The uPD789074 Subseries is provided with the ports shown in Figure 4 1 These ports enable several types of control Table 4 1 lists the functions of each port These ports have digital I O port functions as well as alternate functions For the alternate functions refer to 2 1 Pin Function List Figure 4 1 Port Types Port 2 Port 0 Port 3 Port 1 62 User s Manual U14801EJ3V1UD CHAPTER 4 PORT FUNCTIONS Table 4 1 Port Functions P00 to P07 P10 to P15 P20 Port 0 8 bit I O port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by setting pull up resistor option register O PUO Port 1 Input 6 bit I O port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by setting pull up resistor option regis
16. PUO Pull up resistor option register O PM Port mode register RD Port 0 read signal WR Port 0 write signal 64 User s Manual U14801EJ3V1UD CHAPTER 4 PORT FUNCTIONS 4 2 2 Port 1 This is a 6 bit I O port with an output latch Port 1 can be set to input or output mode in 1 bit units by using port mode register 1 PM1 When pins P10 to P15 are used as input port pins on chip pull up resistors can be connected in 6 bit units by setting pull up resistor option register O PUO RESET input sets port 1 to input mode Figure 4 3 shows a block diagram of port 1 Figure 4 3 Block Diagram of P10 to P15 WRPuo gt P ch Selector Internal bus P10 to P15 Output latch P10 to P15 PM10 to PM15 PUO Pull up resistor option register O PM Port mode register RD Port 1 read signal WR Port 1 write signal User s Manual U14801EJ3V1UD 65 CHAPTER 4 PORT FUNCTIONS 4 2 3 Port 2 This is an 8 bit 1 O port with an output latch Port 2 can be set to input or output mode in 1 bit units by using port mode register 2 PM2 For pins P20 to P27 on chip pull up resistors can be connected in 1 bit units by setting pull up resistor option register B2 PUB2 Port 2 is also used for external interrupt input serial interface I O and timer I O RESET input sets port 2 to input mode Figures 4 4 through 4 7 show block diagrams of port 2 Caution When usin
17. and disable inversion control of timer output TOC90 0 Rewrite CR9O 16 bits Wait for more than one cycle of the count clock Clear the interrupt request flag TMIF90 Enable timer interrupts and timer output inversion lt Program example B gt When count clock 64 fx CPU clock fx TM90 VCT SETI TMMK90 Timer interrupt disable CLR1 TMC90 3 Timer output inversion disable MOVW AX xxyyH CR90 rewrite value setting MOVW CR90 AX CR90 rewriting NOP NOP NOP 32 Wait for 64 fx NOP NOP CLR1 TMIF90 Interrupt request flag clearing CLR1 TMMK9O Timer interrupt enable SET1 TMC90 3 Timer output inversion enable Note Wait for more than one cycle of the count clock after the instruction rewriting CR90 MOVW CR90 AX before clearing the interrupt request flag TMIF90 Users Manual U14801EJ3V1UD CHAPTER 7 8 BIT TIMER EVENT COUNTER 80 7 1 Functions of 8 Bit Timer Event Counter 80 8 bit timer event counter 80 has the following functions e Interval timer e External event counter e Square wave output e PWM output 1 8 bit interval timer When 8 bit timer event counter 80 is used as an interval timer it generates an interrupt at a time interval set in advance Table 7 1 Interval Time of 8 Bit Timer Event Counter 80 Minimum Interval Time Maximum Interval Time Resolution At fx 2 10 0 MHz At fx 5 0 MHz At fx 2 10 0 MHz At fx 2 5 0 MHz At fx 2 10 0 MHz At fx 2 5 0 MHz Operation Operation Oper
18. 1 9 Overview of Functions Part Number uPD789071 4uPD789072 4uPD789074 uPD78F9076 1PD789071 A uPD789072 A 4uPD789074 A Internal memory Mask ROM Flash memory High speed RAM 256 bytes 0 2 0 8 us 8 10 0 MHz Voo 4 5 to 5 5 V operation with system clock General purpose registers 8 bits x 8 registers Instruction set 16 bit operations Bit manipulations such as set reset and test I O ports CMOS I O 24 Serial interface Switchable between 3 wire serial UO and UART modes 1 channel Timers 16 bit timer 1 channel 8 bit timer event counter 1 channel Watchdog timer 1 channel Timer outputs 30 pin plastic SSOP 7 62 mm 300 The outline of the timers are as follows lip S 16 Bit Timer 90 8 Bit Timer Event Counter Watchdog Timer 80 mode External event counter 1 channel rm fd o meme 1 mew 1 NE om m S Note The watchdog timer provides a watchdog timer function and interval timer function Use either of the functions 28 User s Manual U14801EJ3V1UD CHAPTER 1 GENERAL 1 10 Differences Between Standard Quality Grade Products and A Products The differences between standard grade products uPD789071 789072 789074 and A products uPD789071 A 789072 A 789074 A are shown in Table 1 2 Table 1 2 Differences Between Standard Quality Grade Products and A Products Standard Products A Products Electrical specifications Refer to CHAPTER 15 ELECRIDAL
19. 10 4 1 Non maskable interrupt request acknowledgment operation The non maskable interrupt request is unconditionally acknowledged even when interrupts are disabled It is not subject to interrupt priority control and takes precedence over all other interrupts When the non maskable interrupt request is acknowledged the PSW and PC are saved to the stack in that order the IE flag is reset to O the contents of the vector table are loaded to the PC and then program execution branches Figure 10 6 shows the flowchart from non maskable interrupt request generation to acknowledgment Figure 10 7 shows the timing of non maskable interrupt request acknowledgment Figure 10 8 shows the acknowledgment operation if multiple non maskable interrupts are generated Caution During a non maskable interrupt service program execution do not input another non maskable interrupt request if it is input the service program will be interrupted and the new interrupt request will be acknowledged 158 User s Manual U14801EJ3V1UD CHAPTER 10 INTERRUPT FUNCTIONS Figure 10 6 Flowchart from Non Maskable Interrupt Request Generation to Acknowledgment WDTM4 1 watchdog timer mode is selected Yes WDT Overflows Yes WDTM3 0 non maskable interrupt is selected Yes Interrupt request is generated Interrupt servicing is started Interval timer Reset processing WDTM Watchdog timer mode register WDT Watchdog timer
20. C 1 Register Name Index Alphabetic Order 16 bit capture register 90 T O OO iE RO p PERS E IRR RUE EN ARI TEN ERI 16 bit compare register 90 Co 16 bit timer counter 90 TM90 EEN 16 bit timer mode control register 90 TM 8 bit compare regist r 80 R80 etc dci ti tonio Eed de res py ias 8 bit timer counter 80 TMB cirios ane socer i Free dd eee inne NEES cet a eaa bakmenn dead 8 bit timer mode control register 80 TM A Asynchronous serial interface mode register 20 AGIM30 nennen nnns 1 Asynchronous serial interface status register 20 AGlIG20 ennemis 1 B Baud rate generator control register 20 DBPOC 20 1 Buzzer output control register 90 BZC90 ssssssssssssesseeeeeeneenneenneee nnne trennen nenne nnns etre nennen E External interrupt mode register O INTMO sssseeseeeeeeeeeeeeennneeneennneen nennen nnne n nnne n nnne erret 1 DI Interrupt mask flag register 0 1 MKO Mk 1 Interrupt request flag register 0 1 IFO JET 1 0 Oscillation stabilization time selection register OST 1 P Port 0 PO aii ade o at Port T PI LEER Port2 P2 smia rate aedi ean een ae ina endene Port 3 PP take ere Port mode register 0 PMO eto at Smeden Port mode register 1 PM 2 dar e deep ideae p re te ufine hane Port mode register PM edm dite Port mode register 3 PMI iita c ce cc deci e Aid eg e dee b dede eae de dus Processor c
21. Figure 7 3 Format of Port Mode Register 2 Symbol 7 6 Address After reset R W 5 4 3 2 1 0 PM2 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 FF22H FFH R W P2n pin input output mode selection n O to 5 o Output mode output buffer on Input mode output buffer off 100 User s Manual U14801EJ3V1UD CHAPTER 7 8 BIT TIMER EVENT COUNTER 80 7 4 Operation of 8 Bit Timer Event Counter 80 7 4 1 Operation as interval timer The interval timer repeatedly generates an interrupt at a time interval specified by the count value preset in 8 bit compare register 80 CR80 To operate 8 bit timer event counter 80 as an interval timer settings must be made in the following sequence lt 1 gt Disable operation of 8 bit timer counter 80 TM80 TCE80 bit 7 of 8 bit timer mode control register 80 TMC80 0 lt 2 gt Set the count clock of 8 bit timer event counter 80 see Table 7 4 lt 3 gt Set a count value in CR80 lt 4 gt Enable the operation of TM80 TCE80 1 When the count value of 8 bit timer counter 80 TM80 matches the value set in CR80 TM80 is cleared to 0 and continues counting At the same time an interrupt request signal INTTM80 is generated Table 7 4 shows the interval time and Figure 7 4 shows the timing of the interval timer operation Cautions 1 Stop the timer operation before rewriting CR80 If CR80 is rewritten while the timer operation is enabled a match signal may be generated immediately at the point o
22. RECOMMENDED SOLDERING CONDITIONS Modification of description of A 5 Debugging Tools Hardware APPENDIX A DEVELOPMENT TOOLS Addition of chapter APPENDIX B NOTES ON TARGET SYSTEM DESIGN 3rd Edition Modification Version 238 Modification of 1 4 Ordering Information Modification of 1 5 Quality Grades CHAPTER 1 GENERAL Addition of Table 18 1 Surface Mounting Type Soldering Conditions 2 2 User s Manual U14801EJ3V1UD CHAPTER 18 RECOMMENDED SOLDERING CONDITIONS
23. RXB20 enable the receive operation RXE20 1 Remark If the receive data must be read after the receive operation has been disabled RXE20 0 use either method below a After waiting for 1 cycle or more of the source clock selected by BRGC20 set RXE20 to 0 and then read the receive data b Set bit 2 DIR20 of serial operation mode register 20 CSIM20 to 1 and read the receive data Example program for a BRGC29 00H source clock fx 2 INTRXE Reception completion interrupt routine NOP 2 clocks CLR1 RXE20 Stop reception operation MOV A RXB20 Read receive data Example program for b INTRXE Reception completion interrupt routine SET1 CSIM20 2 Set the DIR20 flag to LSB first CLR1 RXE20 Stop reception operation MOV A RXB20 Read receive data 138 User s Manual U14801EJ3V1UD CHAPTER 9 SERIAL INTERFACE 20 3 Cautions related to UART mode a When bit 7 TXE20 of asynchronous serial interface mode register 20 ASIM20 is cleared during transmission be sure to set transmit shift register 20 TXS20 to FFH then set TXE20 to 1 before executing the next transmission b When bit 6 RXE20 of asynchronous serial interface mode register 20 ASIM20 is cleared during reception receive buffer register 20 RXB20 and the receive completion interrupt INTSR20 are as I follows INTSR20 When RXE20 is set to 0 at the time indicated by lt 1 gt RXB20 holds the previou
24. Remark The broken lines indicate the case where the interrupt request that has released standby mode is acknowledged b Releasing by RESET input When STOP mode is released by the RESET signal the reset operation is performed after the oscillation stabilization time has elapsed Figure 11 5 Releasing STOP Mode by RESET Input STOP instruction RESET Y signal Wait 215 f Note m gt Oscillation Operating Reset stabilization Operating mode STOP mode period wait status mode Oscillation Clock Oscillation stop Oscillation gt gt Note 3 28 ms at fx 10 0 MHz operation 6 55 ms at fx 5 0 MHz operation Remark fx System clock oscillation frequency Table 11 4 Operation After Releasing STOP Mode Maskable interrupt request KJENN Executes next address instruction oo 1 feeosmemsemeng mr ERT Retains STOP mode x Don t care 170 User s Manual U14801EJ3V1UD CHAPTER 12 RESET FUNCTION The following two operations are available to generate reset signals 1 External reset input by RESET signal input 2 Internal reset by watchdog timer program loop time detection External and internal reset have no functional differences In both cases program execution starts at the address at 0000H and 0001H by reset signal input When a low level is input to the RESET pin or the watchdog timer overflows a reset is applied and each hardware is set to the status shown in Ta
25. is generated Figure 6 8 shows the timing of timer output see Table 6 2 for the interval time of 16 bit timer 90 Figure 6 8 Timer Output Timing eg O AAA TM90 count value DOSE 0001H EE FFFFH y 0000HX0 0001H ROUTERS INTTM90 d l i i A b A Interrupt Interrupt acknowledgment acknowledgment TOgow i TOF90 EE NT I ES cm flag set Note The TO90 initial value becomes low level during output enable TOE90 1 Remark N 0000H to FFFFH User s Manual U14801EJ3V1UD 91 CHAPTER 6 16 BIT TIMER 90 6 4 3 Capture operation The capture operation consists of latching the count value of 16 bit timer counter 90 TM90 into a capture register in synchronization with a capture trigger and retaining the count value Set TMC90 as shown in Figure 6 9 to allow 16 bit timer 90 to start the capture operation Figure 6 9 Settings of 16 Bit Timer Mode Control Register 90 for Capture Operation TOD90 TOF90 CPT901 CPT900 TOC90 TCL901 TCL900 TOE90 TMC90 EN on O on ot om on Count clock selection Capture edge selection see Table 6 3 16 bit capture register 90 TCP90 starts a capture operation after the CPT90 capture trigger edge is detected and latches and retains the count value of 16 bit timer counter 90 TCP90 fetches the count value within 2 clocks and retains the count value until the next capture edge detection Table 6 3 and Figure 6 10 show the settings of the captu
26. 0 gt 1 108 User s Manual U14801EJ3V1UD CHAPTER 8 WATCHDOG TIMER 8 1 Watchdog Timer Functions The watchdog timer has the following functions e Watchdog timer e Interval timer Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode register WDTM 1 Watchdog timer The watchdog timer is used to detect inadvertent program loops When an inadvertent loop is detected a non maskable interrupt or a RESET signal can be generated Table 8 1 Inadvertent Loop Detection Time of Watchdog Timer Inadvertent Loop Detection Time At fx 10 0 MHz Operation At fx 2 5 0 MHz Operation 2 x 1 fx 205 us 410 us Note Expanded specification products only Remark fx System clock oscillation frequency 2 Interval timer The interval timer generates an interrupt at an arbitrary preset interval Table 8 2 Interval Time At fx 10 0 MHz Operation At fx 5 0 MHz Operation 2 x 1 fx 205 us 410 us Note Expanded specification products only Remark fx System clock oscillation frequency User s Manual U14801EJ3V1UD 109 CHAPTER 8 WATCHDOG TIMER 8 2 Watchdog Timer Configuration The watchdog timer includes the following hardware Table 8 3 Configuration of Watchdog Timer Control registers Watchdog timer clock selection register WDCS Watchdog timer mode register WDTM Figure 8 1 Block Diagram of Watchdog Timer Internal bus 7 bit counter Controller WDCS2 WDCS Run
27. 0 6 0 15 S30MC 65 5A4 2 Cl tv Z alrga e T oO mnim O ojo 222 User s Manual U14801EJ3V1UD CHAPTER 18 RECOMMENDED SOLDERING CONDITIONS The PD789071 789072 and 789074 should be soldered and mounted under the following recommended conditions For soldering methods and conditions other than those recommended below contact an NEC Electronics sales representative For technical information see the following website Semiconductor Device Mount Manual http www necel com pkg en mount index html Table 18 1 Surface Mounting Type Soldering Conditions 1 2 4 PD789071MC xxx 5A4 30 pin plastic SSOP 7 62 mm 300 uPD789072MC xxx 5A4 30 pin plastic SSOP 7 62 mm 300 uPD789074MC xxx 5A4 30 pin plastic SSOP 7 62 mm 300 uPD789071MC A xxx 5A4 30 pin plastic SSOP 7 62 mm 300 uPD789072MC A xxx 5A4 30 pin plastic SSOP 7 62 mm 300 uPD789074MC A xxx 5A4 30 pin plastic SSOP 7 62 mm 300 Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature 235 C Time 30 seconds max IR35 00 3 at 210 C or higher Count Three times or less Package peak temperature 215 C Time 40 seconds max VP15 00 3 at 200 C or higher Count Three times or less Wave soldering Solder bath temperature 260 C max Time 10 seconds max Count WS60 00 1 Once Preheating temperature 120 C max package surface temperature Partial heatin
28. 10 2 Interrupt Request Signals and Corresponding Flag 153 10 8 Time from Generation of Maskable Interrupt Request to Geniclng 160 141 Operation Stat ses im HALT Mode idee dd EA 167 11 2 Operation After Releasing HALT Mode 168 11 3 Operation Statuses in STOP Mode 169 11 4 Operation After Releasing STOP Mode A 170 12 1 Status of Hardware After Reset AAA 173 19 1 Differences Between Flash Memory and Mask ROM Versions conan enne 174 13 2 Communication Mode Lists cuca la ia de 176 1853 Pin Conne ction List Eege eee EG 178 14 1 Operand Identifiers and Description Methods AAA 185 18 1 Surface Mounting Type Soldering Conditions eee 223 User s Manual U14801EJ3V1UD 19 CHAPTER 1 GENERAL x 1 1 Expanded Specification Products and Conventional Products Expanded specification products and conventional products refer to the following products Expanded specification products Products with a rank other than K e Mask ROM versions for which orders were received after December 1 2001 e PD78F9076 shipped after January 1 2002 Conventional products Products with rank K e Products other than the above expanded specification products Note The rank is indicated by the 5th digit from the left in the lot number marked on the package Lot number O O OO A A A Year code Week code Rank Expanded specification products and conventional products differ in operating frequency ratings The differences are shown in Table 1 1 Table 1 1 D
29. 14 1 Operation 14 1 1 Operand identifiers and description methods Operands are described in the Operand column of each instruction in accordance with the description method of the instruction operand identifier refer to the assembler specifications for details When there are two or more description methods select one of them Uppercase letters and the symbols and are keywords and are described as they are Each symbol has the following meaning e Immediate data specification e Absolute address specification e Relative address specification e Indirect address specification In the case of immediate data describe an appropriate numeric value or a label When using a label be sure to describe the st and symbols For operand register identifiers r and rp either function names X A C etc or absolute names names in parentheses in the table below RO R1 R2 etc can be used for description Table 14 1 Operand Identifiers and Description Methods Identifier Description Method X RO A R1 C R2 B R3 E R4 D R5 L R6 H R7 rp AX RPO BC RP1 DE RP2 HL RP3 sfr Special function register symbol saddr FE20H to FF1FH Immediate data or labels saddrp FE20H to FF1FH Immediate data or labels even addresses only addr16 0000H to FFFFH Immediate data or labels only even addresses for 16 bit data transfer instructions addr5 0040H to 007FH Immediate data or labels even
30. 2 Format of Watchdog Timer Clock Selection Register A 111 8 3 Format of Watchdog Timer Mode Register AAA 112 9 1 Block Diagram of Serial Interface 20 116 9 2 Block Diagram of Baud Rate Generator 20 117 9 3 Format of Serial Operation Mode Register 20 119 9 4 Format of Asynchronous Serial Interface Mode Register 20 120 9 5 Format of Asynchronous Serial Interface Status Register 20 122 9 6 Format of Baud Rate Generator Control Register 20 123 9 7 Format of Asynchronous Serial Interface Transmit Receive Data 133 9 8 Asynchronous Serial Interface Transmission Completion Interrupt Timing 135 9 9 Asynchronous Serial Interface Reception Completion Interrupt Timing 136 9 10 elen Uu WEE 137 9 11 3 Wire Serial HO Mode Timing EE 143 10 1 Basic Configuration of Interrupt Function nennen nnne neret nnns nnns 152 10 2 Format of Interrupt Request Flag Register 154 10 3 Format of Interrupt Mask Flag Register AAA 155 16 User s Manual U14801EJ8V1UD LIST OF FIGURES 3 3 Figure No Title Page 10 4 Format of External Interrupt Mode Register 0 156 10 5 Program Status Word Configuration srranvrnnvrnnnvrnnnvrnnnvrnenvrnnnvnnervrnnnvnnesvrnsnvenenvnnsnvnnernnnsnnnesvnnsnnenesrenennnnennne 157 10 6 Flowchart from Non Maskable Interrupt Request Generation to Acknowledoment 159 10 7 Timing of Non Maskable Interrupt Request Acknowledgment AA 159 10 8 Acknowledgment of Non Maskable Interrupt Request AAA 159 10 9 Interrupt Reque
31. 7 4 Operation of 8 Bit Timer Event Counter 80 rrrrvrnnnavnnnnnvnnnnvnnnnvnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnnenn 101 7 4 1 Oper tion s interval timer Neie dcus ectetuer coated e ce e reddet uaa 101 7 4 2 Operation as external event Counter nennen nene enne nens 103 7 4 3 Operation as square wave OUIDU nennen nennen nennen nennen 104 7 4 4 Operation as PWM Output nennen nennen nnne nennen enne nnn ennt nennen 106 7 5 Notes on Using 8 Bit Timer Event Counter 80 rrrnnavnnnnnvnnnnvnnnnvnnnnnvnnnnnnnnnvnnnnnvnnnnnnnnnnnnnnnenn 107 CHAPTER 8 WATCHDOG TIMER snnnonnnnnnnvnvnnnnnvnnennnnvnnnennnnnnvennnnnnnennnnnnnvennnnnnnennnnnnnennnnnnnnennnnnnnennnnnnennn 109 8 1 Watchdog Timer FunctionS sr rrnsnnvnnnnnnnnvnnnnnnnvnnnnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnvennnnnnnnnnnnnnnnnnnnnnneennnnnnr 109 8 2 Watchdog Timer Configuration rrssrrnnvvnnnnvnnnnnvnnnnvnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnnnn 110 8 3 Watchdog Timer Control RegisterS mr rrnrsvrnnnavnnnnvnnnnvnnnnnvnnnnnnnnnvnnnnnvnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnneenn 111 8 4 Watchdog Timer Operation mserrrnvnnnnnvnnnnvvnnnnvnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnennn 113 8 4 1 Operation as watchdog mer 113 8 4 2 Operation as interval timer esssesssssesseeseseenene enne nnne nennen nnne neret enn 114 CHAPTER 9 SERIAL INTERFACE 20 evoveernnnvnvennnnnnvennnnnnnvennnnnnnennnnnnnnennnnnnnennnnnnnnennnnnneennnnnnnnenn
32. 9 SERIAL INTERFACE 20 c Baud rate generator control register 20 BRGC20 BRGC20 is set with an 8 bit memory manipulation instruction RESET input clears BRGC20 to 00H Symbol 7 6 5 4 Address After reset R W 3 2 1 0 TPS203 TPS202 TPS201 TPS200 Selection of source clock for baud rate generator n Pe fe fe fe we some CT 7 ef CI CIO we EII fame CT ee CI ICI pe pem em CT ICO CIO ICI we ese fem IEC 78 1 kHz 39 1 kHz 1 39 1 kHz 19 5 kHz Other than above Setting prohibited EE CTA 1 1 0 Note Expanded specification products only Cautions 1 When writing to BRGC20 is performed during a communication operation the baud rate generator output is disrupted and communication cannot be performed normally Be sure not to write to BRGC20 during a communication operation 2 Be sure not to select n 1 during operation at fx gt 5 0 MHz in 3 wire serial l O mode because the resulting serial clock exceeds the rated range 3 When the external input clock is selected set port mode register 2 PM2 to input mode Remarks 1 fx System clock oscillation frequency 2 n Value determined by setting TPS200 through TPS203 1 n lt 8 If the internal clock is used as the serial clock for 3 wire serial I O mode set bits TPS200 to TPS203 to set the frequency of the serial clock To obtain the frequency to be set use the following expression When an external serial clock is used setting BRGC20 is not necessary f Seri
33. CHAPTER 5 CLOCK GENERATOR nnnnnvnvennnnnnnvennnnnnnvennnnnnevennnnevennnnnevvnnnnnevsnnnnnevvnnnnnevannnnnennnnnnnennnnnnneene 75 5 1 Clock Generator Functions rrrssvrnnnnvnnnnvvnnnnnnnnnnnnnnnvnnnnnvnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnnnennnnnnnnnnnnnnner 75 5 2 Clock Generator Configuration rrnssvrnnnvnnnnnnvnnnnnennnnnnnnnvnnnnnnnnnnnnnnnvennnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnner 75 5 3 Clock Generator Control Register rrsvrrnsnavnnnnvvnnnvvnnnnvnnnnnnnnnnnnnnnvnnnnnvnnnnnnnnnnnnnnnvennnnnnnnnnnnnnnen 76 5 4 System Clock Oscillators rrnsvnnnnavnnnnnvnnnnnnnnnvnnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnnennnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnne 77 5 4 1 System clock oscillator xs A tri S ge eto te rice e Ep bp eie baade 77 5 4 2 Examples of incorrect resonator Copnnechon emen 78 5 4 3 Frequency divider eruan a E eee adenine ieee 79 5 5 Clock Generator Operation rrnnssvnnnnnvnnnnvnnnnnnvnnnnnvnnnvnnnnnvnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnnnennnnnnnnnnnnnnner 80 5 6 Changing Setting of CPU CIlock rrrssrnnnnnvnnnnvnnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnen 81 5 6 1 Time required for switching CPU clock 81 5 6 2 Switching CPU Clock EE 81 CHAPTER 6 16 BIT TIMER 90 0 ccccccsesscccssnsccesesnneesssnncessesnneeesesnneeesesnaceessseneessesnncesseseneeesessnneensas 82 6 1 Functions of 16 Bit Timer 90 rssrvvnnnnnnvonnnnnnnvennnnnnvnnnnnnnvennnnnnvnnnnnnnvennnnnnennnnnnnvennnnnnvene
34. Clocks Operation Z AC CY wx umm s ps pL EAT REC CEET E mme fefelfseme SSCSC dSCCS ae pa Pa fae AE Em felfafe E hm fe LX uma EI emen T as NET e CEEI RN ma a p re LL en s ps eem Deme EC CCT CCT EC pwee ENEE OTWOlWOINININININ INIT ajojo Du a p het T EE EELER ue pa E ma ECT ee amy s eet Imus p s eue A HL byte HL byte A 2 A c HL byte S ES SS ERR pee LLL Dem s s emm EE Tae ipa s m O e peo O e COS f s seem Notes 1 Exceptr A 2 Exceptr A X Remark One instruction clock cycle is one CPU clock cycle fcru selected by the processor clock control register PCC User s Manual U14801EJ3V1UD 187 CHAPTER 14 INSTRUCTION SET OVERVIEW Mnemonic Operand Bytes Clocks Operation Z AC CY ww ems fefe e Dmm Se fe fm mmm 2 s wmm mw Dem tt re LLL mmm FETO epa Dow mem ECTS eje LLL w jme EO cem EEE 2 EE anne fo fe em pb am C amma fe fo E poer eee FET saddr CY lt saddr byte CY ES DS fe e oea Tro Dem HON fa rorem ENE EE EC EO A CY A adare CY EC EC N A CY amp A HL byte CY Bm ECC EE lee ES NETA Area ENERO e Ties am tr e Acree fo arco gt e rocno O Note Only when rp BC DE or HL Remark One instruction clock cycle is one CPU clock cycle fcru selected by the processor clock control register PCC 188 User s Manual U14801EJ3V1UD CHAPTER 14 INSTRUC
35. MHz in UART mode because the resulting serial clock exceeds the rated range 4 Be sure not to select n 1 during operation at fx gt 5 0 MHz in 3 wire serial UO mode because the resulting serial clock exceeds the rated range 5 When the external input clock is selected set port mode register 2 PM2 to input mode Remarks 1 fx System clock oscillation frequency 2 n Value determined by setting TPS200 through TPS203 1 lt n lt 8 User s Manual U14801EJ3V1UD 123 CHAPTER 9 SERIAL INTERFACE 20 The baud rate transmit receive clock to be generated is either a signal generated by dividing the system clock or a signal generated by dividing the clock input from the ASCK20 pin a Generation of baud rate transmit receive clock from system clock The transmit receive clock is generated by dividing the system clock The baud rate of a clock generated from the system clock is estimated by using the following expression fx Baud rate AE TN bps fx System clock oscillation frequency n Value determined by settings of TPS200 through TPS203 as shown in Figure 9 6 2 lt n lt 8 Table 9 3 Example of Relationship Between System Clock and Baud Rate Baud Rate fx 10 0 MHz Dr fx 2 5 0 MHz fx 2 4 9152 MHz teg Eneco Servae ESE BRGG2O Set Value Ee BRGCAO Set Value aja ooo T mm e m hm fo x Note Expanded specification products only Cautions 1 Be sure not to select n 1 during operation at fx gt 2 5 MHz bec
36. Multiple interrupt servicing eeeeeeeeeeeeeeeeneeenen nnne nennen nennen nr 162 10 4 4 Interrupt request hold a etd acd tet ee E es 164 12 Users Manual U14801EJ3V1UD CHAPTER 11 STANDBY FUNCTION ijmmnnnvnnnvvnnnvnnnvnnnnennnennnennnnnnnnennnnnnnnnnnnennvnnnvnnnvnnneenneennnennevnenunnenner 165 11 1 Standby Function and Configuration rrrarrnnnnvnnnnnnnnnvnnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnennn 165 TT Standby e ot oce tette cs 165 11 1 2 Standby function control register sssssssseeeeeeneeneen nennen 166 11 2 Operation of Standby Function rsrrnnnnnvnnnvvnnnnnvnnnnnvnnnvnnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnenn 167 11 2 1 HALT mode ua 167 11 22 STOP M de EE 169 CHAPTER 12 RESET FUNCTION id a SEN dE NEEN ENER 171 CHAPTER 13 2PD78F9076 000000 aa 174 13 1 Flash Memory CharacteristiCS rrrsrrnnnnnnnnnvvnnnnnvnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnenn 175 13 1 1 Programming environment EE 175 13 1 2 Communication mode AA 176 13 4 3 On board pin connections science trees ee ide dees decine ae neared 179 18 1 4 Connection of adapter for flash writing ronvnnnnrnnonvnnnnrnnnnvnnnnrnnnnvnnnnvnnnnrnnrnrnnrnrnnenvnnenrnnenvnnnnrenn 182 CHAPTER 14 INSTRUCTION SET OVERVIEW ernnnnvennnnnvnnnnvnnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnennnn 185 14 1 Operation EE 185 14 1 1 Operand identifiers
37. Name 3 Wire Serial I O UART VPP1 Output Write voltage Ver O O VPP2 x x VDD UO Voo voltage generation von or or voltage monitoring GND Ground Vss CLK Output Clock output x1 O O RESET Output Reset signal RESET O O SI Input Receive signal SO20 TxD20 P01 SO Output Transmit signal SI20 RxD20 P02 SCK Output Transfer clock SCK20 P00 x HS Input Handshake signal x x Note Von voltage must be supplied before programming is started Remark Pin must be connected 178 User s Manual U14801EJ3V1UD O If the signal is supplied on the target board pin does not need to be connected x Pin does not need to be connected CHAPTER 13 PD78F9076 13 1 3 On board pin connections When programming on the target system provide a connector on the target system to connect to the dedicated flash programmer There may be cases in which an on board function that switches from the normal operation mode to flash memory programming mode is required lt Vpp pin Input O V to the Ver pin in the normal operation mode A writing voltage of 10 0 V TYP is supplied to the Ver pin in the flash memory programming mode Therefore connect the Ver pin as follows 1 Connect a pull down resistor of RVPP 10 KQ to the Vp pin 2 Set the jumper on the board to switch the input of Ver pin to the programmer side or directly to GND The following shows an example of Vrr pin connection Figure 13 4 Ver Pin Co
38. PMO to PM3 The port mode registers separately set each port bit to either input or output Each port mode register is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets the port mode registers to FFH When port pins are used for alternate functions the corresponding port mode register and output latch must be set or reset as described in Table 4 3 Caution When port 2 is acting as an output port and its output level is changed an interrupt request flag is set because this port is also used as the input for an external interrupt To use port 2 in output mode therefore the interrupt mask flag must be set to 1 in advance Figure 4 9 Format of Port Mode Register Symbol 7 6 Address After reset R W 5 4 3 2 1 0 PMmn Pmn pin input output mode selection m 0 to 3 n 0to 7 Ea Output mode output buffer on Input mode output buffer off User s Manual U14801EJ3V1UD 71 Symbol 7 6 5 4 lt 3 gt 2 lt 1 gt PU 72 CHAPTER 4 PORT FUNCTIONS Table 4 3 Port Mode Register and Output Latch Settings for Using Alternate Functions om om IO ES m mme fom IO ao m mm fom i ao Caution When using the pins of port 2 for the serial interface the I O or output latch must be set according to the function to be used For details of the settings see Table 9 2 Operation Mode Settings of Serial Interface 20 Remark x Don t care PMxx Port mode register Pxx Port output latch 2 P
39. SPECIFICATIONS EXPANDED SPECIFICATION PRODUCTS and CHAPTER 16 ELECTRICAL SPECIFICATIONS CONVENTIONAL PRODUCTS User s Manual U14801EJ3V1UD 29 CHAPTER 2 PIN FUNCTIONS 2 1 Pin Function List 1 Port pins POO to P07 I O Porto 8 bit I O port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by setting pull up resistor option register O PUO P10to P15 I O Port 1 Input 6 bit I O port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by setting pull up resistor option register 0 PUO P20 1 0 Port 2 Input SCK20 ASCK20 8 bit I O port P21 SO20 TxD20 Input output can be specified in 1 bit units P22 An on chip pull up resistor can be specified by setting pull up resistor SI20 RxD20 option register B2 PUB2 SS20 INTPO INTP1 INTP2 CPT90 TI80 TO80 Port 3 Input TO90 2 bit I O port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be BZO90 specified by setting pull up resistor option register O PUO 30 User s Manual U14801EJ3V1UD CHAPTER 2 PIN FUNCTIONS 2 Non port pins eme vo umeion aerea Aremate Function Input External interrupt input for which the valid edge rising edge Input P24 Lr falling edge or both rising and falling edges can be specified EE Connecting crystal resonator for system cloc
40. a status in which it can be acknowledged is set Figure 10 9 shows the algorithm of interrupt requests acknowledgment When a maskable interrupt request is acknowledged the contents of the PSW and PC are saved to the stack in that order the IE flag is reset to 0 and the data in the vector table determined for each interrupt request is loaded to the PC and execution branches To return from interrupt servicing use the RETI instruction 160 User s Manual U14801EJ3V1UD CHAPTER 10 INTERRUPT FUNCTIONS Figure 10 9 Interrupt Request Acknowledgment Processing Algorithm Yes Interrupt request generated No Interrupt request pending No Yes Interrupt request pending Vectored interrupt servicing xxIF Interrupt request flag xxMK Interrupt mask flag IE Flag to control maskable interrupt request acknowledgment 1 enable 0 disable User s Manual U14801EJ3V1UD 161 CHAPTER 10 INTERRUPT FUNCTIONS Figure 10 10 Interrupt Request Acknowledgment Timing Example of MOV A r 8 clocks Ede por A gr ae EN Saving PSW and PC jump A CPU MOV A r Interrupt servicing program Interrupt If an interrupt request flag xxIF is set before an instruction clock n n 4 to 10 under execution becomes n 1 the interrupt is acknowledged after the instruction under execution is complete Figure 10 10 shows an example of the interrupt request acknowledgment timing for an 8 bit data transfer instruction MOV A r
41. and description methods AA 185 14 1 2 Description of Operation column 186 14 1 3 Description of Flag cColUmMM isi i i enne enne nnne nnne nennen nnne nnns 186 14 2 Operation aii 187 14 3 Instructions Listed by Addressing Type rrnnnnnnnnvnnnnnnnnvnnnnnnnvnnnnnnnvnnnnnnnnnnnnnnnnennnnnnnennnnnnnennnnnner 192 CHAPTER 15 ELECTRICAL SPECIFICATIONS EXPANDED SPECIFICATION PRODUCTS 195 CHAPTER 16 ELECTRICAL SPECIFICATIONS CONVENTIONAL PRODUCTS 209 CHAPTER 17 PACKAGE DRAWING elena ere ds 222 CHAPTER 18 RECOMMENDED SOLDERING CONDITIONS eese 223 APPENDIX A DEVELOPMENT TOOLS eege in ease ue 225 AT Software Package iii tia adi 227 A 2 Language Processing Software rrnsvrnnnvnnnnnnvnnnnvnnnnnvnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnnvennnnnnnnnnnnnnennnnnn 227 A 3 Control Software EE ENEE la Ee 228 AA Flash Memory Writing Tools nnssvvnnnnnnvnnnnnnnnvnnnnnnnvnnennnnnvnnennnnnnnennnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnenr 229 Ab Debugging Tools Hardware mmmssrrnnnnvnnnnvnnnnnnvnnnnnvnnnnvnnnnvnnnnnnnnnnnnnnnvennnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 229 Ap Debugging Tools Software rrrnnrnnnnnvnnnnvnnnnnnvnnnnvvnnnnnnnnnvnnnnnnnnnnnnnnnvennnnnnnnnnnnnnnnnnnnnennnnnnnnnnnnnnn 230 APPENDIX B NOTES ON TARGET SYSTEM DESIGN eese enne nennen nnns 231 User s Manual U14801EJ3V1UD 13 APPENDIX C REGISTER INDEX C 1 Reg
42. as a rule switch on the external power supply after switching on the internal power supply When switching the power supply off as a rule switch off the external power supply and then the internal power supply Use of the reverse power on off sequences may result in the application of an overvoltage to the internal elements of the device causing malfunction and degradation of internal elements due to the passage of an abnormal current The correct power on off sequence must be judged separately for each device and according to related specifications governing the device INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an UO pull up power supply while the device is not powered The current injection that results from input of such a signal or I O pull up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device User s Manual U14801EJ3V1UD EEPROM and FIP are trademarks of NEC Electronics Corporation Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and or other countries PC AT is a trademark of International Business Machines Corporation HP9000 series 700 and HP UX are trademarks of Hewlett Packard Company SPARCstation is a tradem
43. is used as the ceramic resonator see the figure below This is not necessary when using one of the other recommended resonators CSBLA1M00J58 BO CSBFB1M00J58 R1 ID Caution The oscillator constant is a reference value based on evaluation in specific environments by the Rd C1 resonator manufacturer If the oscillator characteristics need to be optimized in the actual application request the resonator manufacturer for evaluation on the implementation circuit Note that the oscillation voltage and oscillation frequency merely indicate the characteristics of the oscillator Use the internal operation conditions of the uPD78F9076 within the specifications of the DC and AC characteristics 212 User s Manual U14801EJ3V1UD CHAPTER 16 ELECTRICAL SPECIFICATIONS CONVENTIONAL PRODUCTS DC Characteristics Ta 40 to 85 C Von 1 8 to 5 5 V Ce o ee pm pe pe Output current Per Perpn uPD78907x 78F9076 high Total for all pins Per ETERNI uPD78907x A Total for all Total for all pins Output current low uPD78907x 78F9076 Total for all Total for all pins uPD78907x A Total for all Total for all pins E Input voltage high ES P00 to P07 P10 to P15 EE A E E bromea ve Keeser usc v fv Input voltage low Vu POO to PO7 P10 to P15 vo eressv o pame Y Ve tawssv_ o ome v Gg Vessossv o 94 v wesuwssv 9 9 v Von 4 5 to 5 5 V lon 1 mA V
44. kQ is required when CSBLA1M00J58 BO or CSBFB1M00J58 R1 1 0 MHz manufactured by Murata Mfg Co Ltd is used as the ceramic resonator see the figure below This is not necessary when using one of the other recommended resonators 198 CSBLA1M00J58 BO CSBFB1M00J58 R1 m Rd C1 User s Manual U14801EJ3V1UD CHAPTER 15 ELECTRICAL SPECIFICATIONS EXPANDED SPECIFICATION PRODUCTS Caution The oscillator constant is a reference value based on evaluation in specific environments by the resonator manufacturer If the oscillator characteristics need to be optimized in the actual application request the resonator manufacturer for evaluation on the implementation circuit Note that the oscillation voltage and oscillation frequency merely indicate the characteristics of the oscillator Use the internal operation conditions of the uPD78F9076 within the specifications of the DC and AC characteristics User s Manual U14801EJ3V1UD 199 CHAPTER 15 ELECTRICAL SPECIFICATIONS EXPANDED SPECIFICATION PRODUCTS DC Characteristics Ta 40 to 85 C Vpp 1 8 to 5 5 V Oe oe e 020 2 AT Output current Per Perpin uPD78907x 78F9076 high Total for all pins Per TOA uPD78907x A Total for all Total for all pins Output current low uPD78907x 78F9076 Total for all Total for all pins uPD78907x A Total for all Total for all pins ES Input voltage high m P00 to P07 P10 to P15 E ee ET Se
45. manipulated with a 16 bit memory manipulation instruction It can also be manipulated with 8 bit memory manipulation instructions however When an 8 bit memory manipulation instruction is used to manipulate TCP90 it must be accessed by direct addressing 16 bit counter read buffer 90 This buffer is used to latch and hold the count for 16 bit timer counter 90 TM90 Users Manual U14801EJ3V1UD CHAPTER 6 16 BIT TIMER 90 6 3 Control Registers of 16 Bit Timer 90 The following four registers are used to control 16 bit timer 90 e 16 bit timer mode control register 90 TMC90 e Buzzer output control register 90 BZC90 e Port mode register 3 PM3 e Port 3 P3 1 16 bit timer mode control register 90 TMC90 16 bit timer mode control register 90 TMC90 controls the setting of the count clock capture edge etc TMC90 is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears TMC90 to 00H User s Manual U14801EJ3V1UD CHAPTER 6 16 BIT TIMER 90 Figure 6 2 Format of 16 Bit Timer Mode Control Register 90 Symbol 7 Address After reset R W vue DD EE FEABH o Re o Timer output of O Timer output of 1 TOF90 Overflow flag setting EN Reset or cleared by software ha Set when the 16 bit timer overflows o o n To 1 cared ste engage i S o EE ER Timer output data inversion control Inversion disabled Inversion enabled TCL901 TCL900 16 bit timer counter 90 count clock fcl selec
46. of Serial Interface 20 Serial interface 20 has the following three modes e Operation stop mode e Asynchronous serial interface UART mode e 3 wire serial WO mode 1 2 3 Operation stop mode This mode is used when serial transfer is not performed Power consumption is minimized in this mode Asynchronous serial interface UART mode This mode is used to send and receive the one byte of data that follows a start bit It supports full duplex communication Serial interface 20 contains a UART dedicated baud rate generator enabling communication over a wide range of baud rates It is also possible to define baud rates by dividing the frequency of the clock input to the ASCK20 pin 3 wire serial UO mode switchable between MSB first and LSB first transmission This mode is used to transmit 8 bit data using three lines a serial clock SCK20 line and two serial data lines SI20 and SO20 As it supports simultaneous transmission and reception 3 wire serial l O mode requires less processing time for data transmission than asynchronous serial interface mode Because in 3 wire serial l O mode it is possible to select whether 8 bit data transmission begins with the MSB or LSB serial interface 20 can be connected to any device regardless of whether that device is designed for MSB first or LSB first transmission 3 wire serial UO mode is useful for connecting peripheral l O circuits and display controllers having conventional
47. or WDTM3 AS timer clock selection Watchdog timer mode register WDTM register 2 WDCS fx 24 Prescaler INTWDT Maskable interrupt request gt RESET INTWDT Non maskable interrupt request Selector 110 User s Manual U14801EJ3V1UD CHAPTER 8 WATCHDOG TIMER 8 3 Watchdog Timer Control Registers The following two registers are used to control the watchdog timer Watchdog timer clock selection register WDCS Watchdog timer mode register WDTM 1 Watchdog timer clock selection register WDCS This register sets the watchdog timer count clock WDCS is set with an 8 bit memory manipulation instruction RESET input clears WDCS to 00H Figure 8 2 Format of Watchdog Timer Clock Selection Register Symbol 7 6 5 4 3 2 1 0 WDCS2 WDCS1 WDCSO Count clock selection At fx 10 0 MHz At fx 5 0 MHz At fx 2 10 0 MHz At fx 2 5 0 MHz operationNete operation operationNete operation 28 1 156 kHz 78 1 kHz 819 us 1 64 ms Address After reset R W FF42H 00H R W Other than above Setting prohibited Note Expanded specification products only Remark fx System clock oscillation frequency User s Manual U14801EJ3V1UD 111 CHAPTER 8 WATCHDOG TIMER 2 Watchdog timer mode register WDTM This register sets the operation mode of the watchdog timer and enables disables counting of the watchdog timer WDTM is set with a 1 bit or 8 bit memory manipulat
48. program may not run correctly 2 2 10 IC mask ROM version only The IC Internally Connected pin is used to set the uPD789071 789072 and 789074 to test mode before shipment In normal operation mode directly connect this pin to the Vss pin with as short a wiring length as possible If a potential difference is generated between the IC pin and the Vss pin due to a long wiring length between these pins or external noise superimposed on the IC pin the user program may not run correctly e Directly connect the IC pin to the Vss pin Vss IC Keep short 34 Users Manual U14801EJ3V1UD CHAPTER 2 PIN FUNCTIONS 2 3 Pin I O Circuits and Recommended Connection of Unused Pins The I O circuit type of each pin and recommended connection of unused pins are shown in Table 2 1 For the I O circuit configuration of each type refer to Figure 3 1 Table 2 1 Types of Pin UO Circuits and Recommended Connection of Unused Pins I O Circuit Type Recommended Connection of Unused Pins POO to PO7 Input Connect to Von or Vss via a resistor P10 to P15 Output Leave open P20 SCK20 ASCK20 P21 SO20 TxD20 P22 SI20 RxD20 P23 SS20 P24 INTPO Connect to Vss via a resistor P25 INTP1 Leave open P26 INTP2 CPT90 P27 T180 TO80 Connect to Voo or Vss via a resistor P30 TO90 Leave open P31 BZO90 RESET C Ver User s Manual U14801EJ3V1UD 35 36 Schmitt triggered input with hysteresis characteristics CHAPT
49. set to 0 Remark fx System clock oscillation frequency 76 Users Manual U14801EJ3V1UD CHAPTER 5 CLOCK GENERATOR 5 4 System Clock Oscillators 5 4 1 System clock oscillator The system clock oscillator is oscillated by the crystal or ceramic resonator 5 0 MHz TYP connected across the X1 and X2 pins An external clock can also be input to the circuit In this case input the clock signal to the X1 pin and input the inverted signal to the X2 pin Figure 5 3 shows the external circuit of the system clock oscillator Figure 5 3 External Circuit of System Clock Oscillator a Crystal or ceramic oscillation b External clock External X1 clock x2 Crystal or ceramic resonator Caution When using the system clock oscillator wire as follows in the area enclosed by the broken lines in Figure 5 3 to avoid an adverse effect from wiring capacitance e Keep the wiring length as short as possible e Do not cross the wiring with the other signal lines Do not route the wiring near a signal line through which a high fluctuating current flows e Always make the ground point of the oscillator capacitor the same potential as Vss Do not ground the capacitor to a ground pattern through which a high current flows e Do not fetch signals from the oscillator Users Manual U14801EJ3V1UD 77 CHAPTER 5 CLOCK GENERATOR 5 4 2 Examples of incorrect resonator connection Figure 5 4 shows an example of incorrect resonator connections
50. synchronous serial interfaces such as those of the 75X XL 78K and 17K Series devices 9 2 Configuration of Serial Interface 20 Serial interface 20 includes the following hardware Table 9 1 Configuration of Serial Interface 20 Registers Transmission shift register 20 TXS20 Reception shift register 20 RXS20 Receive buffer register 20 RXB20 Control registers Serial operation mode register 20 CSIM20 Asynchronous serial interface mode register 20 ASIM20 Asynchronous serial interface status register 20 ASIS20 Baud rate generator control register 20 BRGC20 Port mode register 2 PM2 Port 2 P2 User s Manual U14801EJ3V1UD 115 oLt ankAerakLo8v LIT ENUEN Soen Figure 9 1 Block Diagram of Serial Interface 20 Serial operation mode Asynchronous serial interface Asynchronous serial interface register 20 CSIM20 status register 20 ASIS20 mode register 20 ASIM20 CSIE20 SSE20 DAP20 DIR20 CSCK20 CkP20 Receive buffer PE20 FE20 OVE20 TXE20 RXE20 PS201 P5200 cL2olsL20 i i register 20 RXB20 7 Y Switching of the first bit Transmit shift register 20 FE Transmit SI20 P22 O Receive shift I I shift clock RxD20 register 20 RXS20 C341 Selector t Port mode Receive CSIE20 register PM21 shift clock Data phase g control DE SO20 P21 O TxD20 i Stop bit addition Transmit data counter gt INTST20 Par
51. therefore the interrupt mask flag must be preset to 1 154 User s Manual U14801EJ3V1UD CHAPTER 10 INTERRUPT FUNCTIONS 2 Interrupt mask flag registers 0 and 1 MKO and MK1 The interrupt mask flags are used to enable and disable the corresponding maskable interrupts MKO and MK1 are set with a 1 bit or 8 bit memory manipulation instruction RESET input sets MKO and MK1 to FFH Symbol 7 6 4 Figure 10 3 Format of Interrupt Mask Flag Register lt 2 gt 1 0 Address After reset R W MKO 7 6 5b 4 3 5 4 3 2 1 0 gt g FFESH mm RW Interrupt servicing control o Enable interrupt servicing Disable interrupt servicing Cautions 1 2 Bits 6 and 7 of MKO and bits 2 to 7 of MK1 must all be set to 1 When the watchdog timer is being used in watchdog timer mode 1 or 2 any attempt to read the WDTMK flag results in an undefined value being detected When port 2 is being used as an output port and its output level is changed an interrupt request flag is set because this port is also used as an external interrupt input To use port 2 in output mode therefore the interrupt mask flag must be preset to 1 User s Manual U14801EJ3V1UD 155 CHAPTER 10 INTERRUPT FUNCTIONS 3 External interrupt mode register 0 INTMO INTMO is used to specify a valid edge for INTPO to INTP2 INTMO is set with an 8 bit memory manipulation instruction RESET input clears INTMO to 00H Figure 10
52. transmit data 1 The number of bits with a value of 1 is an even number in transmit data 0 e At reception The number of bits with a value of 1 in the receive data including the parity bit is counted and if the number is odd a parity error occurs ii Odd parity e At transmission Conversely to even parity the parity bit is determined so that the number of bits with a value of 1 in the transmit data including the parity bit is odd The parity bit value should be as follows The number of bits with a value of 1 is an odd number in transmit data 0 The number of bits with a value of 1 is an even number in transmit data 1 e At reception The number of bits with a value of 1 in the receive data including the parity bit is counted and if the number is even a parity error occurs iii O parity When transmitting the parity bit is set to 0 irrespective of the transmit data At reception a parity bit check is not performed Therefore a parity error does not occur irrespective of whether the parity bit is set to 0 or 1 iv No parity A parity bit is not added to the transmit data At reception data is received assuming that there is no parity bit Since there is no parity bit a parity error does not occur 134 User s Manual U14801EJ3V1UD CHAPTER 9 SERIAL INTERFACE 20 c Transmission A transmit operation is started by writing transmit data to transmit shift register 20 TXS20 The start bit parity bit and
53. used User s Manual U14801EJ3V1UD 7 Conversions Data significance Higher digits on the left and lower digits on the right Active low representation xxx Overscore over pin or signal name Note Footnote for item marked Note in the text Caution Information requiring particular attention Remark Supplementary information Numerical representation Binary xxxx or xxxxB Decimal xxxx Hexadecimal xxxxH x Related Documents The related documents indicated in this publication may include preliminary versions However preliminary versions are not marked as such Documents Related to Devices uPD789074 Subseries User s Manual 78K 0S Series Instructions User s Manual U11047E Documents Related to Development Tools Software User s Manuals RA78KOS Assembler Package SM78K Series System Simulator Ver 2 30 or Later Operation Windows Based U15373E External Parts User Open U15802E Interface Specifications ID78K Series Integrated Debugger Ver 2 30 or Later Operation Windows Based U15185E Project Manager Ver 3 12 or Later Windows Based U14610E Documents Related to Development Tools Hardware User s Manuals IE 78KOS NS In Circuit Emulator U13549E IE 78KOS NS A In Circuit Emulator U15207E IE 789046 NS EM1 Emulation Board U14433E Caution The related documents listed above are subject to change without notice Be sure to use the latest version of each document for designing 8 Users Manual U14801EJ
54. 0 Interrupt acknowledgment Interrupt acknowledgment TO80Nete l O e RN Note The initial value of TO80 is low when output is enabled TOE80 1 TCE80 User s Manual U14801EJ3V1UD 105 CHAPTER 7 8 BIT TIMER EVENT COUNTER 80 7 4 4 Operation as PWM output PWM output enables an interrupt to be generated repeatedly at an interval specified by the count value preset in 8 bit co mpare register 80 CR80 To use 8 bit timer event counter 80 for PWM output the following settings are required lt 1 gt lt 2 gt lt 3 gt lt 4 gt lt 5 gt Set P27 to output mode PM27 0 Set the output latch of P27 to 0 Disable the operation of 8 bit timer counter 80 TM80 TCE80 0 Set a count clock for 8 bit timer event counter see Table 7 4 and enable output of TO80 TOE80 1 and PWM output PWME80 1 Set a count value in CR80 Enable the operation of TM80 TCE80 1 When the count value of 8 bit timer counter 80 TM80 matches the value set in CR80 TM80 continues counting and an interrupt request signal INTTM80 is generated Cautions 1 If CR80 is rewritten during timer operation a high level may be output during the next cycle see 7 5 2 Setting of 8 bit compare register 80 2 If setting the count clock to TMC80 and enabling the operation of TM80 are performed at the same time with an 8 bit memory manipulation instruction the error one cycle after the timer has been started may e
55. 0 uPD78F9076MC 5A4 A 30 pin plastic SSOP 7 62 mm 300 Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature 260 C Time 60 seconds max at 220 C or IR60 207 3 higher Count Three times or less Exposure limit 7 days OG after that prebake at 125 C for 20 to 72 hours Wave soldering For details contact an NEC Electronics sales representative e Partial heating Pin temperature 350 C max Time 3 seconds max per pin row e Note After opening the dry pack store it at 25 C or less and 65 RH or less for the allowable storage period Caution Do not use different soldering methods together except for partial heating Remark Products that have the part numbers suffixed by A are lead free products 224 User s Manual U14801EJ3V1UD APPENDIX A DEVELOPMENT TOOLS The following development tools are available for development of systems using the uPD789074 Subseries Figure A 1 shows the development tools e Compatibility with PC98 NX Series Unless stated otherwise products which are supported by IBM PC AT and compatibles can also be used with the PC98 NX Series When using the PC98 NX Series therefore refer to the explanations for IBM PC AT and compatibles e Windows Unless stated otherwise Windows refers to the following operating systems e Windows 3 1 e Windows 95 98 2000 e Windows NT Ver 4 0 User s Manual U14801EJ3V1UD 225 I
56. 0 V User s Manual U14801EJ3V1UD RC oscillation version 25 CHAPTER 1 GENERAL Series for ASSP ROM i Bit 10 Bit Serial Interface Von Remarks Capacity a p 16 Bi A D MIN Value Bytes USB 4uPD789800 8K 2 ch USB 1 ch Inverter PD789842 8Kto 16K 1 ch UART 1 ch control On chip uPD789850 2 ch UART 1 ch bus controller Keyless uPD789861 RC oscillation entry version on chip EEPROM uPD789860 On chip EEPROM 4PD789862 1 ch UART 1 ch VFD uPD789871 4Kto8K drive Meter uPD789881 1 ch UART 1 ch control Notes 1 10 bit timer 1 channel 2 Flash memory version 3 0 V 26 User s Manual U14801EJ3V1UD 1 8 Block Diagram 8 bit timer event TO90 P30 BZO90 P31 16 bit timer 90 CPT90 P26 Watchdog timer KI SCK20 ASCK20 P20 SO20 TxD20 P21 Serial SI20 RxD20 P22 interface 20 5520 P23 Remarks 1 The internal ROM capacity varies depending on the product CHAPTER 1 GENERAL ROM 78K 0S flash CPU core memory Voo Vss IC VPP Port 0 K PO00 to P07 Port 1 gt P10 to P15 Port 2 K gt P20 to P27 Port 3 P30 P31 RESET System control X1 X2 INTPO P24 Interrupt control lt INTP1 P25 INTP2 P26 2 Pin connections in parentheses are intended for the uPD78F9076 User s Manual U14801EJ3V1UD 27 CHAPTER 1 GENERAL
57. 000 5020 output Note R and C are the load resistance and load capacitance of the SO20 output line b 3 wire serial UO mode SCK20 External clock SCK20 cycle time tkcv2 Voo 2 7 to 5 5 V Voo 1 8 to 5 5 V SCK20 high low tkH2 tk2 Voo 2 7 to 5 5 V level width Voo 1 8 to 5 5 V es Note sen SSES pF Voo 1 8 to 5 5 V 1000 5020 output when using SS20 Voo 1 8 to 5 5 V 400 ns to SS20 J when using SS20 from SS207 Note R and C are the load resistance and load capacitance of the SO20 output line 216 User s Manual U14801EJ3V1UD CHAPTER 16 ELECTRICAL SPECIFICATIONS CONVENTIONAL PRODUCTS c UART mode Dedicated baud rate generator output Transfer rate Voo 2 7 to 5 5 V EE EE 78 125 bps Voo 1 8 to 5 5 V d UART mode External clock input ASCK20 cycle time tkcva Voo 2 7 to 5 5 V Von 1 8 to 5 5 V ASCK20 high low tkxs Iva Voo 2 7 to 5 5 V level width Voo 1 8 to 5 5 V Transfer rate Voo 2 7 to 5 5 V C PAS er 39 063 Ea ASCK20 rise fall tR tF time User s Manual U14801EJ3V1UD 217 CHAPTER 16 ELECTRICAL SPECIFICATIONS CONVENTIONAL PRODUCTS AC Timing Test Points Excluding X1 Input 0 8Voo 0 8Voo Ne Test points et 0 2Vop 0 2Voo Clock Timing Vitts MIN X1 input Vins MAX TI Timing TI80 Interrupt Input Timing Ix um mi tINTH INTPO to INTP2 RESET Input Timing RS RESET
58. 00H 0000H 38 User s Manual U14801EJ3V1UD Data memory space FFFFH FFOOH FEFFH FEOOH FDFFH 2000H CHAPTER 3 CPU ARCHITECTURE Figure 3 3 Memory Map uPD789074 Special function registers 256 x 8 bits Internal high speed RAM 256 x 8 bits Reserved space Y 1FFFH Program memory 0000H Internal ROM 8 192 x 8 bits 1FFFH Program area 0080H 007FH CALLT table area 0040H 003FH Program area 0018H 0017H Vector table area 0000H User s Manual U14801EJ3V1UD 39 CHAPTER 3 CPU ARCHITECTURE Figure 3 4 Memory Map uPD78F9076 Data memory space FFFFH Special function registers 256 x 8 bits FFOOH FEFFH Internal high speed RAM 256 x 8 bits FEOOH FDFFH Reserved 3FFFH 4000H space Program memory 3FFFH Program area 0080H 007FH Internal flash memory 16 384 x 8 bits CALLT table area 0040H 003FH Program area 0018H 0017H Vector table area 0000H 0000H 40 User s Manual U14801EJ3V1UD CHAPTER 3 CPU ARCHITECTURE 3 1 1 Internal program memory space The internal program memory space stores programs and table data This space is usually addressed by the program counter PC Products in the uPD789074 Subseries provide the following internal ROM or flash memory containing the following capacities Table 3 1 Internal ROM Capacity Part Number
59. 01 and TCL900 Set BZC90 as shown in Figure 6 12 Figure 6 12 Settings of Buzzer Output Control Register 90 for Buzzer Output Operation BCS902 BCS901 BCS900 BZOE90 eco o 0 Jo fo Jon forfon v Enables buzzer output Setting of buzzer frequency see Table 6 4 Table 6 4 Buzzer Frequency of 16 Bit Timer 90 BCS902 BCS901 BCS900 Buzzer Frequency o fe wem amem omr ren aeewu Teen o o wm mem am user serm mane 9770 Lo o per omme eom name Tase Teen 1200 Lo 1 er amz sens ie mense Tun enne o o ue masse Tun Teen 120m Tene mens Note Expanded specification products only Remark fx System clock oscillation frequency 94 Users Manual U14801EJ3V1UD CHAPTER 6 16 BIT TIMER 90 6 5 Notes on Using 16 Bit Timer 90 6 5 1 Restrictions on rewriting 16 bit compare register 90 1 When rewriting the compare register CR90 be sure to disable interrupts TMMK90 1 and disable inversion control of timer output TOC90 0 first If CR90 is rewritten with interrupts enabled an interrupt request may be generated at the point of rewrite 2 The interval time may be double the intended time depending on the timing at which the compare register CR90 is rewritten Likewise the timer output waveform may be shorter or double the intended output To avoid this rewrite using one of the following procedures lt Prevention method A gt Rewriting by 8 bit access
60. 076 replaces the internal ROM of the uPD789071 789072 789074 789071 A 789072 A and 789074 A with flash memory The differences between the flash memory and the mask ROM versions are shown in Table 13 1 Table 13 1 Differences Between Flash Memory and Mask ROM Versions Flash Memory Mask ROM Version Version uPD78F9076 uPD789071 uPD789072 uPD789074 uPD789071 A uPD789072 A 4PD789074 A Internal memory Flash memory Mask ROM High speed RAM 256 bytes Electrical characteristics Refer to CHAPTER 15 ELECTRICAL SPECIFICATIONS EXPANDED SPECIFICATION PRODUCTS and CHAPTER 16 ELECTRICAL SPECIFICATIONS CONVENTIONAL PRODUCTS Caution There are differences in the noise immunity and noise radiation between flash memory and mask ROM versions When pre producing an application set with the flash memory version and the mass producing it with the mask ROM version be sure to conduct sufficient evaluations on the commercial sample CS not engineering sample ES of the mask ROM version 174 User s Manual U14801EJ3V1UD CHAPTER 13 PD78F9076 13 1 Flash Memory Characteristics Flash memory programming is performed by connecting a dedicated flash programmer Flashpro III part no FL PR3 PG FP3 Flashpro IV part no FL PR4 PG FP4 to the target system with the uPD78F9076 mounted on the target system on board A flash memory program adapter FA adapter which is a target board used exclusively for programming is also provided
61. 20 of asynchronous serial interface mode register 20 ASIM20 the stop bit detection at reception is performed with 1 bit 2 Be sure to read receive buffer register 20 RXB20 when an overrun error occurs If not every time the data is received an overrun error is generated 122 User s Manual U14801EJ3V1UD CHAPTER 9 SERIAL INTERFACE 20 4 Baud rate generator control register 20 BRGC20 BRGC20 is used to specify the serial clock for serial interface 20 BRGC20 is set with an 8 bit memory manipulation instruction RESET input clears BRGC20 to 00H Figure 9 6 Format of Baud Rate Generator Control Register 20 Symbol 7 6 5 4 Address After reset R W 3 2 1 0 BRGC20 TPS202 o o o FF73H 00H R W TPS203 TPS202 TPS201 TPS200 Selection of source clock for baud rate generator ENERENKE EREREREN ESESESES CARNES EN Je Lee EST e v r JL sse o Extemalciockinputio the asero nee Notes 1 Expanded specification products only 2 An external clock can be used only in UART mode Cautions 1 When writing to BRGC20 is performed during a communication operation the output of the baud rate generator is disrupted and communication cannot be performed normally Be sure not to write to BRGC20 during a communication operation 2 Be sure not to select n 1 during operation at fx gt 2 5 MHz in UART mode because the resulting baud rate exceeds the rated range 3 Be sure not to select n 2 during operation at fx gt 5 0
62. 3 Wire Serial WO 182 13 9 Wiring Example for Flash Writing Adapter Using UART AA 183 13 10 Wiring Example for Flash Writing Adapter Using Pseudo 2 MWire AA 184 Ac DevelopmentTools uuaagdu goe eO Het e o aids ie had 226 B 1 Distance Between In Circuit Emulator and Conversion Adapter arnrrnrnnnnvnnnvrnnnnvnnnnrennvnnrnvrnnnvnnenrrerrrnnenrenenn 231 B 2 Connection Condition of Target System sssssssssssssseseeee eene nennen nere nnren nnne nennen nennen 232 Users Manual U14801EJ3V1UD 17 LIST OF TABLES 1 2 Table No Title Page 1 1 Differences Between Expanded Specification Products and Conventional Products AA 20 1 2 Differences Between Standard Quality Grade Products and A Products AA 29 2 1 Types of Pin I O Circuits and Recommended Connection of Unused Pins 35 3 1 Internal ROM Capacity ici a des 41 3 2 Vector Table xiii A A FT ud 41 e ERR tele ue EE EN 4 1 Port EUnDctlons imet nhe cte ttd ette e o tee ivit ater gd ia ds lets 63 4 2 Qonfiguration of Ports aei Het RR a 64 4 3 Port Mode Register and Output Latch Settings for Using Alternate Functions 72 5 1 Configuration of Clock Generator 75 5 2 Maximum Time Required for Switching CPU Clock A 81 6 1 Configuration of 16 Bit Timer 90 2s inei ee lb ie ove 82 6 2 Interval Time of 16 Bit Timer 90 rrrnrnrnnnvnnnvnrnnnnnnnvnrnvnnnnvnvnnvnnnnnnvneenvnnnnenvnnennnnnnnenrnnnnenennrnnnnvnnnenrnnnennvnnenenennn 89 6 3 Settings of Capture Edge iom teo ne
63. 3V1UD Documents for Flash Memory Writing PG FP3 Flash Memory Programmer User s Manual U13502E PG FP4 Flash Memory Programmer User s Manual U15260E Other Related Documents SEMICONDUCTOR SELECTION GUIDE Products and Packages X13769X Semiconductor Device Mount Manual Noe o e Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge ESD C11892E Note See the Semiconductor Device Mount Manual website http www necel com pkg en mount index html Caution The related documents listed above are subject to change without notice Be sure to use the latest version of each document for designing User s Manual U14801EJ3V1UD 9 CONTENTS CHAPTER dac iz nim 20 1 4 Expanded Specification Products and Conventional Products sssss 20 WD A A o 21 1 3 ele Le datan ista 21 1 4 gt Ordering Informatica indian 21 1 5 e a e ML 22 1 6 Pin Configuration Top VieWw rrnssvrnnnvnnnnnvnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnr 23 1 7 78K 0S Series Lineup msme EES 24 1 8 Block SUELE 27 1 9 Overview of Functions 2 Lea Ee EES iii 28 1 10 Differences Between Standard Quality Grade Products and A Products 29 CHAPTER 2 PIN FUNCTIONS iecit desee i
64. 4 Format of External Interrupt Mode Register 0 Symbol 7 6 Address After reset R W 5 4 3 2 1 0 Dees Fopr mmem 9 NENE ES11 ES10 INTP1 valid edge selection EJEA Falling edge EE Setting prohibited Both rising and falling edges o o m o pme O o femma o Cautions 1 Bits 0 and 1 must both be set to 0 2 Before setting INTMO set the corresponding interrupt mask flag to 1 to disable interrupts To enable interrupts clear to 0 the corresponding interrupt request flag then the corresponding interrupt mask flag 156 User s Manual U14801EJ3V1UD CHAPTER 10 INTERRUPT FUNCTIONS 4 Program status word PSW The program status word is used to hold the instruction execution result and the current status of the interrupt requests The IE flag used to enable and disable maskable interrupts is mapped to the PSW The PSW can be read and write accessed in 8 bit units as well as using bit manipulation instructions and dedicated instructions El and DI When a vector interrupt is acknowledged the PSW is automatically saved to a stack and the IE flag is reset to 0 RESET input sets PSW to 02H Figure 10 5 Program Status Word Configuration Symbol 7 6 5 4 3 2 1 0 After reset 02H Used in the execution of ordinary instructions Whether to enable disable interrupt acknowledgment 0 Disabled 1 Enabled Users Manual U14801EJ3V1UD 157 CHAPTER 10 INTERRUPT FUNCTIONS 10 4 Interrupt Processing Operation
65. 6 Bit Timer Mode Control Register 90 for Timer Interrupt Operation TOD90 TOF90 CPT901 CPT900 TOC90 TCL901 TCL900 TOE90 TMC90 0 1 0 1 0 1 0 1 0 1 0 1 0 1 pA Caution If both the CPT901 and CPT900 flags are set to 0 the capture operation is disabled Setting of count clock see Table 6 2 When the count value of 16 bit timer counter 90 TM90 matches the value set in CR90 counting of TM90 continues and an interrupt request signal INTTM90 is generated Table 6 2 shows the interval time and Figure 6 6 shows the timing of the timer interrupt operation Caution Perform the following processing when rewriting CR90 during a count operation lt 1 gt Disable interrupts TMMK90 bit 1 of interrupt mask flag register 1 MK1 1 lt 2 gt Disable inversion control of timer output data TOC90 0 If CR90 is rewritten with interrupts enabled an interrupt request may be issued immediately at the point of rewrite Table 6 2 Interval Time of 16 Bit Timer 90 TCL901 TCL900 Interval Time At fx 2 10 0 MHz At fx 2 5 0 MHz At fx 2 10 0 MHz At fx 2 5 0 MHz Operation Operation Operation Operation s os me emm oe em mam seams 1 sms 7000 Setting prohibited Note Expanded specification products only Remark fx System clock oscillation frequency User s Manual U14801EJ3V1UD 89 90 Count clock TM90 count value CR90 INTTM90 TO90 TOF90 CHAPTER 6 16 BIT TIMER 90 Figure 6 6 Timing of Timer In
66. 6 bit timer counter 90 readout Cautions 1 The count value after releasing the stop mode becomes undefined because the count operation is executed during the oscillation stabilization time 2 Though TM90 is designed for a 16 bit transfer instruction an 8 bit transfer instruction can also be used When using an 8 bit transfer instruction execute it by direct addressing 3 When using an 8 bit transfer instruction execute in the order from the lower byte to the higher byte in pairs If only the lower byte is read the pending state of the counter read buffer is not canceled and if only the higher byte is read an undefined count value is read Figure 6 11 16 Bit Timer Counter 90 Readout Timing CPU clock A ar rd Count clock i d mo Seet 8 XX Count read buffer 0000H X 0001H CT i TM90 read signal i i l A SE Read signal latch prohibited period Remark N 0000H to FFFFH User s Manual U14801EJ3V1UD 93 CHAPTER 6 16 BIT TIMER 90 6 4 5 Buzzer output operation The buzzer frequency is set using buzzer output control register 90 BZC90 based on the count clock selected with TCL901 and TCL900 of TMC90 source clock A square wave of the set buzzer frequency is output Table 6 4 shows the buzzer frequency To operate 16 bit timer 90 as a buzzer output the following settings are required Set P31 to output mode PM31 0 Reset output latch of P31 to 0 Set a count clock by using TCL9
67. 8 bit memory manipulation instruction is used to set CR90 it must be accessed by direct addressing To re set CR90 during a count operation it is necessary to disable interrupts in advance using interrupt mask flag register 1 MK1 It is also necessary to disable inversion of the timer output data using 16 bit timer mode control register 90 TMC90 If CR90 is rewritten with interrupts enabled an interrupt request may be issued immediately at the point of rewrite 16 bit timer counter 90 TM90 TM90 is used to count the number of pulses The contents of TM90 are read with an 8 bit or 16 bit memory manipulation instruction RESET input clears TM90 to 0000H Cautions 1 The count becomes undefined when STOP mode is released because the count operation is performed before oscillation stabilizes TM90 is designed to be manipulated with a 16 bit memory manipulation instruction It can also be manipulated with 8 bit memory manipulation instructions however When an 8 bit memory instruction is used to manipulate TM90 it must be accessed by direct addressing When an 8 bit memory manipulation instruction is used to manipulate TM90 the lower and higher bytes must be read as a pair in that order 16 bit capture register 90 TCP90 TCP90 captures the contents of 16 bit timer counter 90 TM90 This register is set with an 8 bit or 16 bit memory manipulation instruction RESET input makes TCP90 undefined Caution TCP90 is designed to be
68. 90 BZC90 Port mode register 3 PM3 Port 3 P3 82 User s Manual U14801EJ3V1UD ankAerakosv in ENUEN SJESN 8 Figure 6 1 Block Diagram of 16 Bit Timer 90 S Internal bus 16 bit timer mode control register 90 TMC90 TOF90 CPT901 CPT900 TOC90 TCL900 TOE90 fx 2 fx 24 1x 28 Selector CTP90 INTP2 P26 Edge detector 16 bit compare register 90 CR90 Match P30 Output latch O TO90 P30 16 bit timer counter 16 bit capture register 90 TCP90 fx 2 90 TM90 Selector 16 bit counter read buffer Write controller CPU clock BCS902 BCS901 BCS900 BZOE90 Buzzer output control register 90 BZC90 INTTM90 BZO90 P31 P31 Output latch Internal bus 06 YANIL LIG 91 9 YILAVHO 84 1 2 3 4 CHAPTER 6 16 BIT TIMER 90 16 bit compare register 90 CR90 The value specified in CR90 is compared with the count in 16 bit timer counter 90 TM90 If they match an interrupt request INTTM90 is issued by CR90 CR90 is set with an 8 bit or 16 bit memory manipulation instruction Any value from 0000H to FFFFH can be set RESET input sets CR90 to FFFFH Cautions 1 CR90 is designed to be manipulated with a 16 bit memory manipulation instruction It can also be manipulated with 8 bit memory manipulation instructions however When an
69. CSCK20 External TxD20 ASCK20 clock CMOS output input Internal clock External ASCK20 clock input Internal clock External TxD20 ASCK20 clock CMOS output input Internal clock Other than above Setting prohibited Notes 1 These pins can be used for port functions 2 When only transmission is used this pin can be used as P22 CMOS 1 0 Remark x Don t care User s Manual U14801EJ3V1UD 121 CHAPTER 9 SERIAL INTERFACE 20 3 Asynchronous serial interface status register 20 ASIS20 ASIS20 indicates the type of a reception error if it occurs while asynchronous serial interface mode is set ASIS20 is read with a 1 bit or 8 bit memory manipulation instruction The contents of ASIS20 are undefined in 3 wire serial I O mode RESET input clears ASIS20 to 00H Figure 9 5 Format of Asynchronous Serial Interface Status Register 20 Symbol 7 6 5 4 3 2 1 0 Address After reset R W ASIS20 o o o o o Pezo Feo OVE20 FF71H 00H R Parity error flag No parity error occurred A parity error occurred when the transmit parity and receive parity did not match Overrun error flag No overrun error occurred An overrun error occurred 2 The subsequent receive operation was completed before data was read from the receive buffer register Notes 1 Even when the stop bit length is set to 2 bits by setting bit 2 SL
70. ER 2 PIN FUNCTIONS Figure 2 1 Pin I O Circuits Pull up enable pe gt Output H disable gt F Von e P ch N ch Pull up enable DoE Von Output disable Input enable IN OUT Users Manual U14801EJ3V1UD P ch IN OUT 3 1 Memory Space CHAPTER 3 CPU ARCHITECTURE Products in the uPD789074 Subseries can each access up to 64 KB of memory space Figures 3 1 through 3 4 show the memory maps Data memory space FFFFH FFOOH FEFFH FEOOH FDFFH 0800H Figure 3 1 Memory Map uPD789071 Special function registers 256 x 8 bits Internal high speed RAM 256 x 8 bits Reserved space Y O7FFH Program memory 0000H Internal ROM 2 048 x 8 bits User s Manual U14801EJ3V1UD 07FFH Program area 0080H 007FH CALLT table area 0040H 003FH Program area 0018H 0017H Vector table area 0000H 37 CHAPTER 3 CPU ARCHITECTURE Figure 3 2 Memory Map 1PD789072 Data memory space FFFFH Special function registers 256 x 8 bits FFOOH FEFFH Internal high speed RAM 256 x 8 bits FEOOH FDFFH Reserved OFFFH 1000H Program memory space Y OFFFH Program area 0080H 007FH Internal ROM 4 096 x 8 bits CALLT table area 0040H 003FH Program area 0018H 0017H Vector table area 00
71. ER 9 SERIAL INTERFACE 20 Transmit shift register 20 TXS20 TXS20 is a register in which transmit data is prepared The transmit data is output from TXS20 bit serially When the data length is seven bits bits O to 6 of the data in TXS20 will be transmit data Writing data to TXS20 triggers transmission TXS20 can be written with an 8 bit memory manipulation instruction but cannot be read RESET input sets TXS20 to FFH Caution Do not write to TXS20 during transmission TXS20 and receive buffer register 20 RXB20 are mapped at the same address so that any attempt to read from TXS20 results in a value being read from RXB20 Receive shift register 20 RXS20 RXS20 is a register in which serial data received at the RxD20 pin is converted to parallel data Once one entire byte has been received RXS20 feeds the receive data to receive buffer register 20 RXB20 RXS20 cannot be manipulated directly by a program Receive buffer register 20 RXB20 RXB20 holds a receive data New receive data is transferred from receive shift register 20 RXS20 at every 1 byte data reception When the data length is seven bits the receive data is sent to bits O to 6 of RXB20 in which the MSB is always fixed to O RXB20 can be read with an 8 bit memory manipulation instruction but cannot be written RESET input makes RXB20 undefined Caution RXB20 and transmit shift register 20 TXS20 are mapped at the same address so that any attempt to write to R
72. ET input clears ASIS20 to 00H Symbol 7 Address After reset R W PE20 Parity error flag K Parity error did not occur Parity error occurred when the parity of transmit data did not match FE20 Flaming error flag KG Framing error did not occur Framing error occurred when stop bit was not detected ete 1 OVE20 Overrun error GE o Overrun error did not occur error did not occur Overrun error occurred ete 2 when the next receive operation was completed before the data was read from the receive buffer register Notes 1 Even when the stop bit length is set to 2 bits by setting bit 2 SL20 of asynchronous serial interface mode register 20 ASIM20 the stop bit detection at reception is performed with 1 bit 2 Be sure to read receive buffer register 20 RXB20 when an overrun error occurs If not every time the data is received an overrun error is generated 130 User s Manual U14801EJ3V1UD CHAPTER 9 SERIAL INTERFACE 20 d Baud rate generator control register 20 BRGC20 BRGC20 is set with an 8 bit memory manipulation instruction RESET input clears BRGC20 to 00H Symbol Address After reset R W TPS203 TPS202 TPS201 TPS200 Selection of source clock for baud rate generator Po oe e e we some fem OC o pepe pame 2 o fe o pepene ee fo o feo o CO peje oe f EE Ter e ESE A MA ME Other than above Setting prohibited Note Expanded specification products only Cautions 1 When writing to B
73. Figure 10 7 Timing of Non Maskable Interrupt Request Acknowledgment Saving PSW and PC and Interrupt servicing CPU processing Instruction Instruction jump to interrupt servicing program Figure 10 8 Acknowledgment of Non Maskable Interrupt Request First interrupt servicing NMI request second Y e NMI request Y first Second interrupt servicing User s Manual U14801EJ3V1UD 159 CHAPTER 10 INTERRUPT FUNCTIONS 10 4 2 Maskable interrupt request acknowledgment operation A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0 A vectored interrupt request is acknowledged in the interrupt enabled status when the IE flag is set to 1 The time required to start the interrupt servicing after a maskable interrupt request has been generated is shown in Table 10 3 See Figures 10 10 and 10 11 for the interrupt request acknowledgment timing Table 10 3 Time from Generation of Maskable Interrupt Request to Servicing Minimum Time Maximum Time Note The wait time is maximum when an interrupt request is generated immediately before BT and BF instruction 1 fcPu Remark 1 clock fcru CPU clock When two or more maskable interrupt requests are generated at the same time they are acknowledged starting from the interrupt request assigned the highest priority A pending interrupt is acknowledged when
74. H R W CSIE20 3 wire serial l O mode operation control o Operation disabled Operation enabled SSE20 SS20 pin selection Function of SS20 P23 pin 1 Used Fo Communication enabled Communication disabled DAP20 3 wire serial I O mode data phase selection E Outputs at the falling edge of SCK20 Outputs at the rising edge of SCK20 DIR20 First bit specification oum E CSCK20 3 wire serial I O mode clock selection o External clock input to the SCK20 pin 1 Output of the dedicated baud rate generator CKP20 3 wire serial I O mode clock phase selection ES Clock is active low and SCK20 is at high level in the idle state Clock is active high and SCK20 is at low level in the idle state Cautions 1 Bits 4 and 5 must both be set to 0 2 CSIM20 must be cleared to 00H if UART mode is selected User s Manual U14801EJ3V1UD 119 2 CHAPTER 9 SERIAL INTERFACE 20 Asynchronous serial interface mode register 20 ASIM20 ASIM20 is set when serial interface 20 is used in asynchronous serial interface mode ASIM20 is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears ASIM20 to 00H Symbol Figure 9 4 Format of Asynchronous Serial Interface Mode Register 20 lt 7 gt lt 6 Address After reset R W ASIM20 ee ee EE FF70H 00H R W 120 TXE20 Transmit operation control ES Transmit operation stop Transmit operation enable RXE20 Receive operation control EN Receive operation stop Rec
75. Hz bps BRGC20 Set Value Error BRGC20 Set Value Error BRGC20 Set Value Error ume 2m 9 m hm x Note Expanded specification products only Cautions 1 Be sure not to select n 1 during operation at fx gt 2 5 MHz because the resulting baud rate exceeds the rated range 2 Be sure not to select n 2 during operation at fx 5 0 MHz because the resulting baud rate exceeds the rated range ii Generation of baud rate transmit receive clock from external clock input from ASCK20 pin The transmit receive clock is generated by dividing the clock input from the ASCK20 pin The baud rate of the clock generated from the clock input from the ASCK20 pin is estimated by using the following expression Baud rate 7 bps 16 fasck Frequency of clock input from the ASCK20 pin Table 9 6 Relationship Between ASCK20 Pin Input Frequency and Baud Rate When BRGC20 Is Set to 80H Baud Rate bps ASCK20 Pin Input Frequency kHz 132 User s Manual U14801EJ3V1UD CHAPTER 9 SERIAL INTERFACE 20 2 Communication operation a Data format The transmit receive data format is as shown in Figure 9 7 One data frame consists of a start bit character bits a parity bit and stop bit s The specification of the character bit length in one data frame parity selection and specification of the stop bit length is carried out with asynchronous serial interface mode register 20 ASIM20 Figure 9 7 F
76. In addition these pins function as the timer output and the buzzer output Port 3 can be set to the following operation modes in 1 bit units 1 Port mode When this port is used as an input port an on chip pull up resistor can be used by setting pull up resistor option register O PUO 2 Control mode In this mode P30 and P31 function as the timer output and the buzzer output a TO90 This is the output pin of the 16 bit timer 90 b BZO90 This is the buzzer output pin of the 16 bit timer 90 2 2 5 RESET An active low system reset signal is input to this pin 2 2 6 X1 X2 These pins are used to connect a crystal resonator for system clock oscillation To supply an external clock input the clock to X1 and input the inverted signal to X2 2 2 7 VoD This pin supplies positive power 2 2 8 Vss This pin is the ground potential pin User s Manual U14801EJ3V1UD 33 CHAPTER 2 PIN FUNCTIONS 2 2 9 Ver uPD78F9076 only A high voltage should be applied to this pin when the flash memory programming mode is set and when the program is written or verified Handle this pin in either of the following ways e Connect a 10 KQ pull down resistor to the pin e Provide a jumper on the board so that the pin is connected to a dedicated flash programmer in programming mode and to Vss during normal operation If there is a long wiring length between the Ver pin and the Vss pin or external noise superimposed on the Ver pin the user
77. Internal ROM 4PD789071 Mask ROM 2 048 x 8 bits uPD789072 4 096 x 8 bits uPD789074 8 192 x 8 bits uPD78F9076 Flash memory 16 384 x 8 bits The following areas are allocated to the internal program memory space 1 Vector table area The 24 byte area of addresses 0000H to 0017H is reserved as a vector table area This area stores program start addresses to be used when branching by RESET input or interrupt request generation Of a 16 bit program address the lower 8 bits are stored in an even address and the higher 8 bits are stored in an odd address Table 3 2 Vector Table 2 CALLT instruction table area The subroutine entry address of a 1 byte call instruction CALLT can be stored in the 64 byte area of addresses 0040H to 007FH 3 1 2 Internal data memory internal high speed RAM space The uPD789074 Subseries provides 256 byte internal high speed RAM The internal high speed RAM can also be used as a stack memory 3 1 3 Special function register SFR area Special function registers SFRs of on chip peripheral hardware are allocated to the area of FFOOH to FFFFH see Table 3 3 User s Manual U14801EJ3V1UD 41 CHAPTER 3 CPU ARCHITECTURE 3 1 4 Data memory addressing Each product of the uPD789074 Subseries is provided with a wide range of addressing modes to make memory manipulation as efficient as possible The data memory area FEOOH to FFFFH can be accessed using a unique addressing mode according t
78. J3V1UD 203 CHAPTER 15 ELECTRICAL SPECIFICATIONS EXPANDED SPECIFICATION PRODUCTS c UART mode Dedicated baud rate generator output Transfer rate Voo 2 7 to 5 5 V Ir o 78 125 Voo 1 8 to 5 5 V bps d UART mode External clock input ASCK20 cycle time tkcy3 Von 2 7 to 5 5 V Voo 1 8 to 5 5 V ASCK20 high low t us Ia Voo 2 7 to 5 5 V level width Voo 1 8 to 5 5 V Transfer rate Voo 2 7 to 5 5 V AA 39 063 ASCK20 rise fall tr tr time 204 User s Manual U14801EJ3V1UD CHAPTER 15 ELECTRICAL SPECIFICATIONS EXPANDED SPECIFICATION PRODUCTS AC Timing Test Points Excluding X1 Input 0 8Vpo 0 8Voo Dee Test points a 0 2Vpo 0 2Voo Clock Timing Vins MIN X1 input Vis MAX TI Timing lt 1 fn m tri tri TI80 Interrupt Input Timing tinTL mi tinTH INTPO to INTP2 RESET Input Timing m tns RESET CPT90 Input Timing CPT90 User s Manual U14801EJ3V1UD 205 CHAPTER 15 ELECTRICAL SPECIFICATIONS EXPANDED SPECIFICATION PRODUCTS Serial Transfer Timing 3 wire serial I O mode SCK20 SI20 5020 Remark m 1 2 3 wire serial UO mode when using SS20 SS20 tkas2 tkos2 SO20 Output data UART mode external clock input Ka tKL3 La tkH3 tF ASCK20 206 User s Manual U14801EJ3V1UD CHAPTER 15 ELECTRICAL SPECIFICATIONS EXPANDED SPECIFICATION PRODUCTS Data Memory STOP Mode Low Supply Vol
79. L Remark One instruction clock cycle is one CPU clock cycle fcru selected by the processor clock control register PCC N EOINIGIJIOI INJ O NI O O 190 User s Manual U14801EJ3V1UD CHAPTER 14 INSTRUCTION SET OVERVIEW adi CALL laddr16 SP 1 PC 3 x SP 2 PC 3 L PC lt addr16 SP SP 2 CALLT addr5 SP 1 PC 1 SP 2 PC 1 L PCu 00000000 addr5 1 PC lt 00000000 addr5 SP SP 2 PCH c SP 1 PC SP SP lt SP 2 aa a SP SP 4 8 NMIS 0 m pipe meme 0 qe we p ps mew LLL mas fee AA ET fe fe roere pe frene E Ce recrea aroo KECE KECA e recer resora Pocpersssrnme eene e i po rocio Ce ece imeto Porere No Operation saddr addr16 saddr saddr 1 then PC amp PC 3 jdisp8 if saddr O AA A B Remark One instruction clock cycle is one CPU clock cycle fcru selected by the processor clock control register PCC User s Manual U14801EJ3V1UD 191 CHAPTER 14 INSTRUCTION SET OVERVIEW 14 3 Instructions Listed by Addressing Type 1 8 bit instructions MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP INC DEC ROR ROL RORC ROLC PUSH POP DBNZ nd Operand byte saddr addri6 PSW DE HL HL byte addr16 1st Operand WE Ee 5 laddr16 PSW Hd O lt DE HL lt O lt HL byte O lt Note Exceptr A 192 User s M
80. LL PD789417A LLPD789407A 11PD789456 USB HPD789800 Inverter control LLPD789842 On chip bus controller uL PD789850 Keyless entry D HLPD789862 uPD789861 11PD789860 VFD drive uPD789871 Meter control uPD789881 14PD789167Y 14 PD789104A with enhanced timer function 1L PD789146 with 10 bit A D 1LPD789104A with EEPROM added 1LPD7891244A with 10 bit A D RC oscillation version of 4PD789104A 1LPD789104A with 10 bit A D 1L PD789026 with 8 bit A D and multiplier added UART 8 bit A D dot LCD total display outputs 96 UART dot LCD 40 x 16 SIO 10 bit A D internal voltage boosting method LCD 28 x 4 SIO 8 bit A D resistance division method LCD 28 x 4 11PD789407A with 10 bit A D SIO 8 bit A D resistance division method LCD 28 x 4 LLPD789446 with 10 bit A D SIO 8 bit A D internal voltage boosting method LCD 15 x 4 1LPD789426 with 10 bit A D SIO 8 bit A D internal voltage boosting method LCD 5 x 4 RC oscillation version of uPD789306 SIO internal voltage boosting method LCD 24 x 4 8 bit A D internal voltage boosting method LCD 23 x 4 SIO resistance division method LCD 24 x 4 For PC keyboard On chip USB function On chip inverter controller and UART On chip CAN controller 11PD789860 with enhanced timer function SIO and expanded ROM and RAM RC oscillation version of LLPD789860 On chip POC and key return circuit On chip VFD c
81. Low addr High adar PC 54 User s Manual U14801EJ3V1UD CHAPTER 3 CPU ARCHITECTURE 3 3 3 Table indirect addressing Function The table contents branch destination address of the particular location to be addressed by the immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter PC and branched Table indirect addressing is carried out when the CALLT addr5 instruction is executed This instruction can be used to branch to all the memory spaces according to the address stored in the memory table 40H to 7FH Illustration 7 6 5 1 0 nen o 3 3 7 6 5 10 15 8 Effective address 7 Memory Table 0 Low addr Effective address 1 High addr 15 8 7 0 PC 3 3 4 Register addressing Function The register pair AX contents to be specified with an instruction word are transferred to the program counter PC and branched This function is carried out when the BR AX instruction is executed Illustration User s Manual U14801EJ3V1UD 55 CHAPTER 3 CPU ARCHITECTURE 3 4 Operand Address Addressing The following methods addressing are available to specify the register and memory to undergo manipulation during instruction execution 3 4 1 Direct addressing Function The memory indicated by immediate data in an instruction word is directly addressed Operand format addr16 Label or 16 bit immediate data Description e
82. MHz operation can be selected by the PCC setting Two standby modes STOP and HALT can be used The clock for the peripheral hardware is generated by dividing the frequency of the system clock Therefore the peripheral hardware stops when the system clock stops except for an external input clock User s Manual U14801EJ3V1UD CHAPTER 5 CLOCK GENERATOR 5 6 Changing Setting of CPU Clock 5 6 1 Time required for switching CPU clock The CPU clock can be switched by using bit 1 PCC1 of the processor clock control register PCC Actually the specified clock is not switched immediately after the setting of PCC has been changed old clock is used for the duration of several instructions after that see Table 5 2 Table 5 2 Maximum Time Required for Switching CPU Clock Set Value Before Switching Set Value After Switching PCC1 PCC1 PCC1 1 3 pee a fe Remark Two clocks is the minimum instruction execution time of the CPU clock before switching 5 6 2 Switching CPU clock The following figure illustrates how the CPU clock is switched Figure 5 5 Switching Between System Clock and CPU Clock Von ec RESET fx fx Slow Fast operation operation Wait 3 28 ms 10 0 MHz operation Internal reset operation CPU Clock lt 1 gt The CPU is reset when the RESET pin is made low on power application The effect of resetting is released when the RESET pin is later made high and the system clock starts osc
83. NEC User s Manual uPD789074 Subseries 8 Bit Single Chip Microcontrollers uPD789071 uPD789071 A uPD789072 uPD789072 A uPD789074 uPD789074 A uPD78F9076 Document No U14801EJ3V1UD00 3rd edition Date Published October 2005 N CP K O NEC Electronics Corporation 2000 2002 Printed in Japan MEMO 2 User s Manual U14801EJ3V1UD NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction If the input of the CMOS device stays in the area between Vi MAX and Vik MIN due to noise etc the device may malfunction Take care to prevent chattering noise from entering the device when the input level is fixed and also in the transition period when the input level passes through the area between ViL MAX and Vu MIN HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction If an input pin is unconnected it is possible that an internal input level may be generated due to noise etc causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using pull up or pull down circuitry Each unused pin should be connected to Voo or GND via a resistor if there is a possibility that it will be an output pin All handling related to unused pins must be judged separately for each device and according to related specifications governing the dev
84. O80 P27 T180 Wd 8 bit timer mode control register 80 TMC80 Internal bus 1 8 bit compare register 80 CR80 The value specified in CR80 is compared with the count in 8 bit timer counter 80 TM80 If they match an interrupt request INTTM80 is issued CR80 is set with an 8 bit memory manipulation instruction Any value from OOH to FFH can be set RESET input makes CR80 undefined Cautions 1 Before rewriting CR80 stop the timer operation If CR80 is rewritten while the timer operation is enabled the match interrupt request signal may be generated immediately at the point of rewrite 2 Do not clear CR80 to 00H in PWM output mode when PWMESO 1 bit 6 of 8 bit timer mode control register 80 TMC80 otherwise PWM output may not be produced normally 2 8 bit timer counter 80 TM80 TM80 is used to count the number of pulses Its contents are read with an 8 bit memory manipulation instruction RESET input clears TM80 to 00H 98 User s Manual U14801EJ3V1UD CHAPTER 7 8 BIT TIMER EVENT COUNTER 80 7 3 8 Bit Timer Event Counter 80 Control Registers The following three registers are used to control 8 bit timer event counter 80 e 8 bit timer mode control register 80 TMC80 Port mode register 2 PM2 Port 2 P2 1 8 bit timer mode control register 80 TMC80 TMC80 determines whether to enable or disable 8 bit timer counter 80 TM80 specifies the count clock for TM80 and controls the operation of the out
85. OLDERING CONDITIONS e Change of recommended soldering conditions of uPD78F9076 APPENDIX A DEVELOPMENT TOOLS e Modification of description of A 5 Debugging Tools Hardware Addition of APPENDIX B NOTES ON TARGET SYSTEM DESIGN U14801EJ3VOUD00 gt U14801EJ3V1UDOO Modification of 1 4 Ordering Information Modification of 1 5 Quality Grades Addition of Table 18 1 Surface Mounting Type Soldering Conditions 2 2 The mark x shows major revised points 6 User s Manual U14801EJ3V1UD Readers Purpose Organization How to Read This Manual INTRODUCTION This manual is intended for user engineers who wish to gain an understanding of the functions of the uPD789074 Subseries in order to design and develop its application systems and programs This manual is intended to give users an understanding of the functions described in the Organization below Two manuals are available for the uPD789074 Subseries this manual and the Instruction Manual common to the 78K 0S Series uPD789074 Subseries 78K 0S Series User s Manual User s Manual Instructions e Pin functions e CPU function e Internal block functions e Instruction set e Interrupts e Instruction description Other internal peripheral functions Electrical specifications It is assumed that the readers of this manual have general knowledge of electrical engineering logic circuits and microcontrollers For users who use this document as the manual for
86. Operation as interval timer When bits 4 and 3 WDTM4 WDTM3 of the watchdog timer mode register WDTM are set to O and 1 respectively the watchdog timer operates as an interval timer that repeatedly generates an interrupt at an interval specified by a preset count value Select a count clock or interval time by setting bits O to 2 WDCSO to WDCS2 of the watchdog timer clock selection register WDCS The watchdog timer starts operation as an interval timer when the RUN bit bit 7 of WDTM is set to 1 In interval timer mode the interrupt mask flag WDTMK is valid and a maskable interrupt INTWDT can be generated The priority of INTWDT is set as the highest of all the maskable interrupts The interval timer continues operation in HALT mode but stops in STOP mode Therefore first set RUN to 1 to clear the interval timer before executing the STOP instruction Cautions 1 Once bit 4 WDTM4 of WDTM is set to 1 when watchdog timer mode is selected interval timer mode is not set unless a RESET signal is input 2 The interval time may be up to 0 8 shorter than the set time when WDTM has just been set Table 8 5 Interval Generated Using Interval Timer WDCS2 WDCS1 WDCSO At fx 10 0 MHz Operation At fx 5 0 MHz Operation o o o zxm 205 us 41048 Note Expanded specification products only Remark fx System clock oscillation frequency 114 User s Manual U14801EJ3V1UD CHAPTER 9 SERIAL INTERFACE 20 9 1 Functions
87. PD789074MC xxx 5A4 30 pin plastic SSOP 7 62 mm 300 Mask ROM 1PD789071MC A xxx 5A4 30 pin plastic SSOP 7 62 mm 300 Mask ROM UPD789072MC A xxx 5A4 30 pin plastic SSOP 7 62 mm 300 Mask ROM UPD789074MC A xxx 5A4 30 pin plastic SSOP 7 62 mm 300 Mask ROM uPD78F9076MC 5A4 30 pin plastic SSOP 7 62 mm 300 Flash memory 11PD789071MC xxx 5A4 A 30 pin plastic SSOP 7 62 mm 300 Mask ROM UPD789072MC xxx 5A4 A 30 pin plastic SSOP 7 62 mm 300 Mask ROM UPD789074MC xxx 5A4 A 30 pin plastic SSOP 7 62 mm 300 Mask ROM uPD78F9076MC 5A4 A 30 pin plastic SSOP 7 62 mm 300 Flash memory Remarks 1 xxx indicates ROM code suffix 2 Products that have the part numbers suffixed by A are lead free products User s Manual U14801EJ3V1UD 21 x 1 5 Quality Grades Part Number CHAPTER 1 GENERAL Package Quality Grade uPD789071MC xxx 5A4 1PD789072MC xxx 5A4 1PD789074MC xxx 5A4 uPD78F9076MC 5A4 uPD789071MC A xxx 5A4 uPD789072MC A xxx 5A4 uPD789074MC A xxx 5A4 uPD789071MC xxx 5A4 A uPD789072MC xxx 5A4 A uPD789074MC xxx 5A4 A uPD78F9076MC 5A4 A 30 pin plastic SSOP 7 62 mm 300 30 pin plastic SSOP 7 62 mm 300 30 pin plastic SSOP 7 62 mm 300 30 pin plastic SSOP 7 62 mm 300 30 pin plastic SSOP 7 62 mm 300 30 pin plastic SSOP 7 62 mm 300 30 pin plastic SSOP 7 62 mm 300 30 pin plastic SSOP 7 62 mm 300 30 pin plastic SSOP 7 62 mm 300 30 pin plastic SSOP 7 62 mm 300 30 pin plastic SSOP 7 62 m
88. PMENT TOOLS 3rd edition e Addition of uPD789071 A 789072 A and 789074 A e Addition of description of expanded specification products Throughout e Addition of 1 1 Expanded Specification Products and Conventional Products Addition of 1 5 Quality Grades Addition of 1 10 Differences Between Standard Quality Grade Products and A Products CHAPTER 1 GENERAL Modification of description of 6 4 1 Operation as timer interrupt Modification of description of 6 4 2 Operation as timer output Addition of 6 5 Notes on Using 16 Bit Timer 90 Modification of Figure 6 6 Timing of Timer Interrupt Operation Modification of Figure 6 8 Timer Output Timing CHAPTER 6 16 BIT TIMER 90 Addition of 7 5 3 Timer operation after compare register is rewritten during PWM output Addition of 7 5 4 Cautions when STOP mode is set Addition of 7 5 5 Start timing of external event counter CHAPTER 7 8 BIT TIMER EVENT COUNTER 80 Total revision of description of flash memory programming User s Manual U14801EJ3V1UD CHAPTER 13 y PD78F9076 237 Edition 3rd edition APPENDIX D REVISION HISTORY Description Addition of chapter 2 2 Chapter CHAPTER 15 ELECTRICAL SPECIFICATIONS EXPANDED SPECIFICATION PRODUCTS Modification of table of recommended oscillator constant CHAPTER 16 ELECTRICAL SPECIFICATIONS CONVENTIONAL PRODUCTS Change of recommended soldering conditions of uPD78F9076 CHAPTER 18
89. RGC20 is performed during a communication operation the output of the baud rate generator is disrupted and communication cannot be performed normally Be sure not to write to BRGC20 during a communication operation 2 Be sure not to select n 1 during operation at fx gt 2 5 MHz because the resulting baud rate exceeds the rated range 3 Be sure not to select n 2 during operation at fx gt 5 0 MHz because the resulting baud rate exceeds the rated range 4 When the external input clock is selected set port mode register 2 PM2 to input mode Remarks 1 fx System clock oscillation frequency 2 n Value determined by setting TPS200 through TPS203 1 lt n lt 8 The baud rate transmit receive clock to be generated is either a signal divided from the system clock or a signal divided from the clock input from the ASCK20 pin i Generation of baud rate transmit receive clock from system clock The transmit receive clock is generated by dividing the system clock The baud rate of the clock generated from the system clock is estimated by using the following expression Baud rate LEE b Baud rate 537 bps fx System clock oscillation frequency n Value determined by setting TPS200 through TPS203 as shown in the above table 2 lt n lt 8 User s Manual U14801EJ3V1UD 131 CHAPTER 9 SERIAL INTERFACE 20 Table 9 5 Example of Relationship Between System Clock and Baud Rate Baud Rate fx 10 0 MHz fx 2 5 0 MHz fx 2 4 9152 M
90. Since this instruction is executed for 4 clocks if an interrupt occurs for 3 clocks after the execution starts the interrupt acknowledgment processing is performed after the MOV A r instruction is executed Figure 10 11 Interrupt Request Acknowledgment Timing When Interrupt Request Flag Is Set at Last Clock During Instruction Execution 8 clocks eie LS ep ET Ep gp Ed lr gs rp EG ol i i Interrupt CPU NOP MOV A r Saving PSW and PC jump servicing to interrupt servicing program Interrupt If an interrupt request flag xxIF is set at the last clock of the instruction the interrupt acknowledgment processing starts after the next instruction is executed Figure 10 11 shows an example of the interrupt acknowledgment timing for an interrupt request flag that is set at the second clock of NOP 2 clock instruction In this case the MOV A r instruction after the NOP instruction is executed and then the interrupt acknowledgment processing is performed Caution Interrupt requests are held pending while interrupt request flag register 0 or 1 IFO or IF1 or interrupt mask flag register 0 or 1 MKO or MK1 is being accessed 10 4 3 Multiple interrupt servicing Multiple interrupt servicing in which another interrupt is acknowledged while an interrupt is being serviced can be performed using a priority order system When two or more interrupts are generated at once interrupt servicing is performed according to the priority assigned to eac
91. TIMER 8 4 Watchdog Timer Operation 8 4 1 Operation as watchdog timer The watchdog timer detects an inadvertent program loop when bit 4 WDTM4 of the watchdog timer mode register WDTM is set to 1 The count clock inadvertent loop detection time interval of the watchdog timer can be selected by bits 0 to 2 WDCSO0 to WDCS2 of the watchdog timer clock selection register WDCS By setting bit 7 RUN of WDTM to 1 the watchdog timer is started Set RUN to 1 within the set inadvertent loop detection time interval after the watchdog timer has been started By setting RUN to 1 the watchdog timer can be cleared and start counting If RUN is not set to 1 and the inadvertent loop detection time is exceeded a system reset signal or a non maskable interrupt is generated depending on the value of bit 3 WDTM3 of WDTM The watchdog timer continues operation in HALT mode but stops in STOP mode Therefore first set RUN to 1 to clear the watchdog timer before executing the STOP instruction Caution The actual inadvertent loop detection time may be up to 0 8 shorter than the set time Table 8 4 Inadvertent Loop Detection Time of Watchdog Timer WDCS2 WDCS1 WDCSO Inadvertent Loop Detection Time At fx 10 0 MHz Operation At fx 5 0 MHz Operation o o o fax 205 us mis Note Expanded specification products only Remark fx System clock oscillation frequency User s Manual U14801EJ3V1UD 113 CHAPTER 8 WATCHDOG TIMER 8 4 2
92. TION SET OVERVIEW Mnemonic Operand Bytes Clocks Operation Z AC CY seo fame EE CCE fane sadar byte 8 6 1 saddr CY saddr byte CY 4 acre a r ov Dmm DET NE EZ ENTE Ama E IO EEES ENE DER e roren e ae NC poem ES sadar byte 3 6 saddr lt saddr byte We e ERREECHEN Ee am ape Aewe 0 EA ami x Ame seem pr mmm s s femten E ar fefafam ERN Am faa po ane s fe facavee pr Lang 1 e JAeAvHD E Amas p s SCHERER en emm o e e pe mme o e encen ES ar fefafam O ama fe fa faa CN EE am rpe eem dS aim fe e EXEC Remark One instruction clock cycle is one CPU clock cycle fcru selected by the processor clock control register PCC User s Manual U14801EJ3V1UD 189 CHAPTER 14 INSTRUCTION SET OVERVIEW Mnemonic Operand Bytes Clocks Operation Z AC CY w ame a pem roro ams s e mcm I ma fefef ENERO ha oe fo ears s e aceon for Dm a s em P ami e e aterm ERR Doo fame ps Ls pere mem sm mee fa fe eremo m fe om acewe oa Ls pem fo me fi eff ER RN EOS CI CO CA EE NINJ jojo Tr SA ES 9 o or CTC AA s ar s enm m E noe Jules Ie art e erm mte E wn pee s s CEEI 1 m s p m LLL am EIN INC CTC RN Prowse e rows ENEE mm rome Sid Dem os o em mes E m fe p o nme LLL D oe a nm LL mw NETA e rome IE mm II p rome E a O ram e NI de LH mon Te lI de L
93. TMIF80 TMMK80 INTTM90 TMIF90 TMMK90 User s Manual U14801EJ3V1UD 153 CHAPTER 10 INTERRUPT FUNCTIONS 1 Interrupt request flag registers 0 and 1 IFO and IF1 An interrupt request flag is set to 1 when the corresponding interrupt request is issued or when the related instruction is executed It is cleared to O when the interrupt request is acknowledged when a RESET signal is input or when a related instruction is executed IFO and IF1 are set with a 1 bit or 8 bit memory manipulation instruction RESET input clears IFO and IF1 to 00H Figure 10 2 Format of Interrupt Request Flag Register Symbol 7 6 b lt 4 gt lt B gt 2 lt gt lt 0 gt Address After reset R W IFO o STIF20 SRIF20 PIF2 PIF1 PIFO WDTIF FFEOH 00H R W 7 6 5 4 3 2 1 0 gt e o e o o e e moms rem om nm Interrupt request flag 9957 No interrupt request signal has been issued An interrupt request signal has been issued an interrupt request has been made Cautions 1 Bits 6 and 7 of IFO and bits 2 to 7 of IF1 must all be set to 0 2 The WDTIF flag can be read and write accessed only when the watchdog timer is being used as an interval timer It must be cleared to 0 if the watchdog timer is used in watchdog timer mode 1 or 2 3 When port 2 is being used as an output port and its output level is changed an interrupt request flag is set because this port is also used as an external interrupt input To use port 2 in output mode
94. V 1 0 10 0 MHz resonator eg Von 3 0 to 5 5 V 1 0 6 0 MHz Voo 1 8 to 5 5 V 1 0 5 0 MHz Oscillation stabilization Von 4 5 to 5 5 V 10 ms ies Von 1 8 to 5 5 V 30 ms External X1 input frequency fx Von 4 5 to 5 5 V 1 0 10 0 MHz clock xi X2 Voo 3 0 to 5 5 V 1 0 6 0 MHz Voo 1 8 to 5 5 V 1 0 5 0 MHz X1 input high low level width Voo 4 5 to 5 5 V 45 500 ns boba Voo 3 0 to 5 5 V 75 500 ns Voo 1 8 to 5 5 V 85 500 ns X1 x2 X1 input frequency fx Voo 2 7 to 5 5 V 1 0 5 0 MHz X1 input high low level width Voo 2 7 to 5 5 V 85 500 ns OPEN txn txL Notes 1 2 Caution 196 Indicates only oscillator characteristics Refer to AC Characteristics for instruction execution time Time required to stabilize oscillation after reset or STOP mode release Use the resonator that stabilizes oscillation within the oscillation wait time When using the system clock oscillator wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the wiring with the other signal lines Do not route the wiring near a signal line through which a high fluctuating current flows Always make the ground point of the oscillator capacitor the same potential as Vss Do not ground the capacitor to a ground pattern through which a high current flows Do not fet
95. When Ver supply During fx 5 0 MHz Voo pin voltage Ve operation Ippw When V supply voltage Ver Note Erase current Ver pin IPPE When Vrr supply voltage Ver Unit erase time PE oa EES KEE pp f le men ess pass Note The port current including the current that flows to the on chip pull up resistors is not included 208 User s Manual U14801EJ3V1UD CHAPTER 16 ELECTRICAL SPECIFICATIONS CONVENTIONAL PRODUCTS Absolute Maximum Ratings Ta 25 C Pme ffs omues o LL sees v SS Output current high uPD78907x 78F9076 10 Total for all pins Per pin uPD78907x A Total for all pins Output current low uPD78907x 78F9076 Total for all pins 160 mA Per pin uPD78907x A nn m Total for all pins 90 m Operating ambient temperature During normal operation During flash memory programming Storage temperature Tstg Mask ROM version Note Make sure that the following conditions of the Ver voltage application timing are satisfied when the flash memory is written e When supply voltage rises Vpp must exceed Vo 10 ws or more after Voo has reached the lower limit value 1 8 V of the operating voltage range see a in the figure below e When supply voltage drops Von must be lowered 10 ws or more after Ver falls below the lower limit value 1 8 V of the operating voltage range of Voo see b in the figure below Caution Product quality may suffer if the absolute max
96. XB20 results in a value being written to TXS20 Transmission controller The transmission controller controls transmission For example it adds start parity and stop bits to the data in transmit shift register 20 TXS20 according to the setting of asynchronous serial interface mode register 20 ASIM20 Reception controller The reception controller controls reception according to the setting of asynchronous serial interface mode register 20 ASIM20 It also checks for errors such as parity errors during reception If an error is detected asynchronous serial interface status register 20 ASIS20 is set according to the status of the error Users Manual U14801EJ3V1UD CHAPTER 9 SERIAL INTERFACE 20 9 3 Control Registers of Serial Interface 20 Serial interface 20 is controlled by the following six registers Serial operation mode register 20 CSIM20 Asynchronous serial interface mode register 20 ASIM20 Asynchronous serial interface status register 20 ASIS20 Baud rate generator control register 20 BRGC20 Port mode register 2 PM2 Port 2 P2 1 Serial operation mode register 20 CSIM20 CSIM20 is set when serial interface 20 is used in 3 wire serial I O mode CSIM20 is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears CSIM20 to 00H Figure 9 3 Format of Serial Operation Mode Register 20 lt 7 gt 6 Address After reset R W 5 4 3 2 4 0 CSIM20 o DAP20 DiR20 Joscx2o ckeao FF72H 00
97. abilization EE continues time wait l Watchdog i timer overflow Internal reset signal i TNS ee SV STOP instruction execution Stop status Resetperiod Oscillation Normal operati n Normal operation oscillation oscillation Stabilization stops stops time wait reset processing RESET Pg L i I Internal E X JG reset signal L l I I Delay Delay 172 User s Manual U14801EJ3V1UD CHAPTER 12 RESET FUNCTION Table 12 1 Status of Hardware After Reset KE Loaded with the contents of the reset vector table 0000H 0001 H Ports PO to P3 output latch CA CN CA CAN eeapengteet we on OH FFH OH 2H OH 00H 8 bit timer event counter Timer counter TM80 00H 00H OH 00H OH OH OH Program counter PC Compare register CR80 METI M moseas M OH Transmit shift register TXS20 FFH Receive buffer register RXB20 Undefined Interrupts Request flag registers IFO IF1 Mask flag registers MKO MK1 External interrupt mode register INTMO Notes 1 While a reset signal is being input and during the oscillation stabilization period the contents of the PC will be undefined while the remainder of the hardware will be the same as after the reset 2 In standby mode the RAM enters the hold state after a reset User s Manual U14801EJ3V1UD 173 CHAPTER 13 PD78F9076 The uPD78F9
98. addresses only word 16 bit immediate data or label byte 8 bit immediate data or label bit 3 bit immediate data or label Remark For symbols of special function registers see Table 3 3 Special Function Registers User s Manual U14801EJ3V1UD 185 CHAPTER 14 INSTRUCTION SET OVERVIEW 14 1 2 Description of Operation column 14 1 3 186 HE D BO our AR N UVUIOOO gt UO fm oO x PSW CY AC Z IE NMIS XH XL A vi vi addr16 jdisp8 A register 8 bit accumulator X register B register C register D register E register H register L register AX register pair 16 bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer Program status word Carry flag Auxiliary carry flag Zero flag Interrupt request enable flag Flag indicating non maskable interrupt servicing in progress Memory contents indicated by address or register contents in parentheses Higher 8 bits and lower 8 bits of 16 bit register Logical product AND Logical sum OR Exclusive logical sum exclusive OR Inverted data 16 bit immediate data or label Signed 8 bit data displacement value Description of Flag column Blank 0 1 x R Unchanged Cleared to 0 Set to 1 Set cleared according to the result Previously saved value is stored User s Manual U14801EJ3V1UD CHAPTER 14 INSTRUCTION SET OVERVIEW 14 2 Operation List Mnemonic Operand Bytes
99. age Necessary for changing the object library included in the C compiler package according to the customer s specifications Since this is a source file its working environment does not depend on any particular operating system Part number SxxxxCC78K0S L Notes 1 DF789076 is a common file that can be used with RA78KOS CC78KO0S ID78KOS NS and SM78KOS 2 CC78KOS L is not included in the software package SP78KOS User s Manual U14801EJ3V1UD 227 APPENDIX A DEVELOPMENT TOOLS Remark xxxx in the part number differs depending on the host machine and operating system used USxxxxRA78K0S USXxxxCC78K0S PC 9800 series Er Windows 3 5 2HD FD peis IBM PC AT and compatibles English Windows Windows Japanese Windows CD ROM English Windows 3P17 HP9000 series 700 HP UX Rel 10 10 SPARCstation SunOS Rel 4 1 4 Solaris Rel 2 5 1 USxxxxDF789076 USxxxxCC78K0S L AB13 PC 9800 series Japanese Windows 3 5 2HD FD BB13 IBM PC AT and compatibles English Windows 3K13 SPARCstation SunOS Rel 4 1 4 3 5 2HD FD 3K15 Solaris Rel 2 5 1 1 4 CGMT A 3 Control Software Project manager Control software provided for efficient user program development in the Windows environment The project manager allows a series of tasks required for user program development to be performed including starting the editor building and starting the debugger lt Caution gt The project manager is included in the
100. al clock frequency Du Hz fx System clock oscillation frequency n Value determined by setting TPS200 to TPS203 as shown in the above table 1 n lt 8 142 User s Manual U14801EJ3V1UD CHAPTER 9 SERIAL INTERFACE 20 2 Communication operation In 3 wire serial l O mode data transmission reception is performed in 8 bit units Data is transmitted received bit by bit in synchronization with the serial clock Transmit shift register 20 TXS20 SIO20 and receive shift register 20 RXS20 shift operations are performed in synchronization with the fall of the serial clock SCK20 Then transmit data is held in the SO20 latch and output from the SO20 pin Also receive data input to the SI20 pin is latched in receive buffer register 20 RXB20 SIO20 on the rise of SCK20 At the end of an 8 bit transfer the operation of TXS20 SIO20 and RXS20 stops automatically and the interrupt request signal INTCSI20 is generated Figure 9 11 3 Wire Serial UO Mode Timing 1 7 i Master operation timing when DAP20 0 CKP20 0 SSE20 0 SIO20 Write T SCK20 S020 Note SI20 INTCSI20 Note The value of the last bit previously output is output User s Manual U14801EJ3V1UD 143 CHAPTER 9 SERIAL INTERFACE 20 Figure 9 11 3 Wire Serial UO Mode Timing 2 7 ii Slave operation timing when DAP20 0 CKP20 0 SSE20 0 SIO20 Write SCK20 120 5020 INTCSI20 Note The value of the last bit previously
101. al interface UART mode e 3 wire serial UO mode 9 4 1 Operation stop mode In operation stop mode serial transfer is not executed therefore the power consumption can be reduced The P20 SCK20 ASCK20 P21 5020 TxD20 and P22 SI20 RxD20 pins can be used as normal I O ports 1 Register setting Operation stop mode is set by serial operation mode register 20 CSIM20 and asynchronous serial interface mode register 20 ASIM20 a Serial operation mode register 20 CSIM20 CSIM20 is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears CSIM20 to 00H Symbol lt 7 gt Address After reset R W 6 5 4 3 2 1 0 CSIM20 CSIE20 SSE20 ECCE DAP20 DIR20 CSCK20 CKP20 FF72H 00H R W CSIE20 3 wire serial l O mode operation control Operation disabled 1 Operation enabled Caution Bits 4 and 5 must both be set to 0 b Asynchronous serial interface mode register 20 ASIM20 ASIM20 is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears ASIM20 to 00H Symbol 7 Address After reset R W lt 6 gt 5 4 3 2 1 0 ASIM20 TXE20 RXE20 Ps201 PS200 oan SL20 ae FF70H 00H R W TXE20 Transmit operation control o Transmit operation stop Transmit operation enable RXE20 Receive operation control NN Receive operation stop Receive operation enable Caution Bits 0 and 1 must both be set to 0 126 User s Manual U14801EJ3V1UD CHAPTER 9 SERIAL INTERFACE 20 9 4 2 A
102. anual U14801EJ3V1UD CHAPTER 14 INSTRUCTION SET OVERVIEW 2 16 bit instructions MOVW XCHW ADDW SUBW CMPW PUSH POP INCW DECW 2nd Operand word AX rp saddrp SP None 1st Operand ADDW MOVW MOVW MOVW SUBW XCHW CMPW i u MN Note Only when rp BC DE or HL 3 Bit manipulation instructions SET1 CLR1 NOT1 BT BF 2nd Operand addr16 None 1st Operand A bit BT SET1 BF CLR1 sfr bit BT SET1 BF CLR1 saddr bit BT SET1 BF CLR1 PSW bit BT SETI BF CLR1 HL bit SET1 CLR1 CY User s Manual U14801EJ3V1UD 193 CHAPTER 14 INSTRUCTION SET OVERVIEW 4 Call instructions branch instructions CALL CALLT BR BC BNC BZ BNZ DBNZ 2nd NS ong laddr16 addr5 addr16 1st NS ong Basic instructions Sg CALL CALLT 5 Other instructions RET RETI NOP EI DI HALT STOP 194 User s Manual U14801EJ3V1UD CHAPTER 15 ELECTRICAL SPECIFICATIONS EXPANDED SPECIFICATION PRODUCTS Absolute Maximum Ratings Ta 25 C Pme ffs omues o LL sees v SS Output current high uPD78907x 78F9076 10 Total for all pins Per pin uPD78907x A Total for all pins Output current low uPD78907x 78F9076 Total for all pins 160 mA Per pin uPD78907x A nn m Total for all pins 90 m Operating ambient temperature During normal operation During flash memory programming Storage temperature Tstg Mask ROM version Note Make sure that the following conditions of the Ver voltage application t
103. ark of SPARC International Inc Solaris and SunOS are trademarks of Sun Microsystems Inc These commodities technology or software must be exported in accordance with the export administration regulations of the exporting country Diversion contrary to the law of that country is prohibited The information in this document is current as of August 2005 The information is subject to change without notice For actual design in refer to the latest publications of NEC Electronics data sheets or data books etc for the most up to date specifications of NEC Electronics products Not all products and or types are available in every country Please check with an NEC Electronics sales representative for availability and additional information e No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics NEC Electronics assumes no responsibility for any errors that may appear in this document e NEC Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products No license express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Electronics or others e Descriptions of circuits software and other relate
104. assembler package RA78K0S It cannot be used in an environment other than Windows 228 User s Manual U14801EJ3V1UD APPENDIX A DEVELOPMENT TOOLS A 4 Flash Memory Writing Tools Flashpro III FL PR3 PG FP3 Flash programmer dedicated to microcontrollers incorporating flash memory Flashpro IV FL PR4 PG FP4 Flash writer FA 30MC Flash memory writing adapter Used in connection with Flashpro III or Flashpro IV Flash memory writing adapter 30 pin plastic SSOP MC 5A4 type Remark FL PR3 FL PR4 and FA 30MC are products of Naito Densei Machida Mfg Co Ltd For further information contact Naito Densei Machida Mfg Co Ltd 81 45 475 4191 A 5 Debugging Tools Hardware IE 78KOS NS In circuit emulator for debugging hardware and software of application system using the In circuit emulator 78K 0S Series Can be used with an integrated debugger ID78KOS NS Used in combination with an AC adapter emulation probe and interface adapter for connecting the host machine IE 78KOS NS A In circuit emulator with enhanced functions of the IE 78KOS NS The debug function is further In circuit emulator enhanced by adding a coverage function and enhancing the tracer and timer functions IE 70000 MC PS B Adapter for supplying power from a 100 to 240 VAC outlet AC adapter IE 70000 98 IF C Adapter required when using a PC 9800 series except notebook type as the host machine C Interface adapter bus supported IE 70000 CD IF A PC car
105. ation Operation Operation Operation Note Expanded specification products only Remark fx System clock oscillation frequency 2 External event counter The number of pulses of an externally input signal can be counted 3 Square wave output A square wave of arbitrary frequency can be output Table 7 2 Square Wave Output Range of 8 Bit Timer Event Counter 80 Minimum Pulse Width Maximum Pulse Width Resolution At fx 2 10 0 MHz At fx 2 5 0 MHz At fx 2 10 0 MHz At fx 2 5 0 MHz At fx 2 10 0 MHz At fx 2 5 0 MHz Operation Operation Operation Operation Operation Operation Note Expanded specification products only Remark fx System clock oscillation frequency 4 PWM output 8 bit resolution PWM output can be produced User s Manual U14801EJ3V1UD 97 CHAPTER 7 8 BIT TIMER EVENT COUNTER 80 7 2 Configuration of 8 Bit Timer Event Counter 80 8 bit timer event counter 80 includes the following hardware Table 7 3 Configuration of 8 Bit Timer Event Counter 80 ES Compare register 8 bits x 1 CR80 Control registers 8 bit timer mode control register 80 TMC80 Port mode register 2 PM2 Port 2 P2 Figure 7 1 Block Diagram of 8 Bit Timer Event Counter 80 Internal bus 8 bit compare register 80 CR80 Match TI80 P27 if gt INTTM80 TO80 5 JO 8 bit timer counter 2 80 TM80 oO fx 28 0 O T
106. atus word PSW The program status word is an 8 bit register consisting of various flags to be set reset by instruction PC execution Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are automatically restored upon execution of the RETI and POP PSW instructions RESET input sets the PSW to 02H Figure 3 10 Program Status Word Configuration 7 0 rw te z o acl o o tj er 46 User s Manual U14801EJ3V1UD a b c d CHAPTER 3 CPU ARCHITECTURE Interrupt enable flag IE This flag controls interrupt request acknowledge operations of the CPU When IE 0 the interrupt disabled DI status is set All interrupt requests except non maskable interrupts are disabled When IE 1 the interrupt enabled El status is set Interrupt request acknowledgment is controlled with an interrupt mask flag for each interrupt source This flag is reset to 0 upon DI instruction execution or interrupt acknowledgment and is set to 1 upon El instruction execution Zero flag Z When the operation result is zero this flag is set to 1 It is reset to 0 in all other cases Auxiliary carry flag AC If the operation result has a carry from bit 3 or a borrow at bit 3 this flag is set to 1 It is reset to 0 in all other cases Carry flag CY This flag stores overflow and underflow that have occurred upon add subtract instruction execution lt st
107. ause the resulting baud rate exceeds the rated range 2 Be sure not to select n 2 during operation at fx 5 0 MHz because the resulting baud rate exceeds the rated range 124 User s Manual U14801EJ3V1UD CHAPTER 9 SERIAL INTERFACE 20 b Generation of baud rate transmit receive clock from external clock input from ASCK20 pin The transmit receive clock is generated by dividing the clock input from the ASCK20 pin The baud rate of a clock generated from the clock input from the ASCK20 pin is estimated by using the following expression f Baud rate SE 16 bps fasck Frequency of clock input from the ASCK20 pin Table 9 4 Relationship Between ASCK20 Pin Input Frequency and Baud Rate When BRGC20 Is Set to 80H Baud Rate bps ASCK20 Pin Input Frequency kHz c Generation of serial clock in 3 wire serial UO mode from system clock The serial clock is generated by dividing the system clock The serial clock frequency is estimated by using the following expression BRGC20 does not need to be set when an external serial clock is input to the SCK20 pin f Serial clock frequency EE Hz fx System clock oscillation frequency n Value shown in Figure 9 6 determined by setting TPS200 through TPS203 1 lt n lt 8 User s Manual U14801EJ3V1UD 125 CHAPTER 9 SERIAL INTERFACE 20 9 4 Operation of Serial Interface 20 Serial interface 20 provides the following three modes e Operation stop mode e Asynchronous seri
108. ble 12 1 Each pin is high impedance during reset input or during the oscillation stabilization time just after reset clear When a high level is input to the RESET pin the reset is cleared and program execution is started after the oscillation stabilization time has elapsed The reset applied by the watchdog timer overflow is automatically cleared after reset and program execution is started after the oscillation stabilization time has elapsed see Figures 12 2 through 12 4 Cautions 1 For an external reset input a low level of 10 ys or more to the RESET pin 2 When STOP mode is cleared by reset the STOP mode contents are held during reset input However the port pins become high impedance Figure 12 1 Block Diagram of Reset Function Reset controller Reset signal Count clock Watchdog timer Interrupt function User s Manual U14801EJ3V1UD 171 CHAPTER 12 RESET FUNCTION Figure 12 2 Reset Timing by RESET Input ud tees SNE Reset period Oscillation e Normal operation m illati ilizati Normal operation D oscillation stabilization reset processing I stops time wait H I l d RESET i i i i d I L I I Internal reset signal A SS A bg ret Delay Delay Hi Z II E Ee Ee EE ee Ee melde cm Figure 12 3 Reset Timing by Watchdog Timer Overflow NNN Reset period Oscillation Normal operation oscillation st
109. c pee epo dt cane dL ck nnne ic Duae e DL a dd aa dc nu uen dL rung 30 2 1 PIN FUNCTION MIS DTE m 30 2 2 Description of Pin Functions s rrrsannvnnnnnnnvnnnnnnnnvnnnnnnnnnnnnnnnnnennnnnnnennnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnenn 32 2 2 1 P00 t0 P07 POrEO Larsen 32 222 Es GA See net 32 228 vP20 tO P27 POD A e E ER ERRORES 32 224 30 ET E EE ER 255 FEE NS SN 33 2 2 6 appo 33 2 2 7 oM 33 2 2 8 cca EM EE 33 2 2 9 Ver IS rnent 34 2 2 10 IC mask ROM version only d araar ara aaa eaaa as ae aa rea A Ooa Era aa aa Aaa a aoaaa EAR ETNEA TESA 34 2 3 Pin I O Circuits and Recommended Connection of Unused Pins 35 CHAPTER 3 CPU ARCHITECTURE nnrnnnnnnnvvvennnnvvnennnnnvnvennnnvenennnnvenennnnvenennnnnnnennnnnennennnnnenennnnvnnennnnnnnennn 37 3 1 E ele 37 3 1 1 Internal program memory SPACe mrrnnnnnrnrnnnnonnnnvnnnnnnnnntnrnnnnennvnrnnnnnnnnnenvnnnnenvnnnnennnnvnnenvnnenenrnnnnen 41 3 1 2 Internal data memory internal high speed RAM space annrnnnnvnnnnrnnnnrnnnvrnnnnnnenrrnrnvnnenrrnenvnnennn 41 3 1 3 Special function register SFR are 41 3 1 4 Data memory addressing EE 42 3 2 Processor Registers iii eee eene 46 3 2 1 Control registers 5 9 enkeier et edge A p Rete pce Edu 46 3 2 2 General purpose registers EE 49 3 2 3 Special function registers SFRS A 50 3 3 Instruction Address Addressing
110. ch signals from the oscillator User s Manual U14801EJ3V1UD CHAPTER 15 ELECTRICAL SPECIFICATIONS EXPANDED SPECIFICATION PRODUCTS Recommended Oscillator Constant Ceramic resonator Ta 40 to 85 C Mask ROM version Manufacturer Frequency Oscillation Voltage Remarks MHz Constant pF Range Voo Io Jun I MAX Murata Mfg CSBLA1M00J58 BO0 cero 5 5 Re 1 0kQ standard product See chip CSTCC2M00G56 RO capacitor CSTCR4M00G53 RO CSTLS4M00GG53 BO CSTCR4M19G53 RO CSTLS4M19GG53 BO CSTCR4M91G53 RO CSTLS4M91GG53 BO CSTCR5M00G53 RO CSTLS5M00GG53 BO CSTCR6M00G53 RO CSTLS6M00GG53 BO CSTCE8M00G52 RO CSTLS8M00G53 BO CSTCE8M38G52 RO CSTLS8M38G53 BO CSTCE10M0G52 RO CSTLS10M0G53 BO Murata Mfg CSTCR6M00G53093 RO On chip Co Ltd low CSri seMo0GG53093 BO capacitor voltage drive wpol CSTLS8M00G53093 B0 80 CSTLS8M38G53093 B0 8 388 CSTLS10M0G53093 B0 Note A limiting resistor Rd 1 0 kQ is required when CSBLA1M00J58 BO or CSBFB1M00J58 R1 1 0 MHz manufactured by Murata Mfg Co Ltd is used as the ceramic resonator see the figure below This is not necessary when using one of the other recommended resonators CSBLA1M00J58 BO CSBFB1M00J58 R1 m i Caution The oscillator constant is a reference value based on evaluation in specific environments by the Rd C1 resonator manufacturer If the oscillator characteristics need to be optimized in the actual application reque
111. counter 90 TM90 S e que 0000H FF19H FF1AH 16 bit capture register 90 TCP90 Nez quee Undefined FF1BH sp dex mm sm dns W FF42H Watchdog timer clock selection WDCS register 2 W FF70H Asynchronous serial interface mode ASIM20 register 20 FF71H Asynchronous serial interface status ASIS20 register 20 FF72H Serial operation mode register 20 CSIM20 R W FF73H Baud rate generator control register 20 BRGC20 Notes 1 These SFRs are for 16 bit access only 2 CR90 TM90 and TCP90 are designed only for 16 bit access In direct addressing however 8 bit access can also be performed 3 16 bit access is allowed only in short direct addressing User s Manual U14801EJ3V1UD 51 CHAPTER 3 CPU ARCHITECTURE Table 3 3 Special Function Registers 2 2 Address Special Function Register SFR Name Symbol R W After Reset R WE OH FFH FFFAH Oscillation stabilization time selection OSTS register FFFBH Processor clock control register 2 52 Users Manual U14801EJ3V1UD CHAPTER 3 CPU ARCHITECTURE 3 3 Instruction Address Addressing An instruction address is determined by the program counter PC contents The PC contents are normally incremented 1 for each byte automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed When a branch instruction is executed the branch destination address information is set to the PC to branch by th
112. d and interface cable required when using a notebook type PC as the host machine PC card interface PCMICA socket supported IE 70000 PC IF C Adapter required when using an IBM PC AT or compatible as the host machine ISA bus Interface adapter supported IE 70000 PCI IF A Adapter required when using a personal computer incorporating the PCI bus as the host Interface adapter machine IE 789046 NS EM1 NP K907 Emulation board for emulating the peripheral hardware inherent to the device Emulation board Used in combination with an in circuit emulator NP 30MC Probe for connecting the in circuit emulator and target system Emulation probe Used in combination with NSPACK30BK and YSPACK30BK NSPACK30BK Conversion adapter used to connect a target system board designed to allow mounting a 30 YSPACK30BK pin plastic SSOP and the NP 30MC Conversion adapter Remarks 1 NP 30MC and NP K907 are products of Naito Densei Machida Mfg Co Ltd For further information contact Naito Densei Machida Mfg Co Ltd 81 45 475 4191 2 NSPACK30BK and YSPACK30BK are products made by TOKYO ELETECH CORPORATION For further information contact Daimaru Kogyo Ltd Tokyo Electronics Department TEL 81 3 3820 7112 Osaka Electronics Department TEL 81 6 6244 6672 User s Manual U14801EJ3V1UD 229 APPENDIX A DEVELOPMENT TOOLS A 6 Debugging Tools Software ID78KOS NS This debugger supports the in circuit emulators IE 78KOS NS and IE 78KOS NS A for t
113. d information in this document are provided for illustrative purposes in semiconductor product operation and application examples The incorporation of these circuits software and information in the design of a customer s equipment shall be done under the full responsibility of the customer NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information e While NEC Electronics endeavors to enhance the quality reliability and safety of NEC Electronics products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC Electronics products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features e NEC Electronics products are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to NEC Electronics products developed based on a customer designated quality assurance program for a specific application The recommended applications of an NEC Electronics product depend on its quality grade as indicated below Customers must check the quality grade of each NEC Electronics product before using it in a particular application Standard Computers office eq
114. defined 4 4 2 Reading from I O port 1 2 In output mode The contents of the output latch can be read by using a transfer instruction The contents of the output latch are not changed In input mode The status of a pin can be read by using a transfer instruction The contents of the output latch are not changed 4 4 3 Arithmetic operation of l O port 74 1 2 In output mode An arithmetic operation can be performed with the contents of the output latch The result of the operation is written to the output latch The contents of the output latch are output from the port pins Once data is written to the output latch it is retained until new data is written to the output latch In input mode The contents of the output latch become undefined However the status of the pin is not changed because the output buffer is OFF Caution A 1 bit memory manipulation instruction is executed to manipulate one bit of a port However this instruction accesses the port in 8 bit units When this instruction is executed to manipulate a bit of a port consisting both of inputs and outputs therefore the contents of the output latch of the pin that is set to input mode and not subject to manipulation become undefined User s Manual U14801EJ3V1UD CHAPTER 5 CLOCK GENERATOR 5 1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware e Expanded specification products Th
115. e following addressing for details of each instruction refer to 78K 0S Series Instructions User s Manual U11047E 3 3 1 Relative addressing Function The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to the program counter PC and branched The displacement value is treated as signed two s complement data 128 to 127 and bit 7 becomes the sign bit In other words the range of branch in relative addressing is between 128 and 127 of the start address of the following instruction This function is carried out when the BR addr16 instruction or a conditional branch instruction is executed Illustration PC is the start address of PC f the next instruction of a BR instruction 15 8 7 6 0 HE 18M 1 jdisp8 15 0 09 When S 20 a indicates that all bits are 0 When S 1 a indicates that all bits are 1 User s Manual U14801EJ3V1UD 53 CHAPTER 3 CPU ARCHITECTURE 3 3 2 Immediate addressing Function Immediate data in the instruction word is transferred to the program counter PC and branched This function is carried out when the CALL addr16 and BR laddr16 instructions are executed CALL addr16 and BR addr16 instructions can be used to branch to all the memory spaces Illustration In case of CALL addr16 and BR laddr16 instructions CALL or BR
116. e system oscillator oscillates a frequency of 1 0 to 10 0 MHz Oscillation can be stopped by executing the STOP instruction e Conventional products The system oscillator oscillates a frequency of 1 0 to 5 0 MHz Oscillation can be stopped by executing the STOP instruction 5 2 Clock Generator Configuration The clock generator includes the following hardware Table 5 1 Configuration of Clock Generator Control register Processor clock control register PCC Oscillator Crystal ceramic oscillator Figure 5 1 Block Diagram of Clock Generator es LO Clock to peripheral hardware Standby Wait PCC1 Processor clock control register PCC Internal bus X1 T System clock x2 O oscillator STOP Selector User s Manual U14801EJ3V1UD 75 CHAPTER 5 CLOCK GENERATOR 5 3 Clock Generator Control Register The clock generator is controlled by the following register e Processor clock control register PCC 1 Processor clock control register PCC PCC selects the CPU clock and the division ratio PCC is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PCC to 02H Figure 5 2 Format of Processor Clock Control Register Symbol 7 6 5 4 3 2 1 0 Address After reset R W CPU clock fcru selection Minimum instruction execution time 2 fceu At fx 10 0 MHzNete At fx 2 5 0 MHz pr fe T Note Expanded specification products only Caution Bits 0 and 2 to 7 must all be
117. edance state vii Master operation when DAP20 1 CKP20 0 SSE20 0 SIO20 Write SCK20 020 120 INTCSI20 146 User s Manual U14801EJ3V1UD CHAPTER 9 SERIAL INTERFACE 20 Figure 9 11 3 Wire Serial l O Mode Timing 5 7 viii Slave operation when DAP20 1 CKP20 0 SSE20 0 SIO20 Write SCK20 SIO20 Write master Note SI20 5020 INTCSI20 Note The data of SI20 is loaded at the first falling edge of SCK20 Make sure that the master outputs the first bit before the first falling of SCK20 ix Slave operation when DAP20 1 CKP20 0 SSE20 1 SS20 SIO20 Write SCK20 SI20 INTCSI20 PI Notes 1 The data of SI20 is loaded at the first falling edge of SCK20 Make sure that the master outputs the first bit before the first falling of SCK20 2 SO20 is high until SS20 rises after completion of DOO output When SS20 is high SO20 is in a high impedance state User s Manual U14801EJ3V1UD 147 CHAPTER 9 SERIAL INTERFACE 20 Figure 9 11 3 Wire Serial UO Mode Timing 6 7 x Master operation when DAP20 1 CKP20 1 SSE20 0 SIO20 Write SCK20 SO20 SI20 INTCSI20 Note The value of the last bit previously output is output xi Slave operation when DAP20 1 CKP20 1 SSE20 0 SIO20 Write SCK20 SI20 SO20 INTCSI20 Note The value of the last bit previously output is output 148 User s Manual U14801EJ3V1UD
118. eive operation enable PS201 PS200 Parity bit specification mage Always add 0 parity at transmission Parity check is not performed at reception no parity error occurs of osean EE CL20 Transmit data character length specification IU NN Transmit data stop bit length Cautions 1 Bits 0 and 1 must both be set to 0 2 If 3 wire serial I O mode is selected ASIM20 must be cleared to 00H 3 Switch operating modes after halting the serial transmit receive operation Users Manual U14801EJ3V1UD CHAPTER 9 SERIAL INTERFACE 20 Table 9 2 Operating Mode Settings of Serial Interface 20 1 Operation stop mode ASIM20 CSIM20 First Shift P22 SI20 P21 5020 P20 SCK20 Bit Clock RxD20 Pin TxD20 Pin ASCK20 Pin Function Function Function TXE20 RXE20 CSIE20 DIR20 CSCK20 Other than above Setting prohibited 2 3 wire serial UO mode ASIM20 CSIM20 P22 SI20 P21 SO20 P20 SCK20 RxD20 Pin TxD20 Pin ASCK20 Pin Function Function Function TXE20 RXE20 CSIE20 DIR20 CSCK20 leie External SI20 S020 clock CMOS output Internal clock External clock Internal clock Other than above Setting prohibited 3 Asynchronous serial interface mode ASIM20 CSIM20 P22 SI20 P21 SO20 P20 SCK20 RxD20 Pin TxD20 Pin ASCK20 Pin Function Function Function TXE20 RXE20 CSIE20 DIR20
119. er the DOS environment A 2 Language Processing Software RA78K0S Assembler package CC78K0S C compiler package DF789076 Device file CC78K0S L C library source file Program that converts program written in mnemonic into object codes that can be executed by a microcontroller In addition automatic functions to generate a symbol table and optimize branch instructions are also provided Used in combination with a device file DF789076 sold separately lt Caution when used in PC environment gt The assembler package is a DOS based application but may be used in the Windows environment by using the project manager of Windows included in the package Part number SxxxxRA78K0S Program that converts program written in C language into object codes that can be executed by a microcontroller Used in combination with an assembler package RA78K0S and device file DF789076 both sold separately lt Caution when used in PC environment gt The C compiler package is a DOS based application but may be used in the Windows environment by using the project manager of Windows included in the assembler package Part number SxxxxCC78K0S File containing the information inherent to the device Used in combination with other tools RA78K0S CC78KO0S ID78KOS NS SM78KOS all sold separately Part number 4 S xxDF789076 Source file of functions constituting the object library included in the C compiler pack
120. er to use on chip pull up resistors can be specified in 1 bit units by using pull up resistor option register B2 PUB2 regardless of the setting of port mode register 2 PM2 2 Control mode In this mode P20 to P27 function as the timer input output and the serial interface data and clock input output a TI80 This is the external clock input pin for the 8 bit timer event counter 80 b TO80 This is the timer output pin of the 8 bit timer event counter 80 c INTPO to INTP2 These are external interrupt input pins for which the valid edge rising edge falling edge or both rising and falling edges can be specified d CPT90 This is the capture edge input pin of the 16 bit timer counter 90 e SI20 SO20 This is the serial data I O pin of the serial interface f SCK20 This is the serial clock I O pin of the serial interface g SS20 This is the chip select input pin of the serial interface 32 Users Manual U14801EJ3V1UD CHAPTER 2 PIN FUNCTIONS h RxD20 TxD20 These are the serial data I O pins of the asynchronous serial interface i ASCK20 This is the serial clock input pin of the asynchronous serial interface Caution When using P20 to P27 as serial interface pins the input output mode and output latch must be set according to the functions to be used For details of the setting see Table 9 2 Serial Interface 20 Operation Mode Settings 2 2 4 P30 P31 Port 3 These pins constitute a 2 bit I O port
121. f SCK20 Outputs at the rising edge of SCK20 DIR20 First bit specification KO CO CSCK20 3 wire serial I O mode clock selection EN External clock input to the SCK20 pin Output of the dedicated baud rate generator 3 wire serial UO mode clock phase selection Clock is active low and SCK20 is high level in the idle state Clock is active high and SCK20 is low level in the idle state Caution Bits 4 and 5 must both be set to 0 128 User s Manual U14801EJ3V1UD CHAPTER 9 SERIAL INTERFACE 20 b Asynchronous serial interface mode register 20 ASIM20 ASIM20 is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears ASIM20 to 00H Symbol lt 7 gt Address After reset R W TXE20 Transmit operation control o Transmit operation stopped Transmit operation enabled RXE20 Receive operation control o Receive operation stopped Receive operation enabled PS201 PS200 Parity bit specification Co em LL 1 Always add 0 parity at transmission Parity check is not performed at reception No parity error is generated Mee O CL20 Character length specification Cautions 1 Bits 0 and 1 must both be set to 0 2 Switch operating modes after halting the serial transmit receive operation User s Manual U14801EJ3V1UD 129 CHAPTER 9 SERIAL INTERFACE 20 c Asynchronous serial interface status register 20 ASIS20 ASIS20 is read with a 1 bit or 8 bit memory manipulation instruction RES
122. f STOP mode STOP mode is set by executing the STOP instruction Caution Because standby mode can be released by an interrupt request signal standby mode is released as soon as it is set if there is an interrupt source whose interrupt request flag is set and interrupt mask flag is reset When STOP mode is set therefore HALT mode is set immediately after the STOP instruction has been executed the wait time set by the oscillation stabilization time selection register OSTS elapses and then the operation mode is set The operation statuses in STOP mode are shown in the following table Table 11 3 Operation Statuses in STOP Mode Note Maskable interrupt that is not masked User s Manual U14801EJ3V1UD 169 CHAPTER 11 STANDBY FUNCTION 2 Releasing STOP mode STOP mode can be released by the following two sources a Releasing by unmasked interrupt request STOP mode can be released by an unmasked interrupt request In this case vectored interrupt servicing is performed if interrupt acknowledgment is enabled after the oscillation stabilization time has elapsed If interrupt acknowledgment is disabled the instruction at the next address is executed Figure 11 4 Releasing STOP Mode by Interrupt Wait STOP time set by OSTS instruction gt Standby Ge release signal ERAN Operating Oscillation stabilization Operating mode STOP mode wait status mode Oscillation Clock Oscillation stop Oscillation
123. f rewrite an interrupt request will be generated if interrupts are enabled 2 If setting the count clock to TMC80 and enabling the operation of TM80 are performed at the same time with an 8 bit memory manipulation instruction the error one cycle after the timer has been started may exceed one clock To use 8 bit timer event counter 80 as an interval timer therefore make the settings in the above sequence Table 7 4 Interval Time of 8 Bit Timer Event Counter 80 TCL801 TCL800 Minimum Interval Time Maximum Interval Time Resolution At fx 10 0 MHz At fx 5 0 MHz At fx 10 0 MHz At fx 5 0 MHz At fx 10 0 MHz At fx 5 0 MHz Operation Operation Operation Operation Operation Operation T180 input cycle x TI80 input cycle T180 input edge cycle T180 input cycle 2 x TI80 input cycle TI80 input edge cycle Note Expanded specification products only Remark fx System clock oscillation frequency User s Manual U14801EJ3V1UD 101 CHAPTER 7 8 BIT TIMER EVENT COUNTER 80 Figure 7 4 Interval Timer Operation Timing ron cou vave A A A I Clear Clear I 1 D 1 i i 1 i i creo N i TCE80 INTTMBO EP i Interrupt acknowledgment Interrupt acknowledgment I I i I l TO80 i ES ea I l l 1 Interval time Interval time Interval time Remark Interval time N 1 xt N 00H to FFH 102 User s Manual U14801EJ3V1UD CHAPTER 7 8 BIT TIMER EVENT COUNTER 80 7 4 2 O
124. g Pin temperature 350 C max Time 3 seconds max per pin row E uPD78F9076MC 5A4 30 pin plastic SSOP 7 62 mm 300 Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature 235 C Time 30 seconds max at 210 C or higher IR35 107 3 Count Three times or less Exposure limit 7 days after that prebaking is necessary at 125 C for 10 hours Package peak temperature 215 C Time 40 seconds max at 200 C or higher VP15 107 3 Count Three times or less Exposure limit 7 days after that prebaking is necessary at 125 C for 10 hours Wave soldering Solder bath temperature 260 C max Time 10 seconds max WS60 107 1 Count Once Preheating temperature 120 C max package surface temperature Exposure limit 7 days after that prebake at 125 C for 10 hours Partial heating Pin temperature 350 C max Time 3 seconds max per pin row i ee Note After opening the dry pack store it at 25 C or less and 65 RH or less for the allowable storage period Caution Do not use different soldering methods together except for partial heating User s Manual U14801EJ3V1UD 223 CHAPTER 18 RECOMMENDED SOLDERING CONDITIONS Table 18 1 Surface Mounting Type Soldering Conditions 2 2 1PD789071MC xxx 5A4 A 30 pin plastic SSOP 7 62 mm 300 uPD789072MC xxx 5A4 A 30 pin plastic SSOP 7 62 mm 300 uPD789074MC xxx 5A4 A 30 pin plastic SSOP 7 62 mm 30
125. g the pins of port 2 for the serial interface the I O and output latches must be set according to the function to be used For details of the settings see Table 9 2 Operation Mode Settings of Serial Interface 20 Figure 4 4 Block Diagram of P20 Voo WRrus2 P ch A Alternate function Internal bus c Gs 1 P20 ASCK20 SCK20 Alternate Be function PUB2 Pull up resistor option register B2 PM Port mode register RD Port 2 read signal WR Port 2 write signal 66 User s Manual U14801EJ3V1UD CHAPTER 4 PORT FUNCTIONS Figure 4 5 Block Diagram of P21 WRrus2 Von Internal bus PUB2 PM RD WR P ch Selector i P21 TxD20 Pull up resistor option register B2 Port mode register Port 2 read signal Port 2 write signal Alternate function User s Manual U14801EJ3V1UD 5020 67 CHAPTER 4 PORT FUNCTIONS Figure 4 6 Block Diagram of P22 to P26 Von o IECH Alternate function Internal bus Output latch P22 to P26 PM22 to PM26 P22 RxD20 SI20 P23 SS20 P24 INTPO P25 INTP1 P26 INTP2 CPT90 PUB2 Pull up resistor option register B2 PM Port mode register RD Port 2 read signal WR Port 2 write signal 68 User s Manual U14801EJ3V1UD CHAPTER 4 PORT FUNCTIONS Figure 4 7 Block Diagram
126. gnal may be output to the device causing a malfunction To prevent such malfunction isolate the connection with other device or set so that the input signal to the device is ignored Figure 13 6 Malfunction of Another Device uPD78F9076 Connection pin of dedicated flash programmer Pin O Other device If the signal output by the uPD78F9076 affects another device in the flash memory programming mode isolate the signal on the device side uPD78F9076 Connection pin of dedicated flash programmer Pin O Other device If the signal output by the dedicated flash programmer affects another device isolate the signal on the device side 180 User s Manual U14801EJ3V1UD CHAPTER 13 PD78F9076 lt RESET pin gt When the reset signal of the dedicated flash programmer is connected to the RESET signal connected to the reset signal generator on the board a signal conflict occurs To prevent this signal conflict isolate the connection with the reset signal generator If a reset signal is input from the user system in the flash memory programming mode a normal programming operation will not be performed Do not input signals other than reset signals from the dedicated flash programmer during this period Figure 13 7 Signal Conflict RESET Pin HPD78F9076 Connection pin of dedicated L Signal conflict flash writer RESET O Reset signal generator In the flash memory programming mode the si
127. gnal output by the reset signal generator and the signal output by the dedicated flash writer conflict therefore isolate the signal on the reset signal generator side lt Port pins gt Shifting to the flash memory programming mode sets all the pins except those used for flash memory programming communication to the status immediately after reset Therefore if the external device does not acknowledge an initial status such as the output high impedance status connect the external device to Vpp or Vss via a resistor lt Oscillation pins When using an on board clock connection of X1 and X2 must conform to the methods in the normal operation mode When using the clock output of the flash programmer directly connect it to the X1 pin with the on board oscillator disconnected and leave the X2 pin open Power supply To use the power output of the flash programmer connect the Von and Vss pins to Voo and GND of the flash programmer respectively To use the on board power supply connection must conform to that in the normal operation mode However because the voltage is monitored by the flash programmer therefore Voo of the flash programmer must be connected User s Manual U14801EJ3V1UD 181 CHAPTER 13 4PD78F9076 13 1 4 Connection of adapter for flash writing The following figures show examples of the recommended connection when the adapter for flash writing is used Figure 13 8 Wiring Example for Flash Writing Adapter Us
128. h tra tni Voo 2 7 to 5 5 V low level width Voo 1 8 to 5 5 V Interrupt input high tint tint INTPO to INTP2 1 low level width RESET input tast 10 AS low level width CPT90 input high tceu toer 10 us low level width Tcv vs Von Guaranteed operation range Cycle time Tcv us 1 2 3 4 5 6 Supply voltage Von V 202 User s Manual U14801EJ3V1UD CHAPTER 15 ELECTRICAL SPECIFICATIONS EXPANDED SPECIFICATION PRODUCTS 2 Serial interface Ta 40 to 85 C Vopn 1 8 to 5 5 V a 3 wire serial UO mode SCK20 Internal clock SCK20 cycle time tkcvi Von 2 7 to 5 5 V so m SCK20 high low tk fe Voo 2 7 to 5 5 V ton 2 50 ns Delay time from 1 kQ Von 271055V 2 7to5 5V Note SCK20 J to DN Vo 1 8 to 5 5 V 1 000 SO20 output Note Rand C are the load resistance and load capacitance of the SO20 output line b 3 wire serial UO mode SCK20 External clock SCK20 cycle time tkove Vo 2 7 to 5 5 V Voo 1 8 to 5 5 V SCK20 high low tkH2 bz Von 2 7 to 5 5 V level width Voo 1 8 to 5 5 V SCK20 I to C 100 pP SO20 output when using SS20 Von 1 8 to 5 5 V 400 ns to SS20 I e ee Ge i T P m S EC A from SS207 Note R and C are the load resistance and load capacitance of the SO20 output line Voo 1 8 to 5 5 V 1000 User s Manual U14801E
129. h interrupt request in advance see Table 10 1 162 User s Manual U14801EJ3V1UD CHAPTER 10 INTERRUPT FUNCTIONS Figure 10 12 Example of Multiple Interrupts Example 1 A multiple interrupt is acknowledged Main processing INTxx servicing INTyy servicing INTxx INTyy RETI RETI During interrupt INTxx servicing interrupt request INTyy is acknowledged and multiple interrupts are generated The El instruction is issued before each interrupt request acknowledgement and the interrupt request acknowledgment enable state is set Example 2 Multiple interrupts are not generated because interrupts are not enabled Main processing INTxx servicing INTyy servicing IE 0 INTyy INTyy is held pending RETI INTxx IE 0 RETI Because interrupts are not enabled in interrupt INTxx servicing the El instruction is not issued interrupt request INTyy is not acknowledged and multiple interrupts are not generated The INTyy request is reserved and acknowledged after the INTxx servicing is performed IE 0 Interrupt request acknowledgment disabled User s Manual U14801EJ3V1UD 163 CHAPTER 10 INTERRUPT FUNCTIONS 10 4 4 Interrupt request hold Some instructions may hold the acknowledgment of an instruction request pending until the completion of the execution of the next instruction even if the interrupt request maskable interrupt non maskable interrupt and external interrupt is generated during t
130. he Integrated debugger 78K 0S Series The ID78KOS NS is Windows based software It has improved C compatible debugging functions and can display the results of tracing with the source program using an integrating window function that associates the source program disassemble display and memory display with the trace result Used in combination with a device file DF789076 sold separately Part number SxxxxID78KOS NS SM78K0S This is a system simulator for the 78K 0S Series The SM78KOS is Windows based software System simulator It can be used to debug the target system at C source level of assembler level while simulating the operation of the target system on the host machine Using SM78KOS the logic and performance of the application can be verified independently of hardware development Therefore the development efficiency can be enhanced and the software quality can be improved Used in combination with a device file DF789076 sold separately Part number 4SxxxxSM78K0S DF789076 File containing the information inherent to the device Device file Used in combination with other tools RA78K0S CC78KO0S ID78KOS NS SM78K0S all sold separately Part number SxxxxDF789076 Note DF789076 is a common file that can be used with RA78KOS CC78KO0S ID78KOS NS and SM78K0S Remark xxxx in the part number differs depending on the operating system used and the supply medium HASxxxxID78K0S NS HSxxxxSM78K0S AB13 PC 9800
131. he execution The following shows such instructions interrupt request hold instructions e Manipulation instruction for interrupt request flag registers O and 1 IFO and IF1 e Manipulation instruction for interrupt mask flag registers 0 and 1 MKO and MK1 164 User s Manual U14801EJ3V1UD CHAPTER 11 STANDBY FUNCTION 11 1 Standby Function and Configuration 11 1 1 Standby function The standby function is used to reduce the power consumption of the system and can be effected in the following two modes 1 2 HALT mode This mode is set when the HALT instruction is executed HALT mode stops the operation clock of the CPU The system clock oscillator continues oscillating This mode does not reduce the power consumption as much as STOP mode but is useful for resuming processing immediately when an interrupt request is generated or for intermittent operations STOP mode This mode is set when the STOP instruction is executed The STOP mode stops the main system clock oscillator and stops the entire system The power consumption of the CPU can be substantially reduced in this mode The low voltage Vpp 1 8 V max of the data memory can be retained Therefore this mode is useful for retaining the contents of the data memory at an extremely low power consumption STOP mode can be released by an interrupt request so that this mode can be used for intermittent operation However some time is required until the system clock oscillat
132. ice PRECAUTION AGAINST ESD A strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it when it has occurred Environmental control must be adequate When it is dry a humidifier should be used It is recommended to avoid using insulators that easily build up static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with mounted semiconductor devices STATUS BEFORE INITIALIZATION Power on does not necessarily define the initial status of a MOS device Immediately after the power source is turned ON devices with reset functions have not yet been initialized Hence power on does not guarantee output pin levels UO settings or contents of registers A device is not initialized until the reset signal is received A reset operation must be executed immediately after power on for devices with reset functions POWER ON OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface
133. ifferences Between Expanded Specification Products and Conventional Products Power Supply Voltage Von Guaranteed Operating Speed Operating Frequency Conventional Products Expanded Specification Products 4 5to 5 5 V 5 MHz 0 4 us 10 MHz 0 2 us 3 0 to 5 5 V 5 MHz 0 4 us 6 MHz 0 33 us 2 7 to 5 5 V 5 MHz 0 4 us 5 MHz 0 4 us 1 8to 5 5 V 1 25 MHz 1 6 us 1 25 MHz 1 6 us Remark The parenthesized values indicate the minimum instruction execution time 20 User s Manual U14801EJ3V1UD CHAPTER 1 GENERAL 1 2 Features ROM and RAM capacity Program Memory Data Memory Product Name Internal High Speed RAM LT 789072 A Lom ak uPD789074 789074 789074 A 8k KB k Minimum instruction execution time can be changed from high speed 0 2 us to low speed 0 8 us at 10 0 MHz Voo 4 5 to 5 5 V operation with system clock e O ports 24 Serial interface 1 channel 3 wire serial l O mode UART mode 1 channel Timer 3 channels 16 bit timer 1 channel 8 bit timer event counter 1 channel Watchdog timer 1 channel Vectored interrupt sources 9 e Supply voltage Vpp 1 8 to 5 5 V e Operating ambient temperature Ta 40 to 85 C 1 3 Applications Small general home electrical appliances telephones etc 1 4 Ordering Information Part Number Package Quality Grade uPD789071MC xxx 5A4 30 pin plastic SSOP 7 62 mm 300 Mask ROM uPD789072MC xxx 5A4 30 pin plastic SSOP 7 62 mm 300 Mask ROM U
134. illating At this time the oscillation stabilization time 2 fx is automatically secured After that the CPU starts instruction execution at the slow speed of the system clock 0 8 ws 10 0 MHz operation 1 6 us 5 0 MHz operation 2 After the time required for the Vpp voltage to rise to the level at which the CPU can operate at the high speed has elapsed the processor clock control register PCC is rewritten so that the high speed operation can be selected User s Manual U14801EJ3V1UD 81 CHAPTER 6 16 BIT TIMER 90 6 1 Functions of 16 Bit Timer 90 16 bit timer 90 has the following functions e Timer interrupt e Timer output e Buzzer output e Count value capture 1 Timer interrupt An interrupt is generated when the count value and compare value match 2 Timer output Timer output can be controlled when the count value and compare value match 3 Buzzer output Buzzer output can be controlled by software 4 Count value capture The count value of 16 bit timer counter 90 TM90 is latched into a capture register in synchronization with the capture trigger and retained 6 2 Configuration of 16 Bit Timer 90 16 bit timer 90 includes the following hardware Table 6 1 Configuration of 16 Bit Timer 90 Registers Compare register 16 bits x 1 CR90 Capture register 16 bits x 1 TCP90 Timer Timer outputs 1 TO90 Control registers 16 bit timer mode control register 90 TMC90 Buzzer output control register
135. iming are satisfied when the flash memory is written e When supply voltage rises Vpp must exceed Vo 10 ws or more after Voo has reached the lower limit value 1 8 V of the operating voltage range see a in the figure below e When supply voltage drops Von must be lowered 10 ws or more after Ver falls below the lower limit value 1 8 V of the operating voltage range of Voo see b in the figure below Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of port pins User s Manual U14801EJ3V1UD 195 CHAPTER 15 ELECTRICAL SPECIFICATIONS EXPANDED SPECIFICATION PRODUCTS System Clock Oscillator Characteristics TA 40 to 85 C Voo 1 8 to 5 5 V Resonator Recommended Circuit Parameter Conditions Ceramic Oscillation frequency Von 4 5 to 5 5 V 1 0 10 0 MHz resonator MT Von 3 0 to 5 5 V 1 0 6 0 MHz Vop 1 8 to 5 5 V 1 0 5 0 MHz Oscillation stabilization After Voo reaches oscillation 4 ms time voltage range MIN Crystal Oscillation frequency Voo 4 5 to 5 5
136. imum rating is exceeded even momentarily for any parameter That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of port pins User s Manual U14801EJ3V1UD 209 CHAPTER 16 ELECTRICAL SPECIFICATIONS CONVENTIONAL PRODUCTS System Clock Oscillator Characteristics TA 40 to 85 C Voo 1 8 to 5 5 V Ceramic resonator Crystal resonator External clock Notes 1 2 Caution 210 Oscillation frequency Voo oscillation voltage fir range Oscillation stabilization After Voo reaches oscillation Note 2 time voltage range MIN Oscillation frequency fx Oscillation stabilization Voo 4 5 to 5 5 V H Note 2 une Von 1 8 to 5 5 V X1 input frequency fx XA input high low level width an txt X1 input frequency fx Von 2 7 to 5 5 V X1 input high low level width Voo 2 7 to 5 5 V an txt Indicates only oscillator characteristics Refer to AC Characteristics for instruction execution time Time required to stabilize oscillation after reset or STOP mode release Use the resonator that stabilizes oscillation within the oscillation wait time When using the system clock oscillator wire a
137. ing 3 Wire Serial I O VDD 2 7 to 5 5 V O GND e 2 3 4 5 6 7 8 9 4 u PD78F9076 GND VDD VDD2 LVDD FRASHWRITER INTERFACE 182 User s Manual U14801EJ3V1UD Figure 13 9 Wiring Example for Flash Writing Adapter Using UART VDD 2 7 to 5 5 V mO GND 2 3 4 5 6 7 Ko KR O4 8 8 LL 9 Ro S 10 Ge 11 12 13 14 15 GND VDD VDD2 LVDD FRASHWRITER INTERFACE SI O SO SCK CLKOUT RESET VPP RESERVE HS o oO O O O O User s Manual U14801EJ3V1UD CHAPTER 13 PD78F9076 183 CHAPTER 13 4PD78F9076 Figure 13 10 Wiring Example for Flash Writing Adapter Using Pseudo 3 Wire VDD 2 7 to 5 5 V LO GND 2 3 4 5 6 O7 o N o 8 E PE 9 R a 10 E 11 12 13 14 15 GND VDD VDD2 LVDD FRASHWRITER SI SO SCK CLKOUT RESET VPP RESERVE HS INTERFACE O O O O O O O 184 User s Manual U14801EJ3V1UD CHAPTER 14 INSTRUCTION SET OVERVIEW This chapter lists the instruction set of the uPD789074 Subseries For details of the operation and machine language instruction code of each instruction refer to 78K 0S Series Instructions User s Manual U11047E
138. ion instruction RESET input clears WDTM to 00H Figure 8 3 Format of Watchdog Timer Mode Register Symbol 7 6 Address After reset R W 5 4 3 2 1 0 RUN Watchdog timer operation selectionNote 1 ha Stop counting Na Clear counter and start counting RUN 1 WDTM4 WDTM3 Watchdog timer operation mode selectionNote 2 Ke Interval timer mode a maskable interrupt is generated upon overflow occurrence Nete 3 NN Watchdog timer mode 1 a non maskable interrupt is generated upon overflow occurrence Watchdog timer mode 2 a reset operation is started upon overflow occurrence Notes 1 Once RUN has been set to 1 it cannot be cleared to O by software Therefore when counting is started it cannot be stopped by any means other than RESET input 2 Once WDTM3 and WDTMA have been set to 1 they cannot be cleared to O by software 3 The watchdog timer starts operation as an interval timer when RUN is set to 1 Cautions 1 When the watchdog timer is cleared by setting RUN to 1 the actual overflow time is up to 0 8 shorter than the time set by the watchdog timer clock selection register WDCS 2 To set watchdog timer mode 1 or 2 set WDTMA to 1 after confirming WDTIF bit O of interrupt request flag register 0 IFO is set to 0 When watchdog timer mode 1 or 2 is selected with WDTIF set to 1 a non maskable interrupt is generated upon the completion of rewriting WDTM 112 User s Manual U14801EJ3V1UD CHAPTER 8 WATCHDOG
139. ister Name Index Alphabetic Order rrsmrnnnnnvnnnnvennnnvnnnnnnnnnvvnnnnvnnnnnnnnnnnnnnnvennnnnnnnnnnnnnnennn C 2 Register Symbol Index Alphabetic Order essere APPENDIX D REVISION HISTORY omic 14 User s Manual U14801EJ3V1UD LIST OF FIGURES 1 3 Figure No Title Page 2 1 Pin I O Circuits iia a 36 3 1 Memory Map UPD789071 nissens tese ar tr Ao ed oe 37 3 2 MEMONY MAp UPDIOIOM Tc ERA UR DRM NU EGRE BA 38 3 3 Memory Map uPD789074 agent aa are 39 3 4 Memory Map OPD Zoo Ze 40 3 5 Data Memory Addressing oP G0o0 71 42 3 6 Data Memory Addressing oP 700 72 43 3 7 Data Memory Addressing oP 70074 44 3 8 Data Memory Addressing oP ZGEOO 6 45 3 9 Program Counter Configuration a e aaa a E aE a E a raa ae Ra a a aAa ra a aa na nnne nnns 46 3 10 Program Status Word Configuration nennen nennen neret nennt nnne enne nennen 46 3 11 Stack Pointer Configuration AE 48 3 12 Data to Be Saved to Stack Memory sssssssssssssseseseeee enne enne nere nenne nennen nnne t reset nnne nnne nnns 48 3 13 Data to Be Restored from Stack Memory ssssssssssseseeeeeeeneeneen nennen nennen nennt nennt nennt nennen nns 48 3 14 General Purpose Register Configuration nennen nennen nennen nennt nnne nnns 49 4 1 SB M 62 4 2 Block Diagram of POO to POT uio aee e LO E OU GI EIE GEM 64 4 3
140. it the 3 bit counter is initialized and starts counting and data sampling is performed When character data a parity bit and one stop bit are detected after the start bit reception of one frame of data ends When one frame of data has been received the receive data in the shift register is transferred to receive buffer register 20 RXB20 and a reception completion interrupt INTSR20 is generated If an error occurs the receive data in which the error occurred is still transferred to RXB20 and INTSR20 is generated If the RXE20 bit is reset to O during the receive operation the receive operation is stopped immediately In this case the contents of RXB20 and asynchronous serial interface status register 20 ASIS20 are not changed and INTSR20 is not generated Figure 9 9 Asynchronous Serial Interface Reception Completion Interrupt Timing START INTSR20 Caution Be sure to read receive buffer register 20 RXB20 even if a receive error occurs If RXB20 is not read an overrun error will occur when the next data is received and the receive error state will continue indefinitely User s Manual U14801EJ3V1UD CHAPTER 9 SERIAL INTERFACE 20 e Receive errors The following three errors may occur during a receive operation a parity error a framing error and an overrun error After data reception an error flag is set in asynchronous serial interface status register 20 ASIS20 Receive error causes are shown in Table 9 7 It is p
141. k ome 9 v COSTOS vea we v Input voltage low Vit POO to PO7 P10 to P15 ER pame y Me tawssv o orme v Ed wasasessv o 94 v wesuwssv 9 9 v SL Von 4 5 to 5 5 V los 1 mA Vo 10 high Von 1 8 to 5 5 V lou 100 yA PT Output voltage low Voo 4 5 to 5 5 V lo 10 mA uPD78907x 78F9076 Von 4 510 5 5 V lo 3 mA uPD78907x A 4 5 to 5 5 V lo 2 3 mA Von 4 510 5 5 V lo 3 mA uPD78907x A Voo 1 Voo 1 8t0 5 5 V lo 400 KA Voo 1 8t0 5 5 V lo 400 KA Input leakage liit Vin VoD SC other than X1 current high Input leakage EN Vn 0V a5 other than X1 current low Output leakage Vout VoD A current high Output leakage Jo Vour 0V 3 HA current low Software pull up Ri Vn 0V 50 100 200 KQ resistor Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of port pins LIEU 200 User s Manual U14801EJ3V1UD CHAPTER 15 ELECTRICAL SPECIFICATIONS EXPANDED SPECIFICATION PRODUCTS DC Characteristics Ta 40 to 85 C Von 1 8 to 5 5 V Power supply 10 0 MHz crystal Voo 5 0 V 1090 current oscillation operating mode Note 2 mask ROM 6 0 MHz crystal oscillation Von 5 0 V 10 version operating mode C1 C2 22 pF 10 0 MHz crystal Voo 5 0 V 1099 1 0 2 0 oscillation HALT mode 6 0 MHz crystal oscillation Von 5 0 V 21095 HALT mode 5 0 MHz cry
142. k oscillation o Tee Eine RET Let L ns wa gt ws reste spp vote dT S vs ro patear O le memaycomecsd Conectarse a Vep This pin is used to set the flash memory programming mode and applies a high voltage when a program is written or verified User s Manual U14801EJ3V1UD 31 CHAPTER 2 PIN FUNCTIONS 2 2 Description of Pin Functions 2 2 1 P0O0 to P07 Port 0 These pins constitute an 8 bit I O port and can be set to input or output port mode in 1 bit units by using port mode register 0 PMO When these pins are used as an input port an on chip pull up resistor can be used by setting pull up resistor option register O PUO 2 2 2 P10to P15 Port 1 These pins constitute a 6 bit UO port and can be set to input or output port mode in 1 bit units by using port mode register 1 PM1 When these pins are used as an input port an on chip pull up resistor can be used by setting pull up resistor option register O PUO 2 2 3 P20 to P27 Port 2 These pins constitute an 8 bit I O port In addition these pins provide a function to perform input output to from the timer to input output the data and clock of the serial interface and to input the external interrupt Port 2 can be set to the following operation modes in 1 bit units 1 Port mode In port mode P20 to P27 function as an 8 bit I O port Port 2 can be set to input or output mode in 1 bit units by using port mode register 2 PM2 For P20 to P27 wheth
143. lock control register DC Pull up resistor option register O PUO nennen nennen nennt entrent rese nne n nnne nennen Pull up resistor option register B2 PUB enne nnne nennen nnne entrent nnne R Receive buffer register 20 PHNP 1 User s Manual U14801EJ3V1UD 233 APPENDIX C REGISTER INDEX S Serial operation mode register 20 CSIM20 rrnnnvrnenvrnnnvnnenvrnnnvnnenvrnnnvnnenrenenvnnenrnnenvnnenrenennnnenressnrnnenresevesenresenn 119 T Transmission shift register 20 TXS20 rrnrnnanvnnnnrnnenvnnnnrnnnnrnnnvrnnnnnnrnvrnsnvnnevresnnnnenvanennnnenrnnennnennrasennnssnressnnnsenseen 118 W Watchdog timer clock selection register ONDCE conc cc nrr crac 111 Watchdog timer mode register WDTM sssssssessseeeeeeeeennenenennnneenn enne nennen nennen neret rennen enne et nnns 112 234 User s Manual U14801EJ3V1UD APPENDIX C REGISTER INDEX C 2 Register Symbol Index Alphabetic Order A ASIM20 ASIS20 B BRGC20 BZC90 C CR80 CR90 CSIM20 1 IFO 1F1 INTMO M MKO MK1 0 OSTS P PO P1 P2 P3 PCC PMO PM1 PM2 PM3 PUO PUB2 R RXB20 T TCP90 TM80 TM90 TMC80 Asynchronous serial interface mode register 20 120 Asynchronous serial interface status register 20 122 Baud rate generator control register 20 123 Buzzer output control register 90 rrrnnvnnrnnnvnrnnvnvnvnrnnnvnnnnnvnnennnnvnvnsnnnnenvnnrnnnn
144. lt 1 gt lt 2 gt lt 3 gt lt 4 gt lt 5 gt Disable interrupts TMMK90 1 and disable inversion control of timer output TOC90 0 Rewrite the higher byte of CR90 16 bits first Next rewrite the lower byte of CR90 16 bits Clear the interrupt request flag TMIF90 After more than half the cycle of the count clock has passed from the start of the interrupt enable timer interrupts and timer output inversion lt Program example A gt When count clock 64 fx CPU clock fx TM90 VCT SETI TMMK90 Timer interrupt disable 6 clocks CLR1 TMC90 3 Timer output inversion disable 6 clocks MOV A xxH Higher byte rewrite value setting 6 clocks MOV OFF17H A CR90 higher byte rewriting 8 clocks More than 32 clocks in MOV A yyH Lower byte rewrite value setting 6 clocks total MOV OFF16H A CR90 lower byte rewriting 8 clocks CLR1 TMIF90O Interrupt request flag clearing 6 clocks CLR1 TMMK90 Timer interrupt enable 6 clocks SETT TMC90 3 Timer output inversion enable Note This is because the INTTM90 signal is set to the high level for a period of half the cycle of the count clock after an interrupt is generated so the output will be inverted if TOC90 is set to 1 during this period User s Manual U14801EJ3V1UD 95 96 CHAPTER 6 16 BIT TIMER 90 lt Prevention method B gt Rewriting by 16 bit access lt 1 gt lt 2 gt lt 3 gt lt 4 gt lt 5 gt Disable interrupts TMMK90 1
145. luded CCE A CC on 2 High speed mode operation when processor clock control register PCC is set to 00H 3 Low speed mode operation when PCC is set to 02H Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of port pins 214 User s Manual U14801EJ3V1UD CHAPTER 16 ELECTRICAL SPECIFICATIONS CONVENTIONAL PRODUCTS AC Characteristics 1 Basic operation Ta 40 to 85 C Voo 1 8 to 5 5 V TI80 input fr Vo 2 7t056V 2 7t05 5V frequency execution time Voo 1 8 to 5 5 V EM TI80 input high tnx bn Voo 2 7 to EC A 5V low level width Voo 1 81085W 00000000 181055V Interrupt input high tint tint INTPO to INTP2 10 low level width RESET input tRsL AS low level width CPT90 input high cen font 10 us low level width Tcv vs Voo Guaranteed operation range Cycle time Tcv us Supply voltage Von V User s Manual U14801EJ3V1UD 215 CHAPTER 16 ELECTRICAL SPECIFICATIONS CONVENTIONAL PRODUCTS 2 Serial interface Ta 40 to 85 C Vpp 1 8 to 5 5 V a 3 wire serial UO mode SCK20 Internal clock SCK20 cycle time tkov1 Von 2 7 to 5 5 V so m SCK20 high low bm tki Voo 2 7 to 5 5 V ewa so r Delay time from 1 kQ Voo 2 71055V 2 7to5 5V Note SCK20 J to 010 pr Vo 1 8 to 5 5 V 1
146. m 300 Remarks 1 xxx indicates ROM code suffix 2 Products that have the part numbers suffixed by A are lead free products Standard Standard Standard Standard Special Special Special Standard Standard Standard Standard Please refer to Quality Grades on NEC Semiconductor Devices Document No C11531E published by NEC Electronics Corporation to know the specification of the quality grade on the device and recommended applications 22 User s Manual U14801EJ3V1UD its CHAPTER 1 GENERAL 1 6 Pin Configuration Top View 30 pin plastic SSOP 7 62 mm 300 P22 SI20 RxD20 o P100 1 o P11 P31 BZO900 2 29 o P12 IC Ver O 3 O P13 RESET o 4 27 o P14 X20 5 26 0 P15 X10 6 o POO Vss O 7 24 0 P01 Von O 8 O P02 P30 TO90 O 9 P03 P27 T180 T080 O 1 O P04 P26 INTP2 CPT90 0o o POS P25 INTP1 O 19 o0 P06 P24 INTPO O o P07 P23 SS20 0 Caution Connect the IC Internally Connected pin directly to Vss 16 0 P21 SO20 TxD20 Remark Pin connections in parentheses are intended for the uPD78F9076 ASCK20 Asynchronous serial input SCK20 BZO90 Buzzer output SI20 CPT90 Capture trigger input SO20 IC Internally connected SS20 INTPO to INTP2 External interrupt input TI80 POO to P07 Port 0 TO80 TO90 P10 to P15 Port 1 TxD20 P20 to P27 Port 2 Von P30 P31 Port 3 Ver RESET Reset Vss RxD20 Receive data X1 X2 User s Manual U14801EJ3V1UD
147. n Mode 3 wire serial VO Table 13 2 Communication Mode List TYPE Setting Pins Used Number of Ver Pulses COMM PORT SIO Clock CPU Clock Multiple Rate In Flashpro On Target Board SIO ch 0 3 wire sync 100 Hz to 1 25 MHz 11245 1 to 5 MHz MHz 2 SI20 RxD20 P22 SO20 TxD20 P21 SCK20 ASCK20 P20 UART UART ch 0 Async 4 800 to 5 MHz 76 800 bps Notes 2 4 4 91 or 5 MHz RxD20 SI20 P22 TxD20 SO20 P21 Pseudo 3 wire Notes 1 PortA Pseudo 3 wire 100 Hz to 1 kHz 1 2 4 5 1 to 5 MHz MHz DO P02 POO Selection items for TYPE settings on the dedicated flash programmer Flashpro Ill part no FL PR3 PG FP3 Flashpro IV part no FL PR4 PG FP4 2 The possible setting range differs depending on the voltage For details refer to CHAPTER 15 ELECTRICAL SPECIFICATIONS EXPANDED SPECIFICATION PRODUCTS and CHAPTER 16 ELECTRICAL SPECIFICATIONS CONVENTIONAL PRODUCTS 3 2 or 4 MHz only for Flashpro III 4 Because signal wave slew also affects UART communication in addition to the baud rate error thoroughly evaluate the slew 5 Only for Flashpro IV However when using Flashpro III be sure to select the clock of the resonator on the board UART cannot be used with the clock supplied by Flashpro Ill Figure 13 2 Communication Mode Selection Format 10V Ver Von e ae 1 2 n Vss 7 Vrr pulses Von BR RESET Vss 176
148. n names X A C B E D L H AX BC DE and HL Description example MOV A C When selecting the C register for r Instruction code 0 0 0 0 1 0 1 0 Register specify code INCW DE When selecting the DE register pair for rp Instruction code 1 0 0 0 1 0 0 0 Register specify code User s Manual U14801EJ3V1UD 59 CHAPTER 3 CPU ARCHITECTURE 3 4 5 Register indirect addressing Function The memory is addressed with the contents of the register pair specified as an operand The register pair to be accessed is specified with the register pair specify code in the instruction code This addressing can be carried out for all the memory spaces Operand format lo fom IO Description example MOV A DE When selecting register pair DE Instruction code 0 0 1 0 1 0 1 1 Illustration Memory address specified by register pair DE The contents of addressed memory are transferred 7 0 60 User s Manual U14801EJ3V1UD CHAPTER 3 CPU ARCHITECTURE 3 4 6 Based addressing Function 8 bit immediate data is added to the contents of the base register that is the HL register pair and the sum is used to address the memory Addition is performed by expanding the offset data as a positive number to 16 bits A carry from the 16th bitis ignored This addressing can be carried out for all the memory spaces Operand format Description example MOV A HL 10H When setting byte to 10H
149. nch Milton Keynes UK Tel 01908 691 133 J05 6 Users Manual U14801EJ3V1UD MAJOR REVISIONS IN THIS EDITION Page Description U14801EJ2V0UDOO U14801EJ3VOUDOO Throughout e Addition of uPD789071 A 789072 A and 789074 A e Addition of description of expanded specification products pp 20 22 29 CHAPTER 1 GENERAL e Addition of 1 1 Expanded Specification Products and Conventional Products e Addition of 1 5 Quality Grades e Addition of 1 10 Differences Between Standard Quality Grade Products and A Products pp 89 90 91 95 CHAPTER 6 16 BIT TIMER 90 e Modification of description of 6 4 1 Operation as timer interrupt e Modification of Figure 6 6 Timing of Timer Interrupt Operation e Modification of description of 6 4 2 Operation as timer output e Modification of Figure 6 8 Timer Output Timing e Addition of 6 5 Notes on Using 16 Bit Timer 90 CHAPTER 7 8 BIT TIMER EVENT COUNTER 80 e Addition of 7 5 3 Timer operation after compare register is rewritten during PWM output e Addition of 7 5 4 Cautions when STOP mode is set e Addition of 7 5 5 Start timing of external event counter CHAPTER 13 4 PD78F9076 e Total revision of description of flash memory programming Addition of CHAPTER 15 ELECTRICAL SPECIFICATIONS EXPANDED SPECIFICATION PRODUCTS CHAPTER 16 ELECTRICAL SPECIFICATIONS CONVENTIONAL PRODUCTS e Modification of table of recommended oscillator constant CHAPTER 18 RECOMMENDED S
150. nnection Example uPD78F9076 Connection pin of dedicated flash programmer Ver O Pull down resistor RVrp Serial interface pins The following shows the pins used by each serial interface Serial Interface Pins Used 3 wire serial UO SI20 SO20 SCK20 UART RxD20 TxD20 Pseudo 3 wire POO P01 PO2 Note that signal conflict or malfunction of other devices may occur when an on board serial interface pin that is connected to another device is connected to the dedicated flash programmer User s Manual U14801EJ3V1UD 179 CHAPTER 13 PD78F9076 1 Signal conflict A signal conflict occurs if the dedicated flash programmer output is connected to a serial interface pin input connected to another device output To prevent this signal conflict isolate the connection with the other device or put the other device in the output high impedance status Figure 13 5 Signal Conflict Serial Interface Input Pin HPD78F9076 Connection pin of dedicated flash Signal conflict programmer Input pin rs t O Other device d Output pin In the flash memory programming mode the signal output by another device and the signal sent by the dedicated flash programmer conflict To prevent this isolate the signal on the device side 2 Malfunction of another device When the dedicated flash programmer output or input is connected to a serial interface pin input or output connected to another device input a si
151. nnnnenenennnn 82 6 2 Configuration of 16 Bit Timer 90 rrrsvrnnnvvnnnnnvnnnnnvnnnvnnnnnvnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnner 82 6 3 Control Registers of 16 Bit Timer 90 rrrrrnnnnvnnnnnvnnnvnnnnnvnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnnnennnnnnnnnnnnnnner 85 6 4 Operation of 16 Bit Timer 90 rrnsvnnnnvvnnnnvnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnner 89 6 4 1 Operation as timer interrupt nennen nennen nente nnn entr trennen nnns 89 6 4 2 Operation as timer output siet incerti tr td e ec o a denn aS 91 User s Manual U14801EJ3V1UD 11 6 4 3 le ln DEE 92 6 4 4 16 bit timer counter 90 readout r vrerrrnvvnrnnnrnnnnnnnvnvnrnnvnenvnnrennnvnnnnenrnnnnenvnnrnnnnvnnnntnrnnnnenennrennennn 93 6 4 5 Buzzer output operation icce e e aa a ra ere o Eaa Eee ea 94 6 5 Notes on Using 16 Bit Timer 90 rrrssrennnnnnnvennnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnennnnnnnnnnnnnnnnnnnnnnnnnr 95 6 5 1 Restrictions on rewriting16 bit compare register 90 95 CHAPTER 7 8 BIT TIMER EVENT COUNTER 680 eese eeeee nene nennen nnn nnn nn nnn nnn 97 7 1 Functions of 8 Bit Timer Event Counter 80 rrnrsvvnnnavnnnnnvnnnnvnnnnvnnnnnvnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnvennn 97 7 2 Configuration of 8 Bit Timer Event Counter 80 rrrsavrnnnnvnnnnvnnnnvnnnnnvnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnvnnnn 98 7 3 8 Bit Timer Event Counter 80 Control Registers seen 99
152. nnnnner 115 9 1 Functions of Serial Interface 20 rrrrsvrnnnvnnnnnnvnnnnvnnnnvnnnnnvnnnnnnnnnvnnnnnvnnnnnnnnnnnnnnnvennnnnnnnnnnnnnnenn 115 9 2 Configuration of Serial Interface 20 rrrnvvrnnnnvnnnnnnnnnvvnnnnvnnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnvennnnnnnnnnnnnnnenn 115 9 3 Control Registers of Serial Interface 20 rrrnnrnnnnnrnnnvvnnnnvnnnnnnnnnnvnnnnnvnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnenn 119 9 4 Operation of Serial Interface 20 srrnrnvrnnnnvnnnnnvnnnnvnnnnvnnnnnnnnnnnnnnnnvnnnnvnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnenn 126 9 4 1 Operation Stop mode ud iH EE 126 9 4 2 Asynchronous serial interface UART mode 127 9 4 3 3 Wire serial MO ul 3 11 eau p id qe qii 140 CHAPTER 10 INTERRUPT FUNCTIONS i ernnnnnnvevnennnnvvenennnnvnnnennnnnnennnnnnnennnnneennnnnnnennnnnnnennnnnnnennnnnnnenr 150 10 1 Interrupt Function Types esses eene nennen nennen nnnm re 150 10 2 Interrupt Sources and Configuration rrasavnnnnvnnnnvnnnnnvnnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnn 150 10 3 Interrupt Function Control RegistersS rrrssvrnnnvrnnnvnnnnnnvnnnnnnnnnvnnnnnvnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnn 153 10 4 Interrupt Processing OperatiOn rsssrnnnnvnnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 158 10 4 1 Non maskable interrupt request acknowledgment operation eene 158 10 4 2 Maskable interrupt request acknowledgment operaiton no 160 10 4 3
153. nnnnnnvneenvnnnnnvnnenenennvnvenennnnnevnrnenennn 112 User s Manual U14801EJ3V1UD APPENDIX D REVISION HISTORY The following shows the revision history Chapter refers to the chapters in the respective edition Edition 2nd edition Description Change of uPD789071 789072 789074 and 78F9076 from under development to development complete 1 2 Throughout Modification of description of VPP pin connection CHAPTER 2 PIN FUNCTION Modification of Caution on rewriting CR90 in 6 4 1 Operation as timer interrupt CHAPTER 6 16 BIT TIMER 90 Addition of description on reading receive data of UART CHAPTER 9 SERIAL INTERFACE 20 Addition of Note on unused pins in Table 13 2 Communication Mode Addition of Note and Remark to Figures 13 2 Flashpro Ill Connection Example in 3 Wire Serial UO Mode 13 3 Flashpro Ill Connection Example in UART Mode and 13 4 Flashpro Ill Connection Example in Pseudo 3 Wire Mode Modification of value of UART in Table 13 4 Setting Example with PG FP3 Addition of 13 1 5 On board pin connections CHAPTER 13 uPD78F9076 Addition of electrical specifications CHAPTER 15 ELECTRICAL SPECIFICATIONS Addition of package drawing CHAPTER 16 PACKAGE DRAWING Addition of recommended soldering conditions CHAPTER 17 RECOMMENDED SOLDERING CONDITIONS Overall modification of description on development tools Deletion of Embedded Software APPENDIX A DEVELO
154. nterrupt Operation 90 6 7 Settings of 16 Bit Timer Mode Control Register 90 for Timer Output Operation 91 6 8 Timer Output Timing i Ere e EU EEUU ie or a dae 91 6 9 Settings of 16 Bit Timer Mode Control Register 90 for Capture Operation 92 6 10 Capture Operation Timing with Both Edges of CPT90 Pin Gpecfledh A 92 6 11 16 Bit Timer Counter 90 Readout Timing ccooocnncccnnnccnncccnonnnnncncnnnncnnnn cnn nono c cnn nano 93 6 12 Settings of Buzzer Output Control Register 90 for Buzzer Output Operation 94 7 1 Block Diagram of 8 Bit Timer Event Counter 80 98 7 2 Format of 8 Bit Timer Mode Control Register 90 99 7 3 Format of Port Mode Register 2 rrnvrnnnnnnvnnnvanvvnnnnnvnnennnnvnvnrnnnnnnnnnvnnenvnnvnensnnnnennnnensnsvnnnnnsnnennnennenrsnnnnnensnnvnenn 100 7 4 Interval Timer Operation Timing ssssseseseeeeeeeeneenneen nennen nennen nenne nnnen nere nren rere tree nennen nennen 102 7 5 External Event Counter Operation Timing with Rising Edge Specified AA 103 16 Square Wave Output Timing tie n e e Pi le RR e D deet 105 LA PAI OU Tips t ttai MAINS ede it 106 7 8 Start Timing of 8 Bit Timer Counter 80 sssssssssssseseeeeeeeneenenee nennen nennen nnne nnne nnne en rre 107 7 9 External Event Counter Operation Timing nennen nnne nnnen nre 107 7 10 Operation Timing After Compare Register Is Rewritten During PWM Output 108 8 1 Block Diagram of Watchdog Time Thin rti cnet tr lt ee cada dris 110 8
155. o 10 high Voo 1 8 to 5 5 V lou 100 wA Output voltage low Voo 4 5 to 5 5 V lo 10 mA uPD78907x 78F9076 Voo 4 5 to 5 5 V lo 3 mA uPD78907x A 4 510 5 5 V lo 3 mA Voo 4 5 to 5 5 V lo 3 mA uPD78907x A Von 1 Voo 1 8t0 BEN lo 400 4A Voo 1 8t0 BEN lo 400 4A Input leakage lut Vin VoD Se other than X1 current high Input leakage EN Vn 0V ee other than X1 current low Output leakage SH Vout Voo LA current high Output leakage Jo Vour 0V 3 uA current low Software pull up Ri Vn 0V 50 100 200 kQ resistor Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of port pins lt lt lt lt lt lt lt lt User s Manual U14801EJ3V1UD 213 CHAPTER 16 ELECTRICAL SPECIFICATIONS CONVENTIONAL PRODUCTS x DC Characteristics Ta 40 to 85 C Voo 1 8 to 5 5 V Power supply 5 0 MHz crystal oscillation Von 5 0 V 10 o 18 26 m Note 1 H mask ROM C1 C2 22 pF 5 0 MHz crystal oscillation Von 5 0 V 10 os 10 m C1 C2 22 pF CET MECA A E M Note 2 Power supply 5 0 MHz crystal oscillation Von 5 0 V 10 Note 1 1 uPD78F9076 C1 C2 22 pF 5 0 MHz crystal oscillation Von 5 0 V 10 ESKE SES C1 C2 22 pF Eee EE pce os 39 fam Notes 1 The port current including the current flowing through the on chip pull up resistors is not inc
156. o its use such as a special function register SFR Figures 3 5 through 3 8 illustrate the data memory addressing Figure 3 5 Data Memory Addressing uPD789071 FFFFH Special function registers SFRs 256 x 8 bits SFR addressing FF20H Bile EUs Vesey es Ure ewe TE a FFOOH FEFFH Internal high speed RAM Short direct addressing 256 x 8 bits FE20H Y FE1FH FEOOH FDFFH Direct addressing Register indirect addressing Based addressing Reserved 0800H 07FFH Internal ROM 2 048 x 8 bits 0000H Y 42 User s Manual U14801EJ3V1UD CHAPTER 3 CPU ARCHITECTURE Figure 3 6 Data Memory Addressing uPD789072 FFFFH Special function registers SFRs 256 x 8 bits SFR addressing AA eh e elle core ee MEER FF1FH i FFOOH FEFFH Internal high speed RAM Short direct addressing 256 x 8 bits FE20H td aes oe FE1FH FEOOH FDFFH Direct addressing Register indirect addressing Based addressing Reserved 1000H OFFFH Internal ROM 4 096 x 8 bits 0000H Y User s Manual U14801EJ3V1UD 43 A4 CHAPTER 3 CPU ARCHITECTURE Figure 3 7 Data Memory Addressing uPD789074 FFFFH Special function registers SFRs 256 x 8 bits SFR addressing FF20H FF1FH FFOOH FEFFH Short direct addressing Internal high speed RAM 256 x 8 bits F SCH oco SA eee FE1FH FEOOH FDFFH Direct addressing Register indirect addressing Based addressing Rese
157. of P27 WRrus2 Voo EEN Alternate function A Internal bus l JD 1 6 P27 T180 T080 Alternate function PUB2 Pull up resistor option register B2 PM Port mode register RD Port 2 read signal WR Port 2 write signal User s Manual U14801EJ3V1UD 69 CHAPTER 4 PORT FUNCTIONS 4 2 4 Port 3 This is a 2 bit UO port with an output latch Port 3 can be set to input or output mode in 1 bit units by using port mode register 3 PM3 When P30 and P31 are used as input port pins on chip pull up resistors can be connected in 2 bit units by setting pull up resistor option register O PUO Port 3 is also used for timer output and buzzer output RESET input sets port 3 to input mode Figure 4 9 shows a block diagram of port 3 Figure 4 8 Block Diagram of P30 and P31 WRPuo gt P ch Selector Internal bus Output latch P30 P31 PM30 PM31 Alternate function PUO Pull up resistor option register O gt P30 TO90 P31 BZO90 EA PM Port mode register RD Port3 read signal WR Port 3 write signal 70 User s Manual U14801EJ3V1UD CHAPTER 4 PORT FUNCTIONS 4 3 Port Function Control Registers The following two types of registers are used to control the ports Port mode registers PMO to PM3 Pull up resistor option registers PUO and PUB2 1 Port mode registers
158. ontroller total display outputs 25 UART resistance division method LCD 26 x 4 Remark VFD Vacuum Fluorescent Display is referred to as FIP Fluorescent Indicator Panel in some documents but the functions of the two are the same User s Manual U14801EJ3V1UD CHAPTER 1 GENERAL The major functional differences between the subseries are listed below Series for general purpose applications and LCD drive ROM Timer Capacity 16 Bit Watch Small uPD789046 scale PD789026 package general PD789088 purpose PD789074 applica 50789914 tions 4PD789062 4uPD789052 Small 4PD789177 Serial Interface 1 ch UART 1 ch Von MIN Value Remarks scale Pp789167 package general PD789156 purpose PD789146 applica 50789134A tions A D uPD789124A converter PD789114A 4PD789104A 11PD789835 4PD789830 1 ch UART 1 ch 1 ch UART 1 ch RC oscillation version 1 8 Vi 2 7V On chip EEPROM RC oscillation version Dot LCD supported 4PD789488 4PD789478 2 ch UART 1 ch uPD789417A 12Kto24K 4PD789407A uPD789456 12Kto 16K 4PD789446 4PD789436 4PD789426 1 ch UART 1 ch 1 8V 4PD789316 uPD789306 2 ch UART 1 ch 4PD789467 4PD789327 Note Flash memory version 3
159. or stabilizes after STOP mode has been released If processing must be resumed immediately by using an interrupt request therefore use the HALT mode In both modes the previous contents of the registers flags and data memory before setting standby mode are all retained In addition the statuses of the output latches of the I O ports and output buffers are also retained Caution To set STOP mode be sure to stop the operations of the peripheral hardware and then execute the STOP instruction User s Manual U14801EJ3V1UD 165 CHAPTER 11 STANDBY FUNCTION 11 1 2 Standby function control register The wait time after STOP mode is released upon interrupt request until the oscillation stabilizes is controlled with the oscillation stabilization time selection register OSTS OSTS is set with an 8 bit memory manipulation instruction RESET input sets OSTS to 04H However the oscillation stabilization time after RESET input is 2 fx instead of 2 fx Figure 11 1 Format of Oscillation Stabilization Time Selection Register Symbol 7 6 Address After reset R W 5 4 3 2 1 0 OSTS2 OSTS1 OSTSO Oscillation stabilization time selection At fx 10 0 MHz operationNete At fx 5 0 MHz operation PA a fem sam CI a ese eme fam CS Other than above Setting prohibited Note Expanded specification products only Caution The wait time after STOP mode is released does not include the time from STOP mode release to clock
160. ores the shift out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution User s Manual U14801EJ3V1UD 47 CHAPTER 3 CPU ARCHITECTURE 3 Stack pointer SP This is a 16 bit register to hold the start address of the memory stack area Only the internal high speed RAM area can be set as the stack area Figure 3 11 Stack Pointer Configuration The SP is decremented before writing saving to the stack memory and is incremented after reading restoring from the stack memory Each stack operation saves restores data as shown in Figures 3 12 and 3 13 Caution Since RESET input makes the SP contents undefined be sure to initialize the SP before instruction execution Figure 3 12 Data to Be Saved to Stack Memory PUSH rp CALL CALLT Interrupt instruction instructions SP SP 3 SP a SP 2 SP lt SP 2 SP 3 PC7 to PCO SP 2 Lower half SP 2 PC7 to PCO SP 2 PC15 to PC8 register pairs i SP 1 SE SP 1 PC15 to PC8 SP 1 PSW i register pairs d SP gt SP gt SP gt Figure 3 13 Data to Be Restored from Stack Memory POP rp RET instruction RETI instruction instruction sp Lower half SP gt PC7 to PCO SP gt PC7 to PCO register pairs SP41 Upper half SP 1 PC15 to PC8 SP 1 PC15 to PC8 register pairs SP a SP 2 SP SP 2 SP 2 PSW SP SP 3 48 Users Manual U14801EJ3V1UD
161. ormat of Asynchronous Serial Interface Transmit Receive Data One data frame Stop bit e Start bits 1 bit e Character bits 7 bits 8 bits e Parity bits Even parity odd parity O parity no parity e Stop bit s 1 bit 2 bits When 7 bits is selected as the number of character bits only the lower 7 bits bits O to 6 are valid in transmission the most significant bit bit 7 is ignored and in reception the most significant bit bit 7 is always 0 The serial transfer rate is selected by baud rate generator control register 20 BRGC20 If a serial data receive error is generated the receive error contents can be determined by reading the status of asynchronous serial interface status register 20 ASIS20 User s Manual U14801EJ3V1UD 133 CHAPTER 9 SERIAL INTERFACE 20 b Parity types and operation The parity bit is used to detect a bit error in the communication data Normally the same kind of parity bit is used on the transmitting side and the receiving side With even parity and odd parity a one bit odd number error can be detected With O parity and no parity an error cannot be detected i Even parity e At transmission The parity bit is determined so that the number of bits with a value of 1 in the transmit data including the parity bit is even The parity bit value should be as follows The number of bits with a value of 1 is an odd number in
162. oscillation start a in the figure below regardless of whether STOP mode is released by RESET input or by interrupt generation STOP mode release X1 pin voltage Waveform Remark fx System clock oscillation frequency 166 User s Manual U14801EJ3V1UD CHAPTER 11 STANDBY FUNCTION 11 2 Operation of Standby Function 11 2 1 HALT mode 1 HALT mode HALT mode is set by executing the HALT instruction The operation statuses in HALT mode are shown in the following table Table 11 1 Operation Statuses in HALT Mode HALT Mode Operation Status System clock generator System clock oscillation enabled Clock to CPU stopped epu Operation disables Al disabled Port output latch Remains in the state existing before the selection of HALT mode Note Maskable interrupt that is not masked 2 Releasing HALT mode HALT mode can be released by the following three sources a Releasing by unmasked interrupt request HALT mode is released by an unmasked interrupt request In this case if interrupt request acknowledgment is enabled vectored interrupt servicing is performed If interrupt acknowledgment is disabled the instruction at the next address is executed Figure 11 2 Releasing HALT Mode by Interrupt HALT instruction Wait Standby release signal Operating mode HALT mode gt lt gt La gt Clock Oscillation Remarks 1 The broken lines indicate the case
163. ossible to determine what kind of error occurred during reception by reading the contents of ASIS20 in the reception error interrupt servicing see Table 9 7 and Figure 9 10 The contents of ASIS20 are reset to O by reading receive buffer register 20 RXB20 or receiving the next data if there is an error in the next data the corresponding error flag is set Table 9 7 Receive Error Causes Transmission time parity and reception data parity do not match Reception of next data is completed before data is read from receive buffer register Figure 9 10 Receive Error Timing a Parity error occurred STOP RxD20 Input D1 D2 D7 START INTSR20 b Framing error or overrun error occurred START INTSR20 Cautions 1 The contents of the ASIS20 register are reset to 0 by reading receive buffer register 20 RXB20 or receiving the next data To ascertain the error contents read ASIS20 before reading RXB20 2 Be sure to read receive buffer register 20 RXB20 even if a receive error occurs If RXB20 is not read an overrun error will occur when the next data is received and the receive error state will continue indefinitely User s Manual U14801EJ3V1UD 137 CHAPTER 9 SERIAL INTERFACE 20 f Reading receive data When the reception completion interrupt INTSR20 is generated read the value of receive buffer register 20 RXB20 to read the receive data When reading the receive data stored in receive buffer register 20
164. output Note Expanded specification products only Caution Bits 4 to 7 must all be set to 0 Remarks 1 fx System clock oscillation frequency 2 fcl Count clock frequency of 16 bit timer 90 User s Manual U14801EJ3V1UD 87 CHAPTER 6 16 BIT TIMER 90 3 Port mode register 3 PM3 PMSG is used to set each bit of port 3 to input or output When pin P30 TO90 is used for timer output reset the output latch of P30 and PM30 to 0 when pin P31 BZO90 is used for buzzer output reset the output latch of P31 and PM31 to 0 PM3 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM3 to FFH Figure 6 4 Format of Port Mode Register 3 Symbol 7 6 Address After reset R W 5 4 3 2 1 0 FF23H FFH R W EM Output mode output buffer on Input mode output buffer off 88 User s Manual U14801EJ3V1UD CHAPTER 6 16 BIT TIMER 90 6 4 Operation of 16 Bit Timer 90 6 4 1 Operation as timer interrupt 16 bit timer 90 can generate interrupts repeatedly each time the free running counter value reaches the value set to CR90 Since this counter is not cleared and holds the count even after an interrupt is generated the interval time is equal to one cycle of the count clock set in TCL901 and TCL900 To operate 16 bit timer 90 as a timer interrupt the following settings are required e Set the count value in CR90 e Set 16 bit timer mode control register 90 TMC90 as shown in Figure 6 5 Figure 6 5 Settings of 1
165. output is output iii Slave operation when DAP20 0 CKP20 0 SSE20 1 SS20 SIO20 Write SCK20 INTCSI20 Notes 1 The value of the last bit previously output is output 2 DOO is output until SS20 rises When S820 is high SO20 is in a high impedance state 144 User s Manual U14801EJ3V1UD CHAPTER 9 SERIAL INTERFACE 20 Figure 9 11 3 Wire Serial UO Mode Timing 3 7 iv Master operation when DAP20 0 CKP20 1 SSE20 0 SIO20 Write SCK20 5020 SI20 INTCSI20 d v Slave operation when DAP20 0 CKP20 1 SSE20 0 SIO20 Write SCK20 SIO20 Write master Note niu sa ED ED ED ED E Yo ED INTCSI20 d Note The data of SI20 is loaded at the first rising edge of SCK20 Make sure that the master outputs the first bit before the first rising of SCK20 User s Manual U14801EJ3V1UD 145 CHAPTER 9 SERIAL INTERFACE 20 Figure 9 11 3 Wire Serial l O Mode Timing 4 7 vi Slave operation when DAP20 0 CKP20 1 SSE20 1 SS20 SIO20 Write SCK20 1 2 3 4 5 6 7 8 SIO20 Write master Note1 del T B SI20 i Hi Z 020 4 AD Do7 X Dos X Dos j Do4 X Dos Doe X po poo f l Em Notes 1 The data of SI20 is loaded at the first rising edge of SCK20 Make sure that the master outputs the first bit before the first rising of SCK20 2 SO20 is high until SS20 rises after completion of DOO output When SS20 is high SO20 is in a high imp
166. p oe Dade donee 92 6 4 Buzzer Frequency of 16 Bit Timer 90 sanrnrrrnrnnnnnnvnrenvnnvnenvnnennnnnnvnvenvnnnnensnrnnenvnnnnenrnnvnenennrnnenennnnensnnnnenvnrenenennn 94 7 1 Interval Time of 8 Bit Timer Event Counter 90 97 7 2 Square Wave Output Range of 8 Bit Timer Event Counter 80 97 7 3 Configuration of 8 Bit Timer Event Counter 0 98 7 4 Interval Time of 8 Bit Timer Event Counter 90 101 7 5 Square Wave Output Range of 8 Bit Timer Event Counter nennen 104 8 1 Inadvertent Loop Detection Time of Watchdog Tmer eere 109 8 2 Interval TIMO ot rhe A io A Or endo Sea 109 8 3 Configuration of Watchdog Timer nennen nennen neen nne nnen rnit e eren nnns enn 110 8 4 Inadvertent Loop Detection Time of Watchdog Timer emere 113 8 5 Interval Generated Using Interval Timer ooooonnccninccinnccnocccnnonanonncnnnnn nac n nora nan n cnn n nennen nnne 114 9 1 Configuration of Serial Interface 20 115 9 2 Operating Mode Settings of Serial Interface 20 121 9 3 Example of Relationship Between System Clock and Baud Hate 124 9 4 Relationship Between ASCK20 Pin Input Frequency and Baud Rate When BRGC20 Is Set to 80H 125 9 5 Example of Relationship Between System Clock and Baud Hate 132 9 6 X Relationship Between ASCK20 Pin Input Frequency and Baud Rate When BRGC20 Is Set to 80H 132 18 User s Manual U14801EJ8V1UD LIST OF TABLES 2 2 Table No Title Page 9 7 Receive Error Causes E tl iia dd dd 137 ln HL Ve 151
167. peration as external event counter The external event counter counts the number of external clock pulses input to the TI80 P27 T080 pin by using 8 bit timer counter 80 TM80 To operate 8 bit timer event counter 80 as an external event counter settings must be made in the following sequence 1 Set P27 to input mode PM27 1 2 Disable operation of 8 bit timer counter 80 TM80 TCE80 bit 7 of 8 bit timer mode control register 80 TMC80 0 lt 3 gt Specify the rising or falling edge of TI80 see Table 7 4 Disable output of TO80 TOE80 bit O of TMC80 0 and PWM output PWME80 bit 6 of TMC80 0 4 Set a count value in CR80 lt 5 gt Enable the operation of TM80 TCE80 1 Each time the valid edge specified by bit 1 TCL800 of TMC80 is input the value of 8 bit timer counter 80 TM80 is incremented When the count value of TM80 matches the value set in CR80 TM80 is cleared to 0 and continues counting At the same time an interrupt request signal INTTM80 is generated Figure 7 5 shows the timing of the external event counter operation with rising edge specified Cautions 1 Before rewriting CR80 stop the timer operation If CR80 is rewritten while the timer operation is enabled a match interrupt request signal may be generated immediately at the point of rewrite 2 If setting the count clock to TMC80 and enabling the operation of TM80 are performed at the same time with an 8 bit memory manip
168. put controller of 8 bit timer event counter 80 TMC80 is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears TMC80 to 00H Figure 7 2 Format of 8 Bit Timer Mode Control Register 80 Symbol lt 7 gt 6 Address After reset R W 5 4 3 2 1 lt gt TMC80 TCE80 E GEM TCL801 TCL800 TOE80 FF53H 00H R W TCE80 8 bit timer counter 80 operation control EM Operation disabled TM80 is cleared to 0 Operation enabled PWME80 Operation mode selection EM Timer counter operation mode PWM output mode TCL801 TCL800 8 bit timer counter 80 count clock selection At fx 10 0 MHz operationNete 1 At fx 5 0 MHz operation e fem Joe lesen 0 Falling edge of TI80N 2 TOE80 8 bit timer event counter output control H Output disabled port mode Output enabled Notes 1 Expanded specification products only 2 When inputting a clock signal externally timer output cannot be used Caution Always stop the timer before setting TMC80 Remark fx System clock oscillation frequency User s Manual U14801EJ3V1UD 99 CHAPTER 7 8 BIT TIMER EVENT COUNTER 80 2 Port mode register 2 PM2 PM2 specifies whether each bit of port 2 is used for input or output To use the TO80 P27 T180 pin for timer output the PM27 and P27 output latch must be reset to 0 To use the TO80 P27 TI80 pin for timer input PM27 must be set to 1 PM2 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM2 to FFH
169. r more interrupts are simultaneously generated each interrupt has a predetermined priority as shown in Table 10 1 A standby release signal is generated There are three external sources and five internal sources of maskable interrupts 10 2 Interrupt Sources and Configuration There are a total of 9 non maskable and maskable interrupt sources see Table 10 1 150 User s Manual U14801EJ3V1UD Interrupt Type Non maskable interrupt Maskable interrupt Notes 1 Remark CHAPTER 10 INTERRUPT FUNCTIONS Table 10 1 Interrupt Sources Priority Interrupt Source Internal External Vector Table Basic Name Trigger Address Configuration Type INTWDT Watchdog timer overflow Internal when watchdog timer mode 1 is selected INTWDT Watchdog timer overflow when interval timer mode is selected INTPO Pin input edge detection External INTP1 INTP2 INTST20 End of UART transmission on serial interface 20 INTTM80 Generation of match signal for 8 bit timer event counter 80 INTTM90 Generation of match signal for 16 bit timer 90 Priority is the priority order when several maskable interrupt requests are generated at the same time O is the highest and 7 is the lowest Basic configuration types A B and C correspond to A B and C in Figure 10 1 serial interface 20 reception on serial interface 20 There are two interrupt sources for the watchdog timer INTWDT non maskable interrupts and maskable inter
170. rated 00H 00H 00H 00H immediately at the point of rewrite 2 If CR80 is rewritten during timer operation in PWM output operation mode PWME80 1 pulses may not be generated for one cycle after the rewrite 3 Do not set CR80 to 00H in PWM operation mode when PWME80 1 otherwise PWM may not be output normally User s Manual U14801EJ3V1UD 107 CHAPTER 7 8 BIT TIMER EVENT COUNTER 80 3 Timer operation after compare register is rewritten during PWM output When 8 bit compare register 80 CR80 is rewritten during PWM output if the new value is smaller than that of 8 bit timer counter 80 TM80 a high level signal may be output for the next cycle 256 count pulses after the CR80 value is rewritten Figure 7 10 shows the timing at which the high level signal is output Figure 7 10 Operation Timing After Compare Register Is Rewritten During PWM Output Count clock UU UU UU me oon delt Kelt NENN VV 69990 C C C CR80 M x 01H TCE80 H OVF INTTM80 TO80 A CR80 rewritten M 02H to FFH k 4 Cautions when STOP mode is set Be sure to stop timer operations TCE80 0 before executing the STOP instruction 5 Start timing of external event counter When the rising edge of TI80 is selected as the count clock start the timer when TI80 is low level TCE80 0 gt 1 Likewise when the falling edge of TI80 is selected as the count clock start the timer when TI80 is high level TCE80
171. re edge and capture operation timing respectively Table 6 3 Settings of Capture Edge CPT901 CPT900 Capture Edge Selection NE dee Capture operation disabled Caution Because TCP90 is rewritten when a capture trigger edge is detected during a TCP90 read disable the capture trigger edge detection during a TCP90 read Figure 6 10 Capture Operation Timing with Both Edges of CPT90 Pin Specified Count clock TM90 0000H A 0001H Count read buffer 0000H X 0001H z TCP90 Undefined Capture start Capture start CPT90 l A A Capture edge detection Capture edge detection Remark N 0000H to FFFFH M 0000H to FFFFH 92 Users Manual U14801EJ3V1UD CHAPTER 6 16 BIT TIMER 90 6 4 4 16 bit timer counter 90 readout The count value of 16 bit timer counter 90 TM90 is read out with a 16 bit manipulation instruction TM90 readout is performed through a counter read buffer The counter read buffer latches the TM90 count value The buffer operation is then held pending at the CPU clock falling edge after the read signal of the TM90 lower byte rises and the count value is retained The counter read buffer value at the retention state can be read out as the count value Cancellation of the pending state is performed at the CPU clock falling edge after the read signal of the TM90 higher byte falls RESET input clears TM90 to 0000H and TM90 resumes counting in the free running mode Figure 6 11 shows the timing of 1
172. rupts Either one but not both should be selected for actual use User s Manual U14801EJ3V1UD 151 CHAPTER 10 INTERRUPT FUNCTIONS Figure 10 1 Basic Configuration of Interrupt Function A Internal non maskable interrupt Internal bus Vector table address generator gt Standby release signal Interrupt request B Internal maskable interrupt Internal bus Vector table address generator Interrupt request Standby release signal External interrupt mode register 0 INTMO Vector table Interrupt g address generator request Standby release signal IF Interrupt request flag IE Interrupt enable flag MK Interrupt mask flag 152 User s Manual U14801EJ3V1UD CHAPTER 10 INTERRUPT FUNCTIONS 10 3 Interrupt Function Control Registers The interrupt functions are controlled by the following four types of registers Interrupt request flag registers O and 1 IFO and IF1 Interrupt mask flag registers 0 and 1 MKO and MK1 External interrupt mode register O INTMO Program status word PSW Table 10 2 lists interrupt requests the corresponding interrupt request flags and interrupt mask flags Table 10 2 Interrupt Request Signals and Corresponding Flags Interrupt Request Signal Interrupt Request Flag Interrupt Mask Flag INTWDT WDTIF WDTMK INTPO PIFO PMKO INTP1 PIF1 PMK1 INTP2 PIF2 PMK2 INTSR20 INTCSI20 SRIF20 SRMK20 INTST20 STIF20 STMK20 INTTM80
173. rved 2000H 1FFFH Internal ROM 8 192 x 8 bits 0000H Y Users Manual U14801EJ3V1UD CHAPTER 3 CPU ARCHITECTURE Figure 3 8 Data Memory Addressing uPD78F9076 FFFFH Special function registers SFRs 256 x 8 bits SFR addressing FF20H SE Gi GR e TET ern EE FFOOH FEFFH Internal high speed RAM 256 x 8 bits FE20H FE1FH FEOOH Short direct addressing FDFFH Reserved 4000H Direct addressing Register indirect addressing Based addressing 3FFFH Internal flash memory 16 384 x 8 bits 0000H User s Manual U14801EJ3V1UD 45 CHAPTER 3 CPU ARCHITECTURE 3 2 Processor Registers The uPD789074 Subseries provides the following on chip processor registers 3 2 1 Control registers The control registers have special functions to control the program sequence statuses and stack memory The control registers include a program counter a program status word and a stack pointer 1 Program counter PC The program counter is a 16 bit register which holds the address information of the next program to be executed In normal operation the PC is automatically incremented according to the number of bytes of the instruction to be fetched When a branch instruction is executed immediate data or register contents are set RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter Figure 3 9 Program Counter Configuration 15 0 2 Program st
174. s data and INTSR20 is not generated When RXE20 is set to O at the time indicated by lt 2 gt RXB20 renews the data and INTSR20 is not generated When RXE20 is set to 0 at the time indicated by lt 3 gt RXB20 renews the data and INTSR20 is generated User s Manual U14801EJ3V1UD 139 CHAPTER 9 SERIAL INTERFACE 20 9 4 3 3 wire serial l O mode The 3 wire serial I O mode is useful for connection of peripheral I Os and display controllers etc that incorporate a conventional synchronous serial interface such as the 75XL Series 78K Series 17K Series etc Communication is performed using three lines the serial clock SCK20 serial output SO20 and serial input SI20 1 Register setting 3 wire serial I O mode settings are performed using serial operation mode register 20 CSIM20 asynchronous serial interface mode register 20 ASIM20 baud rate generator control register 20 BRGC20 port mode register 2 PM2 and port 2 P2 a Serial operation mode register 20 CSIM20 CSIM20 is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears CSIM20 to 00H Symbol lt 7 gt 6 Address After reset R W 5 4 3 2 1 0 CSIM20 O DAP20 DIR20 egen CKP20 FF72H 00H R W CSIE20 3 wire serial UO mode operation control EN Operation disabled Operation enabled SSE20 SS20 pin selection Function of SS20 P23 pin 1 Used PK IDR Communication enabled Communication disabled DAP20 3 wire serial UO mode data phase
175. s follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the wiring with the other signal lines Do not route the wiring near a signal line through which a high fluctuating current flows Always make the ground point of the oscillator capacitor the same potential as Vss Do not ground the capacitor to a ground pattern through which a high current flows Do not fetch signals from the oscillator User s Manual U14801EJ3V1UD CHAPTER 16 ELECTRICAL SPECIFICATIONS CONVENTIONAL PRODUCTS Recommended Oscillator Constant Ceramic resonator Ta 40 to 85 C Mask ROM version Manufacturer Part Number Frequency Recommended Circuit Oscillation Voltage Remarks Constant pF Range Von Murata Mfg CSBLA1M00J58 BO y E Rd 1 0 kQ Co Ltd standard product CSTCC2M00G56 RO i On chip capacitor CSBFB1M00J58 R1 CSTLS2M00G56 BO CSTCR4M00G53 RO CSTLS4M00GG53 BO CSTCR4M19G53 RO CSTLS4M19GG53 BO CSTCR4M91G53 RO CSTLS4M91GG53 BO CSTCR5M00G53 RO CSTLS5M00GG53 BO Note A limiting resistor Rd 1 0 kQ is required when CSBLA1M00J58 BO or CSBFB1M00J58 R1 1 0 MHz manufactured by Murata Mfg Co Ltd is used as the ceramic resonator see the figure below This is not necessary when using one of the other recommended resonators CSBLA1M00J58 B0 ng CSBFB1M00J58 R1 ID
176. selection EN Outputs at the falling edge of SCK20 Outputs at the rising edge of SCK20 DIR20 First bit specification KO CO CSCK20 3 wire serial UO mode clock selection Ea External clock input to the SCK20 pin Output of the dedicated baud rate generator CKP20 3 wire serial UO mode clock phase selection Wa Clock is active low and SCK20 is at high level in the idle state Clock is active high and SCK20 is at low level in the idle state Caution Bits 4 and 5 must both be set to 0 140 User s Manual U14801EJ3V1UD CHAPTER 9 SERIAL INTERFACE 20 b Asynchronous serial interface mode register 20 ASIM20 ASIM20 is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears ASIM20 to 00H When 3 wire serial UO mode is selected ASIM20 must be set to OOH Symbol lt 7 gt Address After reset R W TXE20 Transmit operation control EY Transmit operation stop Transmit operation enable RXE20 Receive operation control Na Receive operation stop Receive operation enable PS201 PS200 Parity Bit specification CO ems LL 1 Always add 0 parity at transmission Parity check is not performed at reception no parity error occurs m Odd parity CL20 Character length specification ar 1 Transmit data sop bit length specification Cautions 1 Bits 0 and 1 must both be set to 0 2 Switch operating modes after halting the serial transmit receive operation User s Manual U14801EJ3V1UD 141 CHAPTER
177. series Japanese Windows 3 5 2HD FD BB13 IBM PC AT and compatibles English Windows AB17 Japanese Windows CD ROM BB17 English Windows 230 User s Manual U14801EJ3V1UD APPENDIX B NOTES ON TARGET SYSTEM DESIGN The following show the conditions when connecting the emulation probe to the conversion adapter Follow the configuration below and consider the shape of parts to be mounted on the target system when designing a system Figure B 1 Distance Between In Circuit Emulator and Conversion Adapter In circuit emulator IE 78KOS NS or IE 78K0S NS A Target system Emulation board IE 789046 NS EM1 Board on end of NP 30MC TGCN1 ec i s numm y Conversion adapter YSPACKSOBK NSPACK30BK Emulation probe NP 30MC Remarks 1 NP 30MC is a product of Naito Densei Machida Mfg Co Ltd 2 YSPACK30BK and NSPACK30BK are products of TOKYO ELETECH CORPORATION User s Manual U14801EJ3V1UD 231 APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figure B 2 Connection Condition of Target System Emulation board 1E 789046 NS EM1 Emulation probe A NP 30MC Board on end of NP 30MC Guide pin YQGUIDE Conversion adapter YSPACKSOBK NSPACK30BK 13 mm Se w Y Ty Target system Remarks 1 NP 30MC is a product of Naito Densei Machida Mfg Co Ltd 2 YSPACK30BK NSPACK30BK and YQGUIDE are products of TOKYO ELETECH CORPORATION 232 User s Manual U14801EJ3V1UD APPENDIX C REGISTER INDEX
178. st Acknowledgment Processing Algorithm A 161 10 10 Interrupt Request Acknowledgment Timing Example of MOV An 162 10 11 Interrupt Request Acknowledgment Timing When Interrupt Request Flag Is Set at Last Clock During Instruction GT TEE 162 10 42 Example of Multiple Interrupts rnt cicer reet tte pete ce dede nane E puce cnet 163 11 1 Format of Oscillation Stabilization Time Selection Heglster A 166 11 2 Releasing HALT Mode by Interupt AAA 167 11 3 Releasing HALT Mode by RESET A 168 11 4 Releasing STOP Mode by Interrupt AAA 170 11 5 Releasing STOP Mode by RESET Ud ita 170 12 1 Block Diagram of Reset Function rrrnnvnrnrnvnnnnnnnvnrnrnnvnnnvvnrnnenvnnvnenrnnnnenvnnenenvnnvnrervnnnnenvnvenenvnnnnesrnnnnenenrenenenen 171 12 2 Reset Timing by RESET Input O 172 12 8 Reset Timing by Watchdog Timer Overtlow nennen nennen nnne nennen 172 12 4 Reset Timing by RESET Input in STOP Mode mann iue et ete o 172 13 1 Environment for Writing Program to Flash Memory cooooocccnnonccnonocnnonononcnnononcnnnnno emm eene nne 175 13 2 Communication Mode Selection Fommat A 176 19 8 Example of Connection with Dedicated Flash Programmer 177 13 47 Ver Pin Connection Example nici ectetuer codec erc nein aiid A e e Fx end 179 13 5 Signal Conflict Serial Interface Input Pin nennen nennen nennen 180 13 6 Malfunction of Another Device EE 180 13 7 Signal Confliet RESET Pi stories ad 181 13 8 Wiring Example for Flash Writing Adapter Using
179. st the resonator manufacturer for evaluation on the implementation circuit Note that the oscillation voltage and oscillation frequency merely indicate the characteristics of the oscillator Use the internal operation conditions of the uPD789071 789072 and 789074 within the specifications of the DC and AC characteristics User s Manual U14801EJ3V1UD 197 CHAPTER 15 ELECTRICAL SPECIFICATIONS EXPANDED SPECIFICATION PRODUCTS Ceramic resonator Ta 40 to 85 C uPD78F9076 Manufacturer Part Number Murata Mfg Co Ltd Murata Mfg Frequency Recommended Circuit Oscillation Voltage Range Remarks MHz Constant eo Voo CSBLA1M00J58 B0 100 100 2 1 5 5 pem 1 0kQ CSBFB1M00J58 R1 CSTCC2M00G56 RO CSTLS2M00G56 BO CSTCR4M00G53 RO CSTLS4M00GG53 BO CSTCR4M19G53 RO CSTLS4M19GG53 BO CSTCR4M91G53 RO CSTLS4M91GG53 BO CSTCR5M00G53 RO CSTLS5M00GG53 BO CSTCR6M00G53 RO CSTLS6M00GG53 BO CSTCE8M00G52 RO CSTLS8M00G53 BO CSTCE8M38G52 RO CSTLS8M38G53 BO CSTCE10M0G52 RO CSTLS10M0G53 BO CSTCR4M00G53093 RO Co Ltd low csTLS4M00GG53093 B0 voltage drive CSTCR4M19G53093 RO type CSTLS4M19GG53093 BO CSTCR4M91G53093 RO CSTLS4M91GG53093 BO CSTCR5M00G53093 RO CSTLS5M00GG53093 BO CSTCR6M00G53093 RO CSTLS6M00GG53093 BO On EE 3 capacitor 8 388 10 0 4 0 On chip capacitor 4 194 4 915 5 0 CSTLS8M00G53093 B0 80 CSTLS8M38G53093 BO 8 388 CSTLS10M0G53U BO Note A limiting resistor Rd 1 0
180. stal oscillation Von 5 0 V 10 C1 C2 22 pF T DT SN EE enne oos so m Power supply 10 0 MHz crystal Voo 5 0 V 1099 18 0 mA current oscillation operating mode EE 6 0 MHz crystal oscillation Von 5 0 V 10 operating mode Note 2 5 0 MHz crystal oscillation Voo 5 0 V 10 C1 C2 22 pF VDD 2 0 V 109 10 0 MHz crystal Voo 5 0 V 1090 oscillation HALT mode 6 0 MHz crystal oscillation Von 5 0 V 21095 HALT mode 5 0 MHz crystal oscillation Von 5 0 V 21095 C1 C2 22 pF Voo 2 0 V 109 trcs mam c OU hene om es fa Notes 1 The port current including the current flowing through the on chip pull up resistors is not included 2 High speed mode operation when processor clock control register PCC is set to 00H 3 Low speed mode operation when PCC is set to 02H Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of port pins User s Manual U14801EJ3V1UD 201 CHAPTER 15 ELECTRICAL SPECIFICATIONS EXPANDED SPECIFICATION PRODUCTS AC Characteristics 1 Basic operation Ta 40 to 85 C Voo 1 8 to 5 5 V 2 8 AS Cycle time Tcv Voo 4 5 to 5 5 V 0 Mini instruct Minimum struction Voo 3 0 to 5 5 V 0 33 8 us execution time Voo 2 7 to 5 5 V 0 4 8 AS Voo 1 8 to 5 5 V TI80 input fr Voo 2 7 to 5 5 V frequency Voo 1 8 to 5 5 V TI80 input hig
181. stop bit s are added automatically When the transmit operation starts the data in TXS20 is shifted out and when TXS20 is empty a transmission completion interrupt INTST20 is generated Figure 9 8 Asynchronous Serial Interface Transmission Completion Interrupt Timing a Stop bit length 1 INTST20 b Stop bit length 2 START INTST20 Caution Do not rewrite asynchronous serial interface mode register 20 ASIM20 during a transmit operation If the ASIM20 register is rewritten during transmission subsequent transmission may not be performed the normal state is restored by RESET input It is possible to determine whether transmission is in progress by software by using a transmission completion interrupt INTST20 or the interrupt request flag STIF20 set by INTST20 User s Manual U14801EJ3V1UD 135 136 CHAPTER 9 SERIAL INTERFACE 20 d Reception When bit 6 RXE20 of asynchronous serial interface mode register 20 ASIM20 is set to 1 a receive operation is enabled and sampling of the RxD20 pin input is performed RxD20 pin input sampling is performed using the serial clock specified by BRGC20 When the RxD20 pin input becomes low the 3 bit counter starts counting and at the time when half the time determined by the specified baud rate has passed the data sampling start timing signal is output If the RxD20 pin input sampled again as a result of this start timing signal is low it is identified as a start b
182. synchronous serial interface UART mode In this mode the one byte data following the start bit is transmitted received and thus full duplex communication is possible This device incorporates a UART dedicated baud rate generator that enables communication at the desired baud rate from many options In addition the baud rate can also be defined by dividing the clock input to the ASCK20 pin The UART dedicated baud rate generator can also output the 31 25 kbps baud rate that complies with the MIDI standard 1 Register setting UART mode is set by serial operation mode register 20 CSIM20 asynchronous serial interface mode register 20 ASIM20 asynchronous serial interface status register 20 ASIS20 baud rate generator control register 20 BRGC20 port mode register 2 PM2 and port 2 P2 User s Manual U14801EJ3V1UD 127 CHAPTER 9 SERIAL INTERFACE 20 a Serial operation mode register 20 CSIM20 CSIM20 is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears CSIM20 to 00H Set CSIM20 to 00H when UART mode is selected Symbol 7 6 Address After reset R W S 4 3 2 4 0 CSIM20 O DAP20 DIR20 egen ckeao FF72H 00H R W CSIE20 3 wire serial UO mode operation control EG Operation disabled Operation enabled SSE20 SS20 pin selection Function of SS20 P23 pin 1 Used PF a Communication enabled Communication disabled DAP20 3 wire serial I O mode data phase selection ES Outputs at the falling edge o
183. t As soon as a match occurs TM80 is cleared to 0 and continues counting generating an interrupt request signal INTTM80 Setting bit 7 TCE80 of TMC80 to 0 clears the square wave output to 0 Table 7 5 shows the square wave output range and Figure 7 6 shows the timing of square wave output Cautions 1 Stop the timer operation before rewriting CR80 If CR80 is rewritten while the timer operation is enabled a match interrupt request signal may be generated immediately at the point of rewrite 2 If setting the count clock to TMC80 and enabling the operation of TM80 are performed at the same time with an 8 bit memory manipulation instruction the error one cycle after the timer has been started may exceed one clock To use 8 bit timer event counter 80 as a square wave output therefore make the settings in the above sequence Table 7 5 Square Wave Output Range of 8 Bit Timer Event Counter TCL801 TCL800 Minimum Pulse Width Maximum Pulse Width Resolution At fx 10 0 MHz At fx 5 0 MHz At fx 10 0 MHz At fx 5 0 MHz At fx 10 0 MHz At fx 5 0 MHz Operation Operation Operation Operation Operation Operation Note Expanded specification products only Remark fx System clock oscillation frequency 104 User s Manual U14801EJ3V1UD CHAPTER 7 8 BIT TIMER EVENT COUNTER 80 Figure 7 6 Square Wave Output Timing ss EEE KEREN ENER al 140 cour van CPCI CO 2 C XY OA A A Clear Clear NE EE EC E Count start INTTM8
184. t 6 gt lt 5 gt lt 4 gt lt 3 gt lt 2 gt lt 1 gt PUB2 PUB27 PUB26 PUB25 PUB24 PUB23 PUB22 PUB21 PUB20 FF32H 00H R W PUB2n P2n on chip pull up resistor selection n 0 to 7 EON On chip pull up resistor is not used On chip pull up resistor is used User s Manual U14801EJ3V1UD 73 CHAPTER 4 PORT FUNCTIONS 4 4 Operation of Port Functions The operation of a port differs depending on whether the port is set to input or output mode as described below 4 4 1 Writing to I O port 1 2 In output mode A value can be written to the output latch of a port by using a transfer instruction The contents of the output latch can be output from the pins of the port Once data is written to the output latch it is retained until new data is written to the output latch In input mode A value can be written to the output latch by using a transfer instruction However the status of the port pin is not changed because the output buffer is OFF Once data is written to the output latch it is retained until new data is written to the output latch Caution A 1 bit memory manipulation instruction is executed to manipulate one bit of a port However this instruction accesses the port in 8 bit units When this instruction is executed to manipulate a bit of a port consisting both of inputs and outputs therefore the contents of the output latch of the pin that is set to input mode and not subject to manipulation become un
185. tage Data Retention Characteristics Ta 40 to 85 C Data retention power Vom ree voltage Release Release signal set time set time o Oscillation stabilization twat Release by RESET as a E E P 3 Note 1 Notes 1 Oscillation stabilization wait time is the time in which the CPU operation is stopped to prevent unstable operation when oscillation is started 2 Selection of 2 fx 2 fx and 2 fx is possible using bits 0 to 2 OSTSO to OSTS2 of the oscillation stabilization time select register OSTS Remark fx System clock oscillation frequency Data Retention Timing STOP Mode Release by RESET Internal reset operation HALT mode lt jT STOP mode mhain I Operation mode Data retention mode STOP instruction execution _ RESET twat Data Retention Timing Standby Release Signal STOP Mode Release by Interrupt Signal HALT mode lt 3T STOP mode murte Operation mode Data retention mode STOP instruction execution Standby release signal interrupt request twarr User s Manual U14801EJ3V1UD 207 CHAPTER 15 ELECTRICAL SPECIFICATIONS EXPANDED SPECIFICATION PRODUCTS Flash Memory Write Erase Characteristics Ta 10 to 40 C Von 1 8 to 5 5 V Voo 1 8 to 5 5 V Write current lopw When Ver supply During fx 5 0 MHz Voo pin voltage Vrr1 operation Note Write current Ver pin Erase current love
186. ter O PUO Port 2 Input SCK20 ASCK20 8 bit I O port l SO20 TxD20 Input output can be specified in 1 bit units An on chip pull up resistor can be specified by setting pull up resistor SI20 RxD20 option register B2 PUB2 SS20 INTP2 CPT90 TI80 TO80 Port 3 Input TO90 2 bit I O port BZO90 Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by setting pull up resistor option register O PUO User s Manual U14801EJ3V1UD 63 CHAPTER 4 PORT FUNCTIONS 4 2 Port Configuration Ports include the following hardware Table 4 2 Configuration of Port Parameter Configuration Control registers Port mode registers PMm m 0 to 3 Pull up resistor option register O PUO Pull up resistor option register B2 PUB2 Ports CMOS I O 24 Pull up resistors Software control 24 4 2 1 Port 0 This is an 8 bit I O port with an output latch Port O can be set to input or output mode in 1 bit units by using port mode register 0 PMO When pins POO to PO7 are used as input port pins on chip pull up resistors can be connected in 8 bit units by setting pull up resistor option register O PUO RESET input sets port 0 to input mode Figure 4 2 shows a block diagram of port 0 Figure 4 2 Block Diagram of P00 to P07 WRPuo gt P ch Selector Internal bus A PO0 to P07 Output latch POO to P07 PM00 to PMO7
187. terrupt Operation 0000H 0001H PETE FFFFHX0000HX0001 ODONODOX Interrupt i i I lore acknowledgment acknowledgment LAA 5 Overflow flag set Remark N 0000H to FFFFH Users Manual U14801EJ3V1UD CHAPTER 6 16 BIT TIMER 90 6 4 2 Operation as timer output 16 bit timer 90 can invert the timer output repeatedly each time the free running counter value reaches the value set to CR90 Since this counter is not cleared and holds the count even after the timer output is inverted the interval time is equal to one cycle of the count clock set in TCL901 and TCL900 To operate 16 bit timer 90 as a timer output the following settings are required e Set P30 to output mode PM30 0 e Reset the output latch of P30 to 0 e Set the count value in CR90 Set 16 bit timer mode control register 90 TMC90 as shown in Figure 6 7 Figure 6 7 Settings of 16 Bit Timer Mode Control Register 90 for Timer Output Operation TOD90 TOF90 CPT901 CPT900 TOC90 TCL901 TCL900 TOE90 mose mw po w o TO90 output enable Setting of count clock see Table 6 2 Inversion enable of timer output data Caution If both the CPT901 and CPT900 flags are set to 0 the capture operation is disabled When the count value of 16 bit timer counter 90 TM90 matches the value set in CR90 the output status of the TO90 P30 pin is inverted This enables timer output At that time the TM90 count continues and an interrupt request signal INTTM90
188. the uPD789071 A 789072 A or 789074 A gt The only differences between standard products and A products are the quality grades and electrical specifications refer to 1 10 Differences Between Standard Quality Grade Products and A Products For the A products read the part numbers as follows LPD789071 gt 4PD789071 A uPD789072 gt uPD789072 A uPD789074 gt uPD789074 A To understand the overall functions of the PD789074 Subseries Read this manual in the order of the CONTENTS How to read register formats gt The name of a bit whose number is enclosed with lt gt is reserved in the assembler and is defined in the C compiler by the header file sfrbit h To learn the detailed functions of a register whose register name is known See APPENDIX C REGISTER INDEX To learn details of the instruction functions of the 78K 0S Series gt Refer to 78K 0S Series Instructions User s Manual U11047E available separately To learn the electrical specifications of the uPD789074 Subseries gt Refer to CHAPTER 15 ELECTRICAL SPECIFICATIONS EXPANDED SPECIFICATION PRODUCTS and CHAPTER 16 ELECTRICAL SPECIFICATIONS CONVENTIONAL PRODUCTS Caution The application examples in this manual are created for Standard quality grade products for general electric equipment When using the application examples in this manual for purposes which require Special quality grades thoroughly examine the quality grade of each part and circuit actually
189. tion At fx 10 0 MHzNete2 At fx 5 0 MHz Setting prohibited TOE90 16 bit timer counter output control BN Output disabled port mode Output enabled Notes 1 Bit 7 is read only 2 Expanded specification products only Caution Disable interrupts in advance using interrupt mask flag register 1 MK1 when changing the data of TCL901 and TCL900 Also prevent the timer output data from being inverted by setting TOC90 to 1 Remark fx System clock oscillation frequency 86 User s Manual U14801EJ3V1UD CHAPTER 6 16 BIT TIMER 90 2 Buzzer output control register 90 BZC90 This register selects a buzzer frequency based on fcl selected with the count clock select bits TCL901 and TCL900 and controls the output of a square wave BZC90 is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears BZC90 to 00H Figure 6 3 Format of Buzzer Output Control Register 90 Symbol 7 6 lt 0 gt Address After reset R W 5 4 3 2 1 0 BCS902 BCS901 BCS900 Buzzer frequency fx 10 0 MHz operationNete fx 5 0 MHz operation fel fx 2 fcl 2 6 29 fcl fx 2 fcl fx 22 fcl fx 28 fol fx 24 Fs os os f r frem omme foren reve sour rose Ls fe fee enn ann osu serie ziwe orrez o a o me fawn asm aus Lana Des a o por ee tzez sanz 305He Jon am Den aa 1 e ee Jeun asine Ian Jaen eum Tea BZOE90 Buzzer port output control Disables buzzer port output Enables buzzer port
190. tronics office in your country to obtain a list of authorized representatives and distributors They will verify e Device availability e Ordering information e Product release schedule e Availability of related technical literature e Development environment specifications for example specifications for third party tools and components host computers power plugs AC supply voltages and so forth e Network requirements In addition trademarks registered trademarks export restrictions and other legal issues may also vary from country to country GLOBAL SUPPORT http www necel com en support support html NEC Electronics America Inc U S NEC Electronics Europe GmbH NEC Electronics Hong Kong Ltd Santa Clara California Duesseldorf Germany Hong Kong Tel 408 588 6000 Tel 0211 65030 Tel 2886 9318 800 366 9782 Sucursal en Espa a NEC Electronics Hong Kong Ltd Madrid Spain Seoul Branch Tel 091 504 27 87 Seoul Korea Tel 02 558 3737 e Succursale Francaise V lizy Villacoublay France NEC Electronics Shanghai Ltd Tel 01 30 67 58 00 Shanghai P R China Gs Tel 021 5888 5400 Filiale Italiana Milano Italy NEC Electronics Taiwan Ltd Tel 02 66 75 41 Taipei Taiwan Branch The Netherlands ere Eindhoven The Netherlands Tel 040 265 40 10 NEC Electronics Singapore Pte Ltd Novena Square Singapore e Tyskland Filial Tel 6253 8311 Taeby Sweden Tel 08 63 87 200 United Kingdom Bra
191. ty detection SL20 CL20 PS200 PS201 Stop bit detection INTSR20 INTCSI20 Transmit Receive data counter 4 Start bit TF detection Receive clock CSIE20 Reception enabled and receive clock control Baudrate CSIE20 generator CSCK20 fx 2 to fx 2 Detection clock Reception detected ss20 P28 O gt SCK20 P20 O ASCK20 TPS203 TPS202 TPS201 TPS200 Clock phase C CSCK20 Internal clock output Baud rate generator control control register 20 BRGC20 External clock input Internal bus Note See Figure 9 2 for the configuration of the baud rate generator OG 39VJH3lNI TVIHIS 6 YUALdVHO ankAerakosv in ENUEN Sesa LL Figure 9 2 Block Diagram of Baud Rate Generator 20 Reception detection clock Transmit shift clock Receive shift clock Selector T Selector 1 2 Transmit clock counter 3 bits TXE20 Do RXE20 Receive clock counter 3 bits n 2 o 9 o e CSIE20 71 Reception detected B fx 2 fx 2 fx 23 fx 2 fx 25 fx 28 fx 27 fx 28 ASCK20 SCK20 P20 TPS203 TPS202 TPS201 Baud rate generator control register 20 BRGC20 Internal bus TPS200 OG 39V34831NI 1VIH3S 6 YILAVHO 1 2 3 4 5 118 CHAPT
192. uipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster Systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems life support systems and medical equipment for life support etc The quality grade of NEC Electronics products is Standard unless otherwise expressly specified in NEC Electronics data sheets or data books etc If customers wish to use NEC Electronics products in applications not intended by NEC Electronics they must contact an NEC Electronics sales representative in advance to determine NEC Electronics willingness to support a given application Note 1 NEC Electronics as used in this statement means NEC Electronics Corporation and also includes its majority owned subsidiaries 2 NEC Electronics products means any product developed or manufactured by or for NEC Electronics as defined above M8E 02 11 1 4 Users Manual U14801EJ3V1UD Regional Information Some information contained in this document may vary from country to country Before using any NEC Electronics product in your application please contact the NEC Elec
193. ulation instruction the error one cycle after the timer has been started may exceed one clock To use 8 bit timer event counter 80 as an external event counter therefore make the settings in the above sequence Figure 7 5 External Event Counter Operation Timing with Rising Edge Specified nepnmu f LE LI LI LIL by ULI LEU LT LT 1 TM80 count value 00H XotH oeH XosH X 04H Kos X N 1 N XOOH KotH X 02H X 03H X INTTM80 Remark N 00H to FFH User s Manual U14801EJ3V1UD 103 CHAPTER 7 8 BIT TIMER EVENT COUNTER 80 7 4 3 Operation as square wave output 8 bit timer event counter 80 can generate square wave output of an arbitrary frequency at an interval specified by the count value preset in 8 bit compare register 80 CR80 To use 8 bit timer event counter 80 for square wave output settings must be made in the following sequence lt 1 gt Set P27 to output mode PM27 0 Set the output latch of P27 to O lt 2 gt Disable operation of 8 bit timer counter 80 TM80 TCE80 0 lt 3 gt Set a count clock for 8 bit timer event counter 80 see Table 7 5 enable output of TO80 TOE80 1 and disable PWM output PWME80 0 4 Set a count value in CR80 5 Enable the operation of TM80 TCE80 1 When the count value of 8 bit timer counter 80 TM80 matches the value set in CR80 the TO80 pin output will be inverted Through application of this mechanism square waves of any frequency can be outpu
194. ull up resistor option register 0 PUO Pull up resistor option register O PUO sets whether an on chip pull up resistor is used for ports 0 1 and 3 For ports specified by PUO to use on chip pull up resistors pull up resistors can be internally used only for the bits set to input mode No on chip pull up resistors can be used for the bits set to output mode regardless of the setting of PUO On chip pull up resistors also cannot be used when the pins are used as the alternate function output pins PUO is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears PUO to 00H Figure 4 10 Format of Pull up Resistor Option Register 0 lt 0 gt Address After reset R W Pm on chip pull up resistor selection m 0 1 3 o On chip pull up resistor is not used On chip pull up resistor is used Caution Bits 2 and 4 to 7 must all be set to 0 User s Manual U14801EJ3V1UD CHAPTER 4 PORT FUNCTIONS 3 Pull up resistor option register B2 PUB2 This register specifies whether the on chip pull up resistor connected to each pin of port 2 is used The pins for which use of an on chip pull up resistor is specified by PUB2 can use a pull up register internally regardless of the setting of the port mode register PUB2 is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears PUB2 to 00H Figure 4 11 Format of Pull up Resistor Option Register B2 Symbol 7 0 Address After reset R W l
195. vnnnnsnrnnnnenennrenennnnnnenvnnene 87 8 bit compare register ET 98 16 bit compare register 90 nti tpe erre ER an e et eet dern Ete ee Ee 84 Serial operation mode register 20 119 Interrupt request flag register d EE 154 Interrupt request flag register EE 154 External interrupt mode register 0 156 Interrupt mask flag register EE 155 Interrupt mask flag register 1 TT 155 Oscillation stabilization time selection register srrrrvrrrnnrnnnvrnnnnrnnnvrnnnnnnnnnrnnnnnnnnnrnesnrnnnnenernrnsnvnnennn 166 ROMO detent ela ee ee N SA 64 Port EE EE 65 POM liar a oa en daa E Se EE eege ng 66 Port 3L BERI ea SERENA UNI dti UE UMS 70 Processor clock control register aeaa a E a aa a aa ee a aaa i Ae ta aie 76 Port mode register O Port mode register 1 Port mode register 2 Port mode register 3 Pull up resistor option register O EE 72 Pull up resistor option register EE 73 Receive buffer register Oia iia 118 16 bit capture register 90 oir ia 84 8 bittimer Counter 80 certe ete a Aris derre Ana 98 16 bit timer counter 90 teca poe reete deena nerd ca ee eg a RS 84 8 bit timer mode control register 0 99 User s Manual U14801EJ3V1UD 235 TMC90 TXS20 W WDCS WDTM 236 APPENDIX C REGISTER INDEX 16 bit timer mode control register OU 85 Transmission shittregister 20 ET 118 Watchdog timer clock selection regieter AA 111 Watchdog timer mode register srernnnvnnenvnnvnnnvnnvnnnnnnvnrnrnnnnennvnr
196. where the interrupt request that has released standby mode is acknowledged 2 The wait time is as follows e When vectored interrupt servicing is performed 9 to 10 clocks e When vectored interrupt servicing is not performed 1 to 2 clocks User s Manual U14801EJ3V1UD 167 CHAPTER 11 STANDBY FUNCTION b Releasing by non maskable interrupt request HALT mode is released regardless of whether interrupts are enabled or disabled and vectored interrupt servicing is performed c Releasing by RESET input When HALT mode is released by the RESET signal execution branches to the reset vector address in the same manner as the ordinary reset operation and program execution starts Figure 11 3 Releasing HALT Mode by RESET Input HALT NES instruction Wait 219 fx Note RESET signal Oscillation Operating Reset stabilization Operating mode HALT mode period wait status mode gt E Oscillation Se Clock Oscillation MM stop die Oscillation Note 3 28 ms at fx 10 0 MHz operation 6 55 ms at fx 2 5 0 MHz operation Remark fx System clock oscillation frequency Table 11 2 Operation After Releasing HALT Mode mms E A cenas x memesurma Non maskable interrupt request ERT Executes interrupt servicing RESET input Po Reset processing x Don t care 168 User s Manual U14801EJ3V1UD CHAPTER 11 STANDBY FUNCTION 11 2 2 STOP mode 1 Setting and operation status o
197. xample MOV A FEO0H When setting addr16 to FEOOH Instruction code 0 0 1 0 1 0 0 1 OP Code 0 0 0 0 0 0 0 0 00H 1 1 1 1 1 1 1 0 FEH Illustration OP code addr16 low addr16 high Memory 56 User s Manual U14801EJ3V1UD CHAPTER 3 CPU ARCHITECTURE 3 4 2 Short direct addressing Function The memory to be manipulated in the fixed space is directly addressed with the 8 bit data in an instruction word The fixed space where this addressing is applied is the 256 byte space FE20H to FF1FH An internal high speed RAM is mapped at FE20H to FEFFH and the special function registers SFR are mapped at FFOOH to FF1FH The SFR area where short direct addressing is applied FFOOH to FF1FH is a part of the total SFR area In this area ports which are frequently accessed in a program and a compare register of the timer counter are mapped and these SFRs can be manipulated with a small number of bytes and clocks When 8 bit immediate data is at 20H to FFH bit 8 of an effective address is set to 0 When it is at OOH to 1FH bit 8 is set to 1 See Illustration below Operand format Label or FE20H to FF1FH immediate data Label or FE20H to FF1FH immediate data even address only Description example MOV FE90H 50H When setting saddr to FE90H and the immediate data to 50H Instruction code 1 1 1 1 0 1 0 1 OP code 1 0 0 1 0 0 0 O 90H saddr offset 0 1 0 1 0 0 0 0 50H immediate data
198. xceed one clock To use 8 bit timer event counter 80 as a PWM output therefore make the settings in the above sequence Figure 7 7 PWM Output Timing cuneo UUUUUUUUUUUUUUUUUU OVF INTTM80 TO80Note M 01H to FFH Note The initial value of TO80 is low when output is enabled TOE80 1 Caution Do not set CR80 to 00H in PWM output mode otherwise PWM may not be output normally 106 User s Manual U14801EJ3V1UD CHAPTER 7 8 BIT TIMER EVENT COUNTER 80 7 5 Notes on Using 8 Bit Timer Event Counter 80 1 Error on starting timer An error of up to 1 clock is included in the time between when the timer is started and a match signal is generated This is because 8 bit timer counter 80 TM80 is started asynchronously to the count pulse Figure 7 8 Start Timing of 8 Bit Timer Counter 80 TM80 00H 01H 02H 03H 04H count value Timer start 2 Setting of 8 bit compare register 80 8 bit compare register 80 CR80 can be set to 00H Therefore one pulse can be counted when 8 bit timer event counter 80 operates as an event counter Figure 7 9 External Event Counter Operation Timing CR80 00H TM80 count value Interrupt request flag Cautions 1 Before rewriting CR80 in timer counter operation mode PWMESO bit 6 of 8 bit timer mode control register 80 TMC80 0 stop the timer operation If CR80 is rewritten while the timer operation is enabled a match interrupt request signal may be gene

uPD789074 Subseries 8-Bit Single-Chip Microcontrollers UD

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