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MIP405 USERS MANUAL - MPI Distribution AG

1. a ma p00 m en ma i H H If Se o S1 Switch H D HEDDDDE DD a BDO DEER ER D S2 Switch D EDD H ED ul HE Gi DI EH m w em vm vm ooo 1 We H Figure 3 1 2 Parts location Bottom view MIP405 2003 by MPL AG 10 MEH 10085 001 Rev G High Tech Made in Switzerland 3 2 Switch settings Default switch settings are bold 3 2 1 DIP switch S1 Soft
2. MEH 10085 001 Rev G High Tech Made in Switzerland 4 6 Interrupts 4 6 1 CPU Interrupts The PPC405 provides 7 Interrupts They are distributed as follows CPU IRQ IRQ Source Source INTR PIIX Interrupt Controller COMA_INT COMB_INT SMI and NMI PCI_INTA PCI_INTB PCI_INTC PCI_INTD PCI Bus USB Table 4 6 1 CPU Interrupts Note e The 3 Interrupts from the EPLD are routed as follows INTR is the inverted INTR Signal form the PIIX Interrupt Controller COM_INT0 and COM_INT1 are the pulsed Interrupt signals from the DUART NMI is the inverted NMI Signal from the PIIX SMI is the PIIX SMI Signal 4 6 2 ISA Interrupts The ISA Interrupts are routed as follows Device Remarks Timer PIIX Internal not available Free 2 IRQ Controller PIIX Internal not available Free Free Free Free Free RTC PIIX Internal not available Free Free Free Free Free Primary IDE Not Maskable Secondary IDE Not Maskable Table 4 6 2 ISA Interrupts 2003 by MPL AG 26 MEH 10085 001 Rev G Hgh ech e Made i in eege 4 7 Extension registers The PLD is located at the CS7 on the peripheral local bus The bit notations are in big Endian Format That is DO MSB D7 LSB EXT REG Read only Config Register COM_MODE Read Write Communication Mode Register IRQ_REG Read only IRQ Register BOARD_REV Read only Board Revision and populated Configurati
3. 1211 J13 100 10MBit Network Connector z J10 PC104 D4 PCI Connector D3 ED D Q P lt O N O gt w CH CH H IS J12 100 10MBit Network Connector 10 M 0000 TED ami i J16 Secondary co IDE Port 0 i III J15 Primary IDE Port Wi O000 000 00000 0000 O0O000 000 0000 0000 COC COOO0CCOO 000000 OM D ema H H H DRDDDD DEER ERD H HERE H 001I DD 1000111000 HR oo D HEEHERCH d ke on J14 USB Connector gj ii in E EI B H GME DOADA 19 Q J8 J11 PC104 Connector J9 Power Connector Figure 3 1 1 Parts location Top view 9 MEH 10085 001 Rev G High Tech Made in Switzerland 3 1 2 Bottom view
4. 115200 1 MCR 7 0 460800 11 0592 MHz 11 064 MHz 172800 691200 12 MHz 12 002 MHz 187500 750000 18 432 MHz 18 435 MHz 288000 1152000 22 1184 MHz 22 114 MHz 345600 1382400 24 MHz 23 996 MHz 375000 1500000 36 864 MHz 36 869 MHz 576000 2304000 lololo o oj o o o o o lo o Ni on a lwin o 40 MHz 39 992 MHz Table 4 5 1 Baudrate Clocks The Baudrate is calculated according the following formula BaudRate InputClock 16 Divisor If the bit7 in the MCR of the 16C550 is set the baudrate is divided by 4 Following tables shows the divisors for the most common baudrates for all baudrate clocks No 2 12 002MHz Ge No 0 7 3977MHz No 1 11 064MHz Rate MCR 7 1 MCR 7 0 MCR 7 1 MCR 7 0 MCR7 1 div K div K div div K div 625000 MCR 7 0 div 2500000 No 3 18 435MHz MCR 7 1 div Table 4 5 2 Baudrate for Configuration 0 to 3 2003 by MPL AG 24 MEH 10085 001 Rev G No 5 23 996 MHz MCR 7 1 div MCR 7 0 div No 6 36 869 MHz div 0 00 11522 No 7 39 992 MHz MCR 7 0 div 2003 by MPL AG Table 4 5 3 Baudrate for Configuration 4 to 7 25
5. if bit ULED in Register COM_Mode is set Table 3 3 1 Indicators 2003 by MPL AG 11 MEH 10085 001 Rev G High Tech Made in Switzerland 3 4 Connectors 3 4 1 J1 Serial port SERO connector The serial port SERO is implemented as RS232 full Modem Handshake interface For reference the pin numbering on a DB9 male connector has been included Number Sianal_ Description DB9 male 2 DSRO Datasetready _ Ip 6 cTS0 Cleartosend 8 RIO Ring indicator GND Ground 5 EARTH Shield Table 3 4 1 J1 Serial port SERO connector 3 4 2 J2 Serial port COMA connector The serial port COMA is implemented as a full Modem Handshake interface with TTL level signaling Number Sianal Descriotion _ Pinot O 6 CTSA Cleartosend __ _ _ RIA Ring indicator GND Ground VCC5 5V power supply Table 3 4 2 J2 Serial port COMA connector 3 4 3 J3 Debug JTAG connector The Debug JTAG Connector uses a non standard Pinout on a 12Pin 2mm Header Siana TI Desertegpon Pintott CPU TDI CPU JTAG Data In CPU_TRST CPU JTAG Reset CPU_TCK CPU JTAG Clock CPU TMS CPU JTAG Mode Select CPU HALT CPU Halt PLD TDI PLD JTAG Data In 10 PLD TDO PLD JTAG Data Out 11 PLD TMS PLD JTAG Mode Select 2 1 PLD TCK PLD JTAG Clock Table 3 4 3 J3 Debug JTAG connector 2003 by MPL AG 12 MEH 10085 001 Rev G High Tech Made in Switzerland 3 4 4 J4 Serial
6. port SER1 connector The serial port SER1 is implemented as RS232 Interface Since the PPC405 supports only CTS RTS or DSR DTR hardware handshake others hardware handshake signals are not available To switch between the CTS RTS to DSR DTR handshake set the bit SER1_ALT in the COM_MODE register clear the Bit DCS and set the bit RDS in the Register CHCRO of the PPC405 For reference the pin numbering on a DB9 male connector has been included Number Sianal__ Description DB9 male 2 DSRi Datasetready 6 6 CTS1 Cleartosend 8 o Fenm feom lz GND __ Ground 5 Table 3 4 4 J4 Serial port SER1 connector 3 4 5 J5 Serial port COMB connector The serial port COMB is implemented as a full Modem Handshake interface with TTL level signaling Sianal Descriotion Pneu TXDB Transmit data CTSB Clear to send 7 DTRB Data terminal ready RIB Ring indicator GND Ground 10 VCC5_ 5V power supply Table 3 4 5 J5 Serial port COMB connector 3 4 6 J6 Speaker SMBus connector For system expansions the System Management Bus SMBus some General Purpose In Output Signals along with the speaker signals are available on the connector J6 Sianal TI Descriotion pnem _ __ _ General Purpose Output 28 VCC5 5V power supply for the Speaker 10 Table 3 4 6 J6 Speaker SMBus connector Notes All the Signals on the J6 are connected to the SouthBridge PIIX4E 82371EB So the General Purpose Inputs Outputs ar
7. sensible static discharge can be sufficient to destroy or degrade a component s operation 1 5 Equipment safety Great care is taken by MPL that all its products are thoroughly and rigorously tested before leaving the factory to ensure that they are fully operational and conform to specification However no matter how reliable a product there is always the remote possibility that a defect may occur The occurrence of a defect on this device may under certain conditions cause a defect to occur in adjoining and or connected equipment It is the user s responsibility to ensure that adequate protection for such equipment is incorporated when installing this device MPL accepts no responsibility whatsoever for such kind of defects however caused 2003 by MPL AG 4 MEH 10085 001 Rev G High Tech Made in Switzerland 2 General information and specifications This chapter provides a general overview over the MIP405 and its features It outlines the electrical and physical specifications of the product its power requirements and a list of related publications 2 1 Specifications 2 1 1 Electrical Processor e IBM PPC405GP PPC405GPr PowerPC 32Bit RISC Processor e Separate configurable two way set associative instruction 16 kByte and data 8 16 kByte cache units e Clock frequency 266 400 MHz e Very low power consumption Bootloader ROM e Upto 4 8MB Flash EEPROM e 512kB U Boot open source boot loader e Easy boot loade
8. to 5V Please consult the documentation of your debug tool for the correct wiring e NC means Do not Connect 2003 by MPL AG 29 MEH 10085 001 Rev G High Tech Made in Switzerland 7 Support information 7 1 MPL AG In case of questions contact MPL AG or your local distributor MPL AG homepage www mpl ch Email address support mopl ch 7 2 Production serial and revision number To get the actual production revision number of your device please see the label on MIP405 Board MPL MIP405 1 S N 100 A Production Production Serial Number Revision Number 2003 by MPL AG 30 MEH 10085 001 Rev G High Tech Made in Switzerland This page is left blank intentionally 2003 by MPL AG 31 MEH 10085 001 Rev G High Tech Made in Switzerland Copyright and revision history Copyright 2003 by MPL AG Elektronik Unternehmen All rights reserved Reproduction of this document in part or whole by any means is prohibited without written permission from MPL AG Elektronik Unternehmen This manual reflects Revision C of the MIP405 Disclaimer The information contained herein is believed to be accurate as of the date of this publication however MPL AG will not be liable for any damages including indirect or consequential arising out of the application or use of any product circuit or software described herein MPL AG reserves the right to make changes to any product herein to improve reliability funct
9. 104 and PC 104 Plus interface Came Ot eed fees feed Fees Drees 2001 by MPL AG 1 MEH 10085 001 Rev G High Tech Made in Switzerland INTRODUCTION About this manual MIP405 Variants Safety precautions and handling Electrostatic discharge ESD protection Equipment safety 2 GENERAL INFORMATION AND SPECIFICATIONS 2 1 Specifications 2 1 1 Electrical 2 1 2 Physical Power 2 1 3 Environment 2 2 Dimensions 3 PREPARATION FOR USE 3 1 Parts location 3 1 1 Top view 3 1 2 Bottom view 2 Switch settings 3 2 1 DIP switch S1 Software Configuration switch 3 2 2 DIP switch S2 Hardware Configuration Switch 3 3 Indicators 3 4 Connectors 3 4 1 J1 Serial port SERO connector 3 4 2 J2 Serial port COMA connector 3 4 3 J3 Debug JTAG connector 3 4 4 J4 Serial port SER1 connector 3 4 5 J5 Serial port COMB connector 3 4 6 J6 Speaker SMBus connector 3 4 6 1 Connecting an external Reset Switch 3 4 7 J8 J11 PC104 interface pin numbers 3 4 8 J10 PC104 Interface pin numbers 3 4 9 J12 10 100BASETX RJ45 Connector only for Variants with Ethernet on RJ45 3 4 10 J13 10 100BASETX Header Connector only for Variants with Ethernet on Header 3 4 11 J14 USB Connector 3 4 12 E IDE connectors 3 4 12 1 J23 Standard E IDE connector 3 5 U4 Multi purpose socket 3 5 1 Mounting Memory Modules 3 5 2 Switch settings for the Multi Purpose Socket 3 5 3 Required module properties 3 5 4 Device types Examples for th
10. 2 2V Am27C080 AMD 2 0V DIL32 8MBit EPROM 4MBit EPROM 4MBit EPROM 8MBit ERROM Table 3 5 2 Device Types for MPS Note e Since the MIP405 delivers no 12V Vpp only the 4MBit AMD Flash is erasable and writeable on Board All other Flash types are read only e For the Disk On Chip use Mode 3 3 5 5 External bootloader It is also possible to boot from the MPS The device containing the bootloader must be stuffed on the MPS and the switch S2 must be set according the 3 5 2 Switch settings for the Multi Purpose Socket If the Switch S2 5 is switched on the PPC405 will boot out of the MPS please refer to3 2 2 DIP switch S2 Hardware Configuration Switch This feature is useful if a boot flash update has failed 2003 by MPL AG 20 MEH 10085 001 Rev G Hg h ech Made in Switzerland 4 Operation 4 1 Block diagram 16550 Serial 2 amp 3 compatible DUART Flash Up to 8MByte Multi Purpose Socket Up to 4MBit SRAM Serial Connector 2mm Header Peripheral Bus RS232 e Interface Serial 0 Up to 128MByte SDRAM with ECC soldered on Board PowerPC PPC405GP up to 266MHz or PPC405GPr RJ45 up to 400MHz Ge 100MBit PHY 2mm Header RS232 n Interface Serial 1 PC 104 Connector PCI Part PCI Bus 44 pin Flat Cable 2mm Connector 2mm Connector 44 pin Flat Cable Southbridge PIIX4E PC 1 04 Connector 82371EB USB Channel 0 ISA Part USB Connec
11. ER Units mm OOOOC0COOOOOODOOOo0o H DOOR a ma 85 1 DD DD D DDR H 000I PRPRER P HDD pp mp rgpgrgnnnpe pn HD WH H DH EP 8 00 0000 9 9 Power supply plug is only used if not powered via the PC104 Connector Figure 2 2 1 Dimensions MIP405 Drawing not to scale Since the PC104 Plus of the MIP405 is implemented as PCI Host the MIP405 is not a stack through board Please see Chapter 5 Module Stack for further information 2003 by MPL AG 8 MEH 10085 001 Rev G High Tech Made in Switzerland 3 Preparation for use 3 1 Parts location 3 1 1 Top view J1 SERO Connector J4 SER1 Connector J2 COMA Connector J5 COMB Connector J3 Debug JTAG Connector J6 Speaker SMBus Connector U4 Multi Purpose Socket 2003 by MPL AG
12. MPL Industrial PC with IBM PowerPC Processor The MIP405 is a highly integrated industrial single board computer in PC 104 form factor Build around the PPC405 IBM PowerPC Processor it is well suited for applications requiring small size high performance and Low Power The MIP405 can be used in a standard operating environment without the necessity of a fan All major components required to build a industrial PC system are implemented on a single PC 104 sized board It features two E IDE one 10 100Base TX Ethernet two USB Ports four serial ports speaker output and a real time clock The 16 bit PC 104 and the PC 104 PCI interface offers easy and flexible expansion capabilities Integration of the MIP405 into a system is facilitated by the fact of offering standard connectors E IDE 44 pin header and LAN 2mm 12pin header or RJ45 The serial interfaces can be accessed through 2mm 10pin headers Particular precaution has been taken to the EMC so that an entire system can fulfill the CE and FCC requirements The SDRAM is soldered on board and is available with ECC All these features make the MIP405 to the ideal solution for any low cost embedded control application where a flexible industrial PC is needed Features Low Power IBM PPC405 Processor 2 USB Ports Processor clock 266 400 MHz Two EIDE HDD ports Up to 128MByte ECC SDRAM on board Four RS232 ports Integrated 10 100 Mbit s Ethernet Controller Low power consumption PC
13. all the same length Since the MIP405 is the PCI Host in the PC104 Plus stack the MIP405 compensate the clock length differences for all PCI devices as specified by the PCI and the PC104 Plus Specification Therefore the MIP405 must be the most bottom module That is why the MIP405 is equipped with non Stack Through connectors If the MIP405 is used within a PC104 Plus stack please pay attention to following points The MIP405 must be the most bottom Module If other PC 104 Plus Modules are used they must be the next in order All PC104 Plus Modules must have a different slot address refer to the documentation of the PC104 Plus Module for more information The slot address of the module directly on the top of the MIP405 must be 0 the following must be 1 etc Please note that the Modules with the slot address 3 and 4 cannot both be bus masters If PC104 Modules are also used they have to be placed above the PC104 Plus stack 6 Debug Cable for MIP405 To connect the MIP405 to an IBM RISCWatch or similar Debuging Tools an atapter cable must be made Please use the following wiring MIP405 J3 RISCWatch Connector 12pin 2mm Header female 16pin 2 54mm Header female Pin Number Signal Pin Number 1 5V see Note 6 16 Notes e Pin 3 of the MIP405 J3 Connector is hardwired to 5V IBM recommends to connect it either to 3 3V or 5V via an 1K resistor For some debug tools eg OCDemon RAVEN it must be hardwired
14. cted Speaker e Available on a 10 pin 2mm header Indicators Power LED green Reset Power Fail LED red Error LED red HDD activity LED green LAN LED green 1 user programmable LED green 2003 by MPL AG 6 MEH 10085 001 Rev G High Tech Made in Switzerland 2 1 2 Physical Power Form factor PC 104 with connectors in defined I O connectors overhang regions Length 95 9 mm 3 775 inches Width 115 6 mm 4 550 inches Height 14 0 mm 0 550 inch excluding PC 104 bus connectors Weight Typical 110g fully equipped without memory module Power supply Over PC 104 bus interface or through separate 3 pin Mini Combicon power connector Input Power requirement 5V 5VDC 5 Power consumption PPC405GP 266MHz Typical 8300mA 5V with Ethernet USB and 128MB SDRAM PPC405GPr 400MHz Typical 0OmA S5V with Ethernet USB and 128MB SDRAM 2 1 3 Environment Temperature range 0 C to 60 C 32 F to 140 F 266 400 MHz CPU speed without heat sink extended temperature range available Relative humidity 10 90 non condensing 2003 by MPL AG 7 MEH 10085 001 Rev G High Tech Made in Switzerland 2 2 Dimensions aS I m A DH IT P
15. e 4 7 6 IRQ Register INTR Interrupt from PIIX Low Active Will be forwarded to the PPC405 on INTO C_INTO Interrupt 0 from DUART Low Active Will be forwarded as pulsed IRQ to the PPC405 on INT1 C_INT1 Interrupt 1 from DUART Low Active Will be forwarded as pulsed IRQ to the PPC405 on INT1 SMI System Management Interrupt from PIIX Low Active Will be forwarded to the PPC405 on INT2 INIT Init Output from PIIX Low Active Will be forwarded to the PPC405 on INT2 NMI Non maskable Interrupt from PIIX Low Active Will be forwarded to the PPC405 on INT2 Note C_INTO and C_INT1 will be forwarded to the PPC405 as pulsed IRQ 4 7 5 Communication Mode Register COM MODE PLD_CS 0x04 Read Write ae aar SCHERER RE SS o o o o Table 4 7 7 communication Mode Register SER1ALT Alternate SER1 Hardware Handshake If set the SER1 uses DTR DSR Handshaking instead of CTS RTS If this Bit is set clear the Bit DCS and set the bit RDS in the Register CHCRO of the PPC405 Sx Binary encoded value for the baudrate of the DUART and the clock on the UARTSERCLK Input of the PPC405GP See chapter 4 5 1 Baudrate Clock for details ULED If set the User LED is switched on IDERST Reset of the IDE Port If set the IDE Reset is asserted Low 2003 by MPL AG 28 MEH 10085 001 Rev G MPL High Tech Made in Switzerland 5 Module Stack The clock signals of the PCI devices on the PC104 Plus must have
16. e Multi Purpose Socket ceccceeeeeeeeeeeeeeeeeeeeeeeeeeeeeseeeeeeeeseaeeseeeestaeeeeeeeaees 20 3 5 5 External bootloader 4 OPERATION 4 1 Block diagram 4 2 Memory Map 4 2 1 PPC405 System Mapping 4 3 MIP405 Memory Mapping 4 4 Local bus to PCI Mapping 4 5 DUART Operation 4 5 1 Baudrate Clock 4 6 Interrupts 4 6 1 CPU Interrupts 4 6 2 ISA Interrupts 4 7 Extension registers 4 7 1 PLD Partnumber Register 4 7 2 PLD Version Register 4 7 3 Board Revision and Config Register 4 7 4 IRQ Register 4 7 5 Communication Mode Register 3 2003 by MPL AG 2 MEH 10085 001 Rev G High Tech Made in Switzerland 5 MODULE STACK 6 DEBUG CABLE FOR MIP405 7 SUPPORT INFORMATION 7 1 MPL AG 7 2 Production serial and revision number 2003 by MPL AG 3 MEH 10085 001 Rev G High Tech Made in Switzerland 1 Introduction 1 1 About this manual This manual assists the installation and initialization procedure by providing all hardware related information necessary to handle and configure the MIP405 For all bootloader related information please refer to the U Boot User Manual for MPL SBC MEH 10082 002 supplied by MPL AG or your local MIP405 supplier The U Boot User Manual for MPL SBC is also available on the internet under htto www mpl ch in PDF format The manual is written for technical personnel responsible for integrating the MIP405 into their system 1 2 MIP405 Variants Since the MIP405 is availabl
17. e in various population options the information in this Manual about Memory size Processor speed etc may vary with your MIP405 The table below lists the actual as of July 2003 variants for an actual table please consult http www mpl ch Variants CPU SDRAM Flash Ethernet Temperature Range MIP405 1 PPC405GP 266MHz 128MByte ECC 4MByte RJ45 0 C 60 C MIP405 2 PPC405GP 266MHz 64MByte ECC 4MByte Header 40 C 85 C MIP405 3 PPC405GPr 400MHz 128MByte ECC 8MByte Header 0 C 60 C MIP405 4 PPC405GP 266MHz 128MByte ECC 4MByte Header 0 C 60 C Table 1 2 1 MIP405 Variants Note Not all of the variants may be available Please consult for http Awww mpl ch available variants 1 3 Safety precautions and handling For personal safety and safe operation of the MIP405 follow all safety procedures described here and in other sections of the manual Power must be removed from the system before installing or removing the MIP405 to prevent the possibility of personal injury electrical shock and or damage to the product Handle the product carefully i e dropping or mishandling the MIP405 can cause damage to assemblies and components Do not expose the equipment to moisture WARNING There are no user serviceable componenis on the MIP405 1 4 Electrostatic discharge ESD protection Various electrical components within the product are sensitive to static and electrostatic discharge ESD Even a non
18. e the GPIO of the PIIX4E and not of the CPU The names of the GPIOs correspond with the names of the ones of the PIIX4E The Speaker Signal is the buffered Output open drain to the SPRK Signal of the PIIX4E which is driven by the Counter 2 of the PIIX4E For further information please refer to the SouthBridge Manual 2003 by MPL AG 13 MEH 10085 001 Rev G High Tech Made in Switzerland J9 Power Connector This connector is needed if no power via PC104 bus is provided No other inputs than this and the power inputs on PC104 bus must be used to power the board 3 pin power connector Phoenix Contact AG type MC1 5 3 G 3 81 pinout Pin number Description Vin Input voltage 5 Voc GND Ground SRESET System Reset Input active low Table 3 4 7 J9 Power connector Counterpart is the Phoenix Contact AG connector type MC1 5 3 ST 3 81 5 10A WARNING Be aware of the input voltage polarization Wrong polarization of the input voltage can cause serious damage to the MIP405 and attached peripherals 3 4 6 1 Connecting an external Reset Switch On the SRESET input on the External Power Connector exists the possibility to mount an external Reset Switch for system reset see Figure 3 3 The SRESET input is active low and can be connected directly to an open drain output internal 10kQ pull up resistor to 3 3V J Reset Button IN Figure 3 3 Mounting an External Reset Switch WARNING Do not appl
19. flash size the start address may vary 4 4 Local bus to PCI Mapping The CPU internal PLB to PCI bridge maps the 4 local bus areas to 4 PCI areas The U Boot sets following local bus to PCI memory mapping Local Bus PCI MemoryAddress Size Start End Start End PCI Memory Area 1 80000000 9FFFFFFF 80000000 QFFFFFFF 512MB Free for expansions cards PCI Memory Area 2__ A0000000 BFFFFFFF 00000000 OOFFFFFF_ 16MB___ ISA Memory hard wired Table 4 4 1 Local bus to PCI Memory Mapping The local bus to PCI I O mapping is initialized as follows Local Bus Start End Area Notes PCI UO Address Start End E8000000 E800FFFF 00000000 OOOOFFFF E8800000 EBFFFFFF 00800000 O3FFFFFF Table 4 4 2 Local bus to PCI I O Mapping The local bus address has to be added to access a device on the PCI bus For example to access the registers of the first IDE port ISA UO 0x1F0 you have to access the local address 0xE80001F0 Area PCI I O 1 PCI I O 2 Notes ISA I O hard wired PCI I O 2003 by MPL AG 23 MEH 10085 001 Rev G High Tech Made in Switzerland 4 5 DUART Operation The 16C550 is connected to the PPC405 peripheral bus on CS2 and CS3 4 5 1 Baudrate Clock The Baudrate Clock for the 16C550 is derived from the main clock generator With the bits SO S2 in the COM_MODE Register 8 different clocks can be selected Clock nom 7 3728 MHz Clock eff 7 3977 MHz Max Baud MCR 7
20. ion or design Trademarks Brand or product names are trademarks and registered trademarks of their respective holders Our local distributor 2003 by MPL AG 32 MEH 10085 001 Rev G
21. ith Ethernet on RJ45 Standard RJ45 Connector for a 100 Ohm Cable Pin number_ Sanel Description po Din Transmitdata po 2 TX Transmitdata Pp SCT Di Decke det pT NC __ Not connected 8 MG Notconected BL RX __ Receivedata Not connected BL NC Not connected Table 3 4 10 10 100Base TX connector 3 4 10 J13 10 100BASETX Header Connector only for Variants with Ethernet on Header 12Pin 2mm Header Number Sianal_ TL Desertegon ot Dr TransmitData 2 JD TransmitData 2 RXx Receive Data TERM1 Termination 1 RX Receive Data Loo T ne S 10 NC 11 EARTH Shield EARTH Shield Table 3 4 11 J13 10 100Base TX Header 3 4 11 J14 USB Connector The USB connector is a 10 pin 2mm pitch header It has the signals for two USB ports on it Pin number Descrintion Cable Power 5VDC Port Cable Power 5VDC Port2 Balanced Data Line Port Balanced Data Line Port2 Data1 Balanced Data Line Port1 Data2 Balanced Data Line Port2 GND Cable Ground Port1 GND Cable Ground Port2 NC Not connected NC Not connected Table 3 4 12 J14 USB connector 2003 by MPL AG 17 MEH 10085 001 Rev G High Tech Made in Switzerland 3 4 12 E IDE connectors There are two 44 pin header 2 mm pitch E IDE connectors on the MIP405 Physically each connector works as an independent IDE channel J15 is connected to the primary and J16 i
22. mory map are intended for use by ROM or Flash type devices While locating volatile SDRAM and SRAM in this region is supported by the controller it is not recommended that these regions be used for this purpose When the optional boot from PCI Memory is selected the PCI Boot ROM address space begins at FFFE 0000 size is 128KB 2003 by MPL AG 22 MEH 10085 001 Rev G High Tech Made in Switzerland 4 3 MIP405 Memory Mapping The mapping of the MIP405 is setup by the U Boot bootloader as follows Function SDRAM 00000000 7FFFFFFF depends on population PCI Memory Area 1 80000000 OFFFFFFF PCI Memory Area 2 A0000000 BFFFFFFF PCI I O 1 E8000000 E800FFFF PCI I O 2 E8800000 EBFFFFFF see 4 4 Local bus to PCI Mapping Extensions Register CS7 External UARTO CS2 F4000000 F4100000 F40FFFFFF F41FFFFF External UART1 CS3 F4200000 F42FFFFF see 4 7 Extension registers see 4 5 DUART Operation MPS CS1 F8000000 F83FFFFF see 3 5 U4 Multi purpose socket FFC00000 FFFFFFFF Flash CS0 depends on population Table 4 3 1 MIP405 Mapping Notes e The PPC405 is setup with the values of Start End and Size If the connected device may not use the entire Area So the external UARTO uses only 8Byte not 1MByte e Since the PPC405 fetches its reset vector from address FFFFFFFC the flash has to end on FFFFFFFF Depending on the
23. on PLD_VERS Read only Versions Number of the PLDs PLD_PART Read only Part Number of the PLDs Table 4 7 1 Extensions Registers 4 7 1 PLD Partnumber Register PLD PART PLD_CS 0x00 Read Only ea Low Di D2 DB ea EE D6 D7 MIPID PLD Part Number Defaut o 0 0 pf SE E CECR Table 4 7 2 PLD Partnumber register PLD Part Number is the Part Index of the PLD This is currently 00 4 7 2 PLD Version Register PLD VERS PLD_CS 0x01 Read SES SES eS ESE SSS ESS SSeS Read PLD a Number Defaut Oo 0 Zo 4 a 3 PLD Version lt PLD Version Number is the Version Number of the PLD This is currently 0x01 4 7 3 Board Revision and Config Register BOARD_REV PLD_CS 0x02 Read Only E Ee D7 PCB2 Defaut Oo 0 0 Po XX XX Table 4 7 4 Board Revision and Config Register Binary decoded PCB Revision Add an ASCII A to this number to get the PCB Revision Currently PCB3 0 0010 gt C Config Inputs Used to distinguish different population or other Options Connected to VCC or GND via Config Resistors Currently following populations Options are valid Variants MIP405 1 MIP405 2 MIP405 4 MIP405 3 only prototypes MIP405 3 Table 4 7 5 Config bits 2003 by MPL AG 27 MEH 10085 001 Rev G High Tech Made in Switzerland 4 7 4 IRQ Register IRQ REG PLD_CS 0x03 Read Only EE DB D4 D D6 D7 C_INT1 Dean 1 17 Tt SE WE ooa ee Tabl
24. ossible Pin mappings DIL32 1MBit SRAM DIL32 4MBit SRAM DIL32 2MBit Flash bulk DIL32 4MBit Flash sector DIL32 2MBit EPROM default DIL32 8MBit EPROM Table 3 5 1 MPS configuration 3 5 3 Required module properties 5V only types 8 bit data width TTL compatible signaling Access time should not exceed 250ns 32 pin 600 mil wide DIL case MPS compatible pin out refer to Table 3 5 1 MPS configuration Since the MIP405 delivers only 3 3V max 12mA VPP Flash programming may not be possible with some Devices 2003 by MPL AG 19 MEH 10085 001 Rev G High Tech Made in Switzerland 3 5 4 Device types Examples for the Multi Purpose Socket Configuration No Type No Manufacturer Vin DIL32 1MBit SRAM E 1MBit SRAM 5V 62C1024L ISSI 2 2V 1MBit SRAM 5V KM681000C KM684000 Samsung 2 2V Samsung 2 2V DIL32 4MBit SRAM 4MBit SRAM 4MBit nonVolatile SRAM DS1250Y AB Dallas 2 2V DIL32 2MBit Flash bulk 2MBit Flash Bulk Erase 12V P28F020 1MBit Flash Bulk Erase 12V P28F010 2MBit Flash Bulk Erase 12V Am28F020 1MBit Flash Bulk Erase 12V Am28F010 DIL32 Disc On Chip 2 DoC 2000 Millenium M Systems 2 0V DIL32 4MBit Flash sector 3 4MBit Flash Sector Erase 5V Only Am29F040 AMD 2 0V DIL32 2MBit EPROM EN 2MBit EPROM Am27C020 AMD 2 0V 1MBit EPROM HN27C101AG Am27C040 Hitachi 2 2V AMD 2 0V NH27C4001G Hitachi
25. r update Memory e upto 128MByte SDRAM on board e ECC Support Multi Purpose Socket e Supports different SRAM FLASH EPROM 32 Pin DIL memory components e Memory sizes up to 2MByte EPROM RTC e Backed with onboard battery e Year 2000 compliant PC 104 Plus Interface e ISA bridge Intel 82371EB Southbridge e 16 Bit PC 104 interface e 32 Bit PC 104 Plus Interface PCI Host 2003 by MPL AG 5 MEH 10085 001 Rev G High Tech Made in Switzerland USB e 2USB 1 0 ports for serial transfers at 12 or 1 5 Mbit s e ESD protected Serial ports Four serial Ports 16C550 compatible Two serial ports with RS232 signaling SERO and SER1 Two serial port with TTL signaling COMA and COMB Standard transfer rates up to 460 kBaud Optional transfer rates up to 1 15 MBaud 3 ports with full modem handshake SERO COMA and COMB Available on four 10pin 2mm headers E IDE ports e 2 separate channels for up to 4 drives available on 44 pin header 2 mm pitch for 2 5 Notebook hard disk PIO Mode 4 and Bus Master IDE transfers up to 14 Mbytes s Ultra DMA 33 mode synchronous DMA mode transfers up to 33 Mbytes s Activity indicator on board Ethernet PPC405GP PPC405GPr integrated 10 100 MBit s Ethernet Controller IEEE802 3 10BASE T and 100BASE TX compatible IEEE 802 3u Autonegotiation Support IEEE 802 3x 100BASE TX Flow Control support Activity indicators for link detection network traffic and 100 Mbit s operation on board ESD prote
26. s connected to the secondary port 3 4 12 1 J23 Standard E IDE connector Pin Sianal_ Desertoon Sianal Description Di Databitz 4 ID Databt8 O D6 Databit6 D9 Deag D5 DatabitS D D i Data bit 11 D e D D Data bit 1 G l l i l D A A RDY R 7 5 DO Databito DRQ HOR 31 IRQ interruptrequest Table 3 4 13 EIDE connectors Pin 3 2003 by MPL AG 18 MEH 10085 001 Rev G High Tech Made in Switzerland 3 5 U4 Multi purpose socket The Multi Purpose Socket allows to add various Memory devices to the MIP405 e SRAM with or without Battery backup up to 4MBit 512kByte e Flash bulk or sector erase up to 4MBit 512kByte e EPROM ROM up to 8MBit 1MByte e Disk On Chip As a special feature the MIP405 allows to boot directly from the MPS 3 5 1 Mounting Memory Modules When selecting a component for the MPS please check out first if the pin out is compatible with one of the pin configuration modes refer to Table 3 5 1 MPS configuration When mounting a Memory Device on the socket remind the markers on the socket and the module for pin 1 marker O o O e O O O O ie O O O fe O bel O bel O ei o O o O fe O O O O O OD fe Figure 3 5 1 Multi Purpose Socket mounting 3 5 2 Switch settings for the Multi Purpose Socket With the DIP switch S2 6 to S2 8 the Pins of the MPS are configurable The following Table shows all p
27. tor 2mm Header USB Channel 1 Power Supply Power Reset Module Connector Battery Figure 4 1 1 MIP405 Block Diagram 2003 by MPL AG 21 MEH 10085 001 Rev G High Tech Made in Switzerland 4 2 Memory Map 4 2 1 PPC405 System Mapping Function Sub Function Start End Local Memory Peripherals 1 00000000 7FFFFFFF Total 80000000 EF5FFFFF PCI Memory 80000000 E7FFFFFF PCI I O E8000000 E800FFFF Reserved E8010000 E87FFFFF PCI I O E8800000 EBFFFFFF Reserved EC000000 EEBFFFFF PCI Configuration Registers EEC00000 EEC00007 Reserved EEC00008 EECFFFFF PCI Interrupt Acknowledge EEDO0000 EEDFFFFF Reserved EEE00000 EF3FFFFF PCI local Configuration Registers EF400000 EF40003F Reserved EF400040 EF5FFFFF Total EF600000 EFFFFFFF UARTO EF600300 EF600307 Reserved EF600308 EF6003FF UART1 EF600400 EF600407 Reserved EF600408 EF6004FF IC EF600500 EF60051F Internal Peripherals Reserved EF600520 EF6005FF OPB Arbiter EF600600 EF60063F Reserved EF600640 EF6006FF GPIO Controller Registers EF600700 EF60077F Reserved EF600780 EF6007FF Ethernet Controller Registers EF600800 EF6008FF Reserved EF600900 EFFFFFFF Expansion ROM 2 F0000000 FFDFFFFF 254MB Boot ROM 2 3 FFE00000 FFFFFFFF 2MB Table 4 2 1 PPC405 System Mapping Notes The Local Memory Peripheral area of the memory map can be configured for SDRAM ROM or Peripherals The Boot ROM and Expansion ROM area of the me
28. ware Configuration switch The Software configuration switch is readable by reading the register EXT_REG Environment Console assignment from Console is serial line 1 not yet defined not yet defined not yet defined not yet defined not yet defined not yet defined not yet defined not yet defined not yet defined not yet defined not yet defined not yet defined not yet defined not yet defined Table 3 2 1 S1 Software Configuration Switch Notes e A switch in ON Position will be read back as High 3 2 2 DIP switch S2 Hardware Configuration Switch Battery backup enabled Battery backup disabled Boot Flash VPP enabled Boot Flash VPP disabled Boot Flash Write protected Boot Flash Write enabled EEPROM Write enabled EEPROM Write protected Boot from MPS Boot from Boot Flash MPS CFGO Off MPS CFG1 Off MPS CFG2 On Table 3 2 2 S2 Hardware Configuration Switch Notes e Boot Flash VPP and WP works only with some Boot flash Devices e Switch S2 6 to S2 8 are used to configure the device used on the MPS Refer to 3 5 U4 Multi purpose socket for details 3 3 Indicators Description Lit when 5V is Ok D8 Power S E D7 Reset Lit when PPC405 is in Reset D6 Error Lit when PPC405 has detected an Error eee Sys_Error D4 LAN D3 User Lit when IDE activity Lit when Network activity Lit
29. y other voltages than Vin or tristate to the SRESET input Exceeding these limits can cause serious damage to the MIP405 2003 by MPL AG 14 MEH 10085 001 Rev G High Tech Made in Switzerland 3 4 7 J8 J11 PC104 interface pin numbers Number RowA RowB oe tenon 1 MOCHCK GND____ SBHE_ MEMCS16 _ 2 b7 RSTDRV__ La23 og D A e E S e D SD1 ENDXFR__ LA17 __ DACKO 9 sbo p HA men brao 20 saii L ck LI at saio Up ti E 22 sa9 Up LI y E 23 sas IRQS Zi saz Ro de de l 25 sas IRQS 26 sas backe ri a Jsa RE de E 28 Ja BAE J P29 SAR 30 SAV OSC 31 SAO Loun Li y Ef 32 enb Ion d d Table 3 4 8 PC 104 connector Signal not available 5V 12V and 12V are not connected and MASTER is pulled down to GND 2003 by MPL AG 15 MEH 10085 001 Rev G High Tech Made in Switzerland 3 4 8 J10 PC104 Interface pin numbers RowB RowC_ RowD pmou LB J22 LGE IA 33v H JSEDD Ion SBOP PAR Table 3 4 9 J10 PC 104 Plus connector Signal not available SBO SDONE and LOCK are pull up to 5V M66EN is connected to GND and 12V and 12V are not connected 3 3V pins are connected to a plane but due to Power supply constrains they are not connected to the 3 3V of the Power Supply 2003 by MPL AG 16 MEH 10085 001 Rev G High Tech Made in Switzerland 3 4 9 J12 10 100BASETX RJ45 Connector only for Variants w

MIP405 USERS MANUAL - MPI Distribution AG

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