SH7450 Group, SH7451 Group User`s Manual Hardware Errata Rev. B
Contents
1. 40 01 or 11 CAN operaion mode bus off state CAN halt mode CANM 10 1 CANM SLPM BOM RBOC Bits in the CiCTLR register Notes 1 The transition timing from the bus off state to CAN halt mode depends on the setting of the BOM bit When the BOM bit is 01 the state transition timing is immediately after entering the bus off state When the BOM bit is 10 the state transition timing is at the end of the bus off state When the BOM bit is 11 the state transition timing is at the setting of the CANM bit to 10 CAN halt mode 2 Write to the SLPM bit in CAN reset mode or CAN halt mode When rewriting the SLPM bit set only this bit to 0 or 1 3 The CAN module does not enter CAN halt mode while the CAN bus is locked in dominant state Enter CAN reset mode instead Re Page 9 of 12 lt ENESAS RENESAS TECHNICAL UPDATE TN SH7 A874A E Date October 1 2013 Table 26 9 Operation in CAN Reset Mode and CAN Halt Mode Incorrect description is corrected Error Mode Receiver Transmitter Bus Off CAN reset mode CAN module enters CAN CAN module enters CAN CAN module enters CAN reset mode forcible reset mode without waiting for reset mode without waiting for without waiting for the end of bus off transition the end of message the end of message recovery CANM 11 reception transmission CAN reset mode CAN module enters CAN CAN module enters CAN CAN module enters CAN reset mode CAN2. After the bit is set to 1 redetection takes place under either of the following conditions e After this bit is set to 0 from 1 recessive bits are detected e After this bit is set to 0 from 1 the CAN module enters CAN reset mode or CAN halt mode and then enters CAN operation mode again 26 3 20 en P g 0 No bus lock detected 1 Bus lock detected CANi Error Interrupt Factor Judge Regist CIEIFR Correction i 0 to 4 Bit Abbreviation Reset Description 7 BLIF 0 Bus Lock Detect Flag The BLIF bit is set to 1 if 32 consecutive dominant bits are detected on the CAN bus while the CAN module is in CAN operation mode After the bit is set to 1 bus lock can be detected again after either of the following conditions is satisfied e After this bit is set to 0 from 1 recessive bits are detected bus lock is resolved e After this bit is set to 0 from 1 the CAN module enters CAN reset mode and then enters CAN operation mode again internal reset 0 No bus lock detected 1 Bus lock detected Re Page 8 of 12 lt ENESAS RENESAS TECHNICAL UPDATE TN SH7 A874A E Date October 1 2013 Contents Figure 26 9 Transition between CAN Operating Modes i 0 to 4 Incorrect description is corrected Error CPU reset CANM 01 or 11 when SLPM 0 CAN sleep mode Bo CAN reset mode CAN operaion mode SLPM 1 2 CANM 01 or 11 When BOM is 00 or 11
3. DMA transfer request masked state to the DMA transfer request enabled state when DEC counter operation is enabled DRIIDECNCNT DECnEN bit 1 Do not rewrite from the DMA transfer request enabled state to the DMA transfer request masked state when DEC counter operation is enabled Re Page 11 of 12 lt ENESAS RENESAS TECHNICAL UPDATE TN SH7 A874A E Date October 1 2013 Added in Rev B Added in Rev B Added in Rev B Added in Rev B 28 27 32 13 32 139 32 145 28 3 12 DRIO DMA Transfer Enable Register DRIOTRMDEN 32 4 1 FlexRay Operation Control Register FXROC 32 12 5 Configuration of NIT Start and Offset Correction Start Table 32 8 State Transitions of FlexRay overall state Machine 28 3 12 DRIO DMA Transfer Enable Register DRIOTRMDEN Incorrect description is corrected Error Controls the enabled disabled states for DRIO transfer related DMA transfer requests If one of these bits is set to 1 the corresponding DMA transfer request signal output is enabled If a DMA transfer mask disable is set at the same time as an internal DMA transfer request the DMA transfer mask disable takes precedence Also note that when DRI acquisition is enabled DRIIDCAPCNT DCPEN bit 1 the DRIOTRMDEN register may only be rewritten from the transfer masked state to the transfer enabled state Do not rewrite any bits in this register from the transfer enabled state to the Controls
4. 0000 to H FD9F FFFF when the user boot MAT is selected An access command is issued to an address other than ROM program erase addresses H FD80 0000 to H FD80 7FFF when the user boot MAT is selected Figure 12 8 Command State Transitions in ROM Read Mode and P E Mode Incorrect description is corrected Error FENTRY H 0001 Correction or FENTRY H 0002 When set from Command the access miss state locked Command miss FENTRY H 0000 or access MISS H 50 Status register clear ROM P E mode command input wait Correction ROM read mode FENTRYR H 0001 or FENTRYR H 0002 When set from Command the access miss state locked Command miss FENTRYR H 0000 or access MISS H 50 Status register clear ROM P E mode command input wait Description of Reset during Programming or Erasure is added Description When a hardware reset by L level input to the RESET pin switching the ower off or a FCU reset by setting the FRESET bit in the FRESETR register is executed during programming or erasure the whole data in the programming or erasure area becomes undefined When the data in an area have become undefined erase the area before using it again Re Page 4 of 12 lt ENESAS RENESAS TECHNICAL UPDATE TN SH7 A874A E Date October 1 2013 Rev Part Contents Description of the bit 5 MOIFE bit in the RSPIi Pin Control Register SPiIPCR is corrected Error When the MOIFE bit
5. is cleared to 0 RSPIi outputs on the MOSIli pin the last data unit from the previous serial transfer during the SSL Added 24 3 3 NEAN period in 24 9 RSPIi Pin Rev B Control Register Correction When the MOIFE bit is cleared to 0 0 RSPIi outputs the final output l SPIPCR level of the previous serial transfer to the MOSIi pin during the SSL negation period When the CPHA bit is 0 MOSIi output value is undefined 0 MOSIi output value equals final output level from previous transfer When the CPHA bit is 0 MOSIi output value is undefined Description of the bit 13 SPNDEN bit in the RSPIi Command Registers 0 to 3 24 3 13 SPiCMDO to SPiCMD3 is corrected oc Error If the SPNDEN bit is 0 the RSPIi sets the next access delay to 1 Added RSPli Command RSPCK in 24 24 Registers 0 to 3 RENGE a 9 Correction if the SPNDEN bit is 0 the RSPli sets the next access delay to 1 RSPCK 2 Pck 0 Anext access delay of 1 RSPCK 2 Pck Table 24 7 MOSIi Signal Value Determination during SSL Negation Period Incorrect description is corrected Error MOIFE MOIFV MOSli Signal Value during SSL Negation Period Final data from previous transfer Table 24 7 Always j Added MOSIi Signal Always H i Value in 24 28 OE Determination an Rev B during SSL Correction g MOIFE MOIFV MOSIli Signal Value during SSL Negation Period Negation Period Laua 0 0 4 Final output level of the previous transfer When the i CPH
6. the enabled disabled states for DRIO transfer related DMA transfer requests If one of these bits is set to 1 the corresponding DMA transfer request signal output is enabled If a DMA transfer mask disable is set at the same time as an internal DMA transfer request the DMA transfer mask disable takes precedence Also note that when DRI acquisition is enabled DRIIDCAPCNT DCPEN bit 1 the DRIOTRMDEN register may only be rewritten from the DMA transfer request masked state to the DMA transfer request enabled state Do not rewrite any bits in this register from the DMA transfer request enabled state to the DMA transfer request masked state when DRI acquisition is enabled Description of the bit 2 FBSEN bit in the FlexRay Operation Control Register FXROC is corrected FRNVMn Correction Correction FRNMVn FRNMVn 32 12 5 Configuration of NIT Start and Offset Correction Start Incorrect description is corrected For the FlexRay module the offset correction start is required to be the OCS bit in the FRGTUC4 register o the NIT bit int the Correction For the FlexRay module the offset correction start is required to be the OCS bit in the FRGTUC4 register gt the NIT bit in the FRGTUC4 register 1 k 1 Table 32 8 State Transitions of FlexRay overall state Machine Incorrect description is corrected To DEFALT CONFIG CONFIG From All states DEFALT CONFIG Condition Hard reset Command CONFIG bits CMD3 to CMDO i
7. 3 4 when DRI acquisition is enabled DRIIDCAPCNT DCPEN bit 1 Added DRIODIN DMA Do not rewrite from the transfer enabled state to the transfer In 28 16 Transfer Enable Rev B Register Correction Also note that it is only possible to rewrite the DRIODINDEN register DRIODINDEN bits from the DMA transfer request masked state to the DMA transfer request enabled state when DRI acquisition is enabled DRIIDCAPCNT DCPEN bit 1 Do not rewrite from the DMA transfer request enabled state to the DMA transfer request masked state when DRI acquisition is enabled 28 3 8 DRIODEC DMA Transfer Enable Register DRIODECDEN Incorrect description is corrected Error If a DMA transfer request mask disable setting and an internal DMA transfer request occur at the same time the DMA transfer request mask disable setting takes precedence Also note that it is only possible to rewrite the DRIODECDEN register bits from the transfer masked state to the transfer enabled state when DEC 28 3 8 counter operation is enabled DRIIDECnCNT DECnEN bit 1 Do Added DRIODEC DMA not rewrite from the transfer enabled state to the transfer masked In 28 21 Transfer Enable Rev B Register Correction If a DMA transfer request mask disable setting and an internal DRIODECDEN DMA transfer request occur at the same time the DMA transfer request mask disable setting takes precedence Also note that it is only possible to rewrite the DRIODECDEN register bits from the
8. A bit is 0 MOSIi output value is undefined 1 0 Always L 1 1 Always H Figure 24 11 RSPI Transfer Format CPHA 0 Incorrect description is corrected Error Serial transfer period RSPCKi CPOL 0 os i cry gt LILFLILILU LULL oa CPOL 1 i Sampling timing Figure 24 11 AROG RSPI Transfer in 24 34 Format Rev B CPHA 0 RSPCKi CPOL 0 mess LPLPLPLr ppp CPOL 1 i Sampling i i i timing MISO CD an an aD a a OD ER x_ SSLi o 1 re Page 5 of 12 RENESAS TECHNICAL UPDATE TN SH7 A874A E Date October 1 2013 Figure 24 12 RSPI Transfer Format CPHA 1 Incorrect description is corrected Error Start Serial transfer period l RSPcki nanmnnnnnnannNn o CPOL 0 l Ao MN B a G p B a D pa yr py CPOL 1 3 Sampling i timing MOSli i MISO i Figure 24 12 o nore RSPI Transfer 3 in 24 34 i 7 Rev B Format l CPHA 1 RSPCKi LI LILILUILILI U CPOL 0 mess Uruna CPOL 1 3 Sampling timing MOSli st MISO i corrected Error Register Name Abbreviation P4 Address Size Page The values after reset of the CANi Clock Select Register CiCLKR i 0 to 4 are Added in 26 5 Rev B Table 26 3 Register Configuration CANO Clock Select Register CAN1 Clock Sea Register CAN2 Clock S Register CAN3
9. Clock Sd Register CAN4 Clock TE Register Correction Register Name CANO Clock Select Register CAN1 Clock Select Register CAN2 Clock Select Register CAN3 Clock Select Register CAN4 Clock Select Register COCLKR C1 CLKR COCLKR C3CLKR C4CLKR Abbreviation COCLKR C1 CLKR COCLKR C3CLKR C4CLKR tENESAS Reset Undefined Undefined Undefined Undefined Undefined H FFFF 6847 HEFEF 7847 HEFEF 6847 WEFEF 9847 H FFFF A847 P4 Address H FFFF 6847 H FFFF 7847 H FFFF 8847 H FFFF 9847 H FFFF A847 8 16 32 8 16 32 8 16 32 8 16 32 26 16 26 16 Page 6 of 12 RENESAS TECHNICAL UPDATE TN SH7 A874A E Date October 1 2013 Rev Part Contents The value after reset of the bit 4 in the CANi Clock Select Register CiICLKR i 0 to 4 is corrected Error Bit T 6 5 4 3 2 1 0 E z z 2 EEEE ccs After Reset 0 0 0 0 0 0 0 0 lt After Reset H 00 gt After Bit Abbreviation Reset R W Description 26 3 2 4 0 0 Reserved Bit Added CANi Clock Should be written with 0 and read as in 26 16 Select Register o Undefined tue Rev B CiICLKR Comccions a i O to 4 Bit T 6 5 4 3 2 1 0 cas After Reset 0 0 0 Undefined 0 0 0 0 lt After Reset Undefined gt After Bit Abbreviation Reset R W Description 4 Undefined 0 Reserved Bit Should be written with 0 and read as undefined value Setting value of the bit 7 to 0 CIRFPCR bit in the CANi
10. Date Oct 01 2013 RENESAS TECHNICAL UPDATE 1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan Renesas Electronics Corporation Product Document Category MPU MCU No TN SH7 A874A E Rev 1 00 l SH7450 Group SH7451 Group User s Manual Information fees Title Hardware Eiraan Rev Bb Category Technical Notification SH7450 Group SH7451 Group carers SH7450 Group SH7451 Group Reference User s Manual Hardware Rev 1 10 Document R91UH0286EJ0110 We inform you of the corrections of SH7450 Group SH7451 Group User s Manual Hardware Rev 1 10 Published on September 27 2011 When you use SH7450 Group SH7451 Group User s Manual Hardware Rev 1 10 should be used together the attached errata In addition the corrections in the following are also included in the attached errata Rev B Technical update TN SH7 A826A E Errata Rev A Technical update TN SH7 A859A E Errata to User s Manual Regarding CAN Module Attached document SH7450 Group SH7451 Group User s Manual Hardware Rev 1 10 Errata Rev B 11 sheets c 2013 Renesas Electronics Corporation All rights reserved Page 1 of 12 stEN ESAS RENESAS TECHNICAL UPDATE TN SH7 A874A E Date October 1 2013 Changes additions are written in reds and underlined Revision History Xili 26 3 14 CANi Status Register Revision History Description of CAN is added Page of Previous Edition 26 49 Description Descri
11. F bit in the CiEIFR register 3 If a CAN bus error occurs during reception after CAN halt mode is requested the CAN mode transits to CAN halt mode Table 26 9 4 If a CAN bus error or arbitration lost occurs during transmission after CAN reset mode or CAN halt mode is requested the CAN mode transits to the requested CAN mode Added Operation in fe Oe el in 26 74 CAN Reset Correction Rev B Mode and CAN Mode Receiver Transmitter Bus Off Halt Mode lt CAN reset mode CAN module enters CAN reset CAN module enters CAN reset CAN module enters CAN reset forcible transition mode without waiting for the mode without waiting for the end mode without waiting for the end rn end of message reception of message transmission of bus off recovery CANM 11 CAN reset mode CAN module enters CAN reset CAN module enters CAN reset CAN module enters CAN reset CANM 01 mode without waiting forthe mode after waiting for the end of mode without waiting for the end end of message reception message transmission of bus off recovery CAN halt mode CAN module enters CAN halt CAN module enters CAN halt When the BOM bit is 00 mode after waiting for mode after waiting for ery Of A halt request from a program of message reception message transmission will be acknowledged only after bus off recovery When the BOM bit is 01 CAN module enters automatically to CAN halt mode without waiting for the end of bus off recovery regar
12. M 01 reset mode without waiting for reset mode after waiting for without waiting for the end of bus off the end of message the end of message recovery reception transmission CAN halt mode CAN module enters CAN halt CAN module enters CAN halt When the BOM bit is 00 mode after waiting for the end mode after waiting for the end A halt request from a program will be of message reception of message transmission acknowledged only after bus off recovery When the BOM bit is 01 CAN module enters automatically to CAN halt mode without waiting for the end of bus off recovery regardless of a halt request from a program When the BOM bit is 10 CAN module enters automatically to CAN halt mode after waiting for the end of bus off recovery regardless of a halt request from a program When the BOM bit is 11 CAN module enters CAN halt mode without waiting for the end of bus off recovery if a halt is requested by a program during bus off Legend BOM bit Bit in CICTLR register i 0 to 4 Notes 1 If several messages are requested to be transmitted mode transition occurs after the completion of the first transmission In a case that the CAN reset mode is being requested during suspend transmission mode transition occurs when the bus is idle the next transmission ends or the CAN module becomes a receiver 2 If the CAN bus is locked at the dominant level the program can detect this state by monitoring the BLI
13. Receive FIFO Pointer Control Register CIRFPCR i 0 to 4 is corrected Error After ae Bit Abbreviation Reset Description Added ee 7to0 CiIRFPCR Undefined R The CPU side pointer for the receive in 26 42 FIFO Pointer FIFO is incremented by writing H FF Rev B Control Register l CIRFPCR Correction i 0 to 4 Bit Abbreviation Reset Description 7to0 CiIRFPCR Undefined The CPU side pointer for the receive FIFO is incremented by writing H FF Setting value of the bit 7 to O CiTFPCR bit in the CANi Transmit FIFO Pointer Control Register CiTFPCR i 0 to 4 is corrected Error After Aree it Bit Abbreviation Reset Description Added pede 7to0 CilFPCR Undefined The CPU side pointer for the transmit in 26 46 ae fe FIFO is incremented by writing H FF Rev B Control Register CITFPCR Correction i 0 to 4 Bit Abbreviation Reset Description 7to0O CIiTFPCR Undefined 4 The CPU side pointer for the transmit FIFO is incremented by writing H FF Re Page 7 of 12 lt ENESAS RENESAS TECHNICAL UPDATE TN SH7 A874A E Date October 1 2013 Rev Page Pat J Contents S O Description of the bit 7 BLIF bit in the CANi Error Interrupt Factor Judge Register CiEIFR i 0 to 4 is corrected Error After Bit Abbreviation Reset R W Description 7 BLIF 0 R W Bus Lock Detect Flag The BLIF bit is set to 1 if 32 consecutive dominant bits are detected on the CAN bus while the CAN module is in CAN operation mode
14. S RENESAS TECHNICAL UPDATE TN SH7 A874A E Date October 1 2013 28 3 Register Descriptions Incorrect description is corrected Error These flags are used to enable DMA transfer requests Set these flags to 1 to enable a DMA transfer request and set them to 0 to disable a request To prevent incorrect DMA operation only rewrite these bits from the DMA transfer masked state to the DMA transfer enabled state when DRI acquisition is enabled DRIIDCAPCNT DCPEN bit 1 Do not rewrite from the DMA transfer enabled state to the DMA transfer Added 283 masked state when DRI acquisition is enabled since that can result R a B aoa ie Correction These flags are used to enable DMA transfer requests Set these l flags to 1 to enable a DMA transfer request and set them to 0 to disable a DMA transfer request To prevent incorrect DMA operation only rewrite these bits from the DMA transfer request masked state to the DMA transfer request enabled state when DRI acquisition is enabled DRIIDCAPCNT DCPEN bit 1 Do not rewrite from the DMA transfer request enabled state to the DMA transfer request masked state when DRI acquisition is enabled since that can result in a DMA transfer request not being handled 28 3 4 DRIODIN DMA Transfer Enable Register DRIODINDEN Incorrect description is corrected Also note that it is only possible to rewrite the DRIODINDEN register bits from the transfer masked state to the transfer enabled state 28
15. dless of a halt request from a program When the BOM bit is 10 CAN module enters automatically to CAN halt mode after waiting for the end of bus off recovery regardless of a halt request from a program When the BOM bit is 11 CAN module enters CAN halt mode without waiting for the end of bus off recovery if a halt is requested by a program during bus off Notes 1 If several messages are requested to be transmitted mode transition occurs after the completion of the first transmission In a case that the CAN reset mode is being requested during suspend transmission mode transition occurs when the bus is idle the next transmission ends or the CAN module becomes a receiver 2 If the CAN bus is locked in dominant state the program can detect this state by monitoring the BLIF bit in the CiEIFR register The CAN module does not enter CAN halt mode while the CAN bus is locked in dominant state Enter CAN reset mode instead 3 If a CAN bus error occurs during reception after CAN halt mode is requested the CAN module enters CAN halt mode However the CAN module does not enter CAN halt mode when the CAN bus is locked in dominant state 4 Ifa CAN bus error or arbitration lost occurs during transmission after CAN reset mode or CAN halt mode is requested the CAN module enters the requested operating mode However the CAN module does not enter CAN halt mode when the CAN bus is locked in dominant state Page 10 of 12 RENESA
16. ected Error DIN2 to DIN4 sampling edge undefined time before DIN1 initialization level release when direct reset is selected DIN2 to DIN4 sampling edge undefined time before Added Man DIN1 initialization level in 38 38 A release Rev A When Special l Mode is On i DIN2 to DIN4 sampling edge undefined time before DIN1 initialization level release DIN2 to DIN4 sampling edge undefined time after DIN1 initialization level release Table 38 35 AUDR Module Timing PVcc 5 0 V Incorrect description is corrected Error item r 38 46 AUDR Module time before AUDRCLK BS Rev A Timing l PVcc 5 0 V Correction item AUDRD output ee d AUDRCLKH 35 time after AUDRCLK AUDRD Re Page 3 of 12 sKENESAS RENESAS TECHNICAL UPDATE TN SH7 A874A E Date October 1 2013 Contents 38 47 Table 38 36 AUDR Module Timing PVcc 3 3 V 12 3 2 Flash Access Status Register FASTAT Figure 12 8 Command State Transitions in ROM Read Mode and P E Mode 12 9 4 Reset during Programming or Erasure Table 38 36 AUDR Module Timing PVcc 3 3 V Incorrect description is corrected Error ltem Symbol Min Max Unit Figures time before AUDRCLK AUDRD Correction tem oo O Anoma Eae e a T m time after AUDRCLK ORD Description of the bit 7 ROMAE bit in the Flash Access Status Register FASTAT is corrected An access command is issued to an address other than ROM program erase addresses H FD80
17. n the FRSUCC1 register B 0001 DEFALT CONFIG Command CONFIG bits CMD3 to CMDO in the FRSUCC1 register B 0001 Correction Condition Hard reset Command CONFIG bits CMD3 to CMDO in the FRSUCC1 register B 0001 All states DEFAULT CONFIG DEFAULT CONFIG CONFIG Command CONFIG bits CMD3 to DEFAULT CONFIG CMDO in the FRSUCC1 register B 0001 Re Page 12 of 12 sLKENESAS
18. no halt request and 11 consecutive recessive bits are detected 128 times or RBOC is 1 CANM 10 when SLPM 0 CANM 01 or 11 CANM aa 0 SLPM 1 2 01 or 11 CAN operaion mode bus off state CAN halt mode CANM 10 CANM SLPM BOM RBOC Bits in the CiCTLR register Figu re 26 9 Notes 1 The transition timing from the bus off state to CAN halt mode depends on the setting of the BOM bit on j When the BOM bit is 01 the state transition timing is immediately after entering the bus off state Transition When the BOM bit is 10 the state transition timing is at the end of the bus off state Added between CAN When the BOM bit is 11 the state transition timing is at the setting of the CANM bit to 10 CAN halt mode in 26 72 2 Write to the SLPM bit in CAN reset mode or CAN halt mode When rewriting the SLPM bit set only this bit to 0 or 1 Operating tetra nse rere crete see tse sent eee nse ma Rev B 5 Correction l Modes l ae CPU reset i 0 to 4 CANM 01 or 11 when SLPM 0 CANM 00 CAN sleep mode 2 ee CAN reset mode CAN operaion mode SLPM 1 2 CANM 01 or 11 When the BOM is 00 or 11 no halt request and 11 consecutive recessive bits are detected 128 times or the RBOC is 1 CANM 10 when SLPM 0 CANM 01 or 11 CANM SLPM 1 2
19. ption of the bit 1 SDST bit in the CANi Status Register CiISTR i 0 to 4 is corrected The SDST bit is set to 1 when at least one SENTDATA bit in the CiMCTLj register is 1 regardless of the value of the CIMIER The SDST bit is set to 1 when at least one SENTDATA bit in the CiMCTLj j 32 to 63 register is 1 regardless of the value of the CiMIER register Page of Previous Edition 26 49 Description Description of the bit O NDST bit in the CANi Status Register CiISTR i 0 to 4 is corrected Correction The NDST bit is set to 1 when at least one NEWDATA bit in the CiMCTLj register is 1 regardless of the value of the CIMIER The NDST bit is set to 1 when at least one NEWDATA bit in the CiMCTL j 0 to 63 register is 1 regardless of the value of the CiMIER register Revision History Description of FlexRay is added Page of Previous Edition 32 17 Description Description of the bit 24 EDB bit in the FlexRay Error Interrupt Register FREIR is corrected Correction Added Revision Correction 0 No error detected on channel B l FlexRay Error TEE in History Interrupt Page of Previous Edition 32 18 Rev A XV Register Description Description of the bit 9 IIBA bit in the FlexRay Error Interrupt Register FREIR is corrected 0 No illegal CPU access to Output Buffer occurred Correction 0 No illegal CPU access to Input Buffer occurred 1 Illegal CPU access to Input Buffer occ
20. urred Revision History Description of Appendix A is added Page of Previous Edition A 1 Added Revision Appendix A Description in History CPU Operation Value after reset of the bit 5 RABD bit in the CPU Operation Mode Register Rev A Xvi Mode Register CPUOPM is revised z Value after reset of the RABD bit is 1 Correction Value after reset of the RABD bit is 0 Added 32 7 1 Description of the bit 29 to 24 PSL5 to PSLO bit in the FlexRay CC Status Vector in FlexRay CC Register FRCCSV is corrected Rev A Status Vector a Register Correction Set to B 000000 when leaving HALT state Table 38 26 RSPI Timing Incorrect description is corrected Error Z a a Table 38 26 setup time Rev A RSPS TMIN Correction Symbol Data input Slave tsu setup time Re Page 2 of 12 lt ENESAS RENESAS TECHNICAL UPDATE TN SH7 A874A E Date October 1 2013 Contents Figure 38 30 RSPI Timing Slave CPHA 0 Incorrect description is corrected O in a figure shows the added part Error SSL00 T n i G input aaa RSPCK2 d a Figure 38 30 MOSIO ia MOSI 4 Acded ange RSPI Timing td Rev A Slave i CPHA 0 Correction S500 k S510 i i S520 input RSPCKEO bo RSPEI j CPO O Input RSPCKO bo RSPCK2 CEPOL 1 input Im omm 4 ar 5 p or N wen D t MZB OUT DATA i LSB OUT A I utp i lor ur MOOSID to BOSIZ j Input Table 38 29 DRI Timing When Special Mode is On Incorrect description is corr
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