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LOGIC DESIGN

1. Notes 1 See Figure 2 to establish pulsed conditions 6 Derate above 81 C at 0 52 mA C 2 Derate above 46 C at 0 54 mA C 7 See Figure 9 to establish pulsed conditions 3 See Figure 7 to establish pulsed conditions 8 Derate above 39 C at 0 37 mA C 4 Derate above 53 C at 0 45 mA C 9 For operation below 20 C contact your local Agilent 5 See Figure 8 to establish pulsed conditions components sales office or an authorized distributor 168 Digital Logic Design Electrical Optical Characteristics at Ty 25 C AlGaAs Red EE IST DE Luminous Intensity Segmentl 12 5 Digit Average ciee ee eal VEG Dominant Wavelengthl3 2 Reverse Voltage Segment or DPIA1 Temperature Coefficient of Vp Segment or DP Thermal Resistance LED Junction to Pin Peak Wavelength Symbol Forward Voltage Segment or DP Vp V 20 3 Ip 100 mA High Efficiency Red Device Series HDSP Parameter Symbol Min Typ Max Units Test Conditions Ip 10 mA Luminous Intensity Segmentl 2 61 ued Digit Average Ip 60 mA Peak 1 of 6 df o i 626 0 Dominant Wavelengthl3l Reverse Voltage Segment or DPI4 7 Temperature Coefficient of Vp Segment or DP Thermal Resistance LED Junction to Pin 169 Khalil Ismailov Yellow Device Series HDSP Parameter Symbol Min Typ Max Units Test Conditions Luminous Intensity Segmentl 1 21 Digit Average 27 Ip
2. 4 P 4 Vu a DIGITAL LOGIC DESIGN Qafqaz University A l LABORATORY Ne gt E 9 10 E V 7 g Second Edition Qafqaz University Press Baki 20I10 Ministry of Education of a Educational Azerbaijan Republic Corporation Institute of Educational Qafqaz University Problems DIGITAL LOGIC DESIGN LABORATORY MANUAL Second Edition Khalil Ismailov Approved by the decision of the Scientific Methodical Commission s Informatics and Computer Technologies Section of the Ministry of Education of Azerbaijan Republic dated January 16 2007 minute No 01 Baku 2010 DIGITAL LOGIC DESIGN Prepared by Reviewed by Editor Design LABORATORY MANUAL Second Edition Kh A Ismailov Professor Department of Computer Engineering Qafqaz University T A Alizade PhD The Institute of Cybernetics of the National Academy of Sciences of Azerbaijan Republic S B Habibullaev Associate Professor Department of Computer Technologies and Programming Azerbaijan State Oil Academy A Z Melikov Professor Associate Member of the National Academy of Sciences of Azerbaijan Republic The Institute of Cybernetics of the National Academy of Sciences of Azerbaijan Republic Sahib Kazimov Is published as a Qafqaz University publication by the proposal of the Publishing Committee dated from 04 10 2006 minute No C QU 250 300 020 and decision of the Senate dated from 11 10
3. Using the parallel inputs to preset the counter set the toggle switches at the parallel inputs so the P3 P1 1 and P2 PO Oand pulse PL LOW The LEDs should now indicate 1010 Pulse the counter until the TCy output LED indicates 0 observing the output LEDs as you do so What sequence of numbers does the counter count Pulse counter one more time What is the count now 74193 IC operation as a mod 16 DOWN counter Disconnect the toggle switch from CPD and exchange it for the pushbutton switch at CPU and vice versa Disconnect the LED from TCy and reconnect it atTCp Clear the counter by pulsing MR HIGH momentarily Pulse the counter through its count sequence and record your observations in Table 10 3 96 Digital Logic Design Table 10 3 Test results for the 74193 IC DOWN counter Input pulse Output states Decimal applied Qs Qo Qi Qo number TC None 0 0 0 0 0 0 h Set the parallel input toggle switches to 1010 and pulse p LOW Note that TCp is now at 1 Pulse the counter until TCp indicates 0 observing the output LEDs as you do so What sequence of numbers does the counter count Pulse the counter one more time What is the count now 97 EXPERIMENT REGISTERS OBJECTIVES 1 Understand the general operation of register circuits 2 Design register circuits using D and J K flip flops 3 Underst
4. 1 Connect V and DC SET to 5 V GND to power ground 2 3 4 5 Connect toggle switches to J and K inputs Connect a normally LOW pushbutton switch to the clock input Connect a normally HIGH pushbutton switch to DC RESET Ls I TI Connect LED monitors to outputs Q and Q or use a logic probe to monitor the outputs Turn the power supply on and observe the states of Q andQ If Q 1 then pulse DC RESET momentarily LOW Note that this input clears the flip flop immediately without a clock signal and that the input is active LOW lI 74LS76 synchronous operation In this step you will observe that the J and K inputs can be used to change the output state of the flip flop You will also observe that in order for these inputs to effect a change a clock pulse must be applied For this reason the J K and CLK inputs are referred to as synchronous inputs Verify this by performing the following steps 1 Change the J and K input switch settings and observe that nothing happens to Q 2 SetJ 1 and K 1 and apply a positive going transition at CLK Do this by pressing and holding the CLK pushbutton switch What happens to Q 3 Repeat step 2 using a negative going transition at CLK Do this A releasing the pushbutton switch What happens to Q This proves that the flip flop responds to only negative going transitions Apply several more pulses to the CLK input What happens A If Q is LOW pulse the CLK inpu
5. 4 3 Y BD BD Y BD BD B D B4 D 4 3 LABORATORY ASSIGNMENTS Assignment 4 1 Construct the K map for the function given in Equation 4 4 Determine the minimized SOP expression and design the corresponding circuit using NAND gates Breadboard the circuit and measure its truth table to confirm correct operation Hint Find a SOP expression for the function by removing the parentheses before trying to map The circuit can be implemented with a single 7400 chip X A BC D x AC D 4 4 Assignment 4 2 Using the map constructed in Assignment 4 1 determine the minimized POS expression for the function of Equation 4 4 by complementing the minimized SOP expression for the function complement Build the corresponding circuit using NOR gates and measure its truth table to verify correct operation Hint The circuit can be implemented with a single 7402 chip Assignment 4 3 Find the minimized SOP expression for the function shown in Fig 4 5 a Construct the corresponding 2 level circuit using NAND gates and inverters Measure and record its truth table to verify correct operation Assignment 4 4 Determine both minimized SOP and POS expressions for the map shown in Fig 4 5 b There are two equally simple minimized expressions Design circuits to implement both expressions using only 2 input NAND gates and inverters 37 Khalil Ismailov Construct the simplest of these two circuits Measure and record its truth ta
6. 4 to 16 Line Decoder 4514 74259 8 Bit Addressable Latch 4099 4026 7 Segment Display Decade Counter 4033 4033 7 Segment Display Decade Counter 4026 4056 BCD to 7 Segment Decoder 7447 7448 4511 4099 8 Bit Addressable Latch 74259 4511 BCD to 7 Segment Decoder 7447 7448 4056 4514 4 to 16 Line Decoder 74154 Shift Registers Device Function Similar Devices 74161 8 Bit Shift Register 74164 4014 4015 74164 8 Bit Shift Register 74161 4014 4015 4014 8 Bit Shift Register 74161 74164 4015 4015 8 Bit Shift Register 74161 74164 4014 4021 8 Stage Shift Register 4094 4094 8 Stage Shift Register 4021 140 Digital Logic Design Computational Devices Device Function Similar Devices 7483 4 Bit Binary Full Adder 74283 7485 4 Bit Magnitude Comparator 4063 4585 74283 4 Bit Binary Full Adder 7483 4063 4 Bit Magnitude Comparator 7485 4585 4585 4 Bit Magnitude Comparator 7485 4063 Monostables and Multivibrators Device Function Similar Devices 74121 Monostable Multivibrator 74221 4098 4528 74221 Dual Monostable Multivibrator 74121 4098 4528 4047 Multivibrator 4538 4098 Dual Monostable Multivibrator 74121 74221 4528 4528 Dual Monostable Multivibrator 74121 74221 4098 4538 Multivibrator 4047 Comprehensive Cross Reference of 74xx and 155xx ICs IC Pins IC Function 7400 14
7. Here are some guidelines to help you perform the experiments and to submit the reports e Read all instructions carefully and carry them all out e Ask a demonstrator if you are unsure of anything e Record actual results comment on them if they are unexpected e Write up full and suitable conclusions for each experiment e f you have any doubt about the safety of any procedure contact the demonstrator beforehand e THINK about what you are doing Most experiments involve the use of the power supply the oscilloscope a signal generator the voltage measurement unit and your breadboard GENERATING DIGITAL SIGNALS FOR TESTING The most common type of signal needed to test logic circuits is a static signal that can be switched HIGH or LOW with a simple single throw SPST switch New students are often confused by how to do this correctly The problems involved and the solution are illustrated in Fig 0 1 The problem is illustrated in a which shows a logic circuit to be tested a 5 V power supply and a switch The logic circuit will be connected to the power supply and the switch should be used to provide a signal input voltage Vin to the circuit such that changing the switch position will change the signal input voltage between logic HIGH and LOW How should the switch be connected It cannot be connected directly across the supply since this would short the supply when it is closed An arrangement sometimes tried by new stu
8. Table 9 2 Determining the mod number of the counter Clock pulse CUP De 0 0 0 0 1 2 3 4 5 6 7 8 Assignment 9 3 a D Refer to the data sheet for the 7493 IC This IC contains four flip flops that may be arranged as a mod 16 ripple counter To do this Qo must be tied externally to CP The MSB of this counter is Qs and the LSB is Qo The counter s mod number may be changed by making the appropriate external connections 7493 IC operation Connect the circuit of Fig 9 5 Connect a normally HIGH pushbutton switch to input CP and LED monitors to outputs Qs through Q Pulse CPoand observe the counter sequence displayed on the LEDs It should be count from 0000 to 1111 and then recycle to 0000 Note that the NAND gate inputs MR and MR have no effect on the counter since they are both tied LOW 87 Khalil Ismailov d Disconnect the pushbutton switch at input CP Connect a square wave generator to this input and set the generator to 10 kHz Monitor the Q output with one vertical input of the oscilloscope and the generator output with the other input Set the horizontal sweep so that you can verify that there is one Q pulse for every 16 generator pulses Is the signal at Q a square wave f 10 kHz 16 625 kHz Fig 9 5 The 7493 IC counter Changing the 7493 mod number Disconnect the pulse generator from the counter and recon
9. e 74163 synchronous 4 bit counter pee carry in CI synchronous reset 9 preset These are synchronous counters so their outputs change precisely together reset and preset are both active low on each clock pulse This is helpful if preset is also known as parallel enable PE you need to connect their outputs to logic gates because it avoids the glitches which occur with ripple counters The count advances as the clock input becomes high on the rising edge The decade counters count from 0 to 9 0000 to 1001 in binary The 4 bit counters count from 0 to 15 0000 to 1111 in binary For normal operation counting the reset preset count enable and carry in inputs should all be high When count enable is low the clock input is ignored and counting stops The counter may be preset by placing the desired binary number on the inputs A D making the preset input low and applying a positive pulse to the clock input The inputs A D may be left unconnected if not required 154 Digital Logic Design The reset input is active low so it should be high Vs for normal operation counting When low it resets the count to zero 0000 QA QD low this happens immediately with the 74160 and 74161 standard reset but with the 74162 and 74163 synchronous reset the reset occurs on the rising edge of the clock input Counting to less than the maximum 15 or 9 can be achieved by connecting the appropriate output s through a NOT o
10. 160 Digital Logic Design 7447 BCD to 7 Segment LED Decoder 7448 BCD to 7 Segment Decoder B C Lt BI RBO RBI D A GND oO U B wW BO pr o Nol Vcc f 7474 Dual D Type Flip Flop RD D CP SD 7476 Dual J K Flip Flop CP1 SD1 RDL J1 Vec CP2 SD2 RD2 oO Aa B wW N FR mn 2 I n B w e 14 wW H N mn mn mn e Nol o Vcc RD2 D2 CP2 SD2 Q2 Q2 K1 Ql Q1 GND K2 Q2 Q2 J2 161 Khalil Ismailov 7483 4 Bit Full Adder With Fast Carry A4 Sum3 A3 B3 Sum2 B2 A2 Bo Rt 91 w Nol ws oy o B4 Sum4 G GND B1 Al Sumi 7493 4 Bit binary Ripple Counter CPI MR1 MR2 NC Vcc NC NC oO Aa R wW Ro t mn ws w H N mn HR mn e Nol o 7495 4 Bit Shift Register Ds DO D1 D2 D3 S GND ov u B w N j I mn ws mn wW j N mn H Cx Nol o CPO NCE Q0 03 GND Q1 Q2 VEG Q0 Ql Q2 Q3 CP1 CP2 162 Digital Logic Design 74138 3 Line to 8 Line Decoder AO Al A2 El E2 E3 7 GND 74139 Dual 4 Line Demultiplexer Ea A0a Ala 0a la 2a 3a GND Boo RF 91 w Nol ws D Bos u w w ws ov o 74151 Multiplexer I3 I2 Il I0 W ND I 92
11. D A 1 A cs A 0 A d A 1 1 5 OPERATIONS WITH A SINGLE VARIABLE a A A A b A A A c A A 20 d A 1 e A A 6 MULTIVARIABLE OPERATIONS a A AB A b A AB A B c A AB A B d A BXC D AC AD BC BD 7 DEMORGAN S THEOREMS When applying these equations to the simplification of a given logic circuit it is best to work your way from the inputs to the outputs developing simplified expressions for the intermediate points in the circuit This is especially important as circuits get more complicated If simplification is not done as the circuit is analyzed the expressions for the outputs are often so complicated that it is difficult to see the simplifying combinations Consider the circuit shown in Fig 2 1 as an example Note that intermediate points in the circuit have been labelled as p q r s t Logic expressions will be derived and simplified at these points as we work our way from inputs to the output X The process is outlined below 20 Digital Logic Design p A B q A A B AA AB AB r AB s BC t rs AB BC ABBC ABC X q t AB ABC B A AC B A AB BC Fig 2 1 Example circuit simplification A simplified circuit can now be drawn as shown in Fig 2 2 A Fig 2 2 Simplified circuit Note that the circuit of Fig 2 2 has 3 fewer gates than the original circuit An even simpler circuit could be realized if the parentheses had no
12. HIGH when activated L output from level detector LOW when at minimum F output from fume sensor HIGH when fumes present With these definitions the requirements statement above can be translated directly into the following equation P MF LF 3 1 A circuit could now be designed to realize this function It should be noted in the above equation that the L variable must be complemented since it is active low One of the greatest difficulties in trying to use a verbal description as the basis for design is insuring that the description is complete and accurate This is especially true as design requirements become more complex In many cases the best approach is to make an exhaustive list of the required output values for all possible combinations of the inputs i e to make a truth table for the required outputs Once the truth table is constructed it is easy to write a Boolean equation for the required outputs and design the circuits accordingly Table 3 1 shows the truth table constructed for the motor control problem described above This is easily obtained by analyzing each of the eight possible combinations of the input variables to determine the required value of the output Table 3 1 Motor control circuit truth table M L F P 0 0 0 1 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 0 28 Digital Logic Design Once the truth table has been dete
13. If you see a line drawn above a label it means it is active low for example reset say reset bar Here is a comprehensive cross reference of TTL and CMOS chips that are readily available Tables of both TTL and CMOS devices are provided along with tables grouping chips with the same functionality together 132 Digital Logic Design Logic ICs chips Logic ICs process digital signals and there are many devices including logic gates flip flops shift registers counters and display drivers They can be split into two groups according to their pin arrangements the 4000 series and the 74 series which consists of various families such as the 74HC 74HCT and 74LS For most new projects the 74HC family is the best choice The older 4000 series is the only family which works with a supply voltage of more than 6V The 74LS and 74HCT families require a 5V supply so they are not convenient for battery operation The table below summarises the important properties of the most popular logic families Property 4000 Series 74 Series 74 Series 74 Series 74HC 74HCT 74LS High High TTL Low Technology CMOS speed CMOS speed CMOS power P TTL compatible Schottky Power Supply 3 to 15 V 2to6V 5 V 0 5 V 5 V 0 25 V Very high mn Very high impedance Unused impedance us R inputs must be connected to Unused inputs OBlC II d Vs or 0 V Inputs cannot be must be unconnected Inputs reliably driven
14. inputs driven by the output Open inputs in TTL logic devices generally act as HIGHs causing inputs that are tied to open outputs to resemble a stuck HIGH input though not always Open CMOS inputs do not generally act as a HIGH or a LOW This being the case inputs tied to an open TTL or CMOS output will resemble a stuck LOW or stuck HIGH input or may even oscillate between HIGH and LOW Open inputs for ECL devices with inputs pulled down by a resistor are LOW Fig B 2 b illustrates an open output in a NAND gate Fig B 2 c shows an open input In the latter diagram the student should note that all signals before point A are unaffected Short between two pins Fig B 2 d shows two input pins shorted together This means that the outputs of the two driver gates are also shorted This condition will cause a fault in TTL and CMOS devices only if the two driver outputs try to go to opposite levels say X to HIGH and Y to LOW In this case if the device is TTL X will be stuck LOW In other words if one output is LOW both will be LOW However if the device is CMOS this condition typically produces an intermediate level see Fig B 3 There is obviously no fault which occurs when both outputs are supposed to be at the same level ECL device outputs can normally be connected together so no logic faults will occur unless the driver gates are damaged by excessive currents Vpp Output 1 Vpp Output 2 Shorted Vpp outputs 0 Vop
15. on the board 120 Digital Logic Design b At least two sections of holes with each section arranged so that the holes are in vertical groups called circuit blocks Each circuit block is isolated from all others This permits several wires to be joined at common junctions The two sections are separated by a horizontal gap This gap separates the sections electrically as well as physically Thus a vertical circuit block in the top section of the board is not connected to the block directly below it in the bottom section ICs will straddle this gap so that each IC pin will be inserted into its own block Connections to each pin will be brought to its block Installing ICs ICs should be installed or mounted on the board to permit wires going from the top section of the board to the bottom to go between the ICs It is not advisable to pass wires over ICs although sometimes it is hard to avoid Strapping ICs to the board in this manner will present problems if the IC has to be removed The consequences of this are obvious As you mount an IC check to make sure that none of its pins are being tucked beneath it If it is necessary to remove an IC always use an IC puller Never remove an IC with your fingers or with a pair of pliers The first causes a definite safety hazard while the second will often result in eventual damage to the IC Wiring the circuit Wires should be dressed so that 3 8 insulation is stripped from each end and the
16. this is done with a NAND gate Connect each of the TRUE term outputs of the demultiplexer in Fig 6 12 indicated by the summation equation to an input of the NAND gate Connect all unused NAND inputs to a logic 1 3 Fill in the column labeled Y of Table 6 6 with the anticipated output logic of the 1 to 8 demultiplexer NAND circuit configured to generate the function of above expression 60 Digital Logic Design Write the pin numbers on the designed circuit Place an 74138 7420 chip pair on a breadboard and assemble the connections to implement the completed circuit illustrated in Fig 6 12 Apply power to the circuit Vcc pin 16 GND pin 8 Stimulate inputs A B and C to complete the Y column of Table 6 6 74138 Fig 6 12 SOP expression implementation using 74138 DMUX circuit Table 6 6 Demultiplexer NAND circuit implementation table Inputs Demultiplexer NAND A B C output output 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 61 Khalil Ismailov In the space provided below draw the corresponding designed circuit and record the test results Assignment No Designed circuit Test results 62 gi oan ARITHMETIC CIRCUITS OBJECTIVES 1 Investigate the operation of a half and full adders 2 Design circuits using typical medium scale integrated arithmetic circuits EQUIPMENT REQUIRED Digital Logic Trainer Integrated circu
17. 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 f Draw the logic diagram for the simplified expression Assignment 2 2 a Examine the logic circuit in Fig 2 5 and write the Boolean expression for output X b Make a truth table for expression X using Table 2 2 c Construct the circuit of Fig 2 5 on the circuit board Connect toggle switches to inputs A B C and D Connect X to a TTL Logic Indicator d Verify the operation of your circuit by setting the toggle switches to each set of input values in Table 2 2 and comparing the outputs observed to the corresponding outputs in the table e In the space provided below simplify X using Boolean theorems List the theorem used in each step of the simplification 23 Khalil Ismailov Fig 2 5 Circuit for Assignment 2 2 Table 2 2 Output logic level at X for an original and simplified circuits four inputs Inputs Output Logic Level at X A B C D For an Original Circuit For a Simplified Circuit 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 f Draw the logic diagram for the simplified expression 24 Digital Logic Design Assignment 2 3 a Simplification using DeMorgan s theorems Draw a logic diagram for the expression F A BC 4 BC
18. 16 bit Random Access Memory K155PY3 7485 16 4 bit Magnitude Comparator K155CII1 7486 14 4 Dual Input XOR gate K155JIII5 7489 16 1 64 bit RAM open collector output K155PV2 7490 14 Decade Counter K155HE2 7491 14 8 bit Shift Register K155HP2 7492 Divide by 12 Counter K155HEA 7493 14 Divide by 16 Counter K155HE5 7495 14 4 bit Right Left Shift Register K155HP1 7496 5 bit Shift Register 7497 16 6 bit Rate Multiplier K155HE8 7498 4 bit Data Selector Storage Register K155HP5 74100 8 bit Bistable Latch K155TK7 74107 14 2 J K Flip Flop K155TB6 74109 16 2 J K Pos Flip Flop K155TB15 74112 16 2 J K Neg Flip Flop K155TB9 74113 14 2 J K edge Triggered Flip Flop w Preset K155TB10 74114 2 J K Neg Edge Flip Flop w Com Clk amp Clr K155TB11 74116 24 2 4 bit with clear latch 74120 16 2 Pulse Sync Driver 74121 14 Monostable Multivibrator K155AT 1 74122 Retriggerable Monostable Multivibrator 74123 16 Dual Reset Multivibrator K155AT3 74125 14 Quad Bus Buffer gate K155JIII8 74126 14 Quad Bus Buffer gate K155JIII14 74128 14 4 Dual Input Schmitt Trigger NOR Buffer K155JIE6 74132 14 4 Dual Input Schmitt Trigger NAND gate K155TJI3 74133 16 1 13 Input NAND gate 74134 16 1 12 Input NAND gate Tri State K155JIA 19 74135 16 4 XOR NOR gate 74136 e 4 XOR gate K155JIII12 74137 16 3 to 8 line Decoder Dmultiplexer 74138 16 Expandable 3 8 Decoder K155HJI7 74139 16 2 Expandable 2 4 Decoder K155HJI1
19. 2 dt The appropriate outputs a g become input C 4 output f low to display the BCD binary coded display test output g decimal number supplied on inputs A D The 7447 has open collector blank output 4 GPa outputs a g which can sink up to 40 blank input output b mA The 7 segment display segments input D 8 6 output c must be connected between Vs and the outputs with a resistor in series 330 Q with a 5 V supply A common anode display is required Display test and blank input are active low so a they should be high for normal operation When mn display test is low all the display segments should light showing number 8 f b g If the blank input is low the display will be blank when the count input is zero 0000 This can be EE used to blank leading zeros when there are several display digits driven by a chain of counters To achieve this blank output should be EA d connected to blank input of the next display down the chain the next most significant digit The 7447 is intended for BCD binary coded decimal which is input values 0 to 9 0000 to 1001 in binary Inputs from 10 to 15 1010 to 1111 in binary will light odd display segments but will do no harm 157 Khalil Ismailov Pin Assignments of 74 Series ICs From http www fsref com Fatal FE200202 SHTML 7400 Quad Dual Input NAND Gate o AN o RENE o NE o MEN o MEME o MEME oo EN Vcc X A NAND B NAND A B A4 00
20. 2006 minute No C QU 105 400 23 Book is printed by Sharg Qarb Publishing House LUV CAN Y Q4 v Iss IN Qafqaz University 2010 Press No 42 CONTENTS Preface a 303 0 6204 AL NAN MK En LIE ANS AE ih CERA ALLEE dE 1 Experiment Guidelines 2 Generating Digital Signals for Testing 0 2 Detecting Logic Signals 44 5 Logic Probes eee 7 logic Pulsets s gt grus uentos c eom Eh OD Qo GE SLT E 7 Power Supplies 444 7 Digital Logic Trainer Y 0039 et 8 Experiment 1 Digital Logic Circuits 44 11 Experiment 2 Simplification of Boolean Functions 19 Experiment 3 Basic Design of Combinational Circuits 000 27 Experiment 4 Karnaugh Maps and Design Minimization 1 33 Experiment 5 Code Converters yy 40 Experiment 6 Design with Multiplexers and Demultiplexers 3 48 Experiment 7 Arithmetic Circuits 63 Experiment 8 Properties of Latches Flip Flops 71 Experiment 9 Ripple Counter Design 000000 82 Experiment 10 Synchronous Counter Analysis lt lt 91 Experiment 11 Registers eee 98 Experiment 12 Shift Register Counters OOO OOO 105 REFERENCES APPENDIX A APPENDIX B APPENDIX C APPENDIX E APPENDIX D 113 114 120 130 150 165 PREFACE This manual is designed to provide practical laboratory experience for the student of digital electronics The manual includes experiments o
21. 4 Dual Input NAND K155JIA3 7401 14 4 Dual Input NAND gate Open Collector K155J1A8 7402 14 4 Dual Input NOR gate K155JIE1 7403 14 4 Dual Input NAND gate OC K155JIA9 7404 14 6 Inverter K155JIH1 7405 14 6 Inverter OC K155JIH2 7406 14 6 30 V 40 mA Inverter K155JIH3 7407 14 6 Buffer Driver OC K155JIII9 7408 14 4 Dual Input AND gate K155JIH 1 7409 14 4 Dual Input AND gate OC K155JIH2 7410 14 4 Triple Input NAND gate K155JIA4 7411 14 3 Triple Input AND gate K155JIH3 7412 14 3 Triple Input AND gate K155JIA10 7413 14 2 Schmitt Trigger NAND K155TJI1 7414 14 6 Schmitt Trigger Inverter K155TJD 7415 14 3 Tri State AND gate K155JIM4 7416 14 6 15 V 40 mA Inverter K155JIH5 141 Khalil Ismailov 7417 14 6 15 V 40 mA Buffer K155JIIIA 7420 14 2 Quad Input NAND gate K155JIA 1 7421 14 2 Quad Input AND gate K155JIM6 7422 14 2 Quad Input NAND gate OC K155JIA7 7423 14 2 Quad Input NOR gate with strobe K155JIE2 7424 14 2 Quad Input NOR gate 7425 14 2 Quad Input NOR gate with strobe K155JIE3 7426 14 4 Dual Input NAND gate K155JIA11 7427 14 3 Triple Input NOR gate K155JIE4 7428 14 4 Dual Input NOR Buffer K155JIE5 7430 14 1 8 Input NAND gate K155JIA2 7432 14 4 Dual Input OR gate K155JIJI 1 7433 14 4 Dual Input NOR Buffer K155JIE 11 7437 14 4 Dual Input NAND Buffer K155JIA12 7438 14 4 Dual Input NAND Buffer OC K155JIA 13 7439 14 4
22. 4017 Decade Counter 7490 74390 4510 4018 BCD Counter Presettable 4518 4029 4 Bit Binary Counter 7493 74161 74163 74193 74393 4510 Decade Counter 7490 74390 4017 4516 Binary Counter Presetable 4520 4518 Dual BCD Counter 4018 4520 Dual Binary Counter 4516 139 Khalil Ismailov Latches and Flip Flops Device Function Similar Devices 7473 Dual J K Flip Flop 7476 4027 7474 Dual D Type Flip Flop 74175 74273 4013 40174 7476 Dual J K Flip Flop 7473 4027 74175 Quad D Type Flip Flop 7474 74273 4013 40174 74273 Octal D Type Flip Flop 7474 74175 4013 40174 74373 Octal D Type Latch Inverting Tri State 74374 74533 74573 74574 4042 74374 Octal D Type Latch 74373 74533 74573 74574 4042 74533 Octal D Type Latch 74373 74374 74573 74574 4042 74573 Octal D Type Latch 74373 74374 74533 74574 4042 74574 Octal D Type Latch 74373 74374 74533 74573 4042 4013 Dual D Type Flip Flop 7474 74175 74273 40174 4027 Dual J K Flip Flop Master Slave 7473 7476 4042 Quad D Type Latch Clocked 74373 74374 74533 74573 74574 40174 Hex D Type Flip Flop 7474 74175 74273 4013 Decoders Device Function Similar Devices 7447 BCD to 7 Segment decoder 15 V 7448 4056 4511 7448 BCD to 7 Segment decoder 7447 4056 4511 74137 3 to 8 Line Decoder 74138 74138 3 to 8 Line Decoder 74137 74154
23. 60 mA Peak 1 of 6 df Forward Voltage Segment or DP Peak Wavelength Dominant Wavelengthl3 71 Reverse Voltage Segment or DPI4 Temperature Coefficient of Vp Segment or DP Thermal Resistance LED Junction R8 pi 345 C W to Pin Seg High Performance Green Device Series HDSP Parameter Units Test Conditions Luminous Intensity Segmentl 1 21 Digit Average Ip 2 60 mA Peak 1 of 6 df Forward Voltage Segment or DP Peak Wavelength Dominant Wavelengthl3 71 Reverse Voltage Segment or DPI41 Temperature Coefficient of p Segment or DP Thermal Resistance LED Junction to Pin Notes 1 Device case temperature is 25 C prior to the intensity measurement 2 The digits are categorized for luminous intensity The intensity category is designated by a letter on the side of the package 3 The dominant wavelength X4 is derived from the CIE chromaticity diagram and is that single wavelength which defines the color of the device 4 Typical specification for reference only Do not exceed absolute maximum ratings 5 For low current operation the AlGaAs HDSP H10X series displays are recommended They are tested at I mA dc segment and are pin for pin compatible with the HDSP H15X series 6 For low current operation the HER HDSP 555X series displays are recommended They are tested at 2 mA dc segment and are pin for pin compatible with the HDSP 550X series 7 The Yellow HDS
24. Binary o Output Switches i X A B Fig 1 4 Experimental OR gate circuit 3 You will now verify the OR operation by setting inputs A and B to each set of logic values listed in the Table 1 1 Record the output voltage observed and convert the output voltage to a logic level Use OV 0 8V 0and2V 5V 1 for the conversions and record your observations in Table 1 1 4 Disconnect the DMM from the circuit and use a TTL Logic Indicator LED Monitor to observe the output Repeat step 3 using the conversion rule LED OFF unlighted 0 and LED ON lighted 1 Record your observations in Table 1 1 5 Disconnect one of the inputs and set the remaining one to O Is the output level O or 1 Based on your observation and knowledge of the OR operation what level does the unconnected input act like Table 1 1 OR gate circuit experimental results Data Switches Output Logic GA as Level 0 1 A 0 0 1 1 Oo 3 oiuv AND Gate 1 Connect the circuit in Fig 1 5 Do not forget the power supply connections Binary o Output Switches X A B Fig 1 5 Experimental AND gate circuit 13 Khalil Ismailov 2 Connect the output to the TTL Logic Indicator You will now verify the AND operation by setting inputs A and B to each set of logic values listed in the Table 1 2 Record the output level observed on the TTL Logic Indicator using Table 1 2 Table 1 2 AND gate
25. Construct the circuit of Fig 10 3 Make the following connections to the 74193 IC 1 Connect toggle switches to Ps through Po 2 Connect normally LOW pushbutton switches to CPu and MR inputs NOTE if necessary you may use a toggle switch for MR 3 Connect LED monitors to Qs through Qo and also at TCu 4 Connect a toggle switch to CP 94 Digital Logic Design 5 Connect a normally HIGH pushbutton switch to PL Toggle switches MR Q Q Qi Qo Fig 10 3 Circuit for Assignment 10 3 b Set the toggle switches to the parallel inputs so that Po P P2 Ps O Set CPo HIGH Clear the counter to 0000 by pulsing MR HIGH Note that TCu terminal count up mode is HIGH c Pulse CPu HIGH a couple of times and note that the counter counts UP Pulse the counter until a count of 1111 is displayed Record the state of TCu Now pulse the counter one more time Now record the value of TCu Record the observations you have made in Table 10 2 95 Khalil Ismailov d D g Table 10 2 Test results for the 74193 IC UP counter Input pulse Output states Decimal applied Qs Q Qi Qo number TCu None 0 0 0 0 0 1 Set CPD LOW Pulse the CPU input several times What happens Return CPD to HIGH and pulse CPU a few more times You should observe that the counter does not count as long as CPD is LOW
26. SWG output to TTL levels DETECTING LOGIC SIGNALS In testing their circuit designs students need to be able to determine logic levels at circuit outputs It is most convenient to have a visual display Although commercially available logic probes are ideal instruments for this Khalil Ismailov purpose the discussion below shows how to use simple light emitting diode LED circuits to satisfy most needs LEDs are semiconductor diodes that emit light when they are forward biased The light can be of various colors depending on the semiconductor used in the diode It is important to remember that LEDs are not made from silicon When they are forward biased the forward voltage drop is about 1 2 V to 1 4 V Fig 0 4 shows three possible ways of using LEDs as logic level indicators Signal line Signal line Signal line N i pP 7404 R 7405 c R a Unsatisfactory b Negative logic c Buffered preferred Fig 0 4 LED indicating circuit Simply connecting the LED between the signal line to be monitored and ground as shown in a is almost always unsatisfactory The most serious problem is that this connection drops the voltage on the signal line to the diode forward bias voltage of 1 2 V to 1 4 V which values are between the HIGH and LOW threshold specifications for TTL logic Thus any other device that is using the signal as input will not function correctly The circuit shown in b connects the diode between the positive suppl
27. anode device diodes are forward biased by applying a LOW level at the segment inputs This type of display is illustrated in Fig 5 3 a To display a 42 Digital Logic Design decimal digit it is thus necessary to have a circuit which will accept a 4 bit BCD input and produce seven outputs which will cause the required segments to be illuminated An integrated circuit frequently used for common anode display devices is the 7447 decoder driver the logic symbol for which is shown in Fig 5 3 b JB M 7447 FRLIIIIILII Ze dde ag WQUr gt UG jE N a De c e e eh og amp p o 7020 5050 E a 7 segment LED display device b Decoder driver Fig 5 3 Common anode LED display device The BCD input is applied to pins D to A with D being the most significant bit The segment outputs a to f are active LOW so that they can forward bias the corresponding diode to which they are connected It should be noted that the 7447 uses open collector outputs and it is necessary to connect the 7447 outputs to the LED inputs through a current limiting resistor For the LED devices used in this laboratory 5 to 10 mA forward current is required for adequate light output and the specified forward voltage drop is 1 6 V Therefore a series current limiting resistors from 270 Q to 680 Q should be used In addition to the BCD inputs and 7 segment code outputs three additional pins are avai
28. asynchronously and overrides all other inputs when active The 74165 device features serial and parallel data input and serial data output through Q7 When the parallel load control input PL is low data are loaded into the register asynchronously through the D inputs When the PL input is high data enter the register serially through the DS input and shifts one bit to the right synchronously with the positive going clock transition The CE input is an active low clock enable clocking is inhibited when HIGH ps PL Do D Dz D3 D4 Ds Dg D DSA 74164 DSB CP upp Qo Q1 Qe Q3 QW Q53Q Qr 74165 ICE Q Q Fig 11 3 8 bit integrated circuit registers Fig 11 3 shows two examples of 4 bit register circuits which are more versatile than the above devices The 7495 shown in a has parallel and serial input capability as well as parallel and serial output capability Separate clocks are used for serial input shift right operation CPO and parallel data input CP1 The operating mode is determined by the level on the select line S when S is HIGH data are parallel loaded synchronously with the trailing edge of CP1 CPO is a don t care from the D inputs but when S is LOW shift right operation occurs with data input serially from the DS input synchronous with the trailing edge of CPA Even more versatile operation is available with the 74194 circuit shown in Fig 11 4 b This circuit is a bidirectional universal shift register w
29. bit changes at a time as quantity is increased Such a code is called a unit distance code Fig 5 1 shows a commonly used unit distance code the Gray code Although this code is shown for four bits it can be extended to any number of bits for more resolution Fig 5 1 a shows the truth table for the code while b illustrates its relation to the K map for four variables Decimal Binary Gray 0 0000 0000 1 0001 0001 2 0010 0011 3 0011 0010 4 0100 0110 5 0101 0111 6 0110 0101 00 01 11 10 7 0111 0100 8 1000 1100 00 9 1001 1101 10 1010 1111 01 11 1011 1110 12 1100 1010 11 13 1101 1011 14 1110 1001 10 15 1111 1000 a Truth table b K map generation Fig 5 1 Gray code It should be noted that K maps provide a unit distance representation of Boolean functions moving from any square to the next either vertically or horizontally or at opposite ends of rows or columns causes only one bit to change The Gray code follows the path shown in the above figure beginning with 0000 41 Khalil Ismailov One of the reasons that Gray code is commonly used is that it is easy to convert between binary and Gray code representations It can be seen from the examination of the truth table in Fig 5 1 a that the most significant bits of both codes are the same In the case of converting from binary to Gray bit N of the Gray code can be generated by th
30. by 7AL5 outputs connected to 1mA must be unless a pull up resistor is HALE SN Compatible hold them at used with 74LS logic 0 TTL outputs Can sink and Can sink and Can sink and Can sink up to source about 5 source about source about 16 mA mA 10 mA 20 mA 20 mA enough to api 7 enough to enough to po Outputs ok to light lightan LED light an LED oni about 2 an LED To To switch To switch mA To switch switch larger larger currents larger currents larger currents currents use a use a use a use a transistor transistor transistor transistor One output can One output ee One output can drive up to 50 can drive up Fan out ai 74HCT CMOS 74HC or 74HCT to 10 74LS inputs but only inputs but only 10 74LS inputs inputs or 50 one 74LS input 74HCT inputs 133 Khalil Ismailov Maximam about 1 MHz about 25 MHz about 25 MHz about 35 MHz Frequency Power consumption A few uW A few uW A few uW A few mW of the IC itself TTL Device Summary Device Function Similar Devices 7400 Quad 2 Input NAND Gate 7403 74132 4011 4093 40107 7402 Quad 2 Input NOR Gate 4001 7493 Guad o Input NAND Gate Open 17200 74139 4011 4093 40107 collector 7404 Hex Inverter 7405 7406 7414 4009 4049 4069 7405 Hex Inverter Open collector 7404 7406 7414 4009 4049 4069 7406 Hex Inverter Open collector 7404 74
31. circuit experimental results Data Switches Output of TTL Logic Output Logic Indicator ON OFF Level 0 1 A 0 0 1 1 Oo 3 oj u 3 Disconnect one of the inputs and set the remaining one to 1 Note the logic level indicated by the TTL Logic Indicator Based on your observation what logic level does the unconnected input act like NOT Gate 1 Connect the circuit in Fig 1 6 Do not forget the power supply connections 2 Connect the output to the TTL Logic Indicator You will now verify the NOT operation by setting input A to each set of logic values listed in the Table 1 3 Record the output level observed on the TTL Logic Indicator using Table 1 3 TTL Binary Switches Fig 1 6 Experimental inverter circuit Table 1 3 NOT gate circuit experimental results Data Switch A Output of TTL Logic Indicator ON OFF Output Logic Level 0 1 0 1 14 Digital Logic Design NOR Gate 1 Connect the circuit in Fig 1 7 Do not forget the power supply connections Y 0039 a Output Trainer Binary o o X A B Switches Fig 1 7 Experimental NOR circuit 2 Connect the output to the TTL Logic Indicator Set the toggle switches to each input combination listed in the Table 1 4 observe and record the output state of the TTL Logic Indicator in the Table 1 4 Table 1 4 NOR gate circuit experi
32. for the given assignment 31 Khalil Ismailov Assignment No Boolean expression Designed logic circuit Truth tables For Assignment 3 5 For Assignment 3 6 A B C X A B C D Y 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 0 1 1 0 0 1 1 1 0 0 0 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 o N EXPERIMENT KARNAUGH MAPS AND DESIGN MINIMIZATION OBJECTIVES 1 Define circuit level and relate it to circuit speed 2 Construct the Karnaugh map of any given function of 2 3 or 4 variables 3 Use Karnaugh map simplification to design minimized 2 level combinational circuits EQUIPMENT REQUIRED Digital Logic Trainer Digital IC chips as required BASIC INFORMATION In addition to providing problem solutions that are functionally correct the circuit design process must also provide solutions that satisfy other constraints In logic circuit design these constraints are typically minimized cost minimized power dissipation and maximized speed Minimized cost and power dissipation typically imply minimizing the chip count for any given logic family In combinational circuits maximizing the circuit speed implies minimizing the circuit logic level again for any given logic family The logic level of a circuit is measured by the maximum
33. from entering through the AC lines and grounded shields or conducting planes to short radiated noise signals to ground 125 Khalil Ismailov B 4 Common Digital IC Faults Digital IC faults are classified as either internal or external faults We begin our discussion with internal faults Internal digital IC faults There are four types of internal failures 1 inputs or outputs shorted to ground or Vcc 2 inputs or outputs open 3 shorts between pins not to ground or Vcc 4 internal circuitry failure These failures are corrected by replacing the faulty IC A discussion on each type of failure follows Short to ground or Vcc This failure causes the inputs or outputs to be either permanently HIGH or permanently LOW referred to as stuck HIGH or stuck LOW Fig B 2 a shows a NAND gate with a stuck LOW input and a stuck HIGH output The stuck HIGH condition may be the result of an internal short in input A an internal short at output X or both Open Fig B 2 Types of failure Connections to output X are also forced HIGH connections to input A are forced LOW Shorts of this type in emitter coupled logic ECL devices result in neither a HIGH nor a LOW 126 Digital Logic Design In troubleshooting this type of failure the student should be aware that signals may not change beyond the point where the short is located Open inputs or outputs An open output will result in an open input for all
34. grown together as in an integrated circuit soldered together as on a printed circuit board or held together by screws and clamps as in house wiring In lab we want something that is easy to assemble and easy to change We also want something that can be used with the same components that real circuits use This is a way of making a temporary circuit for testing purposes or to try out an idea No soldering is required and all the components can be re used afterwards To build a prototype of an electronic circuit a material or device called breadboard is widely used The breadboard derives its name from an early form of point to point construction In the early days of radio amateurs would nail copper wire or terminal strips to a wooden board often literally a board for cutting bread and solder electronic components to them Sometimes a paper schematic diagram was first glued to the board as a guide to placing terminals components and wires The heart of the solderless breadboard is a small metal clip that looks like as in Fig A 1 Fig A 1 Socket and bus strips The clip is made of nickel silver which like mock turtle soup contains no silver a material which is reasonably conductive reasonably springy and reasonably corrosion resistant Because each of the pairs of fingers is independent we can insert the end of a wire between any pair without reducing the tension in any of the other fingers Hence each pair can hol
35. input Select lines gt output lines Fig 6 4 74138 1 to 8 DMUX circuit Table 6 3 shows the demultiplex function of 74138 in terms of select lines Table 6 3 74138 truth table Inputs Outputs Enable Select E3 E2 E1 A2 Ai Ao YO Y1 Y2 Y3 Y4 Y5 YO YZ 0 X X X X X 1 1 1 1 1 1 1 1 X 1 X X X X 1 1 1 1 1 1 1 1 X X 1 X X X 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 0 1 1 1 1 1 1 1 0 0 0 1 0 1 1 0 1 1 1 1 1 1 0 0 0 1 1 1 1 1 0 1 1 1 1 1 0 0 1 0 0 1 1 1 1 0 1 1 1 1 0 0 1 0 1 1 1 1 1 1 0 1 1 1 0 0 1 1 0 1 1 1 1 1 1 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 Demultiplexer circuits are multipurpose AND array circuits used extensively in data transmission and in data routing applications 52 Digital Logic Design LABORATORY ASSIGNMENTS Assignment 6 1 Design a multiplexer which will multiplex one of two nibbles 4 bits of data to the output of the multiplexer Use one 74157 integrated circuit Hint For this device the A inputs are selected for each stage when S 0 The nibble 1 So S3 is entered into the A inputs of 74157 and the nibble 2 Ro R3 is entered into the B inputs of 74157 Fig 6 5 Address o S select 1 R select 74157 Select Nibble 1 inputs So Si Nibble2 s inputs S D One nibble of D data outputs Fig 6 5 Nibble multiplexing Construct the circuit and w
36. into a single full length 50 contact strip If this is what you want you will have to bridge the central gap yourself When we combine two socket strips three bus strips and three binding posts on a plastic base we get the breadboard Fig A 5 These strips connect the holes on the top of the board This makes it easy to connect components together to build circuits To use the breadboard the legs of components are placed in the holes the sockets The holes are made so that they will hold the component in place Each hole is connected to one of the metal strips running underneath the board me Fig A 5 The breadboard The orange lines indicate connected holes Each wire forms a node A node is a point in a circuit where two components are connected Connections between different components are formed by putting their legs in a common node On the bread board a node is the row of holes that are connected by the strip of metal underneath The long top and bottom row of holes are usually used for power supply connections 116 Digital Logic Design The rest of the circuit is built by placing components and connecting them together with jumper wires Then when a path is formed by wires and compo nents from the positive supply node to the negative supply node we can turn on the power and current flows through the path and the circuit comes alive You will build your circuits on the terminal stri
37. isolation is presented The student should when applying the procedure in the lab perform each step in the order given After sufficient experience with digital circuits is attained common sense and intuition may lead the student directly to the faulty device and thereby reduce the amount of troubleshooting time Step 1 Perform a visual inspection of the system or circuit Look for loose or damaged connecting wires cables and printed circuit PC boards evidence of burning or extreme overheating missing components and blown fuses If the circuit or system is mounted on prototype boards look for wiring errors damaged boards and digital ICs improperly inserted Also check for incorrect circuit design Step 2 Check all power source levels and confirm that power is actually being applied to the circuit or system Step 3 Study all relevant documentation on the circuit or system such as block diagrams schematics and operating instructions Learn how the circuit or system operates normally 122 Digital Logic Design Step 4 Verify all operating modes of the circuit by running tests Step 5 Record results of the tests run in step 4 Test results often show patterns that may lead to the faulty device Repeat steps 4 and 5 at least once before proceeding to step 6 Step 6 If the circuit passes all tests end the procedure If the circuit fails at least one test continue to the next step Step 7 Analyze the test results r
38. length of wire is no more than needed to make a neat connection between circuit blocks If the wires are too long some circuits will malfunction especially flip flops and flip flop devices such as counters You may have to rearrange the ICs on the board to solve this problem if it occurs Another way to solve the problem is by inserting a 2 kQ resistor in series with the wire at the input end of the wire Have a lab partner call out each connection to be made Route the wires along the circuit board neatly bending them smoothly wherever necessary Avoid bending the wire sharply since this will increase the likelihood of fracture beneath the insulation resulting in an open circuit or an intermittent open Minimize the number of crossovers that is wires routed over other wires The overall appearance should be neat not like a bowl of spaghetti If you have made all of your connections as outlined above it may not be picture perfect but the neatness will pay off in reduced troubleshooting time and easier IC replacement B 2 Testing the Circuit Circuit testing is also known as troubleshooting You are probably accustomed to discrete circuit e g a transistor amplifier troubleshooting methods Since 121 Khalil Ismailov each circuit element of a discrete circuit is accessible to the troubleshooter faulty circuit elements can be isolated by making basic measurements such as voltage resistance capacitance and inductance usin
39. note the states of both LEDs Q Q Predicting the states of a latch when power is first applied is impossible so the values just recorded are random Clear Q by momentarily pulsing the R input HIGH If Q is already HIGH pulsing the R input will have no effect on the circuit 74 Digital Logic Design a Logic symbol Inputs Mode description Output Sp Rp CP J K Q Asynchronous set 0 1 x x x 1 Asynchronous reset 1 0 x x x 0 Hold 1 1 4 010 Q Store 0 1 1 4 0 1 0 Store 1 1 1 4 1 0 1 Toggle 1 1 J 1 1 Q b Function table Fig 8 4 74LS76 flip flop Pulse the S input HIGH and observe the effects on the circuit outputs Q Q Note that releasing the pushbutton does not cause Q to change from its new state Why Now pulse the S input HIGH again What effect does this have on the circuit outputs Pulse the R input HIGH and observe that Q changes back to LOW and stays LOW even after the pushbutton is released Alternatively pulse the S and R inputs HIGH several times Note that the outputs are always at opposite states Press and hold the S and R inputs HIGH at the same time Note that both outputs are now LOW Release the pushbuttons and note the states of the outputs Are they both still LOW 75 Khalil Ismailov Assignment 8 2 g 7475 IC D latch operation Note that the 7475 has four D latches The latch CLK inputs are t
40. number of gates between inputs and outputs The greater the logic level the slower the circuit because each gate causes a timing delay called the propagation delay before the output can respond to changes in the inputs Fig 4 1 a shows a 4 level circuit which realizes the function X A B CD E The circuit shown in Fig 4 1 b is a 2 level circuit which realizes the same function in the form X AB ACD E This circuit would be faster than the circuit in a because there are fewer propagation delays between inputs and output It should be noted that the 2 level circuit corresponds to a sum of products SOP representation of the function A design must often effect a compromise 33 Khalil Ismailov between chip count and speed depending on the design environment For example if the function X were being generated in a system which had unused 2 input gates available but no 3 input gates the 4 level circuit of a may be preferred since it could be built without requiring any additional chips C D B A X E a A B X C D E b Fig 4 1 Circuit logic levels All Boolean functions can always be represented as a SOP and alternatively as a product of sums POS The Karnaugh map K map is a graphical representation of a Boolean function which is particularly useful in determining the minimized simplest SOP or POS expressions for a function The specific arrangement of the K map eliminates the need for extensiv
41. one on each side of QA 1 reset j the chip They are ripple counters so 8 QB 2 4174393 11 QA 1 beware that glitches may occur in QC 4 QB 2 8 logic systems connected to their m outputs due to the slight delay before aD 8 9 QC 4 the later outputs respond to a clock ov 8 QD 8 pulse The count advances as the clock input becomes low on the falling edge this is indicated by the bar over the clock label This is the usual clock behaviour of ripple counters and it means a counter output can directly drive the clock input of the next counter in a chain For normal operation the reset input should be low making it high resets the counter to zero 0000 QA QD low Counting to less than 15 can be achieved by connecting the appropriate output s to the reset input using an AND gate if necessary For example to count 0 to 8 connect QA 1 and QD 8 to reset using an AND gate 153 Khalil Ismailov Connecting ripple counters in a chain The diagram below shows how to link ripple counters in a chain notice how the highest output QD of each counter drives the clock input of the next counter 74160 3 synchronous counters roset ik eed id e 74160 synchronous decade counter clock CK carry out CO standard reset input A output QA 1 e 74161 synchronous 4 bit counter input B 2 output QB 2 standard reset e 74162 synchronous decade counter synchronous reset input D 8 6 74163 output QD 8
42. oscilloscopes and function generators to trainer elements and circuits Two sets of independent 7 segment displays with BCD 7 segment decoder driver and decimal point input terminal input with 8 4 2 1 code 2800 holes accepting all DIP devices components with leads and solid wires 0 3 mm to 0 8 mm Power lead connecting leads fuse dust cover and user manual 220V AC 10 50 Hz 10 EXPERIMENT DIGITAL LOGIC CIRCUITS OBJECTIVES 1 To determine by experiment the function table for the digital logic gates 2 To construct a simple combinational logic circuit and prove its function table EQUIPMENT REQUIRED Digital Logic Trainer Digital Multimeter DMM Dual Trace Oscilloscope 1 each 7400 7402 7404 7408 and 7432 integrated circuits BASIC INFORMATION In digital circuitry a gate is a circuit with two or more inputs and a single output If the inverter is considered to be a gate it is an exception to the rule with a single input Not all people consider the inverter to be a gate There are two basic gate circuits OR and AND Fig 1 1 B B Fig 1 1 OR and AND gates Fig 1 2 NOR and NAND gates 11 Khalil Ismailov When the inverter is added to the AND and OR gates as in Fig 1 2 NOT AND NAND or NOT OR NOR circuits result making two more types of gates Combinations of basic gates can be used to perform complex logic operations in computers and other digital equipment Fig 1 3 is an ex
43. ripple dock T counter reset The 74390 contains two separate decade 0 to 9 counters one on each side of the chip They are ripple counters so beware that glitches may occur in any logic gate systems connected to their outputs due to the slight delay before the later counter outputs respond to a clock pulse rm Counter 1 amp 3 8 E LL zimuneg 152 Digital Logic Design The count advances as the clock input becomes low on the falling edge this is indicated by the bar over the clock label This is the usual clock behaviour of ripple counters and it means a counter output can directly drive the clock input of the next counter in a chain Each counter is in two sections clock A QA and clock B QB QC QD For normal use connect QA to clock B to link the two sections and connect the external clock signal to clock A For normal operation the reset input should be low making it high resets the counter to zero 0000 QA QD low Counting to less than 9 can be achieved by connecting the appropriate output s to the reset input using an AND gate if necessary For example to count 0 to 7 connect QD 8 to reset to count 0 to 8 connect QA 1 and QD 8 to reset using an AND gate Connecting ripple counters in a chain please see 74393 below 74393 dual 4 bit 71 FK 2 to 6V HC 0 15 ripple counter dock OK 1 0 5V LS HCT 7 reset clock CK The 74393 contains two separate 4 bit 0 to 15 counters
44. segment displays are designed for viewing distances up HDSP 550x Series HDSP 552x Series HDSP 560x Series HDSP 562x Series HDSP 570x Series HDSP 572x Series HDSP H15x Series to 7 metres 23 feet These devices use an industry standard size package and pinout Both the numeric and 1 overflow devices feature a right hand decimal point All devices are available as either common anode or common cathode Devices AlGaAs Red HER Yellow Green Package HDSP HDSP l I HDSP HDSP Description Drawing H151 5501 5601 Common Anode Right Hand Decimal Common Cathode Right Hand Decimal 5607 Common Anode 1 Overflow Common Cathode 1 Overflow Two Digit Common Anode Right Hand Decimal Two Digit Common Cathode Right Hand Decimal Note 1 These displays are recommended for high ambient light operation Please refer to the HDSP H10X K12X AlGaAs and HDSP 555X HER data sheet for low current operation 165 Khalil Ismailov These displays are ideal for most applications Pin for pin equivalent displays are also available in a low current design The low current displays are ideal for portable applications For additional information see the Low Current Seven Segment Displays data sheet Part Numbering System 5082 X X X X XX X X X HDSP X X X X X X X X X THEN Mechanical Options 00 No Mechanical Option Color Bin Options 21 0 No Color Bin Limitation Maximum Intensity Binl 2 0 No M
45. synchronous operation of the 7476 do the following steps 1 Set 1 and K 0 Turn the power on and note the states of Q and Q If the flip flop is not cleared Q 0 then pulse the DC RESET input LOW momentarily Press and hold the CLK input HIGH You should observe that this has no effect on the outputs Now release the pushbutton What happens to Q Pulse the CLKinput several more times and note that this has no effect on the outputs Change J to 0 Note that this has no effect on the outputs Pulse the CLK input several times You should observe that this also has no effect on the outputs Why Change K to 1 and note that Q does not change Press and hold the CLK input HIGH What happens to Q Now release the CLK pushbutton What happens to Q now Pulse the CLK input several more times and note that Q does not change Change J to 1 Note that Q remains LOW Press and hold the CLK pushbutton HIGH What happens to Q j Release the pushbutton What happens to Q now Pulse the CLK input several more times You should observe that Q changes states on each CLK pulse 80 Digital Logic Design r In step q you should observed that the flip flop loaded the J and K inputs only when the CLK is high and they were transferred to Q and Q on a negative going transition at CLK Now you will observe the chief disadvantage of the master slave data at the J and K inputs can affect the flip fl
46. the count direction can be changed by a control signal The advantage of ripple counters is their simple hardware But they are asynchronous circuits and with added logic can be unreliable and delay dependent This is particularly true for logic that provides feedback paths from counter outputs to counter inputs Also due to the length of time required for the ripple to occur large ripple counters are slow circuits As a consequence synchronous binary counters are favored in all but low power designs where ripple counters have an advantage Counter applications often require decoding the output count states produced by a counter Counter decoding can be used to shorten a count sequence to enable other logic circuits when a specific count state is reached or to display the count state as a decimal number The basic binary ripple counter is restricted to a counter modulus which is a power of 2 Many applications however require other moduli There is a simple design solution which permits the design of ripple counters of any modulus If modulus N is required the terminal count will be N 1 after which the counter should recycle to state O This can be realized by decoding state N and applying the output of the decoding gate asserted active low to the asynchronous reset inputs of the flip flops This technique forces the counter back into state O Fig 9 3 shows a mod 6 ripple counter designed in this way Note that state 6 is 84 Digi
47. u D o 6 Nol Vcc Vcc Eb A0b Alb 0b 1b 2b 3b Vcc I5 I5 I6 I7 so S1 S2 163 Khalil Ismailov 74192 BCD Decade Up Down Counter 74193 4 bit Binary Up Down Counter D1 Q1 Q0 CPd CPu Q2 Q3 GND oO U RB wW B3 1 2 o Nol 6 5 4 Vcc DO MR Ted TCu PL D2 D3 74194 4 Bit BiDirectional Shift Register MR DSR DO D1 D2 D3 DSL GND oO U RB Q N fs o w Vcc Q0 Q1 Q2 Q3 CP S1 so 164 Digital Logic Design APPENDIX E 14 2 mm 0 56 inch Seven Segment Displays Technical Data Features Industry Standard Size Industry Standard Pinout 15 24 mm 0 6 in DIP Leads on 2 54 mm 0 1 in Centers Choice of Colors AlGaAs Red High Efficiency Red Yellow Green Excellent Appearance Evenly Lighted Segments Mitered Corners on Segments Gray Package Gives Optimum Contrast 50 Viewing Angle Design Flexibility Common Anode or Common Cathode Single and Dual Digits Right Hand Decimal Point 1 Overflow Character Categorized for Luminous Intensity Yellow and Green Categorized for Color Use of Like Categories Yields a Uniform Display High Light Output High Peak Current Excellent for Long Digit String Multiplexing Intensity and Color Selection Option See Intensity and Color Selected Displays Data Sheet Sunlight Viewable AlGaAs Description The 14 2 mm 0 56 inch LED seven
48. very basic information and suggestions concerning each area It is not meant to replace any laboratory standards However much of the information given here can be used as reference material that can be and should be reviewed from time to time Most of the experiments contain operational testing of various ICs At times this may appear to be a tedious undertaking on your part Don t fall into the trap of treating this sort of experimentation mechanically taking for granted that an IC will operate just as it did in the classroom lecture In the classroom you are working with the ideal In the lab you will occasionally work with ICs that are less than ideal In fact they may not work at all or at least not in the manner they were designed to work If you keep in mind that lab experimentation is not only to verify principles but also to learn to recognize common problems associated with the circuits you will get more out of the experiments As you will learn verification of a circuit s operation is one of the first steps taken in troubleshooting B 1 Prototype Circuit Wiring It is assumed that you will be wiring circuits using a prototype circuit board Such boards come in different sizes but most have the following features a Two horizontal rows of holes one at the top and one at the bottom The contacts underneath the holes on each of these rows are connected together to form a bus They are not directly connected to the other holes
49. 05 7414 4009 4049 4069 74240 74241 74244 74365 74541 4050 7407 Hex Buffer 4503 40106 7408 Quad 2 Input AND Gate 4081 7410 Triple 3 Input NAND Gate 4023 7411 Triple 3 Input AND Gate 4073 7414 Hex Inverter Schmitt trigger 7404 7405 7406 4009 4049 4069 7420 Dual 4 Input NAND Gate 4012 7421 Dual 4 Input AND Gate 4082 7427 Triple 3 Input NOR Gate 4025 7430 8 Input NAND Gate 4068 7432 Quad 2 Input OR Gate 4071 7447 BCD to 7 Segment decoder 15V 7448 4056 4511 7448 BCD to 7 Segment decoder 7447 4056 4511 7473 Dual J K Flip Flop 7476 4027 7474 Dual D Type Flip Flop 74175 74273 4013 40174 7476 Dual J K Flip Flop 7473 4027 7483 4 Bit Binary Full Adder 74283 7485 4 Bit Magnitude Comparator 4063 4585 7486 Quad 2 Input XOR Gate 74266 4030 4070 4077 7490 Decade Counter 74390 4017 4510 7493 4 Bit Binary Counter 74161 74163 74193 74393 4029 74121 Monostable Multivibrator 74221 4098 4528 zita Qed 2 AnpHENAND Gate 7400 7403 401 1 4093 40107 Schmitt trigger 134 Digital Logic Design 74137 3 to 8 Line Decoder 74138 74138 3 to 8 Line Decoder 74137 74154 4 to 16 Line Decoder 4514 74161 4 Bit Binary Counter 7493 74163 74193 74393 4029 74163 4 Bit Binary Counter 7493 74161 74193 74393 4029 74161 8 Bit Shift Register 74164 401 4 4015 74164 8 Bit Shift Register 74161 4014 4015 74175 Quad D Type Flip Flop 7474 742
50. 2 Fig B 3 CMOS short between pins and intermediate levels Internal circuitry failure Failure in the circuits within a digital IC can cause its inputs and outputs to be stuck HIGH or stuck LOW 127 Khalil Ismailov External digital IC faults In addition to the four types of internal failure there are four types of external failures that can occur 1 line shorted to ground or power supply 2 open signal line 3 short between signal lines 4 failure of a discrete component To discover these faults look for poor soldering joints solder bridges open wires or traces or test components such as capacitors and resistors for opens shorts and or values that are out of tolerance Line shorted to ground or power supply This type of failure will appear like an internal short and can t be distinguished from it Perform a careful visual inspection to isolate this fault Open signal line Fig B 2 e shows an open signal line that results in an open input only for points beyond point B All inputs before A are unaffected by the open line Signal tracing and or continuity checks are useful techniques for discovering this type of fault Short between two signal lines This type of fault cannot be distinguished from an internal short Often poor soldering on PC boards results in solder bridges across the signal lines On prototype boards look for bare connecting wires poorly dressed too close together In either case a visual in
51. 4 143 Khalil Ismailov 74140 14 2 Quad Input NAND Line Driver K155JIA16 74141 1 of 10 Decoder Driver Nixie K155HJI1 74143 24 4 bit 7 segment counter latch 74145 16 10 4 Line Encoder K155HJI10 74148 16 Octal Encoder K155HB1 74150 24 16 Input Multiplexer K155KII1 74151 16 8 Input Multiplexer K155KII7 74152 16 8 Line to 1 line Data Selector Multiplexer K155KII5 74153 16 2 Quad Input Multiplexer K155KII2 74154 24 1 of 16 Decoder Demultiplexer K155U 13 74155 16 2 2 4 Decoder Demultiplexer K155H IA 74156 16 2 2 4 Decoder Demultiplexer K155HJI5 74157 16 4 Dual Input Multiplexer K155KII16 74158 16 4 2 1 Multiplexer K155KII18 74159 24 1 of 16 decoder demultiplexer OC K155HI19 74160 16 BCD Decade Counter K155HE9 74161 16 Synchronous Binary Counter 4 bit K155HE10 74162 16 BCD Decade Counter K155HE11 74163 16 Synchronous Binary Counter K155HE18 74164 14 Serial In Parallel Out Register K155HP8 74165 8 bit Parallel to Serial Converter K155HP9 74166 16 8 bit Shift Register K155HP10 74167 16 Sync Decade Rate Multiplier 74168 16 4 bit Up Down Sync Decade Counter K155HE16 74169 16 4 bit Up Down Sync Binary Counter K155HE17 74170 16 4x4 Register File K155HP32 74172 24 16 bit Mult Port Register File K155PII3 74173 16 4 bit D Register 3 State K155HP15 74174 16 6 DFlip Flo
52. 4 13 TTL Function Switches 3 1 Hz 100 Hz Function Generator 14 TTL One Shuttle Pulse Circuit FGO4 One Shot Multivibrator A Voltmeter 15 TTL Single Edge Pulse 5 2x7 Segment Decoder Generator 6 8 Bit TTL Logic Indicator 16 TTL Single Edge Pulse 7 Adapter 1 Generator 8 Adapter 2 17 Binary Switches 9 4 5 V TTL Power Source Khalil Ismailov Fixed DC Power Supply Variable DC Power Supply Voltmeter Variable Clock Generator Logic Indicators Data Switches TTL Function Switches One Shuttle Pulse Circuit Adapter Output Seven Segment Displays Removable Solderless Breadboard Accessories Power Supply Specifications Voltage range TTL 5V and 5V Maximum current output 1 A Voltage range 0 V 18 V 0V 18V Maximum current output 0 5 A Two 3 digit LED displayed voltmeters with range from 0 to 99 9 V Four frequency ranges 1Hzto110Hz 10 Hz to 1100 Hz 100 Hz to 11 kHz 950 Hz to 100 kHz Output sinusoidal triangle and square waves Sinusoidal and triangle output range are adjustable from 0 1 Vpp to 10 Vpp TTL output level is a fixed 5 V 8 sets of independent LEDs indicating high and low logic states One 8 bit DIP switches giving 8 bit TTL level output Two switches each having debounced 5 V and 5 V outputs Up position 5 V down position 5 V Produces negative and positive pulses for TTL applications Allows to connect DMMs
53. 5 20 Tri State Octal Transcender K155AI16 74247 16 BCD to 7 Segment Decoder Driver K155H I18 74248 16 BCD to 7 Segment Decoder Driver 74249 16 BCD to 7 Segment Decoder Driver 74251 16 Tri State 8 1 Multiplexer K155KII15 74253 16 2 Tri State 4 1 Multiplexer K155KII12 74257 16 4 2 1 Multiplexer K155KITT 1 74258 16 4 2 1 Multiplexer K155KII14 74259 16 8 bit Addressable Latch K155HP30 74260 14 2 5 Input NOR gate K155JIE7 74265 16 4 Comp Out Element 74266 14 4 Dual Input XNOR gate OC 74273 20 8 DFlip Flop K155HP35 74278 14 4 bit Priority Register 74279 16 Quad Set Reset Latch K155TP2 74280 14 Octal D Flip Flop K155HII5 74283 16 e 4 bit Full Adder K155UM8 74287 16 1024 bit PROM 74288 16 e 256 bit PROM 74289 16 64 bit RAM Open Collector Outputs K155PY9 74290 14 Decade Counter 145 Khalil Ismailov 74293 14 4 bit Binary Ripple Counter 74298 16 4 Two Port Register K155KII13 74299 20 8 Input Shift Storage Register K155HP24 74322 8 Serial Parallel Register with Sign Extend K155HP28 74323 8 Shift Storage Reg w Sync Rst amp Common K155HP29 1 O 74348 16 8 to 3 Priority Register K155HB2 74350 4 bit Shifter with 3 state Outputs K155HPA42 74352 2 4 input Multiplexer MUX K155KII19 74353 16 2 4 bit Multiplexer Inverting Output K155KII17 74365 16 6 Three State Buffer K155
54. 73 4013 40174 74193 Dual 4 Bit Binary Counter 7493 74161 74163 74393 4029 74221 Dual Monostable Multivibrator 74121 4098 4528 7407 74241 74244 74365 74541 4050 74240 Octal Buffer 4503 40106 7407 74240 74244 74365 74541 4050 74241 Octal Buffer 4503 40106 7407 74240 74241 74365 74541 4050 74244 Octal Buffer 4503 40106 74259 8 Bit Addressable Latch 4099 74266 Quad 2 Input XOR Gate 7486 4030 4070 4077 74273 Octal D Type Flip Flop 7474 741 75 401 3 40174 74283 4 Bit Binary Full Adder 7483 7407 74240 74241 74244 74541 4050 74365 Hex Buffer 4503 40106 74373 Octal D Type Latch Inverting 74374 74533 74573 74574 4042 Tri State 74374 Octal D Type Latch 74373 74533 74573 74574 4042 74390 Dual Decade Counter 7490 401 7 4510 74393 Dual 4 Bit Binary Counter 7493 74161 74163 74193 4029 74533 Octal D Type Latch 74373 74374 74573 74574 4042 7407 74240 74241 74244 74365 4050 74541 Octal Buffer 4503 40106 74573 Octal D Type Latch 74373 74374 74533 74574 4042 74574 Octal D Type Latch 74373 74374 74533 74573 4042 CMOS Device Summary Device Function Similar Devices 4001 Quad 2 Input NOR Gate 7402 4009 Hex Inverter 7404 7405 7406 7414 4049 4069 4011 Quad 2 Input NAND Gate 7400 7403 74132 4093 40107 4012 Dual 4 Input NAND Gate 7420 135 Khalil Ismailov 4013 Dual D Typ
55. 7402 Quad 2 Input NOR Gate 4001 7427 Triple 3 Input NOR Gate 4025 4001 Quad 2 Input NOR Gate 7402 4025 Triple 3 Input NOR Gate 7427 Khalil Ismailov AND Gates Device Function Similar Devices 7408 Quad 2 Input AND Gate 4081 7411 Triple 3 Input AND Gate 4073 7421 Dual 4 Input AND Gate 4082 4073 Triple 3 Input AND Gate 7411 4081 Quad 2 Input AND Gate 7408 4082 Dual 4 Input AND Gate 7421 OR Gates Device Function Similar Devices 7432 Quad 2 Input OR Gate 4071 4071 Quad 2 Input OR Gate 7432 XOR Gates Device Function Similar Devices 7486 Quad 2 Input XOR Gate 74266 4030 4070 4077 74266 Quad 2 Input XOR Gate 7486 4030 4070 4077 4030 Quad 2 Input XOR Gate 7486 74266 4070 4077 4070 Quad 2 Input XOR Gate 7486 74266 4030 4077 4077 Quad 2 Input XOR Gate 7486 74266 4030 4070 Buffers Device Function Similar Devices 7407 Hex Buffer 74240 74241 74244 74365 74541 4050 4503 40106 74365 Hex Buffer 7407 74240 74241 74244 74541 4050 4503 40106 4050 Hex Buffer 7407 74240 74241 74244 74365 74541 4503 40106 4503 Hex Buffer 7407 74240 74241 74244 74365 74541 4050 40106 40106 Pes Buffer 7407 74240 74241 74244 74365 74541 4050 4503 Schmitt trigger 138 Digital Logic Design Inverters
56. B4 01 X4 1 0 A3 Lek B3 x3 7402 Quad Dual Input NOR Gate o EAENE o N o EE o MEN o MEN MEME oo MEE 7404 Hex Inverter o ANE ME o MEN o ME o EN o ME o MEE Vcc X A NOR B NOR AB X4 00 B4 01 A4 10 x3 11 B3 A3 Vcc X A INV AX A6 01 X6 10 A5 X5 A4 X4 158 Digital Logic Design 7408 Quad Dual Input AND Gate Al Bl X1 A2 B2 X2 GND 1 o 14 mn w HR N H HR mn e Nel Vcc B4 A4 X4 B3 A3 x3 7410 Tri Triple Input NAND Gate Al Bl A2 B2 C2 X2 GND o 14 mn w H N mn mn mn e Nol Vcc x C1 X1 C3 B3 A3 x3 7411 Tri Triple Input AND Gate Al Bl A2 B2 C2 X2 GND o mn Bs mn w mn N mn mn mn e Nol Vcc X C1 X1 C3 B3 A3 x3 X A AND B A NAND B NAND C A AND B AND C 159 AND AB X NAND ABC X AND A B CX Khalil Ismailov 7420 Dual Quad Input NAND Gate A 1 14 Vcc X A NAND B NAND C NAND DNAND ABCDKX B 2 13 A2 0000 NC 3 12 B2 000 11 NC 0 0 1 0 10 02 001 D2 0100 X2 010 0110 011 7427 Tri Triple Input NOR Gate Bl 1 FE Vcc X A NOR B NOR C NOR o HEN o MEE o MEE o MER c MER co MEE 7432 Quad Dual Input OR Gate Al 1 esas Br ma X AORB OR 5 o EM o ANE o MEE o MEN o MEN oo MEE
57. Device Function Similar Devices 7404 Hex Inverter 7405 7406 7414 4009 4049 4069 7405 Hex Inverter Open collector 7404 7406 7414 4009 4049 4069 7406 Hex Inverter Open collector 7404 7405 7414 4009 4049 4069 7414 Hex Inverter Schmitt trigger 7404 7405 7406 4009 4049 4069 4009 Hex Inverter 7404 7405 7406 7414 4049 4069 4049 Hex Inverter 7404 7405 7406 7414 4009 4069 4069 Hex Inverter 7404 7405 7406 7414 4009 4049 Interface Devices Device Function Similar Devices 74240 Octal Buffer 7407 74241 74244 74365 74541 4050 4503 40106 74241 Octal Buffer 7407 74240 74244 74365 74541 4050 4503 40106 74244 Octal Buffer 7407 74240 74241 74365 74541 4050 4503 40106 74373 Octal D Type Latch 74374 74533 74573 74574 4042 Inverting Tri State 74374 Octal D Type Latch 74373 74533 74573 74574 4042 74533 Octal D Type Latch 74373 74374 74573 74574 4042 74541 Octal Buffer 7407 74240 74241 74244 74365 4050 4503 40106 74573 Octal D Type Latch 74373 74374 74533 74574 4042 74574 Octal D Type Latch 74373 74374 74533 74573 4042 Counters Device Function Similar Devices 7490 Decade Counter 74390 4017 4510 7493 4 Bit Binary Counter 74161 74163 74193 74393 4029 74161 4 Bit Binary Counter 7493 74163 74193 74393 4029 74163 4 Bit Binary Counter 7493 74161 74193 74393 4029 74193 Dual 4 Bit Binary Counter 7493 74161 74163 74393 4029 74390 Dual Decade Counter 7490 4017 4510 74393 Dual 4 Bit Binary Counter 7493 74161 74163 74193 4029
58. Dual Input NAND Buffer OC 7440 14 2 Quad Input NAND Buffer K155JIA6 7442 16 BCD to Decimal Decoder Driver K155HJI6 7445 16 BCD to Decimal Decoder Driver K155HJI24 7446 16 BCD to 7 Segment LED Decoder Driver 7447 16 1 BCD to 7 Segment LED Decoder Driver 7448 16 BCD to 7 Segment LED Decoder 7449 14 BCD to 7 Segment LED Decoder K155IIIIA 7450 14 2 Dual Input AND inverter gate K155JIP1 7451 14 2 Dual Input AND OR K155JIP11 7453 14 4 Wide AND OR inverter gate K155JIP3 7454 14 4 Dual Input Inverter K155JIP13 7455 2 Wide 4 Input AND OR INVERT Gate K155JIP4 74H version is expandable 7460 Dual 4 input Expander K155JI I1 7464 4 2 3 2 Input AND OR inverter gate K155JIP9 7465 4 2 3 2 Input AND OR inverter gate K155JIP10 7470 14 Gated edge triggered J K Flip Flop 7472 14 J K Master Slave Pulse Triggered J K FF K155TB1 7473 14 2 J K Flip Flop with Clear 7474 14 2 D Flip Flop With Preset and Clear K155TM2 7475 16 1 4 bit Bistable Latches K155TM7 7476 16 2 J K Flip Flop K155TK3 7477 16 2 4 bit Bistable Latches K155TM5 142 Digital Logic Design 7478 14 2 Edge Triggered J K Flip Flop K155TB14 7480 14 e Gated Full Adder K155HM1 7481 16 bit Random Access Memory K155PY1 7482 16 1 Single 2 bit Binary Full Adder K155HM2 7483 16 1 4 bit Binary Full Adder K155HM3 7484
59. JIII10 74366 16 6 Three State Inverting Buffer K155JIH6 74367 16 6 Three State Buffer K155JIIT11 74368 16 6 Three State Inverting Buffer K155JIH7 74373 20 Octal Transparent D Latch K155HP22 74374 20 8 D Flip Flop Tri State K155HP23 74375 16 4 bit Bisettable Latch 74377 20 8 D Flip Flop With Clock Enable K155HP27 74378 16 6 D Flip Flop With Clock Enable 74379 16 4 D Flip Flop With Clock Enable K155TM10 74381 20 ALU Function Generator K155HK2 74382 e 4 bit Arithmetic Logic Unit ALU 74385 Quad 4 bit Adder Subtractor K155HM7 74386 14 4 Dual Input XOR gate 74387 16 1024 bit PROM OC 74390 16 2 Decade Ripple Counter K155HE20 74393 14 2 Modulo 16 Counter K155HE19 74395 4 bit Universal Shift Registers with Three K155HP25 State Outputs 74396 16 8 Storage Register K155HP43 74398 e 4 2 port Register 74399 16 4 Dual Input Multiplexer Dual Port Register K155KII20 74401 Cyclic Redundancy Check CRC Gen Check 74402 Serial Data Polynomial Generator Checker 74413 64x4 FIFO w Parallel I O 74425 14 Quad Bus Buffer 74426 14 Quad Bus Buffer 74433 e FIFO 146 Digital Logic Design 74450 e 16 to 1 Multiplexer with Complementary K155JIP7 Outputs 74451 Dual 8 to 1 Multiplexer K155JIH5 74452 Dual Decade Counter Synchronous K155JIA18 74465 O
60. Measurements Outputs alb c djelf g BCD Code Number Expected Number Observed 0000 0010 0100 0110 1000 1001 1100 1111 In the space provided below determine minimized expressions and design corresponding circuit for the assignments 5 2 and 5 3 using required gates 46 Digital Logic Design Assignment No K maps and minimized Boolean expressions Designed logic circuit 47 EXPERIMENT DESIGN WIIH MULTIPLEXERS AND DEMULTIPLEXERS OBJECTIVES 1 Understand the operation of integrated circuits used for multiplexing and demultiplexing 2 Design multiplexing and demultiplexing circuitry using appropriate integrated circuits EQUIPMENT REQUIRED Digital Logic Trainer Integrated circuits See Assignments BASIC INFORMATION There are many applications where it is required to use one wire or other transmission path to carry signals from two or more sources This process is called multiplexing and the circuits which accomplish this are called multiplexer MUX circuits Essentially a multiplexer circuit is an electronic switch which has the capability of connecting one line from a number of input lines to an output line as determined by the binary input values supplied to a few select lines A number of chips are available to implement the more commonly encountered multiplexer requirements They vary from a 2 to 1 multipl
61. Note that this circuit also solves the problem of circuit initialization When power is first applied no matter what the initial state of the flip flops the register will become set to its normal state after several clock pulses The circuit in Fig 12 2 b operates in a similar fashion except the NAND gate acts as a one stuffer filling the register with ones until all flip flops but the last have been set after which condition a zero will be fed into the serial input Thus this circuit is an active LOW self correcting ring counter cea Een a a ee FRA Ds gt D Di D D Ds gt D Di D D TY CPO 7495 en 7495 CP1 CP1 Q Qi Q Q Qo Q Q Q Clock Clock Output Output a Active high circuit b Active low circuit Fig 12 2 Self correcting ring counter diagrams Another popular shift register counter is the Johnson counter In this type of circuit the complement of the serial data output is fed back to the serial data input A 3 bit version of this circuit using D flip flops is shown in Fig 12 3 The circuit illustrates the use of a simple RC circuit to provide power up initialization by briefly holding the direct reset lines LOW The values of R and C are not critical 1 kQ and 0 01 uF work well Note that there are 6 states for the 3 bit counter In general for an N bit Johnson counter there are 2N normally used states and therefore 2N 2N unused states Although there are few
62. ODE DP ANODE DP CATHOPDE DP D CATHODE NO 1 C CATHODE NO 1 C ANODE NO 1 E ANODE NO 2 CATHODE a b DP r Eamon awone 2 anope a e 7 CATHODEa ANODE a ANODE a b DP CATHODE a b DP CATHODE c d DP CATHODE NO 1 D ANODE NO 2 G CATHODE NO 2 G ANODE NO 2 C CATHODE NO 2 ANODE DE EN ANODE CATHODE ANODE c d ANODE f CATHODE d ANODE d NO PIN E CATHODE NO 1 DP CATHODE NO 2 DP ANODE NO 2 B CATHODE NO 2 D CATHODE NO 2 B ANODE NO 2 A ANODE NO 2 A CATHODE NO 2 ANODE a EEE E DIGIT NO 2 ANODE DIGIT NO 2 CATHODE DIGIT NO 1 ANODE DIGIT NO 1 CATHODE B CATHODE NO 1 B ANODE NO 1 A CATHODE NO 1 A ANODE NO 1 GCATHODENO G ANODE NO 1 NOTES 1 ALL DIMENSIONS IN MILLIMETRES INCHES 2 ALL UNTOLERANCED DIMENSIONS ARE FOR REFERENCE ONLY 3 REDUNDANT ANODES 4 REDUNDANT CATHODES 5 FOR HDSP 5600 5700 SERIES PRODUCT ONLY 167 Khalil Ismailov Internal Circuit Diagram Absolute Maximum Ratings AlGaAs Red HER Yellow Green HDSP H150 HDSP 5500 HDSP 5700 HDSP 5600 Description Series Series Series Series Average Power per Segment or DP 05 105 Peak Forward Current per 60151 mA Segment or DP DC Forward Current per Segmentor DP Forward Current per DC Forward Current per Segmentor DP or DP i al EE TET omastaan e ee fe Fe ee S Lead Solder Temperature for 3 Seconds 1 60 mm 0 063 in below seating plane
63. P 5700 and Green HDSP 5600 displays are categorized for dominant wavelength The category is designated by a number adjacent to the luminous intensity category letter 170
64. QA QD low The counter may be preset by placing the desired binary number on the inputs A D and briefly making the preset input low Note that a clock pulse is not required to preset unlike the 74160 3 counters The inputs A D may be left unconnected if not required Connecting counters with separate up and down clock inputs in a chain The diagram below shows how to link 74192 3 up down counters with separate up and down clock inputs notice how carry and borrow are connected to the up clock and down clock inputs respectively of the next counter carry feset up up down counter borrow down QD OC OB OA Decoders 7442 BCD to decimal 1 of 10 decoder 42 to 46V HC 5V LS HCT The 7442 outputs are active low which input A 1 means they become low when selected but are high at other times They can input B 2 sink up to about 20 mA input C 4 The appropriate output becomes low in input D 8 response to the BCD binary coded output Q9 decimal input For example an input of binary 0101 5 will make output Q5 low and all other outputs high 9 output Q7 The 7442 is a BCD binary coded decimal decoder intended for input values O to 9 0000 to 1001 in binary With inputs from 10 to 15 1010 to 1111 in binary all outputs are high Note that the 7442 can be used as a 1 0f 8 decoder if input D is held low 156 Digital Logic Design 7 segment Display Drivers 7447 BCD to 7 segment display driver input B
65. a Demonstrate the circuit for your instructor 103 Khalil Ismailov CLOCK 5 V 45 V Qa Qs Qc Qo CLOCK START s Fig 11 6 Parallel to serial data converter 5V ov 5V ov 5V ov 5 V Qp 0 V Timing Diagram 11 1 104 EXPERIMENT SHIFT REGISTER COUNTERS OBJECTIVES 1 Understand the operation and properties of ring and Johnson counters 2 Design ring counters using flip flops or integrated circuit registers including provisions for self starting and self correction 3 Design Johnson counters using flip flops or integrated circuit registers including provisions for self starting and self correction EQUIPMENT REQUIRED Digital Logic Trainer 2 7474 1 7496 and 1 74194 integrated circuits Other integrated circuits and components as required BASIC INFORMATION Shift registers can easily be transformed into counters by feeding back some function of the stored data into the serial data input As the register is clocked it will undergo a repetitive cycle of state transitions i e it will function as a counter depending on the type of feedback used and the initial data stored in the register The simplest and most widely used shift register counter is the ring counter in which the serial output is fed back to the serial input Ring counters can be designed using flip flops or integrated circuit registers Fig 12 1 shows a 3 bit ring counter designed
66. a Qs Qc Q Fig 11 5 Ring counter circuit Assignment 11 4 Parallel to serial data conversion 1 Examine the circuit of Fig 11 6 This circuit operates as a parallel to serial data converter It first loads the data present at A through D and then shifts the data out of Qo The shifting of the loaded data is controlled by the occurrence of a START pulse Since the START pulse occurs asynchronously to the clock pulses the two flip flops are used to synchronize the loading and shifting of the 74194A Assume that the START pulse has been inactive and that clock pulses have been continuously applied for a long time before tO see the waveform in Fig 11 6 Draw the waveforms you might expect to appear at QX Qx QY and Qd in response to the START pulse shown in the figure Use Timing Diagram 11 1 Wire the circuit in Fig 11 6 Use a normally HIGH pushbutton switch for the START pulse Connect a square wave generator set at 100 Hz to input CLK of the 74194A Connect toggle switches to A through D and set these switches to 1101 Connect one vertical input of the oscilloscope to the output of the generator Use the other vertical input to monitor first Qx Qx Qv and Qv in that order Do this by pulsing the START pushbutton several times while connected to each output You may have to slow the clock down or speed it up so that the outputs are easily observed Verify that output waveform Qp is the serial representation for the parallel dat
67. able maximum The only way to avoid this is to make R very small but this will drain a large current from the power supply when the switch is closed Es V 5 Vec A Veo TIN Vm Logic Vout Vw re Vout GND Circuit GND H cui GND g GND Power SPST Supply Switch 15 v psv 51 4 f r r Va is Vec Vcc Vin Logic Vout Logic Vout I y Circuit Circuit tie GND GND ora c d Fig 0 1 Generating a static logic level signal The circuit shown in d functions much better the student still needs to understand its limitations In this circuit when the switch is closed the input to the test circuit is connected directly to ground so that the LOW voltage is at zero volts regardless of the magnitude of the input current When the switch is Khalil Ismailov open the test circuit input voltage is connected to the 5 0 V supply through the resistor R Note that whatever input current Ix is required by the circuit under test must flow through R and will therefore produce a voltage drop reducing the HIGH level input voltage V to a value of 5 RI There are two factors to consider First HIGH level input currents are considerably lower than LOW level input currents due to the nature of the circuitry used in the integrated circuits Second the HIGH level input voltage can be allowed to drop to as low as 2 0 V without violating circuit specifi
68. able 1 5 NAND gate circuit experimental results Data Switches Output of the TTL Logic Output Logic B Indicator ON OFF Level 0 1 0 0 0 1 1 0 1 1 Verify that your results agree with the truth table for NAND gate 16 Digital Logic Design 3 Disconnect the toggle switch from input B of the NAND gate What will the state of output X be when A 0 When A 1 Verify your results 4 Connect the output GND and TTL of a FG04 Function Generator on the Y 0039 Digital Logic Trainer to input B and set the generator to 1 kHz x 1k position Remove the output connection to the TTL Logic Indicator and connect one of the vertical inputs of the oscilloscope in its place Connect the output of the function generator to the other vertical input of the oscilloscope and trigger internally using this channel Set input A alternately to O and 1 and observe the effect on the output Draw the waveforms displayed on the oscilloscope for each setting of a using Timing Diagrams 1 3 and 1 4 SV ov Timing Diagram 1 3 5V 0V Timing Diagram 1 4 Combinational Logic 1 Wire the circuit shown in Fig 1 9 Do not forget the power supply connections Binary Switches Output X AB C Fig 1 9 Experimental combinational logic circuit 17 Khalil Ismailov 2 Connect the TTL Logic Indicator to output 3 Setthe toggle switches to each i
69. ach combination includes the maximum number of squares CD CD CD CD CD CD CD CD AB 1 AB 1 1 AB 1 1 AB 1 1 AB 1 1 AB 1 1 AB 1 1 AB 1 1 a Function X b Function Y Fig 4 4 Simplifiable K maps As an example consider the function mapped in Fig 4 4 a The column of 1 s on the right can all be combined the two 1 s in the lower left column can be combined with the 1 s on the opposite ends of the rows and the remaining 1 has no adjacent squares so that it cannot be combined The minimized functional expression is shown in 4 2 X CD AD ABCD 4 2 Equation 4 2 is the minimized 2 level SOP expression for the function X It should be noted that any SOP or POS expression can be implemented by a 2 level circuit input inverters necessary to generate variable complements are ignored in determining level since in many practical applications variables are available in both true and complemented form To find the minimized POS form for a function it is simply necessary to find the minimized SOP form for the function complement and then complement 36 Digital Logic Design the result Consider the function Y shown in Fig 4 4 b Examining the empty squares these would be 1 for the complement of the function it can be seen that 2 4 square combinations can be made center and corners The resulting expression and corresponding minimized POS form are shown in Equation
70. adder using Table 7 1 to record your observations on the Sum and Carry outputs Table 7 1 Test results for the half adder circuit Inputs Outputs oO ol gt OD of 3 Design the full adder Using the K maps in Fig 7 3 find minimized SOP expressions for the sum and carry outputs Build a corresponding 2 level circuit using only NAND gates and inverters 67 Khalil Ismailov 4 Connect toggle switches to each input and LED monitors to both outputs Test the full adder using Table 7 2 to record your observations on the Sum and Carry outputs Table 7 2 Test results for the full adder circuit Inputs Outputs A B Ci S C 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 5 Two bit ripple adder Connect the half adder and full adder together according to the diagram shown in Fig 7 7 to form a two bit ripple adder Toggle switches Toggle switches LED monitor LED LED monitor monitor Fig 7 7 2 bit ripple adder Test the operation of the adder by setting the toggle switches to several different values and observing the sum and carry indicated by the LED monitors Demonstrate the circuit operation for your instructor 6 7483 IC adder operation Install a 7483 IC on the circuit board and make the following connections a Connect Vcc to 5 V and GND to power ground b Connect Co to pow
71. ample of combining AND and OR gates To analyze this circuit it would be necessary to consider what happens for all possible inputs It would be rear today to find a logic gate built from discrete transistors Integrated circuits ICs have been used exclusively for logic gates for the past several years The most widely used digital circuit family is the transistor transistor logic TTL family Examples are a 5400 or a 7400 series The 5400 series is a military version of the commercial 7400 series The AND gate is a 7408 The OR gate is a 7432 The 5 V Vcc attaches to pin 14 in both devices Likewise the ground pin is pin 7 This is not always true so refer to data manuals or published pin outs before you make any connections Also note that as in all other ICs the location of pin 1 is indicated by either a dot over the pin or the notch on one end of the package Note that in TTL a disconnected input is equivalent to the input set at high A B Inputs Output C p Fig 1 3 Combinational logic circuit PROCEDURE OR Gate 1 Connect the 7432 OR gate as shown in Fig 1 4 Note that 5 V and ground connections are not shown on logic diagrams but you must be sure to connect them For the reminder of this experiment you may use wire connections to the switches on the Digital Logic Trainer Y 0039 to connect the inputs to Logic 1 or ground for the 1 and 0 inputs 12 Digital Logic Design 2 Connect the output to the DMM
72. and assemble the connections to implement the circuit illustrated in Fig 6 9 Apply power to the circuit Vcc pin 16 GND pin 8 Test the circuit using appropriate data points Assignment 6 4 Design construct and test a circuit using an 74151 that will convert 8 bits of parallel data to a serial stream of data on the output Use an LED to signal a logic 1 output on the output line 1 2 Construct the circuit and write the pin numbers on the designed circuit Place the 74151 chip on a breadboard and assemble the connections to implement the circuit illustrated in Fig 6 10 Connect any data logic 1 s or 0 s to the inputs DO D7 of the 74151 You must simulate a counter circuit on the A B and C inputs to select each bit of data to be placed on the output line Apply power to the circuit Vcc pin 16 GND pin 8 Stimulate inputs A B and C and data inputs DO through D7 to demonstrate circuit operation 58 Digital Logic Design 74151 7 D7o D6 2 D5 2 Logic 4 D40 switches D3 2 D20 D10 Logic D0o switches A or counter 1 Bo output Co signals Fig 6 10 Conversion of parallel data to a serial stream Assignment 6 5 Using a 74151 and a 74138 design a multiplexer demultiplexer circuit which will take 8 data lines multiplex them onto a single output line and then demultiplex the single data line onto 8 output lines Fig 6 11 The selection of the input and output data lines mu
73. and the operation and properties of integrated circuit registers EQUIPMENT REQUIRED Digital Logic Trainer 2 7474 2 74LS76 and 2 74194 integrated circuits Other integrated circuits and components as required BASIC INFORMATION A register is a linear array of flip flops that is used for storage and simple processing of data The general structure of hypothetical 5 bit register is shown in Fig 11 1 Parallel data in Dp Di D D Da Control Serial data in Serial data out Clock n m la m IR Parallel data out Fig 11 1 General register structure The register structure outlined in Fig 11 1 illustrates all of the capabilities that can be found in a register circuit In this example there are five flip flops so that the register can store five bits of data which can be input to the flip flops 98 Digital Logic Design in parallel fashion using the inputs Do to Da or one bit at a time in serial fashion using the serial data input Stored data are available either serially at serial data out or in parallel at the Qo to Qs outputs Serial operation of the register is accomplished by shifting the data to the right with the bit on the serial data input being stored in the least significant flip flop Qo and the Q output of the most significant flip flop Qs being available at the serial data output Shift right operation is synchronous while parallel load operation can be either synchronous or asynchronous depending o
74. aximum Intensity Bin Limitation Minimum Intensity Bin 2 0 No Minimum Intensity Bin Limitation Device Configuration Colorl 1 1 Common Anode 3 Common Cathode Device Specific Configuration Refer to Respective Datasheet Package H 14 2 mm 0 56 inch Single Digit Seven Segment Display Notes 1 For codes not listed in the figure above please refer to the respective datasheet or contact your nearest Agilent representative for details 2 Bin options refer to shippable bins for a part number Color and Intensity Bins are typically restricted to 1 bin per tube exceptions may apply Please refer to respective datasheet for specific bin limit information 166 Digital Logic Design Package Dimensions FRONT VIEW A B TOP END VIEW A B C D 10 LUMINOUS COLOR BIN NOTE 5 INTENSITY 51 CATEGORY 520 TYP t x x 14 22 E 10 56 1 047 8 r 2 54 100 DATE TV COD 3 95 155 MIN x id l ae l d 1234 481 6 86 Las 1 270 12 573 SIDE VIEW A B C D 496 MAX FRONT VIEW C D TOP END VIEW E F COLOR BIN INOTE 5 LUMINOUS INTENSITY CATEGORY 762 030 DATE CODE TE B MIN E f YP 6 15 14 13 12 1110 SIDE VIEW rm NO 1 FRONT VIEW E F FUNCTION A B c D CATHODE e ANODE e CATHODE c ANODEc E CATHODE d ANODE d ANODE c d CATHODE c d ANODE CATHODE CATHODE b ANODE b c c ANODE a b DP CATH
75. b Construct the circuit using the diagram you drew in step a Connect toggle switches to inputs A B and C and a TTL Logic Indicator to the circuit output Set the toggle switches to each input combination listed in Table 2 3 and record the output value observed Table 2 3 Output logic level at F for an original and simplified circuits three inputs Inputs Output Logic Level at F A B C For an Original Circuit For a Simplified Circuit 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 25 Khalil Ismailov c Simplify F using the DeMorgan s Theorems d Draw the logic diagram for the simplified expression e Construct the simplified circuit and record the output values in the appropriate column of Table 2 3 Verify the results in both columns for F 26 EXPERIMENT BASIC DESIGN OF COMBINATIONAL CIRCUITS OBJECTIVES 1 Design combinational circuits using a verbal description of the requirements 2 Design combinational circuits using truth tables to specify requirements EQUIPMENT REQUIRED Digital Logic Trainer Digital IC chips as required BASIC INFORMATION Many simpler combinational circuits can be designed directly from a verbal description of the requirements For example consider the following problem A circuit must be designed to start a pump motor The motor will start if a HIGH logic level is applied to a control relay This motor run
76. ble to verify correct operation Hint Factor the minimized SOP expressions to avoid using a 3 input gate The best circuit will be a 3 level circuit which can be built with one inverter and one 7400 chip CD CD CD CD CD CD CD CD AB 1 AB 1 1 1 AB 1 1 AB 1 1 AB 1 1 AB 1 1 AB 1 1 1 AB 1 1 1 a Function X b Function Y Fig 4 5 K maps for Assignment 4 3 In the space provided below determine minimized SOP or and POS expressions and design corresponding circuit for the given assignment using required gates Assignment No K map CD CD CD CD AB AB AB AB 38 Digital Logic Design Minimized SOP or and POS expressions Designed logic circuit Truth Table Output 39 EXPERIMENT CO DE CONVERTERS OBJECTIVES 1 Understand unit distance codes design circuitry to convert between Gray code and binary 2 Exercising the design of combinational circuit to convert between different BCD codes 3 Use 7 segment displays and 7 segment decoder integrated circuits to design BCD display circuitry EQUIPMENT REQUIRED Digital Logic Trainer Digital Multimeter DMM Integrated circuits See Assignments BASIC INFORMATION Code conversion is frequently required in digital system design particularly at the interface between the inter
77. cations Both of these mean that in most applications the resistor R can be made reasonably large so that the HIGH level voltage is properly defined without drawing too much current from the power supply when the switch is closed The resistor R is known as pull up resistor When designing static logic level sources its value must be chosen to produce adequate voltage levels for the circuits to be tested In almost all cases values between 1 0 kQ and 10 0 k2 will work well The student is cautioned however that if a single switch circuit is to be used to provide multiple inputs to a test circuit it may be necessary to adjust the value of the pull up resistor to maintain adequate HIGH level voltages In building a logic circuit facility the student will need multiple static signal sources Fight such circuits should be sufficient for most Assignments in the Laboratories The second type of signal generating requirement necessary for testing logic circuits is the ability to generate a single pulse from a manual switch This type of circuit is referred to in the Laboratory equipment lists as a push button manual pulser The pulse produced by the pulser must be clean with sharp edges Also for greatest versatility the pulser should be able to produce both HIGH going as well as LOW going pulses A simple SPST switch circuit such as that of Fig O d cannot be used because of the problems of switch bounce When the mechanical contacts of the sw
78. cillator K1551T6 74626 Dual Voltage Controlled Oscillator with K155IT2 Enable Control Two Phase Outputs 74629 16 2 Voltage Controlled Oscillator 74640 20 Tri State Octal Bus Transceiver K155AII9 147 Khalil Ismailov 74641 Octal Bus Transceiver OC K155AII7 74643 Octal Bus Transceiver with Mix of Inverting K155AII16 and Noninverting Three State Outputs 74644 Octal Bus Transceiver OC 74645 20 Tri State Octal Bus Transceiver K155AII8 74646 24 8 Trans Reg Three State 3 Wide K155BA1 74648 8 Bus transceiver w tristate output K155BA2 74651 transceiver register K155AII17 74652 transceiver register K155AIDA 74657 8 bidir xceive w 8 bit parity gen chk amp 3 state 74670 16 e 4x4 Register File 3 State K155HP26 74673 16 bit Ser Parallel shift reg w com ser i o 74675 16 bit Serial Parallel shift register 74676 16 bit Parallel Serial shift register 74682 20 8 bit Comparator 74684 20 8 bit Comparator 74685 20 8 bit Comparator 74688 20 8 bit Magnitude Comparator 74779 8 bit bidir binary counter w tristate outputs 74794 8 bit register w readback 74804 o Hex 2 input NAND Drivers K155JIA20 74805 e Hex 2 input NOR Drivers K155JIE8 74808 M Hex 2 input AND Drivers K155JIH7 74821 e 10 bit D Flip Flo
79. creases the speed of the adder circuit but it does require additional circuitry The above discussion focuses mainly on the design of addition circuitry A full subtractor circuit could be designed using the same process as was used for the full adder However adder circuits can be used to perform subtraction if the number being subtracted subtrahend is changed to its two s complement Many of the commonly required arithmetic functions are available as medium scale integrated MSI circuits in both the TTL and CMOS families Whenever possible these chips should be used in practical designs to minimize chip count A typical example is the 7483 74283 adder chip shown in Fig 7 6 CMOS equivalents are the 4008 and 74HC283 This chip adds two 4 bit words A and B and a carry input CI to produce a 4 bit sum X and a carry out CO The carry out function is generated by carry look ahead circuitry so that the maximum specified propagation delay from carry in to carry out is just 20 nsec The CI and CO connections permit the chip to be cascaded to form longer adders If the 7483 is used to add only 4 bit words the CI input must be held low Fig 7 6 7483 74283 adder 66 Digital Logic Design LABORATORY ASSIGNMENTS Assignment 7 1 1 Design the half adder Build a corresponding 2 level circuit using only NAND gates and inverters 2 Connect toggle switches to the two inputs and LED monitors to both outputs Test the half
80. ctal Buffer with Three State Outputs K155AIT14 74472 20 512x8 3 state PROM 74474 24 512x8 3 state PROM 74490 16 2 BCD decade ripple counter 74521 20 Octal Comparator 74524 Octal Registered Comparator 74533 Octal Transparent Latch w tristate output K155HPA40 74534 8 D Flip Flop K155HP41 74537 1 of 10 decoder w tristate outputs K1554122 74538 1 of 8 decoder w tristate outputs 74539 2 1 of 4 decoder w tristate outputs 74540 20 8 Tri State Inverter Buffer K155AII12 74541 20 8 Non Inverting Buffer Line Driver K155AII13 74543 8 Registered Transceiver 74544 8 Registered Transceiver Inverting 74545 8 Bidirectional Transceiver w tristate outputs 74552 8 Registered Transceiver w parity amp flags 74563 8 D Latch w tristate outputs 74564 8 D Flip Flop w tristate outputs 74569 4 bit bidirectional counter w tristate out 74571 16 512x4 3 State PROM 74573 20 8 D Latch w tristate outputs K155HP33 74574 20 8 D Flip Flop w tristate outputs K155HP37 74579 8 bit binary counter w tristate outputs 74583 4 bit BCD Adder 74590 16 1 8 bit Three State Binary Counter 74593 e 8 Bit Binary Counter with Input Registers K155HE21 and Three State Outputs 74595 16 8 bit Serial to Parallel Shift Register 74620 e 8 Inverting bus transceiver w tristate outputs K155AII25 74623 8 Inverting bus transceiver w tristate outputs K155AII26 74624 14 1 Voltage Controlled Os
81. cuit board and make the following connections to one of the D flip flops 1 W N or R Connect V and DC SET to 5 V GND to power ground Connect a toggle switch to the D input Connect a normally HIGH pushbutton switch to the CLK input Connect a normally HIGH pushbutton switch to DC RESET Connect LED monitors to Q and Q or monitor the outputs with a logic probe p 7474 synchronous operation Apply power and monitor the Q output Observe that nothing happens when you toggle the D input switch back and forth This is because the D input is a synchronous input that operates with the CLK input Clear Q to 0 by momentarily pulsing the DC RESET input LOW Set D to 1 and apply a negative going transition at CLK Do this by pressing and holding the CLK pushbutton LOW What happens to Q Now apply a positive going pulse at CLK by releasing the pushbutton switch What happens This proves that the flip flop responds only to positive going transitions Make D 0 and pulse CLK momentarily This should clear Q back to 0 k 7474 asynchronous operation For both DC SET and DC RESET verify the following 1 The inputs are active LOW and do not require a pulse at CLK to become activated 2 The inputs override the synchronous input signals 77 Khalil Ismailov Assignment 8 4 Edge triggered JK flip flop 74LS76 IC Install a 74LS76 IC on the circuit board and make the following connections
82. d Once these are known the next state can be determined This analysis proceeds until all possible states have been analyzed It is best to conduct this analysis in tabular form using a table to list the state transitions The final results of the analysis can best be presented by a state diagram The design of natural binary synchronous counters in which the modulus is a power of 2 is very routine As binary is counted upward the least significant bit LSB toggles at every change The next least significant bit toggles when 91 Khalil Ismailov the LSB is 1 The third least significant bit toggles when both the preceding bits are 1 This pattern continues for counts of any length Therefore to design an N bit binary counter the design procedure is as follows for J K flip flops 1 Tie the J and K inputs of the LSB flip flop high so that it always toggles 2 Tie the J and K inputs of the second least significant flip flop to the Q output of the LSB flip flop so that it toggles when the LSB flip flop is 1 3 Tie the J and K inputs of any other flip flop to the AND of the Q outputs of all preceding flip flops so that it toggles only when all of them are 1 The circuit diagram of a 4 bit binary synchronous counter designed with this procedure is shown in Fig 10 1 The most significant bit MSB and LSB flip flops have been labelled in the Figure Note that the 3 input AND gate could be replaced by a 2 input gate if the output fro
83. d a wire with maximum tension To make a breadboard an array of these clips is embedded in a plastic block which holds them in place and insulates them from each other Fig A 2 114 Digital Logic Design In general the breadboard consists of two terminal strips and two bus strips often broken in the centre Each bus strip has two rows of contacts Each of the two rows of contacts are a node That is each contact along a row on a bus strip is connected together inside the breadboard Bus strips are used primarily for power supply connections but are also used for any node requiring a large number of connections Fach terminal strip has 60 rows and 5 columns of contacts on each side of the centre gap Each row of 5 contacts is a node Fig A 2 Embedded clips Depending on the size and arrangement of the clips we get either a socket strip or a bus strip The socket strip is used for connecting components together It has two rows of short 5 contact clips arranged one above another Fig A 3 Fig A 3 Shorted socket and bus strips The bus strip is used to distribute power and ground voltages through the circuit It has four long 25 contact clips arranged lengthwise Fig A 4 ROO TATT IRC OOO TAA TT RE MONO OH ONO NHO OND ODCOC ODOOO DOODOO OCOODD OCOUR Fig A 4 A bus strip 115 Khalil Ismailov Note that in their infinite wisdom the manufacturer elected not to join the adjacent 25 contact strips
84. d and assemble the connections to implement the circuit illustrated in Fig 6 7 3 Apply power to the circuit Vcc pin 16 GND pin 8 4 Test the completed circuit using appropriate data points 55 Khalil Ismailov f A B C Fig 6 7 f A B C implemented using 4 1 multiplexer b Design construct and test a circuit which uses an 74151 to implement the logic function specified in the truth table Table 6 5 Compare this method with a discrete logic gate implementation To use a multiplexer as a logic function generator the logic function is formed by srtting the data inputs to the appropriate logic level The select inputs become the inputs for the variables specified in the function Table 6 5 Logic function implementation table Inputs Output R S T M 0 0 0 1 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 0 1 1 1 0 Notice from the truth table that M is a 1 for the following input variable combinations 000 010 011 100 101 For all other combinations M is O For this function to be implemented with the multiplexer the data input selected by each of the above mentioned combinations must be connected to a HIGH Vco through pull up resistor All other data inputs must be connected to a LOW ground as shown in Fig 6 8 The logic function is described as M RST RST RST RST RST 56 Digital Logic Design The implementation of this funct
85. d never result in an overflow condition using the 7483 74283 the 7486 and any additional circuitry The range of results that must be accommodated so that overflow does not occur is 63 x2 or 126 to 126 The result requires a total of 8 bits including the sign bit The input values will require only 7 bits including the sign bit In the space provided below draw the corresponding designed circuit and record the test results 69 Khalil Ismailov Assignment No Designed circuit Test results 70 EXPERIMENT PROPERTI ES OF LATCHES FLIP FLOPS OBJECTIVES 1 Understand the operation and properties of commonly used latch and flip flop circuits 2 Conduct laboratory tests to verify the operation of latch and flip flop circuits EQUIPMENT REQUIRED Digital Logic Trainer Dual trace oscilloscope 7400 7402 7474 7475 7476 74LS76 74279 integrated circuits Other integrated circuits and components as required BASIC INFORMATION All of the previous experiments have focused on combinational circuits i e circuits in which the state of the output at any given time depends only on the combination of values on the inputs at that time More generally digital circuits are sequential in nature In sequential circuits the state of the output at any given time is determined by the combination of values on the inputs at that time and at previous times Sequential circuits are therefore characterized by the pro
86. d transition times A signal that fails to meet anyone of these requirements can cause the IC to function incorrectly Common symptoms brought on by improper signal characteristics include flip flops counters and flip flop registers that respond incorrectly to signals at clock clear and preset inputs The characteristic s causing the problem must be determined and brought back into specification Power supply Improper levels Since all IC logic devices use voltage to represent logic levels trouble with the output level of the supply can cause ICs to function improperly A common cause of improper power supply levels is overload This can be particularly true in prototype systems and circuits Symptoms of this type of trouble include the condition where logic HIGH at circuit outputs is less than Vou Disconnecting a few ICs from the power supply will usually cause the level of Vcc to rise if this is the case Using a larger power supply or redesigning the existing one for higher current output will solve the problem Power supply Poor regulation Poor regulation in a power supply will cause Vcc to fluctuate when large numbers of logic circuits are switching states These fluctuations act like noise pulses and can cause false triggering of logic devices This problem is especially significant in TTL circuits 124 Digital Logic Design A symptom caused by this problem is flip flops counters and registers triggering when they a
87. dents is shown in b In this case when the switch is open the input to the circuit is an open circuit so that the input voltage is undefined which will not produce correct operation of the circuit to be tested There are two possible solutions which are shown in Fig O I c and d In both of these the switch is in series with a resistor between the terminals of the power supply but the circuit shown in c will not usually be satisfactory and the circuit in d is one that should be used This circuit is referred to in the Laboratories as a static logic level signal source The reasons why the circuit Digital Logic Design in c will not operate correctly are due to the properties of the inputs to TTL and other integrated circuits In order for TTL circuits to function correctly the LOW input level must be below 0 8 V while the HIGH input level must be above 2 0 V The circuit in c will always produce a correct HIGH level of 5 0 V when the switch is open and the logic under test draws its current directly from the supply However when the switch is closed current will flow out of the circuit input through the resistor R to ground R is called a pull down resistor This produces a voltage drop across R and a LOW level input voltage Vi which is above ground In TTL circuitry current flow when the input voltage is HIGH Thus an appreciable current flowing through R when the switch is closed can bring the input voltage above the allow
88. e Multiplexer 1 Multiplexer 2 Strobe Select lines Output Strobe Select lines Output 1G 1 S0 1Y 2G 1 so 2Y 1 X X 0 1 X X 0 0 0 0 1DO 0 0 0 2DO 0 0 1 1D1 0 0 1 2D1 0 1 0 1D2 0 1 0 2D2 0 1 1 1D3 0 1 1 2D3 The 74151 an 8 to 1 MUX shown in Fig 6 3 functions in an identical manner except both true and complement outputs are available Selection lines S2 S1 and SO select the particular input to be multiplexed and applied to the output Strobe S acts as an enable signal Table 6 2 shows the multiplex function of 74151 in terms of select lines 74151 Fig 6 3 74151 8 1 IC multiplexer 50 Digital Logic Design Table 6 2 74151 truth table Strobe Select lines Output G S2 i So Y 1 X X X 0 0 0 0 0 DO 0 0 0 1 D1 0 0 1 0 D2 0 0 1 1 D3 0 1 0 0 D4 0 1 0 1 D5 0 1 1 0 D6 0 1 1 1 D7 The 74150 is a 16 to 1 MUX which therefore requires four select lines to select one of the 16 inputs Note that the output Y is inverted for this chip so that the output in this case would be the complement of the level applied to D9 No experiments using 74150 are assigned in this manual so its schematic diagram and truth table are not presented as well Multiplexers are versatile circuits that are used in applications such as data selection cascaded operation binary wo
89. e Flip Flop 7474 74175 74273 40174 4014 8 Bit Shift Register 74161 74164 4015 4015 8 Bit Shift Register 74161 74164 4014 4016 4 Channel Analogue Multiplexer 4052 4017 Decade Counter 7490 74390 4510 4018 BCD Counter Presettable 4518 4021 8 Stage Shift Register 4094 4023 Triple 3 Input NAND Gate 7410 4025 Triple 3 Input NOR Gate 7427 4026 7 Segment Display Decade Counter 4033 4027 Dual J K Flip Flop Master Slave 7473 7476 4029 4 Bit Binary Counter 7493 74161 74163 74193 74393 4030 Quad 2 Input XOR Gate 7486 74266 4070 4077 4033 7 Segment Display Decade Counter 4026 4042 Quad D Type Latch Clocked 74373 74374 74533 74573 74574 4047 Multivibrator 4538 4049 Hex Inverter 7404 7405 7406 7414 4009 4069 7407 74240 74241 74244 74365 7 2080 E PUROT 4541 4503 40106 4052 Dual 4 Channel Analogue 4016 Multiplexer 4056 BCD to 7 Segment Decoder 7447 7448 4511 4063 4 Bit Magnitude Comparator 7485 4585 4068 8 Input NAND Gate 7430 4069 Hex Inverter 7404 7405 7406 7414 4009 4049 4070 Quad 2 Input XOR Gate 7486 74266 4030 4077 4071 Quad 2 Input OR Gate 7432 4073 Triple 3 Input AND Gate 7411 4077 Quad 2 Input XOR Gate 7486 74266 4030 4070 4081 Quad 2 Input AND Gate 7408 4082 Dual 4 Input AND Gate 7421 4093 KE ek NAND Gate Schmitt 7400 7403 74132 4011 40107 4094 8 Stage Shift Register 4021 4098 Dual Monostable Multivibrator 74121 74221 4528 4099 8 Bit Addressabl
90. e Latch 74259 7407 74240 74241 74244 74365 7 4908 dex Butter 4541 4050 40106 4510 Decade Counter 7490 74390 4017 136 Digital Logic Design 4511 BCD to 7 Segment Decoder 7447 7448 4056 4514 4to 16 Line Decoder 74154 4516 Binary Counter Presetable 4520 4518 Dual BCD Counter 4018 4520 Dual Binary Counter 4516 4528 Dual Monostable Multivibrator 74121 74221 4098 4538 Multivibrator 4047 4585 4 Bit Magnitude Comparator 7485 4063 Ls 7407 74240 74241 74244 74365 7 40106 Hex Buffer Schmitt trigger 4541 4050 4503 40107 Dual 2 Input NAND Gate 7400 7403 741 32 401 1 4093 40174 Hex D Type Flip Flop 7474 741 75 74273 4013 NAND Gates Device Function Similar Devices 7400 Quad 2 Input NAND Gate 7403 74132 401 1 4093 40107 7463 usd 2 Input NAND Gate Open 7400 74132 4011 4093 40107 collector 7410 Triple 3 Input NAND Gate 4023 7420 Dual 4 Input NAND Gate 4012 7430 8 Input NAND Gate 4068 74132 Quad 2 Input NAND Gate Schmitt trigger 7400 7403 401 1 4093 40107 4011 Quad 2 Input NAND Gate 7400 7403 74132 4093 40107 4012 Dual 4 Input NAND Gate 7420 4023 Triple 3 Input NAND Gate 7410 4068 8 Input NAND Gate 7430 4093 Quad 2 Input NAND Gate Schmitt trigger 7400 7403 74132 4011 40107 40107 Dual 2 Input NAND Gate 7400 7403 741 32 401 1 4093 NOR Gates Device Function Similar Devices
91. e clock 85 Khalil Ismailov input of the counter and to one vertical input of a dual trace oscilloscope Connect the other vertical input of the oscilloscope to the Q output of flip flop C Trigger on output Q of flip flop C What is the frequency of the signal at C Move the oscilloscope input from C to A Trigger on B What is the frequency of this signal Finally move the oscilloscope input from B to A Trigger on A What is the frequency of this signal Based on your observations what is the mod number of this counter Table 9 1 Test results for the 3 bit ripple counter Clock pulse DP stale 0 0 0 0 1 2 3 4 5 6 7 8 Assignment 9 2 Changing the mod number of a counter Modify the counter circuit so that the wiring is like that shown in Fig 9 4 Fig 9 4 Circuit for Assignment 9 2 86 Digital Logic Design 1 2 Connect the pushbutton to the counter clock input Connect LED monitors to the Q outputs of each flip flop Clear the counter by pulsing it until the LED monitors indicate a count of 000 or by lifting the DC RESET line connection from the NAND gate output and grounding it momentarily then reconnecting it to the NAND gate Using Table 9 2 record the counter output states you observe as you pulse the counter through its new count sequence Determine the mod number of this counter by examining the counter sequence
92. e exclusive OR of binary bits N and N 1 The relationship for converting from Gray to binary is somewhat more difficult to see but careful examination of the truth table shows that binary bit N can be generated by the exclusive OR of Gray bit N with all more significant bits Hence circuitry to convert between 4 bit binary and Gray code would be designed as shown in Fig 5 2 It should be noted that this algorithm can be extended to binary and Gray codes of any length Conversion between binary and BCD is more difficult but MSI chips are available to use in this process The 74184 and 74185 are integrated circuits designed for conversion between binary and BCD Both chips are custom read only memory ROM chips that have been programmed to accomplish BCD to binary conversion 74184 and binary to BCD conversion 74185 B3 t G3 G3 B3 m us PEE es E ud En 14 Fig 5 2 Binary and Gray code conversion The last code conversion application to be discussed is conversion between BCD and 7 segment code Light emitting diode LED display devices are available in DIP packages to permit a visual display of the ten decimal digits Eight LEDs are used connected either in a common anode or common cathode arrangement to display the decimal point and the seven individual segments The decimal digits are displayed by selectively forward biasing the segment diodes to create appropriate illuminated patterns In the common
93. e set to any state Use a manual pulser for the clock Determine the circuit operation for all possible states and record the corresponding state diagram Assignment 12 3 Use a data manual to determine the properties of the 7496 5 bit shift register Using this integrated circuit design a 5 bit active LOW self correcting ring counter which has a control input INIT which when pulsed HIGH will set all flip flops to one so that the first clock pulse following INIT will establish the 01111 state Build the circuit and verify the operation of the INIT control as well as the normal operating sequence of the counter Assignment 12 4 Using the 74194 integrated circuit design a 4 bit self correcting Johnson counter circuit which will generate the waveform shown in Fig 12 5 Build the circuit and test its operation for the normal state sequence confirming the 111 Khalil Ismailov generation of the desired waveform Using the parallel load capability of the register force the circuit into an unused state and clock the circuit until it returns to the normal state sequence thus confirming its self correction ability Counter Clock BLEIBEN ERU Output Waveform Fig 12 5 Johnson counter waveforms 112 REFERENCES Thomas L Floyd Digital Fundamentals 9 e Pearson education Inc 2006 Susan A R Garrod Robert J Borns Digital Logic Analysis Application and Design Saunde
94. e use of Boolean algebra to simplify the equation Instead the simplification is done graphically using the K map The K map contains a cell for each input combination A logic function with n input variables has 2 cells on the K map A two variable K map has 4 cells a three variable K map has 8 cells and a four variable K map has 16 cells Occasionally five variable K maps are formed by using two four variable maps Functions requiring larger K maps are usually handled by computer simulation and Boolean algebra techniques 34 Digital Logic Design Fig 4 2 shows two alternative notations for a K map for 4 variables They are equivalent Each square corresponds to one of the possible combinations or minterms of the 4 variables The combination corresponding to any particular square can be determined from the coordinates of the associated row and column Note that these coordinates are assigned in such a way that in moving from one square to the next either horizontally or vertically only one variable changes from true to complemented or complemented to true form Two squares are defined to be adjacent if this condition applies Note that this property also applies to squares at opposite ends of rows and columns so that these squares are also adjacent Similar maps can be formed for any number of variables though maps for more than 6 variables are generally too unwieldy Boolean functions are mapped by first writing the functi
95. e waveforms on Timing Diagram 12 1 Repeat this procedure for each of the other outputs of the counter The mod number of this counter is The outputs of the counter are are not square waves The frequency of each output is 5 Johnson counter Rewire the ring counter so that it is a Johnson counter Disconnect the square wave generator and reconnect the pushbutton switch to the clock input of the counter Clear the counter Verify the operation of the Johnson counter by pulsing the counter LOW eight times while observing the output Record your observations in Table 12 1 109 Khalil Ismailov svi 2 3 4 5 6 7 8 9 10 11 12 13 14 Clock y HUI M T M Timing Diagram 12 1 Table 12 1 Test results for the Johnson counter Shift pulse Output state Qi Q Q Qo 0 0 0 0 0 1 2 3 4 5 6 7 8 6 Repeat step 4 using Timing Diagram 12 2 The mod number of this counter is The outputs of the counter are are not square waves The frequency of each output is 110 Digital Logic Design Assignment 12 2 12 34 5 6 7 8 9 10 11 12 13 14 Clock K OV 5V Qo 0 V 5 V Qi OV 5V Q2 0V 5V ov Timing Diagram 12 2 Using 7474 integrated circuits design an active HIGH self correcting 4 bit ring counter Build the circuit and test its operation Use static logic level switches to control the direct set and reset inputs so that the counter can b
96. ecorded above and select a possible location for the fault Step 8 Check all signals and static logic levels at this location and record them If nothing appears abnormal return to step 7 Step 9 Analyze the test results recorded above and select a possible faulty device Step 10 Check the device for proper functioning If it is a discrete component take basic Ohm s Law measurements and or use a device tester to determine if the device is faulty If the device is an IC check the IC for proper functioning This includes checking inputs and outputs for stuck HIGH and stuck LOW conditions and other types of digital IC faults see below Common Digital IC Faults If the device passes all tests then return to step 9 Step 11 Repair or replace the faulty device and return to step 4 B 3 Common Causes of Faults in Digital Systems In this section several common causes of faults in digital systems are listed along with symptoms given for each cause and steps that may be taken to correct or minimize its effects on the system Defective components Components normally fail because of age because the maximum voltage or current rating of the device was exceeded due to improper design or because of the breakdown of another component improper connections or excessive ambient temperature In the case of digital ICs overheating caused by improper connections especially prototype circuits overvoltage or ambient temperature may result in t
97. er ground c Connect toggle switches to inputs Ao through As and Bo through Bs d Connect LED monitors to sum outputs So through Ss and also to Ca 68 Digital Logic Design 7 Verify that the adder is operating correctly by entering the input values listed in Table 7 3 and recording your observations on the outputs in the table Table 7 3 Test results for the 7483 IC Inputs Outputs A3 A2 Ai Ao B3 B2 B Bo C4 S3 S2 S So 0 0 1 1 0 0 0 1 0 1 1 1 0 0 1 1 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 Assignment 7 2 Construct the K maps for the difference and borrow out functions of a full subtractor Design build and test a corresponding circuit using XOR gates wherever appropriate Assignment 7 3 Design a circuit using the 7483 74283 to add two binary numbers whose values can range from 0 to 63 The adder must be able to add two 6 bit numbers in order to compute values up to 63 The adder must be able to add two 6 bit numbers in order to compute values up to 63 This requires two 7483 74283 adders cascaded together In the cascaded operation the unused input bits must be tied to ground for a logic LOW equivalent to adding a O This is necessary to obtain the correct results since unused TTL inputs float to a logic HIGH which is equivalent to adding a 1 Assignment 7 4 Design an adder subtractor that can compute values between the range of 63 and 63 an
98. er unused states than in a comparable length ring counter they still present a problem If the counter transitions into an unused state it will lock into some count sequence other than that for which it was designed This is shown in the lower half of the state diagram The simplest way to provide self correction for the Johnson counter is to fully decode one of the states in an unused state 107 Khalil Ismailov sequence and use the decoded output to clear or set the register thus returning the counter to its normal state sequence This technique also makes the circuit self starting Fig 12 3 3 bit Johnson counter One disadvantage of the Johnson counter compared to the ring counter is that the Johnson counter must include decoding circuitry if an output is required for each state However it is always possible to decode the normally used states in a Johnson counter with 2 input AND gates The all 1 s state and the all O s state are decoded by gating opposite ends of the flip flop chain while the remaining states are decoded by suitably gating the adjacent 1 and O for each of the bit patterns Johnson counters represent a middle ground between ring counters and binary counters A Johnson counter requires fewer flip flops than a ring counter but generally more than a binary counter it has more decoding circuitry than a ring counter but less than a binary counter Thus it sometimes represents a logical choice for certain applicati
99. evices are also available which are triggered on the trailing HIGH to LOW edge of the clock in this case an inverting bubble would be shown on the clock input line 73 Khalil Ismailov Fig 8 3 7474 flip flop The most versatile flip flop is the JK flip flop The 74LS76 is an integrated circuit containing two JK flip flops Fig 8 4 a shows the logic symbol for the flip flop and b shows the function table summarizing its operation Note that the synchronous J and K inputs are triggered on the trailing clock edge As with the 7474 there are asynchronous active low direct set and reset inputs that over ride the clock and J and K inputs The main advantage of JK logic compared to SR logic is that all four possible combinations of the levels on the JK lines produce useful operation It can be seen from the function table that in addition to hold store 1 and store 0 operation the input condition where J K 1 produces a toggle mode of operation i e the flip flop changes state after the active clock edge It is important to note that the 7476 IC in contrast to the newer 74LS76 is not actually an edge triggered device but rather a master slave flip flop LABORATORY ASSIGNMENTS Assignment 8 1 a NOR latch Wire the NOR gate latch shown in Fig 8 1 a Connect normally LOW pushbutton switches to the R and S inputs of the circuit You will monitor circuit outputs Q and Q with LED monitors b Turn the power supply on and
100. exer four in a package to a 16 to 1 multiplexer All of these commonly used integrated circuits have a number of features in common Each has an active LOW enable strobe input s the purpose of which is to allow for cascading devices The remaining pins are divided between data inputs select lines and outputs The binary code impressed on the select inputs determines which input line is connected to the output line The 74157 is a quad arrangement of four identical 2 to 1 stages which share a common select line Fig 6 1 Since input selection is from 1 to 2 lines for each stage only a single select line is required For this device the A inputs 48 Digital Logic Design are selected for each stage when S 0 input A B Note that the outputs are available in true form for all four stages 74157 Fig 6 1 74157 quad 2 1 IC multiplexer 74153 is a dual A line to 1 line multiplexer It has the schematic representation shown in Fig 6 2 Selection lines S1 and SO select the particular input to be multiplexed and applied to the output 74153 Fig 6 2 74153 dual 4 1 IC multiplexer Each of the strobe signals acts as an enable signal for the corresponding multiplexer 49 Khalil Ismailov Table 6 1 shows the multiplex function of 74153 in terms of select lines Note that each of the on chip multiplexers act independently from the other while sharing the same select lines S1 and SO Table 6 1 74153 truth tabl
101. g conventional test equipment Modern digital circuits and systems on the other hand consist mainly of digital ICs The IC s components are not accessible to the troubleshooter so the troubleshooter must rely on knowledge of the IC s operation s in order to isolate the IC as being faulty The experiments in this manual are designed to give you the necessary experience to test for and recognize proper operation of ICs A digital IC is considered defective or faulty if its outputs do not respond correctly according to its truth table for each set of input conditions and for each of its various operating modes A similar statement can be made for digital circuits and systems Once it has been verified that a circuit or system is not responding correctly a fault is said to exist and further troubleshooting is indicated The next troubleshooting step is to isolate the cause of the fault which may be in one or more smaller circuits or subsystems By progressively isolating smaller circuits and perhaps smaller subsystems the troubleshooter will eventually isolate the defective components which may be one or more ICs and or discrete components After replacing the defective components the circuit or system is tested for proper operation once more Once proper operation is established for all operating modes the troubleshooter s task is completed Now that the student is acquainted with the nature of digital troubleshooting a procedure for fault
102. he IC operating only sporadically After cooling down the IC will usually operate normally IC loading problems Exceeding the fan out of a TTL logic output may result in the output voltage dropping below Vokmin or rising above Voumax To verify this condition the output voltage should be checked for a level of 0 V 0 8 V for a LOW and 2 V 5 V for a HIGH If not the excessive fan out is causing a problem 123 Khalil Ismailov CMOS and MOS logic outputs will not be affected significantly by exceeding the fan out limits However any transitions at the output will show an increase in rise time and fall time This is because each CMOS or MOS input loads the output capacitively 5 pF each input Some common symptoms to look for are flip flops counters and flip flop registers that do not respond to the signal at the clock input Measure tr and tr of the clock signal and compare the measurements to the minimum required by the flip flop counter or register for proper triggering To correct the problem caused by excessive fan out a buffer should be used or the fan out reduced by load splitting Another solution is to insert a pulse shaping circuit such as a Schmitt trigger between the overloaded output and the clock input Improper signal characteristics A digital IC may function improperly if logic signals not meeting its requirements are applied to its inputs Minimum requirements are given for amplitude pulse duration an
103. he black clip to power supply ground If probe has a single LED to indicate logic levels the LED should be blinking to indicate that the level at the probe tip is floating If probe has two LEDs to represent the two logic levels both should be out If you have a DMM available connect its leads between the logic power ground and the probe tip The DMM should read a value between 1 3 and 1 5 volts This value is called by various names indeterminate bad invalid and floating All refer to the fact that if a voltage value falls into a range of greater than 0 8 volts and less than 2 0 volts the value cannot represent a logic O or a logic 1 These values all have a tolerance of 20 Most logic probes have three LEDs for logic indicators One lights for a logic 1 input and another for a logic low input The third lights when the input is pulsing LOGIC PULSERS A logic pulser generates digital pulses Like the logic probe the pulser uses the logic power supply to get its own power The tip of the pulser is placed on a circuit node where an injected pulse is desired The pulser senses the logic state of the node and generates a pulse that will attempt to drive the node to the opposite state For example if the logic pulser is placed into the circuit where there is a logic low signal level it will automatically generate a high level signal It is a valuable aid in troubleshooting since it permits the triggering of gates and other devices w
104. hich controls when the outputs change state in response to the data inputs There are generally two classifications of sequential circuits asynchronous and synchronous In asynchronous circuits outputs change as soon as the logic inputs change whereas in synchronous circuits outputs can only change in response to a timing or clock signal Asynchronous circuits are frequently subject to operational errors due to the effects of circuit delays and the unpredictable times at which circuit flip flops change state In contrast synchronous circuits can only change state when a clock pulse occurs their operation is more orderly and their design is more straight forward An example of a clocked D type flip flop is the 7474 integrated circuit which contains two flip flops The flip flop logic symbol is shown in Fig 8 3 This flip flop has most of the features found on current integrated circuit flip flops There are two sets of inputs The D and CP inputs are synchronous whereas the Spand Rpinputs are asynchronous If these inputs are inactive the flip flop state is determined by CP and D Q will become equal to the value 1 or 0 on the D input when the clock input CLK makes a LOW to HIGH transition This device is an example of an edge triggered flip flop since state changes are synchronized to the leading LOW to HIGH edge of the clock pulse The edge triggered nature of the flip flop is signified by the triangle on the CP input Edge triggered d
105. ide good noise immunity They are ideal for slowly changing or noisy signals e 7402 quad 2 input NOR Note the unusual gate layout Triple 3 input gates e 7410 triple 3 input NAND e 7411 triple 3 input AND e 7412 triple 3 input NAND with open collector outputs e 7427 triple 3 input NOR Notice how gate 1 is spread across the two sides of the package 150 7486 output gate 2 input gate 2 ga L5 174132 u gate input gate 2 g layoutt 2 to 6V HC 5V LS HCT 7412 input gate 3 input gate 2 5 7427 110 input gate 3 input gate 3 output gate 3 Digital Logic Design Dual 4 input gates 7420 dual 4 input NAND 7421 dual 4 input AND NC No Connection a pin that is not used 7430 8 input NAND gate NC No Connection a pin that is not used Hex NOT gates e 7404 hex NOT 7405 hex NOT with open collector outputs e 7414 hex NOT with Schmitt trigger inputs The 7414 has Schmitt trigger inputs to provide good noise immunity They are ideal for slowly changing or noisy signals 151 I VH input gate 1 1 o 14 Ev LSINCT input gate 1 2 113 input gate 2 input gate 2 input gate 1 4 er NC input gate 1 5 input gate 2 2 to 6V HC 45V LS HCT 2 to 6V HC 45V LS HCT output gate 4 Khalil Ismailov Counters x clockB 1 O clockA 7490 decade 0 9 ripple counter u 7493 4 bit 0 15 ripple counter reset0 AND NC These are ripple counter
106. ied together in pairs resulting in dual two bit D latches You will use only one of the D latches for this experiment so examine Fig 8 5 closely for the proper connections to be made h Install a 7475 IC on the circuit board and make the connections shown in Fig 8 5 Connect a toggle switch to D1 a normally LOW pushbutton switch to CLK and LED monitors to Q1 and Q When the circuit is completed perform the following steps 1 o wW Toggle switch 5 V LED monitors Fig 8 5 The7475 IC D latch Turn the power supply on and monitor the outputs of the latch Change the toggle switch back and forth a few times and note that there is no effect on Qi This is because the latch is in the latch mode and the data inputs are not enabled Set D 0 Press and hold the CLK input HIGH Observe that Q is LOW ve D back and forth a few times What happens to Qi Now set D 1 and release the CLK pushbutton What happens to Qv Change D back and forth several times Observe that Q does not change This proves that the data at D is latched on the negative going transition of the clock signal and that the output at Q follows the data at D while the clock signal is HIGH 76 Digital Logic Design Assignment 8 3 i Edge triggered D flip flop 7474 IC The 7474 IC has two individual positive edge triggered D flip flops with separate clock inputs and DC SET and DC RESET inputs Install a 7474 IC on the cir
107. ignment 11 1 Design a serial input shift right register circuit using 74LS76 flip flops The circuit must have an asynchronous master reset input which will clear the register when made LOW Use the pushbutton manual pulser to clock the circuit and static logic level switches to drive the serial data input and the master reset input Build the circuit and test it to verify correct operation by clocking in a 4 bit combination of serial data and verifying that the correct data have been stored in the register Test at least 8 different input combinations including the 0000 and 1111 combinations Remember to test the master reset operation 101 Khalil Ismailov Assignment 11 2 Design build and test a 4 bit shift right register with a synchronous parallel load capability using 7474 flip flops The parallel load must be synchronized to the leading edge of the clock The operating mode is to be determined by a control input MODE which when HIGH will provide parallel load operation but when LOW will provide serial operation Adequately test the circuit to provide reasonable assurance of correct operation in both the serial input and parallel load modes Hint Base the design on the circuit shown in Fig 11 2 b Synchronous operation can be obtained by also using the clock as input to the NAND gates driving the preset and clear flip flop inputs Assignment 11 3 74194A serial operation 1 Install a 74194A IC on the circuit board and ma
108. ion with logic gates would require five 3 input AND gates one 5 input OR gate and three inverters unless the expression can be simplified 74151 cc Input R variables G Q Fig 6 8 Three variable logic function generator Construct the circuit and write the pin numbers on the designed circuit Place the 74151 chip on a breadboard and assemble the connections to implement the circuit illustrated in Fig 6 8 3 Apply power to the circuit Vcc pin 16 GND pin 8 4 Test the circuit using appropriate data points N c Consider the following sum of products expression Y f A B C ABC ABC AB BC To implement this expression with a multiplexer it must first be expanded into each of its unique terms It is advantageous to express the final argument in summation form Y f A B C ABC ABC AB C C BC A A Y f A B C ABC ABC ABC ABC ABC The implementation of this function is shown in Fig 6 9 Note that the inputs to the multiplexer that are identified as TRUE logic 1 in the summation expression are tied to a logic 1 The remaining inputs are tied to a logic O 57 Khalil Ismailov N 2 4 74151 cc 7 6 5 4 3 2 1 0 Input variables B C D D D D D D D D s2 Sl so Fig 6 9 Three variable logic function generator Construct the circuit and write the pin numbers on the designed circuit Place the 74151 chip on a breadboard
109. itch are closed they actually bounce together a multiple and indeterminate number of times before coming to rest in a closed position This produces a voltage that switches between HIGH and LOW before setting to a LOW level so that rather than producing a single pulse multiple pulses would be produced In order to avoid this a single pole double throw SPDT switch must be used with some type of a latch circuit One commonly used circuit is shown in Fig 0 2 Digital Logic Design Ld 7400 Fig 0 2 Manual pulser circuit For the push button SPDT switch the center pole is connected to ground The cross coupled gates form a NAND latch which has the property that the output level is determined by the last input to become LOW this removes the switch bounce effects Note that both LOW going and HIGH going pulses are provided at the outputs with the HIGH going pulse derived from the gate with its input connected to the normally open NO pole of the switch The 7400 integrated circuit contains four NAND gates Using this single integrated circuit package with two swatches and four resistors would provide the student with the capability of having two independent pulse sources available for testing circuit designs Fig 0 3 shows a circuit for converting the output of a conventional square wave generator SWG so that it is compatible with TTL levels 5 V 2 2 kQ 74LS14 SWG IN TTL OUT Fig 0 3 Circuit for converting
110. ith four distinct operating modes determined by the logic levels on control inputs S and So When both inputs are HIGH parallel load operation occurs When So is HIGH with S LOW the register shifts right assuming serial data input from Dsr For the opposite condition with Si HIGH and So LOW the register shifts left with serial data input from Ds into the Qs 100 Digital Logic Design flip flop Finally when both control lines are LOW the register is placed in a hold or do nothing state it maintains the stored data regardless of the activities of the clock Both serial and parallel operations are synchronized to the leading edge of the clock The active LOW master reset is asynchronous and overrides all other inputs S Do Dj D D Da Do Di D2 D3 Dag So Si 74194 CP MR Qo Qi Q Q 7495 Q Q Q Fig 11 4 Versatile 4 bit registers The integrated circuit registers discussed above are just four examples of the variety of capabilities available in integrated circuit packages Although their use simplifies the design of register applications the designer must be aware that there are generally restrictions on the timing of input transitions on the control lines For example HIGH to LOW transitions on the control lines SO and S1 of the 74194 should only take place when the clock is at a HIGH level Violating the specified conditions will generally result in unpredictable operation and loss of data LABORATORY ASSIGNMENTS Ass
111. ithout removing them from their circuits POWER SUPPLIES Whenever possible a fixed 5 V power supply should be used This is not only more convenient but it avoids the possibility of circuit damage due to incorrect voltage level settings However there are some assignments that require other voltage levels 15 V 15 V for the circuit under test and the student may find it necessary to use a dual variable supply for these These should be used and Khalil Ismailov adjusted carefully because TTL digital circuits are easily damaged if the power supply voltage varies significantly from the specified 5 V level TTL circuits require an accurate well regulated voltage supply of 5 V 0 25 V DIGITAL LOGIC TRAINER Y 0039 Digital Logic Trainer Y 0039 Fig 05 provides all the basic functions necessary for learning digital logic fundamentals and prototyping digital logic circuits Fig 05 Digital Logic Trainer Y 0039 Function of Controls Connectors and Indicators Before turning this trainer on familiarize yourself with the controls connectors indicators and other features described below The following descriptions are keyed to the items called out in Fig 0 6 Digital Logic Design OOO O O G O O oc BUTTO amp 3 Fig 0 6 The front panel of Y 0039 1 Power ON OFF Switch 10 TTL Ground GND 2 0 418V 0 18 V 11 5 V TTL Power Source Adjustable DC Power Source 12 Breadboard PS0
112. its See Assignments BASIC INFORMATION The fundamental binary arithmetic operation is the addition of two bits Consider adding two bits A and B The addition process produces two results a sum bit S and a carry bit C From the rules for binary addition the carry bit is 1 if A B 1 while the sum bit is 1 if A B 1 0 or 0 1 i e if A and B are different This basic operation is described algebraically in equations 7 1 A circuit which performs this operation is called a half adder One possible implementation is shown in Fig 7 1 S AB AB AGB 7 1 C AB CD A B Fig 7 1 Half adder 63 Khalil Ismailov The operation of subtracting two bits is described similar to the above Consider finding the difference of two bits X Y Again there are two results of this operation the difference bit D and the borrow bit B The rules of binary subtraction lead to the algebraic description shown in equation 7 2 One possible circuit implementation is shown in Fig 7 2 D XY XY X Y B XY X Y 7 2 Fig 7 2 Half subtractor The general problem of designing a circuit to add two N bit numbers is solved by the same process used for manual addition Two corresponding bits from the numbers are added together with the carry generated from the addition of the two preceding less significant bits Of course no carry is used in the addition of the least significant bits a half adder could therefore perform thi
113. ke the following connections a Connect toggle switches to A through D SR SER So and to S b Connect a normally HIGH pushbutton switch to CLK and CLR c Connect LED monitors to Qa through Qo 2 Set S and So to HIGH SR SER to LOW and A through D to LOW Note that this has no effect on the outputs Pulse CLR LOW momentarily to clear the register if it is not already cleared Return So and S to LOW 3 Verify that neither the serial data input SR SER nor the parallel data inputs A through D have an effect on the register as long as both So and S are LOW when CLK is pulsed LOW Do this by setting SR SER 1 D A 1 and C B 0 and momentarily pulsing CLK LOW 4 Now set So to HIGH and pulse CLK You should observe that the LEDs indicate 1000 Set SR SER to LOW and pulse CLK three more times You should observe that the 1 is shifted one position to the right on each pulse The output now reads 5 Set S HIGH and pulse CLK LOW momentarily Observe that the register output changes to the value represented by the parallel data input switches 1001 This type of data transfer is called 74194A wired as a ring counter 6 Fig 11 5 shows the 74194A wired as a ring counter Examine the circuit then make the necessary changes to the 741944 so that it is the same as that shown in the figure Verify that the circuit operates as a four bit ring counter 102 Digital Logic Design A B C D 74194A CLR Q
114. lable on the 7447 to permit testing the display and expanding the circuitry to drive multidigit displays with leading and or trailing zero blanking When asserted the active low LT input will turn on all outputs and their corresponding LEDs The B R pin functions as both an input and an output If it used as an input and forced LOW all outputs are off regardless of the state of any other input This pin functions as an output in response to the ripple blanking input RBI If this pin is asserted active LOW and the BCD input is zero the B R output will be forced LOW and all segment outputs will be off This property makes it possible to blank either leading or trailing zeros in a multidigit display by connecting the B R output to the RBI input of adjacent digit drivers 43 Khalil Ismailov LABORATORY ASSIGNMENTS Assignment 5 1 Design build and test circuits for converting 4 bit Gray code to binary and 4 bit binary to Gray code using XOR gates and the algorithm described in the Basic Information This can be done with one 7486 IC Connect the circuit to four switches and four indicator lamps and check for proper operation using a truth table shown in Fig 5 1 a Assignment 5 2 The circuit shown in the Basic Information for converting Gray code to binary is a multilevel circuit with propagation delays that become increasingly more severe as the number of bits increases Design a 2 level circuit using only NAND gates and inverter
115. m the preceding gate were used as input This procedure could be used for succeeding stages also in longer counters so that only 2 input AND gates would be required The disadvantage of this practice is that the gate propagation delays accumulate and limit the maximum operating speed of the circuit Fig 10 1 4 bit binary synchronous counter Synchronous counter design follows a systematic procedure to specify the count sequence required and to determine the input logic functions to obtain the desired count sequence The flip flop excitation table describes the input conditions that produce the output state from each individual J K flip flop The excitation table for J K flip flops is shown in Table 10 1 With synchronous counters the next output state from each flip flop is determined by the present state and the present inputs applied to that stage The J K excitation table forms the basis of synchronous counter design An 92 Digital Logic Design excitation table for the counter is constructed by specifying the present state and next state for each flip flop in the order of the count sequence For each transition the necessary J and K inputs to produce the required sequence are listed A logic function for each J and K input is then derived from the excitation table Table 10 1 The excitation table for J K flip flops K ee P i iot Condition 0 0 0 X No change reset 0 1 1 X Toggle set 1 0 X 1 Toggle rese
116. mental results Data Switches Output LED Monitor Output Logic ON OFF Level 0 1 A 0 0 1 1 oi joju Verify that your results agree with the truth table for NOR gate 3 Disconnect input B from the toggle switch Set toggle switch A alternately to 0 and 1 and observe the effect on the output Based on your observation the disconnected NOR input acts like a input level 4 Connect the output GND and TTL of a FG04 Function Generator on the Y 0039 Digital Logic Trainer to input B and set the generator to 1 kHz x 1k position Disconnect the TTL Logic Indicator from the NOR output and connect one of the vertical inputs of the oscilloscope in its place Connect the other vertical input to the output of the FG04 Function Generator and trigger on this channel Set input A alternately to O and 1 and observe the effect on the output Sketch the waveform displayed on the oscilloscope for both settings of switch A using Timing Diagrams 1 1 and 1 2 15 Khalil Ismailov 5V 0 V Timing Diagram 1 1 5V 0 V Timing Diagram 1 2 NAND Gate 1 Connect the circuit in Fig 1 8 Do not forget the power supply connections Binary Switches Fig 1 8 Experimental NAND circuit 2 Connect the output to the TTL Logic Indicator Set the toggle switches to each input combination listed in the Table 1 5 and record your observations of the output monitor in the Table 1 5 T
117. n digital fundamentals and design It is not intended that all the experiments be completed or that every experiment be done in its intirety Instructors will probably want to make certain exercises optional to the student Each experiment begins with a set of stated objectives text references and required equipment followed by a procedure for meeting each objective Most experiments specify logic circuits needed to perform the experiment while a few require that the student design and draw the circuit s This manual contains several appendixes at the end The students is encouraged to become familiar with the contents of the appendixes early even though serious reading of much of the information on troubleshooting and digital faults can be deferred until it is needed Appendix A covers the types of circuit breadboards used in laboratory experiments for temporary circuit testing Appendix B covers several topics which should be helpful to the student Included in the material are general hints on proper breadboarding digital troubleshooting and information on typical digital system and IC faults The information about digital ICs and 74 series family cross reference of 155 series Russian ICs are found in Appendix C The pin layout for digital ICs used in experiments are found in Appendix D of this manual The information about seven segment displays of type HDSP is provided in Appendix E Khalil Ismailov EXPERIMENT GUIDELINES
118. n of a Logic Circuit Build a circuit to implement the Boolean function F A B 1 4 13 12 11 10 9 8 14 13 12 11 170 9 8 1 2 3 4 5 6 7 1 2 3 4 5 6 7 Quad 2 Input 7400 Hex 7404 Inverter 118 Digital Logic Design 7404 7400 The complete designed and connected circuit Sometimes the chip manufacturer may denote the first pin by a small indented circle above the first pin of the chip Place your chips in the same direction to save confusion at a later stage Remember that you must connect power to the chips to get them to work For chips with many legs ICs place them in the middle of the board so that half of the legs are on one side of the middle line and half are on the other side A completed circuit might look like the following A completed circuit assembled on the breadboard 119 Khalil Ismailov APPENDIX B WIRING AND TROUBLESHOOTING DIGITAL CIRCUITS Objectives 1 To discuss general wiring procedures for digital circuits 2 To introduce the student to formalized troubleshooting procedures 3 To list some of the common faults found in digital systems Discussion The experiments in this manual are designed to give you hands on experience with digital circuits More than that they provide you with an opportunity to develop sound breadboarding and troubleshooting skills that will be invaluable to you whether you eventually become an engineer or a technician This appendix will present some
119. n segment code using the 7447 decoder driver Fig 5 4 Use binary switches on the left side of the Y 0039 Digital Logic Trainer to connect the four BCD inputs A1 B1 C1 D1 and A2 B2 C2 D2 to logic 1 or logic 0 Record in Table 5 3 the number you would expect to see on the display if each code were placed on the 7447 inputs 7 SEGMENT DECODER DRIVER O O O O O O O A1 B1 C1 D1 A2 B2 C2 D2 LSB MSB LSB MSB Fig 5 4 Y 0039 2x7 Segment Decoder Driver Section Table 5 3 Decoder Driver Observations BCD Code Number Expected Number Observed A1 B1 C1 D1 A2 B2 C2 D2 First Second First Second 0000 0000 0010 0001 0011 0101 0100 0110 0111 1000 1001 1010 1011 1100 1101 1111 45 Khalil Ismailov b Test circuit for converting BCD to seven segment code using the 7447 decoder driver Fig 5 5 Use binary switches on the left side of the Y 0039 Digital Logic Trainer to connect the four BCD inputs A B C D to logic 1 or logic 0 Record in Table 5 3 the number you would expect to see on the display HDSP 5501 if each code were placed on the 7447 inputs When a BCD input is connected measure the seven segment outputs a to g with a DMM Record the measurements as high or low in Table 5 4 Also record the number displayed on the LED 5V 5 V Common b Anode From Binary Switches Fig 5 5 Experimental circuit Table 5 4 Decoder Driver
120. n the register design Some registers are designed to shift left as well as right these are known as bidirectional shift registers In any register circuit with multiple capabilities the action performed at any time is determined by control inputs Registers can be designed using any of the common flip flop types Fig 11 2 a shows a simple shift right register circuit using D flip flops with serial data input and both serial and parallel data output capabilities Fig 11 2 b shows the circuit modifications that could be made for each flip flop to incorporate an asynchronous parallel load capability Note that in this circuit the asynchronous parallel load control line would be active HIGH and override the clock DS IN DS OUT CLK Q2 b Asynchronous parallel load circuit Fig 11 2 Register circuit design with D flip flops 99 Khalil Ismailov A wide variety of registers are available as integrated circuits Fig 11 3 shows the logic symbols for two 8 bit integrated circuit registers that are especially useful for serial parallel and parallel serial conversions The 74164 features serial data input and parallel data output Serial data input and shift right operation is synchronized to the leading edge of the clock CP Serial data input is gated through the two inputs DSA and DSB These may be tied together or one may be used as an active HIGH enable for the other The active LOW master reset input MR clears the register
121. nal circuitry and the devices to which the system is connected For example many digital systems require that some output be displayed using decimal numbers so that it is readily understood In this case output quantities are most conveniently represented in BCD in order to drive commonly used display devices Another example is provided by digital systems typically in a control application that receive input from sensors which encode the position of a rotating shaft in such a way as to minimize errors In both of these cases it is necessary to design circuitry to convert between the codes used by the interface devices and the binary number system used internally in the system Consider the problem of encoding the position of a rotating shaft If shaft position were encoded using the normal binary number system then as the shaft position changed the binary numbers output from the encoder would 40 Digital Logic Design change Assuming a 4 bit representation the situation might be encountered in which the output changed from 0111 to 1000 Notice that all four bits would have to change for one increment in position Since it is impossible for all bits to change simultaneously there would be some periods of time when the encoder output would be in error for example 1111 or 1110 This could introduce other errors in the system using this data input To avoid the problem what is needed is a binary representation or code in which only one
122. nect the pushbutton switch in its place Disconnect MR and MR from ground and connect one of them to Qs and the other to Qi e Pulse CPo repeatedly and observe the count sequence displayed on the LEDs Record this sequence of output states in Table 9 3 88 Digital Logic Design Table 9 3 Observing the count sequence R Output states z Input pulse applied oF Q Qi Oo Decimal number None 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 4 5 6 7 8 9 10 11 12 13 14 15 f What is the mod number of the counter in step j Verify the mod number you gave by disconnecting the pushbutton switch at CPo and applying a 10 kHz square wave to this input Then measure the frequency of the signal at Q3 Is this output a square wave Now connect the 7493 IC as shown in Fig 9 6 Repeat steps g j using Table 9 4 to record your observations Based on the results recorded in Table 9 3 determine whether or not the signal at Q3 is a square wave Q2 Qi Qo Fig 9 6 The 7493 IC counter f 10 kHz 10 1 kHz 89 Khalil Ismailov Table 9 4 Yest results for the 7493 IC counter 2 Output states Input pulse applied oF Q Qi Qi Decimal number None 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 4 5 6 7 8 9 10 11 12 13 14 15 i Cascading 7493 IC c
123. nput combination in Table 1 6 and observe the output Table 1 6 Combinational circuit experimental results Data Switches Output LED Monitor Output Logic A B C ON OFF Level 0 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 18 EXPERIMENT SIMPLIFICATION OF BOOLEAN FUNCTIONS OBJECTIVE To use Boolean theorems to simplify logic circuits EQUIPMENT REQUIRED Digital Logic Trainer 1 each 7400 7402 7404 7408 7410 7411 7427 and 7432 integrated circuits BASIC INFORMATION One of the more common tasks of digital design is circuit simplification Although formal techniques exist for the methodical simplification of Boolean circuits and corresponding expressions the designer should be able to use the fundamental laws and basic relationships of Boolean algebra to analyze a given circuit and find a simplified expression for its output which will lead to a simpler circuit realization These skills are developed by knowing the necessary laws and relationships and gaining experience in their application The fundamental laws and basic relationships are summarized below FUNDAMENTAL LAWS 1 COMMUTATION a A B B A D A B B A 2 ASSOCIATION a A B C A B C b A BC AB C 3 DISTRIBUTION a A BC A BA C b A B C AB AC 19 Khalil Ismailov BASIC RELATIONSHIPS 4 OPERATIONS WITH 1 AND 0 a A 0 0
124. ns of the chips on your breadboard It is better to make the short connections before the longer ones Mark each connection on your schematic as you go so as not to try to make the same connection again at a later stage e Getone of your group members to check the connections before you turn the power on e f an error is made and is not spotted before you turn the power on Turn the power off immediately before you begin to rewire the circuit 117 Khalil Ismailov e At the end of the laboratory session collect you hook up wires chips and all equipment and return them to the demonstrator e Tidy the area that you were working in and leave it in the same condition as it was before you started Common Causes of Problems e Not connecting the ground and or power pins for all chips e Not turning on the power supply before checking the operation of the circuit e leaving out wires e Plugging wires into the wrong holes e Driving a single gate input with the outputs of two or more gates e Modifying the circuit with the power on In all experiments you will be expected to obtain all instruments leads components at the start of the experiment and return them to their proper place after you have finished the experiment Please inform the demonstrator or technician if you locate faulty equipment If you damage a chip inform a demonstrator don t put it back in the box of chips for somebody else to use Example Implementatio
125. o the next more significant 4 bit adder Of course regardless of how many bits are added in a given application the carry input to the circuit adding the least significant bits of the numbers must be zero A3 B3 A B Aj Bi Ao Bo Cm Fig 7 5 4 bit full adder The circuit shown in Fig 7 5 is frequently called a ripple carry adder because the sum does not become valid until the carry propagates or ripples through the chain of full adders This property is the major disadvantage of this circuit since it makes the circuit slow to respond to changes in the inputs For a long 65 Khalil Ismailov ripple carry adder this problem can be very severe From Fig 7 4 it can be seen that the carry output circuit is not a 2 level circuit Since the exclusive OR is a complex gate it has a longer propagation delay than other basic SSI gates so that the carry output function of the full adder circuit shown in the figure cannot respond to changes in the inputs until after a delay in excess of three gate propagation delays In a 16 bit ripple carry adder for example the sum would not be valid for a change in inputs until after a delay well in excess of 48 propagation delays Where fast adder circuits are required the ripple carry adder is clearly not adequate In practice carry look ahead circuits are used which produce the carry bits directly from the inputs rather than waiting for the carry to propagate through the chain This considerably in
126. o you if you review it from time to time There is too much information relating to troubleshooting to include all of it in a short appendix Your learning resource center or library may have some video tapes journals or books on the subject 129 Khalil Ismailov APPENDIX C 74 SERIES ICs and CROSS REFERENCE of 155 SERIES RUSSIAN ICs General characteristics There are several families of logic chips numbered from 74xx00 onwards with letters xx in the middle of the number to indicate the type of circuitry e g 74LS00 and 74HCOO The original family now obsolete had no letters e g 7400 The 74LS Low power Schottky family like the original uses TTL Transistor Transistor Logic circuitry which is fast but requires more power than later families The 74 series is often still called the TTL series even though the latest chips do not use TTL The 74HC family has high speed CMOS circuitry combining the speed of TTL with the very low power consumption of the 4000 series They are CMOS chips with the same pin arrangements as the older 74LS family Note that 74HC inputs cannot be reliably driven by 74LS outputs because the voltage ranges used for logic 0 are not quite compatible use 74HCT instead The 74HCT family is a special version of 74HC with 74LS TTL compatible inputs so 74HCT can be safely mixed with 74LS in the same system In fact 74HCT can be used as low power direct replacements for the older 74LS ICs in most circuit
127. on The DC SET and DC RESET inputs are asynchronous inputs that operate independently from the synchronous inputs J K and CLK The asynchronous inputs override the synchronous inputs when activated Verify this by holding the DC RESET input LOW and observe that the flip flop output stops toggling even though clock pulses are still being applied Q will remain LOW until the first clock pulse after the DC RESET pushbutton is released Disconnect the jumper connection from DC SET to V at the V end only and touch this wire to ground You should now observe that the flip flop output stops toggling and remains HIGH as long as DC SET is held LOW 79 Khalil Ismailov Assignment 8 5 p 7476 master slave J k flip flop operation The 7476 IC identical to the 74LS76 IC that was tested in Assignment 4 except that the flip flop circuits are pulse triggered instead of edge triggered This will permit you to observe the differences between edge triggered flip flops and master slave flip flops Install a 7476 IC on the circuit board and make the following connections to one of the J K flip flops 1 wW N A 5 Connect V and DC SET to 5 V GND to power ground Connect toggle switches to the J and K inputs Connect a normally LOW pushbutton CLK Connect a normally HIGH pushbutton switch to DC RESET Connect LED monitors to Q and Q or monitor the outputs with a logic probe 7476 synchronous operation To test the
128. on as a sum of products it may be necessary to remove parentheses and then placing a 1 in all squares corresponding to each product term The map thus contains the same information as the truth table of the function Consider the function shown in Equation 4 1 and its K map shown in Fig 4 3 X A BC BCD ABCD 4 1 CD CD CD CD Nw 00 01 11 10 AB 00 AB 01 AB 11 AB 10 a b Fig 4 2 Karnaugh maps for 4 variables CD CD CD CD AB 1 1 1 AB I AB 1 1 1 1 AB 1 1 1 1 Fig 4 3 K map of Equation 4 1 35 Khalil Ismailov The way in which the various terms map onto the squares should be noted The single term A maps onto the 8 squares in the lower half on the map which correspond to A 1 The 2 variable term maps onto 4 squares only two of which are new in this case the 3 variable term maps onto 2 squares and the 4 variable term maps onto a single square The procedure for finding the simplest expression for a given K map is the reverse of the mapping process described above Adjacent squares are combined so that they can be represented by a single term An expression is minimized if it has the fewest possible number of terms and each term has the fewest possible number of variables Thus in deriving minimized expressions from a given K map all function 1 s should be included by making the fewest number of combinations in which e
129. ons LABORATORY ASSIGNMENTS Assignment 12 1 1 Ring counter Construct the circuit of Fig 12 4 Connect all clear inputs to a single normally HIGH pushbutton switch Connect the other two pushbutton switches to the DC SET and the clock input of flip flop 3 Connect LED monitors to each flip flop output 108 Digital Logic Design To normally HIGH pushbutton switch CLOCK 2S gg A og DNE o To normally HIGH pushbutton switch Fig 12 4 Ring counter 2 Clear the counter by pulsing the clear line LOW momentarily Pulse the clock input LOW several times and note that the counter outputs do not change Now preset flip flop 3 to 1 by pulsing its DC SET input HIGH momentarily The LEDs should now indicate a count of 1000 Pulse the clock input LOW momentarily The counter output is now Pulse the clock input two more times Observe that the 1 now occupies the rightmost position of the counter display Now pulse the clock input once more Where is the 1 positioned now 3 Verify that it does not matter which flip flop is preset in order to get the counter started Do this by reconnecting the DC SET pushbutton switch to any of the other flip flops and repeating step 2 Disconnect the clock input from the pushbutton switch and replace it with the output of a square wave generator set at 1 kHz Display the generator output and Qs on the oscilloscope and observe the time relationship between the two signals Draw th
130. oolean function 3 Draw the logic diagram of the circuit using required logic gates with a minimum number of ICs 4 Obtain the necessary chips construct the circuit and test it for proper operation by verifying the conditions stated above LABORATORY ASSIGNMENTS Assignment 3 1 Design a circuit to activate an alarm in an industrial process control application The alarm which is activated by a HIGH level signal is to depend on three variables pressure P temperature T and level L which are monitored in the process Assume that setpoint values have been assigned for each variable so that the Boolean variables are either 1 or 0 as the physical quantities are above or below the setpoint values The alarm conditions are 1 LOW level with HIGH pressure 2 HIGH level with HIGH temperature 3 HIGH level with LOW temperature and HIGH pressure Design the corresponding alarm control circuit using NAND gates and inverters Assignment 3 2 The design of the control circuitry for the CPU central processing unit of a computer requires that a control signal be generated which depends on a clock signal CLK and two state signals T1 and T2 The control signal must go LOW only when CLK is HIGH and T1 is LOW or when CLK is LOW and T2 is HIGH Design the circuit to generate the control signal Use only NOR gates and inverters Assignment 3 3 Design a circuit to realize the function X in Table 3 3 Use only NAND gates and inverte
131. op outputs any time while the CLK input is HIGH SET J O and K 1 Clear the flip flop by momentarily pulsing DC RESET to LOW Press and hold the CLK pushbutton HIGH Change J to 1 and then back to 0 Noe release the pushbutton You should observe that Q changes to 1 even though J 0 and K 1 at the time of the negative going transition This demonstrates that should an unwanted glitch or noise spike occur on J or K while the CLK input is HIGH it may cause the flip flop outputs to be invalid when CLK goes LOW 81 EXPERIMENT RI PPLE COUNTER DESIGN OBJECTIVES 1 Design and understand the basic operation of binary ripple counters Design ripple counters of any modulus 2 Investigate the application of J K flip flops on counting circuits 3 Investigate the operation and a method of changing the mod number of the 7493 IC counter EQUIPMENT REQUIRED Digital Logic Trainer Dual trace oscilloscope Integrated circuits and components as required BASIC INFORMATION A counter is a circuit consisting of a number of flip flops and gates working together to count the number of clock pulses applied to its input Counters are available in two categories ripple asynchronous counters and synchronous counters In a ripple counter the flip flop output transition serves as a source for triggering other flip flops Clock input is applied to only the first of the series of flip flops Clock pulses for the other flip flops come from the p
132. ounters Connect the circuit shown in Fig 9 7 Apply a 6 kHz square wave to input CPo of the mod 10 counter With the oscilloscope determine the frequency of the signal at Qs of the mod 6 counter What is the mod number of this counter arrangement Mod 6 7493 CP MR MR Q Q ei Qo Not used fout fin 60 Mod 10 7493 MR MR Q S Q1 Qo fn 10 Fig 9 6 Cascading 7493 IC counters 90 EXPERIMENT SYNCHRONOUS COUNTER ANALYSIS OBJECTIVES 1 Completely analyze synchronous counter circuits and represent their operation using a state diagram 2 Investigate the operation of the 74193 IC counter EQUIPMENT REQUIRED Digital Logic Trainer 2 74LS76 and 1 74193 integrated circuits Other integrated circuits and components as required BASIC INFORMATION In synchronous sequential circuits all flip flops are clocked from the same signal source In theory state changes all occur at the same time and the glitch problems common to asynchronous circuits due to propagation delay effects are eliminated For this reason synchronous circuits are almost always preferable to asynchronous circuits The analysis of a synchronous circuit can be conducted in a simple and orderly manner as follows If there are N flip flops in the circuit there are a total of 2 states For each state following the logic of the circuitry the logic levels on the J and K inputs for each flip flop can be determine
133. output and borrow output to lengthen the modulus and to provide additional counter output stages Selection of a counter circuit for a particular application should be based on matching the requirements of the application to the capabilities of the counter Key parameters that should be checked include counter modulus maximum clock frequency clock pulse requirements cascade inputs and outputs count enable inputs and asynchronous preset and clear inputs 93 Khalil Ismailov LABORATORY ASSIGNMENTS Assignment 10 1 Theoretically analyze the circuit shown in Fig 10 2 using a state table technique to determine the circuit operation Build and test the circuit to confirm your analysis Connect each of the asynchronous inputs of the flip flops to a static logic level source so that the circuit can be set to any desired state Use a push button manual pulser to supply clock pulses Use LED indicating circuits on the Q outputs to indicate counter state What is the count sequence Theoretically and experimentally determine circuit behaviour for all possible states Fig 10 2 Counter circuit for Assignment 10 1 Assignment 10 2 Design build and test a glitch free synchronous mod 6 counter that counts from 000 to 101 and then recycles to 000 Insure in the design that all unused states transition to state 000 Test the circuit as described in Assignment 10 1 Assignment 10 3 a 74193 IC operation as a mod 16 UP counter
134. p 74823 10 bit D Flip Flop 74825 e 8 bit D Flip Flop 74827 10 bit buffer line driver 74828 10 bit buffer line driver 74832 e Hex 2 input OR Drivers K155JI I3 74841 10 bit transparent latch 74843 9 bit transparent latch 74845 8 bit transparent latch 74881 4 bit Arithmetic Logic Unit Function K155HII14 Generator 74882 32 bit Lookahead Carry Generator K155HII16 74899 9 bit latchable transceiver w parity gen chk 74900 9 bit 3port latchable datapath multiplexer 74902 14 6 Non Inverting TTL Buffer 74903 14 6 Inverting Buffer 74905 24 12 bit Successive Approximation Register 148 Digital Logic Design 74906 14 Open Drain N Channel Buffer 74907 14 Open Drain P Channel Buffer 74911 28 4 digit expandable Display Cont 74921 22 1024 bit Static SG CMOS RAM 74922 18 16 key Encoder 74923 20 20 key Encoder 74925 16 4 digit Counter Multiplexer 7 Seg Display 74928 18 4 digit Counter Multiplexer 7 Seg Display 149 Khalil Ismailov APPENDIX D 74 SERIES IC PIN ASSIGNMENTS Gates Quad 2 input gates e 7400 quad 2 input NAND e 7403 quad 2 input NAND with open collector outputs 7408 quad 2 input AND e 7409 quad 2 input AND with open collector outputs e 7432 quad 2 input OR e 7486 quad 2 input EX OR e 74132 quad 2 input NAND with Schmitt trigger inputs The 74132 has Schmitt trigger inputs to prov
135. p K155TM9 74175 16 4 DFlip Flop K155TM8 74176 14 Preset Decade Counter 35 MHz 74177 14 Preset Binary Counter 35 MHz 74180 14 9 bit Odd Even Parity Generator K155HII2 74181 24 4 bit Arithmetic Logic K155HII3 74182 16 Look ahead Carry Generator K155HIIA 74183 Dual Carry Save Full Adder K155HM5 74184 BCD to Binary Converter K155IIP6 74185 Binary to BCD Converter K155IIP7 74188 16 e 256 bit PROM 144 Digital Logic Design 74189 16 16x4 SRAM K155PY8 74190 16 BCD Decade Up Down Counter K155HE12 74191 16 Up Down Binary Converter 4 bit K155HE13 74192 16 Up Down Decade Counter BCD K155HE6 74193 16 Up Down Binary Counter 4 bit K155HE7 74194 16 4 bit Bidirectional Universal Shift Register K155HP11 74195 16 Universal 4 bit Shift Register K155HP12 74196 16 Preset Decade Counter K155HE14 74197 14 Preset Binary Counter K155HE15 74198 24 8 bit Bidirectional Universal Shift Reg K155HP13 74219 64 Bit RAM w Tristate Outputs 74221 16 2 Monostable Multivibrator K155ATA4 74238 16 3 to 8 line Decoder Demultiplexer K155HI19 74240 20 Tri State Octal Line Driver K155AII3 74241 20 Tri State Octal Line Driver K155AIIA 74242 e Quad Bus Transceiver K155HII6 74243 14 Tri State Quad Bus Transceiver K155HII7 74244 20 8 Tri State Octal Line Driver K155AII5 7424
136. perty of memory The basic logic circuit component that provides the property of memory is the flip flop The flip flop is a fundamental digital circuit component that has two stable states Its output can be either HIGH or LOW depending on the sequence of logic levels that has been previously applied to the inputs There are a variety of common flip flop devices used in digital circuits Figures 8 1 a and c show two basic flip flop circuits called latches which are designed from gates First consider the NOR latch in a Assume initially that a logic LOW is applied to both the S and R inputs If a logic HIGH is now 71 Khalil Ismailov applied to the S input the Q output is forced LOW This level is fed back to the lower gate and the Q output is forced HIGH Now assume that the S input is allowed to return to a LOW level Note that nothing changes in the outputs due to the feedback The Q output remains forced LOW and the Q output remains HIGH This is one of the two stable states of the circuit usually referred to as the SET state By similar reasoning if a high level is now applied to the R input the Q output is forced LOW and the Q output is forced HIGH If the R input is now returned to a LOW level again there is no change in the outputs This is the second stable state or RESET state of the circuit From the above it follows that if S and R are both LOW the state of the outputs is determined by which input was last as
137. ps by inserting the leads of circuit components into the contact receptacles and making connections with 22 26 gauge wire There are wire cutter strippers and a spool of wire in the lab It is a good practice to wire 5 V and 0 V power supply connections to separate bus strips The 5V supply MUST NOT BE EXCEEDED since this will damage the integrated circuits ICs used during the experiments Incorrect connection of power to the ICs could result in them exploding or becoming very hot with the possible serious injury occurring to the people working on the experiment Building the Circuit Throughout these experiments we will use TTL chips to build circuits The steps for wiring a circuit should be completed in the order described below e Turn the power off before you build anything e Make sure the power is off before you build anything e Connect the 5 V and ground GND leads of the power supply to the power and ground bus strips on your breadboard Before connecting up use a voltmeter to check that the voltage does not exceed 5 V e Plug the chips you will be using into the breadboard Point all the chips in the same direction with pin 1 at the upper left corner Pin 1 is often identified by a dot or a notch next to it on the chip package e Connect 5 V and GND pins of each chip to the power and ground bus strips on the breadboard e Select a connection on your schematic and place a piece of hook up wire between corresponding pi
138. puts of NOT gates to 5 V or to ground depending on the required input code Ro R7 Construct the circuit and write the pin numbers on the designed circuit Place the 74157 and 7404 chips on a breadboard and assemble the Apply power to the circuit Vcc pin 16 GND pin 8 for 74157 and Vcc Digital Logic Design Assignment 6 3 The digital multiplexer can be used to implement sum of products SOP expressions to provide a logic function generation and its ouiput can represent the Boolean expression for any combinational logic function a Design construct and test a circuit which uses an 74153 to implement a sum of products expression Y f A B C ABC ABC ABC ABC The multiplexer implementation table is shown in Table 6 4 Table 6 4 MUX implementation table Connect A and B Express F in terms of the other to select lines input C y M A B C F MUX 0 0 0 1 F C So connect C to Input O 0 0 1 0 MUX input 0 0 1 0 0 0 1 1 1 E 1 0 0 0 1 0 1 0 ed 1 1 0 1 1 1 1 1 Fe The circuit can be implemented as shown in Fig 6 7 Keep in mind in the example above that bits A and B were connected to the select lines If any other bits are connected to the select lines then the implementation table needs to be rearranged 1 Construct the circuit and write the pin numbers on the designed circuit 2 Place the 74153 chip on a breadboar
139. r NAND gate to the reset input For the 74162 and 74163 synchronous reset you must use the output s representing one less than the reset count you require e g to reset on 7 counting O to 6 use QB 2 and QC 4 Connecting synchronous counters in a chain The diagram below shows how to link synchronous counters such as 74160 3 notice how all the clock CK inputs are linked Carry out CO is used to feed the carry in CI of the next counter Carry in CI of the first 74160 3 counter should be high co ms gj synchronous eounter CK OD OC OB OA 2 to 6V HC 74192 up down decade 0 9 counter 5V LS HCT 74193 up down 4 bit 0 15 counter These are synchronous counters so their outputs change precisely together on each clock pulse This is helpful if down clock 4 74192 13 borrow output you need to connect their outputs to logic gates because it avoids the glitches which occur with ripple counters preset input C 4 input D 8 These counters have separate clock inputs for counting up and down The count increases as the up clock input preset is active low becomes high on the rising edge The 155 Khalil Ismailov count decreases as the down clock input becomes high on the rising edge In both cases the other clock input should be high For normal operation counting the preset input should be high and the reset input low When the reset input is high it resets the count to zero 0000
140. r would circulate the single 1 as shown in the top portion of the state diagram But if a glitch occurred that accidentally set another flip flop to 1 the new data pattern would circulate as shown in the middle portion of the figure If all flip flops were accidentally cleared or set the counter would remain in the corresponding state indefinitely Fortunately there is an easy solution to the unused state problem associated with ring counters This is obtained by driving the serial input not from the serial output but rather from either the NAND or the NOR of all flip flop outputs except for the last stage An example of each circuit is shown in Fig 12 2 Both circuits use a 7495 register operating in shift right mode to form a 4 bit ring counter First consider the circuit in Fig 12 2 a Recall that the output of a NOR gate is always LOW unless all inputs are LOW Thus the NOR gate in a operates as a zero stuffing input to the register continually feeding zeros into the serial data input until all flip flops except Qs have been cleared At this point the NOR gate output goes HIGH and a 1 will be fed into the register on the next active clock transition Thus the circuit in Fig 12 1 a 106 Digital Logic Design is an active HIGH ring counter with self correcting ability If the register accidentally transitions into an unused state it will eventually return to normal operation and will not stay locked in an unused state sequence
141. rd multiplexing time division multiplexing and logic function generation Using multiplexing circuitry allows a single line or small set of lines to be used to carry multiple signals Demultiplexing represents the reverse process A demultiplexer DMUX circuit has the capability of taking data on a single line or small set of lines and connecting that data selectively to one of a larger number of output lines The integrated circuit decoders previously studied can accomplish this task For this reason these integrated circuits are often called decoder demultiplexer circuits Consider the circuit shown in Fig 6 4 which uses the 74138 3 bit decoder Assume that eight separate logic signals have been multiplexed onto the single data input lines Notice that the data input has been connected to the active LOW enable E2 If a select code is applied to the normal decoder data input lines the corresponding output line will be LOW if the chip is enabled if the chip is not enabled recall that all output lines remain HIGH This circuit would function in a similar way if the data input line were connected to the active HIGH enable E3 except the data at the output line would be the inverse of the data at the input Other decoder chips can be used in a similar manner as demultiplexers For example the 74154 4 bit binary decoder can be used to demultiplex a single line onto 1 of 16 outputs 51 Khalil Ismailov 74138 Demultiplexed data
142. re not supposed to and triggering instead at the time other devices in the system are changing states To verify that poor regulation is the problem Vcc should be examined with an oscilloscope If spikes or pulses are riding on the Vcc level causing Vcc to drop by more than 0 2 V then the power supply has poor regulation There are two ways to correct this problem 1 improve the power supply regulation by either replacing or redesigning the current one or 2 use RF decoupling capacitors Grounding problems Poorly designed ground return circuits can cause the voltage at IC ground pins to be nonzero This is because currents flowing through the ground system can cause resistive and inductive voltage drops see Fig B 1 To avoid this problem all ground wires should have low resistance and inductance and each IC ground pin should be connected to the power supply separately PC board ground returns should be large conductive traces 5 V Fig B 1 Grounding problems Noise problems Circuit noise can be externally or internally generated Internally generated noise was discussed earlier Externally generated noise can cause sporadic triggering of logic circuits Common sources are electro mechanical devices e g motors and relays that produce electromagnetic radiation and electronic power control circuitry using SCRs and TRIACs This type of problem can be minimized by using special AC power line filtering devices to prevent noise
143. receding flip flop Thus the clock pulse ripples through the circuit in series fashion In a synchronous parallel counter the clock inputs of all of the flip flops receive the common clock pulse and the change of state is determined from the present state of the counter Although ripple counters are subject to timing constraints and glitch problems they are often easier to design and require less hardware than corresponding synchronous circuits to be considered in Experiment 10 As long as designers understand the problems and limitations of ripple counter circuits and use them appropriately ripple counter circuits offer simple and economical solutions to many practical design problems 82 Digital Logic Design A basic 3 bit ripple counter circuit is shown in Fig 9 1 CLK is the circuit input and the outputs are labeled ABC Note that the JK flip flops are set to toggle mode Flip flop C will toggle for every pulse arriving on the input However flip flop B can toggle only when C makes a HIGH to LOW transition and the same characteristic is true for flip flop A relative to B Fig 9 2 shows the waveforms that would be observed at the outputs assuming that the input is a symmetrical square wave To normally HIGH pushbutton switch Fig 9 1 3 bit ripple counter Fig 9 2 3 bit ripple counter waveforms A number of characteristics of this basic circuit are important to note The coun
144. rite the pin numbers on the designed circuit Place the 74157 chip on a breadboard and assemble the connections to implement the circuit illustrated in Fig 6 5 3 Apply power to the circuit Vcc pin 16 GND pin 8 4 Test the circuit using appropriate data points N Assignment 6 2 Design a multiplexer which will multiplex one of two bytes of data to the output of the multiplexer Use two 74157 integrated circuits Construct the circuit and test it using appropriate data points Hint The select inputs and enable inputs on the 74157s are tied common and controlled by the same select and enable inputs respectively The lower nibble of each byte is entered into one 74157 and the upper nibble of each byte is entered into the other 74157 Fig 6 6 53 Khalil Ismailov Address i S select Select 1 R select 74157 Lower nibble inputs So Lower nibble outputs Si S2 S3 Ro Ri Do R2 D R D D D4 Ds Upper nibble Ds inputs S D Ss Se S7 R4 E Upper nibble outputs R Fig 6 6 Byte multiplexing connections to implement the circuit illustrated in Fig 6 6 pin 14 GND pin 7 for 7404 5 Test the completed circuit using appropriate data points 54 One byte of data outputs To simulate signals for S inputs So S7 use outputs from the TTL Function Switches of the Digital Logic Trainer Y 0039 and for R inputs Ro R7 use output signals from 8 NOT gates of two 7404 IC connecting in
145. rmined for a function the Boolean equation can be written by forming a product term for each input combination for which the value of the function is one and then logically adding the terms together Note that each variable is present in the product terms in its uncomplemented form if the value of the variable is zero This produces a functional expression in the standard sum of products form SOP Often this is not the simplest possible expression Equation 3 2 below shows the expression derived from the motor control circuit truth table Note that this is a more complex expression than that derived from the verbal description P MLF MLF 3 2 When designing from truth tables it is sometimes found that the function has a large number of 1 s as shown in Table 3 2 for a function X of three input variables A B C If the procedure used above were applied in this case the SOP expression would contain many terms A better approach is to generate an expression for the complement of the function this expression can then be complemented to obtain the required function This is shown in equation 3 3 X ABC X ABC A B C 3 3 Table 3 2 Using function complement A B C X 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 29 Khalil Ismailov PROCEDURE For one of the assignment given by the instructor 1 Write the Boolean equation 2 Simplify the B
146. rs 30 Digital Logic Design Assignment 3 4 Repeat Assignment 3 3 for the function Y in Table 3 4 Use only NOR gates and inverters Table 3 3 Table 3 4 o 2 oi o io nn lolololol gt O o 23 o ou o 2 o 2 oi io n OoO l lol lt x O o j o o w Ol OD O O 0 gt lt x lolololol gt Assignment 3 5 Design a majority logic which is a digital circuit whose output is equal to 1 if the majority of the inputs are 1 s The output is O otherwise Design and test a 3 input majority circuit using NAND gates with a minimum number of IC s Assignment 3 6 An analog to digital converter is monitoring the DC voltage of a 12 V storage battery on an orbiting spaceship The converter s output is a four bit binary number ABCD corresponding to the battery voltage in steps of 0 75 V with A as the MSB The converters binary outputs are fed to a logic circuit Fig 3 1 that is to produce a HIGH output as long as the binary value is greater than 1000 810 that is the battery voltage is greater than 8 x 0 75 V 6 V Analog to Digital Logic Circuit Converter Fig 3 1 Circuit for Assignment 3 6 In the space provided below write and simplify the Boolean expression draw corresponding circuit and define output function assignments 3 5 and 3 6
147. rs College Publishing 1991 M Morris Mano Digital Design 2 e Prentice Hall Inc 1991 Ronald J Tocci Neal S Widmer Digital Systems Principles and Applications 7 e Prentice Hall Inc 1998 Jim C DeLoach Frank J Ambrosio Lab Manual A Troubleshooting Approach to accompany DIGITAL SYSTEMS Principles and Applications 6 e Ronald J Tocci Prentice Hall Inc 1995 David M Perkins Laboratory Manual A Design Approach DIGITAL ELECTRONICS A Practical Approach 4 e William Kleitz Prentice Hall Inc 1996 Wikipedia The Free Encyclopedia 7400 Series list http en wikipedia org wiki List of 7400 series integrated circuits 18 11 2005 FreeStyle Reference Fatal Error Technical Reference 74xxx TTL Series http www fsref com Fatal FE200201 SHTML 18 11 2005 J Hewes 2006 Kelsey Park Sports College The Electronics Club http www kpsec freeuk com components 74series htm 18 11 2005 Gupwa Hayuno npousso icrBengoe npezupusraue HTHC Site Map Cross References Russian TTL Chips to 74 th Series 17 01 2006 http www itis spb ru win tech logic htm Semiconductor Logic Device Cross Reference http matthieu benoit free fr cross competitive logic chipxref htm 21 01 06 Agilent Technologies 14 2 mm 0 56 inch Seven Segment Displays http www datasheetcatalog org datasheet HP HDSP 5507 pdf 21 01 06 113 APPENDIX A The Breadboard When building a permanent circuit the components can be
148. s The minor disadvantage of 74HCT is a lower immunity to noise but this is unlikely to be a problem in most situations For most new projects the 74HC family is the best choice The 74LS and 74HCT families require a 5V supply so they are not convenient for battery operation 74HC and 74HCT family characteristics e 74HC Supply 2 to 6 V small fluctuations are tolerated e 74HCT Supply 5 V 0 5 V a regulated supply is best e Inputs have very high impedance resistance this is good because it means they will not affect the part of the circuit where they are connected However it also means that unconnected inputs can easily pick up electrical noise and rapidly change between high and low states in an unpredictable way This is likely to make the chip behave erratically and it 130 Digital Logic Design will significantly increase the supply current To prevent problems all unused inputs MUST be connected to the supply either Vs or OV this applies even if that part of the chip is not being used in the circuit Note that 74HC inputs cannot be reliably driven by 74LS outputs because the voltage ranges used for logic 0 are not quite compatible For reliability use 74HCT if the system includes some 74LS chips Outputs can sink and source about 4 mA if you wish to maintain the correct output voltage to drive logic inputs but if there is no need to drive any inputs the maximum current is about 20 mA To switch larger currents
149. s addition Therefore the general design solution requires a basic circuit with three binary inputs two number bits and the carry input and two outputs the sum bit and the carry bit Such a circuit is called a full adder K maps for the full adder output functions can be constructed as shown in Fig 7 3 using the rules of binary addition In this figure C represents the carry input while A and B represent corresponding bits from the numbers to be added AB AB AB AB AB AB AB AB C 1 1 C 1 1 1 1 1 1 a S Sum bit b Co Carry out bit Fig 7 3 Full adder output functions The sum and carry out functions are best analyzed using exclusive OR relationships The minimized SOP expression is S ABC ABC ABC ABC A BC BO A BC BC A B C ABOC AG BOC 64 Digital Logic Design and C ABC ABC ABC ABC AB C C C AB AB AB C A 6 B The corresponding full adder circuit is shown in Fig 7 4 A B C Co Fig 7 4 Full adder circuit Using full adder circuits as building blocks circuits can be designed for the parallel addition of N bit binary numbers The most straightforward approach is shown in Fig 7 5 for a 4 bit adder Note that a full adder is shown to add the least significant bits AoBo This design would permit 4 bit adders to be cascaded to form larger adding circuits In this application the most significant sum bit S4 would form the carry out t
150. s in an environment which is potentially hazardous due to the possibility of explosive vapors collecting in the confined space in which the motor is located For this reason a fume sensor has been installed in this space which produces a HIGH level output if hazardous fumes are present The motor controls the pumping of fluid into a storage tank and it should operate automatically whenever the level in the tank reaches a minimum value There is a level detector in the tank which produces a LOW output when the level reaches the minimum value It must also be possible for an operator to start the motor manually by activating a switch which produces a HIGH output However the motor should not be started under any conditions when hazardous fumes are present All signal levels are TTL compatible How can the motor control circuit be designed If the situation above can be described by an exact and concise statement it will be possible to develop a corresponding Boolean equation When is it required to start the pump The 27 Khalil Ismailov pump must be started when the manual switch is activated AND there are NO fumes OR when the level detector is activated AND there are NO fumes Note that a corresponding Boolean equation could be written by assigning symbols to the signals involved and taking into account the assertion levels of the signals Assume the following P circuit output to motor relay HIGH for on M output from manual switch
151. s so beware NE output QA 1 that glitches may occur in any logic NC 4 output QD 8 gate systems connected to their 2 to 6V HC ov outputs due to the slight delay toy per 5 supply fa Te before the later counter outputs Ad vum respond to a clock pulse NC output QC 4 The count advances as the clock tb the falli NC No Connection a pin that is not used IDEE DRC OMe TOW ON LIE TAUG on the 7490 pins 6 and 7 connect to an edge this is indicated by the bar internal AND gate for resetting to 9 over the clock label This is the usual clock behaviour of ripple counters and it means a counter output can directly drive the clock input of the next counter in a chain The counter is in two sections clock A QA and clock B QB QC QD For normal use connect QA to clock B to link the two sections and connect the external clock signal to clock A For normal operation at least one reset0 input should be low making both high resets the counter to zero 0000 QA QD low Note that the 7490 has a pair of reset9 inputs on pins 6 and 7 these reset the counter to nine 1001 so at least one of them must be low for counting to occur Counting to less than the maximum 9 or 15 can be achieved by connecting the appropriate output s to the two resetO inputs If only one reset input is required the two inputs can be connected together For example to count 0 to 8 connect QA 1 and QD 8 to the reset inputs 74390 dual decade 0 9
152. s that will convert a 3 bit Gray code to a 3 bit binary output Table 5 1 Use any of the gates 7400 7402 7404 7408 7410 7420 7432 and 7486 but minimize the total number of ICs used Breadboard the circuit and test its operation for all input conditions Hint Construct K maps for the three binary output bit functions Table 5 1 Table 5 2 Decimal Gray Binary Decimal 8421 Code 2421 Code G3 G2 G Bs B2 Bi A BI C D a b c d 0 01010101010 0 0 0 10 0 0 01010 1 O JO 1 O 0 1 1 0 0 10 1 0 0 10 1 2 O 1 1 0 1 0 2 0 0 1 0 0 0 1 0 3 O0 1 0 0 1 1 3 0 0 1 1 0 0 1 1 4 1 1 0 1 0 0 4 0 1 0 0 0 1 0 0 5 1 1 1 1 0 1 5 0 1 0 1 1 0 1 1 6 1101 1 1 0 6 0 1 1 0 1 1 O 0 7 11010 1 1 1 7 0 1 1 1 1 1 0 1 8 1 0 0 0 1 1 1 0 9 1 0 0 1 1 1 1 1 Assignment 5 3 Design a combinational circuit with four input lines that represent a decimal digit in BCD 8421 and four output lines that generate self complementing code 2421 Table 5 2 Provide a fifth output that detects an error in the input BCD number This output should be equal to logic 1 when the four inputs 44 Digital Logic Design have one of the unused combinations of the BCD code Use any of the gates 7400 7402 7404 7408 7410 7420 7432 and 7486 but minimize the total number of ICs used Assignment 5 4 a Test circuit for converting BCD to seve
153. serted HIGH i e the circuit has memory This condition on the inputs is usually referred to as the hold or rest condition If both inputs are asserted HIGH both outputs are forced LOW this condition is not used in applications The NAND latch shown in c operates in a similar way except the inputs are active LOW The hold condition occurs when both inputs are HIGH a LOW on the S input sets the latch Q 1 a LOW on the R input resets the circuit Logic symbols for these latches are shown in b and d R Q 5 B S Q R Q a NOR latch c AND latch S Q 1S Q R Q IR Q b Symbol d Symbol Fig 8 1 Basic latch circuits A number of latch circuits are available as integrated circuits For example the 74279 is a quad NAND latch chip providing four NAND latch circuits The 7475 is a quad latch in which the latch circuits are transparent Fig 8 2 shows a logic symbol for one of the latch circuits contained in the integrated 72 Digital Logic Design circuit Data are applied to the D input As long as the E enable input is HIGH the Q output is the same as the D input in this sense the latch is transparent since its input value can be seen from the outputs When the E input is forced LOW however the data value present at the D input is latched the Q output will remain equal to the D input value at the time the E input was forced LOW Fig 8 2 7475 latch Most integrated circuits in common use have a clock input w
154. spection is necessary to locate this fault Shorted signal lines in TTL will appear different from shorts in CMOS circuits In TTL if one signal is trying to go HIGH and the other is going LOW the level at the short will be about a V This is because resistance at TTL outputs is lower in the LOW state than in the HIGH state For CMOS and MOS devices the level at the short will be about midway between a v and 5 V for this same situation because their output resistance is about the same in both states See Fig B 3 for an example of how waveforms would look for shorted signal lines in CMOS and MOS circuits Note the 2 5 V levels These levels would not normally appear on the waveforms Failure of discrete components While most digital components are ICs there is still circuitry that requires discrete components such as resistors capacitors transistors and diodes These components can be tested either completely out of the circuit or by unsoldering one or more of their leads and checking them with an appropriate test instrument such as an ohmmeter capacitance checker or transistor checker Faulty discrete components could mean another circuit caused the failure Be sure and check around for other faults because in the long run this avoids repeated failures in the device replaced 128 Digital Logic Design Common test equipment used in digital troubleshooting Besides the usual analog test equipment such as VOMs oscilloscopes and
155. st be controlled by a single set of logic signals A B C such that corresponding input and output lines are always selected For example setting A B C to 011 must select input line 3 and output line 3 Build the circuit and test it by applying a pulse source to each input line and confirming its transmission to the correct output line when the appropriate code is input to the select lines 1 Construct the circuit and write the pin numbers on the designed circuit 2 Place the 74151 and 74138 chips on a breadboard and assemble the connections to implement the circuit illustrated in Fig 6 11 3 Apply power to the circuit Vcc pin 16 GND pin 8 for both 74151 and 74138 4 Test the circuit using appropriate data points 59 Khalil Ismailov Serial Transmitted DP Received data 74151 transmission 74138 data 3 line Input data Select A inputs B C Fig 6 11 Multiplexer demultiplexer system Assignment 6 6 Design construct and test a circuit which uses an 74138 demultiplexer to implement a sum of products expression Y f A B C ABC BC 1 Convert the expression to summation form 2 The demultiplexer output is selected and will go low by the address on inputs A B and C when the IC is enabled Therefore we can create the output function Y by summing together the outputs indicated by the summation form of expression obtained in step 1 Since the outputs of the demultiplexer are active low
156. t 1 1 X 0 No change set Synchronous counters can produce a count sequence that is not in counting order Digital security locks might need a counter that generates a random sequence of numbers to serve as a password that must be matched by an appropriate input Other applications that can use a nonserial count feature are ones where the counter output is decoded to enable certain circuits within a digital system Integrated circuit counters are available for counter applications that require serial up or down count sequences The IC counters available are 4 bit binary or decade counters that can be cascaded together for applications requiring more than four output states The IC counters have asynchronous inputs that allow the flexibility of presetting the counter to an initial start value other than zero or resetting the counter back to zero at any instant of time The 74193 is a 4 bit synchronous positive edge triggered binary counter capable of counting up or down two separate clock inputs are used to control up or down counting The counter has a maximum mod 16 count sequence that can be shortened to any modulus less than 16 by using the asynchronous control inputs The clear input resets all count stages back to zero The preset input sets the counter stages to any 4 bit binary number loaded on the parallel inputs of the 74193 The counter can be easily cascaded while counting up or down through the carry
157. t been removed in the last step of the analysis In this case the output is represented as X B A C The corresponding circuit is shown in Fig 2 3 below 21 Khalil Ismailov The logical properties of all three circuits above are identical which could be demonstrated by comparing the truth tables of the outputs However their electronic properties may be different A C B Fig 2 3 Further simplified circuit PROCEDURE Assignment 2 1 Examine the logic circuit in Fig 2 4 and write the Boolean expression for output X Make a truth table for expression X using Table 2 1 Construct the circuit of Fig 2 4 on the circuit board Connect toggle switches TTL Binary Switches on Y 0039 Digital Logic Trainer to inputs A B and C Connect X to a TTL Logic Indicator on Y 0039 Digital Logic Trainer Verify the operation of your circuit by setting the toggle switches to each set of input values in Table 2 1 and comparing the outputs observed to the corresponding outputs in the table In the space provided below simplify X using Boolean theorems List the theorem used in each step of the simplification B X Fig 2 4 Circuit for Assignment 2 1 22 Digital Logic Design Table 2 1 Output logic level at X for an original and simplified circuits three inputs Inputs Output Logic Level at X A B C For an Original Circuit For a Simplified Circuit 0
158. t so that Q is HIGH Set J K 0 and note that nothing happens to Q Pulse the CLK input momentarily and observe that nothing happens to Q Why 5 Set J O and K 1 and note that nothing happens to Q Pulse he CLK input n What happens to Q Apply several more pulses to the CLK input and observe the Q remains in the LOW state 78 Digital Logic Design 6 Change J to 1 and then back to 0 and note that nothing happens to Q Pulse the CLK input momentarily You should observe that Q remains LOW This proves that the J and K input states present at the time of the proper clock transition are the ones transferred to the flip flop output 7 Set 1 K O Note that nothing happens to Q Apply a clock pulse and observe that Q will go HIGH Apply several more clock pulses What happens to Q m Disconnect the pushbutton switch at the CLK input and replace it with the n output of a square wave generator set to 1 MHz or the highest frequency obtainable Connect the oscilloscope to observe the clock signal and output Q Draw the waveforms displayed on the oscilloscope on Timing Diagram 8 1 Verify that the flip flop changes states on the negative going transitions and does not change states on the positive going transitions What is the frequency of the Q waveform compared to the clock waveform 12 34 5 6 7 8 9 10 11 12 13 14 Clock 0V 5V 9 ov Timing diagram 8 1 74LS76 asynchronous operati
159. tal Logic Design decoded with the NAND gate by using just the two most significant bits of the counter since this is the only state in which both bits would be high al C B A Fig 9 3 Mod 6 ripple counter LABORATORY ASSIGNMENTS Assignment 9 1 a gS Q YS Fig 9 1 shows the circuit for a three bit binary counter Examine the circuit closely then construct it Arrange the order of the flip flops exactly as the diagram shows it Connect a normally HIGH pushbutton switch to the clock input of flip flop C Connect LED monitors to the Q outputs of each flip flop The order of the LEDs is important since the output of the leftmost flip flop will represent the LSB of the count and the rightmost the MSB Connect all DC SET inputs to Ve and all DC RESET inputs to a single normally HIGH pushbutton switch Turn the power on and clear the counter by pulsing the DC RESETs LOW momentarily The number stored in the counter is indicated by the LEDs which should all be OFF i e the number should be 0002 Test the counter circuit by pulsing the clock input and observing the count indicated by the LED monitors Record your observations in Table 9 1 Your results should indicate that the counter counts to a maximum of 7 and recycles to 000 on the eighth clock pulse Disconnect the pushbutton switch from the clock input of the counter Connect the output of a square wave generator set at 10 kHz to th
160. ter counts up in binary from 000 to 111 and then recycles The number of states of the circuit referred to as the modulus or mod number of the counter is 8 corresponding to 2 The Q output of each flip flop is a square wave with 83 Khalil Ismailov a frequency output of one half that of the input signal The frequency output from the final stage is 1 2 These characteristics can be generalized For a binary ripple counter with N flip flops the modulus is 2 the terminal count is 2 1 and the final output frequency is the input frequency divided by 2 The number of output bits of a counter is equal to the flip flop stages of the counter A MOD 2 counter requires N stages of flip flops in order to produce a count sequence of the desired length The first stage of a counter is the least significant bit LSB The last stage of a counter is the most significant bit MSB There are many applications where a down counter is required i e a counter which counts downward in binary to a count of O before recycling to its initial count Note that in the above circuit down counter operation would be obtained if the counter outputs were taken from the Q outputs of the flip flops Alternatively the counter outputs could be taken from the Q outputs of the flip flops but each flip flop could be clocked from the Q output of the preceding flip flop This latter scheme is particularly useful in designing a dual mode up down counter in which
161. the like digital troubleshooting requires some specialized equipment A list of these specialized instruments would include the following 1 logic probe 2 logic pulser 3 current tracer 4 logic analyzer Of the four the logic probe is the most useful in general troubleshooting The pulser is useful when it is necessary to trigger gates flip flops counters or other types of circuits to check for proper operation The current tracer is a more specialized test probe used in locating shorts in digital circuits Whenever a short circuit is suspected the current tracer can assist the troubleshooter in pinpointing the exact location of the short The logic analyzer is a complex instrument used to compare many different logic signals at one time However it is expensive and is used mostly in complex systems to solve the more difficult problems that occur in digital Systems The experiments in this manual provide opportunities to gain experience with the logic probe logic pulser and the logic analyzer It is recommended that you become acquainted with the logic probe you will be using by reading the user manual that should accompany the probe If your laboratory has a logic analyzer it would also be to your advantage to learn as much as possible about the instrument before you attempt to use it If there is an operator s manual for the analyzer get it and read it Concluding Remarks The material in this appendix will be of more use t
162. v Open Collector Outputs Some 74 series ICs have open collector outputs this means they can sink current but they cannot source current They behave like an NPN transistor switch 12V load supply 5V logic supply load 74 series open collector output current OV for both supplies must be connected together ov The diagram shows how an open collector output can be connected to sink current from a supply which has a higher voltage than the logic IC supply The maximum load supply is 15 V for most open collector ICs Open collector outputs can be safely connected together to switch on a load when any one of them is low unlike normal outputs which must be combined using diodes There are many ICs in the 74 series and this page only covers a selection concentrating on the most useful gates counter decoders and display drivers For each IC there is a diagram showing the pin arrangement and brief notes explain the function of the pins where necessary For simplicity the family letters after the 74 are omitted in the diagrams below because the pin connections apply to all 74 series gates with the same number For example 7400 NAND gates are available as 74HCOO 74HCTOO and 74LS00 If you are using another reference please be aware that there is some variation in the terms used to describe pin functions for example reset is also called clear Some inputs are active low which means they perform their function when low
163. with J K flip flops Since the serial output is connected to the serial input once the counter has been initialized to a given state it will continue to circulate that initial data as it is clocked if there are no glitches or noise induced state transitions see below Thus modulus of the counter equals the number of flip flops Ring counters are frequently used in applications which require sequencing a number of events Although ting counter circuits are somewhat inefficient in the use of flip flops requiring one for each state such circuits are simple synchronous and need no additional decoding circuitry 105 Khalil Ismailov Fig 12 1 Basic 3 bit ring counter circuit There is one problem associated with ring counter operation that should not be overlooked by careful designs For a ring counter with N flip flops there will be N states in the normally used count sequence However N flip flops have a total of 2 possible states so that in an N bit ring counter there will be 2 N unused states For the basic circuit design shown in Fig 12 1 if the ring counter accidentally transitions into one of the unused states it will thereafter malfunction since it will no longer circulate the correct data pattern For example suppose the 3 bit ring counter of Fig 12 1 were designed for active HIGH operation The asynchronous set and reset inputs could be used to initialize the counter state to 100 Under normal operation the counte
164. y and the signal line through a current limiting resistor R This works well electrically but it has the disadvantage of giving a negative logic indication of the logic level i e the light is ON when the signal line is LOW The circuit in c is the preferred way of using an LED indicator In this circuit the LED is buffered from the signal line by a 7404 or 7405 inverter Thus the LED is ON when the logic level of the signal is HIGH Again a current limiting resistor R is required Its value should be chosen to give adequate intensity for the size of LED being used A value of 330 2 will give a forward bias current of about 10 mA This is the circuit that should be used for the Laboratory Assignments when the Equipment and Supplies list calls for LED indicating circuits Since the 7404 integrated circuit contains six inverters the student will find it most convenient to use a single 7404 or 7405 package with six resistors and six LEDs to build six indicator circuits which can be kept on the breadboard for general use 6 Digital Logic Design LOGIC PROBES A logic probe is a small hand held instrument used to indicate the logic level at a point in a digital circuit It is capable of indicating a logic 0 logic 1 and a level floating between logic O and 1 In many cases it is capable of detecting the presence of high speed pulses The red clip of the logic probe is to be connected to the power supply 5 V of the device under test and t
165. you can connect a transistor Fan out one output can drive many inputs 50 except 74LS inputs because these require a higher current and only 10 can be driven Gate propagation time about 10 ns for a signal to travel through a gate Frequency up to 25 MHz Power consumption of the chip itself is very low a few uW It is much greater at high frequencies a few mW at 1 MHz for example 74LS family TTL characteristics Supply 5 V 0 25 V it must be very smooth a regulated supply is best In addition to the normal supply smoothing a 0 1 uF capacitor should be connected across the supply near the chip to remove the spikes generated as it switches state one capacitor is needed for every 4 chips Inputs float high to logic 1 if unconnected but do not rely on this in a permanent soldered circuit because the inputs may pick up electrical noise IMA must be drawn out to hold inputs at logic 0 In a permanent circuit it is wise to connect any unused inputs to Vs to ensure good immunity to noise Outputs can sink up to 16mA enough to light an LED but they can source only about 2 mA To switch larger currents you can connect a transistor Fan out one output can drive up to 10 74LS inputs but many more 74HCT inputs Gate propagation time about 10 ns for a signal to travel through a gate Frequency up to about 35 MHz under the right conditions Power consumption of the chip itself is a few mW 131 Khalil Ismailo

LOGIC DESIGN

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