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MPC8260 PowerQUICC II ADS User`s Manual

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2. A B 0 F G J K GND 14 P17 P18 1 T 12 CND 1 11 1 1 xH x xH 3m 4 E DVAL 5 59 6 F CS 5 9 6 _ BCSRCS SDRMCS1 5 9 SDRMCS2 AQ 7 8 16 00 7 B 8 016 032 7 048 1 s 10 17 01 9 10 017 053 9 049 2 11 12 Al8 02 g 112 018 034 11 12 050 13 0 14 A19 D3 13 0 ey 14 019 035 13 9 051 A4 15 16 A20 04 15 16 020 036 15 052 A5 17 18 A21 D5 17 18 D21 D37 17 053 6 19 20 A22 06 19 122 022 038 196 054 2 7 21 41 22 A23 D7 21 1 22 023 039 21 1 055 2 A8 23 24 A24 08 23 24924 040 23 D56 A9 25 26 A25 09 25 26 025 041 25 D57 27 42 28 A26 019 27 42 28 026 042 27 42 058 A11 _ 29 30 27 011 _ 29 ga i 027 043 29 D59 12 51 32 A28 pag 31 32 D28 044 31 060 13 33 34 29 013 33 4 020 045 33 D61 14 _ 36 445 36 A30 014 _ 35 3 36 030 046 _ 35 3 062 A15 _ 37 38 A31 015 _ 37 138 031 047 37 06
3. A B 0 F G J 2 D36 L2APO 1 38 RN22 3 3 vise vas Pull Ups avec ACC 037 2 2 1 D38 j L2AP2 3 TRIS 9 9 2088 7 9 ae 5 039 4 gt L2AP3 4 s DBUFEN 05 CETHCEGU A ux 032 6 wa MODCKH1 7 SGLAMP1 7 icis TO F_PD6 7 033 7 oe 71 _ MODCKH2 6 F 053 6 RES F _ 04 6 034 L2AP 1 MODCKH3 4 F CS2 4 I F_PD3 4 x 035 12025 o lt z mr a ARETRY 10K 3 xi F_CS4 3 R59 1 F_PD2 3 gt CPUBC 2 ATMEN 2 TAN 10k F PD1 2 2 RN26 S ws ij F CS1 1 CND CND 2 D gt DVAL 19K LDO 1 047 _ LDPO 1 2 RN35 14 33 RN31 53 833 RN2 CO LD1 2 a 046 2 LDP 1 2 102 3l 045 3 2 _ 3 ol x RS_ENI R x 103 4 4 4 4 8 8 1K BREV1 8 104 043 ATRCKDIS RS_ENI 7 C R70 BREV2 7 gt
4. tmp mnt net prince yair voyager ads pilot sch 15 drw 26 SEP 99 19 06 lost update 21 SEP 99 18 45 A B C D E G H 1 1 2 2 DINA1612 128 RS RXD1 ATMTXEN io FETHTXER ulo PC31 RS_TXD1 A2 5 ATMTCA a2 FETHRXDV cio PC30 02 5 RS_CTS1 5 ATMTSOC 16 FETHTXEN a o 29 16 RS_RXD2 4 ATMRXENY Ba 5 FETHRXER 5 PC28 04 RS TXD2 S ATMRSOC 6 FETHCOL c o PC27 05 G RS CTS2 A6 5 ATMRCA G FETHCRS c PC26 o lt PD25 5 a 16 FETHTXD3 7 16 PC25 57 16 gt PD24 TS ATMTXD 1 ss 6 FETHTXD2 16 PC24 08 5 ABCD 3 2025 A9 16 ATMTXD2 6 FETHTXD1 16 PC23 6 1 5 PD22 aio 5 ATMTXD3 aio 5 FETHTXDO cio 5 PC22 518 PD21 A11 4 FETHRXDO els ATMF CLK ots PD20 A12 5 1216 FETHRXD1 1216 PC20 012 PD19 1 ATMTXD6 815 5 FETHRXD2 cis FETHRXCK DI3 5 PD18 AM ATMTXD7 814 5 FETHRXD3 cial FETHTXCK 014 G A15 ATMRXD7 B15 PB17 eio PC17 015 S
5. tmp_mnt net prince yoir voyoger ods pilot sch 14 driw 26 SEP 99 19 06 lost updote 21 SEP 99 18 45 1 V3 GND BRIDGE CND BRIDGE CND_BRIDCE CND_BRIDGE GND_BRIOGE GND_BRIOGE CND_BRIDGE CND BRIDGE CND_BRIDGE 1 vec 1 2 TH 2 s Rh dp Rh ub h RHH p b O Q QREQ R110 5 6 R107 220 7158 1 2 Rios TMS 2 9 55618 a SRESETY 2105 u s 6 i GND BRIDGE GND_BRIDGE GND BRIDGE HRESET mits 61 XBR3 i 5 566 4 H11 p 4 H12 p usb 2 m 2 5 u w V END A a cso lt 148 amp 156 N N N CND JTAG PORT 5 5 VOYAGER 9 0 58 29 5 GND 1 21 GND 5 eb x3 x x x 3 4 4 3 4 5 f 6 re 5419 T 5 ATMRXD6 7 8 PCO 8 __ 16 7 8 ATMRXD7 9 mJ 10 PB17 10 PC17 9 mJ 10 i PA2 ATMTXD7 i 12 FETHRXD3
6. 1 5 5 4 1 A2 82 SAQ 5 oO B3 VPP C0265 5 vec 052 V e o sis SA 0 2 sN xr 2 lt gt NS S O 0 co r 00 65 3 60 4 we EN 2 0 lt me 8840029 52 0 9 4 9 8 2 SDRMA 0 13 35585685 RANA 384405285 42 BHADDAH 22 ooccoocco BBADD27 50 J82 SAO FLASH80SIMM 472 A1 gai 166 SAT 70 807 167 542 9137 J91 A2 SA2 69 806 83 SDCFGCK AB 091 435 66 SCL 805 82 SDCFCDT 002 138 J83 A4 SDA 67 BD4 J73 A5 A 003 66 A8 004 992 nco 28 9 65 802 re 167 A7 25 64 801 EG A10 006 139 J84 2 63 800 43 007 36 174 A9 5 J93 A10 AP 28 62 8015 110 975 A11 NORTE pog 61 8014 37 nce 54 poto 88 8013 115 J85 NC
7. 741 125 1 CLKCENDB 2 3 8451 ATMRXPTY 1 CLK 5 isi ATMCLK LS t OUT U6 07 ATMRXD 0 7 TAVD1 19 44MHz_20ppm RAVD3 ae Wee RAVD2 74LCXBA1 Ic RAVD1 2 1 Y1 18 ATMRXD7 S 3 A2 v2 7 S Se e aly st ia 16 ATMRXD5 x n do 5853 58585 58 543535 59385385 REFCLK 2 Slag v4 5 4 ATMRXD4 2 2 p 25122122435 1 vae SR c a a gt RDAT7 78 7 ye 3 2 199 2 1992 245 77 ala7 97112 ATMRXD1 i ATMRXDN 23 Ryp RDATS 76 olas 11 ATMRXD Anata Lila RN81 0 vec ATMRSD 29 2 RDAT3 74 Lisle les isa lis RDAT2 23 5 u 0 o 27 I RDAT1 78 us Q1UF TAVS3 CND 28 RCAP2 RDATO 69 ess 1 ATMEN 4 pep ue EN ATMTXDP 12 81 07 1 ile mum 1120 RXPRTY 4 NC 10UF 58 1 1 pp mo 5 6 cM CH 4 5 05 e C LS 19 67 74LCX128 8 s 5 8 A TRREF RRDEN 74 ck126 M 9 x x 18 TVREF ATMRXEN TAVS4 66 8 7 ATP 1
8. tmp_mnt net prince yoir voyoger ods pilot sch 16 drw 26 SEP 99 19 07 lost updote 21 SEP 99 18 45 8 D E G H DIN41612 128 EXPA16 A1 B1 01 O O O ER O O O EXPA19 A4 TSTATO B4 BTOLCS1 C4 04 20 5 5 lt 1 as 6 groLcs2 c8 5 EXPWE 17 o 6 TSTAT 406 606 21 15 lt 2 a6 6 7 5 n B gt 22 7 TSTAT3 B7 C7 EXPGPLO 07 5 23 TSTAT4 B8 ATMRST EXPGPL1 08 24 TSTATS 5 FetursT co 5 EXPGPL2 09 lt ARCH 25 75 TSTAT6 HRESET EXPCPL3 01415 1 EXPA26 11 TSTAT7 B11 IRQ6 C11 EXPGPL4 D11 27 12 5 TOOLRE VO 8121 IR07 2 5 EXPGPLS 01215 Al TOOLREV1 1 C13 013 are BE 1410 EXPALE 1410 O O A18 TOOLREV3 815 5 EXPD1 5 EXPCTLO 01515 1 A16 EXTOLIO 81615 EXPD2 5 g VPPIN A17 EXTOL 817 C17 D17 EXTOL 04 EXTOLIS EXPDS ot 20 820 C20 020 0 A21 821175 EXPD7 e21 5 021
9. ENABLE PON DEFAULT ENABLED RESET PON DEFAULT ATM RESET FETH ENABLE PON DEFAULT FETH ENABLED FETH RESET PON DEFAULT FETH RESET ACTIVE RS232 1 ENABLE PON DEFAULT RS232 1 ENABLE RS232 2 ENABLE PON DEFAULT RS232 2 ENABLE bk kk Data Bits Assignments k K K ENABLE DATA BIT D2 ATM RESET DATA BIT D3 FETH ENABLE DATA BIT D4 MOTOROLA Chapter 5 Support Information For More Information On This Product Go to www freescale com 5 117 Freescale Semiconductor Inc FETH RESET DATA BIT 05 5232 1 ENABLE BIT D6 5232 2 ENABLE DATA D7 Jtag Command Status reg definitions JTAG ENABLED 1 STATE_JTAG_ENABLED JtagEn fb JTAG_ENABLED Power On Defaults Assignments JTAG ENABLE PON DEFAULT JTAG
10. 1 NEAR VOYAGER 1 MODCK2 221 SDRMA13 SDRMA 0 13 MODCK3 62 7 22 2SDRMA12 17 57 4 BSDRMA11 BSDRMA11 5 22 RN62 SDRMA11 SXNVUTENTS ANTARI 25 RN62 SDRMA10 lt gt 471 oo 2 A16 4710 2 16 46 5 9418 A17 46 5 01 3 19 1 BSDRMAQ BSDRMAQ 22 1 SDRMAQ 2 44 a2 5 A18 44102 02 5 RN15 Bus Hold 43 5 6 19 43 5 0316 2 420 78 2 BSDRMA8 BSDRMA8 1222 SDRMAB UB 05 a5 c sg a 06 5 lt D6 Q6 D6 Q6 RNG PNIS A7 37157 07 12 A23 3767 07 1 2 A21 6 f 3 BSDRMA7 8S0RMA7 6 5 SDRMA7 LE 1 LE1 2 A22 5 f 4 BSDRMAG 8508 6 16 5 4 DET DET 24 23 87 1 BSDRMA5 gt BSDRMAS5 8 1 RNT6 SDRMA5 a24 RNIB BSDRMA4 RN S SORMA4 A8 36008 13 848 A24 36008 RNT8 m RN S 9 35 09 09 10 55010 010 S 011 Q11 25 67 BSDRMA3 5 22 SDRMA3 ATE 26 012 012 gt A26 RNIB 5 0 4 _ BSDRMA2 8508 2 RNTS s 22 4 SDRMA2 97 013 013 5 A27 8 1 18 BSDRMA1 2 Q SSORMA1 a 22 RNTO SDRMA 121551014 014 5 28 RN23 rs BSDRMAQ BSDRMAQ RN24 6 22 3 SORMAD 52015 015 9 RN23 RN24 LE2 is BSORMA 0 9 BSDRMA 11 24 i UNDER MULTIPLEXERS AFTER MULTIPLEXER o Y 74ALVT16245 74ALVT1
11. System i f pins SYSCLK PIN 11 BrdContRegCs_B PIN 36 DVal B PIN 43 RBW PIN 86 BCTLI PIN 64 7 PIN 98 for flash support 8 PIN 4 for flash support A27 PIN 5 A28 PIN 7 A29 PIN 8 DO PIN 84 istype DI PIN 78 istype D2 PIN 80 istype D3 PIN 59 D4 PIN 70 istype 05 PIN 57 D6 PIN 60 istype D7 PIN 72 istype Board Control Pins Read Write DimmSize L2Inh B L2Flush B L2Lock B L2Clear B SignaLampO B SignaLampl B AtmEn B 5 108 PIN 44 istype reg buffer Page Base Interleaving PIN 53 istype reg buffer Sdram Dimm Size PIN 15 istype reg buffer flash enable PIN 54 istype reg buffer 60x bus sdram enable PIN 35 istype reg buffer bursting sram enable PIN 34 istype reg buffer local bus sdram enable PIN 32 istype reg buffer status lamp 0 for misc s w visual PIN 33 istype reg buffer status lamp 1 for misc s w visual signaling PIN 94 istype reg buffer
12. ROROR Signal groups Add A10 A19 A21 A28 5 140 8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc LAdd LA10 LA19 LA21 LA28 RowAddNormal LA12 LA19 RowAddPBI 16M LA11 LA18 RowAddPBI 64M LA10 LA17 ColAdd LA21 LA28 SdramAdd SdramA7 SdramA0 C 1 COL ROW SIZE_16M 0 SIZE_64M 1 SDRAM 16M DimmSize SIZE_16M SDRAM 64M SDRAM_16M SDRAM NORMAL PBI 0 SDRAM PBI SDRAM NORMAL MuxCont PBLDimmSize Equations state diagrams Input Latch equations AleOut_B AleIn inverted Ale LAdd le LAdd d Add latching the address Output equations SdramAdd oe hff always enabled MOTOROLA Chapter 5 Support Information
13. Auxiliary Pins Internal Signals LIE System Hard Reset Configuration DataOeNODE istype com data bus output enable on read Control Register Write space saving Mach 7 required for 66Mhz BesrOWrite B NODE istype BesrI Write B NODE istype Reset amp Interrupt Logic Pins RstDeb1 NODE istype keep com reset push button debouncer AbrDeb1 NODE istype keep com abort push button debouncer HardResetEnNODE istype com enables T S hard reset pin SoftResetEnNODE istype enables T S soft reset pin data buffers enable oe oe SyncHardReset_B NODE istype reg buffer synchronized hard rese
14. MPC8260ADS Side Part Location Diagram VDDL Range Selection 1 Trimmer gt eum aan TR J5 TDI Source Selection dei suu Host Controlled Operation Scheme Stand Alone Configuration P19 45V Power Connector P2 12V Power Connector 2 1 2 1 0 00000010000000000002020 P5 COP JTAG Port Connector PB3 RS 232 Serial Port Connectors Hash Memory SIMM Insertion SDRAM DIMM DS3 wS a aO aska J3 Therm Connecctor Ventilator SUPPLY VPP Source S lection Glock Generator kuu SDRAM DIMM Connection Scheme SDRAM DIMM 60X Bus Connection Scheme Local SDRAM Connection Scheme RS
15. For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 2 Hardware Preparation and Installation 2 1 Introduction This chapter provides unpacking instructions hardware preparation and installation instructions for the MPC8260ADS 2 2 Unpacking Instructions NOTE If the shipping carton is damaged upon receipt request carrier s agent to be present during unpacking and inspection of equipment Unpack equipment from shipping carton Refer to packing list and verify that all items are present Save packing material for storing and reshipping of equipment CAUTION AVOID TOUCHING AREAS OF INTEGRATED CIRCUITRY STATIC DISCHARGE CAN DAMAGE CIRCUITS 2 3 Hardware Preparation To select the desired configuration and ensure proper operation of the MPC8260ADS board changes of the Dip Switch settings may be required before installation The location of the switches indicators Dip Switches and connectors is illustrated in Figure 2 1 MPC8260ADS Top Side Part Location Diagram on page 18 The board has been factory tested and is shipped with Dip Switch settings as described in the following paragraphs Parameters can be changed for the following conditions MPC8260 s Internal Logic Supply Level Range Via J1 MPC8260 s Internal Logic Supply Level within range VDDL Via MPC8260 s MODCK 1 3 Determining Core s and CPM s PLLs mul
16. PROJECT MPC8260ADS REV PILOT SHEET 9 OF 18 ENG YAIR LIEBMAN BLOCK 100 10 BASE T CHK DESCRIP 8 6 9 K Amp mnt users yair voyager ads pilot sch 10 drw 22 OCT 99 16 01 lost updote 22 OCT 99 16 01 A B C D E F G H J K 1 FUSE OR MIC297528WT Optional network 1 VCC 295008 To used with MIC28752 regulator GACTORY SOLDERED 4 MIC_REGU_5 3 1 2 VDDH 0 1UF 500V F2 IMBRD620CT 3 OUT m 1 1 N apse 9 B J6 ue 01 N 066 GND 102 208 2 eri 02 5 n 4 T B ll 6142 T3 0UF gt 4 2 2K_1206 500 o R69 ANS R64 p ASSER UNDER x s 80828ANMP 209 cw
17. 68 BCSR7 Board Control Status Register 7 68 COP JTAG POTT oss aaa 68 Fast Download Suppose as ettet edit wt eben i endi n M 69 JTAG TPC Omer aa e ed 71 JTAG Instruction Shift Register JISR 72 JTAG Instruction Register JIR 72 Data Shift Register nenesot eS E 72 Download Control and Status Register 73 Bypass Bellstet eo seu esse enue ace 73 JTAG Machine Bypass 73 Fast Download OperattQ eos steps hu eben 73 JTAG Generated Power On 74 POWER T 74 sm 76 76 t a Ru LEA PL e dd 76 77 Chapter 5 Support Information Interconnect Sd Hals NUI aaa Re 78 P1 Ethernet Port Connector 78 P2 12 Power Connector py tx 78 PB3 5232 Port
18. n 14 SDRAM DIMM S ES aa de 14 SININD 15 PONE co S 15 Communication POLIS 15 Miscellaneous Chang esa aai 15 Chapter 2 Hardware Preparation Installation APNE OAT pd ee 17 Unpacking Instructions us dva rtr e esata 17 Hardware E 17 Setting VDDL Level Range 19 Setting VDDL Supply Voltage Level 19 Setting MODCK 1 3 for PLLs Multiplication Factor DS1 6 8 20 Setting Hard Reset Configuration 21 Setting MODCKH 0 3 PLLs Multiplication Factors 22 MPC8260 JTAG s TDI Source Selection 5 22 SDRAM DIMM Slave Address Selection DS2 25 Installation y S a eee eaten 23 Host Controlled OperatiODi cete 24 Stand Alone s ados 24 5V Power Supply Connection 25 P2 12V Power Supply Connection 25
19. a ec M ee 25 65585 SDC2UV6482_84T_S a TALCX 125 AT AT cN LOI LO LO cO o y oajo oajoj ojojojo 7 13 023 C SDRAM DIMM PER 8 PROJECT MPC8260ADS REV PILOT SHEET 5 OF 18 8 YAIR LIEBMAN BLOCK SDRAM DIMM amp FLASH SIMM CHK DESCRIP 3 J K tmp mnt net prince yair voyager ads pilot sc h 6 drw 26 SEP 99 19 04 last update 21 SEP 99 18 43 LA18 LA 20 29 M8 111716224 811171622 0 A1 A1 i 5 4 0015 29 we A4 0015 22 Te A5 9014 48 L A5 0014481 6 ag 0013146 102 A6 0013146 1018 0012145 103 A7 0012 45 L019 2 A8 0011145 504 AB 0011149 1020 A8 0010142 105 A9 00102 1921 o 4 m 20 A10 009 20 06 FUN 20 10 009 30 222 LA 9 00839 LA Iari Dos S92 L lt LSDDQM0 56 50712 108 36 12 1024 LSDDQM1 nom 006 1 109 1 1028 nos 9 L010 nos 9 LD26 15 0041810011 po4 8 27 6 pos 6 012 0058 1026
20. PS iiu sete ESI WE PET 25 Terminal to MPC8260ADS RS 232 Connection 26 10 100 Base T Ethernet Port Connection 26 Memory Install at lE turtur ur dedi ei uelit uult testa 26 Flash Memory SIMM Installation 27 SDRAM DIMM 27 Chapter 3 Operating Instructions mp 29 Contents ii For More Information On This Product Go to www freescale com Freescale Semiconductor Inc CONTENTS Paragraph Number Number 3 2 Controlsand Indicators esee eta vies us A 29 3 2 1 Power On Switch 29 3 2 2 ABORT Switcli SW l neben a nt a Qa IE 29 3 2 3 S 8 3 aaa EUREN e eu 29 3 2 4 HARD RESET Switches SW2 amp SW3 29 3 2 5 DST Reset COnfig0rattorS WI ete de pde s sS 29 3 2 6 DS2 SDRAM DIMM Configuration Memory 12 Slave Address Switch 29 3 2 7 DS3 Software Options Switch 30 3 2 8 VDDL Voltage Level Range Selection 30 3 2 9 J2 IDDL M 8s rement a L nan 30 3 2 10 J3 Thermal Sense Connector a aise ua ebe
21. 000 Not Supported 001 150 010 100 120 011 80 90 100 70 101 111 Not Supported Table 4 13 Flash Presence Detect 4 1 Encoding FLASH_PD 4 1 Flash TYPE SIZE 0000 Technology SM73288XG4JHBGO 32 MByte 4 banks of 4 X 2M X 8 by Smart Modular 0001 Technology SM73248XG2JHBGO 16 MByte 2 banks of 4 X 2M X 8 by Smart Modular 0010 n Technology M73228XGIJHBGO 8 MByte 1 bank of 4 X 2M X 8 by Smart Modular 0011 1111 gt ot Supported Table 4 14 EXTOOLI 0 3 Assignment EXTTOOLI 0 3 hex External Tool T ECOM MPC8260 Communication tool Reserved Reserved Circuit Emulation Tool Tool Non Existent MPC8260 PowerQUICC II ADS User s Manual For More Information On This Product Go to www freescale com MOTOROLA 4 12 4 BCSR3 to BCSRS Board Control Status Register 3 5 Freescale Semiconductor Inc Table 4 15 External Tool Revision Encoding TOOLREV 0 3 hex External Tool Revision 0 ENGINEERING 1 PILOT 2 Al 3 F Reserved Future revision Table 4 16 ADS Revision Encoding 0 3 ADS Revision 0 ENG Engineering 1 PILOT 2 3 F Reserved lFuture revision Table 4 17 L2 Cache Size Encoding L2CSIZE 0 1 L2 Cache Size 700 Reserved 01 512 KBytes 10
22. 1 011 1 027 H J114 BSDRMAQ 131 012 028 37 DIMMSIZE 4 aaa 131 012 1102837 14 1 013 1 029 38 21 197 013 1 029 22 014 1 030 0 4 1030 39 BSDRMA3 16 015 1 031 40 423 ide 161 17031148 9 _ CY SU CI E tu vjfe bic lt gt u19 MOTOROLA R26 8 Marek PROJECT 260 05 REV PILOT SHEET 17 OF 18 8 ISPTDO3 4 2 ISPTDO1 ENC YAIR LIEBMAN BLOCK CACHE BLOCK amp ADDRESS LATCH MUX ISPTMS R25 NOT ASSEMBLED CHK DESCRIP A B 3 7 J K Q318A355V LON i AHO i LO3rOud Freescale Semiconductor Inc M UE 50 0909824 1 A38 40018 4190530 1019 ONT 49018 133H5 81 20 8 A r 2 E 9 9 9 gt D 5 gt D D Lc gt Alu 2 mI 2 2 2 2 x Fie c 8 wha SIRIS 8 G Ble SI
23. and ATMTSOC When the ATM port is disabled this line may be used for any available function of PC21 D12 PC20 T S MPC8260 s Parallel I O Port C 20 Parallel I O line May be used for any of its available functions D13 FETHRXCK PC19 T S Fast Ethernet Receive Clock When the Ethernet port is enabled this clock 25 MHz for 100 Mbps 2 5 MHz for 10 Mbps is extracted from the received data and driven to the MPC8260 to qualify incoming receive data When the Ethernet port is disabled this line is tristated and may be used for any available function of PC19 014 PC18 T S Fast Ethernet Transmit Clock When the Ethernet port is enabled this clock 25 MHz for 100 Mbps 2 5 MHz for 10 Mbps is normally extracted from the received data and driven to the MPC8260 to qualify out coming transmit data In Slave mode not used with this application this clock should be input to the LXT970 When the Ethernet port is disabled this line is tristated and may be used for any available function of PC18 D15 PC17 T S 8260 Port 17 15 Parallel I O lines May be used to any of their available functions D16 PC16 D17 PC15 D18 RS_CD1 PC14 T O T S RS232 Port 1 Carrier Detect L Connected via RS232 transceiver to RS232 1 input allowing detection of a connected terminal to this port This line is simply a PI O input line to the MPC8260 When RS232 Port 1 is disabled t
24. ATM Chip Select equations AtmUniCsOut B oe H 5 132 8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc AtmUniCsOut_B AtmUniCsIn_B Power On Reset equations S PORIn B clk SYSCLK 5 PORIn Baar 0 S PORIn 0 S PORIn B PORIn oe oe oe oe oe oe LOGIC equations equations JtagStateReset Trst_B 4 PORIn only for jtag state machine JtagReset Trst_B PORIn_B JtagResetState fb global reset JtagState clk Tck JtagState ar JtagStateReset fb JtagState ap 0 Standard JTAG state machine state_diagram JtagState state RESET if Tms then JTAG_IDLE else JTAG_RESET state JTAG_IDLE if Tms then JTAG_SELECT_DR else JTAG_IDLE state JTAG_SELECT_DR DR if
25. CM42AH 19 440 ppm 5V Supply 4 pins 8 pin DIP form factor U7 U9 U23 U37 Quad CMOS buffer with individual Motorola 74LCX125P Output Enable 08 020 021 Octal CMOS Buffer Motorola 74LCX541J 010 Voltage Regulator Variable 1 5 Motorola LM317D2T output D PAK package U11 3 3V Linear Voltage regulator 5A Micrel MIC29500 3 3BT output U12 MPC8260 2 nd generation Power Motorola 8260 QUICC Socket for the above 480 pin ANDON 0 29 05 480 286 G04 N10 1 27mm PGA to PGA 29 X 29 array gold plated contacts Adaptor PGA to BGA 480 pin 0 29 05 480 27 30 10 1 27 29 X 29 array gold plated contacts Socket for the above 480 pin E Tec BPW480 1270 29AD01 1 27mm PGA to BGA 29 X 29 array gold plated contacts screw lock 013 014 SDRAM 2 Banks 512KBytes Fujitsu MB811171622A 100 16 100MHz 015 034 Secondary Cache 256KByte Look Motorola MPC2605ZP66 Aside for PowerPC Microprocessors MOTOROLA Chapter 5 Support Information 5 105 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 5 9 MPC8260ADSL2C Bill Of Material Reference Designation Part Description Manufacturer Part 016 Clock Generator 66MHz 40 MHz M TRON M3H16FCD 3 3V Supply 4 pins 8 pin DIP form factor 017 128 64 64 I O 128 Macrocell Vantis 4 128 64 7
26. Power Reset definitions k k kkk kkk k k PON RESET 0 PON RESET S PORIn B fb PON RESET ACTIVE Chapter 5 Support Information 5 115 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Register Access definitions BCSRO ADD 0 BCSRI 1 BCSR2 ADD 2 BCSR3_ADD 3 VGR_WRITE_BCSR_0 IBrdContRegCs B amp DVal B amp B amp A27 amp A28 amp A29 VGR_WRITE_BCSR_1 IBrdContRegCs B amp DVal B amp amp A27 amp A28 amp A29 VGR WRITE BCSR 2 IBrdContRegCs B amp IDVal B amp B amp A27 amp A28 amp A29 VGR WRITE BCSR 3 IBrdContRegCs B amp DVal B amp B amp A27 amp 28 amp 29 VGR WRITE BCSR 4 IBrdContRegCs B amp IDVal B amp B amp A27 amp A28 amp A29 VGR WRITE BCSR 5 IBrdContRegCs B amp DVal B amp B W amp A27 amp A28 amp 29 VGR WRITE BCSR 6 BrdContRegCs B amp DVal B amp B W amp A27 amp A28 amp A29 VGR WRITE BCSR 7 IBrdContRegCs B amp IDVal B amp B W amp A27 amp A28 amp 29 VGR READ BCSR 0 IBrdContRegCs B amp IR amp A27 amp A28 amp A29
27. S 0 mimm lt 4123 127001 lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt 9 Yan 1126 L2TMS TI 4 90 ol 08 lt aa lt 2 co 2 lt 9 aro 4 4126 L2TRST gt 555 z lala alo z Z Z5 55 ool ajte alajelale 3 921922929 D29 29 8583838358825 5550 BE 555 NNN i CPUBR H2 e uar lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt 22 ea Pad RACK Saget 2 CPU3BR ARTRY 2 2605 Le ae rast K3 TBST E Meus C3 LIE E3 epum L2 CACHE ASSEMBLY NOTES Tx HI TEA CRUSE T ASSEMBLED L2CACHE wr 13 WT 1 U15 U18 U19 U34 CPUDBC 2 R34 R35 R45 R47 R50 851 852 R54 866 R61 R62 22 120887 D3 lt pU2DBG 3 RN25 RN26 RN40 4 C17 C18 C19 C21 C22 C25 C26 C27 C32 CB1 82 83 89 90 cor E19 gt T2 apyapac C91 C94 C95 C96 C97 C98 L2BR 1280 5
28. oe oe oe oe K K K External Read Registers Chip Selects equations Bcsr2Cs B oe Besr2Cs_ B VGR READ BCSR 2 Read Registers registers have read capabilty BCSR2 is read externally equations DataOe READ BCSR_0 VGR READ BCSR 1 ifdef JTAG READ DOWNLOAD READ JTAG DOWNLOAD CSR j IN FLASH amp FlashCs B amp DSyncHardReset_B fb Data oe DataOe fb when VGR READ BCSR 0 then Data ReadBesr0 else when VGR READ BCSR 1 then Data ReadBesr1 ifdef JTAG else when READ JTAG DOWNLOAD DATA then Data JtagShiftDR fb else when READ JTAG DOWNLOAD CSR then Data JtagC S Reg H else when FIRST CFG BYTE READ then MOTOROLA Chapter 5 Support Information 5 129 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Data
29. 22 822 C22 022 A23 tl 82519 023 VA o A 4 5 G 010 24 5 024 gt zT A25 825 EXPD11 C25 025 0 A26 826 5 EXPD12 26 2215 Frets Zu ae 1 o O t EXPD15 c29 29 ss A 231 t 2 5215 0 5 16 LL i CND chi GND 6 Y v 8 PROJECT MPC8260ADS REV PILOT SHEET 16 OF 18 8 ENG YAIR LIEBMAN BLOCK CPM EXPANSION CONN II CHK 3 DESCRIP A B 9 tmp mnt users yair voyager ads pilot sch 17 drw 22 OCT 99 15 33 lost update 22 OCT 99 15 32 241123 L2TCK NID DW O S 00 O S
30. SdramA2 PIN 15 istype SdramA3 PIN 16 SdramA4 PIN 20 istype com SdramA5 PIN 21 istype com SdramA6 PIN 22 istype com SdramA7 PIN 23 istype com Tatched Address lines 10 istype reg_D buffer LA11 NODE istype D buffer LA12 NODE istype D buffer LA13 NODE istype D buffer LA14 NODE istype reg_D buffer 15 NODE istype reg_D buffer LA16 NODE istype reg_D buffer 17 NODE istype reg_D buffer 18 NODE istype reg_D buffer 19 NODE istype D buffer col LA21 NODE istype D buffer LA22 NODE istype D buffer LA23 NODE istype D buffer LA24 NODE istype D buffer LA25 NODE istype D buffer LA26 NODE istype D buffer LA27 NODE istype D buffer LA28 NODE istype D buffer Constant Declaration sk k 3k k K R Ok k k ok ok 2k ok ok ok K H L X Z 1 0 X Z C D U C D U
31. MODCKHO PIN 81 MODCKHI PIN 85 MODCKH2 PIN 79 MODCKH3 PIN 66 Data Buffers Enables and Reset configuration support LIE PIN 61 Transfer Error Acknowledge DataBufEn_B PIN 9 istype com invert data buffer enable ToolCs1 B PIN 30 comm tool cs line 1 ToolCs2_B PIN 91 comm tool cs line 2 ToolDataBufEn B PIN 6 istype comjnvert tool data buffer enable Hard Reset Configuration Logic FlashConfEn_B PIN 10 enable signal from external switch JTAG Logic JtagEn NODE istype reg buffer Tdi PIN 56 Tdo NODE istype reg buffer clocked by falling TdoOut PIN 82 istype 14 Tms PIN 47 Trst_B PIN 46 5 110 8260 PowerQUICC ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PonResetOut PIN 68 istype com active high
32. T 14 CLK3 1 028 805 995 05 40 TSTATS i5 1 029 BD6 11 TSTATG 1 030 34 _L2CLEAR 7 12146 2653 7 1 03 1 35_L2LOCK v2 ora 38 4 mE 1001052 211 00 1 032 MMI 426 BD8 13 36 TOOLREVO TOOLREV RS_ENIN 92 42 58205 9311 01 033 42 4 869 talaa 4135 ZENZ 1 02 1 034 4 16 33 TOOLREV2 gt ATMEN 94 44 PBI 010 018 1 03 1 035 8011 17 32 TOOLREVS FETHIEN 95 036145 8 221 053 01152 5 ATMRST 96 1 05 1 037 46 RNZO 8 416 27 1 06 1 038 27 IMS 8012 19145 12150 EXTOLID XTOLI 0 3 1 07 1 039 lt lt 15 20 21 p13 29 4 FETHRST 3 53 DIMMSIZE 8014 221 4 014127 EXTOLI2 1 08 1 040 8015 23 26 EXTOLI3 al 041 64 LIF LUSH 015 18 26 27 511 010 042 55 6 3 547 at lt lt MEM 5 2044 5 Ans m 1 036 aCSR2CS 1 012 04427 gt 228 Ge 3 V 1 045 853 SR gt 74LCX16244 ER 10 014 0560 BB6 8016 2002 0 47 SWOPTO 1 015 1 047 8017 512 01146 SwoPT1 i 8018 5 44 L2CEC0 L2INH 1511 016 5 642 025 12 1 6 WHITE 3 ABRO HRESET 16 4617 S MODCKH3 03 or 4 o D XU ABR1 12 2046 87 Li 9020 ABRO 18 17019 1 05 1 68 8020 8 41 BREVO REV 0 3 06 x RSTI 19 69 F PD2 04
33. BCSR 0 LIE equations ClockedContReg clk SYSCLK ClockedContReg ar 0 ClockedContReg ap 0 DrivenContReg oe hfff state_diagram PBI state PBI IN ACTIVE if VGR WRITE BCSR 0 amp PBI DATA pin IN ACTIVE amp RESET PBI PON DEFAULT PBI IN ACTIVB PON RESET amp PBI PON DEFAULT PBI IN then IPBI IN ACTIVE else PBI IN ACTIVE state IN ACTIVE if VGR WRITE BCSR 0 amp PBI DATA pin PBI IN ACTIVE amp RESET PBI PON DEFAULT PBI IN ACTIVE PON RESET amp PBI PON DEFAULT PBI IN ACTIVE then PBI IN ACTIVE else IPBI IN ACTIVE state_diagram DimmSize 5 122 MPC8260 PowerQUICC ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc state DIMM SIZE 16M if VGR WRITE BCSR 0 amp DIMM SIZE DATA BIT pin DIMM SIZE 16M amp RESET DIMM SIZE PON DEFAULT DIMM SIZE 16 PON RESET amp DIMM SIZE PON DEFAULT DIMM SIZE 16 then IDIMM SIZE 16M else DIMM SIZE 16M state DIMM SIZE 16M if VGR WRITE BCSR 0 amp DIMM SIZE DATA DIMM SIZE 16M amp RESET DIMM S
34. OOo lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt 4 lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt Ci 1l m lt lt aedgoudagcodgdadgggdgdgaadgdgdogaagadagadgodgagaoagggddoc peranga 4 4844444444484444444444444444444 Sees amp 5854548 S gt gt 5 5 gt gt lt lt 00 lt lt wo M 4 o e x N 8 55555 55859898 Ss 3 888988 gaia 313 PROJECT MPC8260ADS REV PILOT SHEET 1 OF 18 YAIR LIEBMAN BLOCK VOYAGER SYSTEM CHK DESCRIP D amp fa K L M N tmp mnt net prince yair voyager ads pilot sc h 2 drw 26 SEP 99 19 02 last update 26 SEP 99 19 02
35. A16 ATMRXD6 B16 9 16 cie PC16 0165 SDCFCDT 7 5 ATMRXD5 817 G PB15 15 51715 SDCFGCK aia 5 ATMRXD4 aia 2814 5 85601 _ 018 es PD13 A19 ATMRXD3 gio S PB13 eie 5 PC13 019 TS PD12 A20 ATMRXD2 820 5 PB12 c20 G 85 02 D20 5 u PD11 21 S ATMRXD1 82115 PB11 cn PC11 021 0 PD10 A22 5 ATMRXDO 822 PB10 c22 5 0221 5 PDS A23 PAS 823 PB9 c23 5 FETHMDO D23 24 824 5 PBB D24 o PD7 25 lt PA7 825 5 PB7 22516 PC7 025 5 7 PD6 26 8261 5 PB6 C26 5 026 PD5 A27 PA5 827 5 627 5 PC5 027 5 04 A28 lt 4 828 5 PB4 C28 5 PCA 028 lt ATRCKDIS 29 5 829 5 ATMRCLK 2915 PCS 029 5 o 8 o A30 PA2 830 G PC2 030 5 A31 831 C31 PC1 031 A m 832 Pca 03270 O u vee GND L i 6 7 7 MOTOROLA 8 PROJECT MPC8260ADS REV PILOT SHEET 15 OF 18 8 ENG YAIR LIEBMAN BLOCK CPM EXPANSION CONNECTOR 1 CHK DESCRIP A B 6 9
36. o fa en n dS RERO 43 aa 46 COP JPAG Port Softe Reset 46 46 Internal Sources Soft 46 Local NP 46 ABORT e 46 47 Fast Ethernet Transceiver ra retia 47 Clock 47 B s y T 47 Single MPC8260 Mode 48 60x B s M6de qo sagi itas h Seot 48 MULE PST LIND NH HM E 48 ay Su 48 Synchronous DRAM DIMM 60 Bus 49 SDRAM Programming eese tio ul Esa ARR LE 52 SDRAM Re Ireshu uu ass 52 L2 Cache Support Influence On SDRAM Design 53 SDRAM DIMM Configuration Information 53 EI3shMeriory SMM L l 53 Flash Protection LOTi orsa u asa 54 Flash Programming cused amy antes 54 Blashand 2 55 Hard Reset Configuration MPC8260 Revision Dependency 55 Local Bus Synchronous DIS ANI 55 Local
37. CND 9 FETHCRS AST nse ces rab AHS RN 8 RS CIS2 S W CONTROLLED gt 24 08 r EE Da 5 45 AES pB25 TxD4 TxD3 PD25 RXD T D6 09 PD25 T SA 0155 9 3 QFETHTXD2 78 7 22 2 J9 585 PD24 TXD R D5 10 PD24 5 pace 322 415 FETHIXD 8 22 1 RN79 15 2 PD23 RTS RxD4 12 PE 3 c5 FETHIXDO RN 66 22 16 5599 7x07 TxDO PD22 RXD T D5 412 2022 28 FETHRXDO 5 22 4RN 6 AH pB21 RxD7 RxDO PD21 TXD RxD 3 AP 13 PA 5 88 EN2 154 DSCONN FETHRXOT RN 97 22 2 012 pp20 RxD6 RxD1 PD20 RTS RxD2 414 xw 1 24 8 17 2 RN7O AF13 19 RxD5 RxD2 PD19 TxAD4 SPISL ARIS 2019 PD 18 25 MC145583 PETHRADS 14 pg 18 RxD4 Rx03 PD18 RxADA SPicL 16 Pota 19 Txt _ 85202 RXD Q 3 17 DV LIRG ACI _ ATMRXPTY 17 2 12 1 6 16 AJ18 PB16 RX_ER L1CLK PD16 TxPrty AG18 22 8 15 DIZ T3 14 TXD2 2 6 AF 19 15 _ PDi5 RxD1 I2CSDA 128 7 3 33 6 SDCFGDT END 14 RN77 722 2 20 59 44 TX_EN RXD PDi4 RxD I2CcscL AE20 4 22 5 1 __221 001 2 2 i 2818 8221 RN 1 _ AH21 ppt 3 COL LIRO PD13 L1ST1 L1TxD A922 RN 7 2 23 7 2015 1002 8 8 PHI RN TA AC22 PB12 CRS L
38. SA2 6 Rag lt TSTAT2 7 LD22 amp s 5 L2INH 4 4 L2CFG3 1798 TSTAT3 6 CD 1023 915 056 5 BREV3 1 L2BR 3 3 R35 TSTAT4 4 M4 12867 2 sal L2CF G4 1 5 5 3 57 9 RN9 8 oc 12086 1 x R TSTAT6 2 CND CND FETHFDE 5 BALE 10K TSTAT7 1 R135 1024 1 PSDDP6 5 3 3 5 3 3 CHIPS 025 PSDDP2 FETHCFCT 0 S lt 2 8152 sy 1026 3 PSDDP7 j ue C RST1 95 LD27 4 Z y PSDDP3 4 FUE o 8 RSTO 8 LOAPE 8 2 ECEGENS 9 LD31 6 PSDDP1 6 ic DQM_WE4 7 lt gt 7 L2CI AES 5 1030 gt 230026 7 et DOM_WE2 6 6 gt _ __6 029 48 PSDDP5 I DQM_WE7 4 FETHRST 4 xt TP gt 1028 915 PSDDP4 o ayy DOM WEG 3 ATMRST 3 xil i DQM WE5 2 x2 x2 Jm 3 3 RN42 RN11 AM DQM_WE3 1 xi QA GND GND Gerd m TTO 1 1 120 1 4 R52 133 CO 2 gt 02004 2 L2CFG1 ans2 le 3 3 D gt TSIZEQ 3 12023 3 R GRE 435 82624 4 gt Berio BcsRcs 8 L2HIT TMS 9 x RN33 TSIZE3 6 L2TRST 830 ono 7 SDRMCS2 7 4178 D gt APE of x 1861 7 59 e s
39. Since FDS MDINT of the LXT970A is an open drain output it is possible to connect additional off board interrupt requesters on the same IRQ7 provided that they drive IRQ7 with an open drain gate as well The FDS MDINT is a dual functionality signal on its FDS Full Duplex Status function it indicates whether the LXT970 is configured to Full Half Duplex mode while in its alternate function it serves as the transceivers MDINT active low output In order to achieve this functionality bit 1 in register 17 17 1 must be SET after the ADS comes out of Hard Reset Setting this bit is allowed through the MDIO port of the LXT970 Data of which is driven sampled by PC9 of the MPC8260 while its Clock is driven by PC10 Failure in doing so will result in IRQ7 pin of the MPC8260 constantly asserted low 4 3 Clock Generator The MPC8260 requires a single clock source for the main clock oscillator All MPC8260 bus timings are referenced to the main clock input CLKIN unlike the 8 family timings of which are referenced to CLKOUT signal The main clock input is in 1 1 ratio to the bus clock with an internal skew elimination PLL This uses a 66MHz 3 3V clock generator which is connected to a low interskew buffer to split the load between all various clock consumers on board Special care is taken to isolate and terminate the clock routes between the clock distributor and on board consumers this to provide clean clock inputs for prope
40. 1 55 74LCX125 ir RFP 2 3 70 A C4 OPTIC_IF 4 VCC AJK 40 Rere ES lt P RX HFBR 5205 amp ypo 2 8154 rete 28 5 02 axon 3 50 4 7 u LED_GREEN o as 9 R I 41 an 6 5 ouri i 9 19 p gt gt 4 PM5350 50 29 ASE 4 TX o ut TCP 6 R161 6 88 741 125 LD1 tore 51 8198 LED_GREEN 52 i CCND o 8 TDAT7 95 ATMTXD7 ATMTXD 0 7 94 AIMIXD6 80 0 7 BDO 5 117 07 93 5 74LCX 125 o 801 5 melis 92 04 12 11 422 e 802 115 55 21 82 A 803 gd 11415 90 2 gt 804 141 55 89 ATRCKDIS 805 qx 110 52 88 806 109 1 ATMTXPTY 807 844 108 96 15 RNS 97 ATMTSOC 6 J8 ATMCSO 100 TSOC Pse 4 ATMTCA BBCTLO 99 Cs 121 11 ae ATMTXEN L RD TWREN 74LCX125 4 ATMRST 101 86 ATMF CLK 104 ALE ET J20 8122 45 vec ap 339 1206 107 ANALOG ANALOG DIGITAL 859 y gt RIM 59 PANIS EN CO T to wo TSEN 0 NMN m 22902 0060 1 7 lt
41. 7 38 8 39 9 40 10 44 45 col A20 PIN 46 Address Output lines SdramA8 PIN 9istype com SdramA9 PIN 24 istype com SdramA 11 PIN 23 istype com Tatched Address lines 6 NODE istype reg_D buffer LA7 NODE istype reg D buffer LA8 NODE istype reg D buffer 9 NODE istype reg_D buffer LA10 NODE istype reg_D buffer NODE istype reg_D buffer col LA20 NODE istype reg_D buffer Constant Declaration H L X Z 1 0 X Z C D U C D U Signal groups Add A6 A11 A20 LAdd LA6 LA11 LA20 RowAddNormal LA8 LA10 LA11 RowAddPBI 16M LA7 LA9 LA10 not really required RowAddPBI 64M LA6 LA8 LA9 ColAddNormal LA8 LA10 LA20 5 144 8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On
42. ALPHA FCC 301 16 90 With Latches P6 P7 P8 P9 P10 P12 P13 P14 Connector MICTOR 38 pin SMD AMP 2 767004 2 P15 P17 P18 MOTOROLA Chapter 5 Support Information For More Information On This Product Go to www freescale com 5 95 Freescale Semiconductor Inc Table 5 8 MPC8260ADS Bill Of Material Reference Designation Part Description Manufacturer Part Pll Connector header 10 pin dual in SAMTEC TSM 105 03 S DV line SMD P19 Connector 3 pin Power Straight WB 81135 253303353 with false insertion protection Connector 3 pin Power Plug WB 8113B 253200353 R2 R4 R124 R139 R140 Resistor 51 1 0 1 SMD 0603 RODERSTEIN D11 SIRIFCS R148 R149 R151 R152 R153 0 1W R3 R154 Resistor 75 5 SMD 0603 0 1W DRALORIK 011 075RFCS R5 R6 R133 Resistor 82 5 Q 5 SMD 1206 1 DRALORIK D25 82R5FCS 4W R7 Resistor 22 1 5 SMD 1206 1 DRALORIK D25 22K1FCS 4W R8 R39 R44 R49 R56 R57 R77 Resistor 43 2 Q 1 SMD 0603 RODERSTEIN D11 43R2FCS R88 R94 R95 R96 R100 R112 0 1W R121 R9 R10 R11 R25 R26 R60 R65 R90 Resistor 0 O SMD 0603 0 1 W RODERSTEIN 011 000RFCS R103 R107 R110 R113 R115 R116 R117 R119 R142 R13 R14 R15 R16 R17 R29 R31 Resistor 10 1 SMD 0603 RODERSTEIN 011 010KFCS R33 R46 R48 R53 R58 R59 R66 R67 0 1W R18 R19 R122 R125 R128 R129 Resistor 4 7 1 SMD 0603 RO
43. This line may be used off board as an clock line for external device as long as the addresses of the SDRAM DIMM and the external device s do not conflict See 2 4 8 2 SDRAM DIMM Installation on page 27 and 4 7 Synchronous DRAM DIMM 60X Bus on page 49 5 80 8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 5 4 P4 CPM Expansion Interconnect Signals Pin No Signal Name Attribute Description 19 PD13 T O T S 8260 PD 13 4 Port D lines Parallel I O or CPM dedicated lines May be used for any of their available functions A20 PD12 21 PD11 A22 PD10 A23 PD9 A24 PD8 A25 PD7 A26 PD6 A27 PDS A28 PD4 A29 ATRCKDIS I ATM Receive Clock Out Disable When active H the ATMRCLK output on pin C29 of this connector is Tri stated When either not connected or driven low ATMRCLK on pin C29 is enabled This provides compatibility with ENG revision of T ECOM communication tools A30 VCC 5V Supply Connected to ADS s 5V VCC plane Provided as power supply for external tool For allowed current draw see Table 4 22 Off board Application Maximum Current Consumption on page 75 1 T S ATM Transmit Enabled L When this signal is asserted Low while the ATM port is
44. atm uni enable MPC8260 PowerQUICC II ADS User s Manual For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc AtmRst_B istype reg buffer atm uni reset bit AtmRstOut_B PIN 96 istype com atm uni reset driven by register or by HRESET FEthEn B PIN 95 istype reg buffer fast ethernet trans enable FEthRst_B NODE istype reg buffer fast ethernet trans reset bit FEthRstOut_B PIN 3 istype com fast eth trans reset driven by register or by HRESET RS232Enl B PIN 92 istype reg buffer RS232 port 1 enable RS232En2 B PIN 93 istype reg buffer RS232 port 2 enable Board Status Registers Chip Selects Besr2Cs_B PIN 42 istype com Flash Associated Pins PDI 71 PD2 69 PD3 67 PD4 65 FlashCs_B PIN 31 flash bank chip select FlashCs1 B PIN 58 istype com Flash bank1 chip select FlashCs2 B PIN 48 istype com Flash bank2 chip select FlashCs3_B PIN 45 istype com
45. cet C64 C56 C48 555 c69 C54 C46 C45 53 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 10 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 052 C44 C43 551 1UF C40 C39 C37 C38 C42 641 549 650 C80 C47 C70 71 C75 C72 C73 C74 1UF Q 1UF Q 1UF Q 1UF Q 1UF Q 1UF Q 1UF Q 1UF Q 1UF 1UF 2 0 10 Q 1UF Q 1UF Q 1UF Q 1UF 1UF Q 1UF Q 1UF Q 1UF C78 C117 C109 C130 C118 C111 C119 C134 C120 C112 C163 C162 161 coo C15 C24 C16 C20 C77 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 10 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 10 0 1UF 0 1UF 0 1UF SPARE HOME a 10 579 576 6129 C14 C84 C23 1UF Q 1UF Q 1UF Q 1UF Q 1UF Q 1UF 1UF C67 1095 47UF ATUF C108 C123 C138 C107 C140 C113 C115 C127 C139 C126 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 140 2103 C179 C172 C168 C169 C174 C182 C58 C57 C88 C86 C87 092 C85 C159 160 1065 0 10 Q 1UF Q 1U
46. 15 5 6 7 VTDI 1 BR 3 12020 8 4 lt gt SPARET 6 5 xs TOOLCS1 3 4 SPARES 4 s 6 ss _ TOOLCS2 2 y 002 PARES 5 4 Pull Downs sORMCS1 MODCK 1 2 SPARE4 2 TEST 3 GND GND 1 QREQ 1 C x2 lt gt _ 1 MOTOROLA INC 8 PROJECT MPC8260ADS REV PILOT SHEET 12 OF 18 8 ENG YAIR LIEBMAN BLOCK PULL UP DOWN RESISTORS 35 3V Pull Ups NOT ASSEMBLED CHK DESCRIP A B 9 tmp mnt net prince yair voyager ads pilot sch 13 drw 26 SEP 99 19 06 last update 21 SEP 99 18 45
47. 24 9 PD23 10 PD22 All PD21 12 20 13 PD19 14 PD18 15 PD17 T S ATM Receive Parity Line When the ATM port is enabled this line is connected to the receive parity of the PM5350 ATM UNI When this port is disabled this signal is tristated and may be used for any available function of PD17 Al6 ATMTXPTY PD16 T S ATM Transmit Parity Line When the ATM port is enabled this line is connected to the transmit parity of the PM5350 ATM UNI When this port is disabled this signal may be used for any available function of 16 17 SDCFGDT PD15 T S SDRAM Configuration Data This signal is connected to the serial re data line of the SDRAM DIMM configuration Serial EEPROM holding all DIMMs configuration data This line is used in conjunction with SDCFGCK to read or write this memory using the PC protocol This line may be used off board as an data line for external device as long as the addresses of the SDRAM DIMM and the external device s do not conflict See 2 4 8 2 SDRAM DIMM Installation on page 27 and 4 7 Synchronous DRAM DIMM 60X Bus on page 49 A18 SDCFGCK PD14 T S SDRAM Configuration Clock This signal is connected to the serial Pc clock line of the SDRAM DIMM configuration Serial EEPROM holding all DIMMs configuration data This line is used in conjunction with SDCFGDT to read or write this memory using the
48. 3 ATMRXD4 AG19 pA44 RxD4 RxD12 PC14 CD RxADO 5 01 1 002 8 8 MEME 20 41 35 RD 3 RXD11 PC13 CTS_ LIRQ AH 18 PCTS 20 03 Rx3 9 DTR1 4 2 J21 pA12 RxD2 RxD10 PC12 CD_ L1ST3 18 RS CD2 18 Rx4 ATMRXD AH22 pA41 RxD1 R lt xD9 PC11 CTS L1CLko AE 19 2347 PCT 76 pos Rx5 5 ATMRXD0 22 r 62 20 077 132 g Sfi 0 9 6 RR 3 AH23 PAQ SMTXD L1TXDQ PCO CTS_ TxD1 AE21 4 22 5 RN71 FETHMDIO gt 55 PA8 RN72 AF23 bAg SMRXD LTRXDO 22 1 AH25 pA7 SMSYN L1TSYN PC7 CTS_ L1RQ UPPER CONN PAG 24 PAS LIRSYNC PC6 CD_ LICLKO a 2 AG26 5 A5 RSTRT_ DREQ PCB TxClAv L1ST3 m PAS 28 pA 4 RJCT DONE _ PCA RxEn L1STA s etos 4 ena PAS A628 PA3 CLK19 DACK PC3 CTS_ TxD2 AE28 A2 CLK20 DACK PC2 CD_ TxD3 x mE PA1 RJCT DONE PC1 DREQ LIRO EE PCO DREQ SMSYN m PETHTXER 6 33 3 59 31 TX_ER RxSOC 02 4 Tus BEI RN69 _ AC5 pa3Q Rx DV T lt xSOC 404 4 72 5 RS TXDT FETHTXEN 9 29 3 185 PD29 RTS_ RxaD3 ACI RN69 RS CIST Pl O S W CONTROLLED 4 5 monk RN 5 AE3 p828 RX_ER RTS PD28 RXD TxD7 4 RSZRXD2 T6157 S 8 22 6 5827 coL TxDQ PD27 TXD RxD7 2 32
49. CfgByte0 else when SCND CFG BYTE READ then Data CfgBytel else when THIRD CFG BYTE READ then Data CfgByte2 else when FORTH BYTE READ then Data CfgByte3 Reset Logic k k k kk kkk equations Reset oe Reset 0 open drain RstDeb1 Rst1 amp RstDeb1 fb amp 510 Reset push button debouncer AbrDeb1 Abr1 amp AbrDebl fb amp Abr0 Abort push button debouncer HardResetEn RstDeb1 fb amp AbrDeb1 fb both buttons are depressed SoftResetEn RstDeb1 fb amp AbrDeb1 fb only reset button depressed TransRst oe 3 transceivers reset always enabled AtmRstOut_B AtmRst HardReset FEthRstOut_B FEthRst B fb HardReset Hard reset configuration equations RstConf_B oe H RstConf_B L LIE 5 130 MPC8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc NMI generation equations N
50. JtagIR fb hold value Download Shift Bypass Register equations JtagShiftDR clk JtagShiftDR ar JtagStateReset fb JtagShiftDR ap 0 when JtagShiftDrState fb amp INST IS BYPASS JtagShiftDrState fb amp INST IS DOWNLOAD amp JTAG DOWNLOAD SHIFT REG FULL then JtagShiftDRO JtagShiftDR7 Tdi JtagShiftDRO fb JtagShiftDR 1 fb JtagShiftDR2 fb JtagShiftDR3 fb JtagShiftDR4 fb JtagShiftDR5 fb JtagShiftDR6 fb else JtagShiftDR JtagShiftDR fb hold ROROR Receive Full Flag 5 136 MPC8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc equations JtagReceiveFull clk Tck JtagReceiveFull ar JtagReceiveFullReset fb JtagReceiveFull ap 0 when STATE JTAG DR INST IS DOWNLOAD then end of download byte JtagReceiveFull RECEIVE FULL else JtagReceiveFull JtagReceiveFull fb maintain value Receive Full Flag Reset SReadJtagDownloadData clk SYSCLK SReadJtagDownloadData ar 0 SReadJtagDownloadData ap 0 SReadJtagDownloadData READ JTAG DOWNLOAD DATA DVal JtagReceiveFullReset SReadJtagDownloadData
51. SRESET m REMOVED For L2CACHE E2 L2086 5 L2SRST N1 1 R25 R26 019 120 SRESET CZCI J3 2 RN15 RN18 RN23 F2 L2HITS PWRON L2F LUSH 01 rose wg L2LOCK _ 83 2 120 0 L2CLEAR N2 CLR EINE 3 0 2 a lt L2CF CQ U2 ais ered 2 1 F 1781 L2 Cache Module CFG2 0 DP6 E 854 12 03 E17 83 L2CFG4 82 lt gt CFG4 OS oq Ore QUO SP ID o gre u x O S L2CF G 0 1 L2CF G 3 4 SIPI fT TI Irrig SSR 975 9939g97599575 5 5555 55599 9990999949 C irc m u15 00 wl Ss o o 00 00 00 gt 5 gt gt 5 5 as lt o lt lt S m lt gt gt 3 z gt 3 gt Z gt Z gt gt lt mim lt m lt m lt ajo sri i Ol S TW 9 r 9
52. Warning The job of removing J6 and soldering current meter con nections instead is very delicate and should be done by a skilled technician Ifthis process is done by unskilled hand or repeated more than 3 times permanent damage might be inflicted to the MPC8260ADS 3 2 14 77 VPP Source Selector J7 selects the source for VPP programming voltage for the Flash SIMM When jumper is located between pins 1 2 of J7 Factory Set the VPP is connected to the VCC plane of the ADS providing 5V VPP When a jumper is located between positions 2 3 of J7 VPP is drawn from P2 that provides 12V VPP if P2 is indeed connected to a 12V supply J7 options are shown in Figure 3 4 J7 VPP Source Selection below MOTOROLA Chapter 3 Operating Instructions For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Figure 3 4 J7 VPP Source Selection EX XO 5V VPP 12V VPP Factory Set 3 2 15 GND Bridges There are 12 GND bridges on the MPC8260ADS 11 designated as GND reside on digital ground and 1 designated as AGND resides on analog ground plane Only 4 of the 11 digital GND bridges are actually as sembled the rest are SMD bridges and are optional These bridges are meant to assist general measurements and logic analyzer connection Warning When connecting to a GND bridge use only INSULAT ED GND clips Otherwise un insulated clips may cause short circ
53. lt lt 18 S pal ba ra 4 2 IRQS ROTS o r PERRA mo lt bad ood bad Poni bai bad ANNA a w lt wD oj ajoj o lt lt 9 9 9 o Of lt w w lt lt Of w lt lt lt 2 9 ws lt w o oj w aj o 2 2nF zx amp Q 9 i G O N rO s i O 00 0 9 9 x 10 00 O x i 0900 9 in Q we tr 1 0 lt rO rO QN C OV T9 72 Q Q r gt 2 136 2155 EE 2 AB2 yfe 9 VCC
54. s Latch Mux Low L2 Cache Only MODULE vmuxlow5 TITLE 8260 Sdram 1st Latch Mux Pins declaration Control pins Ale 5 AleIn PIN 29 AleOut B PIN 27istype com inverted AleIn connected externaly to Ale B RCB 33 DimmSize PIN 37 PBI PIN 25 Address Input lines row 10 34 PIN 1 12 2 13 PIN 3 14 PIN 9 15 10 16 PIN 11 17 12 18 PIN 35 19 36 col 21 PIN 38 22 39 23 40 24 44 25 45 26 46 27 47 28 48 Chapter 5 Support Information 5 139 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Address Output lines SdramA0 PIN 13 istype SdramA 1 PIN 14 istype
55. 22 1025 LOPS 33 134 1420 LD8 23 24 1024 LA14 35 3 36 LA3Q LD9 25 26 1025 LA15 37 38 LAST NEAR JTAG CONN 1010 27 28 1026 LSB 1011 29 38 1027 MICTOR 58 1012 31 32 1028 013 33 34 1029 MOTOROLA INC 8 LOTS baH 7 PROJECT MPC8260ADS REV PILOT SHEET 13 OF 18 8 015 37 38 LD31 SB ENG YAIR LIEBMAN BLOCK SYSTEM L A Connectors MICTOR 38 CHK DESCRIP A B 3 J K
56. 3 6 0 5 1206 l Ape MEA Gents GND d 2 R82 FEE R65 12 2 lt gt E NEC 3 FUSE Toge 4820 zi gt 2 TAUF 9 036 5 TRIMMER 4920 CND PWR2 FAC SET 1 2 BY i F 1A MBRDE20CT S GND as 71 9 GND 06 2 7 h m UR F Mus Sect 5 122 e 1 3 1 4004 2 RS vec 1 31702 122 10 1206 VCCSYN 1905 OUT e e 2 gt 12 E kx FACTORY_ SOLDERED d Tu ES lt a C134 Q 1UF 10UF 10UF 10UF 10UF o U10 1 E 47UF 0137 te 5 T lt 65 C6 C165 C164 uU AR po 5 o a ND FB lt CND 5 5 142 aes o his 4 1 1206 257205 FB 9 R63 J ae 7975 E 101 Q 1UF L3 0 1UF aye 0149 rau 47UF Ciis GND s C151 al z y 1 9V 2 7V 4 po 90 A782 5 2 duit uS E 2 16 rA 2 R 3 5V POWER 8 Q 7 128 TAVD1 LED GREEN S AJ R0 A T 1 gt 109 R71 9 gt _8 01 74LCX125 S 2 LED CREEN C 180 n 2 DBB 12 11 AG 4 RUN 92917 13 tio LED_YELLOW pA 2 A ARO 4 PORT ENAB
57. Case 1201 01 Motorola MC74LCX16245DT 027 028 027 028 Low Voltage CMOS 5V Tolerant 16 bit Transceiver with Bus Hold 48 pin Plastic TSSOP Low Voltage CMOS 5V Tolerant 16 bit Transparent Latch with Bus Hold 48 pin Plastic TSSOP Philips Philips T4ALVT16245DL T4ALVT16373DL U33 U35 U36 Octal Tri State Buffer 9 Output Low inter skew Clock Buffer Voltage level detector Range 2 8V 2 output 50 23 5 package Motorola Motorola Seiko 74 5410 947 S 80828ANMP EDR T2 U38 Fast Ethernet Transceiver Crystal resonator 25 Fundamental Oscillation mode Frequency tolerance 30 ppm Drive level 2mW max 10uW 100 recommended Shunt capacitance 5 Load capacitance 10pF min Equivalent Series Resistance 400 Max Insulation Resistance 500 MQ min Level 1 EPSON LXT970A 505 Matched Impedance Connector the BOM for the MPC8260ADSL2C with Level II Cache is presented in Table 5 9 MPC8260ADSL2C MOTOROLA Chapter 5 Support Information For More Information On This Product Go to www freescale com 5 99 Freescale Semiconductor Inc Bill Of Material on page 101 5 100 MPC8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 5 9 MPC8260ADSL2C Bi
58. DBB IRQ3 pin is DBB No masking on bus request lines AP 1 3 configured as BNKSEL 0 2 APE configured as IRQ7 and CS11 as CS11 18 05 CS10 configured as CS10 PCI is configured to agent mode not relevant for this application MODCKH 0 3 lProgrammed into the Flash memory in addresses 0x0 0x8 0x10 amp 0 18 and to BCSR With L2 cache Table 3 3 SIU Register Programming Register Init Value hex Description RMR 0001 Check Stop Reset enabled IMMR 04700000 Internal space 0x0470_0000 SYPCR FFFFFFC3 Software watchdog timer count FFFF Bus monitor timing FF PPC Bus monitor Enabled Local Bus monitor Enabled S W watch dog disabled S W watch dog if enabled causes reset S W watch dog if enabled prescaled BCR 004C_0000 Single MPC8260 60X Bus mode 0 wait states on address tenure No L2 cache L2 8844 4000 cache assumed 0 clock hit delay l level Pipeline depth Extended transfer mode Enabled disabled for PPC bus Extended Transfer mode Enabled for Local Bus Odd parity for PPC amp Local Buses not relevant for this application Non MPC8260 master on EXT_BR2 External Master delay enabled Internal space responds as 64 bit slave for external master not relevant for this application With L2 cache on board 3 4 2 Memory Controller Register Programming The memory controller on the MPC8260ADS is initialized to 66 MHz operation I e register programming
59. Flash bank3 chip select FlashCs4_B PIN 55 istype com Flash bank4 chip select 5346 ATM UNI Associated Pins AtmUniCsIn B PIN 22 AtmUniCsOut B PIN 21 istype com remove if short of pins Reset amp Interrupt Logic Pins B 97 RstConf_B PIN 28 istype com Hard Reset master select Rst0 PIN 20 connected to N C of Reset P B Rstl 19 connected to N O of Reset HardReset B PIN 16 istype Actual hard reset output O D MOTOROLA Chapter 5 Support Information 5 109 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SoftReset_B PIN 29 istype com Actual soft reset output O D 18 connected to N C of Abort 17 connected to of Abort NMIEn NODE istype enables 7 5 NMI pin NMI PIN 41 istype com Actual NMI pin O O D Power On Reset Configuration Support
60. Inc Issue MODE SET command When a Mode Register Set command is issued data is passed to the Mode Register through the SDRAM s address lines This command is fully supported by the SDRAM machines of the MPC8260 Mode Register programming values are shown in Table 4 4 66 MHz SDRAM DIMM Mode Register Pro gramming below Table 4 7 66 MHz Local Bus SDRAM Mode Register Programming i ERAN Mote Reg Value Meaning Linel Field MSB Reserved 0 10 70 9 o Burst Read amp Burst Write copy back A8 Reserved 0 7 Reserved 70 6 4 CAS Latency 010 Data Valid 2 Clocks cycles after CAS Asserted A3 Burst Type 0 Sequential Burst 2 AO Burst Length 7011 8 Operand Burst Length 155 l Actually SDRAM s 0 is connected to MPC8260 s A29 and so on 4 9 2 Local Bus SDRAM Refresh The Local Bus SDRAM is refreshed using its auto refresh mode I e using SDRAM machine two s periodic timer an auto refresh command is issued to the SDRAM every 13 4 usec so that all 2048 SDRAM DIMM rows are refreshed within specified 32 8 msec while leaving a 5 4 msec interval of refresh redundancy within that window as a safety measure covering for possible delays in bus availability for the refresh con troller 4 10 L2 Cache Optional To enhance benchmarking optional support is provided for L2 Cache This is implemented with two 2605
61. Tms then JTAG_CAPTURE DR else JTAG SELECT IR MOTOROLA Chapter 5 Support Information 5 133 For More Information On This Product Go to www freescale com 5 134 Freescale Semiconductor Inc state DR if Tms then JTAG_SHIFT_DR else JTAG EXITI DR state JTAG SHIFT DR if Tms then JTAG EXITI DR else JTAG SHIFT DR state JTAG DR if Tms then JTAG PAUSE DR else JTAG UPDATE DR state JTAG PAUSE DR if Tms then JTAG EXIT2 DR else JTAG PAUSE DR state JTAG EXIT2 DR if Tms then JTAG UPDATE DR else JTAG SHIFT DR state JTAG UPDATE DR if Tms then JTAG IDLE else JTAG SELECT DR state JTAG SELECT IR IR if Tms then JTAG CAPTURE IR else JTAG RESET state JTAG CAPTURE IR if Tms then JTAG SHIFT IR else JTAG EXITI IR state JTAG SHIFT IR if Tms then MPC8260 PowerQUICC II ADS User s Manual For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc IR else JTAG_SHIFT_IR state JTAG_EXIT1_IR if Tms then JTAG_PAUSE IR else JTAG UPDATE IR state JTAG PAUSE IR if Tms then JTAG EXIT2 IR else JTAG PAUSE IR state JTAG EXIT2 IR if Tms then JTAG UPDATE IR else JTAG SHIFT IR state JTAG UPDATE IR if Tms then JTAG IDLE else JTAG SELECT DR lt Ok ik k k sk sk ok Jtag
62. VGR READ BCSR 1 IBrdContRegCs amp IR amp A27 amp A28 amp A29 VGR READ BCSR 2 IBrdContRegCs B amp IR W amp A27 amp A28 amp A29 VGR READ BCSR 3 BrdContRegCs amp amp A27 amp A28 amp 29 VGR READ BCSR 4 IBrdContRegCs amp IR B amp A27 amp A28 amp 1429 READ BCSR 5 IBrdContRegCs amp amp A27 amp A28 amp 29 VGR READ BCSR 6 IBrdContRegCs amp amp A27 amp A28 amp A29 VGR READ BCSR 7 IBrdContRegCs amp amp A27 amp A28 amp 29 k k ok ok k ok ok ok ok k 3k k 3k k k k ok 2k BCSR 0 definitions sk k ok sk k 3k gt k k k k ok ok 2k 3 PBI ACTIVE 0 SIZE 16M 0 L2CACHE INHIBITED 0 L2CACHE FLUSHED 0 L2CACHE LOCKED 0 L2CACHE CLEARED 0 SIGNAL LAMP ON 0 Power On Defaults Assignments PBI PON DEFAULT PBI IN ACTIVE DIMM SIZE PON DEFAULT DIM
63. coded in the table below Table 4 8 CFG 0 2 Settings L2 Cache Size Byte CFG 0 2 256K 7000 Reserved 512K 7010 First Module A26 0 7011 Second Module 26 1 2 Snoop is Enabled CFG3 driven low for both modules 3 assertion enabled CFG4 driven high for both modules The caches HRESET lines are connected directly to the SRESET line of the MPC8260 so that whenever Soft reset 15 asserted to by the 8260 the cache is reset along with it loosing all data previously stored in it The cache has 5 control lines that control its operation and state PWRDWN which is constantly set to high no power down support on the ADS L2FLUSH assertion of which flushes out the cache array This signal is controlled by BCSRO L2MISS INH in fact Cache Lock When Asserted the cache does not change it contents Controlled by BCSRO L2TAG CLR Clears all tag memory Controlled by BCSRO L2UPDATE INH In fact cache freeze without information loss Controlled by BCSRO See Table 4 9 BCSRO Description on page 62 AII the above signals are connected directly to both cache modules 4 11 Communication Ports The ADS includes several communication ports to allow convenient CPM evaluation Obviously it is not possible to provide all types of communication interfaces supported by the CPM but it provides a convenient connection to communication interfac
64. on page 19 Changing the voltage to the Core logic of the MPC8260 obviously has an influence over the maximal speed of the core There 15 the power speed trade off i e lower operation speeds may be obtained with lower voltage supply 4 76 MPC8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 4 14 4 VPP Bus The sole purpose of the VPP bus is to supply VPP programming voltage for the Flash SIMM VPP may be connected to either 5V bus or 12V bus selected via J7 Normally VPP is connected to the 5V bus see Figure 3 4 J7 VPP Source Selection on page 32 The 12V bus is connected to a dedicated input connector P2 via a fuse 1A and is protected from over reverse voltage appliance in the same manner done with the 5V bus If either the Flash SIMM is 5V programmable or it is 12V programmable but need not be programmed the 12V supply input connector of the ADS P2 may be left un connected Chapter 4 Functional Description For More Information On This Product Go to www freescale com 4 77 Freescale Semiconductor Inc Chapter 5 Support Information In this chapter all information needed for support maintenance and connectivity to the MPC8260ADS is provided 5 1 Interconnect Signals The MPC8260ADS interconnects with external devices via the following set of connector
65. 001uF 2 KV 10 SMD AVX 1210B102K202NT SIze 1210 Ceramic C208 C209 Capacitor 0 1 X7R 500V 20 JOHANSON 501S43W104MV4E SMD Size 1812 Ceramic DIELECTRIC DI Zener Diode SMD Motorola 1SMCS5 0AT3 D2 D7 Diode Pair common cathode Motorola MBRD620CT D3 D4 05 Diode SMD Motorola LL4004G D6 Zener Diode 12V SMD Motorola 1SMCI2AT3 DS1 Dip Switch 8 X SPST SMD GRAYHILL 90HBW08S DS2 DS3 Dip Switch 4 X SPST SMD GRAYHILL 90HBW04S Fl Fuse 1A 250V Miniature 5 X 20mm Little Fuse 217001 Fast blow F2 Fuse 5A 250V Miniature 5 X 20mm Little Fuse 217005 Fast blow H1 H2 H3 H4 H5 Gnd Bridge Gold Plated PRECIDIP 999 11 112 10 J1 J3 J5 J7 Jumper Header 3 Pole with Fabricated Jumper J2 J6 Jumper 2 Pole Soldered Gold PRECIDIP 999 11 112 10 Plated 1112 13 L4 L5 L6 L7 Ferrite Bid Fair rite 2743021447 LD1 LD2 LD3 LD4 LD8 LD9 110 Led Green SMD SIEMENS 670 LD11 LD5 LD6 LD13 LD14 LD15 LD16 Led Yellow SMD SIEMENS LY 670 LD7 LD12 Led Red SMD SIEMENS LS 670 Pl Connector 8 pin RJ45 Receptacle MOLEX 43202 8110 Shielded 90 P2 Connector 2 pin Power Straight WB 81135 253303253 with false insertion protection Connector 2 pin Power Plug WB 8113B 253200253 PA3 PB3 Connector 2 X 9 pin Stacked EDA Inc 8LE 009 009 D 3 06H Female DType 90 P4 P16 Connector 128 pin Female DIN ERNI ERNI 043326 41612 909 P5 Connector header 16 pin Male T H
66. 1 General Information For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 1 4 Specifications The MPC8260ADS specifications are given in Table 1 1 MPC8260ADS Specifications below Table 1 1 MPC8260ADS Specifications CHARACTERISTICS SPECIFICATIONS Power requirements no other boards attached Microprocessor 5Vdc TBD Typ 3 5 A Max 12Vdc 1A Max MPC8260 running 66 MHz Bus Clock Frequency Addressing Total address range on PPC Bus Total address range on Local Bus Flash Memory SIMM PPC Bus Synchronous Dynamic RAM DIMM PPC Bus Synchronous DRAM On Local Bus Operating temperature 4 Giga Bytes 32 address lines 256 KBytes External 18 address lines 4 Giga Bytes Internal 32 address lines internal decoding 8 MByte 32 bits wide expandable to 32 MBytes 16 MByte 64 bits wide Support for up to 64 MByte 4 MBytes organized as 1 Meg X 32 bit 10 C 30 C room temperature Storage temperature 25 C to 85 C Relative humidity 5 to 90 non condensing Dimensions Length 11 023 280 mm Width 6 417 163 mm Thickness 0 063 1 6 mm 1 12 MPC8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 1 5 ADS Features 64 bit MPC8260 running 66MHz external bus frequency 16 MByte Unbuffered 16
67. 1 27 29 X 29 array gold plated contacts Socket for the above 480 pin E Tec BPW480 1270 29AD01 1 27mm PGA to BGA 29 X 29 array gold plated contacts screw lock 013 014 SDRAM 2 Banks 512KBytes X Fujitsu MB811171622A 100 16 Bit 100MHz 016 Clock Generator 66MHz 40 MHz M3H16FCD 3 3V Supply 4 pins 8 pin DIP form factor 5 98 8260 PowerQUICC ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 5 8 MPC8260ADS Bill Of Material Reference Designation Part Description Manufacturer Part 017 022 4 128 64 64 I O 128 Macrocell 7 5 nsec propagation delay System Programmable Logic Device 100 pin TQPF 16 MByte 168 pin 100MHz SDRAM DIMM organized as 2 X 1 M X 64 AMD Fujitsu M4 128 64 7VC SDC2UV6482D 100T S or PDC2UV6484 102 103 10 T S 168 pin 90 T H DIMM Socket with Plastic Latches 3 3V Unbuffered AMP 390040 6 U24 U29 U30 Low Voltage CMOS 5V Tolerant 16 bit buffer with OEs 48 pin Plastic TSSOP Case 1201 01 Motorola MC74LCX16244DT U25 8 MByte Flash SIMM 95 nsec delay Single bank composed of four LH28F016SCT L95 chips by SHARP Smart Modular Technology SHARP SM73228XG1JHBGO 80 pin SIMM Socket AMP 822032 5 U26 Low Voltage CMOS 5V Tolerant 16 bit Transceiver 48 pin Plastic TSSOP
68. 18 lt 0025 1013 18 lt 0025 1029 UE si CAS 000 B CAS 000 b 5 geal oke oke 5 35 35 Fe 913 114 9 LSDDQM2 A LSDDOM3 LO O 54 lt gt LSDWET _ 9 cem 5 LSDCAS s i CLK7 i 6 8 PROJECT MPC8260ADS REV PILOT SHEET 6 OF 18 8 ENG YAIR LIEBMAN BLOCK LOCAL BUS SDRAM CHK 3 DESCRIP A B 3 7 J tmp mnt net prince yair voyager ads pilot sch 7 drw__26 SEP 99 19 04 last update 26 SEP 99 12 08 duct 15 to o For More Information Th D F G J K GND V3 3 a _ ere ATMTXENT R285 pA31 TxEN COL PC31 CLK1 8RCo 201 PCST RN69 _AD3 pA30 TxC1Av CRS PC30 CLK2 Tx
69. 232 Serial Port Connectors and Debug Station Connection Schemes COP JTAG Port 2 20 211 210 000000000000000000020200 ADS ITAGCS YS CEM ins fone adu JTAG TAP Controller State Diagram ADS Power Illustrations For More Information On This Product Go to www freescale com vii Freescale Semiconductor Inc ILLUSTRATIONS Figure Page Number Title Number viii MPC8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TABLES Table Number 1 1 MPC8260ADS Specifications Table 2 1 a n ttr ua Table 2 2 DS2 SDRAM DIMM Configuration EEPROM Slave Address Table 3 1 SADS Memory Map Q ated oni Laud ouo dude Table 3 2 Power On Reset Configuration Table 3 3 SIU Register Programm cos eio e ys ee e MOT Eco ees Table 3 4 Memory Controller Initializations For 66Mhz Table 4 1 Hard Reset Configuration Wotd Table 4 2 ADS Chip Select A
70. 3 5487 8488 ASIA PACIFC Motorola Semiconductors H K Ltd 8B Tai Ping Industrial Park 51 Ting Kok Road Tai Po N T Hong Kong Tel 852 26629298 Mfax RMFAXOG email sps mot com TOUCHTONE 1 602 244 6609 US amp Canada ONLY 800 774 1848 World Wide Web Address http sps motorola com mfax INTERNET http motorola com sps Technical Information Motorola Inc SPS Customer Support Center 1 800 521 6274 electronic mail address crc wmkmail sps mot com Document Comments FAX 512 895 2638 Attn RISC Applications Engineering World Wide Web Addresses http www mot com PowerPC http Avww mot com netcomm Motorola Inc 1999 All rights reserved For More Information On This Product Go to www freescale com Paragraph Number 1 1 1 2 1 3 1 4 1 5 1 6 1 6 1 1 6 2 1 6 3 1 6 4 1 6 5 1 6 6 2 1 2 2 2 3 2 3 1 2 3 2 2 3 3 2 3 4 232 2 3 6 2 3 7 2 4 2 4 1 2 4 2 2 4 3 2 4 4 2 4 5 2 4 6 2 4 7 2 4 8 2 4 8 1 2 4 8 2 3 1 MOTOROLA Freescale Semiconductor Inc CONTENTS 5 Title Number Chapter 1 General Information Introduction 11 JZADDreviatio EISE u EU ER ee ua 11 Related DGC UATE E S G a ae 11 PCC TIC ACL ONS m au a Ora 12 ATS Heatlte u u m 13 Revision Engineering ENG to Revision PILOT Changes 14 BCSR
71. 4W AVX CR32 102F T DRALORIK D25001KFCS R126 Resistor 2 2 MQ 1 SMD 1206 1 RODERSTEIN D2502M2FCS 4W R127 Resistor 1 5 Q 1 SMD 1206 1 RODERSTEIN 025 O1 R5FCS 4W R130 R143 R144 Resistor 133 Q 195 SMD 1206 1 DRALORIK D25 133RFCS 4W R137 R145 R146 R150 R160 Resistor 2 7 Q 1 SMD 1206 1 RODERSTEIN D25 2R74FCS 4W R138 Resistor 100 9 1 SMD 1206 1 RODERSTEIN D25 100RFCS 4W R147 Resistor 63 4 62 1 SMD 1206 1 DRALORIK D25 63RAFCS 4W R158 R161 Resistor 270 1 SMD 1206 1 DRALORIK D25 270RFCS 4W RN2 RN6 RN8 RN9 RNI10 Resistor Network 10 5 8 ROHM RS8A 1002 J RN12 RN21 RN22 resistors 10 Common Bus RN28 RN30 RN31 RN32 RN33 RN34 RN35 RN40 RN41 RN42 RN43 RN44 RN51 RN52 RN53 RN56 RN57 RN67 RN68 RN74 RN88 RN3 RN4 5 RN7 RN20 RN27 Resistor Network 43 5 4 DALE CRAO6S 08 03 430JRT RN80 RN81 RN82 RN83 RN84 resistors 8 pin RN85 RN86 RN87 RN14 RN16 RN17 RN19 RN24 Resistor Network 22 0 5 4 DALE CRA06S0803220JR RN29 RN36 RN37 RN38 RN39 resistors 8 pin RN45 RN46 RN47 RN48 RN49 RN50 54 55 RN58 59 RN60 RN61 RN62 RN63 RN64 RN65 RN66 RN69 RN70 RN71 RN72 RN73 RN75 RN76 77 RN78 RN79 15 RN18 RN23 DALE CRA06S0803 000 RT Resistor Network 0 4 resistors 8 pin MOTOROLA Chapter 5 Support Information For More Information On This Product Go to www freescale com 5 97 Freescale Semic
72. 7 A2 R24 051 R21 GND 8 PROJECT 8260 05 REV PILOT SHEET 3 OF 18 8 YAIR LIEBMAN BLOCK EXP CONN CLOCKs amp PON RESET CONF NOT ASSEMBLED CHK DESCRIP 9 2359814 tmp mnt net prince yair voyager ads pilot sc h 4 drw 26 SEP 99 19 03 last update 21 SEP 99 18 43 A B 2 0 F G H J K C 800 74LCX 16244 BA 7 8 BA 27 29 800 2 2 0147 TSTATO TSTAT O 7 B0 01146 J21 802 5 44 TSTAT2 2 02 11 1 094 28_RSTCNE e 02 43 STATS 2 1 025 29 SRESET 2 BCSRCS _ 36 1 026 30 TOOLCS1 J17 61 31 13 CLK2 1 027 J18 gt 64 3 027 32 SCLAMPO 804 04 14141
73. ADS User s Manual For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Table 4 1 Hard Reset Configuration Word Prog Offset In Field B si Value Implication Flash me us BiS 12 8 9 7102 CI BADDR29 IRQ2 selected as BADDR29 8 B2 WT BADDR30 IRQ3 selected as BADDR30 L2_HIT IRQ4 unassigned CPU_BG BADDR31 IRQ5 selected as BADDR31 DPPC 10 11 11 Data Parity Pin Configuration set as EXT BR2 as EXT BG2 DP2 as EXT DBG2 as EXT BR3 DP4 as EXT BG3 as EXT DP6 is IRQ6 DP7 as IRQ7 Reserved should be cleared IMMR initial value 0 0 000000 1 the internal space resides initially at this address Boot memory Flash at 0 000000 ABB IRQ2 pin is set to ABB DBB IRQ3 pin is set to DBB Mask Masters Request No masking of Bus Request lines Local Bus pins configured as Local bus pins MODCK1 AP 1 TC 0 set as BKSELO MODCK2 AP 2 TC 1 set as BKSELI MODCK3 AP 3 TC 2 set as BKSEL2 IRQ7 APE set as IRQ7 CS11 AP 0 set as CS11 CSIOPC CS10 BCTL1 DBG_DIS set as CS10 Reserved Should be cleared MODCK HP This fields sets the MODCKH 0 3 field which is the 4 MSB for the 7 bit MODCK field It is programmed into Flash and may be taken from there when DS1 1 is at ON position or it is set by DS1 2 5 when DS1 1 is at OFF position
74. C21 EXPD7 C22 EXPD8 C23 EXPD9 C24 EXPDIO C25 EXPDII C26 EXPDI2 C27 EXPDI3 C28 EXPD14 C29 EXPDI5 C30 N C Not Connected C31 C32 DI GND O Digital Ground Connected to main GND plane of the ADS D2 D3 D4 Expansion Write Enable 0 1 L This are buffered GPCM Write Enable lines 0 1 They are meant to qualify writes to GPCM controlled 05 EXPWEI 8 16 data bus width memory devices This to provide eased access to various communication transceivers EXPWEO controls EXPD 0 7 while EXPWE1 controls EXPD 8 15 These lines may also function as UPM controlled Byte Select Lines which allow control over almost any type of memory device D6 GND Digital Ground Connected to main GND plane of the ADS 5 92 MPC8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 5 7 P16 System Expansion Interconnect Signals Pin No Signal Name Attribute Description D7 EXPGLO D8 EXPGLI D9 EXPGL2 D10 D11 EXPGL3 EXPGL4 D12 EXPGL5 Expansion General Purpose Lines 0 5 L These are buffered GPL 0 5 lines which assist UPM control over memory device if necessary These are output only signals and therefore do not support H W controlled UPM waits D13 GND Digital Ground Connected to main GND plane of the ADS D14 EXPALE Expa
75. COG AVX 12065A152JAT00J SMD 1206 Ceramic C148 C150 C156 22pF 50V 5 1206 5A 220J AT SMD 1206 Ceramic C152 Capacitor luF 20V 10 SMD SIze SIEMENS B45196H5105K109 B Tantalum C170 C175 10 50V 10 SMD 1206 5A 100J AT 1206 Ceramic MOTOROLA Chapter 5 Support Information 5 101 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 5 9 MPC8260ADSL2C Bill Of Material Reference Designation Part Description Manufacturer Part C207 Capacitor 0 001 2 10 SMD AVX 1210B102K202NT SIze 1210 Ceramic C208 C209 Capacitor 0 1 X7R 500V 20 JOHANSON 501S43W104MV4E SMD SIze 1812 Ceramic DIELECTRIC DI Zener Diode SMD Motorola 1SMCS5 0AT3 D2 D7 Diode Pair common cathode Motorola MBRD620CT D3 D4 05 Diode SMD Motorola LL4004G D6 Zener Diode 12V SMD Motorola 1SMCI2AT3 DS1 Dip Switch 8 X SPST SMD GRAYHILL 90 085 582 053 Dip Switch 4 SPST SMD GRAYHILL 90 045 Fl Fuse 1A 250V Miniature 5 X 20mm Little Fuse 217001 Fast blow F2 Fuse 5A 250V Miniature 5 X 20mm Little Fuse 217005 Fast blow H1 H2 H3 H4 H5 Gnd Bridge Gold Plated PRECIDIP 999 11 112 10 J1 J3 J5 J7 Jumper Header 3 Pole with Fabricated Jumper J2 J6 Jumper 2 Pole Soldered Gold PRECIDIP 999 11 112 10 Plat
76. D4 3 RSTO 1 020 1 052 8021 9 20 BREVI BLACK RSTO 20 24 053 18804 8022 1 05 40 1 53051 RSTI ATMCSOY 21 022 23 12106 06047 ATMCSIN 22 72 807 07 07 1 023 1 055 48 i Q M4_128_64 __VC 1 18 801 8024 13 36 SWOPT2 79 MODCKH2 1 057 8025 14 35 F_PD7 80 802 Q9 09 1 058 8026 16 6 81 010 010 55 UISG FAC SET 1 2 8027 17 244 011 32 F P05 uL 1 060 gt 25 83 32 1 3 0 3 1 06 1 23 12 4 199 95 6 Pai 1 062 8028 191012 012130 04 y 17063 8029 2015 01520 N Se eb ba i mar m 1 i a 015 0615541 mue D a 3 4 017 AGAR 4 083 6 ALS i 029 5 9 2 vec BCSR2 2 1Q GND 7 eu 9 END 7 ISPTDI ISPTDO1 RIG ISPTDO ISPTDOS 22 RIS __5 5 876 1 ISPTCK REA i i i QC o MODCKH 0 5 MOTOROLA INC t t 5 01435 C133 6 6124 8 2 E PROJECT MPC8260ADS REV PILOT SHEET 4 OF 18 8 GND ENG YAIR LIEBMAN BLOCK Board Control amp Status Register BCSR V CHK DESCRIP B 3 7 J K tmp mnt net prince yair voyager ads pilot sc h 5 drw 26 SEP 99 19 04 last update 21 SEP 99 18 43
77. Data lines plus useful GPCM and control lines The pinout of P16 is shown in Table 5 7 P16 System Expansion 5 88 MPC8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Interconnect Signals below Table 5 7 P16 System Expansion Interconnect Signals Pin No Signal Name Attribute Description Al EXPA16 Expansion Address 16 31 This is a Latched Buffered version of the MPC8260 s PPC Address lines 16 31 provided for external tool A2 EXPAI7 connection To avoid reflection these lines are series terminated with 43 18 Q resistors A4 19 5 20 6 21 7 22 8 23 9 24 10 25 26 12 27 13 28 14 29 15 16 17 1 This signal is provided to allow Flash programming while the ADS resides in a Card Cage during manufacturing process These lines may 18 be connected to 12V 1A power supply provided that 2 is disconnected 19 Not Connected A20 V3 3 3 3V Power These lines are connected to the main 3 3V plane of the MPC8260ADS this to provide 3 3V power where necessary for 21 external tool connected The amount of current allowed to be d
78. GRAY FETHRXD 0 3 FETHRXD3 1458 27 S FETHRXD2 RNB2 7 48 RXD2 TPOP FETHRXD1 343 6 RW 4915901 Rag agers FETHRXD RNB2 4435 58 RNBQ 20 4 gat FETHRXDV 1338 Bllay py 9 N c207 FETHRXER 3456 RN83 554 5 FETHRXCK RN83 43 54 FIBON 18 7 5 ST 1 EE THO 122 864 coL 2k 2 ge P FETHCRS 1 285 5 CRS RS Lu EN chasis gnd FETHIEN 3 LED YELLOW 530 1206 TRSTE LEDSPD KI 15 LEDRX 42 ALBO GREENR LD4 LD6 2469 330 1206 FETHMDC R142 45 LEDTX 41 LDS NLED GREEN W 330 1206 R156 FETHMDIO 44 LEDLINK 40 LED YELLOW R155 330 1206 IRO7 Shared with 9 1206 SE EE LoS EDRED 330 1206 R162 6 7 1 pF MA505 25MHz V3 3 107 25 vccio 95 vec Fm 4 n R 10 0 01UF Cm amp 10pF BH 12 si ADI 52 1215 vee 6 5812004 GND 8 iA MF2 MFO E ncc 2 R T _ 7 45 512 S R 6 MF2 Seige 5 R116 5 0 01UF 6115 an i R s 22 S1 FETHCFG1 33 cec vccA 24 FETHFDE 13 FDE X R114 E FETHRST 16 CNDA 26 4 34 pwRDwN vccn 27 32 neo 8 01UF 35 GND 36 517 4 61 4 7
79. JTAG SYSTEM on page 70 Figure 4 8 ADS JTAG SYSTEM 4 MPC8260 TMS TRST A 27 29 R W DVAL Toe RUE OR ROUX o xw oo BCSRx Reg BCSR BUS File cont L Download Cont Status Reg N 84 Data Shift Reg Download Data Bu TDI Bd Bypass A gt t Inst Shift Reg t 1 gt Inst Reg gt lt Decode amp Cont Power On Pig Reset Logic TMS TAP Cont N TRST gt m mm a BCSR_ CONT can be seen in the figure above the JTAG machine includes the following components 1 Controller 2 Instruction Shift register 3 Instruction register 4 Data Shift register Download Data register 4 70 MPC8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 5 Download Command and Status register 6 Bypass register 4 13 1 1 JTAG TAP Controller The TAP Test Access Port controller is a standard 16 state JTAG TAP controller Its transitions are deter mined by the state of TMS upon rising edge of TCK T
80. MOTOROLA Chapter 3 Operating Instructions 3 37 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc is based on 66 MHZ timing calculation Table 3 4 Memory Controller Initializations For 66Mhz Reg Device Type Bus Init Value hex Description BRO SM73228XG1JHBGO PPC FF801801 Base at OFF80000 32 bit port size no parity GPCM Smart Modular Tech SM73248XG2JHBGO by FF001801 Base at OFF00000 32 bit port size no parity GPCM Smart Modular Tech SM73288XG4JHBGO 01801 Base at OFE00000 32 bit port size no parity Smart Modular Tech ORO SM73228XG1JHBGO FF800836 8MByte block size CS early negate 6 w s Timing Smart Modular Tech relax 5 73248 27 0 by FF000836 16MByte block size CS early negate 6 w s Timing Smart Modular Tech relax M73288XG4JHBGO FE000836 32MByte block size CS early negate 6 w s Timing relax BRI BCSR PPC 04501801 Base at 04500000 32 bit port size no parity GPCM ORI FFFF8010 32 KByte block size all types access 1 w s BR2 SDRAM DIMM 00000041 Base at 0 64 bit port size no parity Sdram machine 1 Supported OR2 SDC2UV6482C 84 by PPC FF000C80 16MByte block size 2 banks per device row starts at Fujitsu A9 11 row lines internal bank interleaving allowed normal AACK operation SDC8UV6484C 84 by 002 0 64 bloc
81. MPC8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 3 4 Memory Controller Initializations For 66Mhz Reg Device Type Bus Init Value hex Description LSRT 811171622 84 Local 21 Divide MPTPR output by 34 LSRT 1 Generates refresh every 13 4 usec while 16 usec required Therefore is refresh redundancy of 5 4 msec throughout full SDRAM refresh cycle which completes in 27 4 msec I e Application s w may withhold the bus upto app 5 4 msec in a 32 8 msec period without jeopardizing the contents of the local bus SDRAM MPTPR All SDRAMs on board 1900 Divide Bus clock by 26 MPTPR 1 decimal Although this BSMA value corresponds to A 17 19 BKSEL 0 2 when PBI is set only the relevant BKSEL lines according to number of internal SDARM banks are VALID in this case BKSEL2 2 Although this BSMA value corresponds to A 15 17 BKSEL 0 2 when PBI is set only the relevant BKSEL lines according to number of internal SDARM banks are VALID in this case BKSEL 1 2 3BNKSEL 0 2 are not connected for the Local Bus SDRAM Use is done with Local bus address lines MOTOROLA Chapter 3 Operating Instructions 3 41 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 4 Functional Description In this chapter the various ADS s modules
82. Manual 5 1 7 Mach s In System Programming ISP This is a 10 pin generic 0 100 pitch header connector providing In System Programming capability for Vantis made programmable logic on board The pinout of P11 is shown in Table 5 6 P11 ISP Connector Interconnect Signals below Table 5 6 P11 ISP Connector Interconnect Signals Pin No Signal Name Attribute Description 1 ISPTCK I ISP Test port Clock This clock shifts in out data to from the programmable logic JTAG chain 2 N C Not Connected 3 ISPTMS I ISP Test Mode Select This signal qualified with ISPTCK changes the state of the prog logic JTAG machine 4 GND Digital GND Main GND plane 5 ISPTDI I ISP Transmit Data In This is the prog logic s JTAG serial data input sampled by the MPC8260 on the rising edge of TCK 6 VCC O 5V power supply bus 7 ISPTDO O ISP Transmit Data Output This the prog logic s JTAG serial data output driven by Falling edge of TCK 8 GND Digital GND Main GND plane 9 N C Not Connected 10 Not Connected 5 1 8 MPC8260ADS s P16 System Expansion Connector P16 is a 128 pin 90 DIN 41612 connector which provide a minimal system I F required to interface various types of communication transceivers data path of which passes through MPC8260 s serial ports via P4 This connector contains 16 bit lower PPC bus address lines 16 bit higher PPC bus
83. RS232 Pott ZON qana SE UR wats 34 3 3 Memory Maps Sm su ua pakara 34 3 4 MPC8260 Register Programming Ie a ERE UR 36 3 4 1 System Initialization o EN ites Menlo x es ERE 37 3 4 2 Memory Controller Register Programming 37 Chapter 4 Functional Description 4 1 Reset amp Reset Configuratio 42 4 1 1 Powerctr ELI E a aan 42 4 1 1 1 Power On Reset Configuration 42 4 1 2 Tardi Reset 43 iv MPC8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Paragraph Number 4 1 2 1 4 1 2 2 4 1 2 3 4 1 2 4 4 1 3 4 1 3 1 4 1 3 2 4 1 3 3 4 2 4 2 1 4 2 2 4 2 3 4 3 4 4 4 4 1 4 4 2 4 5 4 6 4 7 4 7 1 4 71 2 4 7 3 4 7 4 4 8 4 8 1 4 8 2 4 8 3 4 8 4 4 9 4 91 492 410 4 10 1 4 11 4 11 1 4 11 2 4 11 2 1 4 11 3 4 11 3 1 4 12 4 12 1 4 12 2 4 12 3 MOTOROLA Freescale Semiconductor Inc CONTENTS Page Title Number COPATAG Port Hard 43 Mangal Hard Reset a sassa 43 Internal Sources Hard Reset 43 Hard R st Configuration
84. Register The JTAG Instruction register holds the current JTAG instruction which determines the JTAG logic oper ation at any given time The instructions are loaded into it from JISR when the TAP enters the Update IR state The valid instructions and their associated functions are shown in Table 4 21 JTAG Instruction Codes below Table 4 21 JTAG Instruction Codes Mnemonic Code Bin Function EXTEST 000 Execute Test JTAG public instruction No function with this application since there is no built in test within this JTAG entity Defaults to Bypass DOWNLOAD 0017 Download When holds this instruction and the TAP controller is Shift DR mode the input of the Download Shift register is connected to TDI of the ADS while the of this machine reflects status of JTAG FULL flag in the Download Control and Status register Data may be shifted in to be read by the download agent running on board When the TAP controller moves into EXIT1 DR state the Receive Full flag is set in the Download Control amp Status register so that the download agent may learn about the presence of valid data in the JDSR UPLOAD 010 Up Load Not supported with current revision defaults to Bypass SAMPLE 011 Sample Preload public instruction Not implemented since there PRELOAD external pins to this JTAG entity Defaults to Bypass Reserved 41007 101 Reserved un
85. S Tw S i 02 5 A WORD Al CN CN LO 00 LO 0 LO LO LO CO o 0 9 BSDRMA11 is 2 1 A ALEQUT 7 7 ERU cr 0 non muxed 1 muxed 5 i cLko ALEOUT 9 5 BALE 29 eu CLK2 29 d eu 24 44 1 00 1 016 20 BSORMA4 A10 44 1 00 1 016 20 joo I Y 6 A25 45 7017 21 BSDRMAS A11 45 04 9e 26 5611 02 1 018 22 20 46 1 02 1 018 22 198 27 47 23 BSDRMA7 47 23 BSDRMA11 ET 1 03 1 019 0116524 1 03 1 019 3 red EN M x m 528 4811704 1 020 124 ibe J250 3 J1150 881 1 04 1 020 24 BSORMAS d CE E DE G EN 33 11 1 25 Pal SDMUX 1 25 5 c83 5 cal xX 19 X X x 19 X 1 05 1 021 1 05 1 021 J103 Dw 5 rj 56 Do T3 12 21 06 1 022126 DIMMSIZE 2 og 17922128 J104 s s 8 2812142812972817281287297298752 311 07 1 023 27 311 07 1 023 27 J107 14 9 024135 SOMUX i BSDRMA8 _ 91 524188721 ae ies m ie gt 7 AT 1217018 1 026 8 J108 1217010 1 026 5 lt 1113 HIGH MUX SPARE LOW MUX CACHE 7 1 011 1 027 J41055
86. This Product Go to www freescale com Freescale Semiconductor Inc ColAddPBI 16M LA7 LA9 LA20 not really required ColAddPBI 64M LA6 LA8 LA20 SdramAdd SdramA11 SdramA9 SdramA8 C B 1 COL ROW SIZE_16M 0 SIZE_64M 1 SDRAM 16M DimmSize SIZE_16M SDRAM 64M SDRAM_16M SDRAM NORMAL PBI 0 SDRAM PBI SDRAM NORMAL MuxCont PBI DimmSize Equations state diagrams Input Latch equations LAdd le LAdd d Add latching the address Output equations SdramAdd oe 17 always enabled when ROW amp SDRAM NORMAL then SdramAdd RowAddNormal q else when ROW amp SDRAM PBI MODE amp SDRAM_16M then SdramAdd RowAddPBI 16M q else when ROW amp SDRAM PBI MODE amp SDRAM 64M then SdramAdd RowAddPBI 64M q else when COL amp SDRAM NORMAL then MOTOROLA Chapter 5 Support Information 5 145 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SdramAdd ColAddNormal q
87. activity these figures may be larger The figures in the table refer to the actual write access The write operation continues internally and the device has to be polled for completion 4 8 Flash Protection Logic The Flash SIMM provided with the ADS is divided into 32 blocks of 256K Bytes Each block has an indi vidual Lock Bit associated with it allowing individual block erase write protection The Block Lock bits are protected by a Master Lock Bit creating a second level of protection A block lock bit may be set individually but may be cleared only as a group 1 clearing ALL block lock bits Once a block lock bit is set erasure write of that block is possible only when VPP to the Flash SIMM is 12V When the Master Lock bit is set setting clearing of Block Lock bits is possible only when VPP to the Flash SIMM is 12V otherwise VPP of 5V is sufficient A Master Lock bit set operation requires VPP of 12V Once the Master Lock Bit is Set it may not be cleared 4 8 2 Flash Programming Voltage Support is given to 5V programmable modules as well as 12V programmable modules programming voltage to which is applied either internally 5V or externally via the 12V power input of the ADS P2 which may be left unconnected in case a 5V programmable module is being used or in case there is no need Le initializations that follow the hard reset sequence at system boot 21 J7 is set between 2 3 12V supply i
88. devices It is required to do so anyway since the L2Cache must operate within a full 64 bit data bus environment MOTOROLA Chapter 4 Functional Description For More Information On This Product Go to www freescale com 4 55 Freescale Semiconductor Inc Table 4 6 Local Bus SDRAM Performance Figures 66MHz Bus Clock Cycle Type MHz Bus Clock Freq Burst Read Page Hit 411441 Burst Write Page Miss 41111 Burst Write Page Hit 21111 Refresh 82 From TS Asserted First access may be longer due to internal pipeline delay including arbitration overhead Figure 4 4 Local SDRAM Connection Scheme CS4 65 CS LSDRAS RAS RAS LSDWE PAIS All All LSDA10 10 10 LA 20 21 A 9 8 8 LA 22 29 A 7 0 7 0 CERT CLK CLK LSDDQMO LSDDQMI DQ 15 0 DQ 15 0 LCL D 0 15 LSDDOM2 LSDDQM3 LD 16 31 4 9 Local Bus SDRAM Programming After power up the local bus SDRAM needs to be initialized by means of programming to establish its mode of operation The Local bus Sdram 15 programmed according to the following procedure 1 Issue Precharge All command 2 Issue 8 CBR refresh commands 4 56 MPC8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com 3 Freescale Semiconductor
89. enabled and ATMTFCLK is rising an octet of data ATMTXD 7 0 is written into the transmit FIFO of the PM5350 When the ATM port is disabled this line may be used for any available function of PA31 B2 ATMTCA PA30 T S ATM Transmit Cell Available H When this signal is asserted High while the ATM port is enabled it indicates that the transmit FIFO of the 5350 is empty and ready to except a new cell When negated it may show either that the transmit FIFO is Full or close to Full depending on 5350 internal programming When the ATM port is disabled this line may be used for any available function of PA30 B3 ATMTSOC PA29 T S ATM Transmit Start Of Cell H When this signal is asserted High by the MPC8260 while the ATM port is enabled it indicates to the 5350 the start of a new ATM cell over ATMTXD 7 0 i e 1 st octet is present there When the ATM port is disabled this line may be used for any available function of PA29 B4 ATMRXEN PA28 5 ATM Receive Enable L When this signal is asserted Low while the port is enabled and ATMRECLK goes high on octet of data is available at the PM5350 s ATMRXD 7 0 lines When negated while ATMRFCLK goes high data on ATMRXD 7 0 is invalid however driven When the ATM port is disabled this line may be used for any available function for PA28 MOTOROLA Chapter 5 Support Information 5 81 For More Information On This Produ
90. fb Trst_B IPORIn B JtagResetState fb TDO Selection equations Tdo clk Tck Tdo ar 0 Tdo ap JtagStateReset fb when STATE_JTAG_SHIFT_IR then Tdo JtagShiftIR2 fb else when STATE JTAG SHIFT DR amp INST IS BYPASS then Tdo JtagShiftDRO fb else when STATE JTAG SHIFT DR amp INST IS DOWNLOAD then Tdo JtagReceiveFull fb MOTOROLA Chapter 5 Support Information 5 137 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc when STATE_JTAG_ENABLED then TdoOut Tdo fb else when ISTATE JTAG ENABLED then TdoOut Tdi TdoEnable STATE JTAG ENABLED amp JtagTdoEnable fb ISTATE JTAG ENABLED TdoOut oe TdoEnable fb 5 KR ER R R OR Power Reset Generation equations PonResetOut oe 1 PonResetOut INST IS PON RESET Auxiliary functions equations KeepPinsConnected amp BCTL1 KeepPinsConnected fb END 5 138 MPC8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 5 3 2 018 SDRAM
91. input of the MPC8260 This allows compatibility with existing de bug tools which do not support the use of this machine and might suffer from added delay on TDI Asynchronous Bypass After Power On Reset when J5 is set between positions 1 2 factory set this machine defaults to asynchronous connection between TDI input of this machine and the MPC8260 s TDI with 7 5 nsec delay This allows compatibility with existing debug tools which have not been modified yet to support this machine and can tolerate this delay on the TDI line JTAG Bypass After Power On reset or JTAG reset when this JTAG machine 15 enabled via BCSR6 and J5 is set between positions 1 2 factory set it will be found in Bypass mode i e the default instruction ofthe machine is BYPASS so that when the TAP controller is moved into Shift DR state a single stage shift register is placed between the TDI input of the ADS and the TDI input of the MPC8260 4 13 1 8 Fast Download Operation This section describes the procedure needed to be taken by a debug station programmer so that this machine may be utilized It is assumed here that J5 remains factory set 1 2 and the ADS is after Power On reset and initialized The procedure is as follows Enable this JTAG machine by writing 1 to JTAG EN bit in BCSR6 The machine is now enabled and in JTAG Bypass mode See Table 4 19 BCSR6 Description on page 68 Remember that prior to this operation the length o
92. is connected to the ADS by a COP controller provided by a third party Figure 2 7 Host Controlled Operation Scheme Host Computer VIL Media2COP 16 Wire Flat Cable 5V Power Supply 2 4 2 Stand Alone Operation In this mode the ADS is not controlled by the host via the COP port It may connect to host via one of its other ports e g RS232 port Fast Ethernet port ATM155 port etc Operating in this mode requires an ap plication program to be programmed into the board s Flash memory Figure 2 8 Stand Alone Configuration Host Computer RS232 J mms dE UN Li gg 5V Power Supply Tesque JL 2 24 8260 PowerQUICC ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 4 3 5V Power Supply Connection The MPC8260ADS requires 5 Vdc 5 max power supply for operation Connect the 5V power supply to connector P19 as shown below Figure 2 9 P19 5V Power Connector GND 2 SV wui GND P19 is a 3 terminal block power connector with power plug The p
93. line When the Ethernet port is disabled this line may be used for any available function of PB31 C2 FETHRXDV PB30 T S Fast Ethernet Receive Data Valid H When this signal is asserted High while the Fast Ethernet port is enabled and FETHRXCK goes high it indicates that data is valid on the MII Receive Data lines FETHRXD 3 0 When the Fast Ethernet port is disabled this line is tristated and may be used for any available function go PB30 C3 FETHTXEN PB29 T O T S Fast Ethernet Transmit Enable H The MPC8260 will assert High this line to indicate data valid on the FETHTXD 3 0 lines When the Fast Ethernet port is disabled this line may be used for any available function of PB29 C4 FETHRXER PB28 T S Fast Ethernet Receive Error H When this signal is asserted High by the LXT970 while the Ethernet port is enabled and FETHRXCK goes high it indicates that the port is receiving invalid data symbols from the network When the Ethernet port is disabled this line is tristated and may be used for any available function of PB28 C5 FETHCOL PB27 T S Fast Ethernet Port Collision Detected H When this signal is asserted High by the LXT970 while the ethernet port is enabled it indicates a Collision state over the line When the LXT970 is in Full Duplex mode this line is inactive When the Ethernet port is disabled this line is tristated and may be used for any available function of the P
94. linear voltage regulator made by Micrel the MIC29501 3 3BU which is capable of driving upto 5A facilitating operation of external logic as well With this revision of the ADS a production option is made so that the level on this bus may be varied by means of trimming potentiometer TR2 However this also requires the following changes 1 UII to be changed to MIC29752BWT which is a 7 5A 5 pin variable regulator 2 Soldering in R74 5 1206 R89 3KW 1206 amp TR2 BOURNS 3362P 1 102 Table 5 8 MPC8260ADS Bill Of Material on page 94 WARNING The values for the above components are calculated to al low 3 0V 3 6V range over the 3 3V bus A change in the above values might extend the voltage over this bus to undesired levels presence of which might inflict PER MANENT DAMAGE to the ADS 4 14 3 VDDL Bus The MPC8260 s internal logic and the PLL are powered with lower voltage power source voltage of which may be in 3 ranges of levels 23 2 1 7V 1 9V 1 8V 2 0V Selection between the above range levels is done via J1 which selects between different resistor values within the VDDL s variable regulator 010 feedback network while the fine tuning with a range is done by means of a trimming potentiometer For the different settings of J1 and their corresponding voltage level ranges see 2 3 1 Setting VDDL Level Range on page 19 and 2 3 2 Setting VDDL Supply Voltage Level
95. or transmit event respectively The ATM SAR is connected to the physical medium by an optical I F This is implemented with HP s HFBR 5205 optical I F which operates at 1300 nm with upto 2 Km transmission range 4 11 2 10 100 Base T Port fast Ethernet port with 100 Base TX I F is provided on the ADS This port also supports 10 Mbps ethernet 10 Base T via the same transceiver the LXT970 by Level One The LXT970 is connected to FCC2 of the MPC8260 via MII interface which is used for both the device s control and data path The initial configuration of the LXT970 is done by setting desired values at 8 config uration signals FDE CFG 0 1 and MF 0 4 The MF 0 4 pins however are controlled by four voltage levels this to allow each pin to configure two functions On the ADS these pins are driven by factory set zero ohm resistors connected to a voltage divider allowing for a future option change during production The LXT970 is initially disabled according to the state of FETHIEN in BCSRI See Table 4 10 BCSRI Description on page 64 The LXT970 reset input is driven by HRESET signal of the MPC8260 resetting the transceiver whenever hard reset sequence is taken The LXT970 may also be reset by either asserting the FETH_RST bit in see Table 4 10 BCSRI Description on page 64 or by asserting bit 0 15 MSB of LXT970 control register via the MII I F To allow external use of FCC2 its pins appear at the
96. pins should be connected to GND for normal operation J3 is factory set with a jumper on its 2 3 positions so that THERMI is connected to GND Figure 3 2 J3 Therm Connector 3 30 MPC8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 3 2 11 Optional Ventilator Supply An optional cooling ventilator for the MPC8260 may be powered via J4 a 2 pin header connector not as sembled In order to connect a ventilator to J4 either a 0 1 pitch header should be soldered to it to be con nected to a matching female connector or the ventilator supply wires may be soldered directly to J4 shown in Figure 3 3 JA Ventilator Supply below Warnin The job of soldering wires or header to J4 is very delicate and should be done by a skilled technician If this process is done by unskilled hands or repeated more than 3 times permanent damage may occur to the MPC8260ADS Figure 3 3 14 Ventilator Supply 57 GND J4 3 2 12 15 COP JTAG TDI Source Selection J5 sets the structure of the COP JTAG chain on the ADS For further information over its function see 2 3 6 MPC8260 JTAG s TDI Source Selection JS on page 22 3 2 13 J6 IDDH Measurement J6 resides in IDDH s main current flow To measure IDDH J6 should be removed using a solder tool and a current meter should be connected with as wires as short and thick as possible
97. s Manual for complete description of the MPC8260 s internal memory map Set by Hard Reset configuration 3 4 MPC8260 Register Programming The 8260 provides the following functions on the MPC8260ADS 1 System functions which include Bus SDRAM Controller e Local Bus SDRAM Controller Chip Select generator 2 Communication functions which include SAR Fast Ethernet controller e UART for terminal or host computer connection The internal registers of the MPC8260 must be programmed after Hard reset as described in the following paragraphs The addresses and programming values are in Hexadecimal base For more information on the following initializations see the MPC8260 User s Manual 3 36 8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 3 4 1 System Initialization Table 3 2 Power On Reset Configuration Flash Address Init Value hex Description hex 0 0 ac Internal arbitration Internal memory controller Core enabled Single MPC8260 60X Bus mode 32 Bit boot port size Exceptions vectored to OxFFF00000 Internal space 64 bit slave for external master 8 B2 L2 cache signals configured as BADDRx lines DP 1 7 configured as L2 cache I F and IRQ 6 7 Initial Internal space 0 0 000000 10 02 Boot memory space OxFE000000 OXFFFFFFFF ABB IRQ2 pin is ABB
98. setting is done within the MPC8260 it is the system programmer responsibility to set the correct value for this signal BCSR to ensure proper operation make room for the above SdramA 9 8 are moved to another device along with A20 output of this mux is now qualified with the and PBI information to provide the correct address lines to the sdram dimm Ces se K K K oe oe oe oe oe oe oe oe oe n this file 5 Rev PILOT 03 21 99 Pinout changed to M4 64 32 7V 48 package Pins declaration Control pins 5 RCB 1 DimmSize PIN 2 PBI 3 Address Input lines 37 Chapter 5 Support Information For More Information On This Product Go to www freescale com 5 143 Freescale Semiconductor Inc
99. the Hard Reset configuration word is taken from BCSR when it is ON the Hard Reset configuration word is taken from the Flash SIMM Warning With revision 0 of the MPC8260 on the PILOT revision of the ADS DS1 1 MUST be set to OFF position for proper operation of the ADS 2 3 5 Setting MODCKH 0 3 for PLLs Multiplication Factors When the Hard Reset configuration word is taken from BCSR i e 51 1 is OFF 051 2 5 become influential and set the upper 4 bits ofthe MODCK field during Hard Reset Configuration word acquisition When an individual switch of DS1 2 5 is at the OFF position its corresponding MODCKH line is pulled high 1 during Hard Reset while when at the ON position pulled down 0 DS1 2 5 have no effect when DS1 1 is ON because the upper 4 bits of the MODCK field are read from the Flash memory See 4 1 1 Power On Reset on page 42 2 3 6 8260 JTAG s TDI Source Selection J5 On revision PILOT of this board a new machine was inserted in front of the MPC8260 s port this to provide fast download capability for the ADS Since there are available debug tools designed for the previous ENG revision of the ADS compatibility issues might arise Via J5 it is possible to bypass the new JTAG machine and be perfectly compatible with the ENG revision of the ADS When a jumper is placed between positions 1 2 of J5 then the Fast download JTAG machine may be e
100. the expansion connectors The state of LD13 is controlled by BCSRI This is a soft indication 1 since the LXT970 may be controlled via the MII port it is possible that the state of LD13 does not reflect correctly the status of the LXT970 Note Application S W should always seek to match the state of LD13 to the status of the LXT970 so that this indication is made reliable as to the correct status of the LXT970 3 2 29 ATM ON LD14 When the yellow ATM ON led is lit it indicates that the ATM UNI transceiver the PM5350 is enabled for communication When it is dark the ATM UNI transceiver is disconnected from the MPC8260 enabling the use of its associated FCC1 pins off board via the expansion connectors ATM ON led is controlled by 3 2 30 RS232 Port 1 ON 1015 When the yellow RS232 Port 1 ON led is lit it designates that the RS232 transceiver connected to PB3 MOTOROLA Chapter 3 Operating Instructions 3 33 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc upper DB9 connector is active and communication via that medium is allowed When darkened it desig nates that the transceiver is in shutdown mode and its associated SCC1 pins may be used off board via the expansion connectors 3 2 31 RS232 Port 2 ON LD16 When the yellow RS232 Port 2 ON led is lit it designates that the RS232 transceiver connected to PA3 lower DB9 connector is active and commun
101. up on the ADS with a 10 resistor This line is shared with the ATM UNI s interrupt line and therefore when driven by external tool MUST be driven with an Open Drain gate Failure to do so may result in permanent damage to the MPC8260 or to ADS logic MOTOROLA Chapter 5 Support Information 5 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 5 7 P16 System Expansion Interconnect Signals Pin No Signal Name Attribute Description C12 IRQ7 I Interrupt Request 7 L Connected to MPC8260 s DP7 CSE1 IRQ7 signal Pulled up on the ADS with a 10 resistor This line is shared with the Fast Ethernet transceiver s interrupt line and therefore when driven by an external tool MUST be driven with an Open Drain gate Failure to do so might result in permanent damage to the MPC8260 and or to ADS logic C13 GND Digital Ground Connected to main GND plane of the ADS C14 T O T S Expansion Data 01 15 This is a double buffered version of the PPC bus D 0 15 lines controlled by on board logic These lines will be 5 EXPDI driven only if BTOLCS1 or BTOLCS2 are asserted Otherwise they are tristated 16 EXPD2 E The direction of these lines is determined by buffered BCTLO in C17 EXPD3 function of R W C18 EXPD4 C19 5 20 EXPD6
102. various cache sizes see Table 4 17 L2 Cache Size Encoding on page 67 20 23 24 BREVN 0 3 SWOPT2 Board Revision Number 0 3 This field represents the revision code hard assigned to the ADS See Table 4 16 ADS Revision Encoding on page 67 for revisions encoding Software Option 2 This is the LSB of the field Shows the state of a dedicated dip switch DS3 3 providing an option to manually change a program flow For the setting of DS3 see 3 2 7 DS3 Software Options Switch on page 30 25 27 FLASH PD 7 5 Flash Presence Detect 7 5 These lines are connected to the Flash SIMM presence detect lines which encode the Delay of Flash SIMM mounted on the Flash SIMM socket For the encoding of FLASH 4 1 see Table 4 12 Flash Presence Detect 7 5 Encoding on page 66 28 31 FLASH PD 4 1 Flash Presence Detect 4 1 These lines are connected to the Flash SIMM presence detect lines which encode the type of Flash SIMM mounted on the Flash SIMM socket For the encoding of FLASH 4 1 see Table 4 13 Flash Presence Detect 4 1 Encoding on page 66 l There is additional bit to this field See bit 24 in the same table MOTOROLA Chapter 4 Functional Description For More Information On This Product Go to www freescale com 4 65 4 66 Freescale Semiconductor Inc Table 4 12 Flash Presence Detect 7 5 Encoding FLASH_PD 7 5 FLASH DELAY nsec
103. 03 AE 1 30 5 ATMTSOC 524 4 AFl pang TxSOC TX_ER PC29 CLK3 TINZ 2 PC29 6177 Sisa ATMRXEN 7 22 2 05 pA28 RxEn_ TX_EN AES PC28 OND 8 rum a RN75 ALTI PA27 RxSOC RX DV PC27 CLK5 TxD0 eua Ee gt 222 28 PA2G RxCIAv RXEN PC26 CLKG TOUT3_ C5 a 0176 0 0 7 6 20 3 AJ8 p A25 TxD0 1xD8 PC25 CLK7 T D2 AES PC25 t ee s j 2 126 2 ATMTXDI RN78 8 RA 1 bA24 TxD1 TxD9 PC24 CLKB TxD3 AES 24 LL 3 3 c5 2 6 24 3 RN 9 AGI pA23 TxD2 TxD10 PC23 CLKG BRCO AF10 23 ci 5 ATMTXD3 9 221 AF12 pA23 TxD3 TxD11 PC22 CLK10 DONE_ 010 PC22 RS EN1 6 5 8 ATMIXD4 6 22 3 RN O 13 pA21 TxD4 TxD12 PC21 CLK 11 8860 172 452 ATMECLK 4 RIMON e ATMTXDS RN7O 5 RR 4 pA20 TxD5 TxD13 PC20 CLK 12 TCATE 12 100 443 2 5028 MC145583 N 6 2 22 2 RN D 158 19 r p 6 T D14 ecis cuk13 8Rco AO13 43 2 894 FETHRXCK 24 10 85601 ATMTXD7 RN 6 5 22 4 J16 5418 7 57 T 015 PCIB CLK14 TGATE 866 FETHTXCK 17 519 12 cmi T qmi 6 ATMRXD 0 7 ATMRXD RN amp AE16 415 amp D15 Pct 7 CUKT5 TiN4 ALB 7 15 3 ns 14 TXD1 2 AF17 pa 16 RxD6 RxD14 PC16 CLK16 TIN3 15 PC16 PC11 PC12 PC 15 17 ND 4 ATMRXDS AF 18 PA15 RxD5 RxD13 PC15 CTS A616 _PC15 22604
104. 1 EXPALE 9 89 BA25 35 14 25 A8 33 16 EXPD10 09 09 ile RN27 A10 B10 BA26 33 16 6 26 G1 32 17 1 010 010 191 A11 B11 27 32 17 5 27 62 8012 301 5 8412119 ExPD12 011 011 E 25 8013 29 1 13 20 ExPD13 lors 020 gt 8014 27 22 14 8015 26 5 23 8428 35442 1209 28 CPM EXP GPL buffer 5 26415 815 BA29 29 045 1322 29 5 T R2 27 22 25 014 914 0 2 BA31 261545 01523 1 126 EXPD 0 15 BA 16 31 424 PNE EXPA 16 31 74LCX125 8D 0 15 8AD027 2 3 88AD027 Y U24 1 BBCTLO U23 TOBUFEN CPM EXP Address Buffers 74LCX 125 CPM EXP Data Buffers 0028 5 6 BBADD28 Ls M4 u23 6 74LCX 125 9 8 BBADD29 Ls 8 96 Q E 2 38 947 Q 5 45 2 qa 39 SDRAM CLK 2 Rad 9128 mE SEE SM CK S gt o2 26 2 57 BCSR High MUX MICTOR High MUX ute 4 TTL_CLK1_SEL 03 TE SAN CERCA 6 EN 0425 SDRAM CLK 0 ON MODCKx 70 I x _ 0843 a LOCACHE 5 5 8 EE 0815 VOYAGER gi 16 zx Tristate 07 43 ME EXPANSION MICTOR 2145 p2 15 MODCKHO MODCKH 0 3 035 i S s O B 12 MODCKHS MODCK 1 R25 ape 5 MODCK2 7 K 8
105. 1 3 for PLLs Multiplication Factor DS1 6 8 on page 20 while MODCKH 0 3 are obtained from either the Flash memory or from 051 2 5 BCSR depended on the state of 051 1 See 2 3 5 Setting MODCKH 0 3 for PLLs Multiplication Factors on page 22 This newly introduced feature helps in cases where a user inadvertently erases the Flash memory containing the Hard Reset con figuration word essential for system start up The configuration master is determined upon the rising edge of PORST according to the state of RSTCONF signal driven low this board to set the MPC8260 as a configuration master After power on reset negates the hard reset sequence starts during which many other different options are configured see 4 1 2 4 Hard Rest Configuration on page 43 among these options are additional clock configuration bits MODCKH 0 3 the most significant bits of the MODCK field which determine addi tional options for the clock generator Although these bits are sampled whenever the hard reset sequence is entered they are influential only once after power on reset If a hard reset sequence is entered later MODCKH 0 3 although sampled are don t care l e the capacitor its input is discharged 4 42 MPC8260 PowerQUICC ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 4 1 2 Hard Reset Hard Reset may be generate
106. 32 port 1 is enabled this signal is the receive data line for that port When this port is disabled this signal is tristated and may be used to any available alternate function for PD31 A2 RS TXDI PD30 T S When RS222 port 1 is enabled this signal is the transmit data line for that port When this port is disabled this signal may be used to any available alternate function for PD30 A3 PD29 T S 8260 Port D 29 line Parallel I O or CPM dedicated line May be used for any of it s available functions MOTOROLA Chapter 5 Support Information 5 79 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 5 4 P4 CPM Expansion Interconnect Signals Pin No Signal Name Attribute Description A4 RS RXD2 PD28 T S When RS232 port 2 is enabled this signal is the receive data line for that port When this port is disabled this signal is tristated and may be used to any available alternate function for PD28 5 RS_TXD2 PD27 T O T S When 5232 port 2 is enabled this signal is the transmit data line for that port When this port is disabled this signal may be used to any available alternate function for PD27 PD26 T S MPC8260 s PD 26 18 Port D lines Parallel I O or CPM dedicated lines May be used for any of their available functions 7 PD25 8
107. 5 3 38 15 12 5 1 2 4 SDCAS SDRAS 5 9 6 1 DOM_WEO SDWE 4 APE 8 8 DQM_WE 1 SORMA10 o ABB 10 ARETRY DQM_WE2 mE 12 DOM_WE3 SDMUX e 13 0 14 TSIZEO DOM_WE4 BCTLQ CPUDBG 15 16 TSIZE1 DQM_WE5 L28R BRY 17 18 TSIZE2 L28G ALE 19 20 TSIZE3 DOM_WE7 12080 DBC 21 1 22 TTO VOYAGER LSDRMCS XBR3 23 24 ATMCSIN XBG3 MODCK3 25 26 172 TOOLCS1 XDBG3 GaL 27 420 28 TT3 TOOLCS2 IRQ6 L2HIT 29 30 4 58 IRQ7 CPUBR 31 32 TA csg o HRESETY 33 34 510 35 3 536 25 SRESET 35 3 36 MODCK1 511 37 CPUBC E PORST 37 38 MODCK2 SR 5 1 2 3 2 5m 9 6 CLKB LL RSTCNF Lm p 8 1416 BADD27 145 LCPLB 10 LA17 6 BADD28 n LSDWE 11E 12 LA18 LSDA10 13 0 14 1419 1119 4 4 LWR 15 E 16 1420 LSDCAS 5 9 RESERVED PCI_CLK LSDRAS 17 18 421 LDO 8 1016 LSDDOMO 1986 20 1 22 LD1 10 1017 LSDDOM1 21 1 22 1 23 19 LD2 11 12 1018 LSDDOM2 23 E24 1424 J12 LD3 13 14 1019 LSDDQM3 25 26 LA25 J10 LD4 15 16 1020 LOPO 27 2422 28 LA26 7 J13 LD5 17 18 1021 LOP1 29 50 27 7 J11 LD6 19 20 1022 LDP2 31 32 LA28 J170 LD7 218
108. 5 141 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc when ROW amp SDRAM NORMAL then SdramAdd RowAddNormal q else when ROW amp SDRAM PBI MODE SDRAM_16M then SdramAdd RowAddPBI 16M q else when ROW amp SDRAM PBI MODE amp SDRAM 64M then SdramAdd RowAddPBI 64M q else SdramAdd ColAdd q END 5 142 MPC8260 PowerQUICC ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 5 3 3 919 SDRAM s Latch Mux High L2 Cache Only MODULE vmuxhig5 TITLE MPC8260 Sdram 2nd Latch oe oe oe oe oe oe oe K This file contains 2 nd part of Address latch amp mux for the MPC8260 ADS sdram The is required only with L2 Cache installed on board Otherwise it is not assembled and SdramA 13 8 are connected to MPC8260 s proper address lines K K n this file 4 Rev PILOT 02 18 99 Added support for PBI Page Based Interleaving feature added with 8260 rev To provide that support the following were made Added DimmSize input which provides SDRAM dimm size information Only 16Meg reset default and 64Meg DIMMs are supported This signal originates in BCSR Added PBI indication Since PBI s actual
109. 5 stored in a 256 Byte Serial EEPROM residing on the DIMM compatible with protocol In fact all necessary information is in the first half of the EEPROM while the second half is system available On the ADS the DIMM configuration EEPROM is connected to the MPC8260 controller to inquire for SDRAM DIMM s configuration after hard reset sequence An example of such a serial eeprom access protocol may be seen in AT24C02 by Atmel data sheet This document may be obtained on the Internet at URL Attpz www atmel com atmel products prodl62 htm As can be seen from the Atmel document 3 bits of the device s 7 bit slave address b 1010A5A are compared against the SA 2 0 signals on the DIMM On the ADS these lines are controlled by a DIP Switch DS2 so that the DIMM s slave address may be changed in favor of other devices that may reside on the bus 4 8 Flash Memory SIMM The ADS is provided with 8 Mbytes of 95 nsec Flash memory SIMM the SM73228XG1JHBGO by Smart Modular Technology composed of four LH28F016SCT L95 chips by Sharp arranged as 2M X 32 in single bank Support is given to 16 MBytes and 32 MBytes SIMMs as well The Flash SIMM resides an 80 pin DIMM size is recorded within the configuration Serial EEPROM residing on the DIMM but obviously may not be used to qualify logic MOTOROLA Chapter 4 Functional Description 4 53 For More Information On This Product Go to www freescale c
110. 54 Resistor 75 Q 5 SMD 0603 0 1W DRALORIK D11 075RFCS 5 R6 R133 Resistor 82 5 Q 5 SMD 1206 1 DRALORIK D25 82R5FCS 4W R7 Resistor 22 1 5 SMD 1206 1 DRALORIK D25 22K1FCS 4W R8 R39 R44 R49 R56 R57 R77 Resistor 43 2 Q 1 SMD 0603 RODERSTEIN D11 43R2FCS R88 R94 R95 R96 R100 R112 0 1W 121 R9 RIO R11 R34 R50 R52 R54 Resistor 0 Q SMD 0603 0 1W RODERSTEIN D11 000RFCS R55 R60 R62 R65 R90 R103 R107 R110 R113 R115 R116 R117 R119 R142 R13 R14 R15 R16 R17 R29 R31 Resistor 10 KO 1 SMD 0603 RODERSTEIN D11 010 5 R33 R35 R46 R47 R48 R53 R58 0 1W R59 R61 R66 R67 R18 R19 R122 R125 R128 R129 Resistor 4 7 1 SMD 0603 RODERSTEIN D11 04K7FCS R134 0 1W R20 R22 R27 R28 R36 R37 R38 Resistor 150 Q 5 SMD 1206 1 RODERSTEIN D25 150RFCS R71 4W R21 R23 R24 Resistor 1 5 KQ 5 SMD 1206 1 RODERSTEIN D25 01 5 5 4W R32 R40 R41 R42 R43 R73 R76 Resistor 22 1 SMD 0603 0 W RODERSTEIN D11 22ROFCS R78 R84 R63 R79 Resistor 10 Q 1 SMD 1206 1 4W RODERSTEIN D25 10R FCS AVX CR32 10ROF T R64 Resistor 2 2 KQ 1 SMD 1206 1 RODERSTEIN D25 02K2F CS 4W R68 R70 R80 R81 R86 R87 R92 Resistor 1 5 SMD 0603 DRALORIK D11 001KFCS R93 R97 R99 R101 R102 R109 0 1W R136 R69 Resistor 47 195 SMD 1206 1 RODERSTEIN D25 047KFCS 4W R75 Resistor 0 SMD 1206 1 4W RODERSTEIN D25 000RFCS MOTOROLA Chapter 5 Support Information 5 103 For More Information On This Produc
111. 57 _ 6 95 4 058 815 Q 1UF 059 16 0027 26 260 8160128 17 129 Q 1UF 62 A18lpi sg x c2 03 8171 398338933 29498437 4 35520528 28554894 49479429989 lt ao acit semester ls lt 0 1UF dE 358588 C25 jojo 6555155 eremi N 2 4 E e 0 1UF 2 19 Q 1UF C27 Q 1UF u2s 101d spo 156040 304 S38sn 1utu 95 71 66 100 96 71 66 120 910 9 150 For More Information This Produ T Go to
112. 60 s A10 4 50 MPC8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Figure 4 3 SDRAM DIMM 60X Bus Connection Scheme SDC2UV6482C 84 CS2 IE PSDRAS mE DIMM SIZE 0 16M 1 64M RAS PBI PSDCAS CAS p PSDWE LATCH A 6 8 WE 0 BANKSEL 1 2 7 9 BINE BA 1 0 1 SDRMAI 0 A 8 10 ESS SDRMA9 ET A 6 28 8 0 018 PSDDOM 7 em 40 55 y oos A 119 77 s i CKE CLK 3 6 ALE LE 20 28 3 6 CLK 1 4 PSDAMUX DCDAT aa DCCLK SA 2 0 Serial EEPROM Slave Address Setting Switches As can be seen from the above with respect to the previous revision of the ADS the address latch mux was expanded and is conditioned with PBI and DIMM SIZE indications from BCSRO The SDRAM performance is shown in Table 4 3 SDRAM DIMM 84MHz Performance Figures on page 51 Table 4 3 SDRAM DIMM 84MHz Performance Figures System Clock System Clock Cycle Type Cycles 66MHz Bus G Bus Clock Clock Freq q With L2 cache Burst Read Page Miss 6 1 1 1 7 1 1 1 Burst Read Page Hit 41 1 1 1 51111 Burst Write Page Miss 41 1 1 1 51 1 1 1 Burst Write Page 211 11 41111 Refresh 82
113. 6245 aol2 D31 ao 2 8031 ns 5 2 82 A2 82 ALE 0 BALE 8316 028 4343 6 8028 Yy gt mf 8512 4045 652 025 _ 38 6 LL 8025 AT 97 1 024 _ 37147 87 12 8024 74LCX541 OET OET 0 3 4 DOM WEQ 2 1 yi 18 1 BWEO 99 5 17 7222 EXPWE 0 2 Y2 07 361 8 13 807 025 361 8 13 8025 du T SWETS 06 35 14 806 022 35 14 8022 A9 B9 A9 B9 5 15 dh EXPWE 1 D5 35 16 805 021 35 16 8021 4 4 A10 810 A10 B10 DOM_WE2 6 ag 5 14 amp yXIRNTA BWE2 Da 132 17 804 020 i2 4 17 8020 IA Y 7 15 BWE3 3 30 19 803 019 30 19 8019 6 6 A12 B12 A12 812 TOOLCS 1 8 12 BTOLCS1 i in 02 29 20 802 018 29 20 8018 7 Y 13 815 A13 813 TOOLCS2 9 11 g BTOLCS2 D1 27 22 801 D17 27 22 BD17 A8 Y8 A14 814 A14 B14 1 RN17 6 Da 26 45 gig 23 BDO 016 126 p15 23 8016 19 5 24 T R2 24 T R2 40E2 OED 021 uo CPM EXP STROBE Buffer DBUFEN 412 125 _2 38 22 1 BBCTLO 12 RNGA 7 037 7 Main Data Buffers 74LCX125 ME 6122 RNO4 4 037 74LCX125 T 5 p 8s EXPCTLO MOTOROLA INC 8 tg 64 PROJECT MPC8260ADS REV PILOT SHEET 2 OF 18 8 CND 4 U37 YAIR LIEBMAN BLOCK BUFFERS CHK DESCRIP A B 3 K tmp mnt net prince yai
114. 7 5 nsec propagation delay System Programmable Logic Device 100 pin TQPF 018 019 M4 64 32 32 I O 64 Macrocell 7 5 Vantis M4 64 32 7VC48 nsec propagation delay In System Programmable Logic device 48 pin 022 16 MByte 168 100MHz Fujitsu SDC2UV6482D 100T S or SDRAM DIMM organized as 2X 1 PDC2UV6484 102 103 MX 64 10 T S 168 pin 909 T H DIMM Socket AMP 390040 6 with Plastic Latches 3 3V Unbuffered U24 U29 U30 Low Voltage CMOS 5V Tolerant 16 Motorola MC74LCX16244DT bit buffer with OEs 48 pin Plastic TSSOP Case 1201 01 U25 8 MByte Flash SIMM 95 nsec delay Smart Modular SM73228XGIJHBGO Single bank composed of four Technology LH28F016SCT L95 chips by SHARP SHARP 80 pin SIMM Socket AMP 822032 5 U26 Low Voltage CMOS 5V Tolerant 16 Motorola MC74LCX16245DT bit Transceiver 48 Plastic TSSOP Case 1201 01 U27 U28 Low Voltage CMOS 5V Tolerant 16 Philips T4ALVT16245DL bit Transceiver with Bus Hold 48 pin Plastic TSSOP U27 U28 Low Voltage CMOS 5 Tolerant 16 Philips T4ALVT16373DL bit Transparent Latch with Bus Hold 48 pin Plastic TSSOP U33 Octal Tri State Buffer Motorola 74 5410 035 9 Output Low inter skew Clock Motorola MPC947 Buffer U36 Voltage level detector Range 2 8V Seiko S 80828ANMP EDR T2 2 output SOT 23 5 package U38 Fast Ethernet Transceiver Level 1 LXT970A 5 106 MPC8260 PowerQUICC II ADS User s Manual MOTOROLA
115. 7 FX 59 8012 n 62 0011 SDRMCS1 30 NCB 0012 58 8011 143 e 0013157 8010 mE 114 85 0014 55 809 44 45 11 55 808 SDRMCS2 129 nor 109 0015 440 766 J72 1 NC13 196 8 8023 SORAS 115 SDRAM168DIMM 0 SDGAS e Trs NC15 154 10 8021 165 9 SDWE 27 13 0019111 8020 25 445 0020 12 8019 A OM_W DOMO 13 8018 1 29 127 0021 459 o DOM1 NC19 14 BD17 x DOM WEA 46 184 0022 160 DQM2 NC20 15 BD16 6 47 0023 58 r3 DOM WE3 112 21 00 2 DOM WE2 113 Eran 1 PSDDP1 0024 E 8041 DOM_WES 130 29 PSDDP2 DQ25 17 9978 57 9 Q DOM WE7 131 PSDDP3 DQ26 158 g PSDDP4 0027 956 CLK3 lt 00 5 132 i 028 22 8027 diss C5 F_PD1 73 pp4 0029 26 8026 CLK 1 PSDDP6 27 BD25 154 CLK2 7 500 7 0030 024 55 10 C PSDDP 0 7 DQ31 0163 LK3 CKEO 65 CN 0 sf 10 O r C CN C0 u O C ro st D Q0 O GC V3 3 4444444 10 D 00 DO O O O 7 10K ad 0 CY OG C3 CI 63163 NC1 ce S r SM73228XC1JHBCO
116. 8 pin Synchronous Dram DIMM residing on 60X bus con trolled by SDRAM machine 1 Support for 64 MBytes DIMM single bank only Option al address Latch Multiplexer is required if an L2 cache module is assembled Support for PBI Page Based Interleaving in both Single and 60 2 modes Support for Automatic DIMM Identification via MPC8260 s PC port and DIMM s serial EEPROM Optional 1 2 MByte L2 Cache on board using 2 MPC2605 Lookaside cache modules 8 MByte 80 pin Flash SIMM buffered from 60X bus Support for upto 32 MByte con trolled by 5 or 12V Programmable with Automatic Flash SIMM identification via BCSR Support for both On and OFF SIMM Flash reset 5V 12V VPP for Flash SIMM Jumper Selectable 4 MByte unbuffered SDRAM on Local bus controlled by SDRAM machine 2 soldered directly on board Board Control amp Status Register BCSR Controlling Board s Operation Fast Download support via JTAG Power On Reset Option via JTAG Programmable Power On Reset and Hard Reset Configurations via Flash memory option ally provided by BCSR dip switch selectable providing a rescue mode in case of inad vertent Flash erasure Module Enable Indications for all on board communication modules High density MICTOR Logic Analyzer connectors carrying all MPC8260 signals for fast logic analyzer connection 155 Mbps ATM UNI on with Optical I f connected to the MPC8260 via UTOPIA I F using th
117. 82 From TS Asserted First access may be longer due to internal pipeline delay including arbitration overhead MOTOROLA Chapter 4 Functional Description 4 51 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 4 7 1 SDRAM Programming After power up the SDRAM needs to be initialized by means of programming to establish its mode of op eration The SDRAM is programmed according to the following procedure 1 Issue Precharge All command 2 Issue 8 CBR refresh commands 3 Issue MODE SET command When a Mode Register Set command is issued data is passed to the Mode Register through the SDRAM s address lines This command is fully supported by the SDRAM machine of the MPC8260 Mode Register programming values are shown in Table 4 4 66 MHz SDRAM DIMM Mode Register Pro gramming below Table 4 4 66 MHz SDRAM DIMM Mode Register Programming SDRAM Address SDRAM Reg Value Meaning zl Field Line MSB Reserved 0 10 0 9 Os 41 0 Burst Read amp Burst Write Copy Back data cache 1 Burst Read amp Single Write Write Through Data cache 8 Reserved 0 7 0 A4 CAS Latency 010 Data Valid 2 Clocks cycles after CAS Asserted A3 Burst Type 0 Sequential Burst 2 0 Burst Length 7011 8 Burst Length Actually SDRAM s AO is connecte
118. A Chapter 3 Operating Instructions 3 29 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 3 2 7 DS3 Software Options Switch DS3 is a 4 switch Dip Switch This switch is connected over SWOPT 0 2 lines which are available at BCSR2 S W options may be manually selected according to DS3 state DS3 is factory set to all ON Figure 3 1 DS3 Description SWOPTO Pulled to 1 SWOPTO Driven to 0 SWOPTI Pulled to 1 SWOPTI Driven to 0 SWOPT 2 Pulled to SWOPT2 Driven to 0 RESERVED DS3 3 2 8 VDDL Voltage Level Range Selection selects between 3 different voltage level ranges available for VDDL For further information over its function see 2 3 1 Setting VDDL Level Range on page 19 3 2 9 J2 IDDL Measurement J2 resides in IDDL s main current flow To measure IDDL J2 should be removed using a solder tool and a current meter should be connected instead with wires as short and thick as possible Warning The job of removing J2 and soldering the current meter connections instead is very delicate and should be done by a skilled technician If this process 15 done by unskilled hands or repeated more than 3 times permanent damage may occur to the MPC8260ADS 3 2 10 J3 Thermal Sense Connector There are 2 dedicated pins 0 1 which provide a way to take internal temperature measurements of the MPC8260 These
119. B27 MOTOROLA Chapter 5 Support Information 5 83 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 5 4 P4 CPM Expansion Interconnect Signals Pin No Signal Name Attribute Description FETHCRS PB26 I O T S Fast Ethernet Carrier Sense H When this signal is asserted High while the Ethernet port is enabled and the LXT970 is in half duplex mode it indicates that either the transmit or receive media are non idle When the LXT970 is in either full duplex or repeater operation it indicates that the receive medium is non idle When the Ethernet port is disabled this line may be used for any available function of PB26 C7 FETHTXD3 PB25 I O T S Fast Ethernet Transmit Data 3 0 This is the MII transmit data bus The MPC8260 drives these lines according to rising edge of FETHTXCK C8 FETHTXD2 PB24 When the ethernet port is disabled these lines may be used for any C9 FETHTXDI PB23 available respective function C10 FETHTXDO PB22 21 T O T S Fast Ethernet Receive Data 3 0 This is the receive data bus The LXT970 drives these lines according to rising edge of FETHRXCK cu FETHRXDI PB20 When the ethernet port is disabled these lines are tristated and may be FETHRXD2 19 used for any available respective parenthesized funct
120. BCSR or directly to the MPC8260 15 depended See 3 2 12 15 COP JTAG TDI Source Selection on page 31 and 4 13 COP JTAG Port on page 68 Test port Reset L When this signal is active Low it resets the JTAG logic of both the MPC8260 and the Fast Download machine This line is pull down on the ADS with 1K resistor to provide constant reset of the JTAG logic QREQ Quiescent Request L When asserted low this line indicates that the 8260 desires to enter low power mode This signal may be required by a debug station V3 3 3 3V power supply bus TCK Test port Clock This clock shifts in out data to from the MPC8260ADS JTAG logic Data is driven on the falling edge of and is sampled both internally and externally on it s rising edge TCK is pulled up internally by the MPC8260 N C Not Connected TMS Test Mode Select This signal qualified with TCK in a same manner as TDI changes the state of the JTAG machines This line is pulled up internally by the MPC8260 10 GND Digital GND Main GND plane Was N C with ENG revision 11 SRESET Soft Reset L This is the MPC8260 s soft reset which is in fact a non maskable interrupt making the PPC take the reset exception from the reset vector This line may be driven by the MPC8260 as well during soft reset sequence for 512 system clocks This line is pulled up on the ADS with a res
121. Bcsr0 PBI for simulation DimmSize L2Inh B L2Flush B L2Lock B L2Clear B SignaLampO B SignaLampl B Besrl AtmEn for simulation 5 114 MPC8260 PowerQUICC II ADS User s Manual For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc AtmRst_B FEthEn B FEthRst B RS232Enl B RS232En2 Besr6 JtagEn for simulation ToolCs ToolCs1 B ToolCs2 B FlashCsOut FlashCs4 B FlashCs3 B FlashCs2 B FlashCsl Reset HardReset B SoftReset ResetEn HardResetEn SoftResetEn TransRst AtmRstOut B FEthRstOut Rst Rst1 Rst0 Abr AbrL Abr0 Debounce RstDeb1 AbrDeb1 SyncReset SyncHardReset B DSyncHardReset B RstCause PORIn_B Rst1 Rst0 Abr1 Abr0 HoldOffCnt HoldOffCnt1 HoldOffCnt0 F PD3 F PD2 F PD1 FlashCs B BrdContRegCs B AtmUniCsIn B ToolCs1 B ToolCs2 B BufEn DataBufEn B ToolDataBufEn ConfAdd 27 28 ifndef 2 CfgByte0 0 0 0 0 1 1 0 0 CfgBytel 1 0 1 1 0 0 1 0 CfgByte2 0 0 0 0 0 0 1 0 CfgByte3 0 0 0 0 MODCKH0 MODCKH1 MODCKH2 MODCKH3 ifdef L2CACHE CfeByte0 0 0 0 1 1 1 0 0 CfgBytel 1 0 1 1 0 0 1 0 CfgByte2 0 0 0 0 0 0 1 0 CfgByte3 0 0 0 0 MODCKH0 MODCKH1 MODCKH2 MODCKH3 Modck MODCKHO0 MODCKH3
122. Bus SDRAM Programming 56 Local Bus SDRAM 57 I 2 Cache Optional tote 57 L2 Cache Configuration amp Control 58 Communication 58 58 59 EX TOT C OB OL yam 60 RS232 60 RS 232 Signal Description 60 Board Control amp Status Register BCSR 61 BCSRO Board Control Status Register 0 62 BCSRI Board Control Status Register 63 BCSR2 Board Control Status Register 2 64 Contents V For More Information On This Product Go to www freescale com 4 12 4 4 12 5 4 12 6 4 13 4 13 1 4 13 1 1 4 13 1 2 4 13 1 3 4 13 1 4 4 13 1 5 4 13 1 6 4 13 1 7 4 13 1 8 4 13 2 4 14 4 14 1 4 14 2 4 14 3 4 14 4 5 1 5 1 1 2122 5 1 3 5 1 4 5 1 5 5 1 6 5 1 7 5 1 8 5 2 5 3 5 3 1 5 3 2 5 3 3 6 1 Freescale Semiconductor Inc CONTENTS Page Number BCSR3 to BCSRS Board Control Status Register 3 5 67 BCSR6 Board Control Status Register 6
123. C23 C24 C28 Capacitor 0 1uF 16V 10 SMD AVX 0603 YC104KAT20 C29 C30 C31 C33 C34 C35 C36 0603 Ceramic C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C64 C65 C67 C69 C70 C71 C72 C73 C74 C75 C76 C77 C78 C79 C80 C84 C85 C86 C87 C88 C92 C99 C104 C105 C106 C107 C108 C109 C110 C111 C112 C113 C114 C115 C116 C117 C118 C119 C120 C122 C123 C125 C126 C127 C128 C129 C130 C131 C137 C138 C139 C140 C144 C145 C146 C151 C157 C159 C161 C162 C163 C166 C168 C169 C172 C173 C174 C177 C179 C182 C184 C188 C192 C194 C200 C201 C202 C203 C204 C205 C63 C68 C93 C100 C101 C121 Capacitor 47uF 20V 10 SMD AVX TAJD476K016 C132 C134 C149 C160 SIze D Tantalum C66 Capacitor 100uF 10V 10 SMD AVX TAJD107K016R Size D Tantalum C135 Capacitor 1500pF 50V 5 COG AVX 12065A152JAT00J SMD 1206 Ceramic C148 C150 C156 22pF 50V 5 1206 5A 220J AT SMD 1206 Ceramic C152 Capacitor 1uF 20V 10 SMD SIze SIEMENS B45196H5105K109 B Tantalum C170 C175 10 50V 10 SMD SIEMENS 1206 Ceramic 5 94 MPC8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 5 8 MPC8260ADS Bill Of Material Reference Designation Part Description Manufacturer Part C207 Capacitor 0
124. C8260 Since MDDIS pin of the LXT970 is driven low with this application the negation of this signal causes all the H W configuration bits to be sampled for initial values and device control is moved to the MDIO channel which is the control path of the MII port 6 RS232bN 1 RS232 port 1 Enable When asserted low the RS232 transceiver for port 1 1 R W upper is enabled When negated the RS232 transceiver for port 1 is in standby mode and 5 pins are available for off board use via the expansion connectors 7 RS232EN 2 RS232 port 2 Enable When asserted low the RS232 transceiver for port 2 1 lower is enabled When negated the 5232 transceiver for port 2 is in standby mode and 5 2 pins are available for off board use via the expansion connectors 8 31 Reserved Un implemented ATM transceiver itself does not enter standby mode the fact that it 15 disconnected from the 8260 emulates this state 2Required for voltage levels adaptation 4 12 3 BCSR2 Board Control Status Register 2 BCSR2 15 status register which is accessed as word at offset 8 from the BCSR base address Its a Read Only register which may be read at any time BCSR2 s various fields are described in Table 4 11 BCSR2 Description on page 64 Table 4 11 BCSR2 Description BIT MNEMONIC Function 0 7 TSTAT 0 7 Tool Status 0 7 This field is reserved for external tool st
125. CPM expansion connectors and the ethernet transceiver Independent Interface MOTOROLA Chapter 4 Functional Description For More Information On This Product Go to www freescale com Freescale Semiconductor Inc may be Disabled Enabled at any time via the MII s MDIO port The LXT970 is able to interrupt the MPC8260 via the IRQ7 line This line is shared also with the CPM expansion connectors Therefore any tool that is connected to IRQ7 or IRQ6 for that matter should drive these lines with an Open Drain buffer Both IRQ6 and IRQ7 are pulled up on the ADS 4 11 2 1 LXT970 Control The LXT970 is controlled via the MII management port which is a 2 wire interface a clock MDC and a bidirectional data line This is in fact a bus 1 up to 32 devices may reside over it while the protocol defines a 5 bit slave address field which is compared against the slave address set to each device by hardware during device reset according to the levels on MF 4 0 pins On the ADS the slave address is hard set to b00000 The MPC8260 on the ADS interfaces this port using two PI O pins PC9 for MDIO and PC10 for MDC There is no special support within the MPC8260 for the MDIO port and the protocol is im plemented in S W The MDIO port may interrupt a host in 2 ways driving low the MDIO line during IDLE time b using a dedicated interrupt line FDS MDINT which may also serve as Full Duplex indicatio
126. DEFAULT RS232 2 then 5232 2 ENABLE else RS232 2 ENABLE state 185232 2 ENABLE if VGR WRITE BCSR 1 amp RS232 2 ENABLE DATA BIT pin RS232 2 ENABLE amp RESET RS232 2 ENABLE PON DEFAULT RS232 2 ENABLE PON RESET amp RS232 2 ENABLE PON DEFAULT RS232 2 ENABLE then RS232 2 ENABLE else IRS232 2 ENABLE BCSR 3 ifdef JTAG state_diagram JtagEn state JTAG_ENABLED if WRITE JTAG DOWNLOAD CSR 6 JTAG ENABLE DATA BIT pin JTAG ENABLED amp IPON RESET ENABLE PON DEFAULT JTAG ENABLED PON RESET amp ENABLE PON DEFAULT ENABLED then ENABLED 5 128 8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc else JTAG_ENABLED state TAG ENABLED if WRITE JTAG DOWNLOAD CSR amp TAG ENABLE DATA BIT pin JTAG ENABLED amp RESET JTAG ENABLE PON DEFAULT JTAG ENABLED PON RESET amp ENABLE PON DEFAULT JTAG ENABLED then JTAG ENABLED else ENABLED
127. DERSTEIN D11 04K7FCS R134 0 1W R20 R22 R27 R28 R36 R37 R38 Resistor 150 0 5 SMD 1206 1 RODERSTEIN D25 150RFCS R71 4W R21 R23 R24 Resistor 1 5 5 SMD 1206 1 RODERSTEIN D25 01 5 5 4W R32 R40 R41 R42 R43 R73 R76 Resistor 22 1 SMD 0603 0 1W RODERSTEIN D11 22ROFCS R78 R84 R63 R79 Resistor 10 1 SMD 1206 1 4W RODERSTEIN D25 10R FCS AVX CR32 10ROF T R64 Resistor 2 2 KQ 1 SMD 1206 1 RODERSTEIN D25 02K2F CS 4W R68 R70 R80 R81 R86 R87 R92 Resistor 1 5 SMD 0603 DRALORIK D11 001KFCS R93 R97 R99 R101 R102 R109 0 1W R136 R69 Resistor 47 195 SMD 1206 1 RODERSTEIN D25 047KFCS 4W R75 Resistor 0 SMD 1206 1 4W RODERSTEIN D25 000RFCS R82 Resistor 0 5 Q 1 SMD 1206 1 RODERSTEIN D25 0R50F CS 4W 5 96 MPC8260 ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 5 8 MPC8260ADS Bill Of Material Reference Designation Part Description Manufacturer Part R83 Resistor 51 Q 1 SMD 1206 1 AW DRALORIK D25 051J S R91 Resistor 243 Q 1 SMD 1206 1 RODERSTEIN D25 243RF CS 4W R98 Resistor 110 Q 1 SMD 1206 1 AVX CR32 111J T 4W R104 R106 R108 R111 155 R156 Resistor 330 Q 5 SMD 1206 1 RODERSTEIN D25 330RJCS R157 R159 R162 4W R114 R118 R120 Resistor 1 1 SMD 1206 1
128. Dedicated State Signals Falling Edge equations FallingTckSignals clk Tck FallingTckSignals ar JtagStateReset fb FallingTckSignals ap 0 JtagResetState STATE JTAG RESET Active Low JtagShiftIrState STATE JTAG SHIFT IR JtagShiftDrState STATE JTAG SHIFT DR JtagTdoEnable STATE JTAG SHIFT IR Z STATE JTAG SHIFT DR Jtag Instruction Shift Register equations JtagShiftIR clk Tck MOTOROLA Chapter 5 Support Information For More Information On This Product Go to www freescale com Freescale Semiconductor Inc JtagShiftIR ap JtagReset fb reset gt bypass JtagShiftIR ar 0 when JtagShiftIrState fb amp STATE JTAG ENABLED then JtagShiftIR Tdi JtagShiftIRO fb JtagShiftIR 1 fb else when STATE JTAG CAPTURE IR amp STATE JTAG ENABLED then INST CODE BYPASS interim default else JtagShiftIR JtagShiftIR fb Instruction Register equations JtagIR clk Tck JtagIR ap JtagReset fb reset gt bypass JtagIR ar 0 when STATE JTAG UPDATE IR amp NEXT INST DOWNLOAD NEXT_INST_PON_RESET then JtagIR JtagShiftIR fb else when STATE JTAG UPDATE IR amp INST DOWNLOAD NEXT INST PON RESET then JtagIR INST CODE BYPASS else JtagIR
129. ENABLED eng compatible Okk Kk k K k Data Bits Assignments ENABLE BIT D0 Flash Declarations II FLASH ENABLE 0 SM73228XU1 2 1X8 MByte bank SM73248XU2 F_PD 1 2 X 8 MByte banks SM73288XU4 F_PD 0 4X 8 MByte banks FLASH SM73228XU1 SM73248XU2 amp A8 SM73288XU4 amp A7 amp A8 FLASH BANK SM73248XU2 amp A8 SM73288XU4 amp A7 amp A8 FLASH BANK3 A7 amp A8 amp SM73288XUA FLASH A7 amp amp SM73288XU4 Reset Declarations kK HARD RESET 0 SOFT RESET 0 DRIVE MODCK TO VGR HardReset B HARD RESET ACTIVE although power on driven by HRESET 5 118 8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc HARD RESET ASSERTED SyncHardReset_B fb HARD RESET ACTIVE data buffers enable 3k k K R oe BUFFER DI
130. ET e N C reserved for KEY CKSTP OUT e 19 GND For the detailed description of the COP JTAG connector signals see Table 5 5 P5 JTAG Con nector Interconnect Signals on page 86 4 13 1 Fast Download Support Download rates through the COP port are inherently slow due to very long COP scan chains and the extra neous amount of data transferred On revision PILOT of the ADS support was added for fast download through the JTAG port In essence an additional to MPC8260 s JTAG machine was added in front of the MPC8260 s JTAG port This machine supports the minimal public set of JTAG instructions required by JTAG rules to be a part of a JTAG chain while having in fact zero pins This machine includes a serial to parallel interface the serial part 15 driven by JTAG while the parallel is mapped into the PPC bus embedded in BCSR s memory improve crosstalk immunity for COP JTAG signals pins 2 and 10 were connected to GND According to the general recommendation and with ENG revision of this board they should be were N C No Boundary Scan pins Excluding the JTAG I F pins which are not count for that matter MOTOROLA Chapter 4 Functional Description 4 69 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc space This configuration allows zero data overhead during downloads The block diagram of the JTAG system the ADS is shown in Figure 4 8 ADS
131. F Q 1UF Q 1UF Q 1UF 1UF Q 1UF Q 1UF 1UF 1UF 0 10 0 10 Q 1UF 47UF Freescale Semiconductor Inc C122 C106 C116 C125 C105 0147 1UF 1UF 1UF 0 10 0 10 0 10 0 10 0 10 14 C59 6 My od RN23 1 2 RN24 84 RN38 1 2 RN39 RN50 BRR RN49 BRA RN58 6998 RN62 6998 RNE 5 4 62 Sd RN698 95600 RN24 Rot RN63 THERMO THERM1 CND v3 FAC_SET_2_3 ug GND TEST VOYAGER_TEST J120 TEST 012 TEST amp ERMAL PROJECT MPC8260ADS REV PILOT SHEET 11 OF 18 YAIR LIEBMAN BLOCK CAPS amp SPARE CHK DESCRIP This Product ion to o For More Informa 2359314 tmp_mnt net prince yair voyager ads pilot sch 12 drw 26 SEP 99 19 06 last update 26 SEP 99 13 57
132. FETH RESET ACTIVE state FETH RESET ACTIVE if VGR WRITE BCSR 1 amp FETH RESET DATA BIT pin FETH RESET ACTIVE amp RESET FETH RESET PON DEFAULT FETH_ RESET PON RESET amp FETH RESET PON DEFAULT FETH RESET ACTIVE then FETH RESET ACTIVE else IFETH RESET ACTIVE state diagram 5232 B state RS232 1 ENABLE if VGR WRITE BCSR 1 amp RS232 1 ENABLE DATA BIT pin RS232 1 ENABLE amp IPON RESET RS232 1 ENABLE PON DEFAULT RS232 1 ENABLE PON RESET amp RS232 1 ENABLE PON DEFAULT RS232 1 then 188232 1 ENABLE MOTOROLA Chapter 5 Support Information 5 127 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc else RS232_1 ENABLE state RS232 1 ENABLE if VGR WRITE BCSR 1 amp RS232 1 ENABLE DATA BIT pin RS232 1 ENABLE amp IPON RESET 5232 1 ENABLE PON DEFAULT IRS232 1 ENABLE PON RESET amp RS232 1 ENABLE PON DEFAULT 5232 1 ENABLE then RS232 ENABLE else IRS232 1 ENABLE state diagram RS232En2 B state RS232 2 ENABLE if VGR WRITE BCSR 1 amp RS232 2 ENABLE DATA BIT pin RS232 2 ENABLE amp IPON RESET RS232 2 ENABLE PON DEFAULT RS232 2 PON RESET amp RS232 2 ENABLE PON
133. For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 5 9 MPC8260ADSL2C Bill Of Material Reference Designation Part Description Manufacturer Part 1 Crystal resonator 25 MHz EPSON 505 Fundamental Oscillation mode Frequency tolerance 30 ppm Drive level 2mW max 10uW 100 uW recommended Shunt capacitance 5pF Max Load capacitance 10pF min Equivalent Series Resistance 400 Max Insulation Resistance 500 min Matched Impedance Connector 5 3 Programmable Logic Equations The MPC8260ADS has one programmable logic device on it U17 serving the role of Board Control and Status Register and providing miscellaneous system control functions on the ADS Implemented using an M4 128 64 7VC by Vantis The MPC8260ADSL2C the same ADS but with L2 Cache on it has an additional 2 programmable logic devices U18 and 019 serving as Latch Mux for the SDRAM DIMM Implemented using an M4 64 32 7VC48 by Vantis The design files for the above devices are written ABEL format and are listed below MOTOROLA Chapter 5 Support Information For More Information On This Product Go to www freescale com 5 107 Freescale Semiconductor Inc 5 3 1 017 BCSR amp System Control MODULE 12 Pins declaration
134. Freescale Semiconductor Inc 11 1999 Rev 0 213 8260 PowerQUICC II ADS User s Manual owerPc AA MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PowerQUICC II is a trademark of Motorola Inc Mfax is a trademark of Motorola Inc The PowerPC name the PowerPC logotype PowerPC 601 PowerPC 603 PowerPC 603e PowerPC 604 PowerPC 604e and RS 6000 are trademarks of International Business Machines Corporation used by Motorola under license from International Business Machines Corporation is a registered trademark of Philips Semiconductors Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors There are no express or implied copyright licenses granted hereunder to design or fabricate PowerPC integrated circuits or integrated circuits based on the information in this document Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters can and do vary in different applications All operating parameters incl
135. ICLKO PD12 L1ST2 L1RXD 2925 20 105 9 DTR2 amp 2811 452 AJ24 5641 Rx03 TxD0 PD11 L1RQ RxDO 425 PD11 181 eto 1 R56 24 584 RxD2 TxD1 PD10 L1CLKO RxD 1 2927 10 261 005 Rx5 PBS 5224 AG24 589 RxD1 TxD2 PD9 SMTXD RxPrty A426 POS 2 CND 2 27 bB amp R DO TxD3 PD8 SMRXD TxPrty 2625 poa 7 987 5 24 4 AE26 587 TxD0 RxD3 PD7 SMSYN TxAD3 28 Ub RN 3 a 22 1 AD25 pB6 TxD1 RxD2 PD6 T D4 DAck 29 PD6 LOWER CONN PBS 7 RR 2 AD256 pas r n gyp1 PD6 TxD3 D0NE _ A027 5 12 167 PB 4 17 PB4 RN73 6 RR 3 AD28 PBA TxD3 RxDO PDA L1TSYN SMRXD 28 04 PD 4 13 5 F RN73 012 MOTOROLA INC 8 PROJECT MPC8260ADS REV PILOT SHEET 7 OF 18 ENG YAIR LIEBMAN BLOCK CPM amp 85232 CHK DESCRIP 8 2359314 J K tmp mnt net prince yoir voyager ads pilot sch 8 drw 26 SEP 99 19 05 last update 23 SEP 99 14 12
136. IZE PON DEFAULT IDIMM SIZE 16M PON RESET amp DIMM SIZE PON DEFAULT DIMM SIZE 16 then DIMM SIZE 16M else IDIMM SIZE 16M lt Okoik k k 9k sk state diagram L2Inh state L2CACHE INHIBITED if VGR WRITE BCSR 0 amp L2CACHE INH DATA BIT pin L2CACHE INHIBITED amp RESET L2CACHE INH PON DEFAULT L2CACHE INHIBITED PON RESET amp L2CACHE INH PON DEFAULT INHIBITED then IL2CACHE INHIBITED else L2CACHE INHIBITED state 2 INHIBITED if VGR WRITE BCSR 0 amp L2CACHE INH DATA BIT pin L2CACHE INHIBITED amp RESET L2CACHE INH PON DEFAULT L2CACHE_INHIBITED PON RESET amp L2CACHE INH PON DEFAULT L2CACHE INHIBITED then L2CACHE INHIBITED else IL2CACHE INHIBITED R R R state diagram L2Flush B state L2CACHE FLUSHED if VGR WRITE BCSR 0 amp 2 FLUSH DATA BIT pin L2CACHE FLUSHED amp RESET L2CACHE FLUSH PON DEFAULT L2CACHE FLUSHED PON RESET amp L2CACHE FLUSH PON DEFAULT 2 FLUSHED then IL2CACHE FLUSHED MOTOROLA Chapter 5 Support Information 5 123 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc else L2CACHE_FLUSHED state 2 FLUSHED if VGR WRITE BCSR 0 amp L2CACHE FLUSH DATA BIT
137. LD5 7 042 7 C LDP3 2989 Z y 6 HRESET 1K gt 6 gt 106 8 041 a 8 4 BCSR2CS 4 gt ROY SWOPTO 4 LD7 915 040 o 5 xi que L2LOCK 3 a SRESET 1K z SWOPT1 3 iz 2 SGLAMPO 2 R102 BREVO 2 RN56 9 RN8 RN67 9 1 E L2CLEARY 19K SWOPT2 1 GND CND gt K 2012 i 052 ii 3 4355 RN74 3 5 lt MW 2 gt 055 2 8 SDMUX 19k 5015 3 lt A of lt LSDDOM2 9 1014 4 055 Xs 5 R17 9 lt gt 4 R52 R45 L2CACHE f 15000 3 Ses TOR al 5 10 6 048 6 4 x 15000 1 7 eA EXTOLI2 7 1011 a D49 7 00 No L2CACHE 9 IRQ7 6 LSDOQMO 6 LD9 8 050 0 0 256 2 MEL SDRAS 10K EXTOLI3 lt gt IRQ6 4 LSDCAS 4 A 5 108 9 5 D51 915 0 004 512 L2CACHE 1508455 3 sowe CZ 3 2 LWR 2 R16 TOOLREV2 2 RN51 2 TEST 1 LSDWE Hee l GND GND REO SDCFGDT AJK TOOLREV3 1 lt O SPARES 2 R LDi amp _ 065 ot LI RN34 353 10 53 3 SDCFGCK ATK TS LD17 2 TR D62 2 BREVO R19 2 904 A 1018 z D61 _ 3 of x ber co 10K LD19 060 x8 SAD RET LD20 6 lt aE 6 BREVI A 7 lt gt SA1 7 L2CFG1 10K TSTAT1 81 2 18217 088 7 6
138. LED 6 _ E _ v R27 ED_YELLOW 2 2 _ FAST ETHERNET PORT ENABLED 72120 RAVD 1 1 120 RAVD2 7 120 TAVD2 74 R28 E 1 E 1 gt T R145 1 PORSTO e 01uF 5 p 1UF ATMEN 3142 yo AZ LED YENLOW 180 _ 89232 PORT 1 ENABLED eir 971 971 eir 971 FETHEN _ 4 3 16 ne R22 T 193 C187 cT C192 u C184 5 4A4 15 5 5 cios cm2 5 RS EN2 elas 1514 LED YELLOW 5 415232 PORT 2 ENABLED 7 2 SCLAMPO 71 46 R20 7 pu yo Ro 12 LED CREE T 3 AB AU 4 GENERAL PURPOSE SIGNALING E D1 vec QAVD1 QAVD2 TAVD4 19 25 ou AR 1208 RAVOS U33 150 1 2 1942 KJ i5 _ RIO 1012 p 01UF 10uF 10UF lo o1UF o o1UF joo1uF 97 T T OTOROLA al E 8 er 2 181 519 eus lt PROJECT MPC8260ADS REV PILOT SHEET 10 OF 18 8 ENG YAIR LIEBMAN BLOCK POWER amp INDICATIONS GND NOT ASSEMBLED CHK DESCRIP 8 Da 9 K tmp_mnt net prince yair vayager ads pilot sch 11 drw 26 SEP 99 19 05 last update 26 SEP 99 12 09 A B D V3 3 C30 C29 C35 C36 C28 C34 C31 C33 C62 C65
139. LREV3 16 EXTOLIO I External Tool Identification 0 3 This lines should be driven by an external tool with the Tool Identification Code to be read via BCSR2 of EXTOLII the ADS These lines are pulled up on the ADS by 10 resistors See B18 EXTOLI2 also Table 4 11 BCSR2 Description on page 64 B19 EXTOLI3 B20 N C Not Connected B21 V3 3 3 3V Power Out These lines are connected to the main 3 3V plane of the MPC8260ADS this to provide 3 3V power where necessary for B22 external tool connected The amount of current allowed to be drawn from this power bus is found in Table 4 22 Off board Application B23 a 2 Maximum Current Consumption page 75 B24 B25 N C Not Connected 5 90 8260 PowerQUICC ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 5 7 P16 System Expansion Interconnect Signals Pin No Signal Name Attribute Description B26 5V Supply Connected to ADS s 5V VCC plane Provided as power supply for external tool For allowed current draw see Table 4 22 B27 Off board Application Maximum Current Consumption on page 28 23 29 B30 B31 B32 Cl GND Digital Ground Connected to main GND plane of the ADS C2 CLK8 Buffered System Clock This is a low skew buffered version of the MPC8260 s CLKIN signal to be
140. M SIZE 16M L2CACHE INH PON DEFAULT L2CACHE INHIBITED 5 116 8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc L2CACHE FLUSH PON DEFAULT L2CACHE FLUSHED L2CACHE LOCK PON DEFAULT L2CACHE LOCKED L2CACHE CLEAR PON DEFAULT L2CACHE CLEARED SIGNAL LAMPO PON DEFAULT SIGNAL LAMP SIGNAL PON DEFAULT SIGNAL LAMP 2 2K Data Bits Assignments Ca MOSES ICD SSSI IOSD ISIE IIASA PBI 01 DIMM SIZE Dl L2CACHE DATA BIT 2 2 FLUSH DATA BIT D3 L2CACHE LOCK DATA BIT D4 L2CACHE CLEAR DATA 05 SIGNAL LAMPO DATA D6 SIGNAL LAMPI DATA 27 R R k k ok ok BCSR 1 definitions k k k k k k kK k kk kkk 2k ok LIE _ 0 _ 0 FETH ENABLED 0 FETH RESET 0 RS232 1 ENABLE 0 RS232 2 ENABLE 0 Power On Defaults Assignments
141. MI NMIEn NMI B 0 O D NMIEn RstDeb1 fb amp AbrDeb1 fb only abort button depressed local data buffers enable equations SyncHardReset_B clk SYSCLK SyncHardReset_B ar 0 SyncHardReset_B ap 0 DSyncHardReset_B clk SYSCLK DSyncHardReset_B ar 0 DSyncHardReset_B ap 0 SyncHardReset_B HardReset_B DSyncHardReset_B SyncHardReset_B fb DataBufEn B oe H DataBufEn B FlashCs B covers also hard reset config BrdContRegCs_B AtmUniCsOut B provides data hold for write ToolCsl_B ToolCs2_B amp IBUFFER HOLD OFF ToolDataBufEn B oe ToolDataBufEn ToolCs1 B ToolCs2 B amp HOLD OFF local data buffers disable data contention protection MOTOROLA Chapter 5 Support Information For More Information On This Product Go to www freescale com 5 131 Freescale Semiconductor Inc Since with MPC8260 hard reset conf is read from flash during HRESET asserted and since these are all consequitive read cycles and since the cycles following hard reset are also reads b
142. Manual For More Information On This Product Go to www freescale com MOTOROLA sk k 3k gt k k k ok ok 3 H L X Z 1 0 X Z CDU C D U Signal groups 1 Add A27 A29 Data DO D7 ContReg PBI DimmSize L2Inh B L2Flush_B L2Lock_B L2Clear_B SignaLampO SignaLampl B AtmEn B AtmRst B FEthEn B FEthRst B RS232Enl B RS232En2 B JtagEn fb ReadBesr0 PBI DimmSize L2Inh B L2Flush B L2Lock B L2Clear B SignaLampO B SignaLampl B ReadBesr1 0 0 AtmEn B AtmRst_B fb FEthEn B FEthRst B fb RS232Enl B RS232En2 B ReadBesr3 0 0 MOTOROLA Freescale Semiconductor Inc Chapter 5 Support Information For More Information On This Product Go to www freescale com 5 113 Freescale Semiconductor Inc JtagEn fb DrivenContReg PBI DimmSize L2Inh B L2Flush B L2Lock B L2Clear B SignaLampO B SignaLampl B AtmEn B FEthEn B RS232Enl B RS232En2 ClockedContReg PBI DimmSize L2Inh B L2Flush B L2Lock B L2Clear B SignaLampO B SignaLampl B AtmEn B AtmRst B FEthEn B FEthRst B RS232Enl B RS232En2 B JtagEn
143. ON PON RESET amp SIGNAL LAMPI PON DEFAULT SIGNAL LAMP ON then SIGNAL LAMP ON else ISIGNAL LAMP MOTOROLA Chapter 5 Support Information 5 125 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc oe oe State Machines state diagram AtmEn B state ATM ENABLED if VGR WRITE BCSR 1 amp ENABLE DATA ENABLED amp RESET ENABLE PON DEFAULT ENABLED PON RESET amp ENABLE PON DEFAULT ENABLED then ENABLED else ATM ENABLED state ATM ENABLED if VGR WRITE BCSR 1 amp ATM ENABLE DATA BIT pin ATM ENABLED amp RESET ENABLE PON DEFAULT ENABLED PON RESET amp ATM ENABLE PON DEFAULT ATM ENABLED then ATM ENABLED else ENABLED state diagram AtmRst_B state ATM RESET ACTIVE if VGR WRITE BCSR 1 amp RESET DATA BIT pin ATM RESET ACTIVE amp IPON RESET RESET PON DEFAULT RESET PON RESET RESET PON DEFAULT ATM RESET then IATM RESET ACTIVE else ATM RESET state ATM RESET ACTIVE if VGR WRITE BCSR 1 am
144. PC2 12 FETHTXCK i me 12 6 PA3 ATMTXD6 13 gg 0 14 FETHRXD2 14 FETHRXCK 13410 14 PD19 PA4 5 16 mg 16 FETHRXD1 16 PC20 16 mg 16 2020 ATMTXD4 PBS 17 18 FETHRXDO PCB 1 18 ATMFCLK 17 18 PD21 ATMTXD3 195 20 FETHTXDO 20 22 19 20 022 7 2 7 21 22 FETHTXD1 PC7 1 22 PC23 07 21 1 22 023 ATMTXD 1 23 24 FETHTXD2 24 24 PD8 23 24 024 ATMTXDO Pag 25 26 FETHTXD3 FETHMDIO 26 PC25 26 26 28 ATMRXDO ATMRCA 27 442 28 FETHCRS ga 28 PC26 2010 27 28 RS CTS2 ATMRXD1 ATMRSOC PB11 29 30 FETHCOL PC11 30 PC27 PD11 29 30 RS TXD2 7 ATMRXD2 ATMRXEN 12 _ 31 peg 32 FETHRXER RS CD2 32 PC28 12 31 peg 32 RS_RXD2 7 ATMRXD3 ATMTSOC 2813 53 34 FETHTXEN PC13 34 PC29 2013 _ 335g 34 RS CIS1 4 14 35 3 36 FETHRXDV RS CD1 3 36 PC30 SDCFGCK 35 3 36 RS TXD1 5 37 38 FETHTXER PC15 38 PC31 SDCFGDT 37 mg pg 38 RS RXD L LSR __ L LSR L LSR MICTOR38 MICTOR38 MICTOR38 MICTOR38 PROJECT MPC8260ADS REV PILOT SHEET 14 OF 18 8 YAIR BLOCK CPM L A Coonectors CHK DESCRIP A B 3
145. PC8260 externally as well as internally it samples the Hard Reset configuration This configuration is taken from the current Hard Reset configuration source only over the MOTOROLA Chapter 4 Functional Description 4 43 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MS 8 bits of the data bus DO D7 whenever HRESET is asserted The only exception to this are the MOD 0 3 bits which are actually sampled only once after power on reset With this revision PILOT of the ADS Hard Reset configuration word may be sampled from two sources selected by 081 1 1 When DS1 1 is in the ON position the configuration word is taken from the Flash memory lo cated at its base address 2 When DS1 1 is in the OFF position the configuration word is taken from BCSR Unlike with the Flash memory this word may not be reprogrammed by the user as it is programmed into pro grammable logic This option allows convenient recovery when the Flash memory is inadvert ently erased with Hard Reset Configuration word lost For additional information see 2 3 3 Setting MODCK 1 3 for PLLs Multiplication Factor 051 6 8 on page 20 2 3 4 Setting Hard Reset Configuration Source on page 21 and 2 3 5 Setting MODCKH 0 3 for PLLs Multiplication Factors on page 22 During hard reset sequence the MPC8260 reads the Hard Reset configuration source at addresses 0 0 8 0x18 0 20 a byt
146. R 14 JTAG UPDATE IR 15 STATE JTAG RESET JtagState fb JTAG RESET STATE JTAG IDLE JtagState fb JTAG IDLE 5 120 8260 PowerQUICC II ADS User s Manual For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc STATE JTAG SELECT DR JtagState fb JTAG SELECT DR STATE JTAG CAPTURE DR JtagState fb JTAG CAPTURE DR STATE JTAG SHIFT DR JtagState fb SHIFT DR STATE JTAG DR JtagState fb JTAG DR STATE JTAG PAUSE DR JtagState fb JTAG PAUSE DR STATE JTAG EXIT2 DR JtagState fb EXIT2 DR STATE JTAG UPDATE DR JtagState fb JTAG UPDATE DR STATE JTAG SELECT IR JtagState fb JTAG SELECT 18 STATE JTAG CAPTURE JtagState fb CAPTURE STATE JTAG SHIFT IR JtagState fb JTAG SHIFT STATE JTAG IR JtagState fb STATE JTAG PAUSE IR JtagState fb PAUSE STATE JTAG EXIT2 IR JtagState fb EXIT2 STATE JTAG UPDATE IR JtagState fb UPDATE Instruction codes INST CODE BYPASS 7 INST CODE EXTEST 0 INST CODE DOWNLOAD 1 INST CODE UPLOAD 2 not supported for 1st implementaion INST CODE PON RESET 6 INST CODE UN IMPLEMENTED b011 b100 b101 NEXT INST BYPASS JtagShiftIR fb INST CODE BYPASS NEXT INST EXTEST JtagShiftIR
147. R7 For additional information on BCSR7 see Table 3 1 ADS 4 72 8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory on page 34 and Table 4 20 BCSR7 Description on page 68 4 13 1 5 Download Control and Status Register This register has no direct JTAG access however it enables the operation of this machine and contains status information set by this machine It is available on the PPC Bus memory map designated as BCSR6 For further information on BCSR6 see Table 3 1 ADS Memory Map on page 34 and Table 4 19 BCSR6 Description on page 68 4 13 1 6 Bypass Register The bypass register is a single stage register which must exist in any JTAG implementation Its purpose is to shorten the scan chain as much as possible for a device residing on the scan chain When the JIR contains the BYPASS code and the TAP controller is in Shift DR state this register is placed between TDI TDO pair of this machine Any unimplemented instruction with this machine defaults to the BYPASS instruction 4 13 1 7 JTAG Machine Bypass There are 3 levels of bypass for this JTAG implementation this to provide compatibility with earlier versions of this board and debug tools The bypass options are 1 2 3 Hard wired Bypass When J5 is between positions 2 3 then the TDI input to the VADS 15 connected directly to the TDI
148. READ FlashCs B 4 DSyncHardReset B fb amp ConfAdd 2 amp IHRESET IN FLASH BYTE READ FlashCs_ 4 DSyncHardReset B fb amp ConfAdd 3 amp Chapter 5 Support Information 5 119 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc IHRESET IN FLASH amp R ELLILLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLELLLLELLELLLLLLELLLLLLLLLLLLI JTAG LOGIC definitions R R signals groups JtagShiftDR JtagShiftDRO JtagShiftDR7 JtagC S Reg JtagEn fb 0 0 0 0 0 0 JtagReceiveFull fb JtagState JtagStateO JtagState3 JtagShiftIR JtagShiftIRO JtagShiftIR2 JtagIR JtagIRO JtagIR2 FallingTckSignals JtagResetState JtagShiftIrState JtagShiftDrState JtagTdoEnable Read BrdContRegCs B DVal B R W A27 A28 A29 for simulation only Constant definition JTAG RESET 0 JTAG_IDLE 1 JTAG SELECT DR 2 JTAG CAPTURE DR 3 JTAG SHIFT DR 4 DR 5 JTAG PAUSE DR 6 JTAG EXIT2 DR 7 JTAG UPDATE DR 8 JTAG SELECT IR 9 JTAG CAPTURE IR 10 JTAG SHIFT IR 11 JTAG IR 12 JTAG PAUSE IR 13 JTAG EXIT2 I
149. RMCS2 5 SPARE1 SEARE 575 F266 29 3 RN29 LSDRMCS e F27 RN48 5 22 4 SPARE4 CS5 PARES cse 1228 22 1 RN B 01 51 SPARE6 57_ 025 5 64 3 1001082 SPARE 1 SPARE 4 6 029 1 6455 MODCK 1 MDCK 1 TCO BKSLO cso E28 089 5 MDCK2 TC1 8KSL1 CS10 BCTL1 0BCDI 2 5 MOCK3 TC2 BKSL2 511 S28 N55 es cs 2 LA14 PAR WE 709 8320 zr RNB LA15 F RM_ SMI_ WE DOM BS 1 A H ENEA LA16 TRDY_ WE _ DQM BS_2 6 LA17 IRDY_ we 3 28 RM37 e223 DOM WES LA18 STOP_ _ _4 826 Em 437 LA19 DEVSEL_ WE_ DOM BS_6 Na s DES LA20 IDSEL_ WE _ DQM BS_6 s E o LA21 PERR we 85_7 25 ak 5 5 4 DOM WE LA22 SERR N38 LA23 REQ0 psoato cpo 23 7 22 2 SDRMA10 LA24 REQ1 PSDwE GpL1 824 _RN46 5 4 4 m POE SORAS GPL2 A24 8 RA 1 LA26 CNT1 PSDCAS cpL3 823 RNAG 6 22 3 SDCAS LA27 PCLK UPWT GPL4 225 5 55 4 46 PSDAMUX GPL6 022 RMSE S 4 LA29 INTA_ BCTL0_ 5 45 4 LA30 LOCK_ us LA31 PORST RESET AHS HRESET greseT AES SRESET A94 RSTCNF NN x I O J OY NNNNNNANNANN OOo Oooo
150. RN53 RN56 RN57 RN67 RN68 RN74 RN88 5 RN7 RN20 RN27 Resistor Network 43 5 4 DALE CRAO6S 08 03 430JRT RN80 RN81 RN82 RN83 RN84 resistors 8 pin RN85 RN86 RN87 RN14 RN16 RN17 RN19 RN24 Resistor Network 22 0 5 4 DALE CRA06S0803220JR RN29 RN36 RN37 RN38 RN39 resistors 8 pin RN45 RN46 RN47 RN48 RN49 RN50 54 55 RN58 59 RN60 RN61 RN62 RN63 RN64 RN65 RN66 RN69 RN70 RN71 RN72 RN73 RN75 RN76 77 RN78 RN79 5 104 8260 PowerQUICC ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 5 9 MPC8260ADSL2C Bill Of Material Reference Designation Part Description Manufacturer Part SWI SPDT push button RED Sealed C amp K KS12R22 CQE SW2 SPDT push button WHITE Sealed C amp K KS12R21 CQE SW3 SPDT push button BLACK Sealed KS12R23 CQE Tl Transistor Dual TMOS VT 2V Motorola MMDF3N02HD TRI Trimmer Pot 1 KQ Single Turn BOURNS 3362P 1 102 Ul Fiber Optic I F Module 1300 nm HP HFBR 5205 wavelength 2 Km Range U2 US 3 3V Powered Single Supply RS232 Motorola MC145583V Transceiver 3 Tx 5 Rx U3 10 100 Base T Filter network HALO TG22 3506ND U4 Saturn User Network I F S UNI for PMC Sierra Inc 5350 155 52 amp 51 84 Mbps 128 06 Clock Generator 19 44 MHz 20
151. Reserved ur No L2 Cache BCSR3 to BCSRS are additional control status registers which may be accessed as a word at offset 0xC to 0x14 from BCSR base address These registers are not implemented They may be read or written but with no valid data nor any effect on the ADS The description of BCSR3 to BCSRS is shown in Table 4 18 BCSR3 to BCSRS Description below Table 4 18 BCSR3 to BCSR5 Description 5 Function DEF ATT 0 31 Reserved Un Implemented Chapter 4 Functional Description 4 67 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 4 12 5 BCSR6 Board Control Status Register 6 BCSR 6 is used for the JTAG Fast Download I F Status amp Control Although it resides only over D 0 7 lines of the PPC data bus it is accessed as a word at offset 0x18 from BCSR base For additional information on that I F see 4 13 1 Fast Download Support on page 69 The description of BCSR6 is shown in Table 4 19 BCSR6 Description below Table 4 19 BCSR6 Description PON BIT MNEMONIC Function DEF ATT 0 JTAG EN JTAG Enable When this bit is active High the JTAG machine for fast download 0 R W is enabled for use When inactive TDI is asynchronously driven to MTDO In this mode Power On default COP controller S W may operate on the ADS in ENG re
152. ResetState istype reg buffer sampling state on falling JtagShiftIrState NODE istype reg buffer sampling state on falling JtagShiftDrState NODE istype reg buffer sampling state on falling JtagTdoEnable istype reg buffer sampling state on falling JtagShiftIRO NODE istype reg buffer JtagShiftIR1 NODE istype reg buffer JtagShiftIR2 NODE istype reg buffer JtagIRO istype reg buffer JtagIR1 istype reg buffer JtagIR2 istype reg buffer Jtag Inst Shift register Jtag Inst register JtagReceiveFull JtagReceiveFullReset NODE istype com NODE istype reg buffer indicates receive shift reg ready for read by memory cont resets the receive full flag SReadJtagDownloadData NODE istype reg buffer JtagStateReset istype jtag state machine only JtagReset NODE istype com global reset TdoEnable NODE istype com enables the muxed TdoOut Misceleneous LIE KeepPinsConnected istype com Constant Declaration 5 112 MPC8260 PowerQUICC II ADS User s
153. SABLED 1 BUFFER ENABLED BUFFER DISABLED BUFFER HOLD OFF HoldOffCnt fb 0 the delay is required for read as well since a fast device eg besr may content with the flash END OF FLASH READ DVal B amp FlashCs B amp B amp DSyncHardReset B fb end of flash read cycle not during hard reset config END READ DVal amp AtmUniCsIn B amp R B end of atm uni m p i f read cycle END OF OTHER CYCLE DVal B amp FlashCs B amp AtmUniCsIn B another access B amp AtmUniCsIn B amp R B W atm write IDVal amp ToolCs1 B amp B W tool 1 write IDVal amp ToolCs2 B amp tool 2 write IDVal amp FlashCs B amp flash write Hard Reset Configuration Logic I HRESET IN FLASH FlashConfEn B 0 HARD RESET ASSERTION HardReset B 0 amp SyncHardReset B fb 0 amp DSyncHardReset 1 50 ASSERTED FlashCs B 0 FIRST BYTE READ FlashCs amp DSyncHardReset B fb amp ConfAdd 0 amp IHRESET IN FLASH amp SCND BYTE READ B amp DSyncHardReset B fb amp ConfAdd 1 4 IHRESET IN FLASH THIRD BYTE
154. SET line may be driven internally by the MPC8260 it is driven to the MPC8260 with an open drain gate If off board H W connected to the ADS is to drive HRESET line then it should do so with an open drain gate this to avoid contention over this line To save on board area a dedicated button is not provided but is shared with the Soft Reset button and the ABORT button when both depressed Hard Reset is generated 4 1 2 3 Internal Sources Hard Reset The MPC8260 has internal sources which generate Hard Reset Among these sources are 1 Loss of Lock Reset When one of the PLLs Core CPM is out of lock hard reset is generated 2 5 Reset When the core enters Check Stop state from some reason hard reset may be generated depended on CSRE bit in the RMR 3 Bus Monitor Reset When the bus monitor is enabled and a bus cycle is not terminated hard reset is generated 4 S W Watch Dog Reset When the S W watch dog is enabled and application s w fails to perform its reset routine it will generate hard reset 5 COP JTAG Reset Internal Hard reset may be forced by driving the HRESET line via the ex ternal pin s scan chain Not useful for run time In general the MPC8260 asserts a reset line HARD or SOFT for a period 512 clock cycles after a reset source has been identified A hard reset sequence is followed by a soft reset sequence 4 1 2 4 Hard Rest Configuration When Hard Reset is applied to the M
155. SISIS Nee 1805 ERR 5 5 m aa 444294 9944 3949 3934 48945 44585 M3 s d o ANG CLK wa 2 M og c d awa No d cy C3 00 wel X 1 01 V6 5 2 02 DH2 03 A4 DH3 D4 AS 05 V4 us A6 D6 w3 7 07 v3 DH7 Q 08 wio A9 ua 09 9 0 018 US A11 011 9 12 012 13 013 DHi2 S 14 DHi3 i 014 Ue oy 14 D15 A16 016 87 A17 017 6 A18 DH17 018 19 014 5 20 0H19 D20 4 A21 021 B5 22 DH21 71 A 022 C6 23 0H22 lt gt 223 023 84155 024 10 A25 0H24 025 B10 26 DH25 026 10 27 DH26 A 027 49 28 0H27 028 B9 29 DH28 A D29 A8 30 DH29 5 A31 D30 B8 S Q D3t uzi S i APO 052 10 gt 019 2 055 2 034 w11 012 055 apr 819 L2APE 056 01111 E18 L2APEN 037 12 5 APEN 038 V12 F18 TSI Dsg wig 029 Tsizo 18 TSIZE T 017 17 TSIZE2 040 W14 S121 TSIZES 041 w15 TSIZ2 DL9 042 1410 043 16 0111 n 044 15 T DL12 045 17 2 0115 046 16 3 0114 047 v17 048 049 B11 TDI 0117 051 A12 pi1g TDO D52 8121724 TMS D53 612 21 TRST C22 054 3 055 813 123 0 1 056 14 24 Cia 0
156. SYN CPM PLL SSoSSN8s2 CLK1 z5925 580 CLKIN VCCSYN1 CORE PLL 60299859 LOP C BE LDP C BE1 OREO aor eas LOP C BE2 TRST s 6866690999 TRST_ 98 LDP C BE S TMS AJ3 TMS TCK AGE 028 522 4 LWRT s s LSOWE_ CPL1 Mit ra 5 NIS LOE SDRAS GPL2 E26 5 52 4 LSDRAS 3 BR 4 6 BR is reserved for slave Voyager or external CPU LSDCAS_ GPL3 026 RN5O LSDCAS 80 EX RN B Fala L2CACHE XBR2 c26 RNBO LOTA AEE N54 3 77 6 m ABB IRO2 LSDAMUX GPL5 827 4 10565 Dac 52 4 RN36 z s LT THEFT 1 aea s 088 IF03 R CPUBG E em 04 83 2 629 RNG1 1 LSDDQM3 5 lt CPUBG_ BADD31 LWE _ DQM 8S_3 CPUDBG 6 22 3 9 2 S AACK RN54 8 22 1 F3laack ALE 12 4 23 5 ALE ARETRY 2 RN54 E1 ARTRY TS ES 4 RN54 74 TA N362 227 02 07 05 RN36 22 1 4 Bu 442 RN45 V3 348 RN36 2 CI 8AD029 1RQ2 U2 N581 tp BG 2 7 12 4 J190 T S NMI_OUT_ WT 8ADD30 1RO3 US 1632 77 1 ue TRQ7 INTOUT A TRIS 25 __7 22 2 THERMO C29 RN B 22 1 BCSRCS TRM1 52 27 6 RN49 SDRMCS1 0 1 MPC8260 cez 28 RN39 5 4 4__SD
157. Table 4 22 Off board Application Maximum Current Consumption Power Bus Max Current VCC 2A V3 3 1 5A As can be seen from Figure 4 10 ADS Power Scheme above VPP may be provided also from the ex pansion connectors This option 15 provided for production testing To protect on board devices against supply spikes decoupling capacitors typically 0 1uF are provided between the devices power leads and GND located as close as possible to the power leads while 47 uF bulk capacitors are spread around MOTOROLA Chapter 4 Functional Description For More Information On This Product Go to www freescale com 4 75 Freescale Semiconductor Inc 4 14 1 5V Bus Some of the ADS peripherals reside on the 5V bus Since the MPC8260 is not 5V tolerant buffering is provided between 5 peripherals and the MPC8260 protecting the MPC8260 from the higher voltage level The 5V bus is connected to an external power connector via a fuse 5A To protect against reverse voltage or over voltage being applied to the 5V inputs a set of high current diodes and zener diode is connected between the 5V bus GND When either over or reverse voltage is applied to the ADS the protection logic blows the fuse while limiting the momentary effects on board 4 14 2 3 3V Bus The MPC8260 the SDRAMs the address and data buffers are powered by the 3 3 bus which is produced from the 5 bus using a low voltage drop
158. able respective function Bll ATMTXD4 PA21 B12 5 20 B13 ATMTXD6 PA19 B14 7 PA18 B15 ATMRXD7 PA17 T S ATM Receive Data 72 0 When the ATM port is enabled this bus carries the cell octets read from the PM5350 receive FIFO This lines 16 ATMRXD6 16 are updated the rising edge ATMRFCLK B17 ATMRXDS PA15 When the ATM port is disabled these lines are tristated and may be used for any available respective function B18 ATMRXD4 PA14 B19 ATMRXD3 13 B20 2 12 B21 ATMRXD PA11 B22 ATMRXDO 10 5 82 MPC8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 5 4 P4 CPM Expansion Interconnect Signals Pin No Signal Name Attribute Description B23 PAY T S 8260 Port A 9 0 Parallel I O or dedicated CPM lines be used for any of their available functions B24 PA8 B25 PA7 B26 PA6 B27 PAS B28 4 29 B30 PA2 B31 B32 PAO Cl FETHTXER PB31 T S Fast Ethernet Transmit Error H When the Ethernet port is enabled this signal will be asserted High by the MPC8260 when an error is discovered in the transmit data stream When the port is operation at 100 Mbps the LXT970 responds by sending invalid code symbols on the
159. allows total flexibility in selecting desired MODCK When MODCKH 0 3 are set to this value 5 and MODCK 1 3 101 both CPM and Core MFs are set to 2 When MODCK 1 3 111 CPM s MF is set to 2 while Core s MF is set to 3 lFor L2 Cache Boards Was 00 with ENG version of this board In fact not significant with this application since the only possible master the L2 Cache wakes up disabled 4DP7 is also set as IRQ7 They are logic OR ed into the interrupt controller gt Applies only ONCE after Power On reset Programmed into Flash and Factory Set for DS1 2 5 MOTOROLA Chapter 4 Functional Description 4 45 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 4 1 3 Soft Reset Soft Reset may be generated on the ADS from the below sources 1 COP JTAG Port 2 Manual Soft Reset 3 Internal MPC8260 source Soft Reset when generated causes the MPC8260 to reset its internal logic while keeping its hard reset con figuration and memory controller setup and then jumping to the Reset vector in the exception table Since soft reset does not reset the refresh logic for dynamic RAMs their contents is preserved SRESET when asserted is extended internally by the MPC8260 for an additional 512 bus clock cycles at the end of which the MPC8260 waits for 16 bus clock cycles and then re checks the state of the SRESET line SRESET is an ope
160. any time BCSRI gets its defaults upon Power On reset BCSR1 fields are described in Table 4 10 BCSRI Descrip tion below MOTOROLA Chapter 4 Functional Description 4 63 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 4 10 BCSR1 Description BIT MNEMONIC Function ida ATT 0 1 Reserved Un implemented 2 ATM_EN ATM Port Enable When asserted low the ATM UNI chip PM5350 connected to 1 R W is enabled for transmission and reception When negated the ATM transceiver is in fact in standby mode and its associated buffers are in tri state mode freeing all its 1 signals for off board use via the expansion connectors 3 ATM_RST ATM Port Reset When asserted low the ATM port transceiver is in reset state 1 R W This line is driven also by HRESET signal of the MPC8260 4 FETHIEN Fast Ethernet Port Initial Enable When asserted low the LXT970 s MII port 1 R W residing on FCC2 is enabled after Power Up or after FETH_RST is negated When negated high the LXT970 s MII port is isolated after Power Up or after FETH RST is negated and all i f signals are tri stated After initial value has been set this signal has no influence over the LXT970 and MII isolation may be controlled via MDIO 0 10 bit 5 RST Fast Ethernet port Reset When active low the LXT970is reset This line is also 1 R W driven by HRESET signal of the MP
161. are described to their design details 4 1 Reset amp Reset Configuration There are several reset levels for the MPC8260 all of which are provided by ADS logic 1 Power On Reset 2 Hard Reset 3 Soft Reset 4 1 1 Power On Reset The power on reset to the MPC8260 initializes the processor state after power up There are 3 sources for power on reset on the ADS 1 dedicated logic using Seiko S 80728AN DR T1 which is a voltage detector of 2 8V 2 4 asserts input to the MPC8260 for a period of 2 5 sec This time period is long enough to allow for VDDL stabilization time powered by a different voltage regulator It is as sumed that the stabilization time for both linear regulators see Figure 4 10 ADS Power Scheme on page 75 is about the same 2 Power On Reset may be generated manually as well by a dedicated push button SW1 when de pressed simulates a power up state for the above voltage detector 3 With this revision Power On reset may also be generated by the logic which is integrated with BCSR See 4 13 2 JTAG Generated Power On Reset on page 74 4 1 1 1 Power On Reset Configuration At the end of the Power On reset sequence MODCK 1 3 and MODCKH 0 3 are sampled by the MPC8260 to configure the various clock modes of MPC8260 core bus etc Selection among the MODCK 1 3 combination options is done by means of 3 dip switches DS1 6 8 see 2 3 3 Setting MODCK
162. atus report The exact R meaning of each bit within this field is tool unique and therefore will be documented separately per each tool These signals are available at the System expansion connector P16 4 64 MPC8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 4 11 BCSR2 Description MNEMONIC Function PON DEF ATT TOOLREV 0 3 TOOL Revision 0 3 This field may contains the revision code of an external tool connected to the ADS The various combinations of this field will be described per each tool user s manual These signals are available at the System expansion connector P16 12 15 EXTTOLI 0 3 External Tools Identification These lines which are available at the CPM expansion connectors are intended to serve as tools identifier On board S W may check these lines to detect The presence of various tools h w expansions at the CPM expansion connectors For the external tools codes and their associated combinations see Table 4 14 EXTOOLI 0 3 Assignment on page 66 16 17 SWOPT 0 1 Software Option 0 1 This field shows the state of a dedicated dip switches DS3 1 2 providing an option to manually change a program flow 18 19 L2CSIZE 0 1 L2 Cache Size 0 1 This field encodes the size of the L2 Cache present on the ADS For the encoding of the
163. aximum Current Consumption Table 5 1 P1 Ethernet Port Interconnect Signals 5 2 uP2 s Interconnect eti Table 5 3 Interconnect Signals Table 5 4 CPM Expansion Interconnect Signals Table 5 5 P5 JTAG Connector Interconnect Signals Table 5 6 P11 ISP Connector Interconnect Signals Table 5 7 P16 System Expansion Interconnect Signals Table 5 8 MPC8260ADS Bill Of Material uie reatu ts 5 9 MPC8260ADSL2C Of Material MOTOROLA Tables For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table Page Number Title Number x MPC8260 PowerQUICC ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 1 General Information 1 1 Introduction This document is an operation guide for the MPC8260ADS board It contains operational functional and general information about the MPC8260ADS This board is meant to serve as a platform for s w and h w development around the MPC8260 processor Using its on board resources and a debugge
164. condition is detected on the 10 100 Base T port 1 simultaneous receive and transmit This led functions in this duty provided that bits 7 6 of LXT970 s register 19 are cleared 3 2 23 Indication LD8 The green VDDL indicator led LD8 is lit to indicate VDDL power activity Since level may vary LDS s illumination level also varies accordingly 3 2 24 3 3V Indicator LD9 The green 3 3V led LD9 indicates the presence of the 3 3V supply on the ADS 3 2 25 RUN Indicator 1010 When the green RUN led LD10 is lit it indicates that the MPC8260 is performing cycles on the PPC Bus When dark the MPC8260 is either running internally or stuck 3 2 26 General Purpose Indicator 0 LD11 This green indication led has no dedicated function over the ADS It is meant to provide some visibility for program behavior It is controlled by BCSRO 3 2 27 General Purpose Indicator LD12 This red indication led has no dedicated function over the ADS It is meant to provide additional visibility for program behavior Its different color from LD11 provides additional information It is controlled by BCSRO 3 2 28 Fast Ethernet Port Initially Enabled LD13 When the yellow ETH ON led is lit it indicates that the fast ethernet port transceiver the LXT970 is initially active When it is dark it indicates that the LXT970 is initially in power down mode enabling the use of its associated FCC2 pins off board via
165. ct Go to www freescale com Freescale Semiconductor Inc Table 5 4 P4 CPM Expansion Interconnect Signals Pin No Signal Name Attribute Description BS ATMRSOC PA27 T S ATM Receive Start Of Cell H When this signal is asserted High while the ATM port is enabled it indicates that the 1 st octet of data for the received cell is available at the PM5350 s ATMRXD 7 0 lines This line is updated over the rising edge of ATMRFCLK When the ATM port is disabled this line is tristated and may be used for any available function for PA27 26 T S Receive Cell Available When this signal is asserted High while the ATM port is enabled and ATMRFCLK goes high it indicates that the PM5350 s receive FIFO is either full or that there are 4 empty bytes left in it PM5350 internal programming dependent When the ATM port is disabled this line is tristated and may be used for any available function of PA26 B7 ATMTXDO PA25 T S Transmit Data 13 0 When the ATM port is enabled this bus carries the ATM cell octets written to the PM5350 s transmit FIFO This B8 ATMTXDI bus is considered valid only when ATMTXEN is asserted and are sampled on the rising edge of ATMTFCLK B ATMTXD2 PA23 2 When the ATM port is disabled these lines may be used for any B10 ATMTXD3 PA22 avail
166. d on the ADS by the following sources 1 COP JTAG Port 2 Manual Hard reset 3 MPC8260 s internal sources Hard Reset when generated causes the MPC8260 to reset all its internal hardware except for PLL logic re acquires the Hard reset configuration from its current source and jumps to the Reset vector in the exception table Since hard reset resets also the refresh logic for dynamic RAMs their content is lost as well HRESET when asserted is extended internally by the MPC8260 for additional 512 bus clock cycles at the end of which the MPC8260 waits for 16 bus clock cycles and then re checks the state of the HRESET line HRESET is an open drain signal and must be driven with an open drain gate by which ever external source is driving it Otherwise contention will occur over that line which might cause permanent damage to either ADS logic and or to the MPC8260 itself 4 1 2 1 COP JTAG Port Hard Reset To provide convenient hard reset capability for a COP JTAG controller HRESET line appears at the COP JTAG port connector 5 COP JTAG controller may directly generate hard reset by asserting low this line 4 1 2 2 Manual Hard Reset Manual hard reset allows run time Hard reset when the COP controller is disconnected from the ADS and to support resident debuggers Depressing both Soft Reset and ABORT buttons SW3 amp SW2 asserts the HRESET pin of the MPC8260 generating a HARD RESET sequence Since HRE
167. d to MPC8260 s A28 and so on The SDRAM machine one of the MPC8260 needs to be initialized as well this after BCSR2 is read to find out whether a L2 cache is present on board The programming of the SDRAM machine 1 is shown in Table 3 4 Memory Controller Initializations For 66Mhz on page 38 4 7 2 SDRAM Refresh The SDRAM is refreshed using its auto refresh mode using SDRAM machine one s periodic timer an auto refresh command is issued to the SDRAM every 13 4 usec so that all 2048 SDRAM DIMM rows refreshed within specified 32 8 msec while leaving an interval of 5 4 msec of refresh redundancy within that window as a safety measure to cover for possible delays in bus availability for the refresh controller 4 52 8260 PowerQUICC II ADS User s Manual fact each SDRAM component is composed of 2 internal banks each having 2048 rows but they refreshed in parallel For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc 4 7 3 L2 Cache Support Influence On SDRAM Design To support an optional L2 Cache on the ADS the following measures are taken 1 Optional Latch Multiplexers are added over selected address lines See Figure 4 2 SDRAM DIMM Connection Scheme on page 50 These latch mux are normally bypassed by zero ohm resistors that are not assembled for L2 Cache boards 2 MPC8260 supports additional wait state on PSDMUX li
168. devices each containing 256 KBytes of look aside cache along with its control providing a total of 512 KBytes of L2 cache The cache is connected directly over the 60X bus and is supported gluelessly by the MPC8260 The cache data sheet may be obtained via the internet at URL http mot sps com books dl156 pdf mpc2605rev5 pdf The presence of the L2 Cache calls for the introduction of latch multiplexers over SDRAM s address lines this since the MPC2605 snooping logic needs to monitor the address as is linear rather than multiplexed and the bus works by the 60X bus protocol allowing address pipelining These latch multiplexers are soldered in place only in case a cache is installed on board Otherwise they are omitted and bypassed by zero ohm resistors See also 4 7 3 L2 Cache Support Influence On SDRAM Design on page 53 MOTOROLA fact each SDRAM component is composed of 2 internal banks each having 2048 rows but they refreshed in parallel 2Le residing on the same bus as the processor 3 Only single level is allowed with the 8260 Chapter 4 Functional Description For More Information On This Product Go to www freescale com 4 57 Freescale Semiconductor Inc 4 10 1 L2 Cache Configuration amp Control The cache is configured via 5 configuration lines CFG 0 4 for the following functions 1 Cache size is set by CFG 0 2 The various settings of these lines per each cache module are en
169. e Flash SIMM Table 5 2 P2 Interconnect Signals Pin Number Signal Name Description 1 12V 12V input from external power supply 2 GND GND line from external power supply 5 1 3 PB3 5232 Ports Connectors The RS232 ports connectors PA3 and PB3 are 9 pin 90 female D Type Stacked connectors signals of which are presented in Table 5 3 PA3 PB3 Interconnect Signals below Table 5 3 PA3 PB3 Interconnect Signals Pin No Signal Name Description 1 CD Carrier Detect output from the MPC8260ADS 2 TX Transmit Data output from the MPC8260ADS 3 RX Receive Data input to the MPC8260ADS 4 DTR Data Terminal Ready input to the MPC8260ADS 5 GND Ground signal of the MPC8260ADS 6 DSR Data Set Ready output from the MPC8260ADS 7 N C No connect 8 CTS Clear To Send output from the MPC8260ADS 9 N C No connect Refer to 4 11 3 RS232 Ports on page 60 5 1 4 MPC8260ADS s P4 CPM Expansion Connector P4 is a 128 pin 90 DIN 41612 connector which allows for convenient expansion of the MPC8260 s serial ports This connector contains all CPM pins plus power supply pins to provide for easy tool connection The pinout of is shown in Table 5 4 CPM Expansion Interconnect Signals below Table 5 4 P4 CPM Expansion Interconnect Signals Pin No Signal Name Attribute Description Al RS RXDI PD31 T S When 52
170. e PMC SIERA 5350 10 100 Base T Port on FCC2 with T P I F controlled using Level One LXT970 Dual RS232 port residing on SCC1 amp SCC2 Module disable 1 low power mode option for all communication transceivers BCSR controlled enabling use of communication ports off board via expansion connectors Dedicated MPC8260 s communication ports expansion connectors for convenient tools connection carrying also necessary bus signals for transceivers M P I F connection Use is done with 2 X 128 pin DIN 41612 receptacle connectors The DIMM is unbuffered from the 60X bus and therefore should consume as small capacitive drive power as possible 2BCSR controlled for 60X Bus mode MOTOROLA Chapter 1 General Information For More Information On This Product Go to www freescale com Freescale Semiconductor Inc o External Tools Identification amp status read Capability via BCSR Power On Reset Push Button o Soft Hard Reset Push Button o ABORT Push Button Single 5V Supply o Reverse Over Voltage Protection for Power Inputs o Multi Range MPC8260 Internal Logic supply Ranges include 1 7V to 1 9V 1 8V to 2 0V and 2 3V 2 7V currently changeable within a range o Software Option Switch provides 8 S W options via BCSR 1 6 Revision Engineering ENG to Revision PILOT Changes This section describes only the functional changes between the above revisions It does not c
171. e Size 04500000 BCSR 0 7 2 32 04507FFF 04500000 BCSR0 04507FE3 04500004 BCSRI 04507FE7 04500008 BCSR2 04507FEB 0450000 BCSR3 04507FEF 04500010 BCSR4 04507FF3 04500014 BCSR5 04507FF7 04500018 BCSR6 04507FFB 0450001C BCSR7 04507FFF 04508000 Empty Space 045 04600000 Proc 5350 I F 8 04607 Control 04608000 Empty Space 046FFFFF 047000004 MPC8260 32 0470FFFF Internal 04710000 Empty Space FCFFFFFF FE000000 Flash SIMM 32M SIMM 32 FEFFFFFF SM73288 FF000000 16M SIMM FF7FFFFF SM73248 FF800000 8 SIMM FFFFFFFF SM73228 Local bus is fully transparent to the 60X bus 1 no mapping register If a CS 15 5 signed to the Local bus its address space is completely visible to the 60X bus gt The device appears repeatedly in multiples of its port size in bytes X depth E g BCSRO appears at memory locations 4700000 4700010 4700020 while BCSR1 appears at 4700004 4700014 4700024 and so on The internal space of the ATM UNI control port is 256 bytes however the minimal block size that may be controlled by a CS region is 32K Bytes Initially at 00000 hFOOOFFFF set by hard reset configuration MOTOROLA Chapter 3 Operating Instructions 3 35 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Refer to the MPC8260 User
172. e Vs TRI s rotation direction is shown in Figure 2 3 VDDL Trimmer TRI below MOTOROLA Chapter 2 Hardware Preparation and Installation 2 19 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc LOW Figure 2 3 VDDL Trimmer TR1 TRI HIGH Note On ENG boards VDDL level changed in opposite direc tion regarding spin 1 it increases CCW and creases CW WARNING While in higher ranges of VDDL and higher ranges of in ternal operation frequencies the MPC8260 might require some sort of COOLING measures to be taken Failure in doing so might result in PERMANENT DAMAGE in flicted to the MPC8260 2 3 3 Setting MODCK 1 3 for PLLs Multiplication Factor DS1 6 8 After 1K cycles the negation of the Power On Reset signal the MPC8260 samples the 7 MODCK lines the lower 3 on MODCK 1 3 and the upper four MODCKH 0 3 field is read from the Hard Reset con figuration source to establish the multiplication factors of the CPM s and Core s PLLs The levels on MODCK 1 3 lines are set using DS1 switches 6 8 When an individual switch is at the OFF position its associated MODCK line is pulled high 1 while when at the ON position the associated MODCK is pulled down 0 DS1 is shown in Figure 2 4 051 Description on page 21 while the various combina tions for DS1 6 8 and their associated 1 3 values are sho
173. e applied by ADS logic to the MPC8260 via its interrupt controller 1 ABORT NMI 2 ATM interrupt 3 Fast Ethernet PHY Interrupt 4 2 1 ABORT Interrupt The ABORT is generated by a push button When this button is depressed the IRQO input to the MPC8260 is asserted The purpose of this type of interrupt is to support the use of resident debuggers if any is made available to the ADS This interrupt is enabled by setting the MSR EE bit To support external off board generation of an NMI the IRQO line is driven by an open drain gate This allows for external h w to also drive this line If external h w indeed does drive IRQO it is compulsory that 4 46 MPC8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc IRQO is driven by an open drain gate 4 2 2 ATM UNI Interrupt To support ATM UNI User Network I F event report by means of interrupt the interrupt output of the UNI INTB is connected to IRQ6 line of the MPC8260 Since INTB of the UNI is an open drain output it is possible to connect additional off board interrupt re questers on the same IRQ6 provided that they drive IRQ6 with an open drain gate as well 4 2 3 Fast Ethernet Transceiver Interrupt To support Fast Ethernet Transceiver event report by means of interrupt the FDS MDINT interrupt output of the LXT970A is connected to IRQ7 line of the MPC8260
174. e devices to the MPC8260 via the CPM expansion connectors residing on the edge of the board The communication ports interfaces provided on the ADS are listed below 1 155 Mbps UNI on with Optical I f connected via UTOPIA I F 2 10 100 Port FCC2 controlled 3 Dual RS232 port residing on 5 amp SCC2 4 11 1 ATM Port To support the MPC8260 s ATM controller a 155 52Mbps User Network Interface UNI is provided on board connected to FCC1 of the MPC8260 via the UTOPIA I F This is implemented with 5350 S UNI 155 ULTRA by PMC SIERA Although these transceivers are capable of supporting 51 84Mbps rate lFor minimum 8 Bus clock cycles 4 58 MPC8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc support is given only to the higher rate The control over the transceiver is done using the microprocessor i f of the transceiver controlled by the MPC8260 memory controller s GPCM Since the UNI is 5V powered and the MPC8260 3 3V powered 5V intolerant the UNI is buffered LCX buffers from the MPC8260 on both the receive part of UTOPIA I F and the microprocessor control ports The ATM transceiver may be enabled disabled at any time by writing 0 I to the ATMEN bit in BCSRI When ATMEN is negated 1 the microprocessor control port remains accessible on MPC8260 memor
175. e each time to assemble the 32 bit configuration word A total of 32 bytes of data 15 read from D 0 7 to acquire 8 full configuration words for system that may have up to 8 MPC8260 chips The configuration word for a single 8260 is stored in the Flash memory SIMM and in BCSR while the other 7 words are not initialized as there are no additional MPC8260 chips on this ADS Table 4 1 Hard Reset Configuration Word Data Prog m Offset In Value Field Bus Bit Value Implication Flash Hex mses Bin Hex ERB 0 0 Internal Arbitration Selected 0 1 0 Internal Memory Controller CSO active at system boot CDIS 2 70 Core Enabled EBM 3 0 P 0 sets Single MPC8260 Mode for regular ADS boards 1 sets 60X Bus Mode for boards with L2 Cache assembled L2 or L2C suffix BPS 4 5 ur Sets 32 Bit Boot Port Size CIP 6 0 Sets Core Initial Prefix MSR IP 1 so that the system exception table is placed at address OxFFF00100 regardless of Flash memory size ISPS 7 70 64 bit internal space for external master access fact don t care on this board as neither an external master is present with regular ADS boards nor the internal space of the MPC8260 is non cached with L2 cache boards l Although the MPC8260 as configuration master reads 8 configuration words only the first configuration word is influential 4 44 MPC8260 PowerQUICC II
176. ed L1 L2 L3 L4 L5 L6 L7 Ferrite Bid Fair rite 2743021447 LD1 LD2 LD3 LD4 LD8 LD9 LD10 Led Green SMD SIEMENS 670 LDII LD5 LD6 LD13 LD14 1015 LD16 Led Yellow SMD SIEMENS LY 670 1071012 SIEMENS LS 670 Pl Connector 8 pin RJ45 Receptacle MOLEX 43202 8110 Shielded 90 P2 Connector 2 pin Power Straight WB 81135 253303253 with false insertion protection Connector 2 pin Power Plug WB 8113B 253200253 PA3 PB3 Connector 2 X 9 pin Stacked EDA Inc 8LE 009 009 D 3 06H Female DType 90 P4 P16 Connector 128 pin Female DIN ERNI ERNI 043326 41612 909 P5 Connector header 16 pin Male T H ALPHA FCC 301 16 90 With Latches P6 P7 P8 P9 P10 P12 P13 P14 Connector MICTOR 38 pin SMD AMP 2 767004 2 P15 P17 P18 5 102 MPC8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 5 9 MPC8260ADSL2C Bill Of Material Reference Designation Part Description Manufacturer Part Pll Connector header 10 pin dual in SAMTEC TSM 105 03 S DV line SMD P19 Connector 3 pin Power Straight WB 81135 253303353 with false insertion protection Connector 3 pin Power Plug WB 8113B 253200353 R2 R4 R124 R139 R140 Resistor 51 1 Q 1 SMD 0603 RODERSTEIN D11 51R1FCS R148 R149 R151 R152 R153 0 1W R3 R1
177. ed Interleaving Refresh enabled normal operation code address muxing mode 2 19 on BNKSEL2 8 on 10 7 clocks refresh recovery 3 clocks precharge to activate delay 2 clocks activate to read write delay 4 beat burst length 1 clock last data out to precharge 1 clock write recovery time no extra cycle on address phase normal timing for control lines 2 clocks CAS latency SDC8UV6484C 84 412EB452 Bank Based Interleaving Refresh enabled normal 64 MByte operation code address muxing mode 1 A 13 15 on BNKSEL 0 2 9 PSDA10 7 clocks refresh recovery 3 clocks precharge to activate delay 2 clocks activate to read write delay 4 beat burst length 1 clock last data out to precharge 1 clock write recovery time no extra cycle on address phase normal timing for control lines 2 clocks CAS latency C372B452 Page Based Interleaving Refresh enabled normal operation code address muxing mode 2 A 16 17 on BNKSEL 1 2 on PSDA10 7 clocks refresh recovery 3 clocks precharge to activate delay 2 clocks activate to read write delay 4 beat burst length 1 clock last data out to precharge 1 clock write recovery time no extra cycle on address phase normal timing for control lines 2 clocks CAS latency MOTOROLA Chapter 3 Operating Instructions 3 39 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 3 4 Memory Controller In
178. else when COL amp SDRAM PBI amp SDRAM 16M then SdramAdd ColAddPBI 16M q else when COL amp SDRAM PBI amp SDRAM 64M then SdramAdd ColAddPBI 64M q END 5 146 MPC8260 PowerQUICC ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 6 Schematics 6 1 Introduction This chapter shows the schematics for the 8260 ADS board MOTOROLA Chapter 6 Schematics 6 147 For More Information On This Product Go to www freescale com net princ e yoir voyo ger ods pilot sc h 1 drw 26 SEP 99 19 00 lost updote 21 SEP 99 18 42 A B C 0 G K L N 1288 128 1 120867 1 9 XBR3 XDBG3 VCCSYN 1 x 0 0 xem o s e 4 0 0 x 0 0 9 x m
179. erefore the slower devices on the bus 1 the Flash Simm the BCSR and the ATM UNI M P i f are buffered removing their capacitive load from the PPC bus while the SDRAM DIMM and the cache are not buffered from the 60X bus Latches are provided over address and strobe lines while transceivers are provided for data Use is done with 74ALVT buffers by Philips which are 3 3V operated 5V tolerant and provide Bus Hold to reduce pull up down resistor count This type of buffer reduces noise on board due to reduced transitions ampli tude To further reduce noise and reflections damping resistors are placed over SDRAM DIMM s address and strobe lines over all MPC8260 s strobe lines and over Local Bus SDRAM s address lines The data transceivers open only if there is an access to a valid buffered board address or during Hard Reset configuration That way data conflicts are avoided between unbuffered memory reads and the data buffers The MPC8260 s local bus is not buffered at all this since there is only one slave on that bus i e the SDRAM 4 6 Chip Select Generator The memory controller of the MPC8260 is used as a chip select generator to access on board memories saving board s area reducing cost power consumption and increasing flexibility The MPC8260 s chip selects assignment to the various memories registers on the ADS are as shown in Table 4 2 ADS Chip Select Assignments below Table 4 2 ADS Chi
180. f the MPC8260 s JTAG machine implemented as a set of ad ditional instructions and logic within the JTAG permissions This port may be connected to a dedicated debug station for extensive system debug There are several third party debug solutions on the market These debug stations may be connected to the Not provided with the ADS 4 68 MPC8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc host computer via either Ethernet Parallel Port RS232 or any other media The debug station connection scheme is shown in Figure 4 6 Debug Station Connection Schemes below Figure 4 6 Debug Station Connection Schemes Host Ethernet Parallel ADS Media Adaptor RS232 USB 16 Wire Media Media To COP ET COP To support debug station connection to the COP JTAG port 16 generic header connector 5 is provided on the ADS carrying the COP JTAG signals as well as additional signals aiding in system debug The pinout of this connector is a general Motorola recommendation for including a COP JTAG port in a design The pinout of the COP JTAG connector is shown in Figure 4 7 COP JTAG Port Connector on page 69 Figure 4 7 COP JTAG Port Connector TDO GND N C recommended TDI TRST QREQ V3 3 TCK N C TMS e 10 GND N C recommended SRESET Q GND HRES
181. fb INST CODE EXTEST NEXT INST DOWNLOAD JtagShiftIR fb INST CODE DOWNLOAD NEXT INST UPLOAD JtagShiftIR fb INST CODE UPLOAD NEXT INST PON RESET JtagShiftIR fb INST CODE PON RESET NEXT INST UN IMPLEMENTED JtagShiftIR fb INST CODE UN IMPLEMENTED INST IS BYPASS JtagIR fb INST CODE BYPASS INST IS EXTEST JtagIR fb INST CODE EXTEST INST IS DOWNLOAD JtagIR fb INST CODE DOWNLOAD INST IS UPLOAD JtagIR fb INST CODE UPLOAD INST IS PON RESET JtagIR fb INST CODE PON RESET READ JTAG DOWNLOAD CSR VGR READ BCSR 6 WRITE JTAG DOWNLOAD CSR VGR WRITE BCSR 6 READ JTAG DOWNLOAD DATA VGR READ BCSR 7 MOTOROLA Chapter 5 Support Information 5 121 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc RECEIVE FULL 1 JTAG DOWNLOAD SHIFT REG FULL JtagReceiveFull fb RECEIVE FULL Equations state diagrams equations IBesrOWrite_B BrdContRegCs_ amp DVal B amp W amp A28 amp 1429 Bcsr1Write B BrdContRegCs_ amp DVal B amp W amp A28 amp 29
182. fthe instruction chain is 8 bit MPC8260 only while the data scan chain s length depended only on the scan selected within the MPC8260 After this operation the length of the instruction chain 15 11 bits added 3 bits for this machine preceding the MPC8260 s in the chain while the length of the data scan chain is added with ei ther 1 bit bypass or 8 bit download preceding the 8260 in the chain MSB side 2 When this machine is in Bypass download a s w agent to free memory space using the same method done with the previous revision of this board Remember that the data scan chain is 1 bit longer than it used to be MSB side MOTOROLA Chapter 4 Functional Description 4 73 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc This agent basically polls the JTAG RX FULL flag in the Download Command amp Status reg ister see Table 4 19 BCSR6 Description on page 68 when active reads the Download Data register See Table 4 20 BCSR7 Description on page 68 and puts the data byte read where required Obviously the minimum it should know are the base address and size of data buffer being loaded however its level of sophistication is upto the system programmer Run this agent again using the same method done with the previous version of this board 3 Shift in DOWNLOAD instruction for this machine and BYPASS instruction for the MPC8260 4 Move the TAP controller into Sh
183. he state Test Logic Reset may be reached synchro nously according to rising TCK from any state by simply driving TMS high for 5 consecutive rising edges of TCK The test logic is also reset asynchronously by either driving TRST low by the debug station or by Power On Reset generated by the board s Power Up or SW1 depressed or by this logic The TAP controller state diagram is shown in Figure 4 9 JTAG TAP Controller State Diagram on page Figure 4 9 JTAG TAP Controller State Diagram Test Logic Reset S 0 Run Test idle Exit2 IR Update IR a Suicidal manner MOTOROLA Chapter 4 Functional Description 4 71 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 4 13 1 2 JTAG Instruction Shift Register JISR The instruction shift register is a 3 bit register selected during Shift IR state of the TAP controller The in struction is shifted in during that state while the output of the shift register LSB is driven into MTDO to be concatenated to the next device on the JTAG chain the MPC8260 That way all devices on the JTAG chain may be shifted in with the desired instruction for them When the TAP controller moves into Update IR state the JTAG Instruction register is loaded with the value shifted into JISR During JTAG logic reset the JISR is reset into a default state of Bypass 4 13 1 3 JTAG Instruction
184. hen a jumper is placed between positions 2 3 of J1 a level range of 1 7V to 1 9V VDDL is selected This level range is a preparation for the next revision of the MPC8260 3 When a jumper is misplaced for J1 a level range of 1 8V to 2 0V is selected for VDDL This is in preparation for 2V capable future devices Figure 2 2 VDDL Range Selection J1 JI P EET 2 2 bx 2 E A x 23V 2 7V L7V L9V L8V 2 0V WARNING 15 Factory Set according to the revision of MPC8260 with which it is assembled Prior to changing a MPC8260 device Extra Care should be taken with J1 setup If a se lected Voltage Range 15 above the specification for the newly inserted MPC8260 PERMANENT DAMAGE might be inflicted to the MPC8260 J1 selects only a range of Voltage levels on VDDL The actual level is selected by TR1 See Setting VDDL Supply Voltage Level on page 19 2 3 2 Setting VDDL Supply Voltage Level After VDDL s Voltage Level Range is selected via J1 the actual level of VDDL is tuned via TRI VDDL may be measured upon J2 using a DVM or any other high input impedance voltage measuring device VDDL level is factory set at the mid range for the appropriate level range but may be changed via TRI Rotating TRI CCW will reduce VDDL voltage down to range low while rotating it CW will increase VDDL upto range high 1 08 provides visual indication for VDDL level it illuminates brighter with rise of VDDL VDDL chang
185. his revision of the ADS to address the Flash However there is an erratum associated with revision 0 of the MPC8260 by which the BADDR lines do not function during Hard Reset configuration sequence As a result with rev 0 MPC8260 chips the only possible way for the ADS to acquire Hard Reset configuration is by taking it from BCSR NOTE Due to the above if revision 0 MPC8260 silicon is used with revision PILOT of this board DS1 1 MUST be set to OFF position for the ADS to come up correctly 4 9 Local Bus Synchronous DRAM To enhance ATM performance 4 MBytes of SDRAM are provided on the Local Bus as connection table storage The SDRAM is unbuffered from the MPC8260 s local bus and is configured as 2 X 512K X 32 It is implemented with two MB811171622A 84 chips by Fujitsu or compatible The local SDRAM s timing is controlled by the second SDRAM machine of the MPC8260 which is dedi cated for the Local Bus and is assigned to a CS line according to Table 4 2 ADS Chip Select Assignments on page 48 The local bus SDRAM connection scheme is shown in Figure 4 4 Local SDRAM Connection Scheme on page 56 The local bus SDRAM performance is shown in Table 4 6 Local Bus SDRAM Performance Figures 66MHz on page 55 Table 4 6 Local Bus SDRAM Performance Figures 66MHz Bus Clock Cycles a 66 Cycle Type MHz Bus Clock Freq Burst Read Page Miss 61 1 1 1 l As well as all other slow static
186. his line is tristated and may be used for any available function of PC14 D19 T S 8260 Port 13 Parallel I O line be used to any of its available functions MOTOROLA Chapter 5 Support Information 5 85 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 5 4 P4 CPM Expansion Interconnect Signals Pin No Signal Name Attribute Description D20 RS_CD2 PC12 T O T S RS232 Port 2 Carrier Detect L Connected via RS232 transceiver to RS232 DTR2 input allowing detection of a connected terminal to this port This line is simply a PI O input line to the MPC8260 When RS232 Port 2 is disabled this line is tristated and may be used for any available function of PC12 D21 T S 8260 Port C 11 Parallel I O line be used to any of its available functions D22 FETHMDC PC10 T S Fast Ethernet Port Management Data Clock This slow clock S W generated qualifies the management data I O to read write the LXT970 s internal registers When the Ethernet port is disabled this line may be used for any available function of PC10 D23 FETHMDIO PC9 T S Fast Ethernet Port Management Data I O This signal serves as bidirectional serial data line qualified by to allow read write the LXT970 s internal registers When the Ethernet port is disabled
187. his signal has no function in a ADS that does not have an L2 Cache installed R W L2C_CLEAR L2 Cache Clear When this bit is active Low for min 8 bus clock cycles the L2 cache invalidates all its entries without flushing the same process as with HRESET asserted However it still monitors the bus so it can immediately respond when this process ends This signal is connected to the L2 TAG CLR of the MPC2605 but has no function when a cache is not installed on the ADS R W 4 62 MPC8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 4 9 BCSRO Description Function DEF ATT 6 SIGNAL 0 Signal Lamp 0 When this signal is active low a dedicated Green LED LD11 1 R W illuminates When in active this led is darkened This led may be used for S W signalling to user 7 SIGNAL LAMP 1 Signal Lamp 1 When this signal is active low a dedicated Red LED 1012 1 illuminates When in active this led is darkened This led may be used for S W signalling to user 8 31 Reserved Un Implemented 4 12 2 BCSRI Board Control Status Register 1 The BCSRI serves as a control register on the ADS Although it resides only over D 2 7 lines of the PPC data bus it 15 accessed as a word at offset 4 from BCSR base address It may be read or written at
188. ication via that medium is allowed When darkened it desig nates that the transceiver is in shutdown mode and its associated SCC2 pins may be used off board via the expansion connectors 3 3 Memory Map All accesses to ADS s memory slaves are controlled by the MPC8260 s memory controller Therefore the memory map is reprogrammable to the desire of the user After Hard Reset is performed by the debug station the debugger checks for the existence size delay and type of the SDRAM DIMM and Flash memory SIMM mounted on board and initializes the memory controller accordingly The SDRAM and the Flash memory respond to all types of memory access 1 problem supervisory program data and DMA This memory is a recommended memory map and since it is a soft map devices address may moved about the map to the convenience of any user Table 3 1 ADS Memory Map ADDESS RANGE Memory Type Device Name Size 00000000 SDRAM SDCUV6482 SDC8UV6484 64 OOFFFFFF DIMM 16 MByte 64 MByte 01000000 04000000 SDRAM Local 811171622 32 043FFFFF Bus 04400000 Empty Space 044 3 34 8260 PowerQUICC ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 3 1 ADS Memory Map ADDESS Port RANGE Memory Type Device Nam
189. ift DR state 5 Shift in a Byte of data The data shifted out is the state of JTAG RX FULL flag If the byte shifted out does not contain a 0 it indicates that new data was shifted in before the agent was able to read the previous That way the host may become aware of an errornous situation with the operation of the s w agent To play safe it is recommended to shift in a arbitrary data until JTAG RX FULL is found cleared Then a byte of valid data may be shifted in 6 Move the TAP to EXITI DR gt PAUSE DR gt EXIT2 DR The passage through EXIT1 DR sets the JTAG RX FULL flag in the Download Command amp Status register The agent then can read the valid data from the Download Data register After that data has been read by the agent the FULL is cleared 7 Repeat steps 4 to 6 above until the end of the buffer 4 13 2 JTAG Generated Power On Reset Since some of the COP debug stations are Ethernet driven a need may arise to generate Power On Reset from a remote location through the JTAG and to be able to do so when the board is stuck To support such action the RESET instruction was introduced When 15 is set to positions 1 2 and JTAG is enabled in the Download Control amp Status register it is possible to Power On Reset the board through JTAG The way to do it is 1 Move the TAP controller into Shift IR 2 Shiftin PON RESET code As aresult ofthe above Power On reset is generated resetting
190. implemented defaults to Bypass PON RESET 10 Power On Reset When this code is loaded into the Power On Reset is generated to the VADS eventually resetting the TAP controller into Test Logic Reset state As a result the JIR is reset into Bypass code BYPASS Bypass JTAG public instruction When the holds this value and the controller is in Shift DR state a single bit shift register is placed between the TDI TDO of this JTAG machine 4 13 1 4 Data Shift Register The data shift register is an 8 bit shift register shifted in LSB first on the rising edge of TCK When JIR contains the DOWNLOAD code and the TAP controller is in Shift DR state the input of this shift register is connected to TDI input of the VADS The TDO of this logic on the other hand reflects the state of the JTAG_RX_FULL status bit in the Download Control amp Status register That way the host may check prior to shifting in data whether the agent has read the previous byte of data When RX FULL flag is active data remains frozen in the register until it is read by the agent That way the host may shift in arbitrary data just to read back status of JTAG_RX_FULL Since that flag is set only by the passage through EXIT1_DR this register will contain the last 8 bits shifted in This register is available on the PPC Bus memory map D 0 7 so it may be read by a download agent running on board It is designated as BCS
191. in stand alone mode it is the responsibility of the user to provide means of handling the interrupt since there is no resident debugger with the MPC8260ADS The ABORT switch signal is de bounced and may be disabled by software 3 2 3 SOFT RESET Switch SW3 The SOFT RESET switch SW2 performs Soft reset to the MPC8260 internal modules maintaining MPC8260 s configuration clocks amp chip selects and SDRAMs contents The switch signal is debounced and it is not possible to disable it by software 3 2 4 HARD RESET Switches SW2 amp SW3 When BOTH switches SW2 and SW3 are depressed simultaneously HARD reset is generated to the MPC8260 When the MPC8260 is HARD reset all its configuration is lost including data stored in the SDRAMs and MPC8260 has to be re initialized 3 2 5 051 Reset Configuration Switch 051 is a 8 switch Dip Switch For its function see 2 3 3 Setting MODCK 1 3 for PLLs Multiplication Factor DS1 6 8 on page 20 2 3 4 Setting Hard Reset Configuration Source on page 21 and 2 3 5 Setting MODCKH 0 3 for PLLs Multiplication Factors on page 22 3 2 6 DS2 SDRAM DIMM Configuration Memory Slave Address Switch 052 sets the slave address for the SDRAM DIMM s serial configuration memory For its function see 2 3 7 SDRAM DIMM Slave Address Selection DS2 on page 23 Except for Hard Reset configuration word which is acquired only once after PON Reset MOTOROL
192. ion C14 FETHRXD3 PB18 C15 17 T S MPC8260 s Port B 17 4 Parallel I O lines May be used to any of their available functions C16 16 C17 15 C18 14 19 C20 12 21 22 10 23 9 C24 PB8 C25 PB7 C26 PB6 C27 5 28 PB4 C29 ATMRCLK T S ATM Receive Clock A divide by 8 of the ATM line clock recovered by the ATM receive logic Added with PILOT revision of the ADS to assist Circuit Emulation Tool Enabled only when pin A29 of this connector is either not connected or driven low Otherwise Tri stated C30 GND Digital Ground Connected to main GND plane of the ADS C31 C32 5 84 MPC8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 5 4 P4 CPM Expansion Interconnect Signals Pin No Signal Name Attribute Description DI PC31 T S 8260 Port 31 22 Parallel I O lines May be used to any of their available functions D2 PC30 D3 PC29 D4 PC28 D5 PC27 D6 PC26 D7 PC25 D8 PC24 D9 PC23 D10 PC22 D11 ATMTFCLK PC21 T O T S ATM Transmit FIFO Clock Upon the rising edge of this clock driven by the 8260 while the ATM port is enabled the cell octets are written to the PM5350 s transmit FIFO This clock samples ATMTXD 7 0
193. is given to change the SDRAM DIMM configuration EEPROM slave address for the convenience of the user DS2 is shown in Figure 2 6 DS2 Description on page 23 Figure 2 6 DS2 Description SA2 SA2 SAI SAL RESERVED DS2 The various position combinations of DS2 and their associated SDRAM DIMM configuration EEPROM s slave addresses are shown in Table 2 2 DS2 SDRAM DIMM Configuration EEPROM Slave Address below Table 2 2 DS2 SDRAM DIMM Configuration EEPROM Slave Address Slave Address bin Switch 1 Switch 2 Switch 3 1010000 ON ON ON 1010001 ON ON OFF 1010010 ON OFF ON 1010011 ON OFF OFF 1010100 OFF ON ON 1010101 OFF ON OFF 1010110 OFF OFF ON 1010111 OFF OFF OFF DS2 is factory set to 1 2 3 ON 2 4 Installation Instructions When the MPC8260ADS has been configured as desired by the user it can be installed according to the required working environment as follows Host Controlled Operation Stand Alone MOTOROLA Chapter 2 Hardware Preparation and Installation 2 23 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 4 1 Host Controlled Operation In this configuration the MPC8260ADS is controlled by a host computer via the COP port which is a subset of the JTAG port This configuration allows for extensive debugging using on host debugger The host
194. istor When driven externally it MUST be driven with an Open Drain gate Failure to do so may result in permanent damage to the MPC8260 or to ADS logic 12 GND Digital GND Main GND plane 13 14 HRESET T O 8260 Hard Reset L When asserted by an external H W generates Hard Reset sequence for the MPC8260 During that sequence asserted by the MPC8260 for 512 system clocks Pulled Up on the ADS using a 1 resistor When driven by an external tool MUST be driven with an Open Drain gate Failure to do so may result in permanent damage to the MPC8260 and or to ADS logic Not Connected 15 XBR3 CKSTOP_OUT IO Normally configured as XBR3 which has no function with this connector May be configured as CKSTP OUT Check Stop L When asserted Low indicates that the MPC8260 core has entered a Check Stop state 16 GND MOTOROLA Digital GND Main GND plane Chapter 5 Support Information 5 87 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 5 1 6 P6 P7 P8 P9 P10 P12 P13 P14 amp P15 Logic Analyzer Connectors These are 38 pin SMT high density matched impedance connector made by AMP They contain all MPC8260 signals unbuffered The pinout of these connectors is shown in Chapter 6 Schematics For signal description of these connectors see the MPC8260 User s
195. itializations For 66Mhz Reg Device Type Bus Init Value hex Description PSDMR Contd SDC2UV6482C 84 16 MByte DIMM SIZE BCSRO should be Cleared SDC8UV6484C 84 64 MByte DIMM SIZE BCSRO should be Set PPC 60X Bus Mode 416EB45A PBI in BCSRO should be Cleared Bank Based Interleaving Refresh enabled normal operation code address muxing mode 1 A 15 17 on BNKSEL 0 2 A9 on PSDAIO 7 clocks refresh recovery 3 clocks precharge to activate delay 2 clocks activate to read write delay 4 beat burst length 1 clock last data out to precharge 1 clock write recovery time extra cycle on address phase normal timing for control lines 2 clocks CAS latency C2AAB45A PBI in BCSRO should be Set 412EB45A PBI in BCSRO should be Cleared Page Based Interleaving Refresh enabled normal operation code address muxing mode 2 19 on BNKSEL2 8 on 10 7 clocks refresh recovery 3 clocks precharge to activate delay 2 clocks activate to read write delay 4 beat burst length 1 clock last data out to precharge 1 clock write recovery time extra cycle on address phase normal timing for control lines 2 clocks CAS latency Bank Based Interleaving Refresh enabled normal operation code address muxing mode 1 A 15 17 on BNKSEL 0 2 9 PSDA10 7 clocks refresh recovery 3 clocks precharge to activate delay 2 clocks activate to read write delay 4 beat b
196. k size 4 banks per device row starts at Fujitsu A9 12 row lines internal bank interleaving allowed normal AACK operation BR3 Reserved OR3 BR4 MB811171622A 84 Local 04001861 Base at 04000000 32 bit port size no parity Sdram machine 2 OR4 00880 4 MByte block size 2 banks device row starts at 8 10 row lines internal bank interleaving allowed normal AACK operation 5 5350 04600801 Base at 04600000 8 bit port size no parity on PPC bus ORS FFFF8E36 32K Byte block size delayed CS assertion early CS and WE negation for write cycle relaxed timing 7 w s for read 8 for write extended hold time after read 3 38 8260 PowerQUICC ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 3 4 Memory Controller Initializations For 66Mhz Reg Device Type Bus Init Value hex Description PSDMR SDC2UV6482C 84 PPC 416EB452 Bank Based Interleaving Refresh enabled normal 16 MByte operation code address muxing mode 1 A 15 17 on Single BNKSEL 0 2 9 PSDA10 7 clocks refresh MPC8260 recovery 3 clocks precharge to activate delay 2 clocks Bus activate to read write delay 4 beat burst length 1 clock Mode last data out to precharge 1 clock write recovery time no extra cycle on address phase normal timing for control lines 2 clocks CAS latency C2AAB452 Page Bas
197. king the side locks on itself The SDRAM insertion is shown in Figure 2 14 SDRAM DIMM Insertion below MOTOROLA Chapter 2 Hardware Preparation and Installation For More Information On This Product Go to www freescale com 2 27 Freescale Semiconductor Inc Figure 2 14 SDRAM DIMM Insertion RIGHT SIDE VIEW 2 28 8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 3 Operating Instructions 3 1 Introduction This chapter provides necessary information to use the MPC8260ADS in host controlled and stand alone configurations This includes controls and indicators memory map details and software initialization of the board 3 2 Controls and Indicators The MPC8260ADS has the following switches and indicators 3 2 1 Power On RESET Switch SW1 The Power On RESET switch SW1 performs Power On reset to the MPC8260 as if the power was re applied to the ADS When the MPC8260 is reset that way all configuration and all data residing in volatile memories are lost After PORST signal is negated the MPC8260 re acquires the power on reset and hard reset configuration data from the hard reset configuration source Flash BCSR 3 2 2 ABORT Switch SW2 The ABORT switch is normally used to abort program execution this by issuing a level 0 interrupt to the MPC8260 If the ADS is
198. l operates in conjunction to DIMM SIZE signal below In Single MPC8260 Mode i e without L2 Cache this bit has no effect R W DIMM SIZE Sdram DIMM Size 60X mode 1 with L2 Cache this bit in conjunction with PBI above controls the address muxing scheme for the Sdram DIMM When Low the addressing scheme matches a 16 MByte DIMM while when High the addressing scheme matches a 64 MBytes DIMM In Single MPC8260 Mode i e without L2 Cache this bit has no effect R W L2C INH L2 Cache Inhibit When this bit is active low the L2 cache is inhibited and unable to respond to cacheable cycles However bus activity is still monitored by the cache so that it may respond immediately after this signal is negated This signal is connected to the MPC2605 s L2 UPDATE INH This signal has no function in a ADS that does not have an L2 Cache installed L2C_FLUSH L2 Cache Flush When this bit is active low for min 8 bus cycles the MPC2605 initiates a process within which valid lines are marked invalid while dirty lines are written back to memory and marked invalid This signal is connected to L2 FLUSH signal of the MPC2605 This signal has no function in a ADS that does not have an L2 Cache installed L2C_LOCK L2 Cache Lock When this bit is active low the MPC2605 will stop entering new data into the cache while yet maintaining existing data and responding to cacheable cycles T
199. ll Of Material Reference Designation Part Description Manufacturer Part C2 C102 C180 C193 C198 Capacitor 68uF 16V 10 SMD AVX TAJD686K016R C199 Size D Tantalum C3 C5 C6 C7 C8 C103 C141 Capacitor 10uF 20V 10 SMD SIEMENS B45196 H4475 K20 C142 C147 C153 C154 C155 Size C Tantalum C158 C164 C165 C167 C171 C176 C178 C195 C196 C206 C4 C9 C10 C11 C12 C13 C181 Capacitor 10nF 50V 10 NPO VITRAMNON VJ1210A103K XAT C183 C185 C186 C187 C189 SMD 1210 Ceramic C190 C191 C197 C14 C15 C16 C17 C18 C19 C20 Capacitor 0 1uF 16V 10 SMD AVX 0603 YC104KAT20 C21 C22 C23 C24 C25 C26 C27 0603 Ceramic C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 61 C62 C64 C65 C67 C69 C70 C71 C72 C73 C74 C75 C76 C77 C78 C79 C80 C81 C82 C83 C84 C85 C86 C87 C88 C89 C90 C91 C92 C94 C95 C96 C97 C98 C99 C104 C105 C106 C107 C108 C109 C110 C111 C112 C113 C114 C115 C116 C117 C118 C119 C120 C122 C123 C125 C126 C127 C128 C129 C130 C131 C137 C138 C139 C140 C144 C145 C146 C151 C157 C159 C161 C162 C163 C166 C168 C169 C172 C173 C174 C177 C179 C182 C184 C188 C192 C194 C200 C201 C202 C203 C204 C205 C63 C68 C93 C100 C101 C121 Capacitor 47uF 20V 10 SMD AVX TAJD476K016 C132 C134 C149 C160 SIze D Tantalum C66 Capacitor 100uF 10V 10 SMD AVX TAJD107K016R Size D Tantalum C135 Capacitor 1500pF 50V 5
200. lt lt lt lt n ug 7 G c c co crj F O G gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt HRR o n o 00 e 00 oo A oo u4 TS DIS CND CND CND v 8 PROJECT MPC8260ADS REV PILOT SHEET 8 OF 18 8 ENG YAIR LIEBMAN BLOCK ATM 155 CHK DESCRIP tmp mnt net prince yair voyager ads pilot sch 9 drw 26 SEP 99 19 05 last update 21 SEP 99 18 44 is Product to For More Information On Th LXT970 Tp 32 1022 3506 2 FETHTXD 0 4 FETHTXD4 63 m 1 FETHTXD3 62 5 FETHTXD2 61 FETHTXD1 60 702 29 P1 910 I 62 TPIP 51 1 8 BLUE 5 54 1 R2 7 ORANGE TPON R Rf R 6 BLACK m FETHTXEN 58 TX 15 TX_ER R A R S 6461 3 YELLOW 3 46 2 BROWN i 36 RXD4 1
201. lug is designed to accept 14 to 22 AWG wires It is recommended to use 14 to 18 AWG wires To provide solid ground two Gnd terminals are supplied It is recommended to connect both Gnd wires to the common of the power supply while VCC is connected with a single wire NOTE Since hardware applications may be connected to the MPC8260ADS via the expansion connectors P4 and P16 the additional power consumption should be taken into consideration when a power supply is connected to the MPC8260ADS 2 4 4 P2 12V Power Supply Connection The MPC8260ADS may require 12 1 A max power supply for 12V programmable Flash SIMM The MPC8260ADS can work properly without the 12V power supply if there is no need to program a 12V programmable Flash SIMM Connect the 12V power supply to connector P2 as shown below Figure 2 10 P2 12V Power Connector 1277 aa 10 P2 is 2 terminal block power connector with power plug plug is designed to accept 14 to 22 AWG wires It is recommended to use 14 to 18 AWG wires 2 4 5 COP JTAG Connector P5 The MPC8260ADS COP interface connector P5 is 16 pin male Header connector The connection between the MPC8260ADS and the COP controller is by a 16 line flat cable supplied with the COP controller board obtained from a third party developer Figure 2 11 P5 COP JTAG Port Connector below shows the pin configuration of the connector MOTOROLA Chapter 2 Hardwa
202. n M aa REA 30 3 2 11 J4 Optional Ventilator Supply tnter daten ert repete ener tend 31 3212 Source Selection u I 31 3 2 13 J6 MIDE Me3ASUTEROBTID su E e 31 3 2 14 JT VPP Source Selector 31 3 2 15 GIS OE rS e 32 3 2 16 ATM TX Indicator 32 3 2 17 ATM RX Indicator e u Su 32 3 2 18 Ethernet RX Indicator 22 3 2 19 Ethernet TX Indicator 04 32 3 2 20 Ethernet LINK Indicator LD5 32 3 2 21 Fast Ethernet Indicator LD6 aa EORR LS EXE MEE 32 3 2 22 Fast Ethernet CLSN Indicator ED aun u an 33 3 2 23 EDS ca 8708 L S DA S e do tue DM S SS a 33 3 2 24 3 33 Indicator LCDI zu usa m LE E 33 3 2 25 RUN Indicator za sende ieu to au vat onte ive int ded idu at 33 3 2 26 General Purpose Indicator 0 LD11 33 3 2 27 General Purpose Indicator 1 LD12 5 ie instar 33 3 2 28 Fast Ethernet Port Initially Enabled LD13 33 3 2 29 ATM ON ED ess anu aba 33 3 2 30 RS232 Port TON U uA 33 3 2 31
203. n On the ADS this line is connected to the MPC8260 s DP7 CSE1 IRQ7 line appearing also at the CPM expansion nectors After the LX970 is reset the FDS MDINT pin wakes up as FDS rather than MDINT and there fore MUST be initially programmed to MDINT function by setting 17 1 bit otherwise IRQ7 may be constantly driven low possibly generating interrupts to the MPC8260 if not masked properly Since IRQ7 may also be driven by any tool connected to the expansion connectors it should be driven with an Open Drain buffer 7 is pulled up on the ADS 4 11 3 RS232 Ports To assist user s applications and to provide convenient communication channels with both a terminal and a host computer two identical RS232 ports are provided on the ADS connected to SCC1 and SCC2 ports of the MPC8260 This is implemented by an MC145583 transceiver which generates RS232 levels internally using a single 3 3V supply and has a standby mode When the RS232EN1 RS232EN2 bits in asserted low the corresponding transceiver is enabled When negated the corresponding transceiver enters standby mode within which the receiver outputs are tri stated enabling use of the corresponding port s pins off board via the expansion connectors The RS232 ports are implemented with two 9 pin female D Type stacked connectors PA3 the lower which is connected to SCC2 and PB3 the upper which connected to SCC1 Both connectors are configu
204. n drain signal and must be driven with an open drain gate by every external source driving it Otherwise contention will occur over that line which might cause permanent damage to either the ADS logic and or to the MPC8260 itself 4 1 3 1 COP JTAG Port Soft Reset To provide convenient soft reset capability for COP JTAG controller SRESET line appears at the COP JTAG port connector P5 The COP JTAG controller may directly generate Soft reset by asserting low this line 4 1 3 2 Manual Soft Reset Manual soft reset allows run time soft reset when the COP controller is disconnected from the ADS and for resident debuggers support Depressing the Soft Reset button SW3 asserts the SRESET pin of the MPC8260 generating a Soft Reset sequence Since SRESET line may be driven internally by the MPC8260 it is driven to the MPC8260 with open drain gate If off board hardware is connected to the ADS is to drive SRESET line then it should do so with an open drain gate to avoid contention over this line which might inflict permanent damage to either the ADS logic and or to the MPC8260 itself 4 1 3 3 Internal Sources Soft Reset The only internal Soft reset source is the COP JTAG soft reset which may be generated using Public JTAG instructions to shift active value 0 to the SRESET pin via the boundary scan chain This is not useful for run time 4 2 Local Interrupter There are 2 external interrupt which ar
205. nabled to precede the 8260 in the JTAG chain When a jumper is placed between positions 2 3 of J5 the Fast download JTAG machine 15 bypassed and the TDI input goes directly from the COP JTAG connector P5 to the 8260 See also 4 13 1 Fast Download Support on page 69 J5 should be set between 2 3 if problems are encountered with the use of existing COP JTAG debug equip ment since this indicates that its software is not capable of using the fast download machine Figure 2 5 J5 TDI Source Selection gt Fast Download be Enabled Fast Download Disabled ENG Compatible Factory Setup See 4 8 4 Hard Reset Configuration MPC8260 Revision Dependency on page 55 Provided that DS1 1 is in OFF position 3HARD bypass Even when the Fast download logic enabled via J5 it wakes up asynchronously bypassed Through a noise filtering network 2 22 8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 3 7 SDRAM DIMM Slave Address Selection 052 The SDRAM DIMM has a serial configuration EEPROM which is accessed using protocol Each slave device on that bus has an 7 bit address field 3 of which the LSBs within this device may be set externally Since the SDRAM DIMM configuration is read using the MPC8260 s re port which may be required for user s application an option
206. ne so that the row address may be allowed to propagate via the Latch Multiplexers in time for the Activate command 3 With this revision of the ADS support for Sdram PBI Page Based Interleaving was added Therefore the relative location of the Row Address field is shifted up the address lines depend ed on the number of internal banks within SDRAM DIMM This since the Bank Select line s are inserted between the Column LSB and Row MSB address lines As can be seen from Figure 4 3 SDRAM DIMM 60X Bus Connection Scheme on page 51 PBI and DIMM SIZE signals driven via BCSRO select the correct address line group for a specific DIMM size with PBI set Note Since there is no indication in H W for PSDMR PBI state and as for DIMM s size these parameters are set to the ADS logic via BCSR It is the system s programmer responsibility to set these parameters correctly in BCSR reflecting the current state of PSDMR PBI and the DIMM s size Failure in doing so will result with im proper operation of the SDRAM DIMM on ADS boards with L2 Cache assembled The performance of the SDRAM is harmed by the addition of the external multiplexers of the SDRAM s address lines The effects may be seen in Table 4 3 SDRAM DIMM 84MHz Performance Figures on page 51 4 7 4 SDRAM DIMM Configuration Information Unlike memory SIMMs which have few presence detect lines for configuration report the DIMM s config uration information 1
207. nformation On This Product Go to www freescale com Freescale Semiconductor Inc IPON RESET L2CACHE CLEAR PON DEFAULT CLEARED PON RESET amp L2CACHE CLEAR PON DEFAULT L2CACHE_CLEARED then L2CACHE CLEARED else IL2CACHE CLEARED state diagram 0 state SIGNAL LAMP if VGR WRITE BCSR 0 amp SIGNAL LAMPO DATA BIT pin SIGNAL LAMP amp RESET SIGNAL LAMPO PON DEFAULT SIGNAL LAMP ON PON RESET amp SIGNAL PON DEFAULT SIGNAL LAMP then ISIGNAL LAMP ON else SIGNAL LAMP ON state SIGNAL LAMP ON if VGR WRITE BCSR 0 amp SIGNAL LAMPO DATA SIGNAL LAMP amp RESET SIGNAL LAMPO PON DEFAULT SIGNAL LAMP ON PON RESET amp SIGNAL LAMPO PON DEFAULT SIGNAL LAMP ON then SIGNAL LAMP ON else ISIGNAL LAMP state diagram SignaLampl B state SIGNAL LAMP ON if VGR WRITE BCSR 0 amp SIGNAL LAMPI DATA BIT pin SIGNAL LAMP amp RESET SIGNAL PON DEFAULT SIGNAL LAMP ON PON RESET amp SIGNAL LAMPI PON DEFAULT SIGNAL LAMP then ISIGNAL LAMP ON else SIGNAL LAMP ON state SIGNAL LAMP ON if VGR WRITE BCSR 0 amp SIGNAL LAMPI DATA SIGNAL LAMP 6 RESET SIGNAL PON DEFAULT SIGNAL LAMP
208. nsion Address Latch Enable H This a buffered MPC8260 s ALE provided for expansion board s use 015 EXPCTLO Expansion Control Line 0 This line is a buffered version of MPC8260 s BCTLO Bus Control Line 0 which serves as R W provided for expansion board s use D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 GND Digital Ground Connected to main GND plane of the ADS IMS Bit MOTOROLA Chapter 5 Support Information 5 93 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 5 2 MPC8260ADS Part List In this section the MPC8260ADS s bill of material is listed according to their reference designation The BOM for the MPC8260ADS is shown in Table 5 8 MPC8260ADS Bill Of Material below while Table 5 8 MPC8260ADS Bill Of Material Reference Designation Part Description Manufacturer Part C2 C102 C180 C193 C198 Capacitor 68uF 16V 10 SMD AVX TAJD686K016R C199 Size D Tantalum C3 C5 C6 C7 C8 C103 C141 Capacitor 10uF 20V 10 SMD SIEMENS B45196 H4475 K20 C142 C147 C153 C154 C155 Size C Tantalum C158 C164 C165 C167 C171 C176 C178 C195 C196 C206 C4 C9 C10 C11 C12 C13 C181 Capacitor 10nF 50V 10 NPO VITRAMNON VJ1210A103K XAT C183 C185 C186 C187 C189 SMD 1210 Ceramic C190 C191 C197 C14 C15 C16 C20
209. obtained on the Internet at URL Attp z www fujitsumicro com products memory sdram mod html while the SDRAM chips from which the DIMM is composed data sheet may be obtained at URL Attp www fujitsumicro com products memory sdrams html The SDRAM s timing is controlled by SDRAM Machine 1 associated with 60X bus via its assigned Chip Select line See Table 4 2 ADS Chip Select Assignments on page 48 The SDRAM connection scheme is shown in Figure 4 2 SDRAM DIMM Connection Scheme below MOTOROLA Chapter 4 Functional Description 4 49 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Figure 4 2 SDRAM DIMM Connection Scheme SDC2UV6482C 84 52 50 52 PSDRAS RAS PSDCAS CAS PSDWE crum WE BANKSEL 1 2 BA 0 5 10 gt 10 19 gt A9 20 28 gt A 8 0 PSDDOM 0 7 DQMB 0 7 60 65 DQ 0 63 CKE CLK 3 6 CLK 1 4 I2CDAT SDA SA 2 0 Serial EEPROM ee Slave Address Setting Switches As can be seen from the above figure with this revision of the ADS there are few changes with respect to previous revision of the ADS 1 MPC8260 s BKSEL 1 2 are connected to DIMM s BA 1 0 respectively instead of BK SEL 0 1 2 8260 A17 is connected to DIMM s instead of BKSEL2 3 BKSELO is unused 4 8260 19 is connected to DIMM s A9 instead of MPC82
210. om Freescale Semiconductor Inc SIMM socket To minimize use of MPC8260 s chip select lines only one chip select line CSO is used to select the Flash as a whole while distributing chip select lines among the module s internal banks is done by on board pro grammable logic according to the Presence Detect lines of the Flash SIMM plugged into the ADS The access time of the Flash memory provided with the ADS is 95 nsec however devices with other delays may be supported as well Reading the delay section of the Flash SIMM Presence Detect lines see Table 4 11 BCSR2 Description on page 64 the debugger may establish via ORO the correct number of wait states considering 66MHz Bus clock frequency required for accessing the Flash SIMM The control over the Flash is done using the GPCM and a dedicated 50 region controlling the whole bank During hard reset initializations the debugger or any application S W for that matter reads the Flash Presence Detect lines via BCSR and decides how to program BRO amp ORO registers within which the size and the delay of the region are determined The performance of the Flash memory is shown in Table 4 5 Flash Memory Performance Figures below Table 4 5 Flash Memory Performance Figures Number of Bus Clock Cycles 66 MHz Bus Clock Freq Cycle Type N Flash Delay nsec 95 Read Access 8 Write Access 9 From TS asserted However due to internal
211. onductor Inc Table 5 8 MPC8260ADS Bill Of Material Reference Designation Part Description Manufacturer Part SWI SPDT push button RED Sealed C amp K KS12R22 CQE SW2 SPDT push button WHITE Sealed C amp K KS12R21 CQE SW3 SPDT push button BLACK Sealed KS12R23 CQE Tl Transistor Dual TMOS VT 2V Motorola MMDF3N02HD TRI Trimmer Pot 1 KQ Single Turn BOURNS 3362P 1 102 Ul Fiber Optic I F Module 1300 nm HP HFBR 5205 wavelength 2 Km Range U2 US 3 3V Powered Single Supply RS232 Motorola MC145583V Transceiver 3 Tx 5 Rx U3 10 100 Base T Filter network HALO TG22 3506ND U4 Saturn User Network I F S UNI for PMC Sierra Inc 5350 155 52 amp 51 84 Mbps 128 06 Clock Generator 19 44 MHz 20 CM42AH 19 440 ppm 5V Supply 4 pins 8 pin DIP form factor U7 U9 U23 U37 Quad CMOS buffer with individual Motorola 74LCX125P Output Enable 08 020 021 Octal CMOS Buffer Motorola 74LCX541J 010 Voltage Regulator Variable 1 5 Motorola LM317D2T output D PAK package U11 3 3V Linear Voltage regulator 5A Micrel MIC29500 3 3BT output U12 MPC8260 2 nd generation Power Motorola 8260 QUICC Socket for the above 480 pin ANDON 0 29 05 480 286 G04 N10 1 27mm PGA to PGA 29 X 29 array gold plated contacts Adaptor PGA to BGA 480 pin 0 29 05 480 27 30 10
212. onnected to SCC1 s RTS on PD29 On Port 2 Lower connector connected to SCC2 s RTS on P26 4 12 Board Control amp Status Register BCSR Most of the hardware options on the ADS are controlled or monitored by the BCSR which is a 32 bit wide read write register file BCSR resides over the PPC Bus accessed via the MPC8260 s memory controller see Table 4 2 ADS Chip Select Assignments on page 48 and in fact includes 8 registers BCSRO to BCSR7 Since the minimum block size for a CS region is 32K Bytes and only A 27 29 lines are decoded by the BCSR for register selection BCSRO BCSR7 are duplicated many times inside that region See also Table 1 1 MPC8260ADS Specifications on page 12 The following functions are controlled monitored by the BCSR 1 2 3 4 5 6 7 8 9 10 11 12 PBI 60X Bus mode only L2 Cache Inhibit L2 Cache Flush L2 Cache Lock L2 Cache tag Clear ATM Port Control which includes Transceiver Enable Disable Transceiver Reset Fast Ethernet Port Control which includes Transceiver Initial Enable Transceiver Reset RS232 port 1 Enable Disable RS232 port 2 Enable Disable Flash Size Delay Identification External off board tools Support which include Tool Identification Revision Tool Status Information S W Option Identification Since there are only 3 5232 transmitters in the device DSR is connected to CD MOTOROLA Chap
213. ontain numerous parts reference designation changes nor parts value changes etc These changes reflect only on the schematics and bill of material 1 6 1 BCSR o address space was doubled to eight 32 bit registers part of which is still reserved to allow for future expansion o BCSRO0 and BCSRI were moved to D 0 7 instead of D 24 31 o Added optional Power On and Hard Reset configurations dip switch enabled with full MODCK control via dip switches o On BCSRO added 2 control bits PBI and DIMM SIZE to provide PBI support when working with L2 Cache These bits have no use in Single MPC8260 mode o Added support for Fast Download via JTAG BCSR6 amp BCSR7 with internal and exter nal bypass options for ENG compatibility The ADS wakes up in ENG compatibility mode o Added support for Power On Reset via JTAG o Codes for L2Cache size were changed 0 are now reserved 11 No L2Cache 01 512 L2Cache 1 6 2 SDRAM DIMM PPC Bus o Added PBI support To allow this the addressing scheme was changed so that BK SEL 0 2 are connected to NC BAT1 BAO correspondingly rather than BA1 BA0 A11 correspondingly In addition for 60X mode PBI support the Latch Mux was enlarged and qualified by PBI and DIMM SIZE bits in BCSRO Hard reset is applied by depressing BOTH Soft Reset amp ABORT buttons Unless a 12V programmable Flash SIMM is being used 1 14 8260 PowerQUICC II ADS U
214. oot the hold off state machine may be left in NO HOLD OFF for HRESET asserted duration without warrying about contention between flash and data buffers equations HoldOffCnt clk SYSCLK HoldOffCnt ar 0 HoldOffCnt ap 0 HoldOffTc HoldOffCnt fo 3 when END OF FLASH READ 4 END OF READ amp HoldOffCnt fb 0 HoldOffCnt fb 0 amp HoldOffTc fb amp DSyncHardReset B fb then HoldOffCnt HoldOffCnt fb 1 else HoldOffCnt 0 Flash Chip Select equations FlashCsOut oe hf FlashCs1 FlashCs B amp FLASH amp HRESET IN FLASH IFlashCs amp FLASH amp IN FLASH amp DSyncHardReset B fb FlashCs2_B FlashCs B amp FLASH BANK2 amp HRESET IN FLASH FlashCs amp FLASH BANK2 amp IHRESET IN FLASH amp DSyncHardReset B fb FlashCs3_B FlashCs amp FLASH BANK3 amp HRESET IN FLASH FlashCs amp FLASH BANK3 amp IHRESET IN FLASH amp DSyncHardReset B fb FlashCs4_B FlashCs B amp FLASH amp HRESET IN FLASH IFlashCs B FLASH amp IHRESET IN FLASH amp DSyncHardReset B fb
215. p ATM RESET DATA BIT pin ATM RESET ACTIVE amp IPON RESET RESET PON DEFAULT ATM_ RESET ACTIVE PON RESET RESET PON DEFAULT RESET then ATM RESET ACTIVE else IATM RESET ACTIVE state_diagram FEthEn 5 126 MPC8260 PowerQUICC ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc state FETH_ENABLED if VGR WRITE BCSR 1 amp FETH ENABLE DATA BIT pin ENABLED 4 RESET FETH ENABLE PON DEFAULT FETH ENABLED PON RESET amp FETH ENABLE PON DEFAULT _ then IFETH ENABLED else FETH ENABLED state FETH ENABLED if VGR WRITE BCSR 1 amp FETH ENABLE DATA FETH ENABLED amp RESET FETH ENABLE PON DEFAULT ENABLED PON RESET amp FETH ENABLE PON DEFAULT FETH ENABLED then FETH ENABLED else IFETH ENABLED state_diagram FEthRst_B state ACTIVE if VGR WRITE 1 amp FETH RESET DATA FETH RESET ACTIVE amp IPON RESET FETH RESET PON DEFAULT FETH RESET PON RESET amp FETH RESET PON DEFAULT RESET ACTIVE then IFETH RESET ACTIVE else
216. p Select Assignments Chip Select Assignment Bus Timing Machine 50 Flash Memory SIMM 60X Buffered GPCM Hf necessary Required for Flash and BCSR address which covered in a Chip Select region that controls a buffered device allow a configuration word stored in Flash memory become active gt And off board See further 4 48 MPC8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 4 2 ADS Chip Select Assignments Chip Select Assignment Bus Timing Machine CS1 BCSR 60X Buffered GPCM CS2 SDRAM DIMM Single Bank only 60X Main SDRAM Machine 1 CS3 Reserved for future use CS4 SDRAM Soldered on board Local SDRAM Machine 2 55 ATM Microprocessor I F 60X Main UPMB CS6 Comm Tool M P I F Cs 1 60X Buffered GPCM UPMx CS7 Comm Tool M P I F Cs 2 60X Buffered GPCM UPMx CS 8 11 Unused 4 7 Synchronous DRAM DIMM 60X Bus To enhance performance especially in higher operation frequencies 16 MBytes of SDRAM DIMM are provided on board The SDRAM DIMM s data bus is unbuffered from the MPC8260 60X bus and is con figured as 2 X 1M X 64 The SDC2UV6482C 84T S 15 an unbuffered 168 pin DIMM by Fujitsu compat ible which is composed of eight 2 X X 8 SDRAM chips MB81117822A 84 The DIMM s data sheet may be
217. pin L2CACHE FLUSHED amp RESET L2CACHE FLUSH PON DEFAULT 2 FLUSHED PON RESET amp L2CACHE FLUSH PON DEFAULT L2CACHE FLUSHED then L2CACHE FLUSHED else IL2CACHE FLUSHED state_diagram 12 state L2CACHE LOCKED if VGR WRITE BCSR 0 amp L2CACHE LOCK DATA BIT pin LOCKED amp RESET L2CACHE LOCK PON DEFAULT L2CACHE LOCKED PON RESET amp L2CACHE LOCK PON DEFAULT LOCKED then IL2CACHE LOCKED else L2CACHE LOCKED state 2 LOCKED if VGR WRITE BCSR 0 amp L2CACHE LOCK DATA BIT pin L2CACHE LOCKED amp RESET L2CACHE LOCK PON DEFAULT LOCKED PON RESET amp L2CACHE LOCK PON DEFAULT L2CACHE LOCKED then L2CACHE LOCKED else IL2CACHE LOCKED state_diagram L2Clear_B state L2CACHE CLEARED if VGR WRITE BCSR 0 amp L2CACHE CLEAR DATA BIT pin L2CACHE CLEARED amp RESET L2CACHE CLEAR PON DEFAULT L2CACHE CLEARED PON RESET amp L2CACHE CLEAR PON DEFAULT L2CACHE CLEARED then IL2CACHE CLEARED else L2CACHE CLEARED state CLEARED if VGR WRITE BCSR 0 amp L2CACHE CLEAR DATA BIT pin L2CACHE CLEARED amp 5 124 8260 PowerQUICC II ADS User s Manual MOTOROLA For More I
218. r a developer is able to download code run it set breakpoints display memory and registers and connect proprietary h w via the expansion connectors to be incorporated into a desired system with the MPC8260 processor This board could also be used as a demonstration tool 1 application s w may be programmed into its Flash memory and ran in exhibitions etc 1 2 Abbreviation List ADS the MPC8260ADS the subject of this document e UPM User Programmable Machine GPCM General Purpose Chip select Machine e GPL General Purpose Line associated with BSCR Board Control amp Status Register ZIF Zero Input Force Ball Grid Array SIMM Single In line Memory Module DIMM Dual In Line Memory Module PBI Page Based Interleaving T ECOM or El Communication Tool attachable to this board via expansion connectors 1 3 Related Documentation 8260 PowerQUICC User s Manual 2605 Data Sheet PMC SIERRA 5350 Long Form Data Sheet PMC SIERRA 5350 Errata Notice PMC SIERA 5350 Reference Design PMC SIERA 5350 Reference Design Errata LXT970A by Level One Data Sheet http www levell com product quickref html network LXT970 Demo Board User s Guide http www levell com product quickref html network Rither on or off board 2 Access to documents in this site requires registration MOTOROLA Chapter
219. r operation Figure 4 1 Clock Generator Scheme gt MPC 8260 CLOCK GEN LOW 66 MHz BUF ri 4 4 Bus Configuration The MPC8260 on the ADS may be configured in 2 possible bus modes depended upon the presence of L2 Cache on board 1 Single MPC8260 Mode MOTOROLA Chapter 4 Functional Description 4 47 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 60X Bus Mode 4 4 1 Single MPC8260 Mode When a L2 Cache is not present on the ADS the MPC8260 is configured in Single MPC8260 Mode Le assuming only one master on the bus with no support for external master access This allows for internal address multiplexing to occur with the external address multiplexers made redundant and therefore not as sembled improving SDRAM performance 4 4 2 60x Bus Mode When L2 Cache is installed on the ADS the MPC8260 may no longer operate in single MPC8260 mode this since the address must be seen as is by the cache calling for the introduction of the external address latch multiplexers required for the PowerPC bus SDRAM In this mode SDRAM performance is harmed due to added wait state on the first access in a page caused by the delay associated with the external multiplex ers 4 5 Buffering In order to achieve best performance it is necessary to reduce the capacitive load over the 60X bus as much as possible Th
220. r voyager ads pilot sc h 3 drw 26 SEP 99 19 02 last_update 21 SEP 99 18 43 741 16244 16 47 2 8 16 47 2 09 AQ 17 46 8 17 801 46 3 EXPD1 01 01 A1 44 5 6 802 4 A2 2 8 02 451120 026 19 803 23 6 03 03 5 BS 1 RN7 BD4 41 4 8_ 4 OET 74LCX541 BD5 20 9 SDRMA10 2 18 EXPCPLO A5 85 Al Y1 2 806 11 EE 04 04 5 2m SDWE 3l vali 44 EXPGPL1 07 37 12 7 05 05 SDRAS 4 16 4 43 EXPGPL2 7 87 22 38 11 22 1 06 06 ts 15 4 T RT BA23 37 12 23 4 4 48 fale cr Is SDCAS Blas 5 14 8420 EXPCPL3 O0EZ2 71 ye 3 KA EXPGPL4 808 36 13_EXPD8 T NEST SDMUX 8 4312 EXPGPL5 809 35 14 9 BALE 9 1
221. rawn from this power bus is found in Table 4 22 Off board Application A22 i1 Maximum Current Consumption on page 75 A23 A24 A25 N C Not Connected MOTOROLA Chapter 5 Support Information 5 89 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 5 7 P16 System Expansion Interconnect Signals Pin No Signal Name Attribute Description A26 5V Supply Connected to ADS s 5V VCC plane Provided as power supply for external tool For allowed current draw see Table 4 22 27 Off board Application Maximum Current Consumption on page 28 23 29 A30 1 32 GND Digital Ground Connected to main GND plane of the ADS B2 B3 B4 TSTATO I Tool Status 0 7 This lines may be driven by an external tool to be read via BCSR2 of the ADS These lines are pulled up on the ADS by B5 TSTATI 10 resistors See also Table 4 11 BCSR2 Description on B6 TSTAT2 page 04 B7 TSTAT3 B8 TSTAT4 B9 TSTATS 10 TSTAT6 Bll TSTAT7 B12 1 Tool Revision 01 3 This lines should be driven by an external tool with the Tool Revision Code to be read via BCSR2 of the ADS These TOOLREVI lines pulled up on the ADS by 10 resistors See also B14 TOOLREV2 Table 4 11 BCSR2 Description on page 64 15 TOO
222. re Preparation and Installation 2 25 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Figure 2 11 5 COP JTAG Port Connector TDO TDI QREQ TCK TMS SRESET HRESET CKSTP_OUT 2 4 6 Terminal to MPC8260ADS RS 232 Connection A serial RS232 terminal or any other RS232 equipment may be connected to the RS 232 connectors PA3 and PB3 The RS 232 connectors are a 9 pin female D type connectors arranged in a stacked configuration PA3 connected to SCC2 of the MPC8260 is the lower and PB3 connected to SCC1 of the MPC8260 is the upper in the stack The connectors are arranged in a manner that allows for 1 1 connection with the serial port of an IBM AT or compatibles i e via a flat cable The pinout which is identical for both PA3 and PB3 is shown in Figure 2 12 PB3 RS 232 Serial Port Connectors on page 26 Figure 2 12 PA3 PB3 RS 232 Serial Port Connectors a CD TX RX DTR GND DSR N C CTS N C Oo Un Nme 2 4 7 10 100 Base T Ethernet Port Connection The 10 100 Base T port connector P1 is an 8 pin 90 receptacle RJ45 connector The connection between the 10 100 Base T port to the network is done by a standard cable having two RJ45 8 jacks on its ends The pinout of P1 is described in Table 5 1 Ethernet Port Interconnect Signals on page 78 2 4 8 Memory Installation The MPC8260ADS is supplied with two
223. red to be directly via a flat cable connected to a standard IBM PC like RS232 connector Figure 4 5 RS 232 Serial Port Connectors PA3 and PB3 Cp h a TX RX DTR GND DSR N C CTS N C Ne 4 11 3 1 RS 232 Ports Signal Description In the list below the directions T 0 and are relative to the ADS board Le 1 means input to the Also known as MDIO port supported on the ADS 4 60 MPC8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com ADS Freescale Semiconductor Inc CD Data Carrier Detect This line is always asserted by the ADS TX Transmit Data On Port 1 Upper connector connected to SCC1 s TxD on PD30 On Port 2 Lower connector connected to SCC2 s TxD on PD27 Receive Data On Port 1 Upper connector connected to SCC1 s RxD on PD31 Port 2 Lower connector connected to SCC2 s RxD on PD28 Data Terminal Ready This signal is used by the software on the ADS to detect if a terminal is connected to the ADS board On Port 1 Upper connector connected to SCC1 s CD on PC14 On Port 2 Lower connector connected to SCC2 s CD on PC12 DSR Data Set Ready This line is always asserted by the ADS RTS 1 Request To Send This line is not connected on the ADS CTS 0 Clear To Send Port 1 Upper connector c
224. s 79 MPC8260ADS s CPM Expansion Connector 79 PS COP Conte fO Su Saat NUM DAE 86 7 9 P10 P12 P13 14 15 Logic Analyzer Connectors 88 Mach s In System Programming ISP 88 MPC8260ADS s P16 System Expansion Connector 88 MPCS260ADS Part Cist coco 94 Programmable Logic Equations sconto eget 107 U17 BCSR amp System 108 U18 SDRAM s Latch Mux Low L2 Cache Only 139 U19 SDRAM s Latch Mux High L2 Cache Only 143 Chapter 6 Schematics Introd ction opes ON 147 MPC8260 PowerQUICC Il ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Figure Number Figure 1 1 Figure 2 1 Figure 2 2 Figure 2 3 Figure 2 4 Figure 2 5 Figure 2 6 Figure 2 7 Figure 2 8 Figure 2 9 Figure 2 10 Figure 2 11 Figure 2 12 Figure 2 13 Figure 2 14 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 4 1 Figure 4 2 Figure 4 3 Figure 4 4 Figure 4 5 Figure 4 6 Figure 4 7 Figure 4 8 Figure 4 9 Figure 4 10 MOTOROLA Freescale Semiconductor Inc ILLUSTRATIONS Title MPC8260ADS Block Diagram
225. s 1 100 10 Base T Ethernet port 2 P2 12V Power Supply 3 PA3 RS232 port 2 lower 4 PB3 5232 port 1 upper 5 Expansion 6 P5 COP JTAG 7 P6 P7 P8 P9 P10 P12 P13 P14 amp P15 Logic Analyzer MICTOR Connectors 8 P11 Mach s In System Programming ISP 9 P16 System Expansion 5 1 1 Ethernet Port Connector The Ethernet connector on the MPC8260ADS is a Twisted Pair 10 Base T compatible connector It is implemented with a 909 8 pin RJ45 connector signals of which are described in Table 5 1 Ethernet Port Interconnect Signals below Table 5 1 P1 Ethernet Port Interconnect Signals Pin No Signal Name Description 1 Twisted Pair Transmit Data positive output from the MPC8260ADS 2 TPTX Twisted Pair Transmit Data negative output from the MPC8260ADS 3 TPRX Twisted Pair Receive Data positive input to the MPC8260ADS 4 N C Not connected Bob Smith terminated on the MPC8260ADS 5 6 TPRX Twisted Pair Receive Data negative input to the MPC8260ADS 7 N C Not connected Bob Smith terminated on the MPC8260ADS 8 5 1 2 2 12V Power Connector The 12V power connector P2 is a two lead 2 part terminal block connector P2 supplies when necessary 5 78 MPC8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc programming voltage to th
226. s connected to P2 4 54 MPC8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc for Flash programming The selection between VPP s voltage levels is done J7 See 3 2 14 J7 VPP Source Selector on page 31 To avoid inadvertent programming or erasure of the Flash it is recommended to set J7 between 2 3 position while P2 is disconnected so that no VPP is applied to the Flash SIMM 4 8 3 Flash and L2Cache If the L2 cache is installed the MPC8260 needs to be programmed to 60x bus mode This requires the latches for the buffered address bus to the Flash to be enabled On this revision of the ADS the 3 lowest order address lines for the Flash are provided by the BADDR 27 29 lines of the MPC8260 However BADRR29 function of the MPC8260 is multiplexed with CI Cache Inhibit function over the same pin Therefore prior to enabling the L2Cache any code residing in the Flash should be moved into the PowerPC bus SDRAM prior to changing BADDR29 function to SIUMCR 4 8 4 Hard Reset Configuration MPC8260 Revision Dependency As described in 4 1 Reset amp Reset Configuration on page 42 the Flash may provide Hard Reset con figuration programmed into it when 051 1 is set to the corresponding position See 2 3 4 Setting Hard Reset Configuration Source on page 21 As mentioned above BADDR 27 29 lines are used with t
227. ser s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 1 6 3 Flash SIMM 1 6 4 Power Low order address lines are connected to BADDR 27 29 lines This to allow operation in 60X mode However due to rev 0 X errata Power On Reset configuration with rev 0 X 8260s must be taken from BCSR Added Power On Reset connection to SIMMs Reset input to allow use of SIMMs which require external reset VDDL may now be regulated within 3 voltage ranges jumper selectable 23V to 2 7 original MPC8260 spec 1 7V to 1 9V HIP4 spec 1 8V to 2 0V 2V capable HIP4 devices 3 3V bus which drives also VDDH bus may be optionally production option regulated between 3 0 to 3 3V Better Heat Sinking for both Power Regulators 1 6 5 Communication Ports Unified ATM transceiver s receive and transmit fifo clocks ATMRFCLK amp ATMTF CLK into ATMFCLK ATM Rx and Tx indication leds are now operational only when ATM is enabled via BCSR ATMRCLK signal previously unused is connected to P4 for SRTS support When an ENG revision T ECOM boards is connected to the ADS this signal is tri stated RS232 ports 1 2 CTS lines are now controllable by S W via lines 1 6 6 Miscellaneous Changes ALE signal design is changed to allow proper operation in both Single 60 bus modes production configured Added more ground lines to 5 JTAG connector
228. ssignments ce creates ceperit Table 4 3 SDRAM DIMM 84MH2 Performance Figures Table 4 4 66 MHz SDRAM DIMM Mode Register Programming Table 4 5 Hash Memory Performance Figures essere Table 4 6 Local Bus SDRAM Performance Figures 66 7 Table 4 7 66 MHz Local Bus SDRAM Mode Register Programming Table 4 8 2 E 4 9 JBOSRODeSCHDUORS oc ra m u S A Sus huhu Table 4 10 Description Descriptions Table 4 12 Flash Presence Detect 7 5 Encoding 4 13 Flash Presence Detect 4 1 Encoding Table 4 14 EXTOOL I 0 3 Assignment Table 4 15 External Tool Revision Encoding Table 4 16 ADS Revision Encoding NE concave Table 4 17 L2 Cache Size Encoding RE Table 4 18 5 to 5 5 Description 4 19 4 BCSRG Table 4 20 BCSR7 Descriptions Table 4 21 _ JTAG Instruction Codes uideo gue tede rotate Table 4 22 Off board Application M
229. t DSyncHardReset_B NODE istype reg buffer double synchronized hard reset HoldOffCntl HoldOffCnt0 istype reg buffer data buf en hold off counter HoldOffTc istype com terminal count for that counter Power On Reset S NODE istype reg buffer synced pon reset JTAG Logic Chapter 5 Support Information 5 111 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc JtagShiftDRO istype shift data register JtagShiftDR1 NODE istype reg buffer JtagShiftDR2 istype reg buffer JtagShiftDR3 NODE istype reg buffer JtagShiftDR4 istype reg buffer JtagShiftDR5 istype reg buffer JtagShiftDR6 istype reg buffer JtagShiftDR7 istype reg buffer JtagStateO istype reg buffer state machine JtagStatel NODE istype reg buffer JtagState2 istype reg buffer JtagState3 istype reg buffer Jtag
230. t Go to www freescale com Freescale Semiconductor Inc Table 5 9 MPC8260ADSL2C Bill Of Material Reference Designation Part Description Manufacturer Part R82 Resistor 0 5 Q 1 SMD 1206 1 RODERSTEIN D25 0R50F CS 4W R83 Resistor 51 Q 1 SMD 1206 1 AW DRALORIK D25 051J S R91 Resistor 243 Q 1 SMD 1206 1 RODERSTEIN D25 243RF CS 4W R98 Resistor 110 2 176 SMD 1206 1 AVX CR32 111J T 4W R104 R106 R108 R111 155 R156 Resistor 330 Q 5 SMD 1206 1 RODERSTEIN D25 330RJCS R157 R159 R162 4W R114 R118 R120 Resistor 1 1 SMD 1206 1 4W AVX CR32 102F T DRALORIK D25001KFCS R126 Resistor 2 2 MQ 1 SMD 1206 1 RODERSTEIN D2502M2FCS 4W R127 Resistor 1 5 1 SMD 1206 1 RODERSTEIN D25 O1 R5FCS 4W R130 R143 R144 Resistor 133 Q 195 SMD 1206 1 DRALORIK D25 133RFCS 4W R137 R145 R146 R150 R160 Resistor 2 7 Q 1 SMD 1206 1 RODERSTEIN D25 2R74FCS 4W R138 Resistor 100 9 1 SMD 1206 1 RODERSTEIN D25 100RFCS 4W R147 Resistor 63 4 62 1 SMD 1206 1 DRALORIK D25 63RAFCS 4W R158 R161 Resistor 270 Q 195 SMD 1206 1 DRALORIK D25 270RFCS 4W RN2 RN6 RN8 RN9 RN10 Resistor Network 10 KO 5 8 ROHM RS8A 1002 J RN12 RN21 RN22 resistors 10 pin Common Bus RN25 RN26 RN28 RN30 RN31 RN32 RN33 RN34 RN35 RN40 RN41 RN42 RN43 RN44 51 RN52
231. ter 4 Functional Description 4 61 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 13 ADS Revision code 14 Fast Download via JTAG Optional 15 Power On Reset via JTAG Optional Since part of the ADS s modules are controlled by the BCSR and since they may be disabled in favor of external hardware the enable signals for these modules are presented at the CPM expansion connectors so that off board hardware may be mutually exclusively enabled with on board modules 4 12 1 BCSRO Board Control Status Register 0 BCSRO serves as a control register on the ADS Although it resides only over D 0 7 lines of the PPC data bus it 1s accessed as a word at offset 0 from BCSR base address It may be read or written at any time BCSRO gets its defaults upon Power On reset BCSRO fields are described in Table 4 9 BCSRO Descrip tion below Table 4 9 BCSRO Description BIT MNEMONIC Function PON DEF ATT PBI Page Base Interleaving In 60X mode 1 with L2 Cache this bit should reflect system programmer responsibility the state of PBI bit in PSDMR When active High it changes the address Muxing scheme for the SDRAM so that to match a scheme where Bank Select signals are connected below lower row address lines When Inactive the addressing scheme is such that Bank Select lines are taken from the higher order address lines above row address This signa
232. the ADS including this JTAG machine which goes back into Test Logic Reset state The JTAG EN bit in the Download Control amp Status register is reset as well Before re initializing the board there is a need to wait about 3 seconds for the board to recover The state of HESET and SRESET lines of the MPC8260 is visible via the COP JTAG connector 4 14 Power There are 4 power buses with the MPC8260 1 VDDH 2 VDDL Internal Logic 3 VCCSYN CPM PLL 4 VCCSYNI Core PLL and there are 4 power buses on the ADS Since HRESET and SRESET lines appear at the COP JTAG connector P5 it is possible to generate Hard Reset and Soft Reset directly Power On reset however may be remote generated only through JTAG 4 74 8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 1 VCC 5 bus 2 V3 3 3 3V bus 3 VDDL 2V 2 5V bus 4 VPP 5V 12V bus Figure 4 10 ADS Power Scheme ADS Logic amp Peripherals Expansion Con VCCSYN VCCSYNI VDDL VDDH MPC8260 To support off board application development two of the power buses are connected to the expansion con nectors so that external logic may be powered directly from the board The maximum current allowed to be drawn from the board on each bus is shown in Table 4 22 Off board Application Maximum Current Con sumption below
233. this line may be used for any available function of 9 D24 PC8 T S MPC8260 s Port 8 0 Parallel I O lines May be used to any of their available functions D25 PC7 D26 PC6 D27 5 D28 PC4 D29 PC3 D30 PC2 D31 D32 PCO The functions in parenthesis are MPC8260 s parallel I Os Normally connected to ATMTFCLK on the ADS 3MS bit that matter both 100 Base T and 10 Base T 5 1 5 5 JTAG Port Connector P5 is a Motorola standard COP JTAG connector for the 60X processors family It is a 16 pin 90 protected header connector with locks The pinout of P5 is shown in Table 5 5 P5 COP JTAG Connector Inter connect Signals below Table 5 5 P5 JTAG Connector Interconnect Signals Pin No Signal Name Attribute Description 1 TDO Transmit Data Output This 8260 JTAG serial data output driven by Falling edge of TCK 5 86 MPC8260 PowerQUICC ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 5 5 P5 JTAG Connector Interconnect Signals Pin No Signal Name Attribute Description GND Digital GND Main GND plane Was N C with ENG revision TDI TRST I Transmit Data In This is the JTAG serial data input of the ADS sampled on the rising edge of TCK May be connected to either
234. tiplication factor via DS1 MPC8260 s HARD Reset Configuration Source via 081 MPC8260 s MODCKH 0 3 DS1 Power On Reset Source Dependent MPC8260 s JTAG s TDI Source Selection via J5 SDRAM DIMM s Slave Address 082 MOTOROLA Chapter 2 Hardware Preparation and Installation For More Information On This Product Go to www freescale com 2 17 Freescale Semiconductor Inc Freescale Semiconductor Inc Figure 2 1 MPC8260ADS Top Side Part Location Diagram La pu MPC8260 PowerQUICC II ADS User s Manual For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc 2 3 1 Setting VDDL Level Range To support future revisions of the MPC8260 provisions are taken to provide necessary voltage levels on VDDL to match the process by which the MPC8260 is manufactured Via J1 three voltage level ranges are provided 1 When a jumper is placed between positions 1 2 of J1 a level range of 2 3V to 2 7V VDDL is selected This level matches the current specification for the MPC8260 2 W
235. to provide better noise immunity THERM 0 1 signals are detached from GND plane and available at a dedicated header J3 Reduced most MPC8260 s damping resistors to 22 Q HP Logic Analyzer POD s Shrouds may now be soldered in place BADDR lines are not active during Hard Reset Configuration Acquirement MOTOROLA Chapter 1 General Information 1 15 For More Information On This Product Go to www freescale com Reset Interrupts amp Clock MPC8260 Freescale Semiconductor Inc Figure 1 1 MPC8260ADS Block Diagram LOCAL Bus 60X Bus Add OPTIONAL Latch Mux 0 Q Res 60X Bus Data 60X Bus gt lt 3 3 lt gt 5 JTAG EE JTAG SCCU 2 be 4 5 gt lt 16 pin A 3 3 E FCC2 26 LXT970 Magnetics AE amp 2 E 5 NE _ fe 5350 lt 3 3V lt gt gt o D Buffered System Bus 2 4 2 1 16 8260 PowerQUICC ADS User s Manual MOTOROLA DATA Transceivers amp Address Latches Control amp Status Register 60X Bus buffered SDRAM 4 Mbyte 32 Bit 3 3V SDRAM DIMM 16 64 MBytes 64 Bit L2 CACHE 512K 64 Bit OPTIONAL 5V 32 Bit Flash SIMM 8 32MByte
236. types of memory modules Synchronous Dynamic Memory DIMM Flash Memory SIMM is a trademark of International Business Machines Inc 2 26 8260 PowerQUICC ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 4 8 1 Flash Memory SIMM Installation To install memory SIMM it should be taken out of its package put diagonally in its socket 025 no error can be made here since the Flash socket has 80 contacts while the SDRAM socket has 168 and then raised to a vertical position until the metal lock clips are locked See Figure 2 13 Flash Memory SIMM Insertion on page 27 CAUTION The memory SIMMs have alignment nibble near their 1 pin It is important to align the memory correctly before it is twisted otherwise damage might be inflicted to both the memory SIMM and its socket Figure 2 13 Flash Memory SIMM Insertion 1 2 Flash SIMM Socket 2 4 8 2 SDRAM DIMM Installation The SDRAM DIMM 022 is inserted in a different manner The 2 side latches are pulled aside to unlocked position the DIMM is placed in a vertical position similar to its final position between them so that the keys nibbled in the DIMM matches those on the socket and then the DIMM should be pressed evenly and firmly into its place loc
237. uding Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part Motorola and amp are registered trademarks of Motorola Inc Motorola Inc is an Equal Opportunity Affirmative Action Employer Motorola Literature Distribution Centers USA EUROPE Motorola Literature Distribution P O Box 5405 Denver Colorado 80217 Tel 1 800 441 2447 or 1 303 675 2140 JAPAN Nippon Motorola Ltd SPD Strategic Planning Office 4 32 1 Nishi Gotanda Shinagawa ku Tokyo 141 Japan Tel 81
238. uits touching HOT points around them Fail ure in doing so might result in permanent damage to the MPC8260ADS 3 2 16 ATM TX Indicator LD1 The green ATM Receive LED indicator blinks whenever the PM5350 ATM UNI is transmitting cells via the ATM port Illuminates only when the ATM transceiver is enabled BCSRI 3 2 17 ATM RX Indicator LD2 The green ATM Receive LED indicator blinks whenever the PM5350 ATM UNI is receiving cells via the ATM port Illuminates only when the ATM transceiver is enabled via 3 2 18 Ethernet RX Indicator LD3 The green Ethernet Receive LED indicator blinks whenever the LXT970 is receiving data from the 10 100 Base T port 3 2 19 Ethernet TX Indicator LDA The green Ethernet Receive LED indicator blinks whenever the LXT970 is transmitting data via the 10 100 Base T port 3 2 20 Ethernet LINK Indicator LD5 The yellow Ethernet Twisted Pair Link Integrity LED indicator LINK lights to indicate good link integrity on the 10 100 Base T port LD4 is off when the link integrity fails 3 2 21 Fast Ethernet Indicator LD6 When the LXT970 is enabled and is in 100 Mbps operation mode the yellow led LD6 lights 3 32 MPC8260 PowerQUICC II ADS User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 3 2 22 Fast Ethernet CLSN Indicator LD7 The red Ethernet Collision LED indicator CLSN lights whenever a collision
239. urst length 1 clock last data out to precharge 1 clock write recovery time extra cycle on address phase normal timing for control lines 2 clocks CAS latency C372B45A PBI in BCSRO should be Set Page Based Interleaving Refresh enabled normal operation code address muxing mode 2 A 16 17 on BNKSEL 1 2 on PSDAIO 7 clocks refresh recovery 3 clocks precharge to activate delay 2 clocks activate to read write delay 4 beat burst length 1 clock last data out to precharge 1 clock write recovery time extra cycle on address phase normal timing for control lines 2 clocks CAS latency LSDMR MB811171622A 84 Local 418AB552 Refresh enabled normal operation address muxing mode 1 A 16 18 on BNKSEL 0 2 10 on PSDA10 7 clocks refresh recovery 3 clocks precharge to activate delay 2 clocks activate to read write delay 8 beat burst length 1 clock last data out to precharge 1 clock write recovery time Internal address muxing normal timing 2 clocks CAS latency PSRT All Bus Supported Sdram PPC 21 Divide MPTPR output by 34 PSRT 1 Generates refresh every 13 4 usec while 16 usec required Therefore is refresh redundancy of 5 4 msec throughout full SDRAM refresh cycle which completes in 27 4 msec I e Application s w may withhold the bus upto app 5 4 msec in a 32 8 msec period without jeopardizing the contents of the ppc bus SDRAM DIMM 3 40
240. used by an external tool C3 GND Digital Ground Connected to main GND plane of the ADS C4 BTOLCS1 Buffered Tool Chip Select 1 L This is a buffered MPC8260 s CS6 line reserved for an external tool C5 BTOLCS2 Buffered Tool Chip Select 2 L This is a buffered MPC8260 s CS7 line reserved for an external tool GND Digital Ground Connected to main GND plane of the ADS C7 ATMEN ATM Port Enable L This line enables the ATM port UNI s output lines towards the MPC8260 An external tool using the same pins as does the port should consult this signal before driving the same lines Failure to do so might result in permanent damage to the PM5350 ATM UNI C8 ATMRST Port Reset L This signal resets the ATM 5350 external tool may use this signal to its benefit C9 FETHRST Ethernet Port Reset L This signal resets the LXT970 Ethernet transceiver An external tool may use this signal to its benefit C10 HRESET O D MPC8260 s Hard Reset L When asserted by an external H W generates Hard Reset sequence for the MPC8260 During that sequence asserted by the MPC8260 for 512 system clocks Pulled Up on the ADS using 1KQ resistor When driven by an external tool MUST be driven with an Open Drain gate Failure to do so might result in permanent damage to the MPC8260 and or to ADS logic Cll IRQ6 I Interrupt Request 6 L Connected to MPC8260 s DP6 CSE0 IRQ6 signal Pulled
241. vision compatible mode 1 6 Reserved Implemented Read as b 000000 Writes have no effect 0 7 JTAG RX FULL JTAG Receive Full Flag When this signal is active High it indicates that the 0 JTAG Download register was fully written by the Host and should be read by the download agent running on the ADS After the agent has read data from the Jtag Download Data Register this bit is cleared This bit is also cleared by either Power On Reset JTAG TAP Reset asserted TRST and by JTAG TAP reset state This bit is Read Only writing it has no effect 8 31 Reserved Un Implemented 4 12 6 BCSR7 Board Control Status Register 7 BCSR7 is used as the JTAG Fast Download I F data register Although it resides only over D 0 7 lines of the PPC data bus it is accessed as word at offset 0x1C from BCSR base During download the host loads this register with serial data through the JTAG I F The download agent running on the ADS should after polling the JTAG RX FULL flag to be asserted read the data on this register and write it to the ADS s memory BCSR7 is described in Table 4 20 BCSR7 Description below Table 4 20 BCSR7 Description Function DEF ATT 0 7 JTAG DOWNLOA JTAG Data Data shifted into the JTAG Download Data register may be read here 0 R D DATA This is a read only field Writes have no effect 8 31 Reserved Un Implemented 4 13 COP JTAG Port The COP Control Observation Port is part o
242. wn in Table 2 1 MODCK 1 3 En coding on page 21 be either boot memory BCSR on the ADS MPC8260 PowerQUICC II ADS User s Manual For More Information On This Product Go to www freescale com MOTOROLA BCSR FLASH BCSR FLASH MODCKHO MODCKHI MODCKHI MODCKHI MODCKHI r ru MODCKH2 MODCKH2 MODCKH2 MODCKH2 MODCKH3 MODCKH3 MODCKH3 MODCKH3 MODCK1 MODCK2 MODCK2 MODCK2 MODCK2 MODCK3 MODCK3 MODCK3 MODCK3 Freescale Semiconductor Inc Figure 2 4 DS1 Description DS1 40MHz Factory Set 66MHz Factory Set Table 2 1 MODCK 1 3 Encoding 2 3 4 Setting Hard Reset Configuration Source The Hard Reset configuration word read by the MPC8260 while HRESET is asserted may be taken from two sources 1 Flash Memory SIMM fact 8 Hard Reset configuration words are read by a configuration master however only the first rele vant for a single MPC8260 MOTOROLA Chapter 2 Hardware Preparation and Installation 2 21 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 BCSR For additional information as for the contents of the Hard Reset configuration word see 4 1 2 4 Hard Rest Configuration on page 43 When DS1 1 is OFF
243. y map while its associated FCC is detached and may be used off board via the expansion connectors The UNI interrupt output is connected to the MPC8260 s DP6 CSEO IRQ6 pin This allows for interrupt based handshake between the MPC8260 and the ATM UNI in addition to a polling based handshake This is an open drain output and is pulled up on the ADS It is also appears at the CPM expansion connector to be shared with an external tool interrupt request See also 4 2 Local Interrupter on page 46 The ATM transceiver reset input is driven by HRESET signal of the MPC8260 so that the UNI is reset whenever a hard reset sequence occurs The UNI may also be reset by either asserting ATM RST bit in BCSRI see Table 4 10 BCSRI Description on page 64 or by asserting 17 the RESET bit in the Master Reset and Identify Load Meters register via the UNI m p i f The UNI transmit and receive clocks is fed with a 19 44 MHz 20 ppm clock generator 5 V powered while the receive and transmit fifos clocks are provided by the MPC8260 using the same clock CLK11 The ATM transceiver has Transmit and Receive visual indications These however are enabled by setting the following bits in the UNI POPC register offset 0x68 from UNI base TRAFIC to 1 ALARM to 0 TOGGLE l1 to b11 This will generate 100 msec pulse over and OUTO pins of the UNI attached to LD2 and 1 01 re spectively indicating a successful ATM cell receive

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