TELFOR 2006
Contents
1. 0 4 to 0 5 BIMHz p ty lus 1 The measured rise time is commonly related to the oscilloscope rise time and the real rise time using the formula measured tserilloscope T treal The relationship 2 is useble only if tneasurea t 7 8 Otherwise the errors make the correction useless The oscilloscope rise time is form its tehnical manual 400ps 6 The real rise time is shown in Tabel 3 TABLE 3 REAL RISE TIME Measured Oscilloscope Real rise rise time rise time time ps ps ps 456 178 IV CONCLUSION In managing short times extra care should be taken The oscilloscope s bandwidth should be at least five times higher than the fastest clock rate in the design Otherwise in order to make accurate edge speed measurements on the signals you will need to determine the maximum practical frequency present in the signal REFERENCES S Popescu A Gontean LLie Comparing FPGA behavioral simulation post routed simulation with real life experiments Accepted for publication at SIITME2009 XUP Virtex II Pro Development System User Manual Xilinx 2009 Virtex II Pro User Guide Family Xilinx 2004 J Wakerly Digital Design Principles and Practices Third Edition 2006 ISE 10 1 Quick Start Tutorial Xilinx 2008 LeCroy WaveSurfer Xs Series Oscilloscope Operator s Manual 2008 Relating wideband DSO rise time to bandwidth Lose the 0 35 Agilent 55W 18024 2 22. 009 Understanding Oscilloscope Bandwidth Rise Time and Signal Fidelity Tektronix 2002 1 2 3 4 5 6 7 8
3. 17th Telecommunications forum TELFOR 2009 Serbia Belgrade November 24 26 2009 VIRTEX II Timing Simulation vs Reality Silvana POPESCU Aurel GONTEAN Abstract The goal of this paper is understanding the performance capability of a modern FPGA in a post layout simulator using a typical design For this an eight phase generator was used as a test circuit and the delays between the outputs have been evaluated and corrected Keywords FPGA rise time simulation VHDL I INTRODUCTION FPGA Field Programmable Gate Array is an Ain FPGAs contain programmable logic components called logic blocks and a hierarchy of reconfigurable interconnects that allows the blocks to be wired together To define its behavior the FPGA is programmed generally using a hardware description language HDL The most common language is VHDL VHSIC Very High Speed Integrated Circuits Hardware Description Language VHDL is used for two different goals simulation of electronic designs and synthesis of such designs Synthesis is a process where a VHDL is compiled and mapped into an implementation technology such as a FPGA Also VHDL allows the description of a concurrent system unlike some programs in which the code run sequentially 1 II HARDWARE AND SOFTWARE RESOURCES A Virtex II Board The Virtex II Pro Development System provides an advanced hardware platform that consists of a high performance Virtex II Pro Platform FPGA surrounded
4. ase waveform generator is shown below OUTIS el fed fel ie el el pa Ihe j entity 8phase is port clk in std_logic reset start restart in std_logic OUT out std_logic_vector 1 to 8 End 8phase architecture 8phase_arch of 8phase is signal R_W std_logic_vector 1 to 8 signal Aux std_logic begin process clk R_W begin if clk event and clk 1 then if reset 17 then Aux lt 1 R W lt 0 0 0 0 0 0 0 0 elsif R_W 0 0 0 0 0 0 0 0 or restart 1 then Aux lt 1 R W lt 1 0 0 0 0 0 0 0 elsif start 1 then Aux lt not Aux if Aux 0 then R W lt R_W 8 amp R_ W 1 to 7 end if end if end if OUT lt not R_W end process end 8phase_arch R_W is an internal active high signal vector used for reading and writing what eventually becomes the circuit s output This signal is inverted to obtain the required active low output signal vector Aux is an auxiliary state bit to keep track of the two states within each phase The OUT i and Aux signals are all outputs from the flip flops clocked by the same clock clk 4 This design is tested in simulation first behavioral and then post routed B Behavioral Simulation The behavioral simulation is used to test the design functionality The behavioral simulation is illustrated in fig 3 Signal clk is th
5. by a comprehensive collection of peripherial components that can be used to create a complex system and to demonstrate the capabilities of the Virtex II Pro Platform FPGA Based on the Virtex II Pro FPGA the board can function as a digital design trainer a microprocessor development system or a host for embedded processor cores and complex digital systems Features of Virtex II board Virtex II Pro FPGA with PowerPC 405 cores Up to 2 GB of Double Data Rate DDR SDRAM System AC controller and Type II CompactFlash connector for FPGA configuration and data storage Embedded Platform Cable USB configuration port S P PhD student Faculty of Electronics and Telecommunication Politehnica University of Timisoara Romania phone 4 0724214627 e mail silvana popescu Q etc upt ro A G Applied Electronics Departament Faculty of Electronics and Telecommunications Politehnica University of Timisoara Romania phone 4 0745119858 e mail aurel gontean etc upt ro High speed SelectMAP FPGA configuration from Platform Flash In System Programmable Configuration PROM Support for Golden and User FPGA configuration bitstreams On board 10 100 Ethernet PHY device Silicon Serial Number for unique board identification RS 232 DB9 serial port Two PS 2 serial ports Four LEDs connected to Virtex II Pro I O pins Four switches connected to Virtex II Pro I O pins Five push buttons connected to Vir
6. e clock used in the application of the eight phase generator signals start restart and reset are the input signals and the OUTTi signals are active low phase outputs 5 The signals in the selected aria are zoomed and shown in fig 4 As expected fig 4 demonstrates that the behavioral simulation does not point out any delays C Post Route Simulation Unlike the behavioral simulation in the post route simulation the delays became noticeable The encirclements from fig 5 are the delays introduced by the post route simulation One of these delays is shown in fig 6 namely the delay between the third and the fourth signal Current Simulation Tame 1000 ns i clk el reset e start e restart E Sa ours ioe OLIT A ex OUT exl cuT 3 ex OUTA xl OUTS ix OUTE ei OLT 7 ex OUTS el period e duty cycle ex offset Fig 3 Behavioral Simulation Current Simulation Time 1000 ns ixl clk g l reset ex start ex restart Em Sa ourp as e OLIT 1 exi CUTE ix OLIT 3 e OUTA ixl OUTS ex OUTIS ixl OLIT 7 i OUTS e period ex duty cycle xl offset SHES Shree zh 4 a m a oO Wy aj eh oh oh oh 2h OO E tT ind F 7 W Dao m s i 650 ng 550 ns Shr 5680 ns 680 ns YOO ns 20 0 OOOO E 0 5 DOOCUOOCHO 710 ns I Eb qubd ee LLL Z1 Oooo SE ae T20 ns 30 ng Sh7F amp hDF Shes amp hFE
7. gh performance digital oscilloscope In order to obtain results the eight signals were routed to the two 40 pin right angle connectors 6 The first measurement was with the eight signals routed to the left expansion connector and the second measurement was with the signals routed to the right connector Fig 7 illustrates the delay between the third and the fouth signal The delay is estimated with the skew function of the digital oscilloscope The skew function calculates the delay between two signals in the following way time of clock edge minus time of the nearest clock2 edge which represents exactly the delay between the two signals P4 p5 Measure value status P1skew C1 C2 606 ps P2 ampl C1 2230 V P3 ampl C2 2 0902 V Timebase 12ns Trigger MEB 20 0 nsidivj Stop 250mV 2 5 GS sfEdge Negative Fig 7 The delay between the third and the fourth signal 5005 Computing all the delays between every two consecutive signals Table 2 illustrates some of the most effective delays TABLE 2 DELAYS AT THE TWO 40 PIN CONNECTORS 1 40 pin 2 40 pin connector connector ps ps Post route simulation ps 758 E Correcting the Measured Rise Time Rise time refers to the time required for a signal to change from a specificed low value 10 to a specified high value 90 The relationship between the rise time and the bandwidth of a digital oscilloscope is given by N o EN N
8. sSnhaestr TAD ns Sh g Fig 4 Zoomed Behavioral Simulation Current Simulation Time 1000 ns exl clk el reset e start e restart m ga ourpm as e OLIT 1 e OUTE gx OLITES exl OUTA gx OLIT 5 e OLIT B gx OLIT 7 e ouT s e period el duty cycle e offset Fig 5 The Post Route Simulation e hF tnt Current Simulation Time 1e 06 ps ion clk e reset el Start ex restart E Wd cump a exi OLT 1 e UTZ ei OUTS ix OUTA ixl OUTS ix OLIT B exi OLIT 7 io OUTS ex period ex duty cycle exl offset PM psz88350 ps ahcr ai ok aj GO H aj aj j a t a i ad a ps enor Fig 6 Zoomed delayed detail between out 3 and out 4 157 za S as ps Eu ps 2000 O00 gu 5 1007 004010 2 ra ps IL Lg enor 20000000 5 10000000 225 nns 25 ns 2795 ns 300 ns 325 ns 350 ns 375 ns 400 ns 475 n NE ee ec 1 eie rane toe 3571 cs T5 k Tw sr ier ie m l mE Tete ee e o a ee Ahe r SS N Se JE z TE i L Snr I B amp hDF B amp hEF t B amp hF7 i a amp a hFB ul ShFD 20000000 0 5 10000000 VINE M M 286650 ps 2867 The delays between every two consecutive signals are listed in Table 1 TABLE 1 DELAYS BETWEEN CONSECUTIVE SIGNALS Delays ps 238 527 104 376 117 208 106 176 Signals D Experimental Results Experimental results were acquired with a LeCroy WaveSurfer Xs Series Oscilloscope a hi
9. stem architectures to be synthesized next generation connectivity standards to be seamlessly bridged and complex hardware and software systems to be co developed rapidly with insystem debug at system speeds Together these capabilities usher in the next programmable logic revolution 3 C Xilinx Web Pack ISE ISE WebPACK from Xilinx is a design software for FPGA design solution for Linux Windows XP and Windows Vista ISE WebPACK is used for FPGA and CPLD design offering HDL synthesis and simulation implementation device fitting and JTAG programming III DESIGN IMPLEMENTATION AND TESTING In order to verify the limits of the ISE Web Pack Suite the eight phase generator has been simulated implemented and tested A Eight phase Waveform Generator The eight phase generator is an application of shift registers in ring counters A shift register is a cascade of flip flops all sharing the same clock which have their inputs and outputs connected together resulting in a circuit that shifts by one position the information stored in it at every transition of the clock input Ring counters are implemented using shift registers so that the output of the last register 1s fed to the input of the first register Figure 3 illustrates a ring counter on 8 bits OUT QUTD OUT OUT oUT 7 OUT OUTE CLEAR ran Les d ar Tis Cam TL rar ras ron Fig 2 A 8 bits ring counter The VHDL program of the eight ph
10. tex II Pro I O pins Six expansion connectors joined to 80 Virtex II Pro I O pins with over voltage protection High speed expansion connector joined to 40 Virtex II Pro I O pins that can be used differentially or single ended AC 97 audio CODEC with audio amplifier and speaker headphone output and line level output Microphone and line level audio input On board XSGA output up to 1200 x 1600 at 70 Hz refresh Fig 1 Virtex II Board Three Serial ATA ports two Host ports and one Target port Off board expansion MGT link with user supplied clock e 100 MHz system clock 75 MHz SATA clock Provision for user supplied clock e On board power supplies e Power on reset circuitry e PowerPC 405 reset circuitry 2 B Virtex II Pro Family FPGA The Virtex II Pro Virtex II Pro X family is the first FPGA family to incorporate both serial transceiver technology and a hard processor core within a general purpose FPGA device This is significant for new high bandwidth embedded processing applications such as packet processing where both high device I O bandwidth and high performance processor cores are needed together The Virtex II Pro Virtex II Pro X family marks the first paradigm change from programmable logic to programmable systems with profound implications for leading edge system architectures in networking applications deeply embedded systems and digital signal processing systems It allows custom user defined sy
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