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1. O O O O O O O O O O a gt RF LEVEL AM 6D 7 TROUBLESHOOTING AND REPAIR RF LEVEL AM 8 Unleveled Condition 6D 8 If the problem is in a specific frequency band or bands and other bands work properly check band control signals and band switches See Table 6D 1 for band control signal state definition and Table 6D 2 to determine pin diode states for various frequency bands A specific band or bands problem will most likely involve a divider a switch a filter or a control signal If all of the frequency bands are affected the leveling loop or associated controls and inputs are probably at fault First check the signal at the output connector J16 of the Premodulator PCA As the instrument frequency is incremented from 15 to 1056 MHz acorresponding signal should be seen at J16 The levels typically range from 6 dBm at 15 MHz to 4 dBm at 1056 MHz with alow of about 2 5 dBm at 256 Mhz High harmonic levels will be seen in the frequencies below 64 MHz Lack of a proper signal here might involve U4 05 Q6 on the Premodulator PCA The input signal to the Premodulator PCA at J5 from the Sum Loop VCO A9 should also be checked The level here should be approximately 7 dBm
2. T oor 5 o 5 rro 9 op 5 gt lt oon dooooooo gt lt lt lt Oy H N N N Oust I I LN core Wt 5888882 88688885 gt x eoe 10 10 QE QI QI 00 10 10 10 10 HSI NL IL QE ILL NINE N V uz oooooof 0 QN NONO NANAS o00002 ooooO2 ooooo l ooooo 2 5 oooooog OT 2 9 e v c H ont naur 114 gt oooooo oOoooooo 2 a 2on oOooooooloooooo oooooo errr er er ele eer eee E 2 oOooocoooo oooooo
3. n 31 133 163 01 102 111 03 106 108 07 113 9 120 122 oo Table 7 12 A12 Sum Loop cont 00 LOOPPM 5 100 iH 011277 ov I 1258 100PPM 5W 100PPM B RES V RES RES C RES 10K 1 RES CF 22M 5 RES F 392 1 TERM FASTON i TAB E 1 Fr Fx P rz A FT Foe AMP SELEC IC STIL DUAL D C BPLR MONOLIT C VOLT AMP LO NO C DMOS FET QUA Jg ROM SUM LOOP C COMPARATOR D C COMPARATOR H C LSTTL RETRG RES NET DIP 14 in 9 1K TE 0 1251 100 IXER DOUBLE BALANCED 5 IXER DOUBLE BALANCED 2 500MHZ DOUBLE BALANCED 0 1251 100 0 125 100PP 0 125W 100 0 1251 100 0 125W 100PPM 5 0 1251 100 0 125W 100PPM 25W 25 SW 100PPM D 1258 100 de 125W 100PPM 100 511 100 oW 00 0 25W 100PPM 0 25W 0 125W 100PPM 110 SOLDER 1000 MHZ 500MHZ TED GBW 600KHZ F E EDG TRG W SET amp CLR HIC MICROWAVE AMP REG FIXED 5 VOLTS 0 1 AMPS IC COMPARATOR QUAD 14 PIN DIP ISE 8 PIN DIP D SWITCH CMOS
4. 0 01 to 1056 MHz in 7 bands 0 01 to 14 999999 MHz 15 to 31 999999 MHz 32 to 63 999999 MHz 64 to 127 999999 MHz 128 to 255 999999 MHz 256 to 511 999999 MHz 512 to 1056 MHz 1Hz Same as reference See REFERENCE The unit operates on an internal 10 MHz TCXO The Frequency variation will be 2 ppm peak to peak over the temperature range of 0 to 50 C Aging rate of lt 1 ppm year typical Internal reference signal 10 MHz available at rear panel REF OUT connector level 0 dBm terminated in 50 ohms Frequency stability after 2 hour warmup is lt 0 05 ppm hour at 25 C 5 Accepts 1 2 or 5 or 10 MHz signal Level required is 0 2 to 2 0 Vrms into 50 ohms termination NOTE Choice is internal switch selectable 1 2 or5 MHz AMPLITUDE 3 1 2 DIGIT DISPLAY ACCURACY 23 50 C ACCURACY 0 to 50 C 19 to 140 dBm for Frequency lt 512 MHz 16 to 140 dBm for Frequency gt 512 MHz 0 1 dB lt 1 or 1 nV in volts Annunciators for dB dBm dBf V mV uV dB uV and EMF 1 dB from 19 to 127 dBm and for F from 0 4 to 512 MHz 1 dB from 16 to 127 dBm and for F gt 512 MHz 1 5 dB from 19 to 127 dBm and for from 0 4 to 512 MHz 1 5 dB from 16 to 127
5. pei Table 7 5 A4 Sub Synthesizer cont DESCRIPTION INDUCTOR 470UH SOCKET SINGLE PWB FOR SOCKET SINGLE PWB FOR PIN SINGLE PWB 0 025 COMPONENT HOLDER 5 6 5MHZ SHLD 042 049 PIN 042 049 PIN 50 JUMPER REC 2 POS 100CTR 025 SQ POST TRANSISTOR SI TRANSISTOR SI TRANSISTOR SI TRANSISTOR SI RES MF 4 32K RES 10K 18 RES 1K 13 0 125W 100 RES 1 37K 418 0 125W 100PPM RES VAR CERM 500 108 0 58 RES CF 51 5 0 125W RES CF 100 0 25W RES CF 510 1 53 0 250 RES CF 200 0 25W RES CF 100 0 125W RES CF 36 5 0 en RES 270 855 0 25W RES MF 04K W PNP HI SPEED SWITCH VMOS PWR 10 237 10 PN SMALL SIGNAL PN SMALL SIGNAL 5 125W 100PPM 0 1251 100PPM Q 5 RES CF 1K 5 0 RES CF 220 5 0 25W RES MF 10K 13 0 125W 100 RES CF 10K 5 0 25 RES MF 4 1 5 4 5 0 125W 100 RES MF 19 1K 1 0 125W 100 RES MF 49 9 1 0 125W 100PP RES 47 5 4 12 0 125 100PP RES CERM 100 4 55 125W 200 1206 RES CERM 75 5 125W 200 1206 RES CERM 180 4 52 125W 200PPM 1206 RES CERM 27 4 55 125W 200PPM 1206 RES CF 15 4 55 0 125W RES CF 210 4 55 0 25W RES CF 180 4 52 0 250 RES
6. 6E 12 FM Mod Rate 5 6E 15 List of Illustrations FIGURE TITLE PAGE 3 1 Basic Structure of Calibration 3 2 3 2 Structure of the AM Calibration 3 6 3 3 Basic Structure of FM Calibration 3 9 3 4 Basic Structure of Level Calibration 3 13 3 5 Basic Structure of the Reference Oscillator Calibration 3 16 4 1 6 4465 eo 4 4 4 2 Alternate Level Accuracy Test Equipment A2 6 1 Instrument Block 2222222222222222221 6 2 6 2 Instrument Troubleshooting Tree 6 3 6A 1 Power Supply Block 6A 2 6B 1 Controller Block Diagram 6B 2 6B 2 Address Decoding B REM 6B 7 6C 1 Frequency Synthesis Fault 41 6C 2 6 2 Sub Synthesizer Block 6C 3 6C 3 Triple Modulus 2 222222
7. ez p 59 6080 1602 7 5 4 Sub Synthesizer 7 31 REPLACEMENT PARTS REFERENCE DESIGNATOR gt 5 gt 1 1 59 o gt Oy gt Mp Co DOH CO IS I 38 42 50 51 02 29 p pr gt 25 28 Ww CO cC ER C4 C4 202 0202 CO C C C oo con 7 30 5 Table 7 6 A5 Coarse Loop VCO See Figure 7 6 CAP PORC 1 8PF 0 1PF 50V 0505 CAP PORC 2 0 1PF 50V 0505 CAP CER 22PF 10 50V COG 1206 CAP CER 100 5 50V C0G 0805 CAP TA 2 2UF 20 25V CAP CER 4 7PF 0 25PF 50V C0G 0805 CAP CER 5 6P 0 25 50V COG 0805 CAP CER 330PF 208 90V 0805 CAP CER 8 2PF 4 0 5PF 50V C0G 0805 CER 3 6PF 4 0 25PF 50V COG 0805 CER 2 0 25PF 50V COG 0805 AL 470UF 20 16V SOLV PROOF AL 1006 20 63V SOLV PROOF DIODE SI VARACTOR PIV 30V 18PF MLF DIODE 51 50 PIN RF SWITCHING 50723 SOCKET SINGLE PWB FOR 042 049 PIN SOCKET SINGLE PWB FOR 0 034 0 037 PIN CONN COAX SMA PWB OR PAN
8. Jas jn E TB 1 8 6080 1601 Figure 7 11 A11 Modulation Control 7 49 REPLACEMENT PARTS 7 50 REFERENCE DESIGNATOR A gt NUMERICS gt 5 ps wN OAM SDF Co gt ot 52 Table 7 12 A12 Sum Loop PCA See Figure 7 12 CAP 2 t 0 25PF 50V COG 0805 CAP CER 100PF 2 100V C0G CAP CER 3 9PF 0 25PF 100V 0 CAP POLYES 0 1UF 20 50V CAP CER 4 7 4 0 25 50V CAP CER 10PF 2 100 COG CAP 0 01UF 20 50V Z C0G 0805 5U CAP CER 4 7PF 0 25PF 100V COH CAP CER 5 50V COG 0805 CAP CER 47PF 5 50V COG CAP CER 0 010 20 50V X 2UF 20 20V Jd Jg 180PF 4 55 50V COG 100 50V 06 2 100V COG CC gu Exi Exd Ex Ex 24 Ex 69 24 24 V GR 24 517 SOLV 6 3V 1007 m Uu duse ov ov ovo ded POLYES 10 10 50V POLYES 2200PF CAP POLYES 0 105 10 50V POLYES 0 47UF CAP TA 0 4 TUF 208 35V 00 20 63
9. 2 3 3 1 Front Panel Controls for AM Calibration 3 5 3 2 Remote Programming Commands for AM Calibration Procedure 3 7 3 3 Front Panel Controls for FM Calibration 3 8 3 4 Remote Programming Commands for FM Calibration Procedure 3 10 3 5 Front Panel Controls for Level Calibration 3 12 3 6 Remote Programming Commands for Level Calibration Procedure 3 14 3 7 Front Panel Controls for Reference Oscillator Calibration Procedure 3 15 3 8 Remote Programming Commands for Reference Oscillator Calibration Procedure sees 3 17 4 1 Recommended Test 4 2 4 2 High Level Accuracy Test 4 7 4 3 High Level Accuracy Test Conditions 4 8 4 4 Modulation Tests 5 4 17 4 5 AM Test 19 6 1 Module Exchange 5 6 4 6 2 General Self Test Results eso bp 6 8 6 3 Digital Test 5 4 6 9 6 4 Test Conditions
10. Wee vot ee 3 3 3 5 AM CALIBRATION 2 3 4 3 6 Front Panel AM Calibration 3 4 3 7 Remote Calibration Procedure 3 6 i continued on page ii TABLE CONTENTS continued SECTION TITLE PAGE 3 8 FM CALIBRATION ds ect PEL EET I Lea 3 7 3 9 Front Panel FM Calibration 3 8 3 10 Remote FM 3 9 3 11 RF LEVEL 3 10 3 12 Front Panel Level Calibration 3 11 3 13 Remote Level Calibration 3 13 3 14 REFERENCE OSCILLATOR CALIBRATION 3 14 3 15 Front Panel Reference Oscillator Calibration Procedure 3 15 3 16 Remote Reference Oscillator Calibration Procedure 3 16 4 PERFORMANCE 5 4 1 4 1 A 4 2 TEST 41 4 3 POWER ON 5 44 4 4 FREQUENCY ACCURACY 5 4 5 4 5 SYNTHESIS 4 5 4 6 HIGH LEVEL ACCURACY 5
11. 4 6 4 7 MID LEVEL ACCURACY 5 4 8 4 8 LOW LEVEL ACCURACY TEST 4 9 4 9 ALTERNATE LEVEL ACCURACY 5 4 10 4 10 FLATNESS 5 13 4 11 5 4 14 4 12 HARMONIC AND LINE RELATED SPURIOUS TEST 4 15 4 13 PHASE NOISE AND NON HARMONIC SPURIOUS TESTS 4 16 4 14 MODULATION 5 5 4 17 4 15 VOLTAGE STANDING WAVE RATIO VSWR 5 5 4 23 4 16 PULSE TESTS 4 24 5 ACCESS PROCEDURES ere tee expe qug 5 1 5 1 INTRODUCTION AND 5 5 1 5 2 LOCATION OF MAJOR 5 5 3 5 3 ACCESS INSTRUCTIONS E C eoa 5 3 5 4 Removing the Front Panel 5 3 5 5 Removing the Rear Panel 5 5 3 5 6 Removing the A2 Coarse Loop 5 4 5 7 Removing the Sub Synthesizer VCO 5 4 5 8 Removing the A4 Sub Synthesizer 5 5 5 9 Removing the A5 Coarse Loop VCO 5 5 5 10 Removing the Mod Oscillator 5 5
12. AMP QUAD JFET TNPUT 14 PIN DIP FLUKE STOCK 0 831526 816249 916249 831982 851766 851714 212633 698688 386557 698720 698720 524058 63186 411030 32091 54229 14785 gt eoD 86676 483438 FRS SPLY CODE OR GENERI 40402 12982 04222 62643 62643 04713 04713 04713 65940 04713 91423 00779 89536 24159 24159 00779 21014 04713 59124 22526 01295 10 15 column indicates static sensitive part MANUFACTURERS PART NUMBER MKT1823104056 8 RPE121 911XTR103M50V 4 SR295E224 C TYPE KRE35VB22RMOX5RP KRESOVB4R7M5X5RP 972 N960B N4448 320911 R82 R47 645991 3 PS6562 D262 PS6560 1 4 511 JB N750A 9505B B 0256 872 1 4 472 JB 1 4 751 J B 1 4 103 JB MF554220F 1 4 102 J 1501 56 C 9 www UJ UJ tz 9 TL084C N755A SR4348RL REPLACEMENT PARTS o Co CO odo OIF 7 69 REPLACEMENT PARTS x EB mt f 6080 1604 Figure 7 17 A7 Relay Driver PCA 7 70 REPLACEMENT PARTS Table 7 20 A21 Attenuator See Figure 7 18 N REFERENCE FLUKE MFRS MANUFACTURERS 0 DESIGNATOR STOCK SPLY PART NUMBER TOT T A NUMERICS 5 NO CODE OR GENERIC TYPE QTY E C po
13. OL 9NILV T3H IN31808d AHONW3W diNO9 1v9 IN3180ud V 167 67 967 LLY 207 407 507 607 53909 40 1945 ZOE 3l 0 99 82 29 39215 Wa ZHN 08 NI ZHN 086 078 dOO1 WNS NI ZHN 26 9 01 LO ZHN 08 3unsvaw 3unsvaw 26 cre Lye dOO1 WAS QNV Qquvoa dOO1 WAS 40709 1 99 Vavd ZHN 01 110 ZHN 08 110 ZHN 096 076 AYNSVAW 606 006 Erz 001 ASHVOO QNV 34001 38 21 09 16 09 Vuvd 110 ZHN 26 91 JYNSYIN 9 9 474 H3ZIS3HLNAS 8hnS QNV YAZISSHLNAS NS 206 Lhe 656 OZE SISSHLNAS AONANOAYS Figure 6C 1 Frequency Synthesis Fault Tree 6C 2 FREQUENCY SYNTHESIS TROUBLESHOOTING AND REPAIR esn 3univuavno 3AULOV 001 01 61041385 20111 o ssa3udav v 5123135 ZHY 02 01 asuvoo OL SHOLV1 NAS GNS OL 7 ape viva 5193135 2 290 ASHVOO OL pes en ant ONIH33lS lt ova 1 u3vosaud 18 01 V smnaonw Me en 1258 103185 sng 3007 viva 3SHVOO OL lt lt a ova 26 19 8 E un 39V L10 z 9en sen ZHIN 02 01 8109188 zzZ zLo
14. DOR COP COND Cn gt I REFERENCE DESIGNATOR 3 18 107 10 39 48 49 103 104 15 44 22 28 mo 4 20 40 64 73 CO CO p DOF DOW Yor N 1 O3 01 c enm 60 61 81 84 94 216 277 67 85 139 300 302 305 310 303 308 2 2 11 4 5 12 3 8 9 58 10 21 22 1 2 Du pu Cd Cd Cd Cd CH V I D X DO UO UO DOM OOo ER E ES E E E E A gt NUMERICS gt 5 ox ox Table 7 10 A10 Premodulator DESCRIPTIO 10 1000MHZ 12UH UCTOR 0 05609 UCTOR 0 04 70H UCTOR 0 0390 UCTOR 0 08208 UCTOR 0 068UH UCTOR 0 02208 UCTOR 5 6UH 0 68UH 10 221MHZ SHLD HZ 0 LOOOMHZ 1000 2 LOOOMHZ 1000MBZ 20 1000MHZ 5 130MHZ Z2o000000U TRA SINGLE PWB 0 S SI NPN SELECTED IEBO SMALL SIG TRANSISTOR SI PNP T092 TRANSISTOR SI PNP T092 TRANSISTOR vin PN HI FREQ SMALL SIGNL RES CERM 220 5 21251 200PPM 1206 RES CERM 22 5 41251 200 1206 RES CF
15. 30153134 66 vc HOLVANALLV ZHWZZ ZE OL 099 YHOLVINGOW 104100 0 889 WV GE o o E 44 1 11 VOd LAdLNO 08 86 _ 952 081 0 dOO1 WNS ZUW 9501 uo1vindoWwaud Figure 6D 2 RF Level Block Diagram 6D 2 TROUBLESHOOTING AND REPAIR RF LEVEL AM RF LEVEL CIRCUIT DESCRIPTION 6D 3 The circuits on the A8 Output PCA the AIO Premodulator PCA and the A11 Modulation Control PCA are interrelated and are described here as a unit The Premodulator receives a 480 to 1056 MHz RF signal from the Sum Loop VCO A9 The Premodulator PCA uses divide by two circuits and switches to develop a 15 to 1056 MHz RF signal This signal is applied to the Output PCA The Output PCA contains the level AM modulator generates a detected voltage for the leveling loop develops the 0 01 to 14 999999 MHz HET BAND signal contains the pulse modulator circuits and provides the final amplification of the 0 01 to 1056 MHz output signal The Modulation Control PCA distributes DC power and control signals to the Output PCA the Premodulator PCA the FM PCA and the Sum Loop PCA It also controls and distributes internal and external modulation signals for AM FM 9 and Pulse modulation The Output Assembly provides a 0 01 to 1056 MHz RF signal to the A20 Attenuator RPP Assembly The Attenuator RPP
16. 0 9 H1OAHOOD Q3HOLIMS S01 1010 V OsId 9020 5021 050 7 001 34001 ASYVOO 90 eovn wns 902 5020 s 933308 ADV 7 E NIVO HOLON ZHW ONIH33IS H3ZIS3HINAS 8hs sor ONIH331S 1020 ONIH33IS dOO 3SHVOO 4090 Woud ZHW OF Figure 6C 7 Coarse Loop Block Diagram 6 21 TROUBLESHOOTING AND REPAIR FREQUENCY SYNTHESIS The steering voltage from the DAC on the Sub Synthesizer PCA J1 16 is amplified and filtered 0207 before it is sent to the Coarse Loop 715 This stage 15 a 500 Hz active Bessel filter The discriminator measures the frequency noise of the VCO and generates a correction signal to reduce the noise A portion of the RF output from the Coarse Loop VCO P2 is amplified U402 and fed into a two stage limiting power amplifier 0405 6 The output of the amplifier is filtered C422 6 CR402 3 This filter is switched at 712 MHz the same point as a VCO band change An op amp U209 drives the pin diode switches 402 3 The output power from the filter is approximately 20 dBm to the 90 degree power splitter on the Discriminator Board A25 The outputs ofthe power splitter are connected to the LO input ofthe mixer U404 and to the delay cable The other end of the delay cable is conne
17. 16 PIN 8 RES 10K 5 500710 91637 MDP1603103J Z 502 601 602 RES NET SIP 6 PIN 5 RES 910 2 459974 91637 5 08 01 5116 An in S column indicates a static sensitive part 7 24 DO REPLACEMENT PARTS e j e 9 719190 335 119130 335 1M 1082 323 RR 6923 E 5924 Pi BB e 9027 ESO COS 5 a E 5 500900 as T OnE ud m o ds 322 quito Gn Erg amp 5141 NO 71815 Ed XS 1 37805 0130 XS T 31926 37805 718130 710130 7 25 Figure 7 3 2 Coarse Loop REPLACEMENT PARTS 7 26 RE DE JEE EE FERENCE SIGNATOR gt gt 5 1 2 6 3 9 4 5 11 36 32 7 10 12 23 27 29 31 13 16 14 15 17 18 19 20 21329 28 34 35 37 4 5 8 2 2 5 6 7 4 6 8 2 1 3 1 4 10 2 6 3 5 7 8 9 AT 2 2 13 14 15 16 17 20 18 19 22 23 24 1 2 3 4 Ci DJ UJ uj ud auo 5 Table 7 4 A3 Sub Synthesizer VCO See Figure CAP CER 1000PF 4 208 100V X7R CAP CER 100PF 5 50V C0G 0805 CAP CER 10PF 4 52 50V C0G 0805 CAP POLYES 0 1UF 4
18. 2 100V COG 000 4 108 50V COG 1206 3 0 5 50V 06 0805 CAP CER 4 CAP CER CAP CER CAP CER 2 CAP CER 2 CAP CER CAP TA 2 CAP CER TA 0 CER 2 1 2 0 4 TPE 2 100V C0G 50 5 50V C0G 0805 2 0 25 100V 2 1007 COG 2 100V COG PF 52 50V COG 0805 0 F 20 207 QOPF 20 100V 7 20 35V 9PF 4 0 25PF 1007 0 01UF 4 105 50V X7R 1206 CAP 39UF 20 6V CAP CER 68PF 2 100 06 CAP CER 2 100V COG CAP CER 6 8PF 1 0 25PF 100V COH CAP 2 50V COG CAP CER 220PF 2 100 06 CAP CER 47PF 4 25 1007 COG CAP TA 2 2UF 4 205 20V CAP CER 470PF 20 1007 CER 1 8PF 0 25PF 006 0805 CAP CER 8 2 0 25PF 100V COH CAP CER 22PF 4 52 50V COG CER 12PF 23 100V COG CAP CER 39PF 2 100V COG CAP CER 000 10 50V 0805 CAP CER 5 50V C0G 0805 CAP AL 10002 203 167 SOLV PROOF CAP PORC 0 4PF 4 0 1PF 50V CAP CER 4 7PF 1 0 25PF 100V COH CAP VAR 0 5 1 3PF 250V CER FLUKE STOCK NO 362889 837526 837526 837526 837526 837526 837526 837526 837526 866426 866426 866426 866426
19. 832030 09 RES MF 200 1 0 125W 100PPM 832063 1 RES MF 1 82K 1 125W 100PPM 851527 8 RES MF 3 92K 1 0 125W 100PPM 844709 7 THERMISTOR DISC NEC 10K 10 25C 104596 1 12 TERM FASTON TAB 110 SOLDER 512889 AMP QUAD 14 PIN DIP 402669 3 16 28 IC COMPARATOR QUAD 14 PIN DIP 381233 4 7 14 IC OP AMP LO NOISE 8 PIN DIP 495051 15 i 495051 5 39 IC DMOS FET QUAD SWITCH 501228 6 IC CMOS 12 BIT 1 2 BIT UP COMPATIBLE 851647 8 IC OP AMP QUAD JFET INPUT 14 PIN DIP 659748 9 IC OP AMP QUAD HIGH SPEED LOW NOISE 845016 10 DUAL LO PWR 8 PIN DIP 478354 11 5 8 DAC WITH AMPLIFIER 845008 12 IC CMOS 14BIT DAC 12BIT ACC CUR OUT 713101 13 IC LSTTL TRIPLE 3 PUT AND GATE 393082 17 26 IC LSTTL RETRG MONOSTAB MULTIVB W CLR 404186 18 20 IC CMOS 3 8 LINE DCDR W ENABLE 713036 21 IC OP AMP JFET INPUT 22V SUPPLY DIP 832584 22 28 35 IC CMOS OCTAL D F F W RESET 143286 38 40 743286 21 IC OP AMP PRECISION LOW NOISE 816744 29 IC OP AMP JFET IN COMPENSTD 8 PIN DIP 418780 30 IC COMPARATOR HI SPEED 14 PIN DIP 647115 31 IC FTTL QUAD 2 INPUT NAND GATE 654640 32 34 IC CMOS DUAL 12 BIT DAC 845011 36 IC OP AMP DUAL PRECISION MATCHED 182315 31 IC VOLT REG FIXED 8 VOLTS 1 5 AMPS 401635 41 IC OP AMP LO NOISE 8 PIN DIP 411745 1 RES NET DIP 16 8 RES 1K 5 358119 2 4 RES NET DIP 16 PIN 8 RES 10 1 55 500710 3p RES NE
20. 2 1 2 3 Front Panel Sections us hte etl aes uU ME 2 2 2 4 Upper Lower Module 5 4 5 2 2 2 5 Rear Panel Secho 232 2 2 2 6 FUNCTIONAL DESCRIPTION 2 2 2 7 Frequencys uu Ma ales dh 2 2 2 8 Frequency 2 4 2 9 Phase Modulation 2 4 2 10 Output Level Control 2 5 2 11 Amplitude Modulation 2 5 2 12 Pulse 2 5 2 13 Internal Modulation 2 6 2 14 Power Supply 2 6 2 15 DIGITAL CONTROLLER SOFTWARE DESCRIPTION 2 6 2 16 User Interface ect Pe Moke Oe PERLE IRAE E 2 6 2 17 Calibration Compensation 2 2 18 1658 PR 20222202 LITE 2 7 2 19 Status 22252 gate ean 27 3 CLOSED CASE 3 1 3 1 IN FRODUCTION RR LOS Medes oooh lt a SAG wd PE 3 1 3 2 Front Panel 3 2 3 3 Retmote Calibtatioti eroe test Bebe Qr Y xA S 3 2 3 4 Calibration
21. RPE121 911COJ3R9C100V RR P EIE F10PCT50V 2 RPE113 COG 681 J 50V RPE122 901C0G6800J100V REPLACEMENT PARTS R C B 5 WD W 00V Peer 7 57 REPLACEMENT PARTS 7 58 Table 7 14 A14 FM PCA cont REFERENCE FLUKE DESIGNATOR STOCK A gt NUMERICS gt DESCRIPTIONc 0 4 RELAY ARMATURE 2 FORM C 5V 133063 L 1 DUCTOR VAR 0 194UH 5 SHLDED 845057 L 2 3 DUCTOR 3 1 102 88MHZ SHLD 74714 L 4 INDUC 3 JUH 5 84MBZ SHLD 413864 L 5 DUCTOR 680008 10 T 5 10 363184 CTOR VARIABLE 4 861138 L 7 DUCTOR 220009 T 108 2 2MHZ SHLD 47801 L 8 16 18 CHO E 6TURN 320911 L 20 22 24 320911 lo 17222 DUCTOR 10 TURNS 463448 19 21 23 PIN SINGLE PWB 0 025 SQ 261500 MP 28 261500 Q lw 32 TRANSISTOR SI N JFET UHF VHF USE 403634 Q 3 TRANSISTOR SI NPN SMALL SIGNAL TO 92 832170 Q 4 TRANSISTOR SI PNP SMALL SIGNAL 229898 Q 5 8 9 TRANSISTOR SI PNP 7092 698290 Q 6 7 TRANSISTOR 51 SMALL SIGNAL 330803 Q 21011 TRANSISTOR SI NPN SMALL SIGNAL 248351 Q 12 13 TRANSISTOR SI PNP HI SPEED SWITCH 369629 0 14 15 TRANSISTOR SI N DMOS 10 72 477729 0 16 TRANSISTOR SI N DMOS FET 1 0 72 783308 R 1 7 RES CF 1 8K 58 0 250 573220 R Bin d RES CF 360 5 0 25W 57
22. 53 54 DUCTOR 0 082UH 10 500MHZ SHLD 256289 91637 IMS 5 082 10 2 L 55 DUCTOR 0 04408 4 155 500MHZ SHLD 249110 72259 WEEO 044 L 57 64 DUCTOR 0 47UH 5 264MBZ SHLD 329664 24759 MR 0 47 2 L 63 DUCTOR 0 68UH 10 221MH SHLD 320937 24759 MR 0 68 L 65 DUCTOR 0 56UH 5 249MHZ SHLD 806570 24759 MR 56 75 DUCTOR VARIABLE 6 809 860796 89536 860796 L 95 DUCTOR 0 1009 5 1000MBZ 844923 52763 5087226 913 1 CABLE TIE 4 0L 100W 75 DIA 172080 06383 55 2 OUTPUT AMP BASE PLATE PLATED 860945 89536 860945 MP 4 25 PIN SINGLE PWB 0 025 50 267500 00779 87623 1 22 d PIN FEED THRU 812735 89536 812735 Q 1 7 9 TRANSISTOR SI NPN HI FREQ SMALL SIGNL 722256 04713 MRF581 4 0 10 722256 O 2 4 6 TRANSISTOR SI PNP 1092 698233 04713 2N3906RLR 7 OQ lv 1253 5 698233 Q0 17 698233 3 TRANSISTOR SI PNP 7092 698290 27014 56552 0262 0 5 13 TRANSISTOR NPN SI RF LOW NOISE 845052 72751 41485 2 0 14 TRANSISTOR SI NPN HI FREQ SMALL SIGNL 723379 25403 BFR96 16 TRANSISTOR SI NPN HI FREQ SMALL SIGNL 845024 04713 587 Q 18 21 TRANSISTOR SI PNP HI SPEED SWITCH 369629 04713 205771 4 3 1 RES VAR CERM 90 4 105 0 58 447862 80204 33868 1 500 R 2 50 RES MF 43 2 1215 0 125W 100 85526 91637 CMF5543R2F 1 1 2 3 15 28 2 4 58 0 258 573238 59124 1 4 202 JB 6 R 53 77 86 513238 4 RES CC 300 5 0 25 348276 01121 3015 R 5 106
23. The attenuator control signals are latched by U39 Darlington driver U40 provides the level shifting necessary to control the A7 Relay Driver RPP PCA Module 1 0 6B 9 Control data is transferred to the RF circuitry through two byte wide unidirectional data buses Data is transferred to the upper module through J3 and to the lower module through J6 Select lines BSELOL BSELIL and BSELSL and address lines SAB2 SABI and SABO are decoded into individual latch enables for the upper module on the A4 subsynthesizer PCA Tri state buffers U24 and U33 provide drive current when active and allow these signals to float when inactive Select lines BSEL2L BSEL3L and BSELAL and address lines BAB2 BABI and are decoded into individual latch enables for the lower module on the All Modulation Control PCA Tri state buffers U25 and U27 provide drive current when active and allow these signals to float when inactive 6B 3 TROUBLESHOOTING AND REPAIR DIGITAL CONTROLLER 6B 4 Timing PAL U15 adds additional wait states to each module I O write cycle to ensure that adequate setup and hold times are provided for every IC on the bus Status and Control 6B 10 Input buffers U35 U36 U37 and U45 read the fault detector signals hardware status signals the option status signals and the status of the REF INT EXT and CALICOMP switches Control and buffer enable data is latched by output latches U34 and U38 DIGITAL CONTROLLER TROUBL
24. The bus error input BERR pin 22 notifies the microprocessor when a memory cycle cannot be completed as a result of a hardware fault Normally the BERR signal should always remain high If the BERR signal goes low verify that pin 1 of U14 is clocked by an 800 kHz signal with a 60 40 duty cycle Also verify that pin 2 of U14 is receiving continuous activity from the address strobe signal AS Interrupts 6B 18 The front panel edit knob interrupt is generated on the Al Display PCA when the knob is turned The interrupt signal from the display PCA connects to 012 pin 13 is low when the knob is in the rest position refer to Edit Knob Interface later in Section 6B 6B 5 TROUBLESHOOTING AND REPAIR DIGITAL CONTROLLER Under normal operation a front panel interrupt should be generated every 540 us at pin 6 of U21 Ifthe display has been turned off by special function there should be an interrupt generated every 16 3 ms Verify the divided outputs from U14 and U20 and make sure that a reset signal at U21 pin 1 is generated after each interrupt Verify that the IEEE 488 Interface interrupt signal IEINTL is in the inactive high state If IEINTL is active make sure the microprocessor kernel and buses are operating correctly since the software must be operating before the IEEE interrupt can be initialized properly Next troubleshoot communications with the IEEE 488 interface IC using the diagnostic tests under the heading I O
25. aaa tie SEDEM Coe 6 9 6 5 ie ie ted 6 10 6 6 Phase Modulation Test 6 10 6 7 6 10 6 8 Coarse Ota A ed TOP cn 26 eee Dune POR 6 11 6 9 Sub Synthesizer 5 6 11 6 10 Sum Loop Tests ue SOL ro IA C 6 11 Tests occ s cs cada Epor ox Co qp ent AEG Doe Dead S 6 12 6 12 Pulse Modulator 4 6 12 6 19 Dott Cost ober do e 6 13 6 14 Status Signals and 6 13 6 15 Parameter Settings of Diagnostic 5 5 6 14 continued on page x LIST OF TABLES continued TABLE 6A 1 6C 1 6C 2 6C 3 6C 4 6C 5 6C 6 6C 7 6C 8 6C 9 6C 10 6C 11 6C 12 6D 1 6D 2 6D 3 6D 4 6D 5 6D 6 6E 1 2 6 3 6 4 6 5 TITLE PAGE Supplies Provided by Power Supply 6A 3 Sub Synthesizer PCA Test 6C 11 Sub Synthesizer VCO PCA DC 6C 17 Coarse Loop RF Voltage Levels eee 6 24 N Diyider Logic States 6 25 Discriminator RF
26. 2 f sum 80 f coarse TROUBLESHOOTING AND REPAIR FREQUENCY SYNTHESIS Ifthe above signals are at the correct frequency and level the problem is likely in the sum loop or the Sum Loop VCO The Sum Loop VCO can be checked for proper operation by shorting to ground the phase lock port and measuring the Sum Loop VCO signal at TP12 using a 500 ohm probe with a spectrum analyzer The measured frequency should be within 2 MHz ofthe expected sum loop frequency If the signal is absent or is far offfrequency either the sum loop VCO or the VCO steering voltage circuit is faulty The steering voltage circuit can be checked by programming the UUT with SPCL 943 and measuring the DC voltage at TP3 the VCO steering port This special function programs the steering DAC to full scale and should result in a reading of 26 00V If the Sum Loop VCO seems to function properly the Sum Loop is probably faulty With phase lock port still shorted to ground use an oscilloscope to measure the signal at TP5 the phase detector output This signal should be atriangle wave of about 0 56V peak peak amplitude The frequency should be less than 2 MHz An improper signal here indicates a problem in the phase detector or the RF circuitry that precedes it The RF circuits can be checked and any problem isolated by measuring signal levels and frequencies at various points with a 500 ohm probe and a spectrum analyzer Table 6C 9 contains expected frequ
27. H P SS 6 32X 750 VP SCREW MACH PH P STL 10 32X 250 SCREW MACH PH P SS 8 32 375 CORD LINE 5 LABEL VINYL 5 B R CODE 5 TEC 3 18AWG SVT PRING GAS 195MMX317 5MM 14 3 ECAL CAL OVER TOP OVER BOTTOM HASSIS SIDE RIGHT HASSIS SIDE LEFT GE LEFT INGE RIGHT ETAL PART STAMPED HOLE PLUG 500 UTPUT COVER PLATED ONTROLLER COVER PLATED 0 LOOP COVER PLATED UBSYNTH COVER PLATED ODULE WA oQ 29 ca 5 DIA 10SCREW 6080 6080A Al SERVICE MANU OPERATORS M EMIRIGID OLLER IEEE RIR 4 L POWER ECT HARNESS FLUKE STOCK 857748 860924 860721 860770 860791 860759 860734 860762 860742 860775 860767 860726 6080A AN Final Assembly MFRS MANUFACTURERS SPLY PART NUMBER CODE _ OR 89536 860853 89536 860861 89536 860866 89536 860874 89536 860879 89536 860890 89536 860817 89536 860820 89536 860841 89536 860846 89536 860825 89536 860833 89536 861088 89536 860895 89536 860903 89536 860858 cae 860812 ERCIA COM ERC COMMERC COMMERC COMMERC COMMERC COMMERC DDP COMMERCIAL COMMERCIAL COMMERCIAL 70903 17239 89536 844712 89536 852160 89536 861158 89536 842796 89536 842794 89536 842799 89536 842802 89536 860580 89536 860585 83330 653 89536 860937 89536 860940 89536 860973 89536
28. The rear panel CAIN COMP switch must be set to the 1 position before performing Special Function 907 If the checksums in both ICs are valid for a given data segment no transfers are performed However if one checksum is valid and the other is invalid the message Sto is displayed and the good data is copied over the bad If both checksums are bad no transfers can be performed Each redundant data segment pair is checked and updatedindividually After all transfers are complete the checksums are verified again and any remaining failures are reported It also resolves the situation where a segment in EEPROM and in the battery backed RAM both have valid checksums but contain different data The EEPROM data segment is always copied to battery backed RAM in this situation Calibration Compensation Memory Origin Status 6B 25 The data in the calibration compensation memory can be generated by The Fluke factory Through Module Exchange MEC The user performing the calibration or compensation procedures The calibration compensation data origin code specifies how the particular data segment was generated A segment s data origin may have a bearing on future actions so it is desirable to know how each was generated Refer to Appendix H Compensation Procedures Special Function 05 displays the data origin codes If all data segments were generated by the Fluke factory the origin code 00 is displayed If any ofthe da
29. gt 23 20 gt 2 9 7 gt gt oO 205 2 882428 34864 095 34284209 88084888 228988 0 SHV Or PS 2 5 ltt onto 2 lt 9 NW 2S c 5 T 2 9 T lt H E a lt 0 lt 2 lt gt lt oc lt 5 zb LL 2 a Radians Phase Modulation Ranges and deviation depend on dialed RF frequency See specifications TFor column R under Outputs 1 is R66 2 is R87 6E 8 TROUBLESHOOTING AND REPAIR FREQUENCY AND PHASE MODULATION The active feedback network consists of a second op amp U38 and resistors R99 and R95 and is functional for switching from ACFM to LOWRATE FM The selected feedback network is controlled by the analog switch U36 for the different modes of operation The Z5 U35 range selection has a 16 to 1 magnitude relationship and is selected in conjunction with the Z7 U32 combinatio
30. 20 50V 800516 C 36 En i E 446450 C 38 A DN EET COG 614586 C 39 98 CAP CER 3300PF 5 50V COG 528554 43 TA 1506 4 202 20V 519686 C 44 CAP CER 2000PF 5 50V COG 832618 C 45 CAP POLYES 10 10 50V 133089 C 46 CAP POLYES 0 010 10 50V 715037 47 CAP POLYPR 470 1 15 100V 844811 C 48 POLYES 0 022UF 4 102 50V 115268 6 39 524 53 CAP CER 330PF 5 100V COG 838474 C 64 67 838474 C 50 CAP POLYPR 2200PF nl 100V 866889 C 51 98 CAP POLYPR 4700PF 3 63V 854513 C 54 56 Ne IS 519074 QC 544 58 CAP 22UF 20 25V 357780 C 59 68 69 CAP TA 10UF 20 35V 417683 C 62 CAP POLYPR 150 4 15 50 422980 C 63 CAP CER 47PF 2 1007 COG 812123 70 POLYPR 0 0786UF 4 12 50V 422998 C 2 89 CAP POLYES 0 47UF 10 50V 697409 C 28 CAP POLYPR 680PF 15 100 866892 CAP VAR 10 120PF 50V CER 631416 C 93 CAP TA UF 10 35V 161919 C 94 CAP CER 680 2 50 COG 743351 95 96 101 CAP 1006 1 208 20 330662 C 102 330662 C 99 CAP CER 6800 5 100V C0G 816710 C 100 CAP CER 82PF 2 100V COG 512350 C 103 CAP TA 22UF 203 10V 658971 C 104 CAP CER 1800PF 54 90V 0 528547 C 105 106 CAP TA 33UF 4 1 5 866897 81 48 DIODE SI VARACTOR PIV 28V 741504 CR 13 DIODE 5 SWITCHING 806646 CR 14 ZENER COMP 6 3V 3 10PPM 2MA 357848 CR 15 17 20 DIOD
31. 4 52 50V 739987 60935 168 2 4700 2 50 C 235 CAP POLYES 2200PF 4 105 50V 780536 96881 IR67222K C 264 CAP 1UF 10 35V 161919 56289 196D105X0035HA1 C 301 303 304 CAP CER 1000 1 205 100V XR 837542 04222 SR151C102MATR 5 C 313 314 837542 403 CAP CER 5 50V COG 0805 494781 05397 CC805C100J5GAT C 405 CAP CER 27PF 2 100V COG 812107 04222 SR291A270GAA C 412 CAP CER 100PF 5 50V COG 0805 514133 05397 CO805C101J5GAT C 421 CAP CER 1 5PF 4 0 25PF 100V 812164 04222 581713 185 422 CAP CER 2 2PF 0 25PF 100V COJ 812099 72982 RPE121911COJ2R2C100V C 423 CER 1 8PF 0 25PF 100V 512897 72982 8101 100COK0189B C 425 426 CAP CER 1 2PF 0 25PF 100V 543256 51406 110 001820100 2 C 428 CAP AL 470UF 20 16V SOLV PROOF 772855 61058 1 0471 C 430 CER 3 9 0 25PF 50V COG 0805 493874 04222 08055A3R9CAT065B C 514 CAP 10UF 4 205 15V 193623 56289 195D106X0015A1 C 519 550 CAP CER 270PF 5 50V COG 658898 72982 RPE122 901 C0G 271 0 50V 2 4700 20 100 7 04222 SR151C472MATR 5 C 529 CAP 2 2UF 10 15 364216 56289 1960225 0015 1 C 530 CAP POLYES 0 047UF 4 102 50V 714709 60935 168 2 047 K A C 545 CAP CER 12PF 2 100V C0G 715169 04222 SR211A126GAT C 546 CAP 39UF 20 20V 358234 31433 1361396M020AS An in S column indicates
32. 5 1 4 5 0 25W 640995 An in S column indicates static sensitive part MANUFACTURERS PART NUMBER 645991 3 702033 2985 6011 75060 012 1203 0085 463448 6087226 233 5087226 913 5087227 513 5087227 813 MR 12 MR 1 8 MR 10 5087221 113 645991 3 87623 1 MRF58 2N3906RLRA BFR91 2N4274 21517 92455 261578 CCF 501620F CCF 501210F CCF 502000F CCF 5082R5F CCF 50 1000F 5063JD3011F CCF 501001F F 55 5621 F F 55 4991 F F 55 4321 F F6580R6FT 1 1 4 102 J B 13B 2B0510B F 55 7500 F F 50182 F55D1500F F5537RAFT 1 F 504640F F1 82941F F 55 121 F653480F 653010 043ED665K FF1 81432F F555900FT 1 4 10 F1 4 30 FF1 83920F FF1 88060F F50VID5230F CMF 55 4020 F 1 4 483 5 50 110 CCF 503570F 5063JD51RlF 1 4 121 J CF1 4VT101J 1 4 CMF551540FT 1 1 4 581 5 OOOr D co 29 gt REPLACEMENT PARTS OR GENERIC Tel Tell TS 1 1 Gir WWF DOR NO SO BONO DE COCOCO A cou 751 REPLACEMENT PARTS 7 52 REFERENCE DESIGNATOR A gt NUMERICS gt 5 D UU ZO DO 00 UJ D O3 UO 00 D 50 50 50 UO UO UO 50 50 UO UO UO UO UO UO UO DDD Ci CiCdicdcicicccaudss s
33. 7 68 REFERENCE DESIG ATOR A gt NUMERICS gt 5 Cd kd 79 79 VU 0 99 99 79 9 UME am Sed 2 16 8 3 1 5 Dor 1 or Eo Dor 3 CO Cn gt c gt Pwr Cnr N car m Oc AE co gn Co o CO DODO CO wo 33 1 Table 7 19 7 Relay Driver See Figure 7 17 CAP POLYES 0 107 4 208 50V CER 0 1 7208 50V XTR CAP CER 0 22UF 20 50V 250 AL 22UF 4 208 35V SOLV PROOF GP AL 4 TUF 205 50V 50 PROOF ENER UNCOMP 30 01 10 4 2 0 4W TENER 7 54 5520 0 0 41 ZENER UNCOMP 9 1V 55 14 0 41 DIODE SI 101500 50018 ZENER UNCOMP 4 7V 59 20 0 0 4W SPACER SWAGED RND BR 1501D 150 HEADER 2 ROW 100CTR RT ANG 16 PIN CHOKE 6TURN INDUCTOR 82UH 10 14MHZ SHLD INDUCTOR 47UH 5 26 5MHZ SHLD SOCKET SINGLE PWB FOR 042 049 PIN SISTOR SI PNP T092 TRANSISTOR SI NPN SMALL SIGNAL RES CF 510 5 0 25W RES CF 4 7K 5 0 251 RES CF 75 RES CF 30 RES CF 0 RES 42 RES CF 1K c
34. CAP CER 1000PF 4 202 50V X TR 0805 514059 05397 0805 102 5 3 3 5 CAP 4 7UF 10 15V 519363 33297 NSC475K15 2 C 6 7 CAP TA 3 3UF 202 50V 772848 56289 195D335X005022 2 CR DIODE 51 SCHOTTKY BARRIER SMALL SIGNL 535195 28480 5082 2800 CR 2 9 DIODE SI BV 70 0V 500 MW 454181 03508 1N4606 8 H 8 RELAY WASHER 803247 COMMERCIAL 8 J SOCKET SINGLE PWB FOR 0 034 0 037 PIN 732826 00779 2 332070 7 J 2 CONN COAX SMA PWB OR PANEL 512087 21845 2985 6011 K 8 RELAY M HIGH FREQUENCY 812669 89536 812669 8 11 SOCKET SINGLE PWB FOR 042 049 PIN 544056 00779 50871 1 1 R RES MF 402 0 5 0 1250 50PPM 461632 03888 PME60 4020DP 2 5 R 10 19 461632 R 3 5 RES 56 9 0 5 0 1251 50PPM 461590 89536 461590 10 R 6 8 461590 11 12 20 461590 R 2 461590 R 13 RES MF 37 4 0 5 0 125W 50PPM 461079 03888 PME60 37R4DP 2 R 14 15 RES 150 0 5 0 125W 50PPM 461624 03888 PME60 1500DP 2 2 R 16 RES 94 2 0 5 0 1251 50PPM 461616 89536 461616 R 17 18 RES MF 83 5 0 5 0 1251 50 461608 89536 461608 2 R 22 RES MF 10K 4 1 0 25W 100PPM 199635 71590 5063001002 23 RES CF 51 5 0 25 572990 59124 CFl 4 510 08 An in S column indicates static sensitive part 1 11 REPLACEMENT PARTS DASHED LINES INSTALLED COMPONENTS MARKED IN ON CKT SIDE 60804 1636 7 72 Figure 7 18 A21 Attentuator PC
35. DOF DO REPLACEMENT PARTS a R15 0545542 cuo cu ORA 023 R21 crad c38 R10 10 087 R12 58 c3e 55 C3 6142614 9 00 0 a R a oc y A 01 C33 R3 AUS a 6080 1605 Figure 7 6 A5 Coarse Loop VCO PCA 7 33 REPLACEMENT PARTS Table 7 7 A6 Mod Oscillator PCA See Figure 7 7 REFERENCE FLUKE MFRS MANUFACTURERS DESIGNATOR STOCK SPLY PART NUMBER TOT A gt NUMERICS gt 5 DESCRIPTION 7 NO CODE OR GENERIC TYPE QTY C 1 CAP TA 2206 4 205 10V 658971 56289 1990226 0010 1 1 C 2 5 8 CAP 10UF 4 202 25V 714774 56289 1990106 0025 1 7 6211212 114714 C 49 10 CAP POLYES 0 1UF 20 50V 837526 40402 1823104056 17 C 16 26 22 831526 C 24 28 33 837526 C 13 14 CAP CER 680PF 5 50V COG 743351 72982 RPE113 COG 681 J 50V 2 C 15 CAP 15PF 4 25 100V COG 369074 80031 2222 631 10159 1 C 25 26 CAP CER 150PF 2 100V COG 512988 05397 C315C151J1G5EA 2 21 CAP CER 10PF 2 100V COG 512343 51406 RPE110COG100G100V 1 CR 1 3 7 DIODE SI BV 75 0V I0 150MA 500MW 698720 65940 1N4448 6 ie 1 INDUCTOR 1000UH 5 4 5MHZ SHLD 147819 24759 MR 1000 1 L 2 4 CHOKE 6TUR 320911 89536 320911 3 P 1 19 SOCKET SINGLE PWB 042 049 PIN 866764 00779 645991 3 19 12 TRANSIST
36. MEASURED SECTION LEVEL POWER ERROR ERROR LIMIT SECTION NOMINAL dBm dBm dB dB dB 0 12 12 2 0 2 12 2 12 0 0 2 1 6 05 9 0 1 12 2 5 9 6 0 3 2 12 0 00 2 0 2 122 02 12 04 3 24 12 12 1 0 1 12 2 121 24 03 4 24 12 11 8 0 2 12 2 11 8 24 0 0 5 24 12 12 0 0 0 12 2 12 0 24 0 2 6 24 12 12 3 0 3 12 2 12 3 24 0 5 7 24 12 11 9 0 1 12 2 11 9 24 0 1 Sum of Errors 1 0 MID LEVEL ACCURACY TEST 4 7 The level accuracy is verified using a power meter with a low level power sensor This verification is done from 24 to 66 dBm at frequencies of 10 14 20 40 80 160 320 550 640 700 850 950 and 1024 MHz REQUIREMENT Amplitude accuracy is lt 1 5 dB from 0 5 to 1024 MHz TEST EQUIPMENT e Power meter Power sensor Low Level REMARKS This test in conjunction with the high level accuracy test and the low level accuracy test verifies the overall level performance of the UUT PERFORMANCE TESTS If the UUT fails this test after passing the high level accuracy test problems with the A21 Attenuator PCA or the A7 Relay Driver are indicated It is convenient to use the UUT RF ON OFF control when zeroing the power meter PROCEDURE 1 Program the UUT to SPCL 909 10 MHz and 24 dBm 2 Calibrate the power meter 3 Zero the power meter 4 Connect the power meter and power sensor to the UUT RF OUTPUT 5 Measure the
37. SS WI TO AIB CABLE TRANSITION ON AGO SYNTHESIZER MODULE it m 5 gt TO AIS POWER SUPPLY ON REAR PANEL A7O TO AIS DOWER SUPPLY ON REAR PANEL A7O TO Al DISPLAY ONT CONTROLLER SIDE ON A O ATTENDATOR FICTER ASSY OUTPUT MODULE THE ITEMS SHOWN ON THIS SHEET ARE LISTED UNDER THE A40 DIVISION IN TABLE 7 1 UNLESS OTHERWISE SPECIFIED 6080A AN T amp B Figure 7 1 6080A AN Final Assembly cont 7 14 REPLACEMENT PARTS DETAIL Hs SANG SEE DETAILS lt aoza aj NAN SEE DETAIL THE ITEMS SHOWN ON THIS SHEET ARE LISTED UNDER THE 50 DIVISION IN TABLE 7 1 UNLESS OTHERWISE SPECIFIED 5 9 3 n gt LU 72 4 Pp 7 OON AX e 2 XY 5 NN A A AEN 3 LN 7 SWITCH PATTERN SIDE A19 28 e e 6080A AN 7 Figure 7 1 6080A AN Final Assembly cont 7 15 REPLACEMENT PARTS POSITION LOCKING PART 5 SHOWN ACOMPSO AROUND WIS 08 700 27 57 ux __ _ COARSE LOOP a EX ACOMPSB ADOMPA7 COARSE SIDE AGO SYNTHESIZER MODULE THE ITEMS SHOWN ON THIS SHEET ARE LISTED UNDER THE A60 DIVISION IN TABLE 7 1 UNLESS OTHERW
38. 0 01 to 3V 1096 HI RF 801 T Frequency Counter 0 1 1050 MHz 10 Hz res 0 1V JF 7220A Modulation Analyzer Input 0 15 to 1300 MHz 0 20 dBm 8901A A P T w Option 003 AM 10 to 90 1 FM 0 1 to 100 kHz dev 1 External LO capability Distortion Analyzer 1 to 10 rng 1 dB 0 4 and 1 kHz HP 339B A P T Power Meter Instrumentation accuracy lt 1 HP 436A Power Sensor 30 to 20 dBm VSWR 1 2 for HP 8482A High level 0 4 to 1 MHz lt 1 1 for 1 to 2000 MHz 1 3 for 2000 MHz Power Sensor 67 to 20 dBm VSWR 14 for HP 8484A Low Level 10 to 30 MHz 1 15 for 30 to 2100 MHz 3 Attenuator 50 20 dB 0 1 to 2100 MHz VSWR 1 15 Narda 777C P LF Synthesized Signal 10 Hz to 11 MHz 10 Hz steps JF 6011A A P Generator 1V peak Spurs and Harm 50 dB HF Synthesized 0 5 to 1024 MHz JF 6080A AN Sig Gen 4 2 Table 4 1 Recommended Test Equipment cont PERFORMANCE TESTS INSTRUMENT NAME MINIMUM REQUIREMENT NOTES Frequency Standard House Standard 10 MHz Test Cable Dual pin to BNC JF 732891 Adapter Coax 50 ohm Type N m to BNC f JF Y9308 Adapter Service 50 ohm Module output to SMA JF 744177 T Two Turn Loop For Leakage test See Figure 4 1 Homebuilt P T VSWR Bridge 10 to 2000 MHz Wiltron 60N50 P 50 Ohm Termination Type N JF Y9317 P Coaxial Cable 50 ohm 3 ft BNC both ends 9111 Coaxial Cable 50 ohm 6
39. 1 5K 5 0 25W RES CF 2K 5 0 25W RES CERM 130 5 12 5W 200 1206 RES CERM 47 5 125W 200PPM 1206 RES CERM 39 5 125W 200 1206 RES ME 422 1 0 5W 100 RES 219 0 51 100 RES CF 1K 4 5 0 25W RES CF 2 7K 5 0 25W RES 100 5 0 5W RES 210 1 0 5W 100PPM RES CERM 11 13 125 100PPM 1206 RES VAR CERM 500 10 0 58 RES CF 22 4 53 0 125W RES CF 51 5 0 125W RES MF 200 1 0 125W 100PPM RES MF 49 9 4 12 0 125W 100PPM RES CF 100 5 0 125W RES CF 24 5 0 125 RES CF 110 5 0 125 RES 82 5 1 0 25 100PPM 12511 RES MF 26 7 1 0 125W 100PPM RES MF 1 4K 1 125W 100 RES MF 2 55K 13 0 125W 100 RES MF 59 0 13 0 5W 100 RES CF 160 5 0 1250 RES MF 511 4 12 0 251 LOOPPM RES CF 360 53 0 1 250 RES CF 22 71 55 0 251 RES CF 33K 5 0 25W RES CF 4 7K 4 52 0 250 RES JUMPER 0 02MAX RES 100 4 5 0 25W RES 68 5 0 125W TRANSFORMER 90KHZ 200MHZ 1 1 IC 2 5 GHZ DIVIDE BY 2 PRESCALER SOIC IC BPLR MONOLITHIC MICROWAVE AMP IC ECL DUAL D M S F F EDGE TRIGGER IC BPLR SELECT GAIN MSA 0404 2GHZ IC OP AMP QUAD 14 PIN DIP RES SIP 6 PIN 5 RES 510 2 RES NET SIP 10 PIN 9 RES 510 2 FLUKE 95722 851563 719955 150920
40. 102 RELAY REED 1 FORM A 5VDC 461434 L 27 8 DUCTOR 10 TURNS 463448 L 6 19 463448 L 3 DUCTOR 0 022UH 20 1000MHZ 844949 L 4 20 DUCTOR 0 1008 5 1000MHZ 844923 L 9 23 DUCTOR 0 33UH 5 5 10MHZ 844886 L 0 21 DUCTOR 0 5609 5 440MHZ 844944 L peo DUCTOR 0 12UH 10 400MHZ SHLD 272617 L 3 15 26 DUCTOR 1 8UH 5 121MHZ SHLD 806554 L 8 24 DUCTOR 10UH 4 105 53MHZ SHLD 249018 L 22 DUCTOR 0 15UH 5 825MHZ 844902 SOCKET SINGLE PWB FOR 042 049 PIN 866764 MP 15 17 19 PIN SINGLE PWB 0 025 SQ 261500 34 261500 Q 2 6 TRANSISTOR SI NPN HI FREQ SMALL SIGNL 722256 0 3 4 1 TRANSISTOR SI PNP T092 698233 5 8 9 TRANSISTOR SI NPN HI FREQ SMALL SIGNL 535013 Q 108 4 535013 Q 10 TRANSISTOR SI NPN HI SPEED SWITCHING 369645 Q 1 TRANSISTOR SI PNP HI SPEED SWITCH 369629 Q 101 103 105 TRANSISTOR SI N JFET LO RDS ON TO 92 507780 Q 106 107 109 TRANSISTOR SI N JFET T0 92 SWITCH 261518 R 4 52 54 RES MF 162 1 0 25W 100PPM 799890 R 5 RES MF 121 4 1 0 25W 100PPM 799734 R 6 78 11 RES MF 200 1 0 25W 100PPM 199759 R 24 50 154 799759 R T 9 RES 82 5 1 0 25 100 199783 R 057 58 RES 100 1 0 25W 100PPM 199668 R 6l 199668 R 2 RES 3 01 4 15 0 25W 100PPM 854356 R 3 21 161 RES MF 1K 1 0 25W 100PP 199791 R 4 RES MF 5 62K 1 0 125W 100PPM 720417 R 5 28 36 RES MF 4 99 1 0 125W 100PPM 714923 R 110 134
41. 10BIT DAC 8BIT ACCUR CUR OUT UAL LO PWR 8 PIN DIP D LSTTL DUAL MONOSTAB MULTIV W SCHMT I SPEED 14 PIN DIP ONOSTAB MULTIVB W CLR PIN 7 5 100 4 5 FLUKE STOCK 0 643486 296681 572974 573022 631374 573410 223545 168237 853630 973584 973584 72151 57331 820282 81755 112038 97425 719559 851563 32086 235218 697102 799635 157104 854732 512889 512103 851282 854039 418566 418269 113218 429910 387233 495051 507228 524868 860994 478354 404202 386920 412734 516930 MFRS MANUFACTURERS SPLY NUMBER CODE OR GENERIC TYPE 59124 CF1 4111JB 91637 MEF1833R2F 50124 1 42400 59124 CF1 4131JB 59124 1 4 750 J B 65940 8257133 59124 1 4 152 J 59124 CF1 4 203 JB 91637 CMF552490FT 1 91637 551151 1 91637 55 4871 1 1 91637 CMF 55 6489 F 1 1 91637 MFF1 81541F 91637 CMF553011FT 1 3299 3329H 1 50 91637 558450 1 59124 MF552491F 59124 CF1 4 473 J B 91637 55 2001 1 1 80294 3329H 1 201 91637 55 1431 1 91637 CMF552872FT 59124 MF556340F 3299 33298 1 202 91637 1050 91637 556190 91637 CMF6042FT 91637 5 51270 91637 55 2320 F 1 1 91637 554990 91637 551021 91637 552101 59124 MF50VTD7321B 59124 1 4 104 JB 59124 1 44727 VT 59124 1 4 472 J 59124 MF50VTD2
42. 15 18 LEVEL For pulse widths 50 ns power in the pulse will be within 20 7 dB of the measured CW level DUTY CYCLE ext 0 100 REP RATE ext DC 16 MHz INTERNAL Internal rates approx 50 duty cycle EXTERNAL PULSE MODULATION The pulse input is TTL compatible and 50 ohm terminated with an internal active pull up It can be modeled as 1 2V in series with 50 ohms at the pulse modulation input connector The signal generator senses input terminal voltage and turns the RF off when the terminal voltage drops below 1 0 1V Max allowable applied voltage 10V PULSE MODULATION RF FREQUENCIES lt 10 MHz RISE amp FALL 5 2 X period of RF Frequency LEVEL ERROR i ERR For pulse widths 10 X period of RF Frequency power in the pulse will be within 40 7 dB of the measured CW level Other specifications are the same as for the 10 to 1056 MHz range NON VOLATILE MEMORY 50 instrument states are retained for typically 2 years even with the power mains disconnected REVERSE POWER PROTECTION PROTECTION LEVEL Up to 50 watts from a 50 ohm source up to 50V DC Signal generator output is AC coupled Protection is provided when the signal generator is off INTRODUCTION AND SPECIFICATIONS Tabl
43. 2 412726 71450 750 61 R100K RES SIP 6 5 RES 510 2 459974 91637 5 08 01 5116 RES FILM TESTED 858378 89536 858378 RES FILM TESTED 851118 89536 851118 RES FILM TESTED 851170 89536 851170 RES NET SIP 10 PIN 9 5 4 7 2 484063 91637 5 10 014726 S column indicates static sensitive part REPLACEMENT PARTS 6080 1606 223 441 0141 541 TETY Rej _ 28 gt SEE S gt TNO O amp NO o 5 2 2 c c c yr du v 9 5 s 1515 5 5 3 EJ RIS 8 5 90 30 TEN 90 bey 2 4 x 4 6 at bdl 641 DE 234 ony 5 E gt gt 948 T 258 9 024 SO EC N 932 31 923 zen gen CN cele EAT Z 01 212 ce 88 go 1 023 E 39 1280 US 8 SEND un 63 3L 39 I iE R x OTT FP OLS 5 2 Thi Ten h 299 19 c N c 018 8113 1218 0818 69 79 0TH bu 448 239 824
44. 24V supply 24V 5 2 23 4V supply 24V 5 TP6 5 1V supply 5 1V 2 TP11 15V supply 15 4 TP16 15V supply 15V 4 TP14 5V supply 5V 5 TP20 37V supply 37V x 5 TP21 30Vsupply 30V x 5 15 5V reference 5V 3 op 6 Ifall supplies are at the appropriate voltages when in standby but are not at the appropriate voltages when the power supply is on verify that the all standby supplies are correct If the fan supply 24V is on and the rest of the supplies with the exception of the 23 4 and 5V are off check the current limit circuitry U2 CR5 CR9 Q4 A short at either the 15 or the 45 1 could cause the current limit to trip and turn all non standby supplies off with the exception of the fan supply In this case verify that the voltage at TP22 is less than 1V which indicates a current limit trip To recover from a current limit shutoff turn off the power supply to standby operation for at least 5 seconds 7 Ifonly the 5 V reference 45 1 V 15V and the 15V supplies are in error check the 5V reference circuitry since it is likely that the fault is with the reference supply 01 CR16 POWER SUPPLY ADJUSTMENT PROCEDURE 6A 5 A single adjustment potentiometer is provided for adjusting the voltage output of the three discrete supplies the 45 1 15 and 15V To adjust these supplies place a voltmeter at the 5 1V supply TP6 and adjust R4
45. 348 550 MHz 512 625MHz Leveled 349 650 MHz 625 730 MHz Leveled 350 800 MHz 730 1056 MHz Leveled 351 100 MHz 15 22 MHz Unleveled 352 100 MHz 22 32MHz Unleveled 353 100 MHz 32 47MHz Unleveled 354 200 MHz 47 64MHz Unleveled 355 500 MHz 256 350 MHz Unleveled 356 1024 MHz 512 730 MHz Unleveled Amplitude 15 0 dBm STATUS SIGNALS AND STATUS CODES 6 35 Table 6 14 lists the major hardware status signals monitored by the software and the corresponding front panel status code Table 6 14 Status Signals and Codes STATUS ASSEMBLY CODE SIGNAL DESCRIPTION A7 Attenuator RPP 240 RPTRPL RPP Tripped A10 Premodulator 241 ALCUNLVL ALC Loop Unleveled or AM Overmodulation A4 Sub Synthesizer 242 SUBUNLKL Sub Synthesizer Unlocked A2 Coarse Loop 243 CORUNLKL Coarse Loop Unlocked A12 Sum Loop 244 SUMUNLKL Sum Loop Unlocked A12 Sum Loop 245 SUMUNLVL Sum Loop Unleveled A2 Coarse Loop 246 REFUNLKL Reference Loop Unlocked A14 FM loop 247 FMUNLKL FM Loop Unlocked or FM Overmodulation 6 13 TROUBLESHOOTING AND REPAIR 6 14 SOFTWARE DIAGNOSTIC FUNCTIONS 6 36 The instrument software includes built in diagnostic functions to aid troubleshooting and alignment Digital Control Latch Test 6 37 Special Function 903 the Latch Test generates continuous activity on the data and address busses so the activity can be monitored with an oscilloscope When the test is initiated the message LAtch AA
46. 6C 5 SUB SYNTHESIZER ADJUSTMENTS 6C 13 6C 6 Steering DAC Full Scale 6C 13 6 7 Lower Clamp Adjustment 699 6C 13 6C 8 Upper Clamp Adjustment 98 6C 14 6C 9 SSB Mixer LO Drive Adjustment 106 6C 14 6C 10 10 kHz Notch Adjustment 56 6C 15 IV continued on page v TABLE OF CONTENTS continued SECTION TITLE PAGE 6C 11 SUB SYNTHESIZER VCO CIRCUIT DESCRIPTION 6C 16 6 12 SUB SYNTHESIZER VCO TROUBLESHOOTING 6C 16 6 13 COARSE LOOP CIRCUIT DESCRIPTION 2 6C 17 6C 14 REFERENCE SECTION BLOCK DIAGRAM 6C 17 6C 15 COARSE LOOP BLOCK 6C 20 6C 16 COARSE LOOP TROUBLESHOOTING 6C 22 6C 17 COARSE LOOP PCA ADJUSTMENTS 5 6C 26 6C 18 Discriminator Video Amplifier Offset Adjustment 102 6C 26 6C 19 Steering Gain Adjustment 221 6C 28 6C 20 Acquisition Oscillator Level Adjustment 227 6C 28 6C 21 40 MHz Oscillator Adjustment 1601 6C 28 6C 22 80 MHz Filter Tuning L612 and 6 13 6C 29 6C 23 80 MHz Level Adjustment 17 6C 30
47. 6E 17 NOTE This procedure concerns the adjustment of the modulation circuitry Other adjustments are covered in other procedures Make adjustments on the Modulation Control PCA as described in the following procedure 1 Make the following equipment settings a Setthe UUT to SPCL 909 800 MHz 0 dBm 4 MHz dev EXT ACFM b Set the 8840A DMM to AC volts autorange Set the 6011A Signal Generator to 1 kHz 383 mV RMS 2 Connect the 6011A to the UUT EXT FM input and to the 8840A 3 Setthe 6011A as measured by the 8840A to 707 mV RMS Set the 8840A to AC volts and autorange Connect the 8840A to J16 P1 on 4048 Modulation Control PCA Adjust R82 for 2 828 RMS 2 mV 4 Set the UUT to 700 MHz Set the 8840A to AC volts autorange Connect the 8840A to J16 P1 on 4048 Modulation Control PCA Adjust R102 for a reading of 2 828 RMS 2 mV on the 8840A 5 Set the UUT EXT offand set the UUT INT FM on The 8840A should read 2 828V RMS 2 mV RMS Set UUT INT FM off and set UUT EXT ACFM on 6 Set the UUT to SPCL 943 Connect the 8840A to J2 P14 Set the 8840A to DC volts Adjust R99 for 10 24V DC 10 mV Connect the 8840A to J1 P3 Set the 8840A to DC volts Adjust R101 for 10 24V DC 10 mV Connect 8840A to J6 P24 Verify that the 8840A reads 10V DC 1V DC 6E 13 TROUBLESHOOTING AND REPAIR FREQUENCY AND PHASE MODULATION 6E 14 7 8 9 Set the UUT to SPCL 909 Connect a 50 ohm termination to U
48. 866426 603506 4586 4586 DD 512962 484378 484378 494781 816850 807206 362772 183548 MFRS SPLY CODE 05397 40402 04222 05397 05397 04222 05397 04222 04222 05397 5397 4222 4222 05397 04222 04222 51406 04222 04222 95215 56289 04222 56289 12982 04222 56289 89536 51406 04222 72982 12982 04222 56289 04222 51406 72982 71590 89536 05397 05397 05397 62643 51406 72982 91293 in S column indicates static sensitive part MANUFACTURERS PART NUMBER OR GENERIC TYPE C320C272M1R5EA MKT1823104056 SR151C472MATR C315C181J1G5EA C320C271J1G5EA SR291A331JATR 315 121065 SR215A201JAT SR291A820CATR C315C151J1G5EA C315C560G1G5EA SR201A101GATR 12065A1001 050 C0805C339D5GAT SR15A470GAT 08055A151JAT065B 110 061820100 SR201A220GATR SR291A270GAA VJ08050120JXAT 1950225 000252 SR151C102MATR 199D474X0035AE3 8101 100 0 0159 12065C103KAT060R 1960396 0006 1 362756 RPE110NPO18RG100 SR151A6R8CAA RPE113 C06 330 6 50V RPE121911C0G2216100V SR201A476CATR 1960224 0020 1 SR151C471KAT GRH708C0GIR8C200VPT 8101 100 060829 R220G13COGHWFAP 376871 C315C390G1G5EA CO805C102K5XAT CC805C100J5GAT KME16VB101M6 3X11RP MA180R4BPT 8101 100C0G0479C 9401 1 gt WW OF Oir ANUA REPLACEMENT PARTS Table 7 8 A8
49. CER 220PF 2 100V COG 812131 72982 121911 062216100 2 C 104 231 232 CAP POLYES 0 022UF 10 50V 715268 60935 185 2 022 K 0050 R C B 3 C 105 106 239 AL 47UF 20 50V SOLV PROOF 822403 62643 KMESOVB47RM6X11RP 17 240 242 243 822403 C 246 247 250 822403 C 251 274 506 822403 C 541 542 601 822403 C 603 613 822403 C 201 302 401 CAP CER 100PF 2 100V C0G 837609 04222 SR201A101GATR 9 C 402 404 413 837609 414 611 614 837609 C 204 210 273 CAP CER 0 01UF 20 50V X7R 816249 72982 RPE121 911X7R103M50V 26 C 406 409 501 816249 C 513 516 518 816249 C 544 602 606 816249 609 610 612 816249 615 620 624 816249 C 625 640 641 816249 C 646 647 652 816249 C 211 CAP CER 470PF 4 202 100V X7R 358275 04222 SR151C471KAT C 212 CAP POLYPR 2200 4 52 100V 854505 40402 1830222014 C 213 CAP CER 150PF 4 22 1007 512988 05397 C315C151J1G5EA C 214 216 CAP POLYPR 4700PF 5 63V 854513 40402 1830472064 2 C 215 CAP CER 390PF 2 50V COG 820530 72982 RPE122 901 COG 391 G 50V C 220 CAP POLYES 1UF 4 102 50V 733089 60935 185 1 00 K 0050 R G B C 223 224 CAP POLYES 0 22UF 10 50V 706028 60935 185 2 22 K 0050 R C B 2 C 225 CAP POLYES 0 1UF 4 102 50V 649913 60935 185 0 1 K 0050 R A B C 228 229 CAP POLYES 2 2UF 10 50V 854500 40402 1826225055 2 C 233 261 CAP POLYES 0 01UF 10 50V 715037 60935 185 01 K 0050 R 2 C 234 CAP POLYES 4700
50. Pyrofilm Div Whippany NJ 04222 AVX Corp AVX Ceramics Div Myrtle Beach SC 04713 Motorola Inc Semiconductor Group Phoenix AZ 05245 Corcom Inc Libertyville IL 05397 Union Carbide Corp Materials Systems Div Cleveland OH 05791 LYN TRON Burbank CA 06383 Panduit Corp Tinley Park IL 06665 Precision Monolithics Sub of Bourns Inc Santa Clara CA 06915 Richco Plastic Co Chicago IL 07263 Fairchild Semiconductor North American Sales Ridgeview CT 09214 General Electric Co Semiconductor Products Department Auburn NY 09969 Dale Electronics Inc Yankton SD 1AV65 Mini Circuits c o Robotron Inc Brooklyn NY 1L965 Lord Industrial Cambridge Springs PA 10059 Barker Engineering Corp Kenilworth NJ 12040 National Semiconductor Corporation Danbury CT 12060 Diodes Inc Northridge CA 12581 Hitachi Metals Inernational Hitachi Magna Lock Div Big Rapids MO 12895 Cleveland Electric Motor Co Cleveland OH 13103 Thermalloy Co Inc Dallas TX 14552 Microsemi Corp formerly Micro Semi Conductor Corp Santa Ana CA 15801 Fenwal Eletronics Inc Div of Kidde Inc Framingham MA 16469 MCL Inc LaGrange IL 16733 Cablewave Systems Inc North Haven CT 17856 Siliconix Inc Santa Clara CA 18324 Signetics Corp Sacramento CA 21845 Solitron Devices Inc Semiconductor Group Rivera Beach FL 22526 DuPont El DeN
51. R 114 RES CF 22 5 0 125 R 8 RES 39 2 1 0 25W 100 123 RES CF 33 5 0 125 R 130 131 RES 300 5 0 125W R 141 RES CF 1 8K 5 0 25W R 142 143 RES CF 20 5 0 25W R 144 145 RES MF 121 1 0 5W 100PPM R 199 RES 187 1 0 SW 100PPM R 200 RES CF 360 1 58 0 125 R 203 5 JUMPER 0 0 0 125W 32 TERM FASTON TAB 110 SOLDER U 9 1C BPLR MONOLITHIC MICROWAVE AMP U C ECL TRIPLE LINE RECEIVER U 3 IC ECL DUAL D M S F F W SET amp RESET 0 4 IXER DOUBLE BALANCED 2 500MHZ U 5 IC GAAS TRANSFER SWITCH U 7 IC STTL DUAL DIFFERENTIAL LINE DRIVER U 9 IC BPLR SELECT GAIN MSA 0404 8 2GHZ W 1 CABLE ASSY RF 2 1 2 RES NET SIP 6 PIN 5 RES 510 4 2 An in S column indicates a static sensitive part HS AWN PE REPLACEMENT PARTS 60804 1607 Figure 7 8 A8 Output PCA 7 39 REPLACEMENT PARTS 7 40 REFERENCE DESIGNATOR A gt NUMERICS gt 5 e 1 4 C 5 6 7 C 8 C 9 12 13 21 24 C 32 41 44 C 53 56 58 C 60 62 64 C 67 11 75 C 33 48 C 34 C 35 52 C 36 C 37 40 C 45 C 46 C 47 50 C 49 69 70 Q 5 C 5 8 C 65 66 C 76 CR 1 8 9 12 J 6 7 L 13 P a We Q 5 10 R 3 5 7 2 4 6 R
52. R 509 529 R 221 RES R 222 RES 224 RES R 22 RES R 228 RES R 230 RES R 231 RES R 232 RES 233 RES 234 RES R 235 RES C R 236 RES R 237 RES R 242 524 527 R 243 R 248 250 301 RES R 249 251 RES R 261 262 636 648 RES 264 634 RES 266 210 304 RES 607 13 R 268 RES M R 302 R 305 R 309 310 RES C R 401 402 R 403 R 404 R 405 411 R 406 407 409 RES R 410 R 412 R 414 R 415 R 416 R 422 425 RES R 25 424 426 R 427 R 428 RES R 501 RES 502 R 503 521 523 504 R 505 R R 510 R R 511 532 R R 512 Ri R 513 R 517 R R 518 RE column indi Table 7 3 A2 Coarse Loop FLUKE STOCK DESCRIPTION 210 0 125W 100PPM 866228 8 0 1258 100 855242 0 125W 100 866202 0 1254 100 866335 0 1254 140035 0 251 513170 513110 513170 96 1 0 125W 100 866210 0 25W 100 199650 199650 0 250 100 199616 0 250 573584 0 12510 100PPM 720268 5 0 1251 100PPM 719658 0 125 100PP 866251 0 1251 100PP 719468 719468 719468 00 105 0 5W 215135 0 125W 100 866256 t 1 0 125W 100 720037 500 10 0 5 325613 0 1251 100 816454 0 251 640961 1 0 125W 100PPM 866181 0 125W 100PP 866207 0 25W 641001 0 125W 100PPM 459859 0 25W 641035 0 125W 100
53. Remove the detector offset adjustment access screw from the bottom module plate cover 5 Zero the power meter 6 Connect the power sensor to the UUT RF OUTPUT connector 7 Note the power meter reading 8 Program the UUT for 12 dBm using the EDIT knob Be certain to use the EDIT knob to change the amplitude for this step or the special function will be automatically cleared 9 Adjust the detector offset adjustment R28 for a power meter reading 23 dB 0 1 dB below the reading obtained in step 7 Program the UUT to 12 dBm 10 Repeat steps 7 through 9 until the difference between the power measurements is 23 0 1 dB This adjustment should require three or fewer iterations TROUBLESHOOTING AND REPAIR RF LEVEL AM 11 Use the EDIT knob to program the UUT to 417 dBm Note the power meter reading 12 Use the EDIT knob to program the UUT for 2 dBm Verify that the power meter reading is 15 dB 40 2 dB below the previous reading 13 Program the UUT for SPCL 50 This disables amplitude fixed range 14 Disconnect the power sensor from the UUT and replace the detector offset adjustment access screw Mod Control PCA AM Depth Adjustment R10 6D 14 TEST EQUIPMENT DVM e Modulation Analyzer e Low Frequency Synthesized Signal Generator LFSSG REMARKS The UUT must be operated at room temperature for at least one hour with the module plate covers in place before continuing with this adjustment procedure CAUTION
54. Remove the plug in capacitor between the A10 Premodulator PCA and the A9 Sum Loop VCO PCA Remove the 6 screws holding the PCA Carefully remove the A9 Sum Loop VCO PCA Removing the A10 Premodulator PCA 5 13 1 Remove the 6 screws holding the bottom output module cover and remove the cover The 10 screws are adjustment access screws and need not be removed Disconnect the RF cable which is part of the A8 Output PCA from the A10 Premodulator PCA Disconnect the Mod Control Premodulator ribbon cable W34 from the A10 Premodulator PCA 4 Remove the plug in capacitor Cl between the 10 Premodulator PCA and the A9 Sum Loop VCO PCA 5 Remove the 6 screws holding the PCA 6 Carefully remove the 10 Premodulator PCA REMOVING THE A11 MODULATION CONTROL PCA 5 14 1 Remove the 6 screws holding the bottom output module cover and remove the cover The 10 screws are adjustment access screws and need not be removed 2 Disconnect the Mod Control Premodulator ribbon cable W34 from the A11 Mod Control PCA 3 Disconnect the two Mod Control Output ribbon cables W33 and W35 from the All Mod Control PCA Remove the 6 screws holding the PCA Carefully remove the A11 Modulation Control PCA ACCESS PROCEDURES Removing the A12 Sum Loop PCA 5 15 A WARNING THE SYNTHESIZER MODULE WHICH MUST BE RAISED TO GAIN ACCESS TO THE A12 SUM LOOP PCA IS HEAVY WHEN RAISING OR LOWERING THE MODULE OBSERVE THE PROCEDURE DESCRIB
55. SOLV CER 68PF 2 100V COG SCHOTTKY BARR ER F T 2 100V COG 8 100V C0G POLYES 0 1708 x 10 50V POLYES 0 068UF 4 1 50V POLYES 0 0150 10 50V 0805 7R 1000PF 20 1007 X7R 68PF 5 50V COG 0805 0805 0805 PROOF 50V COG 0805 50V C0G 0805 POLYES 0 2206 10 50V 10 50V CER 3300PF 1 58 50V C0G POLYES 0 04 TUF 4 10 50V 10 50V CAP POLYES 0 0220F 105 50V PROOF SMALL SIGNL ZENER UNCOMP 4 3V 5 20 0 4W DIODE SI PI ZENER UNCOMP 3 3V 5 2 DIODE 51 SCHOTTKY BARRIER ZENER UNCOMP 3 9V 10 20 0 CUR CONT RESIST DIODE 0 0MA 0 4W SMALL SIGNL 0 4W 500MW DIODE SI BV 75 10 150 ZENER 0 CO P 10 0V 5 12 5 in S column indicates a A 0 4W FLUKE STOCK 0 806752 837609 837609 837609 837609 512947 837526 837526 831526 831526 831526 831526 831526 831526 698696 MFRS SPLY MANUFACTURERS PART NUMBER TOT N 0 T E CODE OR GENERIC TYPE QTY E 51406 04222 72982 40402 51406 51406 04222 72982 05397 04222 72982 static sensitive part GRH708CO0G2R7C200VPT 3 SR201A101GATR 10 8101 100C060399C 1 1823104056 28 GRH708COG4RTC200VPT 2 RPE110C0G100G100V 2 3419 050 104 4 8101 100C0G0479C 2 CC805C100J5GAT 2 08055A470JAT050R 1 RPE121 911X7R103M
56. TEStS cse cete reete bees 6 11 6 32 RF Output 6 12 6 33 Pulse Modulator 5 6 12 6 34 Filter Teste cel ied trac comedet os tal Me cs Re 6 12 6 35 STATUS SIGNALS AND STATUS CODES 6 13 6 36 SOFTWARE DIAGNOSTIC 5 6 14 6 37 Digital Control Latch 6 14 6 38 Instrument Diagnostic 5 6 14 6 39 Set Internal 5 6 14 6 40 Display Synthesizer Loop 6 15 6A eh e A ern 6A 1 6 1 POWER SUPPLY BLOCK 6A 1 6A 2 POWER SUPPLY CIRCUIT 6A 1 6A 3 POWER SUPPLY 6A 4 6A 4 Troubleshooting 6A 4 6A 5 POWER SUPPLY ADJUSTMENT PROCEDURE 5 continued on page iv TABLE OF CONTENTS continued SECTION TITLE PAGE 6B DIGITAL CONTROLLER ccr RE xax xxx ERE Ed 6B 1 6B 1 DIGITAL CONTROLLER BLOCK DIAGRAM 6B 1 6B 2 DIGITAL CONTROLLER CIRCUIT DESCRIPTION 13 6B 1 6B 3 Micropro
57. U 2 PROM MOD OSC MS 861112 U 3 PROM MOD OSC LS 861117 70 1 55 864967 1 FUSE 25X1 Hs 2A 2507 FAST 109173 H 1 8 SCREW MACH PH 5 89 6 32 281 112236 14 15 SCREW MACH TH P STL 4 40 187 854658 16 19 WASHER FLAT FIBER 8 110353 20 23 NUT ELAST STOP HEX n 32 306308 24 27 SCREW CAP BH SCKT STL 6 32 500 542161 28 31 SCREW MACH PH P SS 8 322 150 800441 36 39 SCREW CAP SCKT SS 8 32 375 837575 40 47 WASHER FLAT SS 174 375 032 176743 H 48 50 NUT ELAST STOP HEX STL 6 32 110841 D 51752 CONN ACC D SUB FEMALE SCREWLOCK 250 854810 53 54 CONN ACC MICRO RIBBON SCREW LOCK 854737 H 55 56 WASHER FLAT 55 119 187 010 853296 57 58 WASHER FLAT BRASS 8 0 010 111062 59 63 SCREW MACH PH P AG 55 6 32 500 853986 P 2 BUSHI G COVER R F OUT PUT 868781 P 3 FILTER LINE PART 1157 773119 6 REAR PANEL 860598 7 860601 8 TRANSFORMER COVER PAINTED 860606 P 9 AIR FILTER 861005 P 10 11 CABLE ACC CLAMP 500 ID SCREW MOUNT 100974 P 12 13 CORNER BRACKET 657601 MP 14 15 CORNER HANDLE FRONT 5 25 IN GREY 861161 16 17 POWER SUPPLY BRACKET 860593 P 18 21 MOUNT VIBRATION ISOLATOR NEOPRENE 854083 22 25 PLUG BUTTON 861166 26 29 MOUNT ACC FERRULE 6 32 365 175 855036 P 32 DECAL LINE VOLTAGE FUSE RATING 861125 P 34 CABLE TIE 4 01 100W 75 DIA 172080 T 1 POWER TRANS
58. When the latching comparator U1 A on the Relay Driver PCA changes to the tripped state the positive voltage on U1 A pin 1 is applied to the inverting input of U1 C causing the output of U1 C to go low approximately OV DC This signal RPTRPL informs the Controller that the RPP has been tripped which causes the instrument to go into the RF OFF state and flashes the STATUS light Diodes CR8 and 9 provide bias voltage for the limiter diodes to set the limiting threshold The excess power detection threshold for CR1 on the Attenuator RPP PCA is set by the resistor network at the input of U1 A TROUBLESHOOTING AND REPAIR RF LEVEL AM ATTENUATOR RPPTROUBLESHOOTING Attenuator problems are most likely to be relay contact problems 6D 28 Connect the power meter to the UUT RF OUT connector and check the nominal levels at 100 kHz and 1056 MHz per Table 6D S to isolate a faulty attenuator section Table 6D 6 can be used to verify proper control of the attenuator sections versus the programmed UUT level Errors here could indicate a problem with the Controller PCA or the Relay Driver PCA 01 through Q7 and associated circuitry A through path problem on the Attenuator RPP PCA may be difficult to isolate First verify the Output PCA signal See paragraph 6D 8 If there is an apparent through path problem but one of the observed levels from Table 6D 5 is correct that associated relay may be at fault Another method to isolate a bad relay is t
59. cocto tcp teu Up to 10 000ft VIBRATION 5 to 15 Hz at 0 06 inch 15 to 25 Hz at 0 04 inch and 25 to 55 Hz at 0 02 inch double amplitude DA SHOCK MIL T 288000 Class 5 Style E 1 7 INTRODUCTION AND SPECIFICATIONS 1 8 Table 1 3 6080A AN Specifications cont ELECTROMAGNETIC COMPATIBILITY The radiated emissions induce lt 1 uV into 1 inch diameter 2 turn loop 1 inch from any surface as measured into a 50 ohm receiver COMPLIES WITH THE FOLLOWING STANDARDS CEOS of MIL STD 461B Power and interconnecting leads 0 015 to 50 MHz REO2 of MIL STD 461B 14 kHz to 10 GHz FCC Part 15 J class A CISPR 11 2 Width Height Depth 43 cm 13 3 cm 59 7 cm 17 in 5 25 in 23 5 in POWER 115 230 VAC 10 50 60 and 400 Hz 10 250 VA maximum WEIGHT lt 27 kg 60 1 5 INTRODUCTION AND SPECIFICATIONS Table 1 4 Typical Signal Generator Performance FREQUENCY 10 DIGIT DISPLAY BAND 128 256 BAND 256 512 2 BAND 512 1056 gt 7 te tace REFERENCE Internal REFERENCE
60. cont N REFERENCE FLUKE MFRS MANUFACTURERS DESIGNATOR STOCK SPLY PART NUMBER TOT T h NUMERICS 5 DESCRIPTION NO CODE OR GENERIC TYPE QTY E 5 TRANSISTOR SI PNP T092 698290 27014 MPS6562 D262 1 Q 6 8 TRANSISTOR SI N DMOS FET 10 12 783308 17856 SD215DE 3 1 RES CF 33K 52 0 25 573485 59124 CF1 4 333 JB 1 2 45 56 RES CF 4 5 0 251 513311 59124 1 4 472 J B 5 R 110 116 573311 3 4 79 RES MF 1 37K 4 15 0 5W 100 148874 91637 CMF65 1371 1 1 4 R 80 148874 R 5 40 2 4 18 0 1254 100 120221 91637 55 4022 T 1 R 6 21 RES CF 47 53 0 25W 572982 59124 CF1 4 470 5 2 7 22 RES CF 56K 53 0 251 641126 59124 CFl 4 563 J B 2 R 8 23 RES VAR CERM 10K 10 0 5W 309674 32997 33868 1 103 2 R 9 34 35 RES MF 2 15K t 12 0 125W 100PPM 719880 91637 CMF 55 2151 T 3 R 10 28 RES VAR CERM 2K 10 0 5l 309666 32997 3386R 1 202 2 R ll RES 6 81 13 0 125W 100 866314 91637 CMF556811FT 1 R 12 112 RES MF 4 99K 1 0 125W 100 714923 91637 55 4991 T 2 R 13 RES 8 66K 13 0 125W 100 720557 91637 558661 1 R M RES MF 10K 1 0 1251 100PP 719476 91637 55 1002
61. measured deviation is greater than 177 kHz 3 dB bandwidth NOTE It may be necessary to compensate for residual noise effects using the procedure presented in the manual provided with the Modulation Analyzer 8 Accuracy Test a Connect the LFSSG output to the UUT MOD INPUT connector and the DVM use a BNC T connector 4 2 PERFORMANCE TESTS 4 22 Program the UUT to SPCL 909 EXT and 10 radians phase deviation Program the LFSSG for 3 kHz and 7071V RMS as measured by the DVM Program the modulation analyzer to measure M peak in a 50 Hz to 15 kHz bandwidth Verify that the modulation analyzer reading is between 9 5 and 10 5 radians Program the LFSSG for 10 kHz and 0 7071V RMS as measured by the DVM Verify that the modulation analyzer reading is between 8 5 and 10 0 radians 3 dB bandwidth 15 kHz NOTE It may be necessary to compensate for residual noise effects using the procedure presented in the manual provided with the Modulation Analyzer 9 Incidental AM Test a Program the UUT for 100 kHz deviation INT FM on at kHz EXT FM off a level of 7 dBm and a frequency of 14 MHz Program the modulation analyzer to measure peak AM in a 0 3 to 3 kHz bandwidth Verify that the incidental AM is less than 1 Repeat steps a through cat frequencies of 20 30 40 60 80 100 160 250 320 400 550 640 700 850 950 1056 MHz 10 Residual FM Test Program the UUT for a frequenc
62. particularly off channel radio testing Specifications of the 6080A AN are provided at the end of this section The salient features of the 6080A AN are as follows RF frequency range of 0 5 MHz to 1024 MHz in 1 Hz steps RF level range of 13 to 137 dBm in 0 1 dB steps Internal and External Modulation AM FM and Pulse Internal 10 Hz to 100 kHz Synthesized Sine Wave Modulation Oscillator Fifty Storable and Recallable Memory Locations Standard IEEE 488 GPIB Interface complying with ANSI IEEE Standards 488 1 1987 and 488 2 1987 Closed case calibration capabilities for Frequency Reference AM FM and Level UNPACKING THE SIGNAL GENERATOR 1 2 The shipping container should include a 6080A AN Synthesized RF Signal generator an Operator Manual a Service Manual a line power cord and two BNC dust caps Accessories ordered for the signal generator are shipped in a separate container 1 1 INTRODUCTION AND SPECIFICATIONS 1 2 SAFETY 1 3 This manual contains information warnings and cautions that should be followed to ensure safe operation and to maintain the generator in a safe condition The signal generator is designed primarily for indoor use and may be operated in temperatures from 0 to 50 C without degradation of its safety WARNING TO AVOID ELECTRIC SHOCK USE A POWER CORD THAT HAS A THREE PRONG PLUG IF THE PROPER POWER CORD IS NOT USED THE 6080A AN CASE CAN DEVELOP AN ELECTRICAL POTENTIAL ABOVE EARTH GROUN
63. virtual ground input The average current whichis proportional to the phase error between the FM oscillator and the reference is combined with a fixed current in the input and the difference in current is amplified in the integrating loop amplifier U25 The result achieves phase lock as indicated in the previous paragraph For the wide deviation range N PI phase detector the reference and variable frequency dividers alternately clock the up down counter U1 1 between two states with Rck and Vck signals Refer to Figure 6E 3 The up down counter output four bits connect to the four most significant bits of DAC U23 alternating the DAC between two states of its total range of 16 states This output is converted to a voltage output in an op amp 050 and into a current output with resistors R134 and R94 to drive through the analog switch U24 into the loop amplifier U25 The alternating action of up down continues smoothly as long as the up down inputs do not coincide 6E 5 TROUBLESHOOTING AND REPAIR FREQUENCY AND PHASE MODULATION 6E 6 To prevent coincidence problems from occurring an approaching coincidence condition is detected with one part ofthe OVERLAP PULSE AND COINCIDENCE detector U19 using the divider outputs RSIG and VSIG The RSIG input connects to the D input of a first D flip flop and V connects to the clock input of the same flip flop This sets up the flip flop and Vckl Vck2 switch 018 so that the second flip
64. 04713 04713 65940 03508 28480 00779 00779 89536 24159 89536 89536 24159 52163 89536 24159 24759 in S column indicates a static sensitive part MANUFACTURERS PART NUMBER TOT OR GENERIC TYPE LL35VB106RM5X11C3 6 MKT1823104056 196D826X00200MA3 2 LL16VBlORM5X11CS 3 T362D157M015AS 2 SR151C102MATR 10 SR201A220GATR 1960396 0006 1 J1320R4 IMF10PCT50V CMK5223J63L29B 1830752062 5 21522 5 100 CMK5563J63L29B MKC2 273 K 63V 960106 0010 1 SR201A101GATR 3419 1000 103M 99D106X9035DA1 KMESOVB47RMOX11RP LL10VB47RM6X11C3 CC805C100J5GAT VJ0805Q180JXAT 08056102 5 85 2 22 K 0050 R C B 887154 R67333K 85 0 1 K 0050 R A B 2 P1830101011 18304710115 R15A470GAT 2 P1830331011 830102011 96D225X0015HA1 578A 158 4449 4448 5082 6264 125 4 645991 3 2 332070 7 320911 1 BREE IE CO CO REESE UTE Toy c Cn pan 4 MR O 68 114299 5087226 323 463448 MR390 5PCT WEE270 T c HS REFERENCE DESIGNATOR gt 5 gt 5 L MP MP MP MP D DO DU 99 00 23 DO A3 233 22 99 23 23 13 232 00 233123 23 50 00 0 0 50 50 0 50 dd OO 78 1 21 36 42 37 40 62 63 1 1 10 11 30 61
65. 049 PIN 866764 00779 645991 3 2 PIN FEED THRU 812735 89536 812735 45 JUMPER REC 2 05 100 025 SQ POST 530253 00779 530153 2 Q TRANSISTOR SI NPN SMALL SIGNAL TO 92 832170 04713 MPS6520RLRA Q 102 TRANSISTOR SI NEN DUAL TO 5 640656 27014 LM394C Q 103 104 TRANSISTOR SI PNP SMALL SIGNAL 225599 07263 214250 Q 201 204 502 TRANSISTOR SI VMOS PWR TO 237 VN10KM 640516 17856 11809 0 A 206 607 TRANSISTOR SI HI FREQ SMALL SIGNL D 04713 BFR91 Q Q 403 404 TRANSISTOR SI PNP 1092 698233 04713 2N3906RLRA 0 405 406 TRANSISTOR SI NPN HI FREQ SMALL SIGNL 722256 04713 MRF581 Q 501 TRANSISTOR SI PNP T092 698290 27014 MPS6562 D262 Q 504 505 TRANSISTOR SI PNP HI SPEED SWITCH 369629 04713 215771 Q 506 TRANSISTOR SI N DMOS FET TO 72 783308 17856 SD215DE Q 606 TRANSISTOR SI NPN SMALL SIGNAL 248351 04713 5918 0 611 TRANSISTOR SI NEN SMALL SIGNAL 698225 04713 2N3904RLRA2 R 1 RES MF 90 9K 71 19 0 12511 100PP 720581 91637 55 9092 1 102 RES VAR CERM 10K 4 105 0 5W 309674 32997 3386R 1 103 103 245 246 RES MF 4 99 1 0 125W 100PP 114923 91637 55 4991 1 1 R 104 RES 200K 1 0 125W 100PP 719831 91637 CMF 55 2003 1 R RES MF 10K 1 0 125W 100 719476 91637 CMF 55 1002 T l R 719476 R 106 RES MF 3 32K 1 0 125W 100 866269 91637 CMF553321FT R 107 110 115 RES MF 499 1 0 125W 100PP 816462 91637 C
66. 1 BOVLIOA H0123130 3SVHd 801093130 5 IdN 33 713 dWY d001 NWd NW3 2 V sen 1 ova A3QIH HOLIMS 93315 W4 V ZHW 02 HOLIMS K 39NVH 1X3 ANI 744 193 ANUSOU uno4d A8 zen Wa 1X3 15 2 2 LLY PLYO PN 193138 ANdNi OH1NOO 08 1 1289 ZHW 09 Cc ZHW 09 iexiussous W4 LNI NIVO Wd W3 4015 YOLVTTIOSO W4 ZHW 08 NOILVINGOW H9IH 6 3 Figure 6E 2 Block Diagram TROUBLESHOOTING AND REPAIR FREQUENCY AND PHASE MODULATION 6E 4 The circuits of and Q4 provide clean power supply voltages of nominal 14V DC and 14V DC respectively The circuits of quad op amp 05 and Q6 and Q7 provide steering for the oscillator in the DC FM mode of operation Diode CR14 provides a stable voltage reference which is translated to the required varactor control voltages as required One of the op amps of U5 with Q6 along with the FM STEER and V TC COMP inputs and also variable resistors R35 and R39 and other resistors provide the nominal voltage at Q7 for the correct programmed voltage V PROG at 2 This is divided in the resistor string of R40 R41 R74 and R133 along with the loop control voltage PH DET at TP12 to provide the correct voltage VCO CONTROL for correct frequency ofthe oscillator The control line HIDEVL is programmed by the instrument contro
67. 1 0 0 1048 960 1 1 1 1 1 1 6 25 TROUBLESHOOTING AND REPAIR FREQUENCY SYNTHESIS 6 26 These levels are as measured on the spectrum analyzer The actual levels are 20 dB higher The levels in Table 6C 5 are approximate and can vary as much as 3 dB Table 6C 5 Discriminator RF Section Levels FRONT PANEL COARSE LOOP Q404 C Q405 C C421 A25 J9 FREQUENCY FREQUENCY 544 MHz 640 MHz 9 dBm 3 dBm 3 dBm 3 dBm 704 MHz 800 MHz 11 dBm 3 dBm 0 dBm 6 dBm 1048 MHz 960 MHz 9 dBm 2 dBm 2 dBm 5 dBm If the power is correct at the collector of Q405 but low at C421 the problem is probably in the switched low pass filter Ifthe power is correct at C421 but low at the cable connecting to J10 the problem is probably in the coupler or delay line If the power is correct at the output of the delay line and the DC voltage at the output of the mixeris nearly zero the problem 1 probably defective mixer Any problem with the delay line assembly will necessitate replacing the whole assembly including the cable To check the discriminator amplifier Q101 105 remove the end of the resistor that connects to the Discriminator PCA A25 J3 Connect the resistor to the UUT front panel MOD OUTPUT Program the UUT to MOD FREQ 1 kHz and MOD LEVEL 4 mV There should be a 500 mV p p 1 kHz signal at TP9 COARSE LOOP PCA ADJUSTMENTS 6C 17 Refer to Table 6C 6 for information about the test p
68. 119 RES MF 182 4 12 0 25W 100 799726 91637 CCF 501820F 3 R 7 8 116 RES 30 1 4 15 0 25W L00PPM 799692 91637 CCF 5030RIF 4 An in S column indicates a Static sensitive part 7 37 REPLACEMENT PARTS 7 38 Table 7 8 A8 Output PCA cont FLUKE STOCK 0 799692 720409 325613 155101 8515 12047 74002 7400 72002 72002 14004 74004 740084 854695 573110 573170 746354 783290 740068 851563 719955 241596 233163 719468 740050 740092 740092 740035 740035 866223 631986 747725 573113 557231 215743 851472 866186 714873 CO O Fo 719450 799817 513212 866231 218032 832030 215135 120466 855242 807735 146214 799791 573121 844969 557215 199175 830885 844972 513220 572958 801019 845032 712271 867069 512889 713219 369702 454959 851282 854831 801308 173226 808568 459974 MFRS MANUFACTURERS SPLY PART NUMBER CODE OR GENERIC 91637 CMF555761FT 1 32997 33868 1 501 0112 FF1 463R4 80031 5043ED267K1 80031 5043ED665K 8003 8 5 15 8 8003 0 5 11 8 59124 MF553010F 8003 8 5 24 8003 8 5P120E B 59124 RDS1 8202J 59124 CF1 4 102 JB 59124 RM 3B 280271B 59124 RM73B 2BJ361B 80031 1 8 5P75E B 91637 CMF 55 1401 1 1 91637 CMF552551FT 1 91637 CMF651211FT 1 91637 652670 1 91637 55 1001 1 1
69. 2 R 14 RES VAR CERM 500 4 10 0 5W 325613 32997 33868 1 501 R 145 RES VAR CERM 2K 20 0 5W 226076 32997 3329H 1 202 R 146 RES VAR CERM 100 208 0 5i 193052 80294 3329H 1 101 147 RES MF 665 4 15 0 125W 100 866330 91637 CMF6650FT 1 RT THERMISTOR DISC NEG 10K 10 25C 104596 15801 0 TP 31 23 15 TERM FASTON 110 SOLDER 512889 00779 62395 1 13 0 3 MONOLITHIC MICROWAVE AMP 773218 7 751 530304 3 U 4 IC ECL DUAL D M S F F W SET amp RESET 454959 04713 MC10131P 0 5 IC OP AMP QUAD LOW NOISE 851829 06665 0 470 6 IC ALSTTL HEX INVERTERS 837716 01292 SN74ALS04BN 7 5 1 2 5 1 9 IC LSTTL DUAL D F F EDG TRG W CLR 393124 04713 5 141674 3 0 8 22 51 IC LSTTL QUAD 2 INPUT NAND GATE 393033 04713 SN74LS00N 3 0 9 14 IC LSTIL DUAL DIV BY 2 DIV BY 5 CNTR 483594 01295 SN74LS390N 2 U 10 16 17 IC LSTIL DUAL 4 INPUT NAND GATE 393280 04713 SN74LS20N 3 0 1 IC LSTTL SYNC DIVIDE BY 16 BIN CNTR 393231 27014 DM74LS193N U 13 49 IC FTTL DUAL 4 INPUT MULTIPLEXER 659912 04713 MC74F153N 2 U 15 IC LSTTL TRIPLE 3 INPUT NOR 393090 04713 SN74LS27N U 18 IC LSTTL QUAD 2 INPUT NOR GATE 393041 04713 SN74LS02N U 20 IC LSTTL RETRG MONOSTAB MULTIVB W CLR 412734 04713 SN74LS122N U 21 IC FTIL DUAL D F F EDG TRG W CL amp SET 659508 07263 74F74PC U 23 IC BPLR 10BIT DAC 10BIT ACCUR CUR OUT 477760 24355 AD561D U 24 IC CMOS DUAL SPDT ANALOG SWITCH 853598 34371 HI1 0303 5
70. 2 kHz dev The 8840A should read 15V DC x 200 mV DC Repeat these steps until both specs are met Remove the 8840A from Set the 8840A to DC volts autorange Connect the 8840A to TP12 Set the UUT to 300 kHz dev INT on 1 kHz mod rate Key SPCL 942 to set FM Steer DAC to 2048 Adjust R39 for 0 0V DC 20 mV DC Set the UUT to 200 kHz dev INT on 1 kHz mod rate Set the FM Steer DAC to 2048 Set the 8840A to DC volts autorange Connect the 8840A to TP12 Adjust R35 for 0 0V DC 20 mV DC Set the UUT to INT 10 kHz mod rate Connect oscilloscope channel 1 to TP8 and channel 2 to TP6 Set the UUT for 200 kHz Adjust R63 until one pulse on channel 1 is exactly in the middle of two pulses on channel 2 This represents a 50 alignment ofthe pulses on TP6 and 8 Set the UUT to 10 kHz dev Check for a pulse alignment of 22 7896 3 Remove scope probes Set the UUT to INT 5 rad 6M Dev 5 kHz mod rate Set the 8901A to FM AVE 300 Hz HP 15 kHz LP 96 Note the 8901A reads 100 Press the kHz button on the UUT Adjust R104 for a reading of 10296 to 102 296 on the 8901 A Set the UUT to 800 MHz 50 kHz dev 5 kHz mod rate INT ACFM Set the 8901 for peak off gt 20 kHz filter and all other filters off Adjust R107 for equal plus and minus readings around 50 kHz Plus and minus readings must be within 5 kHz of each other This is a distortion check Set the UUT
71. 470 5 0 25W RES CF 200 5 0 25W RES CERM 47 5 125W 200PPM 1206 RES CERM 120 5 125W 200PPM 1206 RES CERM 82 5 125W 200PPM 1206 RES CF 100 5 0 25W RES CF 160 5 0 251 RES 10K 1 0 125W 100PPM RES 680 5 0 251 RES 7 5 5 0 25W RES CERM 150 17 55 125W 200 1206 RES CERM 100 5 125W 200PPM 1206 RES CC 150 17 55 0 5W IC BPLR MONOLITHIC MICROWAVE AMP IC COMPARATOR QUAD 14 PIN SOIC FLUKE STOCK 0 800854 800862 855098 806380 140563 4133 773218 741561 MFRS SPLY CODE 51406 51406 51406 51406 04222 05397 in S column indicates a static sensitive part MANUFACTURERS PART NUMBER OR GENERIC TYPE MA181R8B MA182R7B MA1844R7B MA183R6B 1206FA 220 ATOSOR CO805C101J5GAT C0805C339D5GAT VJ0805Q8R2DXAT GRH708C0G5R6C200VPT CC805C100J5GAT 1990225 0025 1 08055A3R6CATO51B GRH708C0G2R7C200VPT GRM42 6COG4 3K50VPB GRH708COG4R7C200VPT 120 65A0R8DATO50R GRH708COG1R8C200VPT 100471 VJ0805Q1RODXAT BB215 BA885 645991 3 75060 012 5087227 213 EJ20N22C000 E21935D E02135 D 3904RLRA2 1 4 4710 F1 4VT201J 1382BJ4 108 73B 2BJ121B Q PS DBD RM73B 2B J82R0B CF1 4VT1010 CF1 4VT161J MF50VTD1002F CF1 4VT681J CF1 4VTTR5J CRCW 1206 1500J B02 RM73B2BJ101B EB1515 MSA0304 1M339DT
72. 5 6B 8 6 24 Repairing Calibration Compensation Memory Checksum Errors 6B 9 6B 25 Calibration Compensation Memory Origin 5 5 6B 9 6B 26 FRONT PANEL CIRCUIT DESCRIPTION 6B 9 6B 27 Display Aces I tl Raa Whe og bate eee iere 6B 10 6B 28 Data 5 6B 10 6B 29 Display Filament 6B 10 6B 30 Bright Digit Effect 2 222 21 6B 10 6B 31 Switchboard 6B 10 6B 32 Remote 2 6B 10 6B 33 Edit Knob Interface cob Se 6B 11 6B 34 Display Blanking 6B 11 6B 35 Operate Standby Selection 6B 11 6B 36 FRONT PANEL 6B 11 6B 37 Display and 5 6B 11 ec FREQUENCY 5 5 5 6C 1 FREQUENCY 1 6C 2 SUB SYNTHESIZER BLOCK DIAGRAM 6C 1 6C 3 SUB SYNTHESIZER CIRCUIT DESCRIPTION 6C 1 6C 4 SUB SYNTHESIZER TROUBLESHOOTING 6C 9
73. 5 0 25W 148130 01121 CB2235 R 5 RES CC 43K 4 52 0 25W 193367 01121 CB4335 R 6 RES MF 45 3 12 0 125W 100PPM 296749 91637 CMF5545R3FT 1 7 RES MF 267 1 15 0 125 100 866223 91637 CMF552670FT 1 R 89 14 RES MF 4 75K 41 19 0 125W 100PPM 720276 91637 55 4751 TH 5 15 31 120216 An in S column indicates a static sensitive part REFERENCE DESIGNATOR A gt NUMERICS gt 5 10 13 gt 3 Table 7 15 A15 Power Supply DESCRIPTION RES F 221K 13 01258 25PPM RES 4 42K 4 15 0 1250 100 RES MF 2 21K E 1251 100PPM RES 73 2 1 4 100PPM RES MF 66 5K 15 0 1 251 100 RES CC 2 4K 4 52 0 50 RES CF 10K 4 53 0 208 RES MF 22 1 1 0 125 100PPM RES 5 0 25W RES 732 1 15 0 125W 100 RES 442 4 15 0 1250 100 RES CC 100 4 108 0 5W RES 1 5 0 25W RES 115 1 12 0 125W 100 RES 2 61 4 19 0 5W LOOPPM RES MF 127 1 15 0 125 100 RES MF 3 65K 1 15 0 5W 100PP RES CC 2 4K 5 0 25 RES 1K 5 0 5W RES MP 42K 1 15 1250 25PP RES VAR CERM 5K 4 102 0 5W RES CF 20K 5 0 258 TERM FASTON TAB 110 SOLDER C OP AMP QUAD HIGH SPEED LOW NOISE
74. 65K 1 0 25W 100PPM 854443 71590 5063JD3651F R 631 RES CF 5 1 5 0 125W 854372 59124 RDS21 85R1d R 632 644 RES MF 200 1 0 25W 100PPM 799759 91637 CCF 502000F R RES MF 2 26K 1 0 25W 100PPM 854422 71590 5063JD2261F R 637 RES MF 15 1 0 25W 100 799767 91637 5015 0 R 638 RES 2 87 0 25 LOOPPM 854430 71590 50630D2871F R 639 RES MF 221 1 0 25W 100 799908 91637 CCF 502210F R 640 RES MF 2 94K 1 0 25W 100 854435 71590 5063JD2941F R 641 RES MF 249 15 0 2511 100PPM 854414 71590 5063JD2490F R 642 RES CF 8 2 5 0 1251 854377 59124 80821 88827 R 643 RES 150 1 0 25 100 838508 91637 CCF 501500F 502 SWITCH MODULE 5 SEALED 6 POS 831909 00779 5 435166 601 TRANSFORMER RF 70KHZ 200MHZ 2 1 851634 1AV65 12 11 65 1 12 14 TERM FASTON TAB 110 SOLDER 512889 00779 62395 1 19 512889 13 20 28 PIN SINGLE PWB 0 025 SQ 267500 00779 87623 1 203 IXER DOUBLE BALANCED 1 500 MHZ 733105 16469 SBL 1 27 U 204 512 IC CMOS RETRG MONOSTAB MULTIVB W CLR 741496 12040 MM74HC123AN U 205 207 AMP LO NOISE 8 PIN DIP 417145 18324 5534 U 208 509 IC COMPARATOR QUAD 14 PIN DIP 387233 2040 144339 U 209 508 IC 0P AMP JFET INPUT 8 DIP 412119 12040 LF356 U 210 DUAL LO PWR 8 PIN DIP 478354 12040 1M393N U 301 IC DIVIDE BY 4 PRESCALER 854690 33297 UPB582C U
75. 775338 812826 842849 860643 861133 860960 657601 812743 812750 812768 528539 772236 772236 772236 772236 376822 571968 541730 861047 407908 868799 cont MFRS SPLY CODE 05397 89536 89536 89536 89536 89536 89536 89536 06915 06915 89536 89536 89536 89536 89536 89536 89536 89536 89536 55566 21845 89536 89536 06383 22526 89536 89536 89536 89536 89536 89536 89536 89536 89536 89536 89536 89536 89536 89536 89536 89536 05397 89536 89536 89536 89536 89536 06383 89536 column indicates a static sensitive part MANUFACTURERS PART NUMBER OR GENERIC TYPE C320C102J5G5EA 772236 867155 571968 868930 860952 860957 541730 8 MWSSEB 1 01A 868950 868877 868880 860747 860739 860754 772236 854658 837575 7229 6 SF1132 6002 493551 861161 SST 1M 65524 136 657718 764548 812818 861174 868794 861026 775338 812826 842849 860643 861133 860960 657601 812743 812750 812768 C320C102J5G5EA 112236 376822 571968 541730 861047 ABMM A C 868799 REPLACEMENT PARTS TOT 38 N PN OC 7 5 REPLACEMENT PARTS Table 7 1 6080A AN Final Assembly REFERENCE FLUKE DESIGNATOR STOCK A NUMERICS 5 DESCRIPTION NO MP 63 FILTER SUBASSY SYNTH MODULE 861109 R 1 RES CF 0 51 5 0 25W 381954
76. 784 9942 Malaysia Mecomb Malaysia Sdn Bhd P O Box 24 46700 Petaling Jaya Selangor Tel 60 3 774 3422 Mexico Mexel Servicios en Computacion Instrumentacion y Perifericos Blvd Adolfo Lopez Mateos No 163 Col Mixcoac Mexico D F Tel 52 5 563 5411 Netherlands Philips Nederland Test amp Meetapparaten Div Postbus 115 5000 AC Tilburg Tel 31 13 352445 New Zealand Philips Customer Support Scientific amp Industrial Division 2 Wagener Place Mt Albert Auckland Tel 64 9 894 160 Norway Morgenstierne amp Co A S Konghellegate 3 P O Box 6688 Rodelokka Oslo 5 Tel 47 2 356110 8 89 TECHNICAL SERVICE CENTERS Pakistan International Operations PAK Ltd 505 Muhammadi House Chundrigar Road P O Box 5323 Karachi Tel 92 21 221127 239052 Peru Importaciones amp Representaciones Electronicas S A Avad Franklin D Roosevelt 105 Lima 1 Tel 51 14 288650 Philippines Spark Radio amp Electronics Inc Greenhills P O Box 610 San Juan Metro Manila Zip 3113 Tel 63 2 775192 Portugal Decada Espectral Equipmentos de Elec e Cientificos Av Bomberios Voluntarios Lote 102B Miraflores Alges 1495 Lisboa Tel 351 1 410 3420 Singapore Rank O Connor s Singapore Pte Ltd 98 Pasir Panjang Road Singapore 0511 Tel 65 4737944 South Africa South African Philips Pty Ltd Service Department 195 Main Rd Martindale Johannesburg 2092 Tel 27 11 470
77. 80031 1 8 5 51 80031 1 8 5 160 80031 1 8 5 18 91637 552670 1 59124 CFl1 4R51JB 59124 RM73B 2BJ111B 59124 1 4 431 5 59124 1 42717 32997 3386R 1 201 91637 558871 1 91637 55150 1 91637 551102 2 91637 55 1000 F 1 1 91637 CCF 5018R2F 59124 1 4 152 J 91637 554750 01121 85145 91637 CMF556040FT 1 32997 3386R OT1 10 91637 CMF 55 6491 F 1 1 91637 5530 1 59124 RM73B 28J270B 09969 1206 100 2 02 91637 501001 59124 CF1 4 471 JB 59124 8 521 83907 59124 RDS2 1 8220J 91637 503982 59124 1 83300 59124 80521 83017 65940 8252182 65940 257208 91637 CMF651210FT 1 91637 CMF651870FT 1 59124 CF1 4361J 91637 FRJ 50 00779 62395 1 7E751 MSA0304 04713 10116 04713 MC10131P 1AV65 33025 40 502 2000 01295 UA9638CP 7 751 5 85 2025 89536 808568 91637 5 08 01 5116 REFERENCE DESIGNATOR gt 5 gt 5 DESCRIPTION R 201 R 9 RES MF 5 76K 1 0 125W 100PPM R 0 RES VAR CERM 500 10 0 5W R 1 53 7 RES 63 4 t 12 0 511 100PPM R 2 RES 2 61 1 15 125W 100PPM R 3 RES 6 65K 1 0 125W 100PPM R 4 80 82 RES 15 4 52 0 125W R 6 17 202 RES 11 5 0 125W R m 60 RES 301 1 0 125W 100 R 20 21 42 RES 24 5 0 125W R 43 55 56 R 22 41 RES
78. 821 JB CF1 4 103 JB 1 4 102 JB 3221H 104 CMF551503FT 1 SF CO CIN WW REPLACEMENT PARTS Table 7 14 A14 FM PCA cont N REFERENCE FLUKE MFRS MANUFACTURERS 0 DESIGNATOR STOCK SPLY PART NUMBER TOT T A NUMERICS 5 NO CODE OR GENERIC TYPE QTY E 66 RES 8 45 71 15 0 125 100PPM 866673 59124 MF50VDT8451F 1 R 74 RES 499 1 1 0 125W 100PPM 866686 59124 MF50VDT4990F 1 R 75 81 RES CF 36 5 0 25W 643817 65940 8257360 2 R 76 82 M 5W 108951 01121 EB5115 2 R 77 84 RES MF 4 99K 1 19 0 12511 100PPM 714923 91637 CMF 55 4991 1 1 2 R 78 83 RES MF 10K 18 0 1251 100 719476 91637 CMF 55 1002 T l 2 R 79 RES 22 6 17 15 0 1250 100PPM 866301 91637 CMF552262FT 1 R 80 RES 44 2K 1 0 125W 100 271676 91637 CMF554422FT 1 R 85 RES CF 3 6K 5 0 250 866715 59124 CF1 4VT362d R 87 RES MF 47 5K 1 0 125W 100PPM 866665 59124 MF50VTB4152F 89 123 RES CF 33K 1 55 0 25W 133667 59124 CF1 4 VT333d 2 R 91 92 RES CF 3 3K 5 0 25W 854554 59124 CF1 4VT 3327 REEL 2 R 95 RES MF 442K 17 19 0 1251 100 866678 59124 MF50V
79. 860978 89536 861146 89536 861042 89536 868786 06383 55 89536 861153 89536 02660 06383 55 25 510 89536 868906 89536 857748 89536 860924 89536 860721 89536 860770 89536 860791 89536 860759 89536 860734 89536 860762 89536 860742 89536 860775 89536 860767 89536 860726 column indicates a static sensitive part GENERIC QTY TOT On N 0 T E REFERENCE DESIGNATOR gt 5 X rg tg ci 55555 5 JU hg Fg as E Table 7 1 1 7 2 1 6 7 9 12 lt 16 20 101 104 201 216 301 310 401 402 501 514 601 613 701 702 801 808 901 930 937 944 933 936 1 3 4 5 21 23 24 53 55 56 2 3 32 35 33 34 1 41 42 2 36 37 40 43 44 mn OY gt ka 1 1 41 101 102 201 221 301 303 501 503 701 707 42 43 903 905 1 13 19 20 57 58 62 An in S A40 CAP CER 1000 5 50V COG SCREW MACH PH P MAG SS 6 32 281 SCREW MACH P MAG 55 6 32 1 00 WASHER SPRING STL 138 281 020 BARRIER OUTPUT BOARD PLATED OUTPUT AMP COVER PLATED SUM LOOP LID PLATED AIDE PCB PULL CLAMP CABLE SELF ADHES 1 00X 88X 055 CABLE ACCESSORY CLAMP ADHESIVE NYLON OUTPUT MODULE FILTER
80. 866249 0 25W 572974 5 0 254 573212 0 25W 573410 55 0 251 513311 5 0 25W 721571 1 0 25W 100 854398 18 0 25W 100PPM 199668 1 0 254 100 854419 1 0 251 100 930679 830679 1 0 25W 100 854393 55 0 251 513139 1 0 25W 100PPM 199726 58 0 251 513048 5 0 125W 557231 5 0 125W 854786 0 125W 830893 0 125W 140068 5 0 25W 830596 58 0 251 513063 r 1 0 25W 100PPM 799734 0 125W 854380 r 1 0 125W 100PPM 720144 1 0 5W 100PPM 112152 1 0 1251 100 720292 15 0 1291 100PPM 866272 0 250 100 199916 1 58 1250 200PPM 1206 845458 845458 0 250 641019 0 125 100 719690 0 250 573014 0 254 573071 251 513238 0 125W 25PPM 851212 0 125W 25PPM 851238 125W 100PPM 719815 0 125W 100PPM 720383 0 125W 100PPM 120045 0 250 513055 0 258 641050 cate static sensitive part ANUFACTURERS PART NUMBER F556980FT 1 F5530RIFT 1 F551540FT 1 F553740FT 1 8 5P18E B 1 4 102 J B 551960 1 063JD51RIF 063JD33R2F 1 4 104 J B 551471 F558250FT 386R OT1 10 F951371FT F553011FT 386R 1 501 F552490FT F1 43R0JB F5586R6FT F551780FT F1 46R2JB F1 4120JB F557150FT 4240JB 063JD8450F CF 50 1000F 0632D3920F 063JD68R1F 063JD40R2F Fl 4 511 JB CF 501820F 1 4 181 JB F552552FT 9 F 55 4531 F F 55 2001 F F555491F F553012FT 1 Fl 4 201 F1 4 390 5
81. AND PHASE MODULATION 6E 10 MODULATION CONTROL CIRCUIT DESCRIPTION 6E 8 The following description applies only to the FM modulation circuitry on the Modulation Control PCA A11 which is covered in three parts FM input voltage processing FM STEER and SUN STEER voltage generation FM control signals generation FM Input Voltage Processing 6E 9 The circuits in the list below serve to select and amplify the external FM input signal and the internal mod oscillator signal from a level of 1V AC peak to a level of 4V AC peak at the top of each FM range 4 MHz MHz etc and to provide a vernier output within each range as the multiplying DAC is programmed by the controller Op Amp U27 Associated input resistors capacitors and CMOS switches U39 DAC p o U34 and Op Amp U9A Inverter amp U9B The selection of combinations of EXTAC FM or EXTDC FM and INT FM inputs is made with the CMOS switches in U39 with its associated resistors and capacitors at the input of Op Amp 027 The resistor R82 sets the gain so that a AC peak signal 18 amplified to 4V AC peak The FM DEV DAC U34 1 2 is set to 3600 counts out of 4096 at full scale The FM DEV DAC and op amp U9A produces 4V AC peak to the inverter amplifier circuit U9B which in conjunction with CMOS switch Q6 either amplifies directly or inverts the signal to produce the proper output polarity This accommodates the instrument action of either over or under programming
82. ASSY PROM UPPER HALF PROM LOWER HALF CABLE ASSY 10 CKT RIBBON JUMPER CABLE ASSY OUTPUT MOD CONTROL CABLE ASSY PREMOD MOD CTRL A50 SCREW MACH PH MAG SS 6 32 281 SCREW MACH TH P STL 4 40 187 SCREW CAP SCKT SS 8 32 375 FASTENER SWAGED CHASSIS AL 6 32 ADAPTOR COAX SMA M N M CORE TOROID FERRITE 20 14 5 7 5 CORNER HANDLE FRONT 5 25 IN GREY CABLE TIE 4 0L 100W 75 DIA HEADER 1 ROW 100CTR RT ANG 36 PIN LENS DISPLAY ENCODER WHEEL SHIELD DISPLAY BUSHING INSULATION R F OUTPUT KNOB ENCODER GREY ENCODER MOLDED POWER BUTTON ON OFF DECAL FRONT PANEL FRONT PANEL SWITCH SHIELD DECAL LENS RF OUTPUT BRACKET CORNER BRACKET SWITCH ELASTOMERIC LEFT SWITCH ELASTOMERIC CENTER SWITCH ELASTOMERIC RIGHT PLATED 60 CAP CER 1000PF 5 50V COG SCREW MACH PH P MAG 8 6 32 281 SCREW MACH PH P SS 6 32X 750 WASHER SPRING STL 138 281 020 AIDE PCB PULL HEAT SINK DIVIDER FOR 1 IN COARSE CABLE TIE ANCHOR ADHSV 160TIE DECAL MODULE WARNING DESCRIPTION ___ 6080A AN Final Assembly FLUKE STOCK 528539 772236 772236 7712236 772236 772236 772236 772236 772236 867155 867155 571968 868930 860952 860957 541730 513606 838300 868950 868877 868880 860747 860739 860754 772236 854658 837575 837856 516963 493551 861161 172080 563403 657718 764548 812818 861174 868794 861026
83. Both the frequency and the pulse width are set numerically through front panel entry or via IEEE commands In pulse generation mode MOD OUT is terminated with a nominal 180 ohms To avoid the ambiguity of the pulse output from being set to a DC value the software limits the pulse width to a value that is no wider than the set period minus 100 ns and it prevents it from being set narrower than 100 ns See the Special Function list in Appendix B for selections modulation oscillator modes of operations The appropriate Special Functions allow the selection of direct digital synthesis output waveform pulse generator and pulse width setting In addition by selecting the appropriate special function code it is possible to enable MOD OUT to be continuously on default or to be turned on only during the selection of internal modulation Signal Routing 6F 5 The modulation oscillator is set up to select the active outputs by means of six analog switches Signals from U1 control the various switch functions to route the pulse generator and direct digital dynthesizer output signals to the two outputs INT MOD MOD OUT of the Modulation Oscillator PCA The two switches associated with U9A 51 S2 U6A 6 facilitate the connection of the direct digital synthesizer to the internal modulation source INT MOD The two switches associated with U11B 53 S4 U6C U6D facilitate the connection of the direct digital dynthesizer to the modulation o
84. C OP AMP SELECTED GBW 600KHZ IC COMPARATOR QUAD 14 PIN DIP IC VOLT REG FIXED 24 VOLTS 1 5 AMPS C VOLT REG FIXED 5 VOLTS 1 5 AMPS C VOLT REG FIXED 15 VOLTS 1 5 AMPS VOLT REG HIGH VOLTAGE IC VOLT REG ADJ 1 2 TO 37 V 1 5 AMPS 723353 460410 cont MFRS CODE OR GENERIC TYPE ODD OOW OW gt OWW O19 n S column indicates a static sensitive part REPLACEMENT PARTS ANUFACTURERS PART NUMBER CMF552213FT 9 MFF1 84421F 552211 1 CMF5573R2FT 1 CMF556652FT 1 2425 CF1 4 1030 REEL CMF552212FT 1 CB3025 557320 1 MFF1 84420F 1011 CF1 4 5R6 5 CMF55150FT 1 CMF652671FT 1 CMF551270FT 1 MFF1 223651F CB2425 1025 CMF554021FT 9 3386W W91 502 203 78 0 L M M M L L 22 Co CO 7 63 REPLACEMENT PARTS 281 6080A 1604 bTdl Figure 7 15 A15 Power Supply PCA 7 64 REPLACEMENT PARTS Table 7 16 16 IEEE 488 Connector PCA See Figure 7 16 N REFERENCE FLUKE MFRS MANUFACTURERS 0 DESIGNATOR STOCK PART NUMBER TOT T A gt DESCRIPTIION 9 NO CODE OR GENERIC QTY E H 3 d SPACER SWAGED BROACH RND BR 6 32 187 854666 55566 7332B 632 B 14 2 J 2 CONN MICRO RIBBON REC PWB 24 POS 851675 52500 57 20240 23 1
85. CF 120 5 0 125W 23 40 103 RES CF 2K 5 0 125W R a 27 100 RES CF 1K 5 0 25W R R 30 32 RES CERM 270 5 125W 200PPM 1206 R 31 RES CERM 360 4 55 125W 200 1206 R 33 RES CF 75 5 0 125W R 38 RES MF 1 4K 1 125W 100PPM 39 52 RES 2 55K 1 0 125W 100 R 44 RES MF 1 21K 1 0 5W 100PPM R 45 46 RES MF 267 1 0 5W 100PPM R 48 51 RES MF 1K 4 12 0 125W 100 49 13 16 RES CF 51 5 0 125W Rs RES CF 160 5 0 125W 122 R 58 71 74 RES CF 18 5 0 125W R 59 68 RES MF 267 1 0 125W 100PPM R RES CF 0 51 5 0 25W R 63 RES CERM 110 5 125W 200PPM 1206 R 69 RES CF 430 5 0 25W R 70 RES CF 270 5 0 125W R 72 RES VAR CER 200 10 0 5W R 83 RES MF 8 8 7K 1t 1258 100PPM R 8 RES 115 15 0 1250 100 85 RES 11 1 0 251 50 R 87 RES 100 18 0 125W 100PPM 88 RES 18 2 15 0 25W LOOPPM R 90 RES CF 1 5K 5 0 251 R 91 RES MF 475 1 0 125W 100 R 9 RES CC 510 5 0 25 R 95 RES MF 604 1 0 125W 100PPM R 96 RES VAR CERM 100 10 0 5W R 9 RES 6 49K 1 0 125W 100PPM R 98 99 RES F 30 1 3 19 40 125W LOOPPM 101 102 RES CERM 27 5 125W 200 1206 R 104 RES CERM 10 5 125W 200PPM 1206 R 0 RES 1K 1 0 1251 100 R 2 RES CF 470 55 0 25W R 3 115 RES CF 39 4 52 0 125W
86. CF 91 4 58 0 250 RES CF 56 4 55 0 25W RES MF 21 5K 1 0 1251 100 RES MF 36 5K 1 0 125W 100 RES 100 4 18 0 1258 100 RES 59 0 RES CF 47K 4 RES CF 2 1 5 RES VAR CERM RES VAR CERM 1K 0 1250 100 1250 100 18 0 5 100 0 254 0 251 5K 4 208 0 5W 30 0 51 RES MF 150 15 0 1250 100 RES CERM 62 5 125W 200PPM 1206 RES CERM 220 t 5 125W 200 1206 RES VAR CERM 500 20 0 51 TERM FASTON TAB 110 SOLDER PIN SINGLE PWB 0 025 SQ 05 3 8 LINE DCDR W ENABLE OS OCTAL D F F W RESET 7533L TESTED QUAD LOW NOISE OS DU L 8 BIT MULTIPLYING DAC OS QUAD 2 INPUT AND GATE L TRIPLE LINE RECEIVER TL DUAL D F F EDG TRG W CL amp SET TL QUAD 2 INPUT NAND GATE 360 CELL GATE ARRAY Cas C C C HQ co TE 19 H C2 cj 02 EH C 3 33 3 3 3 NAND GATE TTL QUAD 2 TL DUAL D F F EDG TRG W SET amp CLR FLUKE SSE 226084 193060 720516 854674 746347 226068 512889 512889 267500 713036 743286 143286 802280 851929 854448 141801 369702 659508 654640 123100 418269 363580 MFRS SPLY CODE 12259 00779 00779 98159 00779 04713 17856 04713 04713 91637 91637 91637 91637 in S column indicates a static sensitive part R
87. CLOSED CASE NO ERROR CALIBRATION CODES User measurement indicated problem ERROR CODES 303 306 ERROR CODES CONTROLLER PRESENT See Sec 6B OK CONTINUED PROBLEM FREQUENCY LEVEL SYNTHESIS 334 336 320 333 240 241 MODULATION 241 307 319 If multiple problems 247 249 exist they should be addressed in the order 302 1 Frequency AM See Sec 6D 2 Level FM See Sec 6E MOD OSC See Sec 6F 242 247 339 356 302 302 See Sec 6C See Sec 6D 337 338 3 Modulation Figure 6 2 Instrument Troubleshooting Tree 6 3 TROUBLESHOOTING AND REPAIR 6 4 MODULE REPLACEMENT 6 2 Module replacement involves identifying and replacing the problem module The replacement module may be obtained through the Module Exchange Program or from your spare module stock which may then be restored using the Module Exchange Program Use the troubleshooting tree see Figure 6 2 to help diagnose the problem To help identify the problem module call your local Fluke Technical Center for troubleshooting assistance Once the Fluke service technician believes the problem module is identified a replacement module can be shipped prepaid by an overnight air carrier After verifying that the replacement module corrects the problem return the defective module in the shipping container and include the prepaid return shipping papers and label To order a replacement module use the part number for
88. DIAGRAM 6D 1 6D 3 RF LEVEL CIRCUIT 6D 3 6D 4 RE Paths ooo fod ge Ses ne eal 6D 3 6D 5 Leveling 6D 5 6D 6 E vel 60 6 60 7 RF LEVEL 6D 6 6D 8 Unleveled 6D 8 6D 9 Output Assembly Test Point Signal 6D 9 6D 10 RF LEVEL 6D 10 6D 11 Mod Control PCA Level DAC Offset Adjustment 23 6D 10 6D 12 Mod Control PCA AM DAC Offset Adjustment 8 6D 11 6D 13 Mod Control PCA Detector Offset Adjustment 28 6D 12 6D 14 Mod Control PCA AM Depth Adjustment 0 6D 13 6D 15 Mod Control RF Level Adjustment 20 6D 14 6D 16 Mod Control PCA External Modulation Level Indicator Adjustment 71 6D 15 6D 17 Mod Control PCA Sum Steer Gain Adjustment 6D 15 V continued on page vi TABLE OF CONTENTS continued SECTION TITLE PAGE 6D 18 Output PCA Het Mixer Level Adjustment 72 6D 16 6D 19 Output PCA Het Level Adjustment 60 17 6D 20 Premodulator PCA Bandwidth Adjustment R51 and C7 6D 17 6D 21 Outpu
89. If the Premodulator PCA output appears to be correct the problem is on the Modulation Control PCA the Output PCA between the input W1 and the detector diode CR20 or possibly on the Controller PCA With the instrument programmed for SPCL 01 frequency set to 88 MHz and level set to 13 dBm the voltage at TP7 leveling loop control voltage should be approximately 1 7V DC With the RF output programmed off the voltage at TP7 should be OV If these voltages are not correct look at the Modulation Control PCA circuitry associated with U21 06 08 U9 011 012 04 orcheck inputs from the controller Table 6D 2 Frequency Band Logic States FREQUENCY BAND CIRCUIT BOARD PIN DIODES TURNED ON 01 to 15 Output A8 CR18 CR24 15 to 22 Output A8 CR6 CR10 CR4 CR16 22 to 32 Output A8 CR7 CR11 CR4 CR16 32 to 47 Output A8 CR8 CR12 CR4 CR16 47 to 64 Output A8 CR9 CR13 CR4 CR16 64 to 128 Premodulator A10 CR28 CR22 CR31 128 to 180 Premodulator A10 CR26 CR27 CR71 CR22 CR31 180 to 256 Premodulator A10 CR24 CR25 CR71 CR22 CR31 256 to 350 Premodulator A10 CR9 CR10 CR14 CR15 CR16 350 to 512 Premodulator A10 CR9 CR10 CR17 CR18 CR19 512 to 730 Premodulator A10 11 CR12 CR13 CR17 CR18 CR19 730 to 1056 Premodulator A10 CR11 CR12 CR13 CR14 CR15 CR16 01 to 625 Output A8 CR15 625 to 1056 Output A8 CR14 TROUBLESHOOTING AND REPAIR With the instrument programmed
90. MACH PH P SS 4 40X 250 256156 COMMERCIAL 5 2 NUT MACH HEX STL 8 32 281113 COMMERCIAL 1 J SOCKET SINGLE PWB FOR 042 049 PIN 866764 00779 645991 3 3 gu CONN COAX SMB M PWB OR PANEL 512095 16733 702033 1 L 3 6 8 INDUCTOR 5 608 4 202 130MHZ 844881 52763 5087230 723 21 L 13 16 34 844881 L 35 38 40 844881 L 50 52 69 844881 L 79 84 93 944881 L 4 15 33 CHOKE 6TURN 320911 89536 32091 11 L 41 47 51 320911 L 56 68 72 320911 L 74 76 320911 L 17 20 DUCTOR 0 47UH 5 330MHZ 855002 91637 1 2 31 470955 2 L 18 19 DUCTOR 0 5609 5 300MHZ 855007 91637 IM2 31 56UH5 2 DUCTOR 0 3309 5 410MHZ 854992 91637 1 2 31 33095 2 L 22 23 DUCTOR 0 3909 5 365MHZ 854997 91637 IM2 31 39655 2 L 25 28 DUCTOR 0 2208 5 51097 854976 91637 IM2 31 22UH5 2 L 26 27 DUCTOR 0 27UH 4 55 430MHZ 854989 91637 2 31 270 5 2 L 29 32 DUCTOR 0 1509 5 600MHZ 854971 91637 1 2 31 150853 2 L 30 31 DUCTOR 0 18UH 5 550MHZ 854984 91637 2 31 180 55 2 L 36 31 58 DUCTOR 0 10UH 4 105 400MBZ SHLD 257154 24759 MR 10 3 L 42 59 DUCTOR 0 2709 10 400MHZ SHLD 313031 24759 MR 0 27 2 L 43 DUCTOR 0 33UH 4 108 300MHZ SHLD 261743 24759 33 L 44 62 DUCTOR 0 3200 758 290 HZ SHLD 329656 24759 MR 39 2 L 45 49 73 DUCTOR 10 TURNS 463448 89536 463448 3 L 46 DUCTOR 1500UH 10 2 5MHZ SHLD 343863 24759 MR1500 L 48 66 67 DUCTOR 6800UH 10 1 5MHZ SHLD 363184 24759 MR6800 3
91. OR GENERIC TYPE F55 4530 F T 1 F 55 1001 F T 1 8 F 55 3650 F 1 1 9 ih REPLACEMENT PARTS Dw CO 7 23 REPLACEMENT PARTS Table 7 3 A2 Coarse Loop PCA cont REFERENCE FLUKE MFRS MANUFACTURERS DESIGNATOR STOCK SPLY PART NUMBER A gt NUMERICS gt 5 DESCRIPTION N0 CODE OR GENERIC TYPE 519 536 RES 30 5 0 25W 866343 59124 CF1 4300JB R 522 RES CF 18 4 52 0 251 658773 59124 CF1 4 1880 5 R 525 526 RES CF 51 5 0 25W 572990 59124 CF1 4 510 J B R 537 RES MF 3 48K 4 12 0 125W 100 832071 91637 55 4802 1 1 R 601 603 604 RES MF 3 01K 1 0 25W 100 854356 71590 5063JD3011F R 602 RES MF 2 15 15 0 257 100 854364 71590 5063JD2151F R 605 RES 110 4 1 0 25W 100PPM 199809 91637 CCF 501100F R 606 614 615 RES MF 82 5 1 0 25 100PPM 799783 91637 CCF 5082R5F R 608 RES MF 2 74K 13 0 25W 100PPM 854427 71590 506322741 R 609 1 1 0 251 100 799791 91637 CCF 501001F R 611 633 RES CF 2 2K 5 0 251 573246 59124 1 4 222 JB R 616 RES MF 18 2 4 12 0 25W 100PPM 799817 91637 501882 R 617 RES VAR CERM 100 4 20 0 5 193052 72982 332 H 101 R 630 RES MF 3
92. Output PCA cont N REFERENCE FLUKE MFRS MANUFACTURERS 0 DESIGNATOR STOCK SPLY NUMBER TOT T A gt NUMERICS gt 5 DESCRIPTION NO CODE OR GENERIC TYPE QTY E C 204 CER 680PF 4 52 50V COG 743351 72982 RPE113 COG 681 J 50V 1 C 215 CAP CER 22PF 5 50V COG 0805 855101 51406 GRM708C0G220J200VPT 1 C 216 CER 1 OPF 4 0 50V C0G 0805 512129 95275 080501 00 1 CR 4 5 16 DIODE SI PIN RF ATTENUATING 508077 61804 MA 4P523 6 CR 18 24 508077 CR 6 13 DIODE 51 50 SWITCHING SOT23 854588 25088 885 8 CR 14 15 DIODE 51 PIN EPOXY STRIPLINE 713176 59365 1484 826 2 CR 19 20 DIODE SI SCHOTTKY MATCHED SET OF 2 722410 89536 722410 2 CR 21 23 DIODE SI PIN SELECTED CT amp RS 7402 CT 773192 59365 2636 3 CR 26 36 40 gt DIODE SI BV 75 0V 10 150 500MW 698720 65940 1N4448 6 CR 27 33 DIODE SI PI RF CUR CONTR EPXY STRPLN 773234 59365 MX2010 7 CR 35 DIODE SI SCHOTTKY BARRIER SMALL SIGNL 313247 28480 5082 6264 125 1 Eu d 94220 FILTER RF PIN SLEEVE STYLE 175PF 807289 00779 859653 1 3 FL 4 8 FILTER RF PIN SLEEVE STYLE 2000PF 807271 00779 859612 1 7 FL 13 23 25 807271 FL 14 19 FILTER RF PIN SLEEVE STYLE 1000 854856 00779 859613 1 6 1 3 6 SCREW
93. PCA 4 SUB SYNTHESIZER PCA 5 COARSE LOOP VCO 6 MOD OSCILLATOR PCA 8 OUTPUT 9 SUM LOOP VCO PCA 10 PREMODULATOR PCA 11 MODULATION CONTROL PCA 12 SUM LOOP 13 CONTROLLER 14 FM 15 POWER SUPPLY PCA 16 IEEE 488 CONNECTOR 19 SWITCH PCA 20 ATTENUATOR RPP ASSEMBLY H 1 SCREW MACH TH P SS 6 32 312 2 52 1 SCREW ACH FH P JST 1 8 3 2 375 22 41 SCREW ACH FHU P SS 6 32 250 42 57 SCREW MACH PH P STL 4 40X 187 58 59 SCREW MACH PH P MAG SS 6 32 281 65 STL 8 32 4437 310 311 401 SCREW MACH PH P 656 6 32 315 430 461 491 601 629 671 689 901 903 321 331 437 450 453 456 652 660 904 911 17 DO DX O3 O01Co Co HOw Co OS ow SS 0 eve ONE eor coms E SS SS SS 5 5 ome 9 gt co PO 7 4 An HOOO 11 DECAL CORNER HANDLE BOTTOM FOOT MOLDED CABLE TIE 4 0L 100 DECAL SIDE TR CO TIE CLAMP CABLE ASSY SR CABLE ASSY RE SEMI CABLE ASSY SYNTHESIZER CTRLR CABLE ASSEMBLY R CABLE ASSY DISPLAY CT CABLE ASSY RELAY DRIV CABLE ASSY FRONT PANE CABLE ASSY CTRLR POWER CABLE ASSY SYNTHESIZER POWER CABLE ASSY DISPLAY CTRLR 2 A23 RF INTERCO 10 19
94. T R 15 RES MF 46 4K 4 12 0 125W 50PPM 715185 91637 CMF554642BT 2 R 16 RES 1 62K 12 125W LOOPPM 851506 91637 CMF 55 1621 T R 18 RES 649 1 0 125W LOOPP 720458 59124 MF556490F R 19 104 RES 365 13 0 125W 100 459859 91637 CMF 55 3650 F T 2 R 20 RES VAR CERM 1K 10 0 5W 215150 32997 3386R 1 102 R 24 26 RES MF 20K 13 0 125 100 719823 91637 CMF 55 2012 F T 2 R 25 RES MF 66 5 15 0 12510 100 866322 91637 556652 2 RES MF 100K 13 0 125W 100 719484 91637 CMF1003F R 29 RES MF 49 9K 4 13 0 125W 100PPM 720334 91637 CMF 55 4992 T R 30 46 RES MF 34 8K 12 0 125W 100 866306 91637 CMF553482FT 2 31 RES 16 9K 13 0 125W 100 866293 91637 R 3 RES MF 2 55K 13 0 125W LOOPPM 719955 91637 CMF552551FT R 33 94 RES 499 1 0 1251 100 816462 91637 CMF554990FT 2 36 RES 1 91K 12 0 125W 100 866277 91637 551911 R 37 RES 37 4K 1 0 125W 100 720177 91637 CMF553742FT R 38 RES MF 619 1 0 125W LOOPPM 866244 91637 556190 R 39 RES MF 1K 13 0 125W 100 719468 91637 CMF 55 1001 F 1 1 R 40 RES CF 100K 53 0 25 573584 59124 CF1 4 104 J B R 41 RES 1 5 0 25W 572883 59124 CF1 4 5R6 5 R 42 52 RES MF 24 3K 4 12 0 125W 100 719922 59124 552432 2 R 43 51 RES 6 04K 4 12 0 1250 100PPM 84466 91
95. The AM depth adjustment directly affects the output level and should not be made indiscriminately The AM depth adjustment is normally required only when components in the AM signal processing circuits have been replaced If this adjustment is made it is then necessary to repeat 6D 13 Detector Offset Adjustment R28 and perform the RF Level Adjustment R20 PROCEDURE Adjust the AM depth adjustment R10 for 90 AM depth as measured with the Modulation Analyzer when the UUT is programmed to 90 AM 1 Remove the AM depth adjustment access screw from the bottom module plate cover 2 Connect the output of the LFSSG to the UUT MOD IN connector and to the DVM using a BNC Tee 3 Program the UUT to SPCL 01 350 MHz 4 dBm and EXT AM AT 90 AM DEPTH 4 Program the LFSSG for 1 KHz and a voltage of 0 7071 RMS as measured by the DVM 5 Connect the UUT RF OUTPUT connector to the modulation analyzer input 6 Program the modulation analyzer to measure AM Peak in a 0 05 to 15 kHz bandwidth 6D 13 TROUBLESHOOTING AND REPAIR RF LEVEL AM 6D 14 7 Alternately measure and PEAK and adjust the AM depth adjustment R10 until the readings are symmetrical about 90 8 Reinstall the AM depth adjustment access screw Mod Control PCA RF Level Adjustment R20 6D 15 TEST EQUIPMENT Power meter Power sensor High Level REMARKS The UUT must be operated at room temperature for at least one hour with the
96. The buffer gain match adjustment is normally required only when 0106 or any associated components are replaced or when the adjustment has shifted PROCEDURE The SUMAUDIO buffer amplifier is adjusted for equal gain in the inverting and non inverting modes 1 Program the UUT to SPCL 909 800 MHz 4 MHz deviation and 1 KHz mod frequency Turn INT FM on 2 Connect the DVM to measure the AC voltage between TP2 and TP15 ground 3 Note the DVM reading 4 Program the UUT to 700 MHz 5 Adjust R121 for a DVM reading equal to that noted in step 3 55 mV FM Null Adjustment R116 6 36 6 42 TEST EQUIPMENT e Oscilloscope REMARKS The FM null adjustment is required under the following conditions A12 Sum Loop has been replaced or the A14 FM PCA has been replaced or repaired TROUBLESHOOTING AND REPAIR FREQUENCY SYNTHESIS 0108 0109 or any associated components are replaced or the adjustment has been changed or has shifted PROCEDURE The AC error voltage at TP5 the phase detector output is adjusted for a minimum peak to peak value with the UUT programmed for INT FM on with 4 MHz FM deviation at 168 kHz mod frequency 1 Program the UUT to SPCL 909 700 MHz 4 deviation and 168 kHz mod frequency Turn INT FM on Set the oscilloscope for 50 mV division vertical 2 us division horizontal and AC coupling Connect the oscilloscope probe to monitor the signal at using TP
97. The programmed number ranges between zero and 99 corresponding to 10 kHz steps at the VCO frequency The flip flops in the rate multiplier get set up on count 29 and on count 30 a pulse may or may not be present depending on the programming ofthe rate multiplier This is the shaded pulse in the timing diagram Figure 6C 5 Irregularly spaced rate multiplier pulses cause the mode line to go low and the prescaler divides by 1 at a rate equal to the rate multiplier programming A 16 17 dual modulus prescaler will not allow division from 160 to 320 without holes For example 170 is ten frames of 17 Consequently there is no place to slip in the rate multiplier pulses It is not possible to divide by 171 By using a triple modulus prescaler these problems are solved Continuing with the previous example 170 is 10 frames of 17 and 0 frames of 18 The deleter allows the prescalerto divide by 18 atarate equal to the rate multiplierfrequency Number 171 is 9 frames of 17 and 1 frame of 18 A software algorithm determines whether to operate in the 16 17 mode TRMODL 1 or 17 18 mode TRMODL 0 The frequency at the output of the N divider gate array 1s Fo Fs Fd N Since this must be equal to reference frequency Fr and Fris 1 MHz the VCO frequency is Fo N Fs Fd where Fs is the SSB audio frequency from the low order digit generator and Fd is the fractional division frequency PHASE DETECTOR The 1 reference signal from div
98. UUT on program the UUT to SPCL 909 b Program the UUT to 640 MHz at 10 dBm c Select the fixed range special function on the UUT by pressing 5 d Using the EDIT function on the UUT edit the amplitude to 30 dBm Verify that the UNCAL annunciator illuminates NOTE This procedure leaves the output attenuators set as they would be for a 10 dBm output level but uses the electronic control to turn down the RF level coming out ofthe UUT e Connect the UUT to the Device Under Test port of the VSWR bridge f Connect the RF spectrum analyzer to the RF OUT port of the VSWR bridge 4 23 PERFORMANCE TESTS ga Connect the HFSSG to the RF IN port of the VSWR Bridge Program the HFSSG to 10 MHz at 13 dBm Set the RF spectrum analyzer to display approximately 10 to 1024 MHz and set the reference level to 10 dBm Step the HFSSG from 10 to 1024 MHz in 10 MHz steps Locate the frequency at which the reflected signal displayed by the RF spectrum analyzer is maximum and record this level This is the point with worst case VSWR Disconnect the UUT from the VSWR Bridge and record the new level Calculate the return loss difference between the two recorded levels The difference must be at least 14 dB 14 dB of return loss 1 5 1 VSWR 2 High Level Test a Program the UUT to 10 dBm b Select the special function fixed range on the UUT by pressing 51 c Using the EDIT function on the UUT edit the amplitude to 30 dBm
99. UUT output power in dBm with the power meter The output should agree with the programmed level within the requirement 6 Repeat step 5 for levels of 30 36 42 48 54 60 and 66 dBm 7 Repeat steps 5 and 6 for frequencies of 14 20 40 80 160 320 550 640 700 850 950 and 1024 MHz LOW LEVEL ACCURACY TEST 4 8 An RF spectrum analyzer and amplifier are used to verify the UUT level accuracy at 137 dBm and at frequencies of 10 14 20 40 80 160 320 550 640 700 850 950 and 1024 MHz REQUIREMENT Amplitude accuracy is lt 1 5 dB from 0 5 to 1024 MHz for level between 66 dBm and 117 dBm lt 3 0 dB from 0 5 to 1024 MHz for level between 117 dBm and 137 dBm TEST EQUIPMENT 0 1 to 1 1 GHz amplifier 50 dB attenuator 20 dB attenuator RF spectrum analyzer Power meter Power sensor low level REMARKS This test in conjunction with the mid level accuracy and high Level accuracy test verifies the overall level performance of the UUT If the UUT fails this test after passing the High Level Accuracy Test and the Mid Level Accuracy Test a problem in the A21 Attenuator PCA the A7 Relay Driver PCA or a leak around problem in the attenuator assembly is indicated Check for a broken feed through filter or improper mechanical assembly i e loose screws and or damaged or misplaced gaskets 4 9 PERFORMANCE TESTS 4 10 It is convenient to use the UUT RF ON OFF control when zeroing the p
100. XU15 26 25 C23 553 TP C26 U18 aj 43 Ue Uy 02 028 XU6 XU28 014 u14 u41 u43 Cis 31 1 8 Ui 13 C25 XUL BE 217 23 225 22 5 558 C24 C57 21 020 010 u8 u7 047 023 05 03 XU10 xua xu5 XU3 5 U21 212515 2 01218 C38 155 ono 101519 ce 6080 1601 Figure 7 13 A13 Controller PCA 7 56 Table 7 14 A14 FM See Figure 7 14 REFERENCE FLUKE DESIGNATOR STOCK A NUMERICS 5 DESCRIPTION NO 2 1 8 CAP AL 100UF 450 205 35V 416982 C 2 4 10 CER 5 6PF 0 25PF 63V 027 853403 C di 853403 C 5 22 CAP POLYES 0 1UF 20 50V 837526 21 28 30 837526 C 35 37 40 837526 C 42 61 65 837526 C 66 77 87 837526 C 90 92 97 837526 C 16 CAP CER 1000PF 2 50V C0G 807966 23 25 26 807966 C 28 31 71 807966 C 76 807966 9 1 250V AIR 733212 C 18 CAP CER 56PF 2 100V COG 512970 C 14 CAP CER 560 5 50V COG 528505 C 17 18 CAP 82UF 20 20V 351392 C 9 CAP CER 1 2PF 0 25PF 100V 543256 C 20 24 CAP CER 100 2 100V COG 837609 C 21 CAP CER 3 9PF 4 0 25 1007 007 812149 32 39 00 CAP 68UF 20 15V 193615 C 34 CAP LOUF
101. applied to the ends ofthe varactors TP4 VCO CONTROL is the control voltage to keep the oscillator center frequency at 80 MHz This voltage is about 15V DC for normal high mode and at about 7V DC for high deviation mode FM MODULATION is at OV DC and has the applied modulation The components in the control and modulation lines are for isolation and filtering Amplifier 72 is used to buffer the oscillator output to the sum loop Resistor 5 and associated resistors adjust and establish the proper level The circuit of U1 buffers the 80 MHz signal and U3 and its resistors establish ECL levels to the divide by four U4 The 20 MHz signal from U4 is translated from ECL level to TTL level by the 012 and Q13 circuit TROUBLESHOOTING AND REPAIR FREQUENCY AND PHASE MODULATION NWd NW43 Wd Wd W3 4 91901 4 20 2 W390 7 7 7 21901 HO12313Q0 WONN 53028105 4014 iN3uuUno 79113 N A8 3QIAIQ c3 5 i ezn nos 193130 345 015 C aod IdN owdo0 d 1081NOO W430 4 1 HOLIMS ova 1sv4 381333 4 91901 c 1 3193135 NQ A8 43171 800 ow dn N A8 3QIAIQ 90 60 O3HOLIMS AS 4001 C3 Old 104100 ZHWOZ LLY TOHLNOO GOW 4
102. controller it adjusts its internal settings and programs the new reference oscillator DAC setting When the signal generator receives two consecutive readings within 10 Hz ofthe target value 100 MHz it considers the displayed adjustment value correct and returns the end code The controller program must ensure that each counter reading is settled before sending itto the signal generator The program listing in Appendix G uses a simple but effective method to obtain valid counter readings The programming commands used in aremote level calibration procedure are listed in the Table 3 8 See Table 5B 3 in Section 5B of the Operator Manual for a complete syntax description of each command Table 3 8 Remote Programming Commands for Reference Oscillator Calibration Procedure COMMANDS DESCRIPTION CAL REFOSC Initiate the remote reference oscillator calibration procedure CC RDFREQ Send the counter meter to the 6080A AN CC FREQ Request the RF frequency CC TARGET Request the target value RFOUT Program the RF output on off CC SAVE Save the measured data CC EXIT Abort the cal procedure immediately ERROR Request the rejected entry status STATUS STATUS Load Request the overrange uncal status 3 17 3 18 Section 4 Performance Tests INTRODUCTION 4 1 The information in the Section 4 describes the performance tests for the key parameters of the 6080A AN Synthesized Signal Generator also referred to throughout as the signal
103. decoded I O write location labeled W or RW in Figure 6B 2 Momentarily grounding TP2 performs the same action but writes the data byte 01010101 binary instead These diagnostic tests write the data bytes very fast so that an oscilloscope can be easily triggered Inspect the various I O select signals and their relationship to the data and address signals Normal software activity is halted so the instrument power must be cycled to terminate the test The display should show an odd combination of digits and segments since it is displaying an alternating bit pattern rather than the normal display data Although the module I O selects are generated by the tests it may be easier to test the module I O circuitry using the latch test once the microprocessor circuitry is fully functional If the data read selects to the 488 talker listener IC U28 or the status input buffers are not generated properly momentarily ground TP3 This initiates a diagnostic routine that continuously reads data from each decoded read position labeled R or RW in Figure 6B 2 Cycle the instrument power to terminate this diagnostic function BSELOL W BSEL1L W BSEL2L W BSEL3L W BSELAL W DISPLAY W BSEL5L W IEEE CHIP RW MODULE KEY IN R STAT 1 STAT 2 STAT STAT 4 MODULE 5 W CONTROL CONTROL2 w OUTPUTS READ SELECTS WRITE SELECTS W READ WRITE SELEC
104. details of the difficulty Include the model number type number and serial number On receipt of this information service data or shipping instructions will be forwarded to you 2 receipt of the shipping instructions forward the instrument transportation prepaid Repairs will be made at the Service Center and the instrument will be returned prepaid SHIPPING TO MANUFACTURER FOR REPAIR OR ADJUSTMENT All shipment of JOHN FLUKE MFG CO INC instruments should be shipped in the original packing carton if available If the original carton is not available use any suitable container that is rigid and of adequate size If a substitute container is used the instrument should be wrapped in paper and surrounded with at least four inches of shock absorbing material Table of Contents SECTION TITLE PAGE 1 INTRODUCTION AND 5 1 1 1 1 INTRODUCTION o c7 265 0 1 1 1 2 UNPACKING THE SIGNAL 1 1 1 3 SAFETY oce Ie et REGED eee dn eh ur A oe 1 2 1 4 ACCESSORIES 22242 LI ote E kee S 1 3 1 5 SIGNAL GENERATOR 5 5 1 3 2 THEORY OF 2 1 2 1 INTRODUCTION os Os 2 1 2 2 GENERAL DESCRIPTION
105. does not include effects of residual Phase noise BANDWIDTH 3 INCIDENTAL HIGH RATE PHASE MODULATION Access by SPCL 721 0 to 999 rad 1 to 9 99 rad 10 to 99 9 rad 100 to 400 rad DEV RF FREQUENCY 50 rad 01 to 15 MHz 12 5 rad 15 to 32 MHz 25 rad 32 to 64 MHz 50 rad 64 to 128 MHz 100 rad 128 to 256 MHz 200 rad 256 to 512 MHz 400 rad 512 to 1056 MHz 3 digits 5 0 1 rad at 1 kHz rate 296 THD for 1 kHz rate 196 THD for 1 2 or less max deviation for 1 kHz rate ACPM 20 Hz to 15 kHz DCPM DC to 15 kHz 196 AM at 1 kHz rate for peak dev 10 rad Valid for F gt 1 MHz MAX DEV RF FREQUENCY 5 rad 01 to 15 MHz 1 25 rad 15 to 32 MHz 2 5 rad 32 to 64 MHz 5 rad 64 to 128 MHz 10 rad 128 to 256 MHz 20 rad 256 to 512 MHz 40 rad 512 to 1056 MHz INTRODUCTION AND SPECIFICATIONS Table 1 4 Typical Signal Generator Performance cont HIGH RATE PHASE MODULATION ACPM 20 Hz to 100 kHz BANDWIDTH 3 dB DCPM DC to 100 kHz Access by SPCL 721 NOTE Phase Modulation specs are valid where RF Frequency Modulation Frequency 150 kHz PULSE MODULATION RF FREQUENCIES FROM 10 TO 1056 MHz ON OFF 40 dB minimum for frequencies from 100to 1056 MHz 60 dB minimum for frequencies less than 100 MHz RISE amp FALL 5
106. eon n an 964015 3ounos INSHYND sna viva p i E A 31v5 HO1V1 WOHJ ven wy ZHW 02 711 193 i 2 dv doo1 240 ZHW 26 91 NAS NS lt d 6 E dOOTWNS OL oe 6 ZELEOEN ten 18 25906 1 9 u120 2 ZH 01 ten H3ZIS3HINAS 8nS HOLON doo 3Suvoo WOu3 ZHN Figure 6C 2 Sub Synthesizer Block Diagram 6 3 TROUBLESHOOTING AND REPAIR FREQUENCY SYNTHESIS 6C 4 SINGLE SIDEBAND MIXER The 160 to 320 MHz from the VCO via J7 is filtered C140 2 L70 1 attenuated R69 71 amplified U50 attenuated again R101 3 R106 and amplified U51 and connected to a quadrature 90 degree phase difference 3 dB coupler U52 This signal and two other audio quadrature signals from U59 are summed in the double balanced mixers U53 and U54 to produce two double sideband suppressed carrier signals Because of the phase relationship of the outputs of the mixers the summing ofthe two composite signals in resistor network R75 and R76 results in the upper sideband component being suppressed The predominate remaining signal is the lower sideband signal The lower sideband signal spanning 160 to 320 MHz in 10 kHz steps is amplified by U55 and applied to the N divider where it is divided down to 1 MHz N DIVIDER The main components of the N Divider are t
107. flop U19 will make an overlap pulse clocked by signal Vck1 and reset by signal Vck2 to drive the DAC least significant bits The switch U18 causes the up down counter to use the second V clock Vck2 instead of Vck1 for clocking causing a missing portion The overlap pulse which occurs at the time between the and Vck2 clock signals just fills in for the missing portion The smoothing adjustment R88 is used to make up for inaccuracies oftiming and lower order DAC bit substitution The up down counter is prevented from wrapping around from either high to low or low to high by end count detectors 048 p o 010 and p o U16 inverters and four input NAND gates that control the appropriate clock inputs This control information is also used to determine overmodulation or an unlocked loop condition This information is passed to the uncal detector The uncal detector U20 receives these inputs and the inputs from the other phase detector When the phase detectors are close enough to the edge of normal operation this will trigger the uncal one shot U20 which will stretch out the time of abnormal indication The output FM UNLCK is sent to the instrument controller Following the phase detectors is the loop amplifier U25 which in combination with the analog switch selects the appropriate phase detector and gain resistors R66 and R87 to control the phase locked bandwidth The circuit is followed by the loop filter which has
108. frequency synthesized signal generator LFSSG High frequency synthesized signal generator HFSSG DVM RMS Voltmeter 4 17 PERFORMANCE TESTS NOTE The following procedures must be performed in the order described below to ensure that the proper equipment is connected and appropriate programs are enabled PROCEDURE 1 Internal Modulation Oscillator Frequency Test a b Connect the UUT MODULATION OUTPUT to the frequency counter input Program the UUT to SPCL 909 Program the UUT for 90 INT AM at a 1 kHz rate and a level of 0 dBm Verify that the counter reads 1 kHz 0 1 Hz Program the UUT to the following modulation frequencies and verify the programmed frequency 0 1 Hz 10 100 Hz 10 kHz and 100 kHz Internal Modulation Oscillator Level and Distortion Test Connect the UUT MODULATION OUTPUT to an RMS voltmeter Terminate the RMS voltmeter with a 600 ohm resistor Program the UUT to 1 volt peak modulation output and 1 kHz rate Verify the level as 707 volts 1 on RMS voltmeter Repeat step d at programmed levels of 2 5 and 1 5 volts peak Multiply the RMS value by 1 414 to get the peak value Program the UUT Mod Oscillator Level to 1V RMS and the Mod Oscillator Frequency to 10 kHz Connect the UUT Modulation Output to the input of the distortion analyzer The total harmonic distortion THD should be less than 2 3 AM Accuracy and Distortion Test a Measure the mean AM depth
109. generator Instrument specifications are used as the performance standard These closed case performance tests may be used as e acceptance test upon receipt of the instrument An indication that repair and or calibration is required A performance verification after completing repairs or calibration of the instrument Individual performance tests can also be used as troubleshooting aids The signal generator being tested referred to as UUT the unit under test must be warmed up with all covers in place for at least 2 hours before starting the performance tests Fluke recommends that calibration be performed once a year TEST EQUIPMENT 4 2 Table 4 1 lists the recommended test equipment for the performance tests adjustment procedures and troubleshooting the signal generator Figure 4 1 shows a two turn loop PERFORMANCE TESTS Table 4 1 Recommended Test Equipment Low Residual MANUFACTURER 1 INSTRUMENT NAME MINIMUM REQUIREMENT DESIGNATION NOTES DVM 5 1 2 Digit 0 396 DC 20 kHz JF 8840A 09 A P DMM 3 1 2 Digit 1 DC and 1 kHz JF 8020B RMS Voltmeter 10 Hz to 20 MHz low noise JF 8922A Wideband Amplifier gt 25 dB gain 0 4 to 1050 MHz HP 8447D 010 P NF 9dB RF Spectrum Analyzer 0 1 to 1 7 GHz 100 Hz BW HP 8568A Oscilloscope Four trace 300 MHz 5 mV Div TEK 2465 11 TP FET Probe DC 900 MHz TEK 6201 T 500 ohm Probe DC 3 5 GHz 10X TEK P6156 T RF Voltmeter 0 01 to 700 MHz
110. in the following procedure 1 Center all pots on the Turn UUT off Set the 6011 to 50 kHz at 0 dbm Connect the 6011A to TP12 Connect the spectrum analyzer to TP11 Adjust L6 for a minimum 50 kHz level Remove the 6011 and the analyzer Set the UUT to SPCL 909 800 MHz 62 5 kHz dev 1 kHz mod rate INT ACFM Set the 8840A to AC volts autorange Connect the 8840A to TP1 on the FM PCA Adjust R107 for 2 828 RMS 2 mV RMS Turn INT off Remove the cap from J3 to J17 connecting the FM PCA to the Sum Loop PCA A12 Connect the counter to J3 Adjust L1 to be flush to the top of its housing Adjust C9 for a locked 80 MHz as read on the counter Remove the counter from 73 and connect 436A to 73 Adjust R45 for 5 dBm 1 dB Disconnect 436A from J3 Install the 1000 pF cap from J3 to J17 on the Sum Loop PCA Connect the 8840A to Set 88404 to DC volts Adjust R44 for DC 10 mV DC 10 11 12 13 14 15 TROUBLESHOOTING AND REPAIR FREQUENCY AND PHASE MODULATION Cover the FM oscillator Q1 Q2 section only with a metal cover Set the 8901A to Auto FM peak 300 Hz HP 15 kHz LP Connect the 8901A to J3 Set the UUT to SPCL 909 800 MHz INT ACFM 1 kHz mod rate 400 kHz FM Dev Set 8840A to DC volts autorange Connect the 8840A to TP11 Adjust L1 for 400 kHz FM Dev 2 kHz The 88404 should read 7V DC 100 mV dc Set the UUT to 40 kHz FM Dev Adjust C9 for 40 kHz
111. is displayed and the bit pattern 10101010 Hexadecimal AA is written continuously to each of the decoded module I O latch positions The data is written to each address in sequence so that the activity on the address bus is regular Pressing 7 key changes the displayed message to LAtch 55 and the bit pattern is changed to 01010101 Hexadecimal 55 Pressing the STEP A key changes the pattern back to 10101010 Press any other key to exit Instrument Diagnostic State 6 38 Special Function 909 programs the instrument to a predefined state used by several of the troubleshooting and alignment procedures First the instrument preset state special function 01 is programmed to disable most special functions Then the diagnostic state is programmed immediately The significant parameter settings of the diagnostic state are listed in Table 6 15 Table 6 15 Parameter Settings of Diagnostic States PARAMETER SETTINGS Frequency 300 MHz Amplitude 10 0 dBm AM Depth 30 0 FM Deviation 5 00 kHz Mod Frequency 1 00 kHz All Modulation Off Set Internal DACs 6 39 All internal DACs can be simultaneously forced to a predetermined setting for troubleshooting and alignment by special function The settings are described below CODE FUNCTION 941 Set all DACs to zero 942 Set all DACs to mid scale 943 Set all DACs to full scale NOTE The synthesizer DA C U7 on the A6 Modulation Oscillator PCA cannot be s
112. module plate covers in place before continuing with this adjustment procedure This adjustment is required if any of the following events occur The Output PCA the Modulation Control PCA or the Attenuator RPP Assembly has been replaced The AM depth adjustment is made The level DAC or any associated components are replaced The RF level adjustment has been inadvertently changed CAUTION The RF level adjustment directly affects the output level and should not be made indiscriminately PROCEDURE With the UUT programmed to 9 dBm adjust the RF level adjustment R20 for 9 dBm output as measured with the Power Meter 1 Program the UUT to SPCL 01 350 MHz and 9 dBm 2 Zero the power meter 3 Remove the RF level adjustment access screw from the bottom module plate cover 4 Connect the power sensor to the UUT RF connector 5 Adjust RF level adjustment R20 for a reading of exactly 9 dBm on the Power Meter 6 Reinstall the RF level adjustment access screw TROUBLESHOOTING AND REPAIR RF LEVEL AM Mod Control PCA External Modulation Level Indicator Adjustment R71 6D 16 TEST EQUIPMENT DVM REMARKS This adjustment is normally made if CR12 or R70 R74 are replaced PROCEDURE The potentiometer is adjusted to provide 0 98V DC at TP1 This adjusts both AM and FM indicators as the remaining levels are set by fixed resistors 1 Remove the bottom instrument cover and remove the access screws f
113. mor Flashing RF OFF annunciator indicates a tripped condition Pushing RF ON OFF button will reset signal generator INTRODUCTION AND SPECIFICATIONS Table 1 3 6080A AN Specifications cont IEEE 488 INTERFACE SH1 AH1 T5 TEO L3 LEO SR1 RL1 PRO DC1 DT1 and 22 Complies with IEEE Std 488 1 1987 and 488 2 1987 INTERNAL MODULATION SOURCE SINE 10 Hz to 100 kHz synthesized sine wave DISPLAY 5 00 1 to 99 9 Hz 100 to 999 Hz 1 00 to 9 99 kHz 10 0 to 99 9 kHz 100 to 200 kHz FREQUENCY 0 1 Hz or 3 digits OUTPUT LEVEL 0 to 1V RMS into 600 ohms 2 2 2 THD OUTPUT 600 ohms 10 EXTERNAL MODULATION 1V peak provides indicated modulation index Nominal input impedance is 600 ohms Maximum input level is 5 V peak MODULATION MODES Any combination of AM PULSE and FM internal or external may be used GENERAL TEMPERATURE Operating rtt e to 50 32 to 122 40 to 75 40 to 167 HUMIDITY RANGE etr a 95 to 30 75 to 40 and 45 to 50 ALTITUDE
114. on and let it operate for 15 minutes Program the UUT with SPCL 01 4 Adjust R96 until the DVM reads 1 355V DC 5 Reinstall the pulse cover the module cover and the instrument bottom cover TROUBLESHOOTING AND REPAIR RF LEVEL AM Output PCA Q9 Bias Adjustment R1 6D 22 The following procedure covers the bias adjustment of Q9 on the Output PCA TEST EQUIPMENT Spectrum analyzer REMARKS This adjustment is normally made only when Q9 or associated circuitry is replaced PROCEDURE RI adjusts the collector current of Q9 to minimize harmonic distortion 1 Remove the bottom instrument cover bottom module plate cover and the pulse cover 2 Connect UUT RF Output to the spectrum analyzer Set the spectrum analyzer sweep to coverthe frequency range of 1 to 1300 MHz and set the analyzer reference level to 13 dBm 3 Set UUT to SPCL 01 and amplitude to 13 dBm 4 Edit the frequency to display signal and harmonics on the spectrum analyzer Adjust R1 to minimize the worst harmonic seen This is typically the second harmonic with the UUT frequency at about 300 MHz The harmonic must be less than 30 dBc for proper operation 5 Reinstall the pulse cover the module plate cover and the instrument cover Output PCA Gain Flatness Adjustment C201 6D 23 This procedure describes the adjustment of C201 for the purpose of optimizing gain flatness This adjustment should not be required unless CR20 detector diode or parts in th
115. oscillators are obvious from the schematic TROUBLESHOOTING AND REPAIR FREQUENCY SYNTHESIS Each oscillator uses a common base transistor Q4 configured for negative resistance at the emitter The emitter is coupled to a resonator that consists of a printed transmission line in series with varactor diodes CR7 CR8 and low loss porcelain capacitors C7 C8 Two tuning voltage lines connect to the varactor cathodes and anodes via RF chokes L8 and respectively The cathode lines connect to the VCO steering port J5 The anode lines connect to the VCO phase lock port J6 These ports are used by the 12 Sum Loop to control the operating frequency The voltage across the varactors measured between J6 and J5 varies approximately linearly with frequency in each band from about 42V to 20V The 13 dBm nominal signal at the oscillator transistor collector is applied to an 8 dB attenuator that provides isolation R18 R20 and then to a low pass filter that attenuates harmonics to less than 20 dBc C51 C52 and printed lines PIN diode CR12 has low RF resistance and passes the oscillator signal when the oscillator is on and goes to a high impedance when the oscillator is off Band control signals SUMVCOOH and 50 are decoded by 05 and Q5 Q10 This circuit applies bias current only to the selected oscillator transistor Thus only one oscillator is activated per band PIN diodes CR9 CR12 connect the active oscillator to a
116. paragraph 6D 14 A12 Sum Loop PCA 6 14 Adjustments R116 See paragraph 6C 36 A13 Controller PCA 6 15 Adjustments None To preserve the instrument calibration compensation data transfer the battery backed RAM IC U8 and the EEPROM U9 from the old Controller PCA to the replacement controller If either U8 or U9 are bad review CALIBRATION COMPENSATION MEMORY Section 6B then replace the faulty IC A14 FM Board PCA 6 16 Adjustments R107 FM deviation high rate See paragraph 6E 18 item 12 R39 HIDEV volts steering See paragraph 6E 20 item 8 R35 LOWDEV volt steering See paragraph 6E 20 item 9 R116 on Sum Loop PCA See paragraph 6C 36 A15 Power Supply PCA 6 17 Adjustments None A19 Switch PCA 6 18 Adjustments None A20 Attenuator RPP Assembly A7 A21 A30 6 19 Adjustments R20 RF Level See paragraph 6D 16 Mod Control PCA A compensation data EPROM containing Attenuator RPP level correction data is included See paragraph 6 21 for data transfer instruction A22 Delay Line Assembly A25 A26 Delay Cable Trim Cable 6 20 Adjustments None TROUBLESHOOTING AND REPAIR UPDATING COMPENSATION MEMORY WITH MODULE EXCHANGE DATA 6 21 After installing the A20 Attenuator RPP 8 Output or Sub Synthesizer VCO module exchange assemblies the operator must load the data in the corresponding compensation EPROM into the compensation memory The module exchange EPROM is installed in a socket on
117. provide reasonable confidence of the amplitude accuracy ofthe UUT However additional test frequencies may be included in this test This test verifies the high level accuracy of the signal generator and verifies that the amplitude correction factors for the individual attenuator sections are correct This test in conjunction with the mid level accuracy and low level accuracy tests verifies the overall level performance of the UUT NOTE To test attenuator sections 4 through 7 program the 6080A AN Signal Generator to 12 dBm and key in 57 02 08 through E 8 67 respectively 1 Calibrate and zero the power meter PERFORMANCE TESTS 2 Program the UUT to SPCL 909 3 Connect the power sensor to the UUT RF OUTPUT 4 Program the UUT frequency to 0 5 MHz 5 Select each attenuator section by programming the UUT amplitude to the levels shown in Table 4 2 using SPCL 923 through SPCL 926 and record the measured power at each level 6 Compute the output power error for each programmed level of Table 4 2 by subtracting the programmed power in dBm from the measured power in dBm These errors must not exceed the requirement stated above Table 4 2 High Level Accuracy Test Conditions OUTPUT POWER ATTENUATION PROGRAMMED MEASURED SECTION LEVEL POWER ERROR ERROR LIMIT SECTION NOMINAL dBm dBm dB dB dB 0 0 12 MO 12 12 See 6 M1 1 6 MO M1 6 test
118. provides 0 to 138 dB of attenu ation in 6 dB steps and provides protection for the output circuits RF Path 6D 4 The RF path begins with the 480 to 1056 MHz signal at J5 on the Premodulator PCA This signal comes from the Sum Loop VCO PCA A double pole double throw switch CR1 CR2 CR3 CR4 sends this signal directly to amplifier U4 or through the divide by two circuit U2 and then to U4 The switch is controlled by the logic signal MIDH Both paths use frequency shaping networks to flatten the frequency response The input frequency to U4 is then 240 to 1056 Mhz The signal is further amplified by US The output of US is first low pass filtered at 1100 MHz and then filtered again by the switched filter that is controlled by logic signals HAOCTH and MIDH This filter removes harmonics with low pass filters switched at 350 MHz 512 MHz and 730 MHz The particular filter in place depends on the logic state of HAOCTH and MIDH which control CR9 19 The 240 to 1056 MHz signal goes to the double pole double throw switch CR22 CR23 CR31 CR32 which is controlled by the logic signal GT256H This switch directs the signal directly to the amplifier Q6 or to the divider chain beginning with 011 The 011 output is split One output provides 128 to 256 MHz to a switched filter for reducing harmonics and the other output provides an input signal to the third divider U58 The 128 to 256 MHz output passes through a low pass filter selected by log
119. rejection notches at 50 kHz 90 kHz and 200 kHz This filter rejection reduces the pulses from the phase detectors to maintain minimum spurious modulation of the FM oscillator Also associated with the loop amplifier and loop filter are a comparator U27 and a relay K4 which are used in DCFM mode of operation of the FM PCA The operation to enable DCFM is under control of the instrument controller The controller operation is as follows 1 Setup normal except disconnect input modulation signals 2 Monitor comparator output DCFMLO 3 Adjust FM STEER DAC on Modulation Control PCA using an appropriate algorithm until the comparator senses nearly zero voltage at TP12 Repeat as necessary 4 When satisfied assert the DCFMH control that closes the relay K4 puts TP12 at OV DC ground and disables dividers and phase lock and disconnects phase modulation path The input modulation signals are reconnected through a DC path ICs U29 U30 and U33 generate the control signals for the rest of the circuits for the different ranges of modulation and the different modes of operation in FM 9 and DCFM The inputs are the control lines from the instrument controller and the outputs control the divider phase detector oscillator and modulation circuits See the Modulation Control Table Table 6E 1 for the relationship TROUBLESHOOTING AND REPAIR FREQUENCY AND PHASE MODULATION Modulation Section 6E 7 The modulation
120. resistive signal splitter R22 R23 R50 One signal splitter output goes to series connected monolithic 11 dB amplifiers 01 and 02 A 12 dB pad R26 R28 is between 01 and U2 Two amplifiers are required for adequate isolation between the Sum Loop and the Premodulator assemblies The output of U2 at about 7 dBm is connected to the A10 Premodulator PCA by a plug in capacitor at J7 The other signal splitter output goes to an identically configured circuit including amplifiers U3 and U4 Following U4 is a low pass filter including C69 and C70 that attenuates high frequency harmonics The filtered output from U4 is connected to the A12 Sum Loop PCA at P1 by a through the plate composition resistor This component behaves as a distributed RC lowpass filter at very high frequencies and improves sum loop spurious performance SUM LOOP VCO TROUBLESHOOTING 6C 40 The Sum Loop VCO PCA along with the Sum Loop generates the fundamental frequency band A problem with the Sum Loop VCO can cause Sum Loop Unlock status code 244 or Sum Loop Unlevel status code 245 to appear Self Test error codes 327 through 333 can also be triggered by a faulty Sum Loop VCO To determine that the Sum Loop VCO is faulty rather than another assembly the following tests can be performed Ground the phase lock port of the VCO with a clip lead J6 Sum Loop VCO or Sum Loop 2 Measure the DC voltage at J5 with the signal generator programmed to SPCL
121. resolution 2 Program the UUT to SPCL 909 3 Program the UUT to 800 MHz Frequency counter should read 16 000 MHz 4 Short TP22 to ground 5 Adjust R99 so that the frequency counter reads 15 000 MHz 10 kHz Upper Clamp Adjustment R98 6 8 TEST EQUIPMENT Frequency counter REMARKS The Upper Clamp Adjustment R98 is normally required only when U35 U36 or associated components have been replaced when the Sub Synthesizer VCO A3 has been repaired or replaced or when the adjustment has shifted PROCEDURE The Upper Clamp frequency is adjusted to 32 5 MHz with the N divider signal to the phase detector disabled 1 Connect output J4 ofthe Sub Synthesizer VCO A3 to the frequency counter Set the frequency counter to measure with 1 kHz resolution 2 Program the UUT to SPCL 909 3 Program the UUT to 640 MHz Frequency counter should read 32 000 MHz 4 Short TP21 to ground 5 Adjust R98 so that the frequency counter reads 32 500 MHz 10 kHz SSB Mixer LO Drive Adjustment R106 6 9 TEST EQUIPMENT Probe 10X Spectrum analyzer REMARKS The SSB Mixer LO Drive Adjustment R106 is normally required only when U50 U51 or associated components have been replaced when the Sub Synthesizer VCO A3 has been repaired or replaced or when the adjustment has shifted TROUBLESHOOTING AND REPAIR FREQUENCY SYNTHESIS PROCEDURE The SSB Mixer LO Power as measured with a 10X RF probe using a sp
122. resume the procedure Abort the Cal Procedure Press once the prompt Clr is displayed Press again to abort the procedure The message Clr is displayed to confirm the selection All measured data is discarded and the previous instrument state is restored Press any other key to resume the procedure 3 5 CLOSED CASE CALIBRATION 3 6 Remote AM Calibration Procedure 3 7 This following paragraphs describe the remote AM calibration procedure the remote commands used in the procedure and the elements required to build a functioning controller program Refer to the heading Remote Calibration earlier in Section 3 for general information relating to all remote calibration procedures A complete program listing that runs on a Fluke 1722A controller is provided in Appendix G The basic structure of the AM calibration program is shown in the program in Figure 3 2 initiate the AM calibration procedure with CAL AM initialize modulation meter MAIN LOOP request the RF frequency with CC FREQ if frequency 9e9 goto DONE read modulation meter send reading to 6080A AN with CC RDAM goto MAIN LOOP DONE store new data in calibration memory with CC SAVE end Figure 3 2 Structure of the AM Calibration Program The procedure is initiated by the command CAL AM The controller requests the signal generator s center frequency with the command CC FREQ and waits for a response Whe
123. section consists of a high rate modulation path and a low rate modulation path The modulation signal comes from the Modulation Control PCA at J6 The signal frequency at this point can range from DC to 200 kHz Full scale amplitude for each range is 4 AC peak for full deviation at the modulation frequency The type of modulation is determined following this point The logic control signals for range switching and type of modulation are generated in the two PAL ICs U29 and U33 and selector U30 This was pointed out previously under the heading Phase Detector Loop Circuits and Logic Section See Tables 6E 1 and 6E 2 The high rate path consists of U37 U39 U40 U41 U42 U43 U45 U46 U47 K2 and Z6 U37 U45 and U46 are level translators from TTL CMOS level to the drive level for the analog FET or DMOS switches which require levels for off of nominal 12V DC and for on of 12 DC The Mode switch for DCFM as well as Low rate FM PHMOD normal and High rate PHMOD is U39 This switch functions as a one of four selector on the input of an amplifier U40 The adjustments R104 and C75 are used to balance the different modes of operation The feedback resistors R107 and R108 around this amplifier determine the gain of this path The amplifier output drives the range resistor network Z6 and range switches The range switches are relay switch K2 and analog switches U47 and part of U43 These are controlled by level translato
124. steering DAC value and expect the loop to remain locked The fourth test programs a valid frequency but the steering DAC is set to zero This should force the loop to unlock Table 6 8 Coarse Loop Tests COARSE LOOP EXPECTED STATE CODE FREQUENCY COARSE STEER DAC OF COARSE LOOP 320 640 MHz Normal Locked 321 768 MHz Normal Locked 322 896 MHz Normal Locked 323 640 MHz 0 Unlocked Sub Synthesizer Tests 6 30 The first Sub Synthesizer Test see Table 6 9 programs a valid frequency near the center ofthe Sub Synthesizer range and expects the Sub Synthesizer to remain locked The next two tests force the Sub Synthesizer to frequencies outside of its normal operating range and expect it to go unlocked Table 6 9 Sub Synthesizer Tests SUB SYNTHESIZER EXPECTED STATE CODE RF FREQUENCY FREQUENCY OF SUB SYNTHESIZER 324 804 000000 MHz 240 MHz Locked 325 800 000000 MHz 120 MHz Unlocked 326 807 999999 MHz 350 MHz Unlocked Sum Loop Tests 6 31 The first four sum loop tests see Table 6 10 program a frequency in each of the four Sum Loop VCO bands with the normal steering DAC value and expect that the loop will remain locked The fifth test programs a valid frequency but the steering DAC is set to zero This should force the loop to unlock The next two tests program 4 MHz of FM deviation at a low and a high modulation rate and expect the sum loop to remain locked Table 6 10 Sum Loop Tests
125. supply circuitry 6A 3 TROUBLESHOOTING AND REPAIR POWER SUPPLY 6A 4 The 5V local supply U5 provides negative voltage to U1 and a 1 3V for U7 and U9 shut off voltage U3 Triac Q3 is a voltage surge protector to protect against line voltage surges as well as overvoltage in case of a wrong setting of the line power selector card When the voltage across the 5 1V secondary winding of the transformer is excessive CR2 or CR3 conduct current which fires the gate of Q3 This sets Q3 in the conductive mode shorting the secondary winding and causing the power line fuse to blow POWER SUPPLY TROUBLESHOOTING 6A 3 WARNING TROUBLESHOOTING THE POWER SUPPLY SHOULD BE DONE WITH GREAT CAUTION SINCE IT IS POWERED UP WHILE THE LINE POWER IS CONNECTED TO THE INSTRUMENT THE FRONT PANEL POWER SWITCH DOES NOT BREAK EITHER THE AC LINE POWER OR THE TRANS FORMER SECONDARY THEREFORE THE POWER SUPPLY IS ENERGIZED WHENEVER IT IS CONNECTED TO THE MAINS To troubleshoot the power supply remove the rear panel from the instrument and remove the Power Supply from its bracket Since the power supply is a floating type to reduce ground loops both the GND lines and the GND SENSE lines must be connected via the controller connector J4 It is a good practice to connect load resistors to each of the supply lines The load values should correspond to the load current indicated on the power supply schematic When operating the power supply make
126. that the CAL and COMP annunciators are no longer flashing 11 Turn the power off and remove the module exchange EPROM if desired 12 Reassemble the instrument by reversing the disassembly steps 6 7 TROUBLESHOOTING AND REPAIR 6 8 PARTS REPLACEMENT 6 22 An experienced technician should be able to isolate the defective component and replace it after reading FUNCTIONAL DESCRIPTION in Section 2 and the troubleshooting information contained in this section Schematics are in Section 8 Most parts are replaced using ordinary methods However chip components requiring special attention To replace the chip components use a 600 F soldering iron such as an Ungar 50T7 with a number 76 heater a number 88 tip and 246 silver solder paste such as Electro Science Fabrication SP 37D1 or similar wire solder Replacement of some components may require that alignment compensation and or calibration procedures be performed See the sections of this manual appropriate to the circuit functions being restored Use the performance tests in Section 4 to verify the results of the repairs SELF TEST DESCRIPTION 6 23 The instrument self tests are performed on power up or when initiated by Special Function 02 If any test fails the message FAIL is displayed along with the corresponding status code A complete list of the test failures is displayed upon completion Use the key to scroll the list if there are more than four failures Du
127. the UUT to INT FM Set analyzer to span 0 Hz trigger video Verify that the droop of the demodulated FM is less than 1096 Set the UUT to EXT DCFM Verify that the droop of the demodulated DCFM is less than 2 TROUBLESHOOTING AND REPAIR FREQUENCY AND PHASE MODULATION 25 Set the UUT to 800 MHz 300 kHz dev 1 kHz mod rate EXT on Connect the 8840A to TP12 and check that the 8840A reads OV DC 200 mVdc Set the UUT to 200 kHz dev Check that the 8840A reads OV DC 200 mV DC 26 Set the UUT to 800 MHz 10 kHz dev 1 kHz mod rate EXT ACFM Place a 600 ohm load on the UUT EXT FM input Connect 1953A Counter to UUT output and set the 1953A to read 800 MHz with Hz resolution Set the UUT to EXT The front panel indicator should come on within one second The 1953A should read within 350 Hz of the 800 MHz ACFM frequency Connect the 88404 to TP12 TP12 should read DC Connect the 8840A to J1 P3 The 88404 should read between DC and 8V DC Set the UUT to ACFM Repeat step 25 to verify performance Set the UUT to ACFM 27 Set the UUT to 300 kHz dev Set the UUT to EXT DCFM The front panel DCFM indicator should come on within one second The 1953A should read within 500 Hz of the 800 MHz frequency Connect the 8840A to TP12 TP12 should read 0V DC Connect the 8840A to J1 P3 The 8840A should read between 3V DC and 8V DC Set the UUT to ACFM Repeat step 26 to verify performance 6E 17 6E 1
128. the signal passes through diodes CR21 through CR24 to the pulse modulator U5 A buffer amplifier follows the pulse modulator and consists of Q9 and associated components This provides 8 5 dB of gain This amplifier is then followed by the 6 dB final amplifier which is composed of Q16 and associated components The final amplifier provides at least 20 dBm output at low distortion For HET band operation 0 01 to 15 MHZ the signal from the power splitter is routed through CR18 to the HET band circuitry The RF signal passes through a 95 MHz LPF then an adjustable attenuator R70 through R75 and then to the RF port of U3 a double balanced mixer The signal frequency at the mixer RF port varies from 80 01 to 95 MHz The 80 MHz local oscillator LO signal for the mixer comes from the A2 Coarse Loop PCA through 73 and is amplified by 01 This signal is then amplified by class C amplifier Q10 which is followed by a band pass filter and 3 dB pad to provide 18 dBm at the mixer LO port The mixer 0 01 to 15 MHz output signal is passed through a diplexing low pass filter C99 through C104 R76 that suppresses unwanted mixer spurious products while maintaining a 50 ohm load at the mixer IF port The filtered IF signal is amplified by a two stage IF amplifier Q13 Q14 and associated components The IF amplifier gain is nominally 20 dB The signal then is filtered to remove remaining LO and RF signals before being recombined at CR24 with the main s
129. transistor collector is applied to an 8 dB attenuator that provides isolation R13 R15 and then to a low pass filter that attenuates harmonics to less than 20 dBc C41 C42 and printed lines PIN diode has low RF resistance and passes the oscillator signal when the oscillator is on and goes to a high impedance when the oscillator is off 6C 31 TROUBLESHOOTING AND REPAIR FREQUENCY SYNTHESIS Band control signals CSVCOOH and CSVCOIH are decoded by U3 and 04 08 This circuit applies bias current only to the selected oscillator transistor Thus only one oscillator is activated per band PIN diodes 7 9 connect the active oscillator to a resistive signal splitter R21 R22 that drives monolithic 11 dB amplifiers 01 and U2 The 7 dBm output of 01 connects to the A2 Coarse Loop at J7 by a through the plate coaxial connector and the output of U2 also at 7 dBm connects to the A12 Sum Loop PCA at J8 by a coaxial cable COARSE LOOP VCO TROUBLESHOOTING 6 27 The Coarse Loop controlled by the Coarse Loop generates the coarse loop signal that is further processed in the Sum Loop PCA A problem with the Coarse Loop VCO can cause Coarse Loop Unlock status code 243 to appear Self test error codes 320 through 323 can also be triggered by a faulty Sum Loop VCO To determine that the Coarse Loop VCO is faulty rather than another assembly the following tests can be performed First ground J5 the pha
130. voltage exceeds 190 mV indicating loop unlock The output of 0115 is applied to the 1A input of U114 dual monostable multivibrator and trips the A one shot upon unlock detection One shot A is configured for a 10 ms output pulse and drives comparators U102A and U102B which disable the low and high frequency paths ofthe loop amplifier respectively during the 10 ms pulse U102A turns off 0109 and U102B turns off bias current to 0108 effectively open circuiting the loop amplifier This disabling action opens the loop and allows time for all the frequency inputs to the Sum Loop PCA to settle to proper values following a change in instrument RF frequency prior to sum loop phase lock TROUBLESHOOTING AND REPAIR FREQUENCY SYNTHESIS acquisition The trailing edge of the one shot A pulse triggers one shot B at the 2B input One shot B is configured for a 0 5 ms pulse and drives comparator U102C which switches acquisition oscillator U105 to the 14 kHz mode This acquisition frequency results in optimum lock on behavior During the 0 5 ms pulse unlock comparator U115 is disabled to allow acquisition to occur If Sum Loop PCA inputs are correct acquisition occurs during the 0 5 ms pulse and U105 stops oscillating due to changes in loop dynamics After the 0 5 ms one shot B pulse 7105 is set to the 800 Hz mode to improve closed loop dynamics but doesn t oscillate if the lock was obtained U102D is azero crossing comparator that senses th
131. 0 LF353N U 36 ISOLATOR OPTO LED TO TRANSISTOR DUAL 454330 50579 ILCT 6 254 U 37 60 IC FTTL SYNC PRESET DECADE COUNTER 854450 18324 74 160 2 U 50 IC MONOLITHIC MICROWAVE AMP 773218 7 751 MSA0304 U 5 IC BPLR MONOLITHIC MICROWAVE IC AMP 836593 7 751 MSA 0885 U 52 3DB COUPLER FOR SUBSYNTH 860648 89536 860648 U 53 54 IXER DOUBLE BALANCED 1 500 MHZ 733105 16469 SBL 1 27 2 55 IC BPLR WIDEBAND AMPLIFIER 600 MHZ 854542 18324 NE5205N 56 IC ECL QUAD 2 INPUT NOR GATE 380881 04713 MC10102P U 57 IC ECL DUAL D M S F F W SET amp RESET 454959 04713 MC10131P U 5 IC ECL TWO MODULUS PRESCALER 722298 04713 120111 U 59 IC OP AMP QUAD JFET INPUT 14 PIN DIP 483438 01295 TLO84CN 61 IC CMOS DUAL DECADE RIPPLE COUNTER 854349 18324 74HCT390N U 62 IC STTL 360 CELL GATE ARRAY 72318 61271 121301 U 63 ARRAY 5 TRANS 5 ISO 2 PNP 3 NPN 418954 02735 3096 W 1 CABLE ASSY RF JUMPER 861083 89536 861083 XU 23 SOCKET IC 24 PI 376236 91506 224 AG39D XU 62 SOCKET 1 28 448217 91506 228 AG39D Z 10 RES NET SIP 8 PIN 7 560 2 484451 91637 CSC08A 01 561G 2 20 RES NET SIP 10 PIN 9 RES 510 4 2 478800 91637 CSC10A 01 511 22 RES NET CERM CUSTOM 501841 01121 316B103F 7 22 RES NET SIP 10 PIN 5 RES 1 4 23 655209 91637 5 10 031026 An in S column indicates static sensitive part 7 30 REPLACEMENT PARTS R47 D 035 UM 818 14
132. 0 R A B 35 C 15 334 35 649913 C 36 52 62 649913 C 9 34 CAP 10UF 20 25V 714774 56289 1990106 0025 1 2 C 12 43 CAP CER 33PF 1 25 100V COG 838466 72982 RPE121911C0G330G100V 2 C 1 CAP TA 150 20 20V 807610 56289 199D156X0020DA1 1 37 0 0470 4 205 50 7 831487 04222 SR215C473MAATR 1 63 CAP CER 220PF 4 205 50V COG ee 72982 RPE122 901COG220M50V 20 74065 L 4 CHOKE 6TURI 320911 89536 320911 1 1 6 8 PIN SINGLE PWB 0 025 SQ 267500 00779 87623 1 115 P 12 14 67 267500 P 69 82 84 267500 88 90 98 267500 P 135 139 141 267500 149 151 158 267500 99 109 111 SOCKET SINGLE PWB FOR 042 049 PIN 866764 00779 645991 3 3 P 115 118 122 866764 124 128 130 866764 134 866764 0 TRANSISTOR SI NPN SMALL SIGNAL 150359 07263 2N3053 R RES CF 1M 5 0 25W 573691 59124 1 4 105 J B R 2 RES CF 2K 5 0 25W 573238 59124 1 4 20208 R RES CF 1K 5 0 25W 573170 59124 CF1 4 10208 2 R 4 RES 100 5 0 25W 573014 59124 CF1 4 101 JB R 6 RES CF 4 7K 9 0 25W 573311 59124 CF1 4 472 JB R 7 8 RES CF 120 4 5 0 25W 643494 59124 CF1 4 121 J 2 R 9 10 RES CF 51 5 0 25W 572990 59124 1 4 510 JB 2 R 11 13 RES CF 470 5 0 25W 573121 59124 4 471 JB 3 5 SWITCH DIP SPST 4 POS 408559 00779 435166 2 TP 2 TERM FASTON TAB 110 SOLDER 512889 00779 62395 3 0 16 MPU 8 MHZ DIP
133. 00 ohm 10x probe The collector bias voltages should be 10 4 and 5 1 respectively TROUBLESHOOTING AND REPAIR FREQUENCY SYNTHESIS Table 6C 4 N Divider Logic States FRONT PANEL COARSE LOOP LOGIC STATE FREQUENCY FREQUENCY MHz MHz 128 64 32 16 8 15 00 576 0 0 1 0 0 1 1 15 25 584 0 0 1 0 0 0 15 50 592 0 0 1 0 0 0 1 15 75 600 0 0 1 0 0 0 0 512 608 0 0 0 1 520 616 0 0 0 1 1 1 0 528 624 0 0 0 1 0 1 536 632 0 0 0 1 1 0 0 544 640 0 1 1 1 1 552 648 0 1 1 1 1 1 0 560 656 0 1 1 1 0 1 568 664 0 1 1 1 1 0 0 576 672 0 1 1 1 0 1 584 680 0 1 1 1 0 1 592 688 0 1 1 0 0 600 696 0 1 1 1 0 0 0 608 704 0 1 1 0 1 1 1 616 712 0 1 1 0 1 1 0 624 720 0 1 0 1 0 1 632 728 0 1 1 0 1 0 0 640 736 0 1 1 0 0 1 1 648 744 0 1 0 0 1 0 656 752 0 1 1 0 0 0 664 760 0 1 1 0 0 0 0 672 768 0 1 0 1 1 1 1 680 776 0 1 0 1 1 1 0 688 784 0 1 0 0 1 696 792 0 1 0 l 1 0 0 704 800 1 0 1 1 1 1 1 896 808 0 0 904 816 0 1 0 1 912 824 0 0 0 920 832 1 0 1 1 0 1 1 928 840 1 0 1 1 0 1 0 936 848 0 0 0 944 856 l 0 1 0 0 0 952 864 0 960 872 1 0 1 0 1 1 0 968 880 1 0 1 0 1 0 1 976 888 1 0 1 0 1 0 984 896 0 0 0 992 904 0 0 0 1 0 1000 912 1 0 1 0 0 0 1 1008 920 1 0 1 0 0 0 0 1016 928 1 0 0 1 1 1 1 1024 936 1 0 0 1 1 0 1032 944 1 0 0 1 1 0 1040 952 1 0 0 1
134. 000F 59124 50 09312 59124 50 VI D 15420 65940 1252303 91637 55 1211 1 1 91637 55 1401 F 1 1 80294 3329 1 500 91637 1 01370 59124 CF1 4 VT 1037 REEL 71590 5063001002 59124 CF1 4VI226J 59124 MF50VTD392F 00779 62395 1 1AV65 TFM 2H 8 lAV65 lAV65 SBL 1 59 04713 MLM358P 01295 5 145748 7 751 MSA0304 04713 78105 12040 1339 18324 3553484 17856 550500203 32293 AD7533JN 89536 860994 12040 1M393 04713 SN74LS221N 18324 NE529A 04713 SN74L5122N 91637 0 14031042 column indicates a static sensitive part Wh 10 REPLACEMENT PARTS 057 1 279 140 5 quic e m ale 19714 R15 o J7 14 6080 1607 Figure 7 12 A12 Sum Loop 7 53 REPLACEMENT PARTS Table 7 13 A13 Controller PCA See Figure 7 13 REFERENCE FLUKE MFRS MANUFACTURERS DESIGNATOR STOCK SPLY PART NUMBER TOT A NUMERICS 5 DESCRIPTION N0 CODE OR GENERIC QTY E C 1 CAP AL 47UF 20 50V SOLV PROOF 822403 62643 KMESOVB47RM6X11RP 1 C 2 10 11 CAP POLYES 0 1UF 10 50V 649913 60935 185 0 1 K 005
135. 01 SIGNAL DESCRIPTION TP1 DC 98 5 mV 980 mV Ext AM FM level indicator reference TP2 DC audio 14Vto OV 2 6V Detector Linearizer output TP3 N A TP4 Not Used TP5 DC audio 2 to 4V on Pulse Modulator to Output PCB TP6 DC audio 0 to 2 8V DC AM input scaled by AM TP7 DC audio 0 04 to 3 0V DC nominal 1 0V DC Leveling loop control voltage TP8 DC audio 14V nominal 1 0V DC Modulator control voltage This test point is an input for factory test of ALC loop RF LEVEL AM 6D 9 TROUBLESHOOTING AND REPAIR RF LEVEL AM 6D 10 RF LEVEL ADJUSTMENTS 6D 10 The Output Section adjustments listed below are covered in the following paragraphs e Modulation Control PCA All R23 Level DAC Offset Adjustment R8 AM DAC Offset Adjustment R28 Detector Offset Linearity Adjustment R10 AM Depth Adjustment R20 RF Level Adjustment R71 External Modulation Level Indicator Adjustment R99 Sum Loop Steer Gain Adjustment Premodulator PCA A10 R51 C7 AM Bandwidth Adjustment Output PCA A8 R96 Q16 Bias Adjustment Q9 Bias Adjustment R72 Het Mixer Level Adjustment R10 Het Gain Adjustment C201 Gain Flatness Adjustment R82 R101 and R102 are related to FM performance and are discussed under the heading Alignment of FM PCA A14 in Section 6E Any adjustment can be made independently unless it is noted that it interacts with another adjustment Interdependent adjustments
136. 02842 9 8 Teu q San hi n 0 7 61 Figure 7 14 A14 FM REPLACEMENT PARTS 7 62 Table 7 15 A15 Power Supply PCA See Figure 7 15 N REFERENCE FLUKE MFRS MANUFACTURERS 0 DESIGNATOR STOCK SPLY PART NUMBER TOT T gt gt 5 DESCRIPTION CODE OR GENERIC TYPE QTY E C 1 AL 1000UF 20 507 SOLV PROOF 782391 00199 5 102 1 92 53 CAP AL 22000UF 205 10V SOLV PROOF 844725 62643 KME10VR223M35X301V4 2 C 4 10 17 CAP TA 4 TUF 20 50V 832675 31433 3566475 050 5 9 C 22 24 29 832675 C 32 43 47 832675 5 CAP AL 120000 20 25V SOLV PROOF 844720 62643 KME25VR123M35X30TV4 C 6 CAP AL 4700UF 4 202 25V S0LV PROOF 816827 56289 82D472M025KA5 1 CAP AL 470UF 30 10 80V SOLV PROOF 574160 62643 KME 80VN471K23X27LLV C 8 13 18 CAP POLYES 0 1UF 4 202 50V 837526 40402 MKT1823104056 C 21 23 30 837526 41 42 44 837526 C 58 837526 C 9 TA 4 TUF 4 202 25V 161943 56289 1960475 0025 1 12 19 CAP POLYES 0 22UF 10 100V 2 80031 719A1CB224PK101SA 5 1231 43611 C 14 40 CAP AL 220UF 50 20 357 460279 62643 5 35 220 2 C 15 CAP 220UF 4 202 6V 408682 56289 1960227 0006 4 C 16 25 CAP TA 22UF 20 25V 357780
137. 0V CAP CER 58 501 C06 0805 CAP CER 18PF 5 50V C0G 0805 CER 000PF 1 202 50V 0805 CAP POLYES 0 22UF 4 105 50V CAP POLYES 0 15UF 10 50V CAP POLYES 0 03308 10 50V CAP POLYES 0 1UF 39 1 2 DA AC CAP POLYPR 100 4 15 100 CAP POLYPR 470PF 1 100V CAP CER ATP 25 1000 COG CAP POLYPR 330PF 1 1007 CAP POLYPR 1000 lt gt x 100V CAP TA 2 2UF 08 1 ZENER COMP 6 37 34 TOPPM 2A ZENER UNCOMP 10 0 10 20 0 0 4W DIODE SI BV 75 07 10 150 500MW D ODE SI BV 75 07 RADIAL INSERTED DIODE SI SCHOTTKY BARRIER SMALL SIGNL du ET SINGLE PWB FOR 042 049 PIN SOCKET SINGLE PWB FOR 0 034 0 037 PIN CHOKE 6TURN 1 UCTOR 0 68UH 4 102 221MHZ SHLD UCTOR ADJ 33 8MH UCTOR ADJ 44 2MH UCTOR 1000 10 12MHZ SHLD UCTOR 0 03309 10 1000MHZ UCTOR 10 TURNS 5 6 9MHZ SHLD 5 8MHZ SHLD CJ C2UJCJ C2 DUCTOR 390UH DUCTOR 270UH FLUKE STOCK 603985 603985 837526 837526 837526 837526 837526 837526 91236 463448 463448 186288 186270 MFRS SPLY CODE 62643 40402 56289 62643 31433 04222 04222 56289 84411 65964 40402 69919 65964 68919 56289 04222 04222 56289 62643 62643 05397 95275 05397 60935 96881 96881 60935 40402 40402 04222 40402 40402 56289
138. 1 A9 Sum Loop 6 5 6 12 A10 Premodulator 6 6 6 13 11 Modulation Control PCA 6 6 6 14 A12 Sum Loop 6 6 6 15 A13 Controller 6 6 6 16 EM Board pr eener oh sink hes ee 6 6 6 17 A15 Power Supply 6 6 6 18 AT9 Switch PCA 82 Abed kG hind ete p 6 6 6 19 A20 Attenuator RPP Assembly A7 A21 0 6 6 6 20 22 Delay Line Assembly A25 A26 Delay Cable Trim Cable 6 6 6 21 UPDATING COMPENSATION MEMORY WITH MODULE EXCHANGE 6 7 622 PARTS REPLACEMENT aoe aes ee ee 6 8 6 23 SELF TEST 6 8 6 24 Digital Tests es GAR Cad pe Ua E iP 6 8 6 25 AM TCS MD pet Os eet 6 9 6 26 Tests s e ttt tse 6 9 6 27 ERROR ERWIN Bao Ban Pee 6 9 6 28 t ed DE een be SC 6 10 6 29 Coarse Loop Pests EH 6 11 6 30 Sub Synthesizer 5 6 11 6 31 Sum Loop
139. 1 for 5 1V 0 05V Since the 5 1 15 and 15V supplies are of tracking design both the 15 and the 15V supplies should be at 15V 0 2V 6A 5 6A 6 Section 6B Digital Controller DIGITAL CONTROLLER BLOCK DIAGRAM 6B 1 The A13 Controller PCA under the direction of the instrument software handles the data interface between the front panel remote interface and 6080A AN functions The controller is located in a top side compartment of the lower module section The controller consists of the following functional groups Microprocessor Memory Front Panel Interface IEEE 488 Interface Attenuator Control Interface Module I O Interface Status and Control Latches Refer to Figure 6B 1 to identify the major sections and trace signal paths DIGITAL CONTROLLER CIRCUIT DESCRIPTION A13 6B 2 Microprocessor 6B 3 The software is executed on a 68 16 bit microprocessor The 8 MHz digital system clock signal is generated by an oscillator comprised of gates from 018 and crystal Y1 Supply voltage monitor TL7705A U13 generates the active low reset signal to the 68 000 The reset signal is generated on power up or if 5 V supply drops below 4 5 The reset signal remains low for 200 ms Memory 6B 4 The program instructions and constant data are stored in two 128 KB EPROMs U2 and U3 The stack and program variables are stored in two 8 KB static RAMs U6 and U7 Non volatile front panel setups and one half o
140. 12145 8 8 603506 772855 741504 402776 512095 845086 320937 261743 320911 866764 26150 81273 53025 5350 79979 75694 1465 801282 182045 120045 799635 572958 799908 799726 799783 799676 799759 643502 799650 782060 556829 836593 773218 454900 418780 ke w MFRS SPLY CODE OR GENERIC TYPE 04222 05397 05397 40402 12982 04222 89536 12982 51406 12982 51406 80031 80031 04222 05397 61058 25403 28480 16733 02113 24159 24159 89536 00779 00779 in S column indicates a static sensitive part MANUFACTURERS SR CO CC PART NUMBER 151C102MATR 805C101J5GAT 805C100J5GAT MKT1823104056 81 SR 37 81 RP 81 RPE 22 22 SR C3 201A10 6871 01 100C060339C E110NPO18RG100 GATR 22 631 09228 22 631 10159 S1A6R8CAA 5C181J1G5EA ECEALCU471 BB HP 70 15 4058 3379 2033 0 04XXX S MR 0 68 MR 33 32 64 87 81 53 BF CC RX RM CC CC C 50 R2 CC 50 CC CF 50 50 CF 0911 5991 3 623 1 2135 0153 2 R91 F 501001F 39106150 738 28 03001 F 504640F F553012FT 1 F 5082R5F 63JD33R2F F 50200 1 4 301 J 63005118 63JD1624F 1 41050 lt gt 1 MSA 0885 MSA0304 SC 629441 MC34001P 2 01 100 0 0109 01 100 060829 0C0G1006100V gt Con REPLACEMENT PARTS 6080A 1607 Figure 7 4 A3 Sub Synt
141. 13 7 56 14 FM 7 14 7 57 7 14 7 61 15 Power Supply 7 15 7 62 7 15 7 64 16 IEEE 488 Connector 7 16 7 65 7 16 7 66 19 Switch 7 17 7 67 A20 Attenuator RPP Assembly 7 18 7 68 A7 Relay Driver 7 19 7 69 7 17 7 10 A2 Attenuator Ain 7 20 7 71 7 18 7 12 REPLACEMENT PARTS 7 2 INTRODUCTION 7 1 Section 7 contains an illustrated list of replaceable parts for the 6080 Synthesized Signal Generator Parts are listed alphanumerically by assembly The part lists include the following information 1 Reference Designation 2 Description of each part 3 Fluke Stock Number 4 Federal Supply Code for Manufacturers A list of part manufacturers arranged numerically by Federal Supply Code is provided at the end of Section 7 5 Manufacturer s part number 6 Total Quantity of components per assembly 7 Recommended Quantity This entry indicates the recommended number of spare parts necessary to support one to five instruments for a period of2 years This list presumes an availability of common electronic parts at the maintenance site For maintenance for 1 year or more at an isolated site it is recommended that at least one of each assembly in the instrument be stocked HOW TO OBTAIN PARTS 7 2 Compon
142. 135 714923 R 6 RES MF 4 32K 1 125W 100 851535 R 7 RES MF 80 6 1 0 5W 100PP 158790 R 8 19 29 RES CF 1K 5 0 25W 573170 R 31 573170 R 20 41 RES CERM 51 4 51 125W 200PPM 1206 74627 22 117 RES MF 750 1 0 125W 100PP 120516 23 53 RES MF 182 1 0 25W 100 199726 25 07 5 150 4 1 0 125 100 719674 R 26 RES 37 4 1 0 125 100PP 71450 30 RES MF 464 1 0 25W 100 801282 R 32 RES 2 94K 1 0 125W 100PP 261628 R 33 RES 12 1 1 0 12511 100PP 719542 R 34 RES MF 348 1 15 0 511 100 24576 R 35 RES 301 1 0 5W 100 167494 31 RES 6 65 15 0 12517 100 720474 R 38 RES MF 14 3K 1 0 125W 100PPM 291617 R 39 RES MF 590 1 0 125W 100 866236 R 40 RES CF 100 5 0 25W 573014 42 71 RES MF 68 1 1 0 125W 100PPM 855270 R 3 RES CF 300 5 0 25W 643502 R 44 169 RES 392 1 0 125W 100PP 260299 R 45 RES 806 1 0 125W 100PPM 223552 R 47 RES 523 t 1 0 125W 100 820274 R 48 RES 402 1 15 0 1251 100 120201 R 49 RES CF 4 3 4 5 0 25W 640987 R 51 RES MF 11 1 19 0 125 100PPM 854729 R 55 144 RES 357 1 0 25W 100PP 182045 R 6 RES 51 1 1 0 2501 100 799650 R 59 60 RES 120 5 0 25W 643494 R 6 RES CF 100 5 0 25W 810465 R 69 RES CF 4 7 4 52 0 25W 816637 10 RES MF 154 1 0 125W 100PP 866202 R 72 5
143. 140092 799684 772277 572966 573485 573311 682575 682575 573014 830893 844832 854302 773218 173218 845099 113226 402669 459974 478800 cont MFRS SPLY CODE 52163 89536 24159 52163 52163 52163 52163 52163 52163 52163 00779 04713 21014 04713 04713 59124 59124 59124 59124 59124 59124 59124 91637 91637 59124 59124 01121 91637 59124 32997 59124 8003 91637 59124 59124 8003 8003 91637 59124 91637 91637 91637 91637 80031 71590 59124 59124 59124 59124 89536 59124 59124 1AV65 33297 7 751 04713 7E7531 27014 91637 91637 in S column indicates static sensitive part REPLACEMENT PARTS MANUFACTURERS PART NUMBER OR GENERIC TYPE 5 5087227 013 320911 0 68 5087226 613 5087226 513 5087226 423 5087226 813 5087226 113 6087226 233 5087230 723 87623 1 SPS8763RLRA MPS6562 D262 2N3906RLRA MRF 581 RM73B 2B J2200B RM73B 2BJ22R0B CF1 4 152 J CF1 4 202 J B RM73B 2B J13000B RM73B2BJ470B RM73B 28 J39R00B MFF1 2422F CMF653010FT 1 1 4 102 JB 1 4 272 7 B 1015 652100 1 RK73H2BF110B 3386R 1 501 052 1 82207 1 8 5P51E B CMF 55 2000 F T 1 MF5549R9F CF1 4101J 1 8 5P24E B 1 8 5P110E B CCF 5082R5F 0521 89107 F5526R7F 1 1 F 55 1401 F 1 1 F552551FT 1 F6559ROFT 1 8 58160 8 063JD5110F F1 4361J Fl 4 220 J B Fl 4 333 J 1 4 472 JB 82575 1 4 101 JB F1 8680J 1 1 65 UPB584G E2
144. 15 and strobes the front panel switch matrix The switch columns are strobed in unison with the display fields The switch matrix status is read by the tri state buffer U14 Remote Footswitch 6B 32 The rear panel AUX connector has inputs that accept remotely generated sequence up sequence down and bright digit field frequency or amplitude commands The requests are generated by momentarily grounding the signal of interest The pinout of this connector is provided in Appendix I Electromagnetic emission considerations dictate that the rear panel control inputs are static Gates from U12 013 015 and 016 convert the static rear panel inputs into strobed key requests The software services the requests in the same manner as all ofthe strobed keys The front panel display can be turned off by special function Turning off the display also stops the switch matrix strobes so all strobed keys become totally inactive The front panel ctritct key is excluded from the switch matrix and is connected to circuitry similar to the rear panel control signals This allows the key to remain active when the display is off so it can be used to enable the display TROUBLESHOOTING AND REPAIR DIGITAL CONTROLLER Edit Knob Interface 6B 33 The edit knob interface circuitry receives two input signals WINDOWL and TRIGGERL from the opto interrupters on the A19 switch PCA Ifthe trigger signal makes a high to low transition while the window signal is l
145. 15 for the ground connection Adjust R116 for a minimum peak to peak voltage The waveform should be less than 150 mV peak to peak Loop Gain Adjustment R167 6 37 TEST EQUIPMENT Low frequency synthesized signal generator LFSSG Wideband AC voltmeter WBVM REMARKS The Loop Gain Adjustment is normally required only when U3 0108 or any associated components are replaced or when the adjustment has shifted The upper plate cover of the lower module must be installed prior to this adjustment PROCEDURE An 800 kHz AC signal is applied to the Sum Loop VCO steering port through TP6 Loop gain is adjusted via R167 so that the AC voltages at the Sum Loop VCO steering and phase lock ports are equal 1 3 4 Access R167 TP3 TP4 and TP6 by removing the appropriate plate cover access plugs Program the UUT to SPCL 909 548 MHz 150 kHz FM deviation Turn EXT AC FM on Program the LFSSG to 800 kHz 20 mV RMS Connect the LFSSG output to TP6 via a BNC to clip lead adapter Connect the ground clip to the plate cover adjacent to TP6 6 43 TROUBLESHOOTING AND REPAIR FREQUENCY SYNTHESIS 5 Connect the WBVM to measure the AC voltage between TP3 and the plate cover adjacent to TP3 ground 6 Program the WBVM for dB relative The reading should be 0 dB 7 Connectthe WBVM to measure the AC voltage between TP4 and the plate cover 8 Adjust R167 for an indication of 0 0 dB 1 dB 9 Replace the access plug
146. 1911X7R102M100VPT GR 1 LED YELLOW T1 24 MCD 854547 28480 HLMP 1440 DS 1 DISPLAY VACUUM FLUORESCENT FREQUENCY 812685 89536 812685 05 2 DISPLAY VACUUM FLUORESCENT AMPLITUDE 812693 89536 812693 L 12 32 CHOKE 6108 320911 89536 320911 2 1 8 FOOT ADHESIVE RUBBER BLACK 50X 12 543488 28213 575008 8 11 64 PIN SINGLE PWB 0 025 SQ 267500 00779 87623 1 54 Q 1 TRANSISTOR SI NPN SMALL SIGNAL 698225 04713 2N3904RLRA2 R 1 RES CC 1 5 4 108 1W 109413 01121 GB1521 R 2 RES CF 100K 5 0 250 573584 59124 CF1 4 104 JB R 3 RES 620 1 52 0 251 641092 59124 CF1 4 621 JB R 4 5 RES CF OK 4 55 0 25W 513394 59124 CF1 4 103 JB 2 R RES CF 20 5 0 250 573444 59124 1 4 203 JB 2 8 9 RES 180 5 0 25W 573048 59124 CF1 4 181 JB 2 5 SWITCH PUSHBUTTON DPDT PUSH PUSH 836361 31918 1820 9 0 4 IC CMOS OCTAL D F F W RESET 143286 18324 N74HCT273N 4 U 5 l9 19 IC CMOS DUAL D F F EDG TRG W CLR 741702 04713 74 74 3 U 6 10 IC BIPLR 8CHNL FLOURESCNT DISPLY DRVR 535799 56289 UDN 6118A 5 0 1 IC CMOS RETRG MONOSTAB MULTIVB W CLR 741496 12040 74HC123AN U 12 IC CMOS HEX SCHMITT TRIGGER 723320 04713 74 14 U13 15 IC 74HC 5 HEX INVERTER W OPEN DRAIN 854018 01295 SN74HC05 2 U 14 IC CMOS OCTL LINE DRVR W 3 ST OUT 741892 01295 SN74HCT244N U 16 IL CMOS QUAD 2 PUT AND GATE 741801 04713 MC74HCO8N U 17 IC CMOS QUAD 2 NAND W SCHMT 740852 18324 132 0 2 IC CMOS 3 8 LINE DCDR
147. 2 12 0 M2 M2 0 2 12 require 3 24 12 M3 M3 12 MO M3 24 ments 4 24 12 M4 4 12 4 24 5 24 12 5 5 12 MO M5 24 6 24 12 6 12 MO M6 24 7 24 12 7 7 12 7 24 Sum of Errors 7 Subtract the measured power for section zero from the sum ofthe measured power for that section plus the nominal attenuation for that section This is done for attenuator sections through 7 only Example M0 M1 6 for section 1 The eight section errors and their sum must not exceed the requirement Table 4 3 shows the parameters of the high level accuracy test NOTE To test attenuator sections 4 through 7 program the 6080A AN Signal Generator to 12 dBm and key in CO 21037 through C8 2 87 respectively 4 7 PERFORMANCE TESTS 4 8 8 Repeat steps 4 through 7 with the UUT programmed to each of the following frequencies 14 20 40 80 160 320 550 640 700 850 950 1024 MHz Table 4 3 is an example of this procedure in which the measured power and the error calculations are shown This example is for one frequency and these measurements and calculations are repeated at other frequencies In this case the section errors and the sum of the section errors are within the test limits therefore the unit passed the high level accuracy test Table 4 3 High Level Accuracy Test Conditions Sample OUTPUT POWER ATTENUATION PROGRAMMED
148. 202 50V CAP CER 1 4 0 25PF 100 CAP CER 100PF 2 100V COG CER 100V COG CER 3 4 0 25PF 100V COJ CAP CER 18PF 4 25 100V COG CAP CER 8 2PF 0 25PF 1007 COH CAP CER LOPF 23 1007 COG CAP CER 2 2PF 1 0 25 100V C0G CAP CER L5PF 2 100V COG CAP CER 6 8PF 0 25PF 100V COH CAP CER 180PF 5 100V C0G CAP AL 470UF 20 16V SOLV PROOF ODE SI VARACTOR PIV 28V ODE 51 SMALL SIGNAL 6 VHF ONN COAX SMB PWB OR PANEL DUCTOR 0825UH 5 SHLD DUCTOR 0 68UH 10 221MHZ SHLD DUCTOR 0 33UH 10 300MHZ SHLD OKE 6TUR OCKET SINGLE PWB FOR 042 049 PIN IN SINGLE PWB 0 025 SQ N FEED THRU UMPER REC 2 POS 100CTR 025 SQ POST SISTOR SI NPN HI FREQ SMALL SIGNL F 1K 1 0 25W 100PP RES CERI 125W 200PPM 1206 RES CERI 200 1206 F 464 1 0 25W 100 29 E F1 8 JJ ca rj je 59 8 29 ES e UI wo N a RES 6 0 25W 100PPM RES CF 1M 5 0 125W IC BPLR MONOLITHIC MICROWAVE IC AMP IC BPLR MONOLITHIC MICROWAVE AMP IC ECL DIV BY 10 DIV BY 11 COUNTER AMP JFET IN COMPENSTD 8 PIN DIP T oo 1 4 STOCK 837542 514133 494781 837526 837526 5
149. 22221 6C 5 ge pit ait iT hen ieee 6C 6 6C 5 N Divider Timing 6C 7 6C 6 Reference Section Block Diagram 6C 18 6C 7 Coarse Loop Block 6C 21 6C 8 Sum Loop Block Diagram 22 22222222222222224 6C 33 6D T Level Fault Tree o SERRE TV uev 6D 1 6D 2 RF Level Block 6D 2 6 1 6 Fault 6 1 6E 2 FM M Block 6E 3 6E 3 FM M Timing 22222222222222222 2 6E 5 6F 1 Modulation Oscillator Block 6F 1 Xi xii Section 1 Introduction and Specifications INTRODUCTION 1 1 The 6080A AN Synthesized RF Signal Generator also referred to throughout as the signal generator is a fully programmable precision synthesized signal generator The 6080A AN is designed for applications that require good modulation frequency accuracy and output level performance with excellent spectral purity The signal generator is well suited for testing a wide variety of RF components and systems including filters amplifiers mixers and radios
150. 24 and TP25 should be predominantly high The voltage at 40 should be about 2V If the signals at TP24 and 25 are correct but the voltage at 40 does not change from approximately 2V to 28V as the frequency at TP21 is adjusted above and below 1 MHz the problem is probably in the loop amplifier 034 etc the current source U63 etc the switching diodes CR18 CR19 or the KN DAC 06 07 etc The loop should lock when you reconnect the shorting jumper between 40 and If the loop doesn t lock the final circuitry to check is the low pass filter 1 56 L57 etc the clamp circuit 035 U36 etc and the lead lag network FET 010 should be on 5 V on the gate below a undivided Sub Synthesizer frequency of 230 MHz and off 0V on the gate above 230 MHz You can disable the clamp circuit by disconnecting CR20 and 21 To check the various DACs program the UUT to SPCL 943 This sets all the DACs at full scale The voltage at the output of the KN DAC TP35 REFVOL DAC TP39 and STEERING DAC TP6 should be approximately 10 23V With the UUT programmed to SPCL 942 which sets the DACS to half scale the voltages should be about 5 12V TROUBLESHOOTING AND REPAIR FREQUENCY SYNTHESIS SUB SYNTHESIZER ADJUSTMENTS 6C 5 The following procedures cover the five adjustments on the A4 Sub Synthesizer PCA listed below R5 DAC Full Scale Adjustment R99 Clamp Adjustment R98 Clamp Adjustment R106 Mixer LO Dri
151. 3002 Bobigny Cedex Tel 33 1 4942 8040 Germany F R G Philips GmbH Service fuer FLUKE Produkte Department VSF Oskar Messter Strasse 18 D 8045 Ismaning Munich West Germany Tel 49 089 9605 239 Greece Philips S A Hellenique 15 25th March Street 177 78 Tavros 10210 Athens Tel 30 1 4894911 Hong Kong Schmidt amp Co H K Ltd 18 FL Great Eagle Centre 23 Harbour Road Wanchai Tel 852 5 8330222 India Hinditron Services Pvt Ltd 1st Floor 17 B Mahal Industrial Estate Mahakali Road Andheri East Bombay 400 093 Tel 91 22 6300043 Hinditron Services Pvt Inc 33 44A Raj Mahal Villas Extn 8th Main Road Bangalore 560 080 Tel 91 812 363139 Hinditron Services Pvt Ltd Field Service Center Emerald Complex 1 7 264 5th Floor 114 Sarojini Devi Road Secunderabad 500 003 Tel 08 42 821117 Hindtron Services Pvt Ltd 15 Community Centre Panchshila Park New Delhi 110017 Tel 011 6433675 Indonesia P T Lamda Triguna 6 JATJG Jakarta 13001 Tel 021 8195365 Israel R D T Electronics Engineering Ltd P O Box 43137 Tel Aviv 61430 Tel 972 3 483211 Italy Philips S p A Sezione 8 T amp M Viale Elvezia 2 20052 Monza Tel 39 39 363 5342 Japan John Fluke Mfg Co Inc Japan Branch Sumitomo Higashi Shinbashi Bldg 1 1 11 Hamamatsucho Minato ku Tokyo 105 Tel 81 3 434 0181 Korea Myoung Corporation YeoEui Do P O Box 14 Seoul 150 Tel 82 2
152. 302 308 309 IC ECL QUAD 2 INPUT NOR GATE 851613 04713 10 102 U 303 304 IC ECL QUAD 2 INPUT AND GATE 851618 04713 MC10H104P U 305 310 IC ECL HEX M S D F F EDG TRG 851782 04713 MC1OH176L U 306 IC ECL QUAD 2 INPUT OR NOR GATE 851621 04713 10 107 U 307 IC ECL TRIPLE 2 3 2 INPUT OR NOR GATE 851626 04713 10 105 311 IC BPLR WIDEBAND AMPLIFIER 1200 MHZ 866439 33297 UPC1651G U IC BPLR MONOLITHIC MICROWAVE 7 751 530304 U 1 0 501 OSCILLATOR 10MHZ TCXO 1 866475 57693 535 U 502 511 IC CMOS QUAD 2 INPUT NAND GATE 854468 07263 74 00 U 503 IC CMOS DUAL D F F EDG TRG 854471 07263 74ACT74PC U 504 IC FTTL QUAD 2 1 LINE MUX 854455 18324 N74F157AN U 505 IC STIL 100MHZ DIV BY 2 DIV BY 5 CNTR 473835 01295 SN74S196N U 506 IC ECL DUAL D M S F F W SET amp RESET 454959 04713 MC10131P U 507 IC FTTL HEX INVERTER 634444 04713 MC74E04 U 510 IC COMPARATOR HI SPEED 14 PIN DIP 386920 18324 529 U 513 602 ECL TRIPLE LINE RECEIVER 369702 04713 MC10116P 514 IC CMOS QUAD INPUT NOR GATE 851691 18324 74 02 515 IC CMOS TRIPLE 3 INPUT AND 854781 18324 74 W 1 CABLE ASSY RF JUMPER 861075 89536 861075 Y 601 CRYSTAL 39 999MHZ 0 0005 HC 35 U 855064 71034 BK 1B Z 201 RES SIP PIN 5 RES 10K 2 500876 91637 CSC06A 01 103 G Z 301 304 RES SIP 8 PIN 7 RES 510 2 447482 71450 750 81 R510 Z 501 RES
153. 3097 R 4 RES CC 10K 10 0 125W 246915 R 55 65 34 RES 2K 1 0 125W 100PPM 719815 R 32 106 110 19 5 111 719815 8 9 112 RES CF 47 5 0 25 822189 113 822189 R 0 RES 15 10 0 125W 261800 R 1 21 22 RES CC 10 4 10 0 125W 321125 R 2 15 RES 68 10 0 125W 261818 R 3 14 16 RES CC 100 1 105 0 125W 261826 60 122 261826 15 19 RES CF 56 1 5 0 25W 641068 R 8 20 RES CC 220 5 0 5W 186031 R 2 RES CC 13K 5 0 25W 221598 R 25 67 86 RES CF 1 5K 5 0 25W 810432 R 26 27 RES CF 360 5 0 25W 147527 R 28 29 73 RES CF 2 2K t 55 0 25W 851840 R 30 50 RES CF 100K 5 0 25W 658963 33 RES CC 33 4 102 0 125W 212914 R 34 RES CF 100 5 0 25W 810465 35 107 RES VAR CERM 1K 10 0 5W 393728 36 RES MF 2 49K 1 0 125W 100PPM 810523 R 37 RES 4 99K 1 0 1250 100 721548 R 38 RES MF 5 49K 1 1 0 125W 100PPM 721795 R 39 RES VAR CERM 5K 10 0 51 493593 40 127 RES 453 1 0 125W 100PPM 866681 R 4 RES 68 1 4 15 0 12 5W 100PPM 8552710 42 137 RES CF 2K 5 0 25W 810457 R 43 RES 246 5 0 25W 697599 R 44 119 RES VAR CERM 20K 20 0 5W 234443 R 45 94 RES VAR CERM 50 20 0 5 320861 46 2 4 4 23 0 251 866710 R 47 RES CF OK 5 0 251 697102 R 48 RES CF 1K 5 0 251 780585 49 RES VAR CERM 50K 4 205 0 51 225417 R 5 RES CF 1 2K 52 0 25W
154. 31433 361 226 025 5 2 C 20 38 CAP CER 470PF 10 1000V Z5F 368613 60705 562 5 102 EE471 2 C 28 CAP TA 4 7UF 20 25V 807644 56289 1990475 0025 1 C 31 48 CAP 1002 2 35V 411683 56289 196D106X0035PE4 2 C 33 34 CAP 2 20 10 35V 697433 31433 356 225 035 5 2 C 35 CAP TA 6 8UF 4 208 35V 807602 56289 199D685X0035DA1 39 CAP CER 68PF 4 105 10007 S3N 706812 60705 561CR3LRE102EE680K C 46 CAP CER 1800PF 5 50V C0G 528547 5397 C320C18205G5EA C 49 4700 4 205 507 501 PROOF 747493 62643 KMC50VBAT1M16X25LLV CR 1 DIODE 5 BRIDGE 200 10 1 0 296509 30800 KBP 02M 2 CR 2 3 ZENER UNCOMP 24 04 5 20MA 0 40 810317 04713 970BRR1 2 CR 4 8 DIODE SI 45PIV 7 5A DUAL SCHOTTKY 741322 04713 MBR1545CT 2 5 9 15 ZENER UNCOMP 6 2V 5 20 0MA 0 411 698662 04713 753A SR4348RL 3 CR 6 7 12 DIODE 51 100 PIV 1 5 116111 04713 5392 4 CR 14 116111 CR 10 ZENER UNCOMP 20 0V 5 6 2MA 0 4W 810275 04713 1N968BRR1 CR 11 ZENER UNCOMP 20 0V 55 6 2MA 0 4W 832576 04713 968B CR 16 ZENER COMP 6 3V 2 50 7 5 172148 04717 CZG20121RL CR 17 ZENER UNCOMP 3 3V 5 20 0 0 4W 820423 04713 746ARR1 CR 20 ZENER UNCOMP 6 8V 10 175 0MA 5 OW 483446 04713 53428 CR 21 DIODE SI BV 75 0V RADIAL INSERTED 659516 03508 4448 H 1 4 14 WASHER SHLDR NYLON 113 245 485417 86928 5607 50 5 H 5 6 13 NUT LOCK SS 4 40 55886
155. 5 0 5 Hz for 01 to 15 MHz Band to 15 kHz band 0 5 Hz for 15 to 32 MHz Band 0 5 Hz for 32 to 64 MHz Band 0 5 Hz for 64 to 128 MHz Band 0 5 Hz for 128 to 256 MHz Band 1 Hz for 256 to 512 MHz Band 2 Hz for 512 to 1056 MHz Band SSB PHASE 131 dBc Hz 20 kHz offset Frequency 250 MHz INTRODUCTION AND SPECIFICATIONS Table 1 4 Typical Signal Generator Performance cont 136 dBc Hz 20 kHz offset Frequency 1 GHz lt 140 dBc Hz 20 kHz offset Frequency 500 MHz BROADBAND SSB PHASE NOISE lt 140 dBc Hz 100 kHz offset 13 dBm RESIDUAL AM in 0 05 to 15 kHz 80 dBc AMPLITUDE MODULATION 3 DIGIT DISPLAY Amplitude 10 dBm INDICATED DEPTH 0 to 99 9 RESOLUTION oer ete 0 196 ACCURACY 0 to 9095 296 4 of setting at 1 kHz rate 5 lt 1 5 THD to 30 rate 1 kHz 396 THD to 7096 596 THD to 9096 AM BANDWIDTH 3 4 10 Hz to 100 kHz DC to 100 kHz external only INCIDENTAL 200 Hz at 1 kHz rate 5096 AM NOTE AM specifications apply where RF frequency Modulation Frequency is greater than 150 kHz FREQUENC
156. 5 11 Removing A8 Output 5 5 5 12 Removing the A9 Sum Loop 5 6 5 13 Removing the A10 Premodulator 5 6 5 14 Removing the A11 Modulation Control 5 6 5 15 Removing the A12 Sum Loop 5 7 5 16 Removing the A13 Controller PCA 5 7 5 17 Removing 14 FM 5 8 5 18 Removing the A20 Attenuator RPP Assembly 5 8 5 19 Removing the A22 Delay Cable 5 8 ii continued on page iii TABLEOFCONTENTS continued SECTION TITLE PAGE 6 CIRCUIT DESCRIPTIONS TROUBLESHOOTING AND ALIGNMENT 6 1 6 1 6 1 6 2 MODULE REPLACEMENT sse 6 4 6 3 Display PCA 6 5 6 4 2 5 Loop gue editada edis 6 5 6 5 Sub Synthesizer 23 6 5 6 6 4 Sub Synthesizer 6 5 6 7 5 Coarse Loop VCO 6 5 6 8 Mod Oscillator 2 6 5 6 9 AT Relay Driver Ie 6 5 6 10 ASOutput no iesus o RECURSUS n od 6 5 6 1
157. 50V 20 SR151C102MATR 1960224 0020 1 08055A680JAT050R 08055A181JAT050R 3 0805 101756 SR291A820CATR RPE121911C0G470G100V 315 5606165 SR151C472MATR 2 C320C271J1G5EA C320C151J5G5EA RPE122 901C06430J50V SR21C103MAT 6U 22 GRM708C0G3907200VPT VJ08050180JXAT T356F686L020AS RPE121 911C063906100V 121911 062210100 2 SR291A331JATR R87334K 85 2512 2 168 2 015 85 1 00 K 0050 R G B 85 2 22 K 0050 R C B 2 R67222K SR215A332JAT 4 68 2 047 990474 0035 1 85 0 1 K 0050 R A B 91320847 10 50 85 2 022 0050 8 KM63VB10RM5X11RP 62756 082 2800 2 3 5 QPND 4348 5 082 6264 125 2 748 SR4348RL 4448 748 Table 7 12 A12 Sum Loop PCA cont MFRS SPLY CODE 00719 16733 21845 22526 70707 89536 52163 52163 52163 52163 24159 24159 24159 52163 00779 00779 04713 04713 04713 07263 04713 17856 WhO SS p REFERENCE FLUKE DESIGNATOR 2 STOCK SASSNUMERICSSCSES 0 9 DESCRIPTION J 17 659 SOCKET SINGLE PWB FOR 042 049 PIN 866764 J 2 16 866164 J 0 CONN COAX SMB M PWB OR PANEL 512095 J 1 CONN COAX SMA M PWB OR PANEL 512087 J 7 SOCKET SINGLE PWB FOR 0 012 0 022 PIN 376418
158. 513196 R 52 RES 36 5 1 0 125W 100PPM 855259 R 53 RES CC 43 5 0 125W 115391 5 39 2 1 0 125W 100 855262 55 RES 182 1 0 125W 719757 R 5 RES CF 47K 5 0 25W 721787 R 57 RES CF 1 5K 5 0 25W 573212 58 65 90 RES CF 4 7K 5 0 257 721571 R 93 121511 R 59 RES CF 820 5 0 25W 574970 R 61 RES CF 10K 5 0 25W 573394 62 128 130 RES CF 1K 5 0 25W 573170 R 63 88 117 RES VAR CERM 100K 4 302 0 5W 193045 R 64 RES MF 150K 1 0 125W 100PPM 866327 MFRS SPLY CODE 51984 02113 24759 89536 24759 89536 12982 91637 An in S column indicates a static sensitive part MANUFACTURERS PART NUMBER OR GENERIC TYPE R602 5SR 42 052085 R33 413864 R6800 861138 R 2200 463448 87623 1 J310 PS6520RLRA PS6522 PS6562 D262 PS6560 5918 215771 SD213EE SD215DE 8252182 R25K361 BB1031 55 2001 F 1 1 CF1 4VT470J RCR056150KS BB1001 BB6801 BB1011 1 4 560 JB EB2215 CB1335 CF1 4VT152 CF1 4VT3061J CF1 4VT222J CF1 4 104J VT 4VT101J 52501 1 102 VF50VTD2491F MF55D4991F MF50VTD5491F 32991 1 502 MF50VDT4530F CMF5568RIFT 1 CF1 4VT202J CF1 4 VT243J 332H 203 3329H 1 500 CF1 4VT242J CFl 4 VT 103J REEL F1 4VT102J 3329H 1 503 1 4 122 5 CMF5536R5FT 1 BB4305 CMF5539R2FT 1 C C C e F55D1820F F1 4473J VT Fl 4 152 J 1 44727 VT CF1 4
159. 5255 Spain Philips Iberica Sae Depto Tecnico Instrumentacion c Martinez Villergas 2 28027 Madrid Tel 34 1 4042200 Sweden Philips Kistaindustrier Ab I amp E Technical Customer Support Borgarfjordsgatan 16 S 164 93 Kista Tel 46 8 703 1000 Switzerland Philips A G Technischer Kundendienst Postfach 670 Allmendstrasse 140 CH 8027 Zurich Tel 41 1 482211 Taiwan R O C Schmidt Electronics Corp 5th Floor Cathay Min Sheng Commercial Building 344 Min Sheng East Road Taipei Tel 886 2 501 3468 Thailand Measuretronix Ltd 2102 63 Ramkamhaeng Rd Bangkok 10240 Tel 66 2 374 2516 374 1632 Turkey Turk Philips Ticaret A S Inonu Caddesi 78 80 Posta Kutusu 504 Beyoglu Istanbul Tel 90 1 1435891 Uruguay Coasin Uruguaya S A Casilla de Correo 1400 Libertad 2525 Montevideo Tel 598 2 789015 Venezuela Coasin C A Calle 9 Con Calle 4 Edit Edinurbi Apartado de Correos Nr 70 136 Los Ruices Caracas 1070 A Tel 58 2 241 0309 241 1248 West Germany Philips GmbH Service VSF Unternehmensbereich Elektronik fur Wissenschaft und Industrie Oskar Messter Strasse 18 8045 Ismaning Tel 49 089 9605 260 8 89
160. 6 24 2 MHz Notch Adjustment 205 6C 30 6C 25 Alternate Reference Frequency Selection 6C 31 6 26 COARSE LOOP VCO A5 CIRCUIT DESCRIPTION 6C 31 6C 27 COARSE LOOP VCO TROUBLESHOOTING 6C 32 6C 28 SUM LOOP BLOCK 6C 32 6C 29 SUM LOOP A12 CIRCUIT 6C 34 6C 30 5 odd het ed desee qp 6C 34 6C 31 Audio Section 272522 nt CO AOT pels TUER eae 6C 35 6C 32 SUM LOOP TROUBLESHOOTING 6C 38 6C 33 SUM LOOP ASSEMBLY ADJUSTMENTS 6 41 6C 34 Steering Level Adjustment 112 6C 41 6C 35 Buffer Gain Match Adjustment 121 6C 42 6C 36 FM Null Adjustment 116 6C 42 6C 37 Loop Gain Adjustment 167 6C 43 6C 38 Acquisition Oscillator Level Adjustment 132 6C 44 6C 39 SUM LOOP A9 CIRCUIT 6C 44 6C 40 SUM LOOP 6C 45 6 RE LEVELIAM i orar Res 6D 1 60 1 RF LEVEL 0 6D 1 6D 2 RF LEVEL BLOCK
161. 6 or 17 TRMODL low for 31 N counts The total division is P 31 N 31 A or P 31 N 31 A On the 31st count the counters are reinitialized Figure 6C 5 shows the timing of the A counter programmed to 26 and the N counter programmed to 18 a total division of 213 Only the CKNL and MODEL signals shown in Figure 6C 4 are accessible at U62 pins 6 and 22 respectively FREQUENCY SYNTHESIS TROUBLESHOOTING AND REPAIR 8l 7 1 21 Lt 7 H 91 7300W 5 SLAdNI ITOHINOO 6 8 Aq Figure 6C 3 Triple Modulus Prescaler 6 5 TROUBLESHOOTING AND REPAIR FREQUENCY SYNTHESIS 1 YSLNNOO N Figure 6C 4 N Divider 6C 6 TROUBLESHOOTING AND REPAIR FREQUENCY SYNTHESIS CKNL 27 28 29 30 31 31 31 31 31 31 31 31 26 27 28 29 30 31 26 27 28 26 A COUNTER 20 21 22 23 24 25 26 27 28 29 30 18 19 20 21 22 23 24 25 26 19 18 TCAL N COUNTER TCNL QOL QIL LOADL RMOUTH MODEL Figure 6C 5 N Divider Timing Diagram 6C 7 TROUBLESHOOTING AND REPAIR FREQUENCY SYNTHESIS 6C 8 The N divider gate array includes a two decade rate multiplier that produces the fractional part of the division The N divider gate array rate multiplier produces a pulse train with a programmed number of pulses for a 100 cycle frame ofthe 1 MHz N divideroutput
162. 6 COMMERCIAL 3 H 7 10 1 SCREW MACH PH MAG SS 6 32 281 112236 COMMERCIAL 4 15 172236 H 8 9 SCREW MACH STL 4 40X 500 740761 COMMERCIAL 2 12 SCREW MACH PH STL 4 40X 375 740753 COMMERCIAL H 16 UT PRESS BROACH STL 6 32 393785 24347 KF2 632 J HEADER 1 ROW 156CTR 12 PIN 512160 27264 09 80 1123 J 2 HEADER 1 ROW 156CTR 5 PIN 512186 27264 09 80 1053 J HEADER l ROW 100CTR 15 PIN 854807 00779 1 641216 5 2 J 7 HEADER 1 ROW 100CTR 2 PIN 602698 00779 640456 2 1 3 HEAT DIS PWB MTG 1 380 2 000 500 386235 13103 60320 2 2 HEAT DIS VERT 1 65X1 00X1 50 10 220 853759 13103 62988 2 3 05 1 P 4 5 NSUL PART TRANS SILICONE POWER 534453 55285 7403 09FR 54 2 p 7 8 HEAT DIS VERT 1 65X1 00X1 50 T0 220 853754 13103 6398BP3CNE62GF1 BAG 2 9 HEAT DIS HORIZ 1 860X1 062X 50 0 3 740738 91502 7 423BA 10 11 SPACER SWAGED RND 6 32 187 351882 94423 9533B B 0632 2 12 1 ROW 100CTR 20 PIN 832808 00779 2 103239 0 Q L2 TRANSISTOR SI NMOS PWR 10 220 831255 61752 1RC530 007 2 Q 3 THYRISTOR SI TRIAC VBO 200V 8 0A 413013 02735 128008 Q 4 THYRISTOR SI SCR VBO 100V 0 8A 742643 04713 2N5062 5 TRANSISTOR 91 SMALL SIGNAL 816298 04713 MPS8099RLRA 1 RES CF 220 4 52 0 25W 574244 59124 CFl 4 221 JB 2 RES CC 6 8K 4 102 0 58 108399 01121 EB6821 R 3 RES CC 820 5 0 25W 148015 01121 8215 R 4 RES CC 22K
163. 6080A AN SYNTHESIZED SIGNAL GENERATOR Service Manual P N 868906 Fl K Inc All rights reserved October 1989 1989 John Fluke PO Box C9090 Everett WA 98206 WARRANTY The JOHN FLUKE MFG CO INC warrants each instrument it manufactures to be free from defects in material and workmanship under normal use for 2 years from the date of purchase This warranty extends only to the original purchaser This warranty shall not apply to fuses disposable batteries or any product or parts that have been subject to misuse neglect accident or abnormal conditions of operation In the event of failure of a product covered by this warranty JOHN FLUKE MFG CO INC will repair and calibrate an instrument returned to an authorized Service Center within 2 years of the original purchase provided the warrantor s examination discloses to its satisfaction that the product was defective The warrantor may at its option replace the product in lieu of repair With regard to any instrument returned within 2 years of the original purchase said repairs or replacement will be made without charge If the failure has been caused by misuse neglect accident or abnormal conditions of operation repairs will be billed at a nominal cost In such case an estimate will be submitted before work is stated if requested If any failure occurs the following steps should be taken 1 Notify the JOHN FLUKE MFG INC or nearest Service Center giving full
164. 637 CMF556041FT 1 2 R 44 RES 15 4K 12 0 125W 100 719708 91637 CMF 55 1542 T 47 57 84 RES CF 10K 4 55 0 258 212324 59124 CFl 4 103 JB 4 R 48 100 108 1 21 4 18 0 1251 100 719559 91637 55 1211 T 3 R 73 RES 2K 12 0 125W 100 719815 91637 55 2001 T 2 R 50 RES 5 49 13 0 125W 100 720383 59124 555491 53 RES MF 9 31K 1 0 125W 100PP 866285 91637 CMF559311FT R 54 RES MF 3 48K 12 0 125W 100 832071 91637 CMF 55 4802 F T R 55 RES MF 1 5 12 0 125W 100 719682 91637 CMF 55 1501 T 58 RES MF 3 4K 13 0 125W 100 866280 91637 CMF553401FT R 60 61 RES MF 4 02K 1 0 125W 100PP 235325 91637 MFF1 84021F 2 R 62 RES MF 5 9K 13 0 125W 100 267351 91637 CMF 5901 T 1 R 63 RES MF 17 4K 13 0 125W 100 719740 91637 55 1742 T 6 RES 14 76 15 0 125W 100PP 719666 91637 CMF551472FT 65 68 77 RES CF 30K 53 0 251 574251 65940 8259303 4 R 78 574251 R 66 76 RES 9 09K 1 0 125W 100PP 720573 91637 55 9091 T 2 R 67 75 95 RES CF 560 4 52 0 25 573147 59124 CFl 4 561 J 5 R 96 103 513141 R 69 RES CF 1K 5 0 25W 573170 59124 cFl 4 102 JB R 70 RES 31 6K 4 13 0 125W 100PP 720060 91637 CMF 55 3162 T R 1 RES VAR CERM 5K 103 0 51 288282 32997 33865 1 502 R 72 RES 8 06K 13 0 125W 100PP 720524 9163
165. 7 CMF558061FT 1 R 74 RES 48 7K 13 0 125W 100PP 720300 91637 CMF554872FT 1 R 8 RES MF 845 13 0 125W 100 344317 91637 558450 1 R 82 RES VAR CERM 50 10 0 51 285122 32997 33865 1 502 R 83 RES 226 1 1 0 12511 100 866215 91637 CMF552260FT 1 R 85 RES CF 1 5K 53 0 25W 573212 59124 1 4 152 J R 86 RES CF 3 3K 5 0 25W 573287 59124 1 4 332 JB 87 RES CF 22 53 0 25W 572966 59124 21 4 220 J B R 88 91 RES 130 1 15 0 5W 100 151134 91637 CMF651300FT 1 2 R RES 205 12 0 5W 100PP 513960 91637 52050 1 R 90 RES CC 1K 5 0 51 108597 01121 1025 R 9 RES MF 124 4 12 0 125W 100PPM 866194 91637 CMF551240FT 1 An in S column indicates a static sensitive part 7 47 REPLACEMENT PARTS 7 48 REFE DESI 1 1 1 1 1 I UJ 29 UJ ac lt lt lt lt lt lt lt lt lt Table 7 11 11 Modulation Control PCA cont RENCE FLUKE GNATOR STOCK UMERICS 5 DESCRIPTION NO 97 RES 31 6 1 0 125W 100PPM 855247 98 107 RES MF 590 1 0 125W 100PPM 866236 99 101 102 RES VAR CERM 200 10 0 5W 285148 5 RES MF t 1 0 125W 100PPM 720441 06 RES MF 604 1 0 125W 100
166. 8 Section 6F Internal Modulation Oscillator MODULATION OSCILLATOR BLOCK DIAGRAM 6F 1 Refer to the Modulation Oscillator Block Diagram Figure 6F 1 to identify the major functional sections and follow the signal paths of the internal modulation oscillator INTERNAL MODULATION OSCILLATOR CIRCUIT DESCRIPTION 6F 2 The modulation oscillator is configurable as either a direct digital synthesizer DDS or as a pulse generator Both functions are implemented in a custom integrated circuit and are synthesized from the main reference frequency source of the instrument The Mod Oscillator PCA provides two outputs internal modulation source INT MOD modulation output source MOD OUT which is available at the MODULA TION OUTPUT BNC connector at the front panel All power data control and clock signals are received by the Mod Oscillator PCA via a bus connector J1 and clock connector J2 The Mod Oscillator PCA has two outputs INT MOD and MOD OUT Direct Digital Synthesized Wave Generator 6 3 The direct digital synthesizer frequency can be set from 0 1 Hz to 200 kHz with resolution of 0 1 Hz It is the modulation source for the internal FM M and pulse functions The amplitude ofthe internal modulation source INT MOD signal is leveled 1V pk which is internally routed to the Modulation Control PCA A11 The amplitude of the modulation output is controlled by a level DAC The oscillator is based on an algor
167. 8 21 R 9 12 15 R 18 22 R 10 11 13 14 16 17 R 19 20 R 23 26 28 33 35 50 X R 24 29 32 37 R 25 30 31 R 3 R 38 40 43 R 39 R 44 45 R 46 48 R 49 R 51 U 14 5 Table 7 9 A9 Sum we VCO PCA See Figure 7 CAP PORC 1 8PF 0 1PF 50V 0505 2 t 0 1PF 50V 0505 PORC 4 1 0 50V 0505 CAP PORC 3 6PF 4 0 50V 0505 CAP CER 22PF 10 50V COG 1206 100 5 50V 00 0805 3 3PF 4 0 50V 00 0805 CAP CER 8 2PF 4 0 50V C0G 0805 CAP CER 5 6 0 25PF 50V C0G 0805 CAP CER LOPF 5 50V COG 0805 CAP 2 2UF 20 25V CER 3 6PF 4 0 25PF 50V COG 0805 2 0 25PF 50V COG 0805 CAP CER 4 3PF 10 50V C0G 1206 CER 4 7PF 0 25PE 50V COG 0805 CER 6 8PF 50V C0G 1206 1 8PF 0 25 507 06 0805 CAP AL 17018 20 16V SOLV PROOF CAP CER 3 0 SPF 50V C0G 0805 DIODE SI VARACTOR PIV 30V 18PF MLF DIODE 1 50V PIN SWITCHING SOT23 SOCKET SINGLE PWB FOR 042 049 SOCKET SINGLE PWB FOR 0 012 0 022 PIN INDUCTOR 0 18UH 10 770MHZ PIN SINGLE SOLDER 0 059 DIA TRANSISTOR 91 NP SIGNAL FT TRANSISTOR 51 SMALL SIGNAL TRANSISTOR 91 NPN SMALL SIGNAL RES
168. 80 160 320 550 640 700 850 950 and 1024 MHz ALTERNATE LEVEL ACCURACY TEST 4 9 A measuring receiver is used to verify the UUT level accuracy at various amplitude and frequency settings that test all level ranges of the UUT on all RF bands REQUIREMENTS Amplitude accuracy is lt 1 5 dB from 0 5 to 1024 MHz from 13 to 117 dBm 33 0 dB from 0 5 to 1024 MHz from 117 to 137 dBm TEST EQUIPMENT Measuring receiver Sensor module PERFORMANCE TESTS REMARKS This test is a more comprehensive test then the high level mid level and low level accuracy tests If the UUT fails this test the UUT needs to be calibrated Section 3 or repaired Section 6 If the UUT fails this test at higher levels problems with the A8 Output PCA the A21 Attenuator PCA the A7 Relay Driver PCA may be indicated If the UUT fails this test at lower levels a problem with the A21 Attenuator PCA the A7 Relay Driver PCA or an RF leakage problem with the attenuator assembly is probably indicated Check for loose connectors loose screws improper gasketing ora broken feed through filter Because of operational subtleties in measurement receivers and the intent to reduce the risk of measurement errors the following procedure is written around the use of the H P 8902A as the receiver NOTE The calibration factors for the sensor module must be stored into the measurement receiver s Cal Factor tableprior to performing calibrated R
169. 816926 04713 8 000 8 1 0 6 7 5 8 X 8 STAT RAM 120 NSEC 783332 12581 HM6264LP 12 2 0 8 5 8 X 8 STAT RAM 200 NSEC NVM 810804 89536 810804 0 9 IC NMOS 8K X 8 250 NSEC 800243 66419 XL2865AP 250 U 1 IC 16V8 LOG ARRAY 6080 90201 855049 27014 855049 0 12 8 3 LINE PRIORITY ENCODER 556068 01295 SN74148 0 13 IC VOLT SUPERVISOR 4 55V SENSE INPUT 780577 01295 117705 14 IC CMOS DUAL DIV BY 16 BINARY CNTR 741488 04713 MC74HC393 U 15 IC 16V8 LOG ARRAY 6080 90202 855051 27014 855051 0 16 IC CMOS DUAL 4 PUT NAND GATE 854026 01295 SN74HC20N U 17 5 INVERTERS 799924 18324 74 04 0 18 CMOS HEX INVERTER UNBUFFERED 741199 04713 74 004 0 19 IC 74HC05 HEX INVERTER W OPEN DRAIN 854018 01295 SN74HCO05N U 20 5 14 STAGE BINARY COUNTER 807701 04713 74 4020 U 21 IC CMOS DUAL D F F EDG TRG W CLR 741702 04713 MC74HC74N 0 22 IC FTIL QUAD 2 PUT OR GATE 659904 04713 2 0 23 41 42 3 8 LINE DCDR W ENABLE 773036 04713 74 138 4 U 44 713036 U 2425 227 IC CMOS OCTL LINE DRVR W 3 ST OUT 741892 01295 SN74HCT244N 5 32 33 741892 26 IC CMOS QUAD BUS BUFFER W 3 STATE 854021 01295 74HC125N U 28 IC NMOS GPIB TALKER LISTENER CNTRLR 713143 89536 713143 0 29 IC LSTTL OCTAL GPIB XCVR W OPEN COL 585224 01295 SN75160BN 0 30 IC LSTTL OCTAL GPI
170. 8ACJ SOCKET 1 28 PIN 448217 91506 228 AG39D 2 Z 1 RES NET SIP 6 PIN 5 RES 22K 2 520122 91637 CSC06A 01 223G An in S column indicates a static sensitive part 7 34 REPLACEMENT PARTS C26 8 ul 01 0 c a 8 ow 14 8 Eb H6 H Ru C10 C33 16 C26 ce TPS OO cz 2 6080 1602 Figure 7 7 A6 Mod Oscillator PCA 7 35 REPLACEMENT PARTS 7 36 REFERENCE DESIGNATOR A gt NUMERICS gt 5 17 co vois 39 184 217 14 55 45 117 211 213 52 54 56 201 209 66 68 609 172 09 111 114 40 16 126 130 89 70 171 174 210 88 218 94 96 200 201 CAP CER 2700PF 20 CAP POLYES 0 20 CAP CER 4 Table 7 8 A8 Output PCA See Figure 7 8 700 20 100V X7R CAP CER 180PF 5 100V CAP CER 270PF 5 1007 COG CAP CER 330PF 5 100V C0G CAP CER 120PF 2 100V COG CAP CER 200 5 50V COG CAP CER 82PF 2 100V C0G CAP CER 150PF 2 100V C0G CAP CER 96PF 2 1007 C0G CAP 100
171. 943 All DACS to full scale The reading should be 26 00V 3 Program the UUT to SPCL 942 All DACs to half scale The reading should be 13 00V This tests the VCO steering voltage circuit 6C 45 TROUBLESHOOTING AND REPAIR FREQUENCY SYNTHESIS 6C 46 4 With J6 still grounded examine the generator output with a spectrum analyzer as frequency is stepped in the range from 512 to 1056 MHz The frequency should always be within about 2 MHz of programmed frequency Note that the output section can be bypassed by examining the signal at VCO output J7 with a 500 ohm probe grounding the probe nearby The level at this point is about 14 dBm If the signal is good the problem is likely in another PCA If the signal is faulty only over a frequency band corresponding to one of the VCO bands the associated VCO circuit is likely at fault If the VCO appears to be faulty DC voltages can be measured at various circuit nodes with the UUT programmed to frequencies corresponding to the four VCO bands UUT frequencies of 600 700 800 and 900 MHz will enable each of the four bands Refer to Table 6C 12 for expected approximate voltage measurements These measurements should help isolate the faulty circuit Table 6C 12 A9 Sum Loop VCO PCA Expected DC Voltages LOCATION VOLTS DC ON bias transistor collector Q5 Q6 Q7 or Q8 depends on band 144 OFF bias transistor collectors 0 ON oscillator transistor collector Q1 Q2 Q3 or Q5 d
172. 999999 MHz 32 to 63 999999 MHz 64 to 127 999999 MHz 128 to 255 999999 MHz 256 to 511 999999 MHz 512 to 1024 MHz 1Hz Same as reference See REFERENCE The unit operates on an internal 10 MHz Temperature Compensated Crystal Oscillator TCXO The frequency variation will be 10 ppm peak to peak over the temperature range of 0 to 50 C Internal reference signal 10 MHz available at rear panel REF OUT connector level gt 0 dBm terminated into 50 ohms Frequency stability after 2 hour warmup is lt 0 05 ppm hour at 25 C 5 C Accepts 5 or 10 MHz signal Level required is 0 5 to 2 0V RMS into 50 ohms termination 13 to 137 dBm 0 1 dB lt 1 or 1 nV in Volts Annunciators for dB dBm V mV uV dB dB dBf EMF 1 5 dB from 13 to 117 dBm 3 dB from 117 to 137 dBm 1 5 1 for levels below 10 dBm lt 2 5 1 elsewhere 1 0dB 10dBm INTRODUCTION AND SPECIFICATIONS Table 1 3 6080A AN Specifications cont SPECTRAL PURITY CW ONLY NON HARMONIC 5 5 lt 100 dBc for offsets greater than 15 kHz NOTE Fixed frequency spurs are lt 100 dBc or lt 140 dBm whichever is larger NOTE dBc refers to decibels relative to the carrier frequency orin this case relative to the signal level HARMONICS SUBHARMONICS lt 30 dBc for levels lt 7 dBm POWER LINE 5 05 lt 40 dBc within 15 kHz of c
173. A MANUFACTURER S FEDERAL SUPPLY CODES 55680 Nichicon America Corp Schaumburg IL 56289 Sprague Electric Co North Adams MA 57693 Oscillatek Corp Olathe KS 59124 KOA Speer Electronics Inc Bradford PA 59365 Metelics Corp Sunnyvale CA 60705 Cera Mite Corp formerly Sprague Grafton WI 60935 Westlake Capacitor Inc Tantalum Div Greencastle IN 61058 Matsushita Electric Corp of America Panasonic Industrial Co Div Secaucus NJ 61271 Fujitsu Microelectronics Inc San Jose CA 61752 IR ONICS Inc Warwick RI 61804 M A Com Inc Burlington MA 62643 United Chemicon Rosemont IL 64155 Linear Technology Milpitas CA 65940 Rohm Corp amp Whatney Irvine CA 65964 Evox Inc Bannockburn IL 66419 Exel San Jose CA 66675 Lattice Semiconductor Corp Hillsboro OR 68919 WIMA Harry Levinson Co Seattle WA 7E751 Avantek Inc Santa Clara CA 70903 Cooper Belden Corp Geneva IL 71034 Bliley Electric Co Erie PA 71400 Bussman Manufacturing Div McGraw Edison Co St Louis MO 71450 CTS Corp Elkhart IN 71590 Mepco Centralab A North American Philips Co Fort Dodge 72259 Nytronics Inc New York NY 72962 Elastic Stop Nut Div of Harrard Industries Union NJ 72982 Erie Specialty Products Inc formerly Murata Erie Erie PA 73734 Federal Screw Products Inc Chicago IL 74840 Illinois Capacito
174. A and the voltage to current converter U62 and 012 TROUBLESHOOTING AND REPAIR FREQUENCY SYNTHESIS LOOP AMPLIFIER The loop amplifier integrator consists of operational amplifier U34 C98 and R44 Capacitors C97 and C102 filter the 1 MHz reference The output of the integrator is connected to a multi pole LC filter R45 C104 C105 C106 C107 L56 L57 and R48 that attenuates the delete rate 10 and 20 kHz and reference 1 MHz spurs Diodes CR12 13 CR14 CRI5 CR22 and CR23 speedup the loop during switching Additional lead lag compensation is provided by C114 C115 R58 and R59 The second lead lag network is switched by Q10 when the VCO frequency is above 230 MHz This is necessary to compensate for the wide Kv range ofthe VCO Amplifier U35 is a precision clamp to keep the VCO frequency within a specified range The photoisolator U36 detects when the clamp is active indicating an out of lock condition This signal is sent to the controller as the SUBUNLKL status LOW ORDER DIGITS GENERATOR The low order digits generator consists ofthe clock generator U21 U22 Q1 Q2 the gate array U23 the divide by 1000 060 U61 the low pass filter L75 1 76 and the active quadrature generator 059 Internal to the gate array U23 is a 3 decade rate multiplier associated latches and a divide by 2 The 40 MHz reference from the Coarse Loop is converted to ECL in 020 and then converted to TTL in Ql and Q2 This is followed
175. ACS to full scale 3 Connect the DVM to measure the voltage between TP8 and ground TP14 4 Adjust R221 for 24 00V x 01V 5 Program the UUT for SPCL 00 This clears all Special Functions Acquisition Oscillator Level Adjustment R227 6 20 TEST EQUIPMENT REMARKS The Acquisition Oscillator Level adjustment is normally required only when U206 or any associated components have been replaced or when the adjustment has shifted PROCEDURE Acquisition Oscillator Level at TP6 is adjusted for 3 54V RMS with the phase locked loop disabled 1 Connect TP11 to ground TP13 with a clip lead 2 Connect the DVM to measure the AC voltage between TP6 and ground 3 Adjust R227 for 3 54V RMS 40 MHz Oscillator Adjustment L601 6C 21 TEST Equipment Frequency counter DVM 6C 28 TROUBLESHOOTING AND REPAIR FREQUENCY SYNTHESIS REMARKS The 40 MHz Oscillator Adjustment is normally required only when Q606 or any associated components are replaced or when the adjustment has shifted PROCEDURE The 40 MHz Oscillator is adjusted to 40 MHz with the crystal removed from the circuit 1 Program the UUT to SPCL 909 and select internal reference 2 counter external reference OUT to UUT 10 MHZ IN Set UUT to EXT 3 Move the two on board jumpers from TP22 TP24 to TP22 TP23 and from TP26 TP27 to 25 26 This removes the crystal from the circuit 4 Connect the frequency counter to Set for 1 kHz
176. ATING 508077 61804 4P523 503 ZENER UNCOMP 9 17 58 14 OMA 0 41 386557 04713 119608 CR 508 ZENER UNCOMP 12 01 55 10 5 0 4 249052 14552 IN963B CR 603 605 DIODE SI VARACTOR PIV 28V 741504 25403 BB405B 4 11 16 SOCKET SINGLE PWB FOR 042 049 866764 00779 645991 3 40 CONN COAX SMB PWB OR PANEL 512095 16733 102033 gu D SOC ET SINGLE FOR 0 012 0 022 PIN 376418 22526 75060 012 L 201 202 503 DUCTOR 0 6805 10 221MHZ SHLD 320937 24759 MR 0 68 L 506 609 614 320937 L 203 DUCTOR 2 209 4 55 108MHZ SHLD 806547 24159 MR 2 2 L 204 502 DUCTOR 10UH 10 53MHZ SHLD 249078 24759 MR 10 L 205 DUCTOR VARIABLE 14UH 812792 89536 812792 L 206211 3 1 CHOKE 6TURN 320911 89536 320911 L 507 518 602 320911 L 401 402 405 DUCTOR 10 TURNS 463448 89536 463448 L 406 463448 L 501 DUCTOR 0 82UH 10 200MHZ SHLD 320945 24759 MRO 82 L 510 DUCTOR 5 6UH 5 69MHZ SHLD 867056 24759 MR 5 6 L 601 DUCTOR VAR 0 40209 1 55 SHLDED 854646 02113 142 107085 L 603 DUCTOR 308 108 140 HZ 854612 91637 IM 21 5UH10 L 604 605 DUCTOR 0 2208 10 510MBZ 854604 91637 IM 2 22UH10 L 606 DUCTOR 0 3309 5 410MHZ 854992 91637 1 2 31 330 55 L 611 615 DUCTOR 0 3909 10 365MHZ 854596 91637 IM 2 39UH10 L 607 CORE TORO D FERRITE 047X 138X 118 321182 02114 56 590 65 4 L 612 613 DU CTOR VAR 0 070UH 11 854591 02113 150 02208 1 30 SOCKET SI GLE FOR 042
177. Adjust R140 for 8901A reading of 200 kHz 1 kHz Adjust R117 for symmetrical plus and minus readings about 200 kHz 1 kHz Repeat until both specs are met Set the UUT to 50 MHz 5 kHz mod rate 200 kHz dev INT Set the 8901A to peak 300 Hz HP 15 kHz LP Adjust R139 for a 8901A reading of 200 kHz 1 kHz Adjust R115 for symmetrical plus and minus readings about 200 kHz 1 kHz Repeat until both specs are met Set the UUT to 800 MHz 70 Hz mod rate 5 rad dev INT ACFM Set the 8901A to M peak 15 kHz LP all other filters removed Avg and 70 7 Adjust R145 for 5 rad Set the UUT to 800 MHz 10 kHz mod rate 5 rad dev SPCL 721 INT ACFM Set the 8901A to M peak 300 Hz HP gt 20 kHz LP Adjust C75 for 8901A reading of 5 rad Set the UUT to 1 kHz mod rate The 8901A reading must be 5 rad 05 rad Set the UUT to 800 MHz 70 Hz mod rate 5 rad dev SPCL 721 INT ACFM Set the 8901A to M peak no filters Avg and 70 7 Adjust R146 for 5 rad Set UUT to SPCL 720 Connect the 8840A to TP12 and adjust R49 to 0V DC Connect the 8840A to TP9 Verify that the 8840A reads between 3V DC and 10V DC Set the UUT to SPCL 909 800 MHz 5 dBm mod freq 10 Hz 25 kHz FM deviation SPCL 711 SPCL 752 Set the spectrum analyzer to IP center freq 800 06 MHz span 100 kHz ref level 5 dBm resolution bandwidth 30 kHz video bandwidth 30 kHz sweep time 200 ms log scale 6 dB trigger free run Set
178. Asymmetrical sweep Sweep speed Sweep width and sweep increment Minimum 30 ms per increment selectable as mini mum dwell time where dwell time can be 0 20 50 100 200 or 500 ms at each increment to 10 10 Up to 4096 points in a stepped ramp Load gt 2 TTL high for retrace Load gt 2 O to 50 C 32 to 122 F 40 to 75 C 40 to 167 F 95 to 30 C 75 to 40 and 45 to 50 C Up to 10 000 ft 5 to 15 Hz at 0 06 inch 15 to 25 Hz at 0 04 inch and 25 to 55 Hz at 0 02 inch double amplitude DA Per MIL T 28800D Class 5 Style E INTRODUCTION AND SPECIFICATIONS Table 1 4 Typical Signal Generator Performance cont ELECTROMAGNETIC COMPATIBILITY The radiated emissions induce lt 1 uV into a 1 inch diameter 2 turn loop 1 inch from any surface as measured into a 50 ohm receiver COMPLIES WITH THE FOLLOWING STANDARDS of MIL STD 461B Power and interconnecting leads 0 015 to 50 MHz REO2 of MIL STD 461B 14 kHz to 10 GHz FCC Part 15 J class A CISPR 11 SIZES xm Width Height Depth 43 cm 13 3 cm 59 7 cm 17 in 5 25 in 23 5 in 115 230 10 50 60 amp 400 Hz 10 lt 250 VA WEIGH Titan 27 kg 60 lbs SUPPLEMENTAL CHARACTERISTICS The following characteristics are provided to assist in the applicat
179. B ACTV PULL UP XCVR 585232 01295 5 751618 0 31 5 OCTAL BUS TRANSCEIVER 722017 18324 74HCT245N 34 38 39 IC CMOS OCTAL D F F W RESET 743286 18324 N74HCT273N 3 U 35 37 45 5 D TRANSPARENT LATCH 743294 01295 SN74HCT373N 4 0 40 IC ARRAY 7 TRANS NPN DARLINGTON PAIRS 454116 01295 ULN2003AN 0 43 5 QUAD 2 INPUT OR GATE 817312 04713 MC74HC32N XU 1 SOCKET IC 64 PIN 483842 00779 643575 3 XU gt 5 SOCKET IC 32 PIN 807156 00779 2 644018 3 4 XU 6 10 SOCKET IC 28 PIN 448217 91506 228 AG39D 5 XU 11 15 SOCKET 1 20 PIN 454421 00779 2 640464 1 2 XU 28 SOCKET IC 40 PIN 429282 00779 2 640379 1 Y 1 CRYSTAL 8 00MHZ QUARTZ HC 18U 707133 89536 707133 2 1 11 M RES 1 10 PIN 9 RES 4 7K 2 484063 91637 5 10 014726 17 72521523 484063 An in S column indicates a static sensitive part 7 54 REPLACEMENT PARTS Table 7 13 A13 Controller PCA cont N REFERENCE FLUKE MFRS MANUFACTURERS 0 DESIGNATOR STOCK SPLY PART NUMBER TOT T 5 DS CODE OR GENERIC TYPE QTY E Z Z 12 16 19 RES NET SIP 6 PIN 5 885 4 7 4 25 494690 91637 CSC06B01472G 3 Z 20 24 RES NET DIP 16 PIN 8 RES 120 5 448423 91637 16 03 1210 2 An in S column indicates a static sensitive part 7 55 REPLACEMENT PARTS 212 o E 044112 023 m 02 033 025 035 037 IN N N N 015 012
180. C coarse loop steering DAC sum loop compensation DAC sum loop steering DAC sub synthesizer compensation DAC the Output assembly and the Attenuator assembly In addition the AM FM level and reference oscillator calibration data is stored there Since the integrity ofthis data is crucial to the performance of the signal generator redundant copies of the data are kept in two separate non volatile memory ICs Hardware and software protection schemes guard against accidental destruction ofthe data The rear panel switch labeled CALICOMP must be set to the ON position before updating the calibration compensation memory The calibration compensation memory self test verifies the CRC checksums of each data segment A detailed report of the compensation memory status can be interrogated from the front panel or the IEEE 488 interface If errors are detected by the selftest the signal generator uses only the valid data segments See Appendix F for more information on the compensation memory status codes Self Test 2 18 At power on the signal generator automatically tests the digital and analog circuits If the signal generator fails any self test the test results are automatically displayed as error codes Several special functions are available for additional tests See SELF TEST DESCRIPTION in Section 6 In addition the microprocessor continuously monitors hardware status signals Status Signals 2 19 The status of the rear panel R
181. C 39 is highly recommended prior to troubleshooting Status code 244 indicates that the sum loop is not properly phase locked and is triggered by the free running loop acquisition oscillator This fault condition can be caused by either a problem with the input signals to the sum loop or by a problem in the A12 Sum Loop or the A9 Sum Loop VCO PCA A faulty input signal from either the Coarse Loop the Sub Synthesizer or the FM assembly could result in sum loop unlock First check for status codes that indicate faulty operation of the Sub Synthesizer PCA the Coarse Loop PCA and the FM PCA Repair any indicated assemblies and check whether Status Code 244 still appears If it does check that the following three input signals have the correct frequency and level The FM signal is measured using a 500 ohm probe with the spectrum analyzer while the coarse loop and sub synthesizer cables are detached from the Sum Loop PCA and are connected to the spectrum analyzer directly Note that for any UUT frequency the expected coarse loop and sub synthesizer frequencies can be displayed by entering SPCL 946 and SPCL 947 respectively SIGNAL DESCRIPTION TEST LOCATION FREQUENCY LEVEL Coarse Loop Cable W14 Use SPCL 946 7 dBm FM TP14 80 Mhz 13 dBm Sub Synthesizer Cable W13 See equations below 3 dBm Or use SPCL 947 For f sum lt 760 Mhz f in Mhz f sub synth 2 f coarse 80 f sum For f sum gt 760 Mhz f in Mhz f sub synth
182. CA Table 6D 5 Attenuator Levels ATTENUATOR PROG LEVEL SPECIAL FUNCTION OBSERVED LEVEL NOMINAL 6 dB 6 dBm 6 dBm 12dB 0 dBm 0 dBm 24 dB 1 12dBm 12dBm 24 dB 2 12dBm 923 12dBm 24 dB 3 12dBm 924 12dBm 24 dB 4 12dBm 925 12dBm 24 dB 5 12dBm 926 12dBm 6D 21 TROUBLESHOOTING AND REPAIR RFLEVEL AM 6D 22 Table 6D 6 Attenuator Level Control ATTENUATOR SECTIONS INSERTED AMPLITUDE RANGE IN DBM CW INDICATED BY X A12DB A241 A242 A243 A244 A245 7 0to 20 0 1 010 6 9 x 5 010 0 9 11 0 to 5 1 17 0 to 11 1 23 1 to 17 1 X X 29 1 to 23 2 35 1 to 29 2 X 41 1 to 35 2 X X 471 to 41 2 X X X 53 2 to 47 2 x X 59 2 to 53 3 X X X X 65 2 to 59 3 X X X 71 210 65 3 77 2 to 71 3 X 83 3 10 773 x X X 89 3 to 83 4 X X X X 95 3 to 89 4 X X 101 3 to 95 4 X X X X X 107 4 to 101 4 X X X X X 113 4 to 107 5 X X X X X 119 4 to 113 5 125 4 to 119 5 X X X 147 0 to 125 5 X X X X X X X Section 6E Frequency and Phase Modulation FM oM FAULT TREE 6E 1 The 0 Fault Tree Figure 6E 1 is the starting point for troubleshooting problems MODULATION 241 307 319 247 249 337 338 302 AM 241 307 309 See Paragraph 6D 1 thru 6D 23 247 310 319 See Section 6E MOD OS
183. CAL SERVICE CENTERS U S Service Locations California Fluke Technical Center 16969 Von Karman Avenue Suite 100 Irvine CA92714 Tel 714 863 9031 Fluke Technical Center 46610 Landing Parkway Fremont CA 94538 Tel 415 651 5112 Colorado Fluke Technical Center 14180 East Evans Avenue Aurora CO 80014 Tel 303 695 1171 Florida Fluke Technical Center 940 N Fern Creek Avenue Orlando FL 32803 Tel 407 896 4881 Illinois Fluke Technical Center 1150 W Euclid Ave Palatine IL 60067 Tel 312 705 0500 Maryland Fluke Technical Center 5640 Fishers Lane Rockville MD 20852 Tel 301 770 1576 New Jersey Fluke Technical Center East 66 Midland Avenue Paramus NJ 07652 0930 Tel 201 599 9500 Texas Fluke Technical Center 1801 Royal Lane Suite 307 Dallas TX 75229 Tel 214 869 2848 Washington Fluke Technical Center John Fluke Mfg Co Inc 1420 75th St S W M S 6 30 Everett WA 98203 Tel 206 356 5560 International Argentina Coasin S A Virrey del Pino 4071 DPTO E 65 1430 CAP FED BuenosAires Tel 541 522 5248 Australia Philips Customer Support Scientific and Industrial 23 Lakeside Drive Tally Ho Technology Park East Burwood Victoria3151 Australia Philips Customer Support Scientific amp Industrial 25 27 Paul St North North Ryde N S W 2113 Tel 61 02 888 8222 Austria Oesterreichische Philips Industrie Unternehmensbereich Prof Systeme
184. CAL annunciator remains lit during the procedure When the switch is in the 0 OFF position the data is write protected in hardware The calibration data can be generated in one of two ways by the Fluke factory or by the user Each calibration data segment contains a data origin tag which specifies how the data was created Special function 05 displays the calibration and compensation data origin codes If no user calibration or compensation procedures have been performed the special function displays origin code 00 to signify that all of the data originated at the Fluke factory If any user calibration procedures have been performed the corresponding code is displayed For example if the AM calibration procedure has been performed by the user the data origin special function will display the code 528 A complete list of the data origin codes is given in Appendix F 3 3 CLOSED CASE CALIBRATION 3 4 AM CALIBRATION 3 5 The AM calibration procedures allow a single point calibration ofthe AM depth to be performed An RF modulation meteris connected to the 6080A AN s RF output and the AM calibration factor is adjusted based on the meter reading The procedure specific parameters are as follows Adjustment Range 5 AM Depth Adjustment Resolution 0 196 Target Value 50 096 RF Frequency 300 000000 MHz RF Level 10 0 dBm Internal AM ON Modulation Frequency 1 kHz External Equipment RF Modulation Analyzer HP 8901 or eq
185. CILLATOR No Status or ErroR Codes ChecK MOD OSC OUT Check INT vs EXT Modulation See Section 6F PULSE MODULATION 337 338 See Paragraph 6D 1 thru 6D 26 If 302 try SPCL 04 Then Codes 408 409 428 429 Imply Latch Problems Cal Comp Memory Problems Related To Modulation Figure 6E 1 FM gM Fault Tree 6E 1 TROUBLESHOOTING AND REPAIR FREQUENCY AND PHASE MODULATION 6E 2 BLOCK DIAGRAM 6 2 Refer to the FM gM Block Diagram Figure 6E 2 to identify the major functional sections and in follow the signal paths of the FM section FM OM CIRCUIT DESCRIPTION 6 3 The A14 has a phase locked loop that consists of the following e Voltage controlled 80 MHz oscillator with a modulation port a control port and a presteering section Programmable dividers for reference and variable frequencies e Selectable phase detectors normal and wide range loop amplifier and filter circuitry and logic circuitry Modulation section with both high modulation rate path and low modulation rate path Incorporated in the different sections are logic and controls for achieving frequency modulation normal and low rate and phase modulation normal and high rate Also the function of DC frequency modulation is included The FM modulation deviation is 4 MHZ maximum which is covered in six ranges Equivalent phase modulation ranges exist for 400 Radians maximum 40 Radians max
186. D WARNING PIVOTING MODULE INSTRUCTIONS IF NECESSARY DURING REPAIRS PIVOT THE TOP SYNTHESIZER MODULE UP TO ALLOW ACCESS TO ALL PARTS OF THE SIGNAL GENERATOR THE MODULE IS HEAVY AND CARE SHOULD BE EXERCISED THE GAS STRUT IS PROVIDED FOR PROTECTION CHECK THE CORRECT OPERATION OF THE GAS STRUT BY NOTING THE RESISTANCE TO RAPID CLOSING OF THE MODULE WHILE YOU FIRMLY GRASP THE MODULE BY THE HANDLE OPENING AND CLOSING INSTRUCTIONS ARE GIVEN BELOW AND ARE REPEATED ON THE DECAL ON THE TOP FRONT OF THE SYNTHESIZER MODULE RAISING THE MODULE 1 REMOVE THREE HOLD DOWN SCREWS LOCATED ON THE SIDE RAILS 2 GRASP THE HANDLE AND LIFT UP 3 LOCK IN THE UP POSITION BY INSTALLING ONE SCREW IN THE PROTRUDING BOSS ON EACH SIDE RAIL LOWERING THE MODULE 1 SUPPORT IN THE UP POSITION AND REMOVE TWO LOCK UP SCREWS 2 GRASP THE HANDLE AND LOWER THE MODULE KEEPING YOUR HANDS CLEAR 3 LOCK IN THE DOWN POSITION BY REINSTALLING THE THREE HOLD DOWN SCREWS INTRODUCTION AND SPECIFICATIONS ACCESSORIES 1 4 The accessories and manuals included with each signal generator are listed in Table 1 1 The optional accessories available are listed in Table 1 2 SIGNAL GENERATOR SPECIFICATIONS 1 5 Table 1 3 lists the 6080A AN specifications Table 1 4 lists typical performance characteristics Table 1 1 Accessories Included with each Signal Generator DESCRIPTION PART NUMBER QUANTITY Operator Manual 857748 1 Service Manual 868906 1 Li
187. DT4423F R RES CF 1M 5 0 25W 649970 59124 CF1 4105J VT R 97 RES CF 5 1K 5 0 25W 866723 59124 CF1 4VT512J 1 98 101 RES 7 5K 1 0 125W 100 866660 59124 MF50VDT7501F 2 R RES CF 4 7M 5 0 25W 866731 59124 CF1 4VT475d R 100 RES CF 1 2M 5 0 25W 866728 59124 CF1 4VT125d R 102 RES VAR CERM 200 20 0 5W 226050 80294 3329H 1 201 R 103 144 RES 887 1 0 125W 100PPM 866652 59124 MFSOVTD8870F 2 R 4 RES VAR CERM 2 ub 5W 215743 3299 33868 1 201 R RES MF 2 15K t 12 0 1251 100PPM 866699 59124 MF50VDT2151F R 106 109 135 RES CF 470 4 55 0 251 2 59124 1 4 4710 4 R R 114 RES MF 3 01K 1 0 125W 100PPM 866694 59124 MFSOVDT3011F R 115 RES VAR CERM 5K 4 205 0 51 226084 80294 3329H 1 502 R 116 RES CF 82K 4 55 0 250 655027 59124 CF1 4 VT823d R 118 RES MF 15K 1 1 0 125W 100PPM 866702 59124 MF50VDD1502F R 120 RES MF 549 15 0 1250 100 820332 59124 MF50VTD549F R 121 RES CF 12K 5 0 25W 751199 59124 CF1 4VT123J R 124 142 RES CF 330K 4 55 0 251 866707 59124 CF1 4VT334J 2 R RES 49 9 4 13 0 125W 100PPM 820266 59124 MF50VTD4992F R 129 131 132 RES CF 200 1 55 0 251 573055 59124 CF1 4 201 J B 3 R 133 RES MF 499 1 0 125W 100PPM 816462 91637 CMF554990FT 1 R 134 RES MF 634 1 1 0 125W 100PPM 223560 91637 CMF556340FT 1 R 138 RES CF 5 0 25W 810366 59124 CF1 4VT302J R 139 141 RES VAR CERM 100 10 0 5W 275735 32997 3386R OT1 101
188. DULATION 6E 12 6E 13 Use Table 6E 3 as a guide to check the performance ofthe FM oscillator for faults in frequency lock Note the relationship between the modulation frequency and the NOTE Set SPCL to 909 Freq to 800 MHz Have EXT FM input equal zero FM DEV FREQ VOLTS DC DIVIDER FREQUENCIES DETECTOR EXT FM MHz TP11 TP12 TP2 TP 5 15 6 8 021 Off 80 15 0 0 22 63 04 5 MHz Std 021 50 kHz 80 15 0 0 22 63 0 200 kHz 200 kHz Std U21 100 kHz 80 15 0 0 22 63 0 1 50 kHz NPI 011 23 400 kHz 80 7 0 0 11 6 3 0 1 50 2 NPI U11 23 TP 5 15 positive pulses TP 6 8 negative narrow pulses Tolerances 2 11 12 5V 4 01 V 2 1 Ifthe frequency is wrong check the adjustment of oscillator frequency L1 and C9 2 Ifthe voltages are wrong TP11 TP2 check the steering circuit US 3 Ifthe divider frequencies are wrong check the dividers and input drive levels 4 Ifthe phase detector output at TP12 is high or low check the phase detectors U11 or 021 and current sources 723 and 050 or 010 011 circuits 5 Check low rate modulation path Op Amp U38 should have a zero volt on junction of pin and C70 6 Check CMOS switches U32 35 36 39 43 47 for proper control voltages 7 Check associated CMOS switch drivers Use the Modulation Control Table Table 6E 1 for logic information For U36 39 43 47 V on gt 10
189. Diagnostic Tests laterin Section 6B Microprocessor Bus 6B 19 The dynamic nature of the microprocessor bus makes it difficult to verify the data transmitted at any given time However most common bus faults show recognizable symptoms and can be found with the aid of the address bus diagnostic test To initiate the bus diagnostic test turn offthe instrument power and set DIP switches 2 3 and 4 of S1to the on position Remove U11 from its socket to disable all memory and I O chip selects then turn the power on This test generates predictable activity on the control signals and the address bus Look at the bus control signals AS R W UDS LDS with an oscilloscope Suspect inactive signals or signals that enter invalid logic states Also compare the inputs and outputs of gated signals All the address bus signals should have square waves of varying frequencies The least significant signal A1 has the highest frequency and successively higher order signals have a frequency halfthat ofthe previous line Note that there are small glitches on all ofthe address signals during the low cycle These are normal and are not really glitches The address lines are momentarily tri stated between bus cycles and the pull up resistors only pull the signals part way up before the next bus cycle begins If the microprocessor bus test does not function as described suspect the micro processor kernel and the data bus Check for data lines shorted toge
190. E Adi 20 Noa 9015 n pO 1031409 T we T 1111 1 33HA 01901 ALSH 100 318VN3 Avet 100 en AS8QNVLS At 2 Figure 6 1 Power Supply Block Diagram 6A 2 TROUBLESHOOTING AND REPAIR POWER SUPPLY Table 6A 1 Supplies Provided by Power Supply Assembly VOLTAGE SUPPLY 24V DC Fan and Attenuator 23V DC Oven and Front Panel Standby Supply 5V DC Logic 15V DC Positive Analog 15V DC Negative Analog 37V DC Front Panel Display 30V DC High Voltage Analog 6V AC Display Filament Lines The 24V 23 4V 5V 37V and the 30V supplies use conventional three terminal IC regulators with internal current limit and temperature protection The two highest power regulators 5 and 15V are of a very low noise low ripple design that uses a high gain low noise amplifier 01 in a closed loop circuit with high current Sense FET transistors Q1 and Q2 An over current protection is provided to both the 5 and 15V supplies via the Sense FET series pass element s Q1 Q2 internal current mirror in conjunction with the differential amplifiers U2 When the load current set by R6 or R18 exceeds the the zener diodes CR5 or 9 turn on triggering the gate of the SCR Q4 This in turn sets pin 5 of comparator U3 below its threshold voltage set by R19 and R22 which sets the adjust terminal of the 37V
191. E SI SCHOTT Y BARRIER SMALL SIGNL 313247 CR 24 313247 CR 18 19 25 DIODE SI BV 75 0V 10 150MA 500MW 698720 CR 26 698720 CR 27 28 30 DIODE SI BV 75 0V RADIAL INSERTED 659516 CR 32 A 659516 CR 33 DIODE 51 BARRIER SML SGNL 313247 CR 35 ZENER 5 1 55 20 0 41 866772 CR 36 ZENER UNCOMP 9 17 55 28 1 01 459917 J 56 SOCKET SINGLE PWB FOR 042 4049 866764 7 7 866764 J 3 SOCKET SINGLE 0 012 0 022 PIN 376418 K 1 72 RELAY REED 1 FORM A 5VDC 461434 n MFRS SPLY CODE OR GENERIC TYPE 62643 71590 40402 in S column indicates a static sensitive part MANUFACTURERS PART NUMBER SM 35 VB 100 R569C13U2JHWHAP MKT1823104056 RPE12290706102J50V 10 8052 C315C560G1G5EA C320C561J5G5EA 96D826X00200MA3 110 06 SR201A101GATR 96D686X0015LA3 99D106X0050EA3 99D686X5025EA3 C320C271J1G5EA SR215A332JAT 960156 0020 4 330 2024565 85 85 01 005 0 8 183047101 85 2 022 10050 SR291A331JATR FKP2222F100V 1830472064 199D226X1016DA1 T361B226M025AS 196D106X0035PE4 86 RPE121911C0G470G1 JF86 J1320R47 FKP2681F100V TZ03R121FR174 96D105X0035HA1 990106 0020 2 SR291A820GATR 990226 0010 1 C320C182J5G5EA 99D336X9006CE2 BB405B BA483 N4578A 5082 6264 125 448 448 5082 6264 125 N751ARR1 028709 TAPE REEL 645991 3 75060 012 203 0085
192. ED UNDER THE HEADING INTRODUCTION AND SAFETY EARLIER IN SECTION 5 Disconnect RF cables W13 and W14 from the connectors at the front edge of the output module and remove the nuts and lockwashers from the connectors Raise the synthesizer module Remove the 6 screws holding the top output module cover and remove the cover The 10 screws are adjustment access screws and need not be removed Disconnect the FM Sum Loop ribbon cable W32 from the 12 Sum Loop PCA Remove the plug in capacitor C2 between the 12 Sum Loop PCA and the 14 FM PCA Remove the 6 screws holding the Sum Loop lid and remove the lid Remove the 6 screws holding the PCA Carefully remove the 12 Sum Loop PCA Removing the A13 Controller PCA 5 16 d SQ 199 Y A WARNING THE SYNTHESIZER MODULE WHICH MUST BE RAISED TO GAIN ACCESS TO THE A13 CONTROLLER PCA IS HEAVY WHEN RAISING OR LOWERING THE MODULE OBSERVE THE PROCEDURE DESCRIBED UNDER THE HEADING INTRODUCTION AND SAFETY EARLIER IN SECTION 5 Raise the synthesizer module Remove the 6 screws holding the top output module cover and remove the cover The 10 screws are adjustment access screws and need not be removed Disconnect the front panel display ribbon cables W18 and W36 from the A13 Controller PCA Disconnect the IEEE ribbon cable W17 from the A13 Controller PCA Disconnect the Controller Synthesizer ribbon cable W16 from the A13 Controller PCA Disconnect the
193. EF EXT INT reference switch is continuously monitored The state ofthis switch is used to display the EXTREF annunciator on the front panel and to program the reference source The RF output of the signal generator is considered usable but not necessarily calibrated unless the STATUS indicator is flashing The STATUS indicator flashes when the output of the instrument is considered unusable because of a severe overrange condition or a circuit failure 2 7 2 8 Section 3 Closed Case Calibration INTRODUCTION 3 1 The closed case calibration procedures allow the RF level AM depth FM deviation and the internal 10 MHz reference oscillator to be calibrated without removing the instrument covers The calibration procedures can be performed at the specified 2 year calibration intervals or whenever one wishes to optimize the performance of the 6080A AN Synthesized Signal Generator The procedures can be performed from the front panel or remotely under the control of an IEEE 488 bus controller Each procedure consists of the following steps Setthe rear panel CALICOMP switch to the 1 on position 2 Initiate the calibration procedure 3 Connect the required measurement equipment to the signal generator s RF output 4 Adjust the parameter of interest until the meter reading matches a predetermined target value 5 Store the updated calibration factor Although these procedures are useful for periodic calibration they cannot corre
194. EL INDUCTOR 0 1809 10 770MHZ PIN SINGLE PWB 0 025 80 TRANSISTOR SI NPN SM SIGNAL HI FT TRANSISTOR 1 NPN SMALL SIGNAL TRANSISTOR SI NPN SMALL SIGNAL RES 470 5 0 25W RES CF 200 5 0 25W RES CERM 120 5 125W 200PPM 206 RES CERM 47 5 125W 200PPM 1206 RES 100 5 0 251 RES 160 5 0 251 RES MF 10K 125W 100 RES 58 0 251 RES CF 15 455 RES 150 55 125W 200PPM 1206 IC BPLR MONOLITHIC MICROWAVE AMP IC COMPARATOR QUAD 14 PIN SOIC o OC1O01O0101C01C01 00 854567 810390 810390 146305 146305 746263 746263 810465 854724 658914 854510 854562 746313 773218 141561 MFRS SPLY MANUFACTURERS PART NUMBER CODE OR GENERIC TYPE 51406 51406 04222 05397 MA181R8B MA182R7B 1206 220 ATOSOR 0805 101056 1990225 0025 1 GRH708C0G4R7C200VPT GRH708COGSR6C200VPT 08055 331 060 VJ0805Q8R2DXAT 08055A3R6CAT051B GRH708C0G2R7C200VPT 1 0471 KM63VB10RM5X11RP BB215 BA885 645991 3 2 332010 1 2985 6011 5 5087227 213 1623 1 NE21935D 12895 NE02135 D 2N3904RLRA2 CF1 4VT471d CF1 4VT201J 13B 2BJ121B 1382BJ470B F1 4VT101J F1 4VT161J 02 15000 802 in S column indicates static sensitive part m Wow DWa CO
195. ENERAL DYNAMICS POMONA DIV Dow Chemical Page 2 of 2 A complete line of static shielding bags and acces sories is available from Fluke Parts Department Telephone 800 526 4731 or write to JOHN FLUKE MFG CO INC PARTS DEPT 5 86 9028EVERGREENWAY EVERETT WA 98204 J0089D 07U8604 SE EN Litho in USA Rev 1 MAR 86 Section 5 Access Procedures INTRODUCTION AND SAFETY 5 1 Section 5 describes the general access procedures forthe following major assemblies Front Panel Section Rear Panel Section A2 Coarse Loop PCA A3 Sub Synthesizer VCO PCA A4 Sub Synthesizer PCA A5 Coarse Loop VCO PCA A6 Mod Oscillator PCA A8 Output PCA A9 Sum Loop VCO PCA A10 Premodulator PCA A11 Modulation Control PCA A12 Sum Loop PCA A13 Controller PCA A14 FM PCA A20 Attenuator RPP Assembly A22 Delay Line Assembly Access to other assemblies does not require description 5 1 ACCESSPROCEDURES 5 2 WARNING A PIVOTING MODULE INSTRUCTIONS THE SYNTHESIZER MODULE WHICH MUST BE RAISED TO GAIN ACCESS TO MANY OF THE CIRCUIT BOARDS IS HEAVY WHEN RAISING OR LOWERING THE MODULE OBSERVE THE FOLLOWING PROCE DURES TO AVOID INJURY RAISING THE MODULE 1 REMOVE THE THREE 8 PAN HEAD SCREWS THAT SECURE THE MODULE TO THE CHASSIS SIDES 2 GRASP THE HANDLE AND LIFT THE MODULE 3 LOCK THE MODULE IN THE UP POSITION BY INSERTING TWO OF THE PREVIOUSLY REMOVED 88 SCREWS INTO THE BOSSES PROTRUDING FROM THE CHASSIS SIDES NEAR THE HI
196. EPLACEMENT PARTS MANUFACTURERS PART NUMBER OR GENERIC WEE470 645991 3 87623 1 2829 15 2 530153 2 571 1809 P3918 3904 F 55 432 55 F 55 100 F55137 299W 1 8 5P51 r2 Co lt gt 4 51 ELLE yaje CES www 1039 REEL F551912FT 1 F50VTD4992F F5547R5F 1 1 73B2BJ101B 13B 2BJ750B 73B 2BJ181B 73B 2BJ270B 8 5 15 25227 4 181 08 1 49102 1 4 560 J B F552152FT 1 F553652FT 1 F 55 1000 F F552262FT 1 F555762FT 1 F6559R0FT 1 F1 4473J VT F1 4VT202J 329H 1 502 22 8 102 F 55 7500 F T 1 7138 2876208 73B 2BJ221B 3329h 1 501 62395 1 87623 1 MC74HC138N N74HCT273N 802280 OP470FY AD7628KN MC74HCO8N 10116 MC74FOON 1121302 5 74574 51745000 000 5 ry 1 COCO C202020202020202020 0202 eo 22 ps 7 29 REPLACEMENT PARTS Table 7 5 A4 Sub Synthesizer PCA cont N REFERENCE FLUKE MFRS MANUFACTURERS 0 DESIGNATOR STOCK PART NUMBER TOT T A gt NUMERICS gt 5 5 NO CODE OR GENERIC QTY E U 34 IC OP AMP JFET INPUT 8 PIN DIP 472779 12040 LF356N U 35 IC OP AMP DUAL JFET INPUT 8 PIN DIP 495192 1204
197. ES 0 1UF 20 50V CAP AL 47UF 4 208 50V SOLV PROOF CAP CER 4 7PF 0 25PF 100V COH TA LOUF 4 202 10V CAP CER 33PF 2 50V COG CAP 100 2 100V COG CAP CER 820PF 5 100V 06 CAP TA 39UF 20 CAP TA LOUF 20 20V CAP AL 1000 20 16 501 7 PROOF CAP AL 150 20 35V CAP TA 10UF 20 10V CAP CER 3 3PF 4 0 25PF 100V 07 CAP AL 2200F 4 205 25V SOLV PROOF CAP AL 22UF 50 20 35V AL 0008 50 20 35V CAP POLYES 0 0010 10 507 CAP CER 330PF 4 55 1007 COG CAP CER 47PF 4 25 100V COG CAP CER 5 6PF 0 25PF 1007 COH CAP CER 2 7PF 0 25PF 100V COJ CAP CER 560PF 4 52 50V COG CAP POLYES 0 22UF 10 50V CAP CER 56PF 0 ATUF ENER UNCOMP 6 2V 53 20 0 41 7 ER UNCOMP 4 3V 5 20 0 4W D BV 50 WI 150MA SELCTD VF DIODE SI SCHOTTKY BARRIER SMALL SIGNL 2 ER COMP 6 4V 5 1 PPM 2 0 SI BV 15 09 10 50MA 500MW IC 1 22V 35 PPM T C BANDGAP REF DIODE SI SCHOTTKY BARRIER SMALL SIGNL SOCKET SINGLE PWB 042 049 PIN INDUCTOR 0 22UH T 108 400MBZ SHLD I DUCTOR 1250R CHOKE 6TURN SOCKET SINGLE PWB FOR 042 049 PIN PIN SINGLE PWB 0 025 SQ COMPONENT HOLDER TRANSISTOR 51 1092 TRANSISTOR 51 SMALL SIGNAL TRANSISTOR SI PNP S
198. ESHOOTING 6B 11 Ifthe symptoms indicate a digital or control problem the following suggestions may help isolate the faultto a particular functional circuit Referto the schematic diagrams in Section 8 Verify that all assemblies are receiving the correct voltages from the power supply The most obvious symptom of failure in the A13 Controller PCA is a blank front panel A properly operating front panel indicates that most of the controller and display circuitry is functional If the front panel is totally blank or unresponsive to keystrokes make sure that the display blanking special function is not active by pressing the key or by cycling the power Ifthe front panel is still blank refer to Microprocessor Kernel later in Section 6B Ifthe front panel is operating correctly but the RF output is incorrect try to determine if the fault is on the controller or on an RF circuit board by programming various functions and checking for status codes RF Control 6B 12 Communication with the RF circuitry in the upper and lower modules is through connectors J3 and J6 respectively The RF data and control signals to both modules are buffered by tri state drivers that are active only while data is being transferred and are in the high impedance state at all other times Special Function 903 the latch test generates continuous activity on the data and address buses so that the activity can be monitored with an oscilloscope The latch test is des
199. F power measurements Correctly entered cal factors can be verified on the H P 8902A by using specialfunctions 37 5 and 37 6 Refer to the H P 6902A Owner s Manual PROCEDURE Level Measurements 1 Perform the power meter zero and self calibration for the measurement receiver Refer to the H P 8902A Owner s Manual 2 Connect all instruments as shown in Figure 4 2 3 Program the UUT to SPCL 909 10 MHz 13 dBm and AMPL STEP 6 1 dB 4 Program the Measurement receiver to RF POWER mode and toggle the LOG LIN button to display dBm To enable the correct cal factor selection tune the internal LO on the measurement receiver to that of the UUT RF output 10 MHz V for the first frequency 5 Step the UUT level from 13 dBm to 11 4 dBm using the STEP Verify that each level measured with the measuring receiver agrees with the UUT programmed level and is within 1 5 dB 6 Select TUNED RF LEVEL on the measuring receiver wait for a displayed reading then press the CALIBRATE button Verify that the Recal annunciator goes out and a stable reading is displayed again 7 Stepthe UUT from 11 4 to 127 3 dBm again observing that each stepped level is within 1 5 dB 4 11 PERFORMANCE TESTS NOTE When the Recal annunciator on the measurement receiver lights while stepping through UUT levels press the CALIBRATE button on the measuring receiver and waitfor a stable reading 8 Repeat steps 4 through 7 for each of
200. FORMER 115V 50 400HZ 860804 W 6 CABLE ASSY RF W6 861067 W 7 CABLE ASSY RF W7 861070 11 CABLE ASSY LINE FILTER 860788 7 6 cont MFRS SPLY CODE 89536 59124 89536 89536 89536 71400 89536 89536 73134 10059 89536 89536 89536 86928 12962 05791 05791 89536 89536 89536 89536 05245 89536 89536 89536 89536 06915 89536 89536 89536 11965 89536 11965 89536 06383 89536 89536 89536 89536 An in S column indicates a static sensitive part MANUFACTURERS PART NUMBER OR GENERIC TYPE 861109 CF1 4 51RO J 861112 861117 864967 837575 5710 31 32 22NTM 62 ST 9531 36 1143026 853296 111062 853986 868781 10 1495 860598 860601 861070 860788 I p ES iS DODD IS IO D DODD DOW Es s ES ES IS IE REPLACEMENT PARTS ATTENUATOR ASSY SAE 1 4 THE ITEMS SHOWN ON THIS SHEET ARE LISTED UNDER THE 00 DIVISION IN TABLE 7 1 UNLESS OTHERWISE SPECIFIED 6080A AN T amp B Figure 7 1 6080A AN Final Assembly 7 7 REPLACEMENT PARTS MP9 COVER THE ITEMS SHOWN ON THIS SHEET ARE LISTED UNDER THE A00 DIVISION IN TABLE 7 1 UNLESS OTHERWISE SPECIFIED MPIO TOM COVE 6080A AN T amp B 7 8 Figure 7 1 6080A AN Final Assembly cont REPLACEMENT PARTS H402 H403 e OUTPUT SIDE OF OUTPUT MODULE THE ITEMS SHOWN ON THIS S
201. G AND REPAIR FREQUENCY SYNTHESIS A proper signal at TP5 with TP4 shorted to ground indicates that the RF circuits are probably not faulty and that the problem is in the audio section The loop amplifier acquisition oscillator can be checked by shorting TP5 to ground and measuring the waveform at with an oscilloscope which should be a sine wave of about 800 Hz and 14V pk pk level Next measure the TP waveform with both and TP8 shorted to ground The waveform should be a sine wave of about 13 6 kHz and 8V pk pk level Failure of this test indicates a problem somewhere between TP5 and The programmable attenuator can be checked for proper operation as follows First connect test points 7 and 9 to ground and program the UUT to SPCL 943 DACS set to full scale Measure the resistance from TP4 to ground The reading should be about 240 ohms Next program the UUT to SPCL 941 DACS set to zero The resistance reading should now be about 29 5 ohms Failure of this test indicates a problem somewhere between and Status Code 245 indicates an unleveled condition in the leveling loop that controls the signal amplitude at the RF input of mixer and is triggered when the modulator control voltage at 6 exceeds about 10V This fault condition can be caused by either a level problem in the RF path including the Sum Loop VCO and sum loop circuits between J9 and or by improper signal frequencies within the sum
202. G AND REPAIR FREQUENCY SYNTHESIS in the 1 2 5 MHz external reference mode SPCL 761 REFSEL should be a logic low The signal at 0503 pin 11 will be 1 2 or 5 MHz typically 5 MHz as configured at the factory depending on how SW502 is set The setting of this switch is described in the alignment section Ifthe voltage at TP19 is approximately 13V when in internal reference first check the internal TCXO There should be a 10 MHz TTL signal at U502 pin 12 and U503 pin 3 Power to the TCXO is supplied from Q501 at TP18 To check the external reference connect a 10 source 4 dBm signal to the 10 MHz REF IN There should be a 1V p p sine wave at J6 There should be a 10 MHz TTL signal at U510 pins 9 and 11 and eventually at U503 5 The logic control for the reference section is summarized below STATE EXTREFH TCXOH REFSEL 0502 Q506 External 10 MHz 1 1 1 on 5V 15 External 5 MHz 1 1 0 on on External 2 MHz 1 1 0 off 0V on External 1 MHz 1 1 0 off on Internal TCXO 0 1 1 if normal 10 MHz external 0 if SPCL 761 1 2 or 5 MHz external reference At this point there should be 10 MHz signals at 0503 pins 3 and 11 To check the phase detector remove the jumper between TP20 and TP21 Connect a variable power supply to TP21 Monitor the frequency at U503 pin 11 As you swing the power supply from about 1 to 10V the frequency at TP11 should move below and above 10 MHz by about 200 500 Hz The voltag
203. HEET ARE LISTED UNDER THE A00 DIVISION IN TABLE 7 1 UNLESS OTHERWISE SPECIFIED 6080A AN T amp B Figure 7 1 6080A AN Final Assembly cont 7 9 REPLACEMENT PARTS CONTROLLER SIDE OF OUTPUT MODULE THE ITEMS SHOWN ON THIS SHEET ARE LISTED UNDER THE A00 DIVISION IN TABLE 7 1 UNLESS OTHERWISE SPECIFIED MP18 6080A AN T amp B 7 10 Figure 7 1 6080A AN Final Assembly cont REPLACEMENT PARTS SUBSYNTHESIZER SIDE OF SYNTHESIZER MODULE THE ITEMS SHOWN ON THIS SHEET ARE LISTED UNDER THE A00 DIVISION IN TABLE 7 1 UNLESS OTHERWISE SPECIFIED 6080A AN T amp B Figure 7 1 6080A AN Final Assembly cont REPLACEMENT PARTS n614 THE ITEMS SHOWN ON THIS SHEET ARE LISTED UNDER THE A00 DIVISION IN TABLE 7 1 UNLESS OTHERWISE SPECIFIED lt 2 2 2 COARSE LOOP SIDE OF SYNTHESIZER MODULE 6080A AN T amp B Figure 7 1 6080A AN Final Assembly cont REPLACEMENT PARTS H933 H934o UNDER SCREW HEADS 40 OUTPUT MODULE THE ITEMS SHOWN ON THIS SHEET ARE LISTED UNDER THE A40 DIVISION IN TABLE 7 1 UNLESS OTHERWISE SPECIFIED 6080A AN T amp B Figure 7 1 6080A AN Final Assembly cont 7 13 REPLACEMENT PARTS TO AL ON ASO FRONT 04 72 Wi 6 IEEE BOARD ON REAR PANEL AO H ACO H904 9 w37 Q DN TO VARIOUS POINTS ON SYNTHESIZER MODULE
204. HESIS signal at 2 is next applied to DAC 0109 which is programmed by SUMCOMP bits 0 7 These 8 bits encode a number proportional to Sum Loop VCO 1 Note that Kv is the slope of the frequency vs tuning voltage function Thus DAC 109 scales the signal to account for VCO tuning voltage sensitivity variations with RF frequency Gain adjustment for DAC 0109 is provided by R116 The DAC output at U108 pin 6 is next applied to a switched R C network including R105 108 and related components that is programmed by FM range switching bits SUMVCO4 6 depending on FM deviation range This network scales the signal to the appropriate level The output of the network at TP3 the VCO steering port is the desired AC cancellation signal Noise contribution at the VCO steering port is reduced by C105 which is switched to ground by Q101 when the cancellation circuit is not active SUM LOOP TROUBLESHOOTING 6 32 6 38 Since the primary function of the sum loop is to combine various signal frequencies into the desired fundamental band frequency sum loop problems will generally cause frequency errors at the UUT output A first step in troubleshooting is to check for sum loop fault status codes 244 and 245 The implications and suggested troubleshooting sequence in response to these codes are described below Reading and understanding the detailed circuit descriptions for the sum loop and Sum Loop VCO assemblies paragraphs 6C 28 through 6C 31 and 6
205. Hz 150 ns AH 1 MHz Phase detector up output high 2 8V low 0 5V TP26 ground TP27 DC 2 24V 8 6V Sub Synthesizer VCO control voltage TP30 TTL 10 19 98 kHz 19 98kHz Low order digits signal 1 TTL 1 1 998 MHz 1 998 MHz Intermediate low order digits signal divide by 10 2 ground TTL 9 19 MHz 15MHz Triple modulus pre scaler output TP34 TTL 0 1 MHz 10kHz Modulus select signal 50 ns AL 5 DC 0 10 23V 1 6V Sub Synthesizer loop gain compensation DAC KN output TP36 input For calibration of low pass filter TP37 audio 10 19 98 kHz 19 98kHz Active quadrature generator output 450 mV p p TP38 audio 10 19 98 kHz 19 98kHz Active quadrature generator output 450 mV p p TP39 DC 0 10 23V varies Reference oscillator voltage DAC output TP40 DC 2 24V 8 6V Loop amplifier output TP41 DC 2 24V 8 6V Low pass filter input TP40 TP41 normally connected together except when troubleshooting 6 11 TROUBLESHOOTING FREQUENCY SYNTHESIS 6C 12 AND REPAIR Next use the low impedance probe to check the signal at the input to the divider 058 at pin 15 There should be a 15 dBm lower sideband signal as measured on the spectrum analyzer A problem at this point indicates a problem in the low order digits generator U21 U22 U23 U60 U61 active quadrature generator U59 the SSB mixer U53 U54 or the divider input amplifier U55 Program the signal generator to 804 000500 MHz The sig
206. IAGRAM 6C 14 Refer to the Reference Section Block Diagram Figure 6C 6 and the schematic Section 8 to identify the major functional sections and follow the signal paths ofthe coarse loop reference section The reference section is a phase lock loop in which the VCO is a 40 MHz voltage controlled crystal oscillator a divide by 4 by 8 by 20 by 40 a digital phase frequency detector and associated logic The main reference for the instrument is either a 10 MHz temperature controlled crystal oscillator 0501 or an external 1 2 5 or 10 MHz signal When the instrument is set to internal reference EXTREFH 0 the TXCO is turned on by enabling Q501 via an open collector comparator U509C and associated logic U502 U514 The 10 MHz from the TCXO is routed through U502 to a multiplexer U504B The output ofthe multiplexer is connected to the reference input ofthe phase detector U503A U511D When the instrument is set to external reference EXTREF 1 the TCXO is turned off The external signal from J6 is attenuated R521 523 clipped CR501 2 and high passed C524 5 L502 High speed comparator U510 converts the external reference signal to TTL The output of U510 is connected to the other input of a multiplexer U504B A portion of the comparator output is fed back to the input to provide hysteresis R524 7 6C 17 TROUBLESHOOTING AND REPAIR FREQUENCY SYNTHESIS OSO GOW OL 7HWOZ U3ZIS3HINAS 8
207. IDENTAL lt 1 AM at 1 kHz rate for the maximum deviation or 100 kHz whichever is less Valid for RF frequency 0 5 MHz DCFM CENTER FREQUENCY ERROR 0 196 of dev 500 Hz 1 GHz NOTE After DCFM Cal and without any FM range changes LOW RATE EXTERNAL FM RF Band DEV 10 Hz Rate Access by SPCL 711 sine wave square wave MAX 01 to 15 MHz 80 kHz 40 kHz 15 to 32 MHz 20 kHz 10 kHz 32 to 64 MHz 40 kHz 20 kHz 64 to 128 MHz 80 kHz 40 kHz 128 to 256 MHz 160 kHz 80 kHz 256 to 512 MHz 320 kHz 160 kHz 512 to 1056 MHz 640 kHz 320 kHz Cu ste dte o oe 3096 on a 5 Hz square wave BANDWIDTH 3 0 5 Hz to 100 kHz typical INTRODUCTION AND SPECIFICATIONS Table 1 4 Typical Signal Generator Performance cont DC INPUT INCIDENTAL 1 1 kHz rate and lt 10 kHz dev NOTE FM specifications apply where RF Frequency Deviation 150 kHz RF Frequency Mod Rate 150kHz PHASE MODULATION 3 DIGIT DISPLAY DEVIATION RANGES MAXIMUM ACCURACY 5
208. ISE SPECIFIED 6080A AN T amp B Figure 7 1 6080A AN Final Assembly cont 7 16 REPLACEMENT PARTS H903 H90S UNDER SCREW HEADS MPG2 SUBSYNTHESI ER_ SIDE THE ITEMS SHOWN ON THIS SHEET ARE LISTED 6080A AN UNDER THE A60 DIVISION IN TABLE 7 1 UNLESS OTHERWISE SPECIFIED TO A40 OUTPUT SUB SYNTHESIZER 5 MODULE 909 9 214 TO 5 POWER SUPPLY ON ATO REAR PANEL T amp B 7 17 Figure 7 1 6080A AN Final Assembly cont REPLACEMENT PARTS THE ITEMS SHOWN ON THIS SHEET ARE LISTED UNDER THE A70 DIVISION IN TABLE 7 1 UNLESS OTHERWISE SPECIFIED o A 2 9 fo 47 19 6080 T amp B Figure 7 1 6080A AN Final Assembly cont REPLACEMENT PARTS Table 7 2 Al See Figure REFERENCE FLUKE MFRS MANUFACTURERS 0 DESIGNATOR STOCK 5 PART NUMBER TOT T A gt NUMERICS gt 5 NO OR GENERIC TYPE QTY E C 1 CAP TA 4 7UF 20 50V 832675 31433 1356G475M050AS C 2 CAP TA 10UF 20 10V 176214 56289 196D106X0010KA1 C Je 20 288 CAP POLYES 0 1UF 20 50V 837526 40402 1823104056 2 C 12 14 16 837526 225 837526 7 CAP 1000PF 20 100V X7R 816181 51406 RPE12
209. J CONN D SUB PWB 9 5 811430 00779 747150 8 1 1 34 PIN SINGLE PWB 0 025 SQ 267500 00779 87623 1 34 5 1 2 SWITCH SLIDE SPDT LOW PROFILE 810887 95146 558 12 2 5 3 SWITCH SLIDE DPDT 452862 79727 65113 0018 620 32 1 An in S column indicates static sensitive part 7 65 REPLACEMENT PARTS 60804 1610 7 66 Figure 7 16 A16 IEEE 488 Connector PCA REPLACEMENT PARTS Table 7 17 A19 Switch PCA N REFERENCE FLUKE MFRS MANUFACTURERS 0 DESIGNATOR STOCK SPLY PART NUMBER TOT T gt gt 5 0 CODE OR GENERIC QTY E DT d 2 ISOLATOR OPTO OPTICAL SWITCH INFRARED 523530 09214 22 1 2 1 50 1 ROW PWB 0 100CTR 16 POS 447102 30035 55 109 1 16 1 MP 2 SOCKET l ROW PWB 0 100CTR 7 POS 520809 30035 99 109 1 07 1 An in S column indicates a static sensitive part 7 67 REPLACEMENT PARTS Table 7 18 A20 Attentuator RPP Assembly REFERENCE FLUKE MFRS MANUFACTURERS DESIGNATOR STOCK SPLY PART NUMBER gt gt 5 DESCRIPTION NO CODE OR GENERIC 7 RELAY DRIVER 860809 89536 860809 21 ATTENUATOR ORDER NEXT HIGHER ASSEMBLY A20 H 301 309 SCREW MACH PH P MAG SS 6 32X 375 183225 89536 783225 MP 1 ATTENUATOR HOUSING FILTER ASSY 868948 89536 868948 in 5 column indicates a static sensitive part
210. MALL SIGNAL TRANSISTOR SI NPN SMALL SIGNAL FLUKE STOCK NO 837526 831526 831526 837526 837526 837526 937526 837526 831526 831526 831526 831526 837526 822403 362772 176214 715292 837609 837609 528604 161349 698662 851589 234468 535195 381988 698720 634154 313247 866764 261735 138484 32091 866164 866164 866164 866764 866164 866164 261500 261500 261500 261500 422965 698233 698225 225599 330803 MFRS MANUFACTURERS SPLY PART NUMBER CODE OR GENERIC TYPE 40402 MKT1823104056 8101 100C060479C 1960106 0010 1 113 06 330 6 SR201A101GATR SR151A821MAT 196D396X0006KA1 199D106X0020CA2 156RLR035 199D106X0010BA1 8101 100 000339 35018 22 62643 SM SR291A331JATR 8101 100C0G0569C SR171A2R7CAA C320C561J5G5EA C315C560G1G5EA 1960474 9035 1 1N753A SR4348RL 1N749A FDN9274 5082 2800 52620120 144448 AD41118 5082 6264 125 645991 3 MR 22 138484 320911 645991 3 00779 87623 1 98159 04713 04713 07263 04713 2829 15 2 2N3906RLRA 2N3904RLRA2 244250 56560 S column indicates a static sensitive part KME50VB47RM6X11RP 50V KME16VB101M6 3X11RP KME25VB221M8X11 5RP 35 VB 100 185 001 K 0050 R A B RPE121911C0G470G100V 185 2 22 K 0050 R C B N 0 TOI T QTY E 52 2 1 3 2 9 1 4 4 4 2 2 4 p 49 REPLACEMENT PARTS Table 7 11 A11 Modulation Control PCA
211. MF554990FT 1 229 271 530 816462 R 108 RES 1 5K 1 125W 100 719682 91637 55 1501 F 1 1 R 109 RES MF 3 16K t 1 0 125W 100 866264 91637 CMF553161FT R 111 RES MF 10 1 0 125W 100PP 719443 91637 555 10R0 F T 1 R 112 117 RES MF 49 9 4 1 0 125W 100 720318 59124 MF5549R9F R 113 RES MF 100 1 0 125W 100PP 719450 91637 CMF 55 1000 T 1 R 114 116 RES MF 2 32K 4 1 0 125W 100PP 719914 91637 55 2321 F 1 1 R 118 124 RES 301 1 0 125W 100PP 120029 59124 553010 R 119 RES MF 127 1 0 125W 100PP 866199 91637 CMF551270FT 1 An in S column indicates a static sensitive part 7 22 SIO IS ES NO IS Co CO ON DOr REFERENCE DESIGNATOR gt gt 5 Fr Fe Fx rz rz Fz 55 Fzjrz 55 tz 1 d Fr RES C RES C RES tz Ex tx Fr rx Gi Q hr Ex hm r1 R 120 220 RES R 121 122 R R 123 R 125 RES R 201 202 R R 203 208 213 R R 413 417 421 R 612 R 209 214 217 R R 210 260 308 R 408 610 618 R 2H R R 212 528 R R 215 R R 216 Ri R 218 R R 219 223 225 RES R 226 238 508
212. MSA0304 MC10H131P SMA85 2025 LM324N 5 08 01 5116 CSC10A 01 511 0202020029 10 DDO On CO PO S I E i ES BeN 7 43 REPLACEMENT PARTS Table 7 10 A10 Premodulator cont DESIGNATOR gt gt 5 5 10 5 RES NET SIP 8 4 RES lK 4 2 714345 80294 744 An in S column indicates a static sensitive part MANUFACTURERS PART NUMBER CODE OR GENERIC 46088 101 102 REPLACEMENT PARTS ta x 4557 2 CR14 0 Ad ou oo Pa o o m m a qm 198 2513 0020 6080A 1602 Figure 7 10 A10 Premodulator PCA 7 45 REPLACEMENT PARTS 7 46 REFERENCE DESIGNATOR A gt NUMERICS gt 5 101 103 105 1 107 111 113 1 126 140 13 14 15 19 73 77 22 26 29 62 66 1 130 34 47 51 78 1 80 48 49 15 1 16 60 61 64 1 65 67 68 81 82 CAMARA CACAO RA AIA 25 Table 7 11 A11 Modulation Control See Figure 7 11 CAP POLY
213. NGES LOWERING THE MODULE 1 SUPPORT THE MODULE IN THE RAISED POSITION AND REMOVE THE TWO LOCK UP SCREWS 2 USING THE HANDLE ONLY AND KEEPING HANDS CLEAR OF ALL OTHER PARTS OF THE SIGNAL GENERATOR LOWER THE MODULE 3 LOCK THE MODULE IN THE DOWN POSITION USING THE THREE 8 PAN HEAD SCREWS CAUTION The gas spring can make the synthesizer module swing open when the instrument is turned on its side To avoid this be certain to lock the synthesizer module in the down position after lowering it ACCESS PROCEDURES LOCATION OF MAJOR ASSEMBLIES 5 2 The location of the major assemblies is illustrated in Section 7 Information on exchanging modules is presented in Section 6 CIRCUIT DESCRIPTIONS TROUBLESHOOTING AND ALIGNMENT ACCESS INSTRUCTIONS 5 3 Access instructions foreach assembly ofthe 6080A AN signal generator are provided in the following paragraphs Before performing any disassembly of the signal generator remove the powercord from the rear panel power receptacle and remove the exterior top and bottom instrument covers To install the assemblies reverse the disassembly steps Be certain the pin connectors and filter sockets are straight when replacing a printed circuit assembly PCA Take care that the PCA pulls and RF cables are not pinched between the modules and module covers Removing the Front Panel Section 5 4 1 Remove the two 6 pan head screws that attach the RF connector bracket to the output m
214. OR SI N JFET TO 92 723134 17856 J27138TR 2 3 14 15 RES CF 33K 4 52 0 250 573485 59124 CF1 4 333 J B 3 Es 242543 RES MF 49 9 1 0 125W 25 447177 91637 CMF5549R9FT 9 2 R 3 RES 1K 1 0 125W 50PPM 320333 91637 CMF551001FT 2 4 25 320333 R 8 RES MF 374 1 12 0 125W 866335 91637 CMF553740FT 1 R 9 RES VAR CERM 100 10 0 5 381913 80294 3299 1 101 R 10 RES MF 604 1 0 125W 832030 91637 CMF556040FT 1 R d RES MP 8 87K 15 0 1258 100PPM 658922 59124 50 08871 R 12 RES MF 3 48K 1 0 125W 100 832071 91637 CMF 55 4802 F T 1 R 13 RES VAR CERM 500 10 0 5 520783 32997 3299W 1 501 R 20 26 RES CF LOK 5 0 25 573394 59124 CF1 4 103 J B 2 R RES 51 5 0 25 572990 59124 CF1 4 510 JB R 22 RES F 2 05K 13 0 125W 100 719849 91637 CMF 55 2051 F 1 1 R 24 RES 5 11K 1 0 125W 100 720342 91637 CMF 55 5111 F 1 1 T 1 11 TERM FASTON TAB 110 SOLDER 512889 00779 62395 1 1 U 1 TC CMOS CUSTOM GATE ARRAY 80PN QFP 851324 33297 851324 U 4 5 AMP HIGH SPEED 2000 05 35MHZ 845466 27014 LM6361N 2 U 6 IC COMPARATOR QUAD 14 PIN DIP 387233 12040 LM339N 0 7 IC CMOS 12 1 4 LSB ON BOARD REF 851642 24355 405653 0 8 IC CMOS 12 1 2 BIT UP COMPATIBLE 851647 06665 1548 0 9 11 TC OP AMP DUAL LO OFFST VOLT LO DRIFT 851704 27014 LF412ACN 2 U 10 IC CMOS QUAD SPST ANALOG SWITCH 680744 17856 DG30
215. OUT to the frequency counter 10 MHz reference input and connect the UUT RF OUTPUT to the frequency counter input 2 Setthe UUT REF INT EXT switch to INT 3 Program the UUT to SPCL 909 4 5 PERFORMANCE TESTS 4 6 4 Program the UUT frequency to 111 111111 MHz 5 Program the UUT frequency step to 111 111111 MHz 6 Verify that the reading on the frequency counter agrees with the UUT frequency 1 count as the frequency is stepped from 111 111111 to 999 999999 MHz HIGH LEVEL ACCURACY TEST 4 6 The output power is measured using a power meter at various frequencies First the step attenuator is set for zero attenuation then each attenuator section is individually programmed Finally the output level accuracy and attenuator section errors are computed If a measuring receiver is available for level testing proceed directly to the ALTERNATE LEVEL ACCURACY TEST procedure later in Section 4 TEST EQUIPMENT Power meter Power sensor high Level REQUIREMENT The output level accuracy the attenuator section errors and the sum of the attenuator section errors at each test frequency are lt 1 5 dB from 0 5 to 1024 MHz REMARKS Ifthe UUT fails this performance test it needs to be calibrated Section 3 or repaired Section 6 Possible problem areas if no power on status codes are present include the A8 Output PCA the A21 Attenuator PCA or the A7 Relay Driver PCA The test frequencies of this procedure
216. PCL 943 and measuring the DC voltage at TP8 the VCO steering port This special function programs the steering DAC to full scale and should result in a reading of 24V If the Coarse Loop VCO seems to function properly the Coarse Loop is probably faulty 6C 23 TROUBLESHOOTING AND REPAIR FREQUENCY SYNTHESIS With 500 ohm 10X probe connected to the spectrum analyzer check the levels in the RF section against those in Table 6C 3 These levels are as measured on the spectrum analyzer The actual level is 20 dB higher NOTE The levels in Table 6C 3 are approximate and can vary as much as 3 dB Table 6C 3 Coarse Loop RF Voltage Levels CONNECTION POINT LEVEL P2 14 dbm U401 output 18 dbm U405 output 16 dbm 0402 output 16 dbm 6C 24 At the output ofthe divide by 4 amplifier there should be a 160 MHz 16 dBm signal as measured with the 500 ohm 10X probe The N divider programs the coarse loop in 8 MHz steps The output of the N divider should be approximately 40 MHz ECL level For coarse loop frequencies of 640 800 and 960 MHz there should not be any signal at TP2 Ifthe rate multiplier divider U305 etc is working correctly there should be a 2 MHz ECL signal U305 pin 14 The programming to the rate multiplier 128 64 32 16 8 MHz bits is active low There are 20 steps in the rate multiplier programming The logic states for the N divider are given in Table 6C 4 If the N
217. Program the UUT to SPCL 01 Connect the DVM to measure the voltage between TP6 and ground on the module plate Adjust R8 for an indication of 0 mV 40 5 mV Reinstall the nodule plate cover and the instrument cover when the adjustments are complete 6D 11 TROUBLESHOOTING AND REPAIR RF LEVEL AM 6D 12 Mod Control PCA Detector Offset Adjustment R28 6D 13 The detector offset adjustment sets the detector offset voltage The adjustment also affects AM Depth Adjustment R10 Repeat Section 6D 14 after this adjustment TEST EQUIPMENT Power meter e Power sensor High Level REMARKS The UUT must be operated at room temperature for at least one hour with the module plate cover in place before continuing with this adjustment procedure This adjustment is normally required only when components in the detector or detector linearizer circuits have been replaced If the detector offset is adjusted perform the AM depth adjustment CAUTION The detector offset adjustment directly affects the output level and should not be made indiscriminately PROCEDURE The detector offset adjustment R28 is adjusted to provide a 24 dB change in output power for 24 dB change in the level DAC This is done while operating in fixed range 1 Access R28 by removing the instrument bottom cover 2 Program the UUT to SPCL 01 350 MHz and 12 dBm 3 Program the UUT to SPCL 51 This Special Function enables amplitude fixed range 4
218. SUM STEER MOD EXPECTED STATE CODE FREQUENCY DAC INT FM DEV FREQ OF SUM LOOP 327 550 MHz Normal Off Locked 328 700 MHz Normal Off Locked 329 830 MHz Normal Off Locked 330 975 MHz Normal Off Locked 331 550 MHz 0 Off Unlocked 332 800 MHz Normal On 4MHz 50kHz Locked 333 800 MHz Normal On 4MHz 63 Hz Locked 6 11 TROUBLESHOOTING AND REPAIR 6 12 RF Output Tests 6 32 The RF Output Tests see Table 6 11 verify the presence of an RF signal at the output of the Attenuator RPP assembly The sensitivity of the RPP detection circuitry is increased so that it can be used as a RF signal detector The first test programs a high RF level at a frequency in the fundamental frequency band and expects the RPP indicator to trip The second test programs a high RF level at a frequency in the HET frequency band and expects the RPP indicator to trip The third test programs a level below the detector threshold and expects that the indicator will not trip Table 6 11 RF Output Tests EXPECTED STATE CODE RF FREQUENCY AMPLITUDE OF RPP INDICATOR 334 800 MHz 416 dBm Tripped 335 1MHz 416 dBm Tripped 336 800 MHz 7 dBm Not Tripped Pulse Modulator Tests 6 33 The Pulse Modulator Tests see Table 6 12 configure the RPP circuitry to its high sensitivity mode as in the RF output tests The first test programs a high RF level and enables internal pulse The internal modulation oscillator sends a steady l
219. Section 5 6C 26 A2 Coarse Loop PCA Test 6C 27 5 Coarse Loop VCO PCA Expected DC 6C 32 Sum Loop 5 6C 34 A12 Sum Loop PCA RF Circuitry Test 6C 39 A12 Sum Loop PCA RF Section DC Bias 6C 40 A12 Sum Loop PCA Test 6C 41 A9 Sum Loop PCA Expected DC 6C 46 Band Filter and Frequency Programming Data 6D 7 Frequency Band Logic 5 5 6D 8 Modulator Detector Nominal 6D 9 All Modulation Control PCA Test 6D 9 Attenuator 5 6D 21 Attenuator Level 6D 22 Modulation Control Table 800 MHz RF 6E 8 Modulation Ranges and FM DAC 6E 9 FM Oscillator Frequency Check Table Normal 1 6E 11 FM Oscillator Modulation Control Normal
220. T CERM CUSTOM 501841 MFRS SPLY CODE 91637 91637 32991 59124 91637 An in S column indicates static sensitive part ANUFACTURERS PART NUMBER F5531R6FT F555900FT 865 1 20 556340F 556040 F 55 2000 F 55 182 F553921FT 1417 2395 1 3241 3391 355341 50500203 1548HP L074CN 471 3931 D1524JN D7534KN 7415110 74151231 C148C138N LF356B 74HCT273N OP 37GP C34001P 2 E522N C74FOON AD7537KN 0 2276 7908 E5534AN DP16 03 102J DP1603103J 316B103F dco Bee OR GENERIC TYPE P gt REPLACEMENT PARTS 090000000000 Noa coc NN m 5 5 5 A11 u23 040 912 GA 5 052 aa 014 cs OOOOOO 3 000000 B 5 HEBER ppg 38 Sac Bi gg gum 2 5 FA 27 Stat Ol lol La le 2 j 9 C3 5 en zO 5 ol Im m ojj a m 2 5 5 5 281 or eure Mni ui R89 025 Q R108 2 030 Qo 1 81261 C110
221. TAIN 5 7 2 7 3 SERVICE CENTERS o 7 3 continued on page vii TABLE CONTENTS continued SECTION TITLE PAGE 8 SCHEMATIC 5 8 1 TABLE OF CONTENTS sape 8 1 APPENDICES A INSTRUMENT PRESET 5 1 SPECIAL FUNCTION TABLE recorte E RESERVE ep IP REJECTED ENTRY ERROR 5 OVERRANGE UNCAL STATUS 5 1 SELF TEST STATUS 5 1 COMPENSATION MEMORY STATUS 5 1 EXAMPLE CALIBRATION CONTROLLER 0 1 COMPENSATION 5 1 REAR PANEL AUX CONNECTOR 1 1 viilviii List of Tables TABLE TITLE PAGE 1 1 Accessories Included with each Signal 1 3 1 2 Optional 2222 2 2 22 1 3 1 3 6080A AN 1 4 1 4 Typical Signal Generator 1 9 2 1 Frequency Coverage 5
222. TING 14 6E 11 6E 13 Frequency Check 6E 11 6E 14 Modulation Gheck riae ek dup Edu 6E 12 6E 15 Input Signals and Control Input Signals Checks 6E 12 6E 16 FM 6E 13 6E 17 Adjustments on the Modulation Control PCA 1 6E 13 6E 18 Alignment of FM PCA 1 4 6E 14 6F INTERNAL MODULATION 5 6F 1 6F 1 MODULATION OSCILLATOR BLOCK DIAGRAM 6F 1 6F 2 INTERNAL MODULATION OSCILLATOR CIRCUIT 6F 1 6 3 Direct Digital Synthesized Wave 6F 1 6F 4 Pulse 6F 3 6F 5 Signal ege e Rp toe ep hee een all 6F 3 6F 6 MOD OSCILLATOR TROUBLESHOOTING AND ADJUSTMENTS eese su ee steel 6F 4 6F 7 Direct Digital Synthesizer Troubleshooting 6F 4 6F 8 Pulse Generator 6F 5 7 LIST REPLACEABLE 7 1 TABEE OEF CONTENIS 2555023 22500 BOS ote Ate ERO reU 7 1 7 1 INTRODUCTION s egg 7 2 7 2 HOW TO OB
223. TS RW Figure 6B 2 Address Decoding 6B 7 TROUBLESHOOTING AND REPAIR DIGITAL CONTROLLER CALIBRATION COMPENSATION MEMORY 6B 22 The integrity ofthe calibration compensation data is vital to the performance of the instrument The use of redundant data storage allows the system to recover even if some of the data has been corrupted There are 11 calibration compensation data segments Attenuator Coarse Loop Compensation Coarse Loop Steering Output Sub Synthesizer Sum Loop Compensation Sum Loop steering AM Calibration FM Calibration RF Level Calibration Reference Oscillator calibration Two identical copies of each data segment are maintained in two separate ICs on the Controller PCA One copy is stored in the EEPROM and the other copy is stored in the battery backed RAM Ifthe power fails while either version is being updated the other is still valid Calibration Compensation Memory Status 6B 23 6B 8 Whenever the self tests are performed the checksums are verified for each data segment in the EEPROM and in the battery backed RAM In addition each checksum is compared to the corresponding checksum in the redundant data block If one checksum is valid and the other is invalid the valid copy is used If both copies have invalid checksums overrange uncal status code 250 is set and the STATUS annunciator is flashed If any ofthe checksums fail self test status code 302 is reported Special function 04
224. Triesterstrasse 66 Postfach 217 A 1101 Wein Tel 43 222 60101 x1388 Belgium Philips amp MBLE Associated S A Scientific amp Industrial Equip Div Service Department 80 Rue des deux Gares B 1070 Brussels Tel 32 2 525 6111 Brazil Hi Tek Electronica Ltda Al Amazonas 422 Alphaville CEP 06400 Barueri Sao Paulo Tel 55 011 421 5477 Canada Fluke Electronics Canada Inc 400 Britannia Rd East Unit 1 Mississauga Ontario 142 1X9 Tel 416 890 7600 Chile Intronsa Inc Casilla 16158 Santiago 9 Tel 56 2 232 1886 232 4308 China Fluke International Corp P O Box 9085 Beijing Tel 86 01 512 3436 Colombia Sistemas E Instrumentacion Ltda Carrera 13 No 37 43 Of 401 Ap Aereo 29583 Bogota Tel 57 232 4532 Denmark Philips A S Technical Service amp E Strandlodsveij 1A PO Box 1919 DK 2300 Copenhagen S Tel 45 1 572222 Ecuador Proteco Coasin Cia Ltda P O Box 228 A Ave 12 de Octubre 2285 y Orellana Quito Tel 593 2 529684 Egypt Egypt 10 Abdel Rahman el Rafei st el Mohandessin P O Box 242 Dokki Cairo Tel 20 2 490922 England Philips Scientific Test amp Measuring Division Colonial Way Watford Hertforshire WD2 4TT Tel 44923 240511 Finland Oy Philips AB Central Service Sinikalliontie 1 3 P O Box 11 SF 02630 ESPOO Tel 358 0 52572 France S A Philips Industrielle et Comerciale Science et Industry 105 Rue de Paris BP 62 9
225. U 25 IC OP AMP LO NOISE PLASTIC DIP 854216 06665 OP27GP U 27 IC COMPARATOR GENERAL PURPOSE DIP 845065 64155 LT1011ACN8 U 29 TC 16V8 LOGARRAY 60804 90203 855056 89536 855056 30 IC CMOS 3 8 LINE DCDR W ENABLE 773036 04713 MC74HC138N U 22 IC CMOS 8 1 LINE MUX DEMUX ANALOG SW 836304 04713 74HC4051N U 33 IC 16V8 LOG ARRAY 60803 90204 855143 12040 855143 U 35 IC CMOS QUAD SPST ANALOG SWITCH 620948 24355 ADG201AKN U 36 39 43 ICD OS FET QUAD SWITCH 17856 550500203 4 U 37 45 46 IC COMPARATOR QUAD 14 PIN DIP 387233 12040 13394 3 U 38 IC OP AMP DUAL LOW NOISE LOW CURRENT 855130 06665 OP270FZ U 40 41 IC OP AMP PRECISION LOW NOISE 816744 06665 OP 37GP 2 U 42 IC BPLR ANALOG MULTIPLIER 845151 24355 42020 1 An in S column indicates static sensitive part 7 59 REPLACEMENT PARTS 7 60 REFERENCE DESIGNATOR A NUMERICS DG BG CS CS ox Table 7 14 A14 cont FLUKE FRS MANUFACTURERS STOCK PART NUMBER DESCRIPTION 0 CODE OR GENERIC IC FTTL HEX INVERTER 634444 04713 MC74F04 IC LSTTL HEX INVERTER 393058 04713 5 741 504 AMP JFET INPUT 8 PIN DIP 472719 12040 LF356N RES SIP 6 PIN 5 RES 4 7K 2 494690 91637 CSC06B01472G RES NET SIP 10 PIN 9 RES 100K 2 461038 91637 CSC10A 01 102G RES SIP 6 PIN 5 100
226. UT EXT PULSE MOD Connect the 8840A to J4 P5 The 8840A should read OV DC 2V DC Press the External Pulse Modulation button on UUT front panel to on The 8840A should read 4 2V DC 2V DC Set the UUT to SPCL 909 Set the 8840A to DC volts 2 volt range Connect the 8840A to on the 4048 board Adjust the modulation level sense R71 for 98V 5 mV Remove 8840A from Set the UUT to EXT FM Setthe 6011A to 1 kHz and 383 mV Connectthe 6011A and the 8840A to the UUT FM EXT input a Edit the 6011A level until the 8840A reads 707V RMS Verify on the UUT front panel that the EXT FM LO and the FM HI annunciators are off b Increase the 6011A output voltage to 728V RMS as measured on the 8840 Verify that the EXT FM HI annunciator is on c Decrease the 6011A output voltage to 685V RMS as measured on the 8840A Verify that the EXT FM LO annunciator is on 10 Set UUT to SPCL 909 EXT AM Setthe 6011A to 1 kHz and 383 mV Connectthe 6011A and the 8840A to the UUT AM EXT input a Edit the 6011A level until the 8840A reads 707V RMS Verify on the UUT front panel that the EXT AM LO and the AM HI annunciators are off b Increase the 6011A output voltage to 728V RMS as measured on the 8840A Verify that the EXT AM HI annunciator is on c Decrease the 6011A output voltage to 685V RMS as measured on the 8840A Verify that the EXT AM LO annunciator is on Alignment of FM PCA A14 6E 18 Align the FM PCA as described
227. V DC nominally 13 Vdc V of lt 12V DC 8 Check for CMOS switch leakage of control to the signal path 6E 11 TROUBLESHOOTING AND REPAIR FREQUENCY AND PHASE MODULATION 6E 12 Modulation Check 6E 14 For errors and faults in modulation use Table 6E 4 Table 6E 4 FM Oscillator Modulation Control Normal Operation NOTE Set SPCL 909 RF Freq 800 MHz INTFM 250 kHz 1 kHz Alternate Use EXTFM with low frequency signal generator JF 6011 set to 1 kHz and 383 mV RMS into EXT FM input MOD FREQ VOLTAGE AT SIGNAL AT JUNCTION SIGNAL TP4 U38 1 C70 TP1 100 Hz 500 mV peak 250 mV peak 4 p peak 1 kHz 500 mV peak 25 mV peak 4 p peak 5 kHz 500 mV peak 5 mV peak 4 p peak To check modulation proceed as follows 1 First check FM input to FM PCA at J6 for 4V peak If this is not present check Modulation Control PCA FM circuitry and inputs For error at TP4 and check the high modulation frequency path U40 etc For error at the U38 1 C70 junction check the low frequency modulation path U38 etc Check all ranges for modulation correctness at output Use the Modulation Control Table Table 6E 1 for the logic and the ranges for all FM DEV ranges Check CMOS analog switches and drivers for proper operation Check Phase Modulation for correctness at output If the output is not correct check the M circuits associated with U40 for problems at high modulation frequencies for er
228. W ENABLE 773036 04713 MC74HC138N XCR SPACER LED 471094 89536 471094 2 1 3 RES NET SIP 10 PIN 9 RES 100K 2 461038 91637 5 10 01 1026 3 2 4 RES SIP 6 PIN 5 RES 10K 2 500876 91637 5 06 01 103 G 2 5 RES NET SIP 6 PIN 5 RES 4 7K 2 494690 91637 5 06 014726 in S column indicates a static sensitive part 7 19 REPLACEMENT PARTS Ui Cu 018 CE 012 R1 Uii 58 u2 u3 016 E 555 E bit 1 1 1 d 014 Ju 60804 1604 7 20 Figure 7 2 A1 Display PCA REPLACEMENT PARTS Table 7 3 A2 Coarse Loop PCA See Figure 7 3 N REFERENCE FLUKE MFRS MANUFACTURERS 0 DESIGNATOR STOCK SPLY PART NUMBER TOT T A gt NUMERICS gt 5 DESCRIPTION NO CODE OR GENERIC TYPE QTY E C 101 218 CAP POLYES 0 47UF 10 50V 697409 84411 J1320R47MF10PCT50V 2 C 102 107 206 CAP POLYES 0 1UF 4 202 50V 837526 40402 1823104056 75 C 207 217 219 837526 C 221 222 226 837526 C 227 230 236 837526 C 238 245 249 837526 C 253 263 265 837526 C 266 270 305 837526 C 312 410 411 837526 C 415 417 424 837526 C 427 429 507 831526 C 512 511 520 837526 C 522 526 528 837526 C 531 536 539 837526 C 540 543 548 837526 619 630 631 837526 C 638 639 642 837526 C 65 831526 C 103 605 CAP
229. Y MODULATION 3 DIGIT DISPLAY DEVIATION 0 to 999 Hz 1 to 9 99 kHz 10 to 99 9 kHz 100 to 999 kHz 1104 2 MAXIMUM DEV RF Frequency 500 kHz 01 to 15 MHz 125 kHz 15 to 32 MHz 250 kHz 32 to 64 MHz 500 kHz 64 to 128 MHz 1 MHz 128 to 256 MHz 2 MHz 256 to 512 MHz 4 MHz 512 to 1056 MHz 1 11 INTRODUCTION AND SPECIFICATIONS Table 1 4 Typical Signal Generator Performance cont Minimum FM rate at max deviation in any band ACFM mode is 60 Hz 1 2 max deviation 30 Hz 1 4 max deviation 15 Hz from 1 4 to 1 64 max deviation 15 Hz 1 64 max deviation 60 Hz 1 128 max deviation 40 Hz 1 256 or less max deviation 15 Hz No limit in DCFM mode RESOLUTION 3 digits ACCURACY 5 of setting 10 Hz for rates of 05 to 50 kHz 296 THD for rates from 05 to 50 kHz does not include effects of residual noise lt 1 THD at 1 2 or less max deviation and rates from 0 1 to 50 kHz LOW DISTORTION MODE 0 396 THD noise 3 5 kHz deviation and SPCL 731 rates from 0 3 to 3 kHz BANDWIDTH 1 5 20 Hz to 100 kHz subject to low frequency max deviation limits DCFM DC to 100 kHz INC
230. a The 0 01 MHz to 1056 MHz frequency coverage is divided into the seven bands shown in Table 2 1 THEORY OF OPERATION Table 2 1 Frequency Coverage Bands BAND FREQUENCY COVERAGE HET 0 01 to 14 999999 MHz Divide by 32 15 to 31 999999 MHz Divide by 16 32 to 63 999999 MHz Divide by 8 64 to 127 999999 MHz Divide by 4 128 to 255 999999 MHz Divide by 2 256 to 511 999999 MHz Fundamental 512 to 1056 MHz Three signals are combined in the sum loop to produce a signal that ranges from 480 to 1056 MHz This signal is divided by factors of2 to produce the bands in Table 2 1 The HET band is produced by mixing 80 01 to 94 999999 MHz from the Divide by 8 bad with 80 MHz to produce 0 01 to 14 999999 MHz The three signals that are combined in the sum loop are 576 to 960 MHz in 8 MHz steps from the coarse loop 8 to 16 MHz in 1 Hz steps from the sub synthesizer and 80 MHz from the FM circuitry Ifthe sum loop output frequency is below 760 MHz the FM signal and the sub synthesizer signals are subtracted from the coarse loop signal If the sum loop output signal is above 760 MHz the FM signal and the sub synthesizer signals are added to the coarse loop signal The A2 Coarse Loop contains the reference circuits and generates a 576 to 960 MHz signal in 8 MHz steps The main reference frequency for the signal generator is a 40 MHz crystal oscillator This oscillator is phase locked to either an internal 10 MHz TXCO or an externa
231. a static sensitive part 7 21 REPLACEMENT PARTS Table 7 3 A2 Coarse Loop PCA cont REFERENCE FLUKE MFRS MANUFACTURERS DESIGNATOR STOCK PART NUMBER A gt NUMERICS gt 5 NO CODE OR GENERIC TYPE 547 549 714766 56289 1990106 0010 1 C 604 CAP CER 1 25 100V COG 838466 72982 RPE121911C0G330G100V C 607 CAP CER 4 TPF he 25PF 1007 816215 04222 88171 487 C 616 617 622 CAP CER 82PF 4 22 100V COG 512350 04222 SR291A820GATR C 623 643 649 512350 C 644 650 CAP CER LOPF 2 100V COG 512343 51406 RPE110COG100G100V C 653 654 CAP CER 100PF 2 100V COG 837609 04222 SR201A101GATR CR 101 102 202 DIODE 51 SCHOTTKY BARRIER SMALL SIGNL 313247 28480 5082 6264 125 203 601 602 313247 CR 103 204 205 DIODE SI BV 75 0V 0 150 500MW 698720 65940 1N4448 CR 501 505 507 698720 CR 20 ZENER UNCOMP 3 9V 10 20 0 4W 698654 04713 1N748 SR4348RL CR 206 ZENER UNCOMP 5 1V 58 20 0 4W 722926 04713 CR 207 ZENER UNCOMP 10 0V 10 20 OMA 0 41 180406 04713 1N758 CR 402 403 ODE 5 ATTENU
232. aired most easily by identifying the defective module and replacing it through the Module Exchange Program MEP Alternatively the operator can troubleshoot to the component level and replace the defective part This section of the manual provides the necessary information for both repair methods After any module repair or replacement the adjustments or actions described in the paragraphs particularto the module should be completed followed by the appropriate performance tests Signal generator problems are generally caused by operator error out of specification performance or by catastrophic failure The correction strategy is different in each case Although most operator errors are detected and indicated some are not and may be mistaken for out of specification conditions Rather they may be operator errors that are indicated by either a steady or flashing STATUS indicator or by the REJ ENTRY indicator The signal generators s specifications are in Table 1 3 Referto the Operator Manual for operating information Out of specification performance is usually corrected by performing the appropriate calibration procedure Refer to Section 3 CLOSED CASE CALIBRATION Use the performance tests Section 4 PERFORMANCE TESTS to determine which parameters need adjustment If the problem is not an operator error and is not corrected by calibration the signal generator has had a catastrophic failure The task is then to isolate the fault and mak
233. al check the power supplies Use the I O diagnostic tests described in the A13 Controller troubleshooting section to continuously write data to the display latches Verify that the correct data is written to each latch and is present at the outputs of the display drivers The display blanking output of U11 pin 13 should remain high while the data is written As the edit knob is rotated the window and trigger signals should generate transitions on the input signals to U18 resulting in an interrupt at U12 pin 12 Ifthe signals do not change as the knob is turned suspect the opto interrupters on the A19 switch PCA or the interconnection with the switch PCA Two special function service tests are available to test the front panel indicators and keys Special function 901 checks the front panel displays by lighting all segments The test is exited by pressing any key Special function 902 initiates the key check As each key is pressed its identifier code is displayed in the center ofthe FREQUENCY display field The key identifier codes are assigned in order from top to bottom and from left to right This test is exited by a clear entry 6B 11 6B 12 Section 6C Frequency Synthesis FREQUENCY FAULT TREE 6 1 The Frequency Synthesis Fault Tree Figure 6C 1 is the starting point for trouble shooting frequency related problems SUB SYNTHESIZER BLOCK DIAGRAM 6 2 Refer to the Sub Synthesizer Block Diagram Figure 6 2 to identify t
234. al to analog converter The multiplying factor of this DAC corresponding to the programmed percentage of modulation is calculated by the A13 Controller PCA The modulation signal from the AM DAC is summed with a fixed DC reference voltage The composite signal DC plus modulation is applied to the level DAC a level control multiplying DAC The multiplying factor for this DAC is also handled by the A13 Controller PCA and corresponds to the programmed signal level The multipling factor also includes the level correction information stored in the compensation memory The operation of the ALC loop causes the amplitude of the RF signal to conform to this varying control voltage thus causing amplitude modulation of the signal generator output Pulse Modulation 2 12 Pulse modulation is accomplished by a single pole single throw GaAs FET switch located at the input to the output amplifier This switch can be driven by the internal modulation oscillator or by an external signal The GaAs FET switch provides a very fast and high ON OFF ratio RF pulse 2 5 THEORY OF OPERATION 2 6 Internal Modulation Oscillator 2 13 The modulation oscillator is made up of two sections a periodic wave generator and pulse generator Both functions are implemented in a custom integrated circuit and are synthesized from the main reference frequency source of the 6080A AN The periodic wave generator frequency can be set from 0 1 Hz to 200 kHz with re
235. and need not be removed 2 Remove the 6 screws holding the PCA Carefully remove the Mod Oscillator PCA Removing the A 8 Output P 5 1 1 WARNING THE SYNTHESIZER MODULE WHICH MUST BE RAISED TO GAIN ACCESS TO THE A8 OUTPUT PCA IS HEAVY WHEN RAISING OR LOWERING THE MODULE OBSERVE THE PROCEDURE DESCRIBED UNDER THE HEADING INTRODUCTION AND SAFETY EARLIER IN SECTION 5 Raise the synthesizer module Disconnect RF cable W15 from the connector at the back of the output module and remove the nut and lockwasher from the connector Lower the synthesizer module 5 5 ACCESS PROCEDURES 5 6 Remove the 6 screws holding the bottom output module cover and remove the cover The number 10 screws are adjustment access screws and need not be removed Disconnect the RF cable which is part of the A8 Output PCA from the A10 Premodulator PCA Disconnect the two Mod Control Output ribbon cables W33 and W35 from the Output PCA Remove the 6 screws holding the Output Amplifier cover and remove the cover Remove the 6 screws holding the Output Barrier Remove the remaining 6 screws holding the PCA Do not remove the 4 screws that are in the output amplifier area 10 Carefully remove the A8 Output PCA Removing the A9 Sum Loop VCO PCA 5 12 1 4 Remove the 6 screws holding the bottom output module cover and remove the cover The number 10 screws are adjustment access screws and need not be removed
236. aph 3 14 A3 Sub Synthesizer VCO PCA 6 5 Adjustments R106 on Sub Synthesizer PCA See paragraph 6C 9 A compensation data EPROM containing VCO tuning data is included See paragraph 6C 21 for data transfer instructions A4 Sub Synthesizer PCA 6 6 Adjustments R106 See paragraph 6C 9 Perform Reference Oscillator Calibration See paragraph 3 14 A5 Coarse Loop VCO PCA 6 7 Adjustments None Perform Coarse Loop compensation See Appendix H A6 Mod Oscillator PCA 6 8 Adjustments None AT Relay Driver PCA 6 9 Adjustments None A8 Output PCA 6 10 Adjustments R28 detector offset linearity See paragraph 6D 13 Mod Control PCA R20 RF Level adjustment See paragraph 6D 15 Mod Control PCA RIO AM Depth adjustment See paragraph 6D 14 Mod Control PCA R96 016 Bias adjustment See paragraph 6D 21 Output A compensation data EPROM containing Output PCA level correction data is included See paragraph 6 21 for data transfer instructions A9 Sum Loop VCO PCA 6 11 Adjustments R51 and C7 AM Bandwidth adjust See paragraph 6D 20 Premodulator PCA Perform Sum Loop compensation See Appendix H 6 5 TROUBLESHOOTING AND REPAIR 6 6 A10 Premodulator PCA 6 12 Adjustments R51 and C7 AM Bandwidth adjust See paragraph 6D 20 A11 Modulation Control PCA 6 13 Adjustments R28 detector offset linearity See paragraph 6D 13 R20 RF Level adjust See paragraph 6D 15 R10 AM Depth adjust See
237. arrier RESIDUAL FM RMS in 0 05 to 15 kHz lt 20 Hz SSB PHASE lt 130 dBc Hz 20 kHz offset for Frequency lt 512 MHz lt 124 dBc Hz 20 kHz offset for Frequency gt 512 MHz RESIDUAL AM 0 05 to 15 kHz Band 80 dBc 01 AMPLITUDE MODULATION 3 DIGIT DISPLAY Amplitude 0 dBm INDICATED DEPTH RANGE 0 to 99 9 RESOLUTION tre ted 0 196 ACCURACY 0 to 90 7 AM at 1 kHz rate DISTORTION 5 Total Harmonic Distortion THD 50 AM rates 0 1 1 10 kHz BANDWIDTH 3 10 Hz to 100 kHz INCIDENTAL 200 Hz at 1 kHz rate 5096 AM FREQUENCY MODULATION 3 DIGIT DISPLAY DEVIATION 0 to 999 Hz 1 to 9 99 kHz 10 to 99 9 kHz 100 to 999 kHz 1to4 MHz EXT RATES DC to 100 kHz 1 5 INTRODUCTION AND SPECIFICATIONS 1 6 Table 1 3 6080A AN Specifications cont DEVIATION t DEV RF Frequency rates 1 1 50 kHz 010 1 kHz min Frequency lt 1 MHz Oto 10 kHz min 1 MHz lt Frequency lt 32 MHz to 100 kHz 32 MHz lt Frequency lt 128 MHz Oto 1 MHz min Frequency 128 MHz RESOLUTION 3 digit
238. arse Loop PCA 5 6 A WARNING THE SYNTHESIZER MODULE WHICH MUST BE RAISED TO GAIN ACCESS TO THE A2 COARSE LOOP PCA IS HEAVY WHEN RAISING OR LOWERING THE MODULE OBSERVE THE PROCEDURE DESCRIBED UNDER THE HEADING INTRODUCTION AND SAFETY EARLIER IN SECTION 5 Disconnect RF cables W6 W7 and W15 from the connectors at the rear of the synthesizer module and remove the nuts and lockwashers from the connectors 2 Raise the synthesizer module Remove the 6 screws holding the bottom synthesizer module cover and remove the cover 4 Remove the plug in capacitor and resistor which between the A22 Delay Cable assembly and the A2 Coarse Loop PCA NOTE When reinstalling Cl be certain to put it between JI on the A22 Delay Cable assembly and J9 on the A2 Coarse Loop 72 on A22 and J10 on the A2 PCA are not used 5 Remove the 6 screws holding the heatsinks on U305 and U310 and remove the heatsinks Remove the 6 screws holding the PCA 7 Carefully remove the A2 Coarse Loop PCA Removing the A3 Sub Synthesizer VCO PCA 5 7 A WARNING THE SYNTHESIZER MODULE WHICH MUST BE RAISED TO GAIN ACCESS TO THE A3 SUB SYNTHESIZER VCO PCA IS HEAVY WHEN RAISING OR LOWERING THE MODULE OBSERVE THE PROCEDURE DESCRIBED UNDER THE HEADING INTRODUCTION AND SAFETY EARLIER IN SECTION 5 1 Disconnect RF cable W13 from the connector at the front of the synthesizer module and remove the nut and lockwasher from the con
239. as in the preceding paragraph the voltage at TP8 would be 1 3 0 5 DC In the unleveled state the voltage at TP8 should be greater than 11V DC If the instrument is working properly signal levels between the modulator and the detector are typically as noted in Table 6D 3 Ifthe voltage at TP8 is high the AC voltages will be high unless something is wrong with this part ofthe circuitry Any DC voltage discrepancies should be investigated as indications ofthe problem If high AC voltages are measured the unleveled problem is now most likely with the detector diode CR20 on the Output PCA or with U7 or U41 and associated circuitry on the Modulation Control PCA Output Assembly Test Point Signal Information 6D 9 Table 6D 4 presents the nominal characteristics ofthe signals at the various test points on the Modulation Control PCA The table shows the range of the signal and the expected value for the instrument preset state SPCL 01 Table 6D 3 Modulator Detector Nominal Voltages VOLTS DC VOLTS AC 88 MHz CR31 cathode 15V 180 mV CR28 anode 12V 12V Q5 collector 7 5V 270 mV p p U8 output 5 5V 600 mV p p Q1 collector 9 5V 1 25V CR5 anode TON 1 25 CR14 cathode 7V 12V CR17 anode 7V 1 15V NOTE Measured with a 10 MQ 8 pF oscilloscope probe with short ground Table 6D 4 A11 Modulation Control PCA Test Points TYPICAL TEST SIGNAL FOR POINT TYPE RANGE SPCL
240. at the sum loop The multiplying FM DEV DAC 034 is under controller operation to produce a vernier output within each range or over range in fixed range or variation of nominal reference of 3600 counts out of 4096 for closed case calibration The comparators U16C and U16D with associated resistors serve to trigger one shots U26A and U26B to provide information that the applied external level has a peak amplitude centered around 1 V AC peak The controller responds to deviation from 1V AC peak to alert the operator with front panel indicators for a HI or LO indication FM Steer Voltage Generation 6E 10 The FM Steer signal is derived in DAC p o U32 and op amp U36B and ranges between 0 and 10 2 V DC nominally 5 1V DC The variable resistor R101 is used to adjust this range The level is under control ofthe controller for zeroing the frequency offset in DCFM FM Control Signals Generation 6E 11 The control signals for the FM OSC PCB A14 are sent by the controller and latched in U35 The signals are e Three Range switches FMRN2H FMRNIH and FMRNOH e Four controls DCFMH LOWFMH PMODH and HRPMH FM TROUBLE SHOOTING A14 FM troubleshooting is divided into in three parts e Frequency Check Modulation Check Input Signals and Control Input Checks Frequency Check divider frequencies Table 6E 3 FM Oscillator Frequency Check Table Normal Operation TROUBLESHOOTING AND REPAIR FREQUENCY AND PHASE MO
241. ator 8 is at TTL level and is at 1 kHz the set modulation frequency Ifthe MSB is not as indicated it is probable that the most significant lookup table U2 is faulty Another possibility is that 01 phase accumulator section does not function correctly 3 Next use the oscilloscope to verify the presence of a 10V 5 sine wave at the output of the wave reconstruction DAC TP2 If not suspect the DAC U7 and the DAC output amplifier U9A or the wave tables U2 U3 If the signal is not zero centered or the amplitude is in error check R4 and R5 also verify 10V 2 at pin 4 of U7 4 Verify that a 4 77V p p 5 sine wave is present at TP3 If the sine wave is not present or is of the wrong amplitude check the 3 pole low pass filter components R6 C13 C14 L1 and R7 5 Enter MOD FREQ of 100 kHz 6 Repeat step 4 above 7 Enter MOD FREQ of 1 kHz TROUBLESHOOTING AND REPAIR INTERNAL MODULATION OSCILLATOR 8 Using an oscilloscope check for the presence of a 2V p p sine wave at TP4 and measure its amplitude with an AC voltmeter to verify it is 0 7071V rms within 0 1 40 7 mV If the sine wave is not present or is distorted check S1 S2 U10 and U9B and associated components If amplitude is slightly off recalibrate R9 using normal calibration procedures 9 Using an oscilloscope verify the presence of a 4 66V 4590 sine wave signal at and check for visible distortions Ifthe sine wave is n
242. b to adjust the level until the measured level matches the target level When the remote procedure is performed the process is under the control of a program running on an IEEE 488 bus controller CLOSED CASE CALIBRATION The front panel display is reconfigured during the procedures The target level is displayed in the modulation field the RF frequency is displayed in the frequency field the adjustment value is displayed in the amplitude field and the CAL annunciator is lit The display is consistent for the front panel and remote procedures All adjustments update a temporary copy of the adjustment value The copy in the calibration memory is updated only after the store command is given explicitly After the store command has been given the internal calibration factor is calculated from the displayed adjustment value and is stored in the calibration memory Subsequent amplitude programming commands use the new calibration factor NOTE Set the rear panel CAL COMP switch to the 1 on position before initiating the calibration procedures Front Panel Level Calibration Procedure 3 12 The front panel level calibration procedure is initiated by the following key sequence The display is reconfigured for the procedure Several of the front panel controls are disabled or operate differently than they normally do Table 3 5 shows all ofthe active controls and describes their function while performing the front panel l
243. by a 20 MHz two phase clock generator U21 U22 The input frequency to the rate multiplier is 20 MHz The output frequency can be programmed from zero to 19 995 MHz in 5 kHz steps This signal is ORd with the other phase ofthe 20 MHz clock to produce 20 to 39 995 MHz at U23 pin 1 The signal is also divided by 2 in U23 by 10 in U60 and again by 100 in U61 to produce 10 to 19 99975 kHz in 2 5 Hz steps Not all of this resolution is utilized This TTL signal at TP30 18 filtered by L75 1776 C156 C157 C158 C159 and C160 Op amp U59 forms an active quadrature generator such that the signal at output pins 7 and 14 are offset by 90 degrees These two signals are the 10 to 20 kHz inputs for the PLL single sideband mixer DACS AND LATCHES The control bits for the Coarse Loop PCA are latched by U3 part of U9 and 1 10 DAC 05 with op amp U6D provides the steering voltage for the Coarse Loop VCO and DAC U7B with op amp provides the voltage to tune the reference TXCO SUB SYNTHESIZER TROUBLESHOOTING 6 4 Allfrequencies mentioned are synthesized hence they are exact coherent with the 10 MHz reference unless noted as approximate Status code 242 indicates that the Sub Synthesizer and or Sub Synthesizer VCO 18 not functioning properly This status code is triggered when the Sub Synthesizer VCO control voltage is out ofthe normal operating range A status code 244 which indicates that the Sum Loop is out of lock might also in
244. cable from A2 J15 Connect A2 J15 to the spectrum analyzer Set the spectrum analyzer to 80 MHz 1 MHz span and 10 dBm reference level 3 Adjust R617 for 4 dBm 40 2 4 Reconnect the cable to A2 J15 2 MHz Notch Adjustment L205 6C 24 TEST EQUIPMENT Spectrum analyzer REMARKS The 2 MHz Notch Adjustment is normally required only if L205 and associated components have been replaced or when the adjustment has shifted PROCEDURE The 2 MHz signal at the output of the acquisition oscillator is minimized 1 Program the UUT to SPCL 909 2 Program the UUT to 15 25 MHz 3 Connectthe spectrum analyzer to TP6 with clip leads Set the spectrum analyzer to center 2 MHz 100 kHz span and ref level 20 dB 4 As L205 is adjusted inward a signal should be visible on the spectrum analyzer Adjust L205 to minimize this signal TROUBLESHOOTING AND REPAIR FREQUENCY SYNTHESIS Alternate Reference Frequency Selection 6C 25 REMARKS The unit is configured at the factory for 5 MHz external reference when in alternate reference frequency mode SPCL 761 These are the switch settings for 1 2 MHz externalreference PROCEDURE On the synthesizer module bottom cover remove the metal hole plug labeled A2S502 Set the switches as follows REFERENCE 1 2 3 4 5 6 5 MHz on on off off on off 2MHz off off on on off off 1 MHz off on off on off on COARSE LOOP VCO A5 CIRCUIT DESCRIPTION 6C 26 The A5 Coarse Loop VCO is con
245. cessor vivet E E ee ENS NEED hell 6B 1 6B 4 22252 he aati teo Mee Ies 6B 1 6B 5 Memory Control SG AGES IS Ie EE 6B 3 6B 6 Front Panel 6B 3 6B 7 488 1 6 3 8 Attenuator Control 6B 3 6B 9 Module ozone Sr eo St bn ied 6B 3 6B 10 Status and 6B 4 6B 11 DIGITAL CONTROLLER TROUBLESHOOTING 6B 4 6B 12 12388 eai S ette este tenet al 6B 4 6B 13 Microprocessor 6B 5 6B 14 CIOCKS o Se Pens rS Sedes museo EAD 6B 5 6B 15 Powet On Reset 52 tried 5 6B 16 Unused Microprocessor 5 6B 5 6B 17 BUS EOE mei eeu Spe Prete At ead Pe GB nts en 6B 5 6B 18 b oe Re qur d 6B 5 6B 19 Microprocessor 5 6B 6 6B 20 Address Decoder errs oett Rem es em reet kt tet gos 6B 6 6B 21 I O Diagnostic 5 6B 7 68 22 CALIBRATION COMPENSATION MEMORY 6B 8 6B 23 Calibration Compensation Memory 5
246. circuitry or the phase detector loop amplifier If the voltage is approximately 13V this indicates a problem in the 40 MHz oscillator buffers dividers or phase detector loop amplifier Ifthe voltage at TP19 is approximately 13V first check the 40 MHz oscillator When measuring signals with an oscilloscope all voltages are approximate Use a 10 Meg 8pf probe Make a ground connection at the probe tip with less than 1 inch lead There should be a 40 MHz signal 1 4V p p at TP4 All frequencies are not exact because the reference loop is not locked and will typically be slightly higher than indicated After the buffers at the L605 C624 C625 and L605 C617 C625 junctions this signal should be 630 mV p p After the ECL buffer at U602 pin 2 there should be a 40 MHz ECL signal At TP17 which connects to the Sub Synthesizer A4 there should be a 700 mV p p signal The output of the first divide by 2 U506 pin 15 should be a 20 MHz ECL square wave Following the buffer U513 that supplies the modulation oscillator A6 there should be a 20 MHz 1 2V p p signal at TP17 There should be a 10 MHz ECL square wave at U506 pins 2 and 3 At the collector of Q505 there should be a 10 MHz TTL signal At J7 the 10 MHz Reference Out there should be a 10 MHz 5V p p sine wave When in internal or external 10 MHz reference REFSEL should be a logic high There should be a 10 MHz TTL signal at the phase detector input U503 pin 11 When TROUBLESHOOTIN
247. control the wave form selection allowing up to eight waveforms to be selected via a front panel special function When a wave other than the sine wave is used consideration for the low pass filter cutofffrequency 200 kHz should be made There will be a progressive deterioration of the fidelity of waves with increased frequency depending on the wave shape selected This relates to the higher frequency components of the waves other than sine wave Pulse Generator 6F 4 The pulse generation mode is selected via front panel or IEEE Special Function commands The frequency of the pulse generator can be set from 10 Hz to 200 kHz Frequency and pulse width are determined by numeric values written to the oscillator The built in pulse generator can be used as a modulation source for the internal AM FM and pulse The pulse generator is based on the custom IC U1 which contains a programmable period and pulse width sections Both the period and the width ofthe pulse can be set in increments of 100 ns Internally the pulse frequency is rounded and set to the nearest 100 ns period increment of the entered modulation frequency U4 05 01 Q2 and associated components provide conditioning for the external and internal pulse signals When in the pulse generation mode of operation the internal pulse at INT MOD is presetto 1V pk via U5 U4 buffers the pulse output ofthe custom IC U1 to provide MOD OUT which is fixed at 4 5V CMOS TTL logic level
248. cribed under SOFTWARE DIAGNOSTIC FUNCTIONS in Section 6 Enter Special Function 903 to initiate the latch test Use an oscilloscope to inspect the chip select signals at the inputs and at the outputs of buffers U24 and U25 The first symptom to look for is totally inactive signals or invalid logic states If there are no chip select signals present at the inputs of U23 refer to Address Decoding later in Section If all of the chip select signals are operating correctly connect a scope probe to the signal BSELOL and use the high to low transition ofthe signal to trigger the scope Use another probe to inspect the data and address signals buffered by U24 U25 U27 and U33 during the low period of BSELOL Look for inactive signals and invalid logic states Also compare the buffer inputs to their outputs Press the STEP 57 key then the STEP key to toggle each of the data signals In addition make sure that the buffer control signals are low active TROUBLESHOOTING AND REPAIR DIGITAL CONTROLLER Ifthe signals pass the above tests check the data and address signals at any suspicious latch or DAC on the suspect RF circuit board If a DAC problem is suspected use special functions 941 942 and 943 which set all DACs to zero half scale and full scale respectively Microprocessor Kernel 6B 13 A blank front panel is a symptom of many controller related problems Micropro cessor related problems are difficult to troubleshoot becau
249. ct hardware failures If the required adjustment exceeds the procedure s adjustment limits the signal generator needs repair and CIRCUIT DESCRIPTIONS TROUBLE SHOOTING AND ALIGNMENT in Section 6 should be consulted 3 1 CLOSED CASE CALIBRATION 3 2 Front Panel Calibration 3 2 The bright digit editing feature is used to perform the adjustments when performing a front panel calibration procedure Each calibration subsection describes the function of the front panel controls during the procedure Remote Calibration 3 3 The remote calibration procedures allow the signal generator to be calibrated in a totally automated station When equipped with the required measurement equipment and controller software the process is reduced to connecting the instrument cables and executing the program The controller and signal generator work together in a tightly coupled system The sole function of the controller software is to obtain valid readings from the measurement equipment and convert them into a format understood by the signal generator The controller software must ensure that every reading is settled and valid before sending it to the signal generator The basic structure of a calibration program is shown in Figure 3 1 Initiate 6080A AN calibration procedure Initialize measurement equipment Loop Ask 6080A AN for RF frequency Exit loop if frequency is special end code 9E 09 Get reading from measurement equipment Send
250. cted to the RF input of the mixer The delay cable is trimmed so that when the coarse loop steps in 8 MHz increments the phase is such that the IF output is approximately at DC A filter C418 421 1 403 4 R419 420 is connected to the IF port This filter provides both UHF and HF terminations for the mixer The output ofthe filter is AC coupled C101 R106 to a low noise amplifier Q101 106 The output of this amplifier is resistively summed R123 R125 with the phaselock voltage from U206 Diodes CR101 2 limit the output of the discriminator amplifier while in the acquisition mode To ensure stability the gain of the low noise amplifier is rolled off C104 R119 COARSE LOOP TROUBLESHOOTING 6C 16 6 22 The Coarse Loop A2 be broken up into two sections the reference section and the main coarse loop These sections can be treated independently REFERENCE SECTION A status code 246 indicates a problem in the reference section Ifthe unit is in external reference and there is no reference supplied or if the reference is the wrong frequency or is outside of the lock range specification a status code 246 will be displayed If the unit is in internal reference and the high or medium stability option is installed check to see that the 10 MHz output from the option is correct Measure the voltage at TP19 If this voltage is approximately 13V this indicates a problem with the internal TCXO the internal external reference
251. d Connect the UUT to the Device Under Test port of the VSWR bridge e Step the HFSSG from 10 to 1024 MHz in 10 MHz steps Locate the frequency at which the reflected signal is maximum and record this level f Disconnect the UUT from the VSWR bridge and record the new level g Calculate the return loss between the two recorded levels The difference must be at least 7 5 dB 7 5 dB of return loss 2 2 5 1 VSWR PULSE TESTS 4 16 The Pulse Tests check the static and dynamic operation of pulse modulation REQUIREMENTS Proper pulse operation is tested by checking that Static on off ratio greater than 35 dB Dynamic rise and fall time 1 microsecond TEST EQUIPMENT 4 24 RF spectrum analyzer Pulse generator Power meter Power sensor high level 50 Ohm termination Oscilloscope Detector PERFORMANCE TESTS NOTE The following procedures must be performed in the order described below to ensure that the proper equipment is connected and appropriate programs are enabled PROCEDURE 1 Static Test a b Program the UUT to 1024 MHz and 10 dBm Connect a 50 ohm termination to the pulse modulation input connector Connect the UUT RF OUTPUT to the RF spectrum analyzer input Set the RF spectrum analyzer controls to display the output ofthe UUT using a span of approximately 0 5 MHz to 1024 MHz Activate pulse modulation by pressing the External Pulse key on the UUT Observe the level change on the RF spectrum a
252. d by verifying their checksums The non volatile RAM is tested by verifying the checksum of each memory location Communication with the IEEE 488 interface IC is verified by writing data to the IEEE 488 talker listener IC U28 then reading it back Table 6 3 Digital Test Results CODE DESCRIPTION 302 Calibration Compensation memory checksum test failed 303 RAM test failed 304 EPROM test failed 305 Non volatile memory test failed 306 IEEE interface test failed AM Tests 6 25 The AM Tests program normal and overmodulation conditions and then check the state of the ALC loop leveled indicator Table 6 4 lists the test conditions Table 6 4 AM Test Conditions EXPECTED STATE CODE AM DEPTH AMPLITUDE OF ALC LOOP 307 30 0 13 7 dBm Leveled 308 0 0 16 0 dBm Leveled 309 gt 99 9 gt 20 0 dBm Unleveled RF Frequency 1055 MHz Mod Frequency 1 kHz Internal AM On FM Tests 6 26 The FM Tests program normal and overmodulation conditions and then check the state of the FM loop lock indicator The locked condition is expected in four of the FM bands and once with the Low Rate FM mode enabled The unlocked condition is expected when a very wide deviation is programmed at a low modulation rate Table 6 5 lists the test conditions oM Tests 6 27 The Phase Modulation Tests verify that the FM loop remains locked when two valid phase modulation settings are programmed The first test is perfor
253. dBm and for F gt 512 MHz INTRODUCTION AND SPECIFICATIONS Table 1 4 Typical Signal Generator Performance cont 2 dB from 19 to 100 dBm and for from 0 01 to 0 4 MHz 3 dB from 100 to 127 dBm and for F from 0 01 to 0 4 MHz SOURCE lt 1 51 for levels below 1 dBm lt 2 0 1 elsewhere FLATNESS 23 590 0 5 dB 10 dBm F 0 1 MHz FLATNESS 0 to 50 0 75 dB 10 dBm F gt 0 1 MHz SPECTRAL PURITY CW ONLY NON HARMONIC SPURIOUS lt 100 dBc for offsets greater than 10 KHz NOTE Fixed frequency spurs lt 100 dBc or lt 140 dBm whichever is larger NOTE dBc refers to decibels relative to the carrier frequency orin this case relative to the signal level 30 dBc for levels 13 dBm lt 25 dBc for levels lt 16 dBm POWER LINE 6 lt 50 dBc within 10 kHz of carrier RESIDUAL FM RMS in 0 3 0 2 Hz for 01 to 15 MHz Band to 3 kHz band 0 2 Hz for 15 to 32 MHz Band 0 2 Hz for 32 to 64 MHz Band 0 2 Hz for 64 to 128 MHz Band 0 2 Hz for 128 to 256 MHz Band 0 5 Hz for 256 to 512 MHz Band lt 1 Hz for 512 to 1056 MHz Band RESIDUAL FM RMS in 0 0
254. dated after the store command is given explicitly After the store command has been given the internal calibration factor is calculated from the displayed adjustment value and is stored in the calibration memory NOTE This procedure can be used only to adjust thefrequency ofthe internal reference oscillator It cannot be used to adjust the frequency of the optional high stability or medium stability references CLOSED CASE CALIBRATION NOTE The rear panel CALICOMP switch must be set to the 1 on position before initiating the calibration procedures Front Panel Reference Oscillator Calibration Procedure 3 15 The front panel reference oscillator calibration procedure is initiated by the following key sequence se 118 The display is reconfigured for the procedure Several ofthe front panel controls are disabled or operate differently than they normally do Table 3 7 shows all ofthe active controls and describes their function while performing the procedure Table 3 7 Front Panel Controls for Reference Oscillator Calibration Procedure CONTROLS FUNCTION AND DESCRIPTION Bright Digit Editing KNOB Turn the edit knob to adjust the reference oscillator calibration factor Use the left right arrow keys to move the bright digit within the adjust ment field The bright digit is always located in the adjustment field RF on off Toggles the RF output on off Overrange uncal or Rejected Entry Status Normall
255. de the oscillator runs with the highest Q As deviation is increased a linearizer is added to maintain low distortion which somewhat reduces spectral purity At higher deviations the tuning sensitivity of the oscillator is increased again causing a somewhat higher phase noise At this deviation the linearizer is used to maintain low distortion The phase lock circuit runs off of various reference frequencies depending on the deviation selected To provide a large amount of deviation at low rates a very wide range phase detector is used in the wide deviation ACFM mode Full deviation can be used down to an FM rate of 100 Hz An alternate mode of operation that uses the lowest reference phase detector frequency and the wide range phase detector for all deviations will allow very low modulation rates for less than maximum deviation In DCFM mode full deviation can be used down to DC levels The generator is not however locked to the main timebase in this mode When DCFM is enabled the FM oscillator s center frequency is set to the previous locked center frequency 1 kHz by automatic zeroing circuitry in conjunction with the software routine Phase Modulation 2 9 Phase modulation M is programmable with three digits of resolution in six ranges Phase modulation is internally normalized to 10 kHz then programmed as FM deviation The M index is multiplied by 10 kHz regardless of the modulation frequency to get the equivalent FM deviat
256. dicate a problem with the Sub Synthesizer and or Sub Synthesizer VCO 6C 9 TROUBLESHOOTING AND REPAIR FREQUENCY SYNTHESIS 6C 10 Status code 244 appearing without status code 242 might indicate a marginal break up condition To check the Sub Synthesizer across the band move the jumper on the Sub Synthesizer VCO from TPI TP2 to TPI TP3 This allows the Sub Synthesizer VCO frequency not divided to appear at A3 J2 Connect this output to a spectrum analyzer Program the signal generator to 800 MHz There should be a stable signal at 160 MHz displayed on the spectrum analyzer Step the signal generator in 200 steps while stepping the spectrum analyzer in 4 MHz steps At each point a stable signal should be displayed on the spectrum analyzer If the signal shows evidence of breaking up there is a problem with the Sub Synthesizer and or Sub Synthesizer VCO If there is a status code 242 check to see ifthe VCO control voltage is stuck high low A good way to do this is to measure the DC voltage at TP27 This test point can be accessed without removing the module cover If the DC voltage is around 1 5V the problem is in the circuitry that supplies the 1 MHz reference or in the phase detector circuit if it is around 23V the problem is associated with the whole phase lock loop VCO SSB mixer divider Table 6C 1 shows the characteristics of the signals at the various test points on the Sub Synthesizer PCA The table g
257. displays a list of codes that specify which checksums failed The list can be scrolled by pressing the key If all checksums are valid the code 00 is displayed Refer to Appendix E for a complete list of the checksum status codes The most likely failure mode would either be a defective EEPROM or battery backed RAM IC that would show failures of all the checksum error codes for that IC Replace the defective IC and refer to Repairing Calibration Compensation Memory Checksum Errors later in Section 6B In addition to checksum error codes there are codes that indicate when the checksums are valid but a byte by byte comparison of the data segments reveals that they are different This unusual condition is likely to occur only if one ofthe two calibration compensation memory ICs have been swapped between controller boards Although this situation rarely occurs it is important to detect the condition so corrective action can be taken The data comparison codes are included with the checksum status codes in Appendix E TROUBLESHOOTING AND REPAIR DIGITAL CONTROLLER Repairing Calibration Compensation Memory Checksum Errors 6B 24 Special Function 907 attempts to repair all invalid data segments reported by the calibration compensation memory status command Special Function 907 can be used to repair an error in an individual data segment or to initialize a new EEPROM or battery backed RAM IC following the replacement of a defective part NOTE
258. divider is functional check the mixer amplifier 0205 and 0206 The collector bias at C273 is approximately 8V At TP5 there should be a 40 MHz 1 2V p p signal The output of the filter TP11 should be a 500 mV p p slightly triangular signal The frequency will be a function ofhow close the RF signal is to 650 MHz but less than 125 kHz Reenable the search oscillator by removing the ground from TP28 TP13 Ground TP11 There should be a 100 Hz 10V p p sine wave 0V DC at TP6 Program the UUT to SPCL 943 This programs the DACS to full scale which turns Q201 Q204 on There should be a 100 Hz 650 mV p p sine wave at TP7 Clear the UUT Remove the jumper between TP7 and ground The loop should be locked If the loop still does not lock ground TP9 If the loop locks the problem is in the delay line discriminator section If the loop 18 locked and there still is a status code 243 check the unlock detector U204 Ifthe phase noise ofthe UUT is not within specified limits the problem could be in the discriminator section First measure the DC voltage at TP1 on the Discriminator PCA A25 It should be 100 mV as the RF frequency is changed If the voltage is nearly zero remove the semi rigid cable connecting to 710 and measure the power with the spectrum analyzer It should be between 9 and 14 dBm depending on the RF frequency If there is no power or the power is low check the RF power amplifier levels 0404 0405 against Table 6C 5 using the 5
259. e appropriate repairs The STATUS and Self Test failure codes usually provide a good indication ofthe cause of the problem See Appendix E and Sections 6A through 6F In case of catastrophic failure use the performance tests to help isolate the problem The Instrument Block Diagram Figure 6 1 and the Instrument Troubleshooting Tree Figure 6 2 will help to isolate the problem to a specific section 6 1 TROUBLESHOOTING AND REPAIR Lov Y 92 Sev 9510 AV 13g ZHN 9L ev 1ndinO 701 087 H3ZIS3H1NAS ZHN vzo 0180 ans Indino IMINO 45 8001 WNS ZHW 026 NI 43H 094 JOYLNOO H3ZIS3HINAS OOA ans dOO 3Suvoo 40017 WNS ZHW 201 067 3GISNI ZHW 966 948 1 050 GOW 1 11050 LNO 250 GOW 9v 91 OSO GOW INI SIV 13Nvd HV3H 13NVd LNO 950 GOW Figure 6 1 Instrument Block Diagram 6 2 TROUBLESHOOTING AND REPAIR INSTRUMENT DOES NOT For proper operation see Section 4 MEET SPECS of the Operators Manual For verification of the specifications see Section 4 of the Service Manual CHECK POWER SUPPLY Sec 6a MINOR SPEC PROBLEM no error codes MAJOR PROBLEM PREFORM
260. e 1 4 Typical Signal Generator Performance cont TRIP RESE I oh eem Flashing RF OFF annunciator indicates a tripped condition Pushing RF ON OFF button will reset signalgenerator IEEE 488 INTERFACE FUNCTIONS SH1 T5 L3 LEO SR1 PPO DT1 and E2 INTERNAL MODULATION SOURCE SINE WAVE eet 0 1 Hz to 200 kHz synthesized sine wave FREQUENCY ACCURACY Same as reference 7 mHz DISPLAY RANGES 00 1 to 99 9 Hz 100 to 999 Hz 1 00 to 9 99 kHz 10 0 to 99 9 kHz 100 to 200 kHz FREQUENCY RESOLUTION 0 1 Hz or 3 digits OUTPUT LEVEL RANGE 0 to 4V peak into 600 ohms OUTPUT LEVEL RESOLUTION 3 digits or 4 mv peak whichever is larger 5 lt 0 15 THD for output levels gt 2V peak and mod frequency 20 kHz OUTPUT LEVEL ACCURACY 4 15 mV for mod frequency 100 kHz OUTPUT IMPEDANCE 600 ohms 2 OTHER WAVEFORMS AVAILABLE BY SPECIAL FUNCTION Square Wave Fmod 2 kHz Triangle Wave Fmod 5 kHz EXTERNAL MODULATION INPUTS 1V peak provides indicated modulation index Nominal input impedance is 600 ohms Maximum input level is 5 V peak MODULATION MODES Any combination of AM PULSE and FM or internal or ext
261. e Assembly 5 19 1 2 3 5 8 A WARNING THE SYNTHESIZER MODULE WHICH MUST BE RAISED TO GAIN ACCESS TO THE A22 DELAY CABLE ASSEMBLY IS HEAVY WHEN RAISING OR LOWERING THE MODULE OBSERVE THE PROCEDURE DESCRIBED UNDER THE HEADING INTRODUCTION AND SAFETY EARLIER IN SECTION 5 Raise the synthesizer module Remove the 6 screws holding the bottom synthesizer module cover and remove the cover Remove the plug in capacitor and resistor which are between the A22 Delay Cable assembly and the A2 Coarse Loop PCA ACCESS PROCEDURES NOTE When reinstalling be certain to put it between 71 on the A22 Delay Cable assembly and J9 on the A2 Coarse Loop J2 on A22 and J10 on the A2 are not used Remove the four 6 screws holding the A25 Discriminator PCA Do not remove the screws holding the clamp that attaches the delay line itself to the PCA Remove the two 6 screws holding the lower delay cable retainer Remove the two 6 screws holding the upper delay cable retainer which holds the A26 Delay Cable PCA in place Do not remove the screws holding the clamp that attaches the delay line itself to the PCA do not disconnect the SMA connector on the semi rigid trim cable Remove the A22 Delay Line assembly 5 9 5 10 Section 6 Circuit Descriptions Troubleshooting and Alignment INTRODUCTION 6 1 The 6080A AN Synthesized Signal Generator also referred to as the signal generator is usually rep
262. e RF path following C180 are replaced This adjustment should be followed by output compensation See Appendix H TEST EQUIPMENT Power meter Tuning tool 025 in square Johanson 74192 PROCEDURE 1 Zero the power meter 2 Program the UUT to SPCL 01 350 MHz and 7 dBm Connect the power meter to the UUT RF output 3 Set the power meter to dB REF 4 Edit the UUT frequency from 15 to 1056 MHz and note the variation in level Adjust C201 to minimize the level variation C201 will have the greatest effect at high frequencies Level should be flat with a maximum allowed variation of 3dB 6D 19 TROUBLESHOOTING AND REPAIR RFLEVEL AM 60 20 FM Gain Adjustment R82 Mod Control 6D 24 See Alignment of FM PCA in Section 6E FM steer Gain R101 on Mod Control PCA 6D 25 See Alignment of FM PCA in Section 6E FM INV Balance R102 on Mod Control PCA 6D 26 See Alignment of FM PCA in Section 6E ATTENUATOR REVERSEPOWERPROTECTION RPP 6D 27 The A20 Attenuator RPP Assembly consists of the A21 Attenuator RPP PCA the 7 Relay Driver PCA and a metal housing The Attenuator RPP PCA is mounted inside the housing and the Relay Driver is attached on top of the housing This assembly is mounted to the Output Module opposite the Output PCA The output signal of the Output PCA at is the input to the Attenuator RPP PCA at J1 The Attenuator section of the Attenuator RPP PCA provides an attenua
263. e at TP19 should range between 13 and 13V Reconnect the jumper between TP20 TP21 The last circuitry to check is the out of lock circuitry U509 U512 U515 With the control voltage between 1 to 11V the signal at J2 2 should be a TTL logic high To troubleshoot the 80 MHz doubler section first check the bias voltages At the junction of R648 C652 and T601 the voltage should be about 8 8V The voltage at the collector of Q610 should be about 8 1V The ac voltage on the collector of Q609 should be 40 MHz 2 7V p p There should be an 80 MHz full wave rectified signal 1 2V p p at the output of the doubler CR601 CR602 At J5 there should be a 80 MHz 0 8V p p sine wave MAIN LOOP A status code 243 indicates the coarse loop is out oflock A status code 244 or possibly 245 which indicates the sum loop is out oflock could possibly be caused by a marginal lock condition in the coarse loop The first thing to check is the coarse loop steering circuit Program the UUT to 544 MHz which programs the coarse loop to 640 MHz Connect the output of the Coarse Loop VCO A2 J8 to a spectrum analyzer Ground the phase lock port TP7 and disable the search oscillator by moving the jumper from TP13 to TP28 TP13 There should be a signal at 640 MHz 2 MHz If the signal is absent or is far off frequency either the Coarse Loop VCO or the VCO steering voltage circuit is faulty The steering voltage circuit can be checked by programming the UUT with S
264. e loop integrator summing amplifier U41 The leveling loop control voltage plus any AM is applied to pin 3 of U41 U41 drives the leveling AM modulator through U14 and U15 and circuits that compensate for modulator non linearity R35 R36 CR5 and CR6 form an additional linearizing network that acts on the control signal Amplitude modulation is achieved by summing an appropriately scaled modulation signal with the DC leveling loop control voltage The amplitude modulator on the Output PCA consists of PIN diodes CR27 through CR33 and associated components Attenuation through the modulator is a function of bias current through these PIN diodes This current is provided by the modulator linearizer circuit on the Modulation Control PCA U14 and associated components provide modulator series diode current while U15 and associated components provide shunt diode current Modulator attenuation is approximately proportional to the modulator control voltage on TP8 Proportionality is required to maintain constant leveling loop bandwidth as modulator attenuation varies Minimum attenuation is obtained with a modulator control voltage of 10V while maximum attenuation is obtained with Comparator U10 and associated components form an unleveled indicator circuit The comparator senses the modulator control voltage at TP8 This voltage is normally less than 11 and the comparator output is high If the modulator control voltage exceeds 11 the m
265. e polarity at TP1 the low frequency loop amplifier output and generates the SUMVOLH signal The controller uses this signal during the sum loop VCO calibration routine 0116 15 a monostable multivibrator that is triggered by the acquisition oscillation at U105 that occurs when the sum loop is unlocked and generates the SUMUNLKL signal This informs the controller that the sum loop is not locked SUM LOOP VCO STEERING CIRCUIT The Sum Loop VCO has two ports for frequency tuning the steering port at J5 and the phase lock port at J6 A coarse tuning voltage generated at the steering port tunes the Sum Loop VCO frequency to the desired value within about 2 MHz The phase lock port is driven by the loop amplifier with enough voltage to compensate for the error in the steering port and sets the Sum Loop VCO frequency to the correct phase locked value The following paragraphs describe the circuit that drives the steering port The SUMSTEER signal at J7 14 is an RF frequency dependent DC voltage that 18 proportional to the required Sum Loop VCO steering port voltage This signal is generated in a 12 bit DAC on the A11 Modulation Control PCA that is programmed by data stored in the controller Note that this data is obtained and stored during the Sum Loop VCO compensation procedure and is unique to a given VCO The SUMSTEER signal is low pass filtered and amplified by U103 and associated components Gain adjustment is provided by R112 The DC volta
266. e provides the following general functions Services the front panel and the IEEE 488 Interface Configures the hardware to produce the required output then applies calibration and compensation data to optimize the performance Implements a set of self test and diagnostic functions User Interface 2 16 The software is implemented with a simple operating system that allows several tasks to operate in a round robin fashion Input and output to both the front panel and the IEEE 488 Interface execute at a higher priority and are handled as interrupt routines At power on the software performs a self test and initializes both the RAM and the RF hardware Four tasks are continuously in operation Diagnostic service task Front panel Key task Knob task IEEE 488 task THEORY OF OPERATION The diagnostic service task monitors the instrument status signals The front panel key task knob task and IEEE 488 task process user input A fifth task controls the RF output when a frequency or amplitude sweep is active A sixth task is activated only when needed to process certain STATUS out of range or malfunction or REJ ENTRY rejected entry conditions that cause the display to flash A seventh task is activated when the automatic user compensation procedures have been initiated Calibration Compensation Memory 2 17 The calibration compensation memory contains the instrument specific compensation data for the coarse loop compensation DA
267. e selector card that can be plugged in two different ways Plugging the line voltage selector card into one of its two positions allows selecting the line voltage of 115 or 230V AC The secondary windings ofthe transformer are connected to a linear DC power supply assembly that provides the instrument with the supplies shown in Table 6A 1 NOTE The front panel power switch does not break the AC line power or the transformer secondary The power supply and some other parts of the instrument such as the display assembly arepowered while the lineplug is energized In the standby mode power switch is off the active supplies are the 23 4V and the display filament lines In addition various parts of the power supply assembly are energized such as all transformer secondary windings rectifiers and filter capacitors The bridge rectifiers in the power supply are used in either a bridge or full wave center tapped configuration with capacitor input filters Figure 6A 1 shows the rectifier configurations as well as the component designations for the various supplies 6A 1 TROUBLESHOOTING AND REPAIR POWER SUPPLY 3 1N3WVJI4 AU v 91H90 2 2 en 05 100 318VN3 AV1dS10 AZ 100 an ASh 1no NI tnv t on LUANI 338A 1no NI 1 ASQNV IS E
268. ectrum analyzer is adjusted to 10 dBm as displayed on the spectrum analyzer This corresponds to 10 dBm at the input to the coupler 1 Program the UUT to SPCL 909 2 Program the UUT to 800 MHz 3 Connectthe 10X RF probe to the input ofthe spectrum analyzer Set the spectrum analyzer to 5 dBm reference level 160 MHz 1 MHz span and 1 dB div 4 Touchthe probe tip to input ofthe coupler U52 that connects to C147 This is best done on the top of the coupler with the ground connection on the coupler ground plane 5 Adjust R106 for 10 dBm as displayed on the spectrum analyzer 10 kHz Notch Adjustment L56 6C 10 TEST EQUIPMENT Spectrum analyzer REMARKS The 10 kHz Notch Adjustment is normally required only when L56 L57 and associated components have been replaced or the adjustment has shifted PROCEDURE A signal from the internal modulation oscillator is injected into the Sub Synthesizer phase detector to produce a 10 kHz spur 1 56 is adjusted to minimize this spur 1 Program UUT to SPCL 909 2 On Sub Synthesizer VCO move jumper near J2 from TPI TP2 to 1 Replace the cover on this side of the module 3 Program the UUT to 800 MHz Modulation Frequency 10 KHz Modulation Level to 100 mV Connect the front panel mod out to TP36 on Sub Synthesizer PCA 4 Setspectrum analyzer to center 160 MHz reference level 5 dBm frequency span 100 kHz The signal should be visible in the center of the scr
269. een with 10 kHz sidebands 5 Adjust L56 to minimize these 10 kHz sidebands 6 On the Sub Synthesizer move jumper near J2 back to TP1 TP2 6C 15 TROUBLESHOOTING AND REPAIR FREQUENCY SYNTHESIS SUB SYNTHESIZER VCO A3 CIRCUIT DESCRIPTION 6C 11 The A3 Sub Synthesizer VCO PCA is controlled by the A4 Sub Synthesizer PCA and produces a signal that is further processed in the A12 Sum Loop PCA This assembly includes a varactor tuned oscillator that generates frequencies from 160 to 320 MHz along with low pass filters and an ECL divide by ten circuit QI is configured as an oscillator with a tunable resonant circuit connected between base and collector that provides positive feedback This circuit includes printed transmission lines varactor diodes CR1 CR4 and inductor L1 The frequency tuning voltage at J1 4 is applied to the varactor diodes through RF choke L2 and tunes the oscillator over the range of 160 320 MHz with voltages from about 2V to 22V The oscillator transistor output signal at Q1 emitter 18 next applied to Q2 configured as acommon base stage that provides isolation The 0 dBm output of Q2 is applied to monolithic amplifier U1 which boosts the signal level to 13 dBm at its output Two switched low pass filters including PIN diodes 5 8 and capacitors C13 C22 follow U1 and provide harmonic suppression Comparator 04 senses the tuning voltage VT and enables the low band filter between CR5 a
270. ely 160 to 320 MHz Ifthe frequency cannot be adjusted the problem is probably in the Sub Synthesizer VCO A3 Set the frequency to approximately 240 MHz with the variable power supply Using a spectrum analyzer and the low impedance probe with the 10X attenuator measure the level at the output of U51 A good place to measure this is at the input to the coupler U52 Note that the low impedance probe should be grounded as closely as possible PCA hold down screws and the walls ofthe plate provide good grounds The level at this point should be approximately 10 dBm as measured on the spectrum analyzer Troubleshoot the RF section U50 U51 etc ifthis level is not correct TROUBLESHOOTING AND REPAIR FREQUENCY SYNTHESIS Table 6C 1 Sub Synthesizer PCA Test Points Typical Front panel frequency set to 804 001499 MHz Range Total Sub Synthesizer frequency range 160 320 MHz Front panel from 800 000000 to 807 999999 MHz TEST SIGNAL RANGE TYPICAL FUNCTION POINT TYPE TP2 ground TTL 20MHz 12 5 ns AH Constant 2 phase clock generator TP4 TTL 20MHz 12 5 ns AH Constant 2 phase clock generator TP5 TTL 10 19 98 MHz 19 98 MHz Low order digit gate array output TP6 DC 0 10 23V 2 2V Coarse Loop VCO steering DAC output TP21 TTL 1 MHz 50 ns AL 1 MHz N Divider output TP22 TTL 1 MHz square wave 1 MHz Reference divider output TP23 ground TP24 TTL 1 MHz 10 ns AH 1 MHz Phase detector down output TP25 TTL 1 M
271. emours amp Co Inc DuPont Connector Systems Advanced Products Div New Cumberland PA 24347 Penn Engineering Co 5 Monte CA 24355 Analog Devices Inc Norwood MA 24759 Lenox Fugle Electronics Inc South Plainfield NJ 25088 Siemen Corp Isilen NJ 25403 Amperex Electronic Corp Semiconductor amp Micro Circuit Division Slatersville RI 27014 National Semiconductor Corporation Santa Clara CA 27264 Molex Inc Lisle IL 28213 MN Mining amp Mfg Co Consumer Products Div 3M Center Saint Paul MN 28480 Hewlett Packard Co Corporate HQ Palo Alto CA 30035 Jolo Industries Inc Garden Grove CA 30800 General Instrument Corp Capacitor Div Hicksville NY 31433 Kemet Electonics Corp Simpsonville NC 31918 ITT Schadow Eden Prairie MN 32997 Bourns Inc Trimpot Div Riverside CA 33025 M A ComOmni Spectra Inc Replacing Omni Spectra Microwave Subsystems Div Tempe AZ 33297 NEC Electronics USA Inc Electronic Arrays Inc Div Mountain View CA 40402 Roderstein Electronics Inc Statesville NC 50579 Litronix Inc Cupertino CA 51406 Murata Erie No America Inc Also see 72982 Marietta GA 51984 NEC America Inc Falls Church VA 52500 Amphenol RF Operations Burlington MA 52763 Stettner Electronics Inc Chattanooga TN 55285 Bercquist Co Minneapolis MN 55566 RAF Electronic Hardware Seymour CT TECHNI
272. encies and approximate levels in a suggested test sequence to aid in troubleshooting Note that TP4 is assumed to be shorted to ground Note also that the 500 ohm probe should be grounded as closely as possible to each test point PCA hold down screws and the walls of the plate provide good grounds As another aid to troubleshooting Table 6C 10 contains DC bias voltage information for circuits in the RF section Table 6C 9 A12 Sum Loop PCA RF Circuitry Test Information LOCATION CIRCUIT FREQUENCY LEVELT J11 U1 LO amplifier f coarse 14 dBm TP13 U1 LO amplifier f coarse 1dBm J9 U1 RF amplifier f sum x 2 MHz 34 dBm TP12 U1 RF amplifier f sum 2 MHz 24 dBm Q5 base IF1 amplifier f IF1 35 dBm R25 R26 node amplifier f IF1 15dBm Q6 collector IF1 amplifier 1 5 dBm R17 R45 node FM amplifier 80 MHz 26 dBm TP14 FM amplifier 80 MHz 13 dBm Q9 base IF2 amplifier f sub syn 2 2 MHz 37 dBm Q10 collector IF2 amplifier f sub syn 2 2 MHz 18 dBm J10 ECL TTL buffer f sub synth 18 dBm R57 C60 node U3 LO driver f sub synth 2 26 dBm f IF1 f sub synth 2 80 2 MHz T Levels are approximate and are measured using a 500 ohm probe with a spectrum analyzer 6C 39 TROUBLESHOOTING AND REPAIR FREQUENCY SYNTHESIS 6C 40 Table 6C 10 A12 Sum Loop PCA RF Section DC Bias Voltages LOCATION CIRCUIT VOLTS DC Q1 collector U1 LO amplifier 49 8 Q2 collector U1 LO amplifier 44 9 U7 out
273. ents be ordered directly from the manufacturer by using the manufactur er s part number or from John Fluke Mfg Co or its authorized representative by using the Fluke stock number In the event the part you order has been replaced by a new or improved part the replacement will be accompanied by an explanatory note and if necessary installation instructions To ensure prompt and efficient handling of your order include the following information Quantity 2 Fluke Stock Number 3 Description 4 Reference Designation 5 Printed Circuit Board Part Number and Revision Letter 6 Instrument Model and Serial Number REPLACEMENT PARTS A Recommended Spare Parts Kit for your basic instrument is available from the factory This kit contains recommended quantities ofthose items as listed in the REC QTY column of the parts list Price information of parts is available from the John Fluke Mfg Co Inc or its representative Prices are also available in the Fluke Replacement Parts Catalog which is available on request SERVICE CENTERS 7 3 A list of Fluke Philips technical service centers is provided at the end of Section 7 CAUTION Parts preceded by and asterisk are subject to damage by static discharge 7 3 REPLACEMENT PARTS Table 7 1 See Figure REFERENCE DESIGNATOR A gt NUMERICS__ gt 5 ___ A00 1 DISPLAY PCA 2 COARSE LOOP 3 SUB SYNTHESIZER VCO
274. epends on band 7 8 OFF oscillator transistor collectors 9 4 U1 2 3 4 outputs 4 5 CR9 CR10 11 CR12 node 9 7 Section 6D RF Level AM RF LEVEL FAULT TREE 6D 1 The RF Level Fault Tree Figure 6D 1 is the starting point for troubleshooting RF Level and AM problems RF LEVEL BLOCK DIAGRAM 6D 2 Refer to the RF Level Block Diagram Figure 6D 2 to identify the major functional sections and to follow the signal paths of the Output PCA LEVEL 240 241 334 336 339 356 302 At this point it is necessary If no status codes or only If 302 try SPCL 04 status codes 334 336 and to remove the outside cover of then code large level errors see the Output Module See 401 404 410 Paragraph 6D 27 and 6D 28 for Paragraph 6D 1 thru 6D 26 for 421 424 Attenuator and Relay Driver Output Pre Mod and Mod Control and 430 problems PCAs imply a latch problem or a cal comp memory problem related to level Figure 6D 1 RF Level Fault Tree 60 1 TROUBLESHOOTING AND REPAIR RF LEVEL AM NOILVINGOW asind 1 8 3ounos NOILV InGOW NOLLVINGOW WV IVNH31X3 WV TVNH3LNI 01901 HOIVHUVdWOO 104100 3401 3univuadwiL 9 vc 4 IOHLNOO GOW 899 vc gP vc 4 1 38
275. ernal may be used DIGITAL FREQUENCY SWEEP SWEEP MODES Auto single or manual 1 15 INTRODUCTION AND SPECIFICATIONS 1 16 Table 1 4 Typical Signal Generator Performance cont SWEEP FUNCTIONS DATA ENTRY PARAMETERS SWEEP SWEEP OUTPUT DIGITAL AMPLITUDE SWEEP SWEEP SWEEP FUNCTIONS DATA ENTRY PARAMETERS SWEEP SPEED SWEEP OUTPUT PENLIFT GENERAL TEMPERATURE HUMIDITY RANGE Operating toe eds ALTITUDE Operating VIBRATION Non Operating SHOCK Symmetrical sweep Asymmetrical sweep Sweep speed Sweep width and sweep increment Minimum 40 ms per increment selectable as mini mum dwell time where dwell time can be O 20 50 100 200 or 500 ms at each increment O to 10 1096 V Up to 4096 points in a stepped ramp Load gt 2 TTL high for retrace Load gt 2 Auto single or manual Linear Volts or Log dB Symmetrical sweep
276. es listed in step 7 9 Set the RF spectrum analyzer to display the UUT output signal with a 50 kHz span and 30 Hz resolution Verify that all spurious signals are below 40 dBc for frequencies listed in step 7 4 15 PERFORMANCE TESTS 4 16 PHASE NOISE AND NON HARMONIC SPURIOUS TESTS 4 13 The Phase Noise test uses a phase noise measurement system and a low phase noise reference signal generator to measure the UUT phase noise Non harmonic spurious signals are measured with the phase noise measurement system and low phase noise reference signal generator and are verified with an RF spectrum analyzer See REMARKS REQUIREMENTS Phase noise at frequency gt 512 MHz less than 124 dBc Hz Phase noise at frequency 512 MHz less than 130 dBc Hz Non harmonic spurious signal 100 dBc TEST EQUIPMENT Phase noise measurement system spectrum analyzer High frequency synthesized signal generator HFSSG REMARKS An RF spectrum analyzer cannot be relied upon to make 100 dBc spurious measurements due to the analyzer s own internal spurious signal below 100 dBc at a variety of RF frequencies A phase noise measurement system using a frequency reference with 100 dBc spurious can be used reliably to indicate spurious signals However depending on whether the spurious signal is single sideband or double sideband there may be a 6 dB error in the indicated amplitude Double sideband phase modulated spuriou
277. esponse Each signal generator has level correction data for both the A8 Output PCA and the A20 Attenuator RPP Assembly The level correction data is stored in the compensa tion memory located on the A13 Controller PCA The level correction data is based on the measurements of each assembly during level compensation ofthe signal generator The level correction data is applied only to the vernier level DAC and does not affect the coarse level control provided by the Attenuator RPP Assembly In other words all signal generators have the same attenuator pads inserted at a selected level even though the correction data is different for each signal generator To improve level accuracy in relation to temperature the signal generator uses a software temperature compensation technique This technique uses data that is the same for all signal generators Amplitude Modulation 2 11 The signal generator allows amplitude modulation depth programming from 0 to 99 9 with 0 1 resolution Amplitude modulation depth is programmed using the 12 bit AM DAC A nominal setting of 2997 on the AM DAC corresponds to 99 9 AM depth The output ofthe level DAC is the leveling loop control voltage The signal generator output signal is amplitude modulated by varying this control voltage with the modulating signal A 1V peak modulating signal from the internal modulation oscillator or from the external MOD INPUT connector is applied to the AM DAC a multiplying digit
278. et to mid scale with Special Function 942 TROUBLESHOOTING AND REPAIR Display Synthesizer Loop Frequencies 6 40 The sum loop coarse loop and sub synthesizer frequencies for the programmed RF output frequency can be displayed by the Special Functions listed below CODE FUNCTION 945 Display Sum Loop frequency 946 Display Coarse Loop frequency 947 Display Sub Synthesizer frequency 6 15 6 16 Section 6A Power Supply POWER SUPPLY BLOCK DIAGRAM 6A 1 Refer to the Power Supply Block Diagram Figure to identify the major functional sections and for help in following the power and current paths ofthe power supply POWER SUPPLY CIRCUIT DESCRIPTION 6A 2 The instrument power supply provides all the DC and AC power requirements of the system The DC supplies are provided to all circuitry of the system and to the DC fan The AC power is used for filament heat for the front panel display Line power passes through the line filter and fuse The filter also provides switching for the various power line voltages from which the instrument is designed to operate The AC power is then routed to the power transformer primary winding The transformer includes an additional safety device which serves as a thermal shutoff to break the primary AC supply in case the transformer exceeds a safe operating temperature To accommodate the various line voltages the case ofthe line fused receptacle filter of the 6080A AN contains a line voltag
279. evel calibration procedure Perform the following to execute the front panel level calibration procedure 1 Set the rear panel CALICOMP switch to the 1 on position 2 Enter special function 993 to initiate the procedure 3 Connect the signal generator s RF output to the power meter 4 Setthe appropriate power meter calibration factor if required and zero the power meter 5 Use the edit knob to change the adjustment value until the power meter reads 10 dBm 6 Press the key twice to store the new data CLOSED CASE CALIBRATION Table 3 5 Front Panel Controls for Level Calibration Procedure CONTROLS FUNCTION AND DESCRIPTION KNOB ON OFF STO Bright Digit Editing Turn the edit knob to adjust the level calibration factor Use the left right arrow keys to move the bright digit within the adjustment field The bright digit is always located in the adjustment field RF on off Toggles the RF output on off Overrange uncal or Rejected Entry Status Normally displays the overrange uncal status Displays the rejected entry status code if there is a rejected entry Store Measured Data Press once the prompt Sto is displayed Press again to store the data The message Sto is displayed to confirm the selection The updated calibration factor is stored in the calibration memory and the last valid instrument state is restored Press any other key to cancel the store operation a
280. f the instrument fails any of the self tests the results are shown in the four display fields See Appendix E for the interpretation of the test failure codes If the signal generator passes the self test it is automatically returned to the default instrument state PERFORMANCE TESTS FREQUENCY ACCURACY TEST 4 4 The internal time base is compared to that of a Frequency Standard REQUIREMENTS The frequency of the UUT time base is within the specified limits TEST EQUIPMENT e Frequency standard Frequency counter PROCEDURE 1 Connectthe frequency standard output to the 10 MHZ REF IN connector on the frequency counter and switch the counter to EXT REF 2 Switch the UUT to internal reference 3 Connect the UUT REF OUT connector to the frequency counter CHANNEL A input connector 4 Verify that the counter display is 10 MHz 100 Hz 5 Monitor the frequency for one hour to verify its stability within 40 5 Hz Operating temperature within 5 SYNTHESIS TEST 4 5 The signal generator output frequency is measured at several programmed frequencies using a frequency counter operating on acommon reference with the signal generator REQUIREMENT The signal generator s measured and programmed frequencies agree within 1 count TEST EQUIPMENT Frequency counter REMARKS If the UUT fails this test the frequency synthesis circuitry is probably at fault See Section 6C PROCEDURE 1 Connect the UUT 10 MHz
281. f the redundant calibration compensation memory are contained in the battery backed CMOS RAM U8 The other half of the redundant calibration compensation memory is contained in the EEPROM U9 The rear panel CALICOMP switch protects the calibration compensation memory from accidental destruction 6 1 TROUBLESHOOTING AND REPAIR DIGITAL CONTROLLER er of v er ir TOULNOD 1190 39 343333 8 18 WAIGSW HOIH 4110 31V 1d 7031409 1 WAZISSHLNAS 39V3U31NI 887 9331 39V3U31NI AV1dSI IWH3N39 n 000899 55330 40 SU 002 13538 ZHN 8 9019 30093 AHOW3W 1 333 1 809 51 1 T3NVd 1 Figure 6B 1 6080A AN Controller Block Diagram 6B 2 TROUBLESHOOTING AND REPAIR DIGITAL CONTROLLER Memory Control 6B 5 Decoder PAL 011 decodes the memory selects and contains additional write protection logic for the the calibration compensation memory and the instrument states stored in the battery backed RAM Timing PAL U15 adds one wait state to each memory read or write cycle Individual upper byte and lower byte read and write enable signals are generated from 68HCOOO control signals R W UDS and LDS by U22 Signals RDU and RDL are read enables for the upper byte and lower byte respectively Signa
282. front panel AM calibration procedure is performed Perform the following to execute the front panel AM calibration procedure 1 Set the rear panel CALICOMP switch to 1 on position 2 Enter special function 99 to initiate the AM procedure 3 Connect the 6080A AN s RF output to the modulation meter CLOSED CASE CALIBRATION Select the peak mode enable the 50 Hz high pass filter and enable the 3 kHz low pass filter on the modulation meter Usetheeditknobtochange the adjustment value until the modulation meter reads 50 0 Press twice to store the new data Table 3 1 Front Panel Controls for AM Calibration Procedure CONTROLS FUNCTION AND DESCRIPTION 4 Bright Digit Editing KNOB Turn the edit knob to adjust the AM calibration factor Use the left right arrow keys to move the bright digit within the adjustment field The bright digit is always located in the adjustment field RF on off Toggles the RF output on off Overrange uncal or Rejected Entry Status Normally displays the overrange uncal status Displays the rejected entry status code if there is a rejected entry STO Store Measured Data Press once the prompt Sto is displayed Press again to store the data The message Sto is displayed to confirm the selection The updated calibration factor is stored in the calibration memory and the last valid instrument state is restored Press any other key to cancel the store operation and
283. ft BNC both ends Y9112 A P T Screwdriver electric Set to 7 inch pounds torque Jergens CL6500 CLT50 Power Supply Variable 0 to 30V dc Lambda T Measuring Receiver 10 to 1300 MHz HP 8902A P Set Sensor Module 0 1 to 2600 MHz HP 11722A P Pulse Generator 50 ns pulse width HP 8012B P 10 MHz repetition rate BNC Termination 50 ohm Midwest Microwave P 2048M Detector 3 GHz bandwidth 5 ns rise time Krytar D101 P Phase Noise HP 3048A P Measurement System Tuning Tool 025 inch square drive Johanson 4192 NOTES 1 Adjustment Performance Test T Troubleshooting 2 Helper Instruments 3 VSWR verified and actual attenuation calibrated to 0 2 dB by the operator at application frequencies 4 Two Turn 1 inch diameter loop made of 18 enamel wire soldered to a BNC connector 4 3 PERFORMANCE TESTS Figure 4 1 Two Turn Loop POWER ON TEST 4 3 This performance test is the built in self test that performs a simple functional check of the instrument REQUIREMENT The signal generator successfully passes the self test REMARKS The test is begun each time the signal generator is turned on Press any of the FUNCTION keys or the key to abort the test PROCEDURE 1 Start the test with the power off 2 Press the POWER button on The signal generator automatically starts the self tests which include lighting all indicators and every segment of the display This test takes 5 seconds I
284. ge at the steering port TP3 varies from 0 to 26V depending on RF frequency The source of FM in the signal generator is the 80 MHz signal from the A14 FM PCA an input to the sum loop Since the Sum Loop VCO is phase locked to this signal any frequency modulation on the 80 MHz FM PCA signal is transferred to the Sum Loop VCO However at high levels of FM deviation the required voltage swing at the VCO phase lock port would require a phase detector output greater than possible and thus the Sum Loop would lose lock This problem is avoided by applying an AC signal at the VCO steering port that provides nearly the correct deviation in the Sum Loop VCO during high deviation FM operation Thus the loop must only generate a small error voltage at the VCO phase lock port to maintain lock and the phase detector output stays acceptably small The SUMAUDIO signal at J8 1 is from the Al4 FM PCA and is an AC frequency modulating signal with amplitude proportional to FM deviation This signal is buffered by 0106 which is configured for unity gain and can be switched via U107 for inverting or non inverting operation These two modes are required to properly phase the cancellation signal depending on fundamental frequency band For f fund 760 MHz 0106 inverts while for f fund gt 760 MHz 0106 is non inverting Gain equalization for the two modes is provided by R121 The buffered 6C 37 TROUBLESHOOTING AND REPAIR FREQUENCY SYNT
285. gic signal This is combined with the low and high voltage detector to produce REFUNLKL which is sent to the controller The 40 MHz from the buffer U601 is amplified Q609 and doubled to 80 MHz in a full wave rectifier CR601 CR602 T601 The 80 MHz is filtered L611 L612 C643 6C 19 TROUBLESHOOTING AND REPAIR FREQUENCY SYNTHESIS 6 20 C644 amplified 0610 and filtered again C649 C50 L613 L615 This 18 the 80 MHz signal to the output section J5 When in the DCFM mode and not in the heterodyne band this signal is turned off Q611 via REF80H COARSE LOOP BLOCK DIAGRAM 6C 15 Refer to the Coarse Loop Block Diagram Figure 6C 7 and the schematic Section 8 to identify the major functional sections and follow the signal paths ofthe coarse loop The coarse loop consists oftwo interlocking loops the main phase lock loop and the discriminator loop around the VCO The discriminator loop reduces the phase noise of the VCO The 576 to 960 MHz signal from the Coarse Loop VCO A5 P2 is attenuated R401 403 amplified U401 attenuated again R407 409 and amplified again 0405 This signal drives adivide by 4 pre scaler U301 Theoutputofthe pre scaler 144 to 240 MHz 18 amplified U311 to ECL levels The N divider consists oftwo parts a programmable divide by 3 4 5 6 7 0302 U303 U308 U310 and a programmable 5 bit rate multiplier U304 U305 U306 U307 The divide by 3 4 5 6 7 is aring counte
286. gnals VSIG Vckl and Vck2 The output signals are used to control the phase detectors The relationship of these signals is shown below and is discussed in the the following paragraphs The reference divider also has a circuit REF ON OFF SWITCH part of U6 and Q9 which controls the input 20 MHz that comes from the output board The circuit enables the 20 MHz from the output board except when DCFM is active The function of the different outputs from the dividers is shown in Figure 6E 3 and discussed under the heading Phase Detectors Loop Circuits and Logic Section that follows Within the signals of each divider the signal relationship is fixed for example between R amp Rck but the relationship between the RSIG signals and the VSIG signals can vary in timing as shown by the first and second set of pulses These signal drive the phase detectors as will be discussed in the following paragraphs Phase Detectors Loop Circuits and Logic Section 6E 6 Only one oftwo phase detectors is active at any time One of these U21 is the normal standard dual D flip flop The other U11 is a wide range N PI phase detector which uses U11 an up down counter The standard phase detector uses diode switched resistor current sources the other the N PI uses a switched DAC Also associated with the dividers and phase detectors is an unlock detector U20 which will respond if an overmodulation or unlocked condition exists at the phase detector d
287. h 9 Repeat steps 3 through 8 at 14 20 40 80 160 320 550 640 700 850 950 and 1004 MHz PERFORMANCE TESTS HARMONIC AND LINE RELATED SPURIOUS TEST 4 12 The Harmonic and Line Related Spurious Test uses an RF spectrum analyzer to compare the level ofthe harmonic signal and close in spurious signals to the desired signal at various programmed frequencies REQUIREMENTS RF harmonics lt 30 dBc for levels lt 13 dBm Power line spurious signals 40 dBc signals within 15 kHz of carrier TEST EQUIPMENT RF Spectrum Analyzer PROCEDURE 1 Connect the UUT RF OUTPUT to the RF spectrum analyzer input 2 Program the UUT to SPCL 909 3 Program the UUT to 13 dBm and 0 5 MHz 4 Set the RF spectrum analyzer controls to display the UUT output signal and its harmonics at least three harmonics wherever possible Be careful not to overload the analyzer input Overloading the RF spectrum analyzer causes it to generate harmonics thus invalidating the test 5 Verify that all the harmonics are more than 30 dB below the fundamental signal 6 Program the UUT to 7 0 dBm 7 Verify that all the harmonics are more than 30 dB below the fundamental signal for the following frequencies 14 20 40 80 160 320 550 640 700 850 950 and 1056 MHz 8 Set the RF spectrum analyzer to display the UUT output signal with 2 kHz span and 10 Hz resolution Verify that all spurious signals are below 40 dBc for frequenci
288. he major functional blocks and follow the signal paths of the Sub Synthesizer SUB SYNTHESIZER CIRCUIT DESCRIPTION A4 6 3 The Sub Synthesizer A4 in conjunction with the Sub Synthesizer VCO A3 generates a 16 to 32 MHz signal in 2 Hz steps This board also distributes power control lines and programmable DC voltages to the Coarse Loop PCA A2 Status lines from the Coarse Loop PCA back to the Controller PCA A13 are also routed through this board The Sub Synthesizer phase lock loop PLL is a fractional divider PLL with a single sideband SSB mixer in the feedback path The oscillator for this loop is a separate PCA the A3 Sub Synthesizer VCO PCA The VCO frequency is 160 to 320 MHz A 10 1 divider on the VCO PCA produces the 16 to 32 MHz signal The key signals to the PLL are the 1 MHz reference signal from the 40 MHz reference circuit the 160 to 320 MHz signal from the VCO and the 10 to 20 kHz signal from the low order digit generator circuit The fractional division technique provides provides 10 kHz frequency resolution at the VCO frequency 160 to 320 MHz The SSB mixer in conjunction with the low order digit generator provides an additional 20 Hz resolution at the VCO frequency 6C 1 TROUBLESHOOTING AND REPAIR FREQUENCY SYNTHESIS AONANOAYA YAZISAHLNAS ENS 276 1945 AONANDAYS 3001 3SHVOO 996 2145 dOO WNS 996 1945 Ad 38 NYO S3loNanodud 19 3
289. he measured data CC EXIT Abort the cal procedure immediately ERROR Request the rejected entry status STATUS STATUS Load Request the overrange uncal status REFERENCE OSCILLATOR CALIBRATION 3 14 The reference oscillator calibration procedures allow a single point calibration of the internal 10 MHz reference oscillator to be performed A frequency counter is connected to the 6080A AN s RF output and the reference oscillator calibration factor is adjusted based on the counter reading The procedure specific parameters are as follows Adjustment Range 256 counts 6 ppm minimum Adjustment Resolution 1 count Target Value 100 MHz RF Frequency 100 MHz External Equipment Frequency Counter Fluke 1953A or equivalent When performing the front panel procedure use the edit knob to adjust the calibration factor until the measured frequency matches the target value When performing the remote procedure the process is under the control of a program running on an IEEE 488 bus controller The front panel display is reconfigured during the procedures The target level is displayed in the modulation field the RF frequency is displayed in the frequency field the adjustment value is displayed in the amplitude field and the CAL annunciator is lit The display is consistent for the front panel and remote procedures and is shown below All adjustments update a temporary copy of the adjustment value The copy in the calibration memory is only up
290. he remote commands used in the procedure and the elements required to build a functioning controller program Refer to the heading Remote Calibration earlier Section 3 for general information relating to all remote calibration procedures complete program listing that runs on a Fluke 1722A controller is provided in Appendix G The basic structure of the level calibration program is shown in Figure 3 5 initiate the reference oscillator calibration procedure with CAL REFOSC initialize frequency counter MAIN LOOP request the RF frequency with CC FREQ if frequency 9e9 goto DONE read frequency counter send reading to 6080A AN with CC RDFREQ goto MAIN LOOP DONE store new data in calibration memory with CC SAVE end Figure 3 5 Basic Structure of the Reference Oscillator Calibration Program CLOSED CASE CALIBRATION The calibration procedure is initiated by the command CAL REFOSC The controller requests the signal generators center frequency with the command FREQ and waits for a response When aresponse is received the controller gets counter reading and sends it to the signal generator with the command RDFREQ The program remains in the main loop until the signal generator returns the end code 9 09 Hz in response to the CC FREQ command The main loop is then exited and the data is saved with the CC SAVE command Each time the signal generator receives a reading from the
291. hesizer VCO PCA 7 27 REPLACEMENT PARTS REFERENCE DESIGNATOR A NUMERICS 8 WOR jS on MAGS SS GON TS RO PO HP CO PO Ov gt 1 1 OTRO p EnS ti mw Soni 73 176 1c5 lt gt lt gt 11 80 181 15 19 42 47 175 58 164 CO I lt gt lt gt 60 SAO HOD 15 DAD ow WY ee ee oe 7 28 Table 7 5 A4 Sub Synthesizer See Figure 7 5 CAP AL 100 20 35V CAP POLYES 0 10 20 50V CAP TA 8206 20 20V AL 1006 20 16V CAP TA 150UF 4 205 15V CAP CER 1000PF 4 202 1007 CAP CER 22PF 2 100V C0G CAP TA 39UF 20 6V CAP POLYES 0 47UF 10 50V CAP POLYCA 0 022UF 5 63V CAP POLYPR 7500PF 2 5 63V CAP POLYPR 1500PF 2 5 1007 CAP POLYCA 0 0560F 55 63V CAP POLYCA 0 0270F 105 63V CAP 10UF 208 10V CAP CER 100PF 4 25 100V 06 CAP CER 0 01UF 4 202 1007 CAP TA LOUF 20 35V AL 47UF 208 50V SOLV PROOF CAP AL 47UF 20 1
292. ic signal GT180H for frequencies below 180 MHz Above that frequency filtering is provided by the 260 MHz LPF between U10 and CR31 When a frequency in this band is selected logic signal is high which turns on CR71 The network between 25 27 and CR71 provides level adjustment ofthe signal U58 has two outputs One output provides 64 to 128 MHz to an output filter consisting of T2 and the LPF following it The second output provides these same frequencies to the fourth divider U8 058 is activated by DIHAFL being high to provide DC bias and D2HAFH low to activate the divider U8 provides an output of 32 to 64 MHz U8 and its output are selected by logic signals D3HAF and 3HAFH The fifth divider U9 generates 15 to 32 MHz U9 and its output are selected by logic signals DAHAFL and 4HAFH Filtering for harmonic suppression when the frequency is in the 15 to 64 MHz range is done on the output board following the modulator The appropriate band is selected by diodes CR71 CR28 CR29 or CR30 and is amplified by U10 When a frequency from 15 to 256 MHz is selected it passes to the amplifier through CR31 provides 6 dB of gain and buffering for the 15 to 1056 MHz signal that is the input to the Output PCA 6D 3 TROUBLESHOOTING AND REPAIR RF LEVEL AM 6D 4 The amplitude modulator on the Output PCA consists of PIN diodes CR27 through CR33 and associated components and the modulator receives the 15 to 1056 MHz signal f
293. ide by 10 U37 and the 1 MHz signal from the N divider U62 are connected to a digital phase frequency detector U30 U31 U32 If the N divider output frequency is less than the reference frequency TP25 is low and the voltage atthe output oflevel shifter Q17 is below ground This results in turning off 18 and allowing current from U63 to flow through CR18 out ofthe integrator This raises the voltage at the output of the integrator which raises the VCO frequency Similarly if the N divider output frequency is above the reference TP24 is high turning on CR16 and allowing current to flow through R97 into the integrator This lowers the voltage at the output ofthe integrator which lowers the VCO frequency If the phase between the reference and N divider output slips more than two cycles in either direction the corresponding phase detector output is high or low This provides twice the integrator current during acquisition as a conventional phase frequency detector R51 provides a small bias current to the integrator to bias the phase detector in the linear region consequently the up pump is always on During calibration ofthe VCO the Kv the VCO gain coefficient is measured at many frequencies across the band and compensation data is stored in non volatile memory The instrument software uses this data along with N to control the PLL bandwidth The PLL bandwidth is controlled by changing the current to the up pump via KN DAC U6
294. ignal path The 5V power supply for the LO amplifier is switched off by Q3 so that spurious signals are not introduced when the instrument is operating in the 15 to 1056 MHz bands TROUBLESHOOTING AND REPAIR RF LEVEL AM Leveling Loop 6D 5 The leveling loop controls the 15 to 1056 MHz signal level at the detector diode CR20 on the Output PCA therefore the leveling loop also controls the signal level at the buffer amplifier Q7 on the Output PCA The leveled RF signal is proportional to the leveling loop control voltage which appears at TP7 on the Modulation Control PCA The Schottky detector diode CR20 generates a temperature dependent DC voltage This is a non linear function ofthe applied RF voltage thus temperature compensation and linearization are necessary The detector diode signal is low pass filtered by L34 and C34 and is offset by the voltage across temperature compensating diode CR19 Q1 Q2 and associated components on the Modulation Control PCA form a current source circuit that provides bias current for CR20 and 19 The offset detector diode voltage at U7 pin 3 on the Modulation Control PCA is linearized by amplifier U7 and its associated feedback components Potentiometer R28 provides an adjustment for best detector linearity at low RF levels Thus the voltage at U7 pin 6 TP2 is proportional to the level ofthe RF signal incident on the detector diode CR20 on the Output PCA This voltage is applied to pin 2 ofth
295. imum in high rate phase modulation To attain such a wide deviation the oscillator has a high deviation mode in the top two deviation ranges A linearizer is active in the top three ranges to reduce distortion To achieve the wide range deviation at low rates a wide band phase detector is used for the top deviation ranges and the phase detector reference frequency is appropriately selected Oscillator Section 6E 4 The voltage controlled oscillator section is composed of 01 Q2 L1 1 8 and associated components The adjustable coil L1 adjustable capacitor C9 varactors voltage variable capacitors 1 8 and associated capacitors form the resonant circuit Capacitors C2 and C4 couple the resonant circuit to the input of the active circuit and C10 and couple to the output of the active circuit Parts C9 CR15 and L4 are used to switch between the high deviation mode and normal mode The circuit of Q5 and Q8 drive the PIN diode CR15 between either conduction or high impedance Low impedance at conduction adds C9 in the resonant circuit for a normal mode high Q oscillator circuit High impedance removes C9 from the oscillator for the high deviation mode The varactor voltage must adjust to compensate for the change ofthe capacitance of C9 in or out ofthe circuit The voltage to the varactors has both control and modulation functions Control is applied to the center connection of the varactors TP11 and modulation is
296. ing remove the plug onjumper that connects TP1 and TP2 and install it to connect TP1 to TP3 This bypasses divider U3 and connects the fundamental oscillator signal to 72 This signal should vary from about 160 to 320 MHz at about 3 dBm over the tuning range If this signal is faulty the circuit prior to U3 is faulty Remember to replace the plug on jumper in its original position after troubleshooting DC voltages can be readily measured at various nodes in the circuit and may help to isolate the faulty circuit Table 6C 2 lists expected approximate DC voltages at various circuit nodes as an aid to troubleshooting TROUBLESHOOTING AND REPAIR FREQUENCY SYNTHESIS Table 6C 2 A3 Sub Synthesizer VCO PCA DC Voltages LOCATION VOLT DC Q1 collector 48 7 02 collector 71 U1 output 3 9 5 7 10 node V phaselock lt 7 5V 42 3 CR5 CR7 R10 node V phaselock gt 7 5V 23 U2 output 44 4 US pin 2 43 5 COARSE LOOP CIRCUIT DESCRIPTION A2 6C 13 The Coarse Loop PCA generates frequencies from 576 to 960 MHz in 8 MHz steps It also provides a 40 MHz reference for the Sub Synthesizer a 20 MHz signal for the modulation oscillator and 80 MHz signal for the output section This 80 MHz signal is the local oscillator signal for the heterodyne band and is the reference for the FM circuitry The board can be broken down into two major blocks the reference section and the coarse loop itself REFERENCE SECTION BLOCK D
297. ion Refer to Table 6E 2 Section 6E to determine the FM DAC and range settings from this equivalent FM deviation The maximum programmable phase modulation deviation is dependent on the RF output frequency Phase modulation deviations up to 400 radians may be entered regardless ofthe output frequency However the STATUS indicator is flashed and the FM DAC is clamped at full scale ifthe entry is beyond the allowed upper limit for that frequency band The maximum programmable phase modulation deviation in each frequency band is depicted in Section 4C Modulation of the Operators Manual Phase modulation is achieved by reconfiguring the modulation circuits to cause a true phase modulation response for both internal and external modulation inputs The display is correspondingly changed to indicate deviation in radians Two modes are available large deviation at a limited bandwidth and limited deviation for higher rate bandwidth THEORY OF OPERATION Output Level Control 2 10 Level control is provided by two separate circuits a step attenuator and a vernier level DAC The A20 Attenuator RPP Assembly provides coarse level control in 6 02 dB steps Fine level control 15 provided by a vernier level DAC that varies the leveling loop control voltage The controller microprocessor automatically controls the step attenuator and the vernier level DAC The microprocessor also applies level correction to compensate for the signal generator frequency r
298. ion of the signal generator and to describe the typical performance that can be expected FREQUENCY SWITCHING SPEED 100 ms to be within 100 Hz AMPLITUDE SWITCHING SPEED 100 ms to be within 0 1 dB AMPLITUDE RANGE Programmable from 20 to 147 4 dBm Fixed range selected by special function allows for more than 12 dB of vernier without switching the attenuator EXTERNAL MODULATION Annunciators indicate when a 1V peak signal is applied 2 over a 0 02 to 100 kHz band IEEE All controls except the power switch and the internal external reference switch are remotely programmable via IEEE 488 Interface Std 488 2 1987 All status including the option complement are available remotely EXTERNAL REFERENCE LOCK RANGE 10 ppm PULSE MODULATION PULSE DELAY OFF ON 80 ns typ ON OFF 65 ns typ INTRODUCTION AND SPECIFICATIONS Table 1 4 Typical Signal Generator Performance cont DECEM DRIF t et te mee ppm hr lt 1 16 max deviation after 2 hour warmup and at constant 8 ppm hr for gt 1 16 max deviation temperature Section 2 Theory of Operation INTRODUCTION 2 1 Section 2 of this manual provides a basic description of the 6080A AN Synthesized Signal Generator also referred to throughout as the signal generator Three major topics are covered General Description Briefl
299. ion procedures A complete program listing that runs on a Fluke 1722A controller is provided in Appendix G The basic structure of the FM calibration program is shown in Figure 3 3 initiate the FM calibration procedure with CAL_FM initialize modulation meter MAIN_LOOP request the RF frequency with CC_FREQ if frequency 9e9 goto DONE read modulation meter send reading to 6080A AN with CC_RDFM goto MAIN_LOOP DONE store new data in calibration memory with CC SAVE end Figure 3 3 Basic Structure of FM Calibration Program The procedure is initiated by the command CAL_FM The controller requests the signal generator s center frequency with the command CC_FREQ and waits for a response When a response is received the controller gets a mod meter reading and sends it to the signal generator with the command CC_RDFM The program remains in the main loop until the signal generator returns the end code 9E 09 Hz in response to the CC_FREQ command The main loop is then exited and the data is saved with the CC_SAVE command 3 9 CLOSED CASE CALIBRATION 3 10 Each time the signal generator receives a reading from the controller it adjusts its internal settings and programs the new FM deviation When the signal generator receives two consecutive readings within 0 1 kHz of the target value 100 kHz it considers the displayed adjustment value correct and returns the end code The controller program mus
300. is adjustment is normally required only when components in the het band circuits have been replaced It is also necessary to make this adjustment if R72 is adjusted CAUTION This adjustment directly affects the output level and should not be made indiscriminately PROCEDURE With the UUT programmed to 9 dBm adjust the het level adjustment R10 for equal output power at 14 9 and 15 MHz 1 Program the UUT to SPCL 01 15 MHz and 9 dBm 2 Zero the power meter 3 Remove the het level adjustment access screw from the bottom module plate cover 4 Connect the Power Sensor to the UUT RF OUTPUT connector Note the power meter reading 5 Program the UUT to 14 9 MHz 6 Adjust the het level adjustment R10 for areading equal to that previously noted 7 Reinstall the het level adjustment access screw Premodulator PCA Bandwidth Adjustment R51 and C7 6D 20 The following procedure covers the adjustment of R51 and C7 on the Premodulator PCA This adjustment optimizes the AM bandwidth in the 256 to 1056 MHz band TEST EQUIPMENT Power meter e Tuning tool 025 in sq Johanson 4192 REMARKS This adjustment is normally made only if changes are made to the Premodulator PCA 6D 17 TROUBLESHOOTING AND REPAIR RF LEVEL AM 6D 18 PROCEDURE R51 is adjusted so that the Premodulator output is 3 5 dBm at 800 MHz Assuming that the shape ofthe control voltage versus frequency curve is typical this minimizes the overa
301. istortion analyzer to measure distortion at 1 KHz e Verify thatthe modulation analyzerreading is between 19 and 21 KHz and that the THD is less than 2 Repeat at deviations of 5 and 10 kHz Verify that the modulation analyzer reading is within 5 of programmed value See the following NOTE f Program the UUT to deviation of 50 100 and 200 kHz g Verify that the modulation analyzer reading is the deviation programmed 5 and that the distortion is less than 5 h Repeat steps d through g with the modulation rate set to 100 Hz Verify distortion only NOTE Change the modulation analyzer bandwidth and distortion analyzer frequency appropriatelyfor modulationfrequencyfor steps through i Repeat steps d through g with modulation rate set to 50 kHz Verify distortion only Program UUT to 40 MHz frequency 25 kHz deviation and 1 kHz INT modulation frequency k Verify that the Modulation Analyzer reading is between 23 75 and 26 25 and that the distortion is less than 596 Program the UUT to deviation of 50 100 200 and 250 kHz m Verify that the modulation analyzer readings correspond to that programmed 5 and that the distortion is less than 5 n Repeat steps j through m with the modulation rate set to 100 Hz Verify distortion only o Repeat steps j through m with the modulation rate set to 50 kHz Verify distortion only p Set the modulation rate to 100 kHz with 250 kHz deviation Verify that
302. ithmic wave generation method which provides a very accurate and stable signal source of high purity and low harmonic distortion The main function of this system is implemented in the custom integrated circuit U1 and it uses an external wave lookup table U2 U3 and a 12 bit wave reconstruction DAC U7 and U9B Since a discrete time sampled method is employed in generating the various waves a low pass antialiasing filter R7 C13 C14 L1 is required to reject the sampling frequency the alias signals and the out of band spurious from the output signal The amplitude of oscillation at the MODULATION OUTPUT connector is controlled by a 12 bit multiplying DAC 08 U11A This output level can be set between 0 to 4V pk with 1 mV pk steps into a 600 ohm load 6 1 TROUBLESHOOTING AND REPAIR INTERNAL MODULATION OSCILLATOR ut payesBoquy 2 0 lt 1 gt 713889 lt 0 2 gt 9 5 1016 548 1 lt 07 gt 05 sng viin en o GOW 1 P 01112 1 LTv19 19 5 01 Figure 6F 1 Mod Oscillator Block Diagram 6F 2 TROUBLESHOOTING AND REPAIR INTERNAL MODULATION OSCILLATOR The wave data is stored in two EPROMS 02 03 Three control lines from 01
303. ives the range ofthe signal and the expected value for a typical instrument state The values in the typical apply when the signal generator is programmed to 804 001499 MHz In this troubleshooting procedure it is useful to have the undivided Sub Synthesizer VCO signal available On the Sub Synthesizer move the jumper from 1 2 to If the voltage at TP27 is approximately 1 5 volts check TP22 There should be a 1 MHz TTL square wave If the signal is missing or the frequency is incorrect work backwards from this point If this frequency is correct the problem is probably in the phase detector U30 32 or loop amplifier U34 etc At U21 9 there should be a 10 MHz TTL square wave The input U21 11 should be a 20 MHz TTL square wave At U21 3 there should be a 40 MHz TTL signal There should be a 40 MHz ECL signal at both U20 2 and U20 14 The frequency input J6 from the Coarse Loop A2 should be approximately a 600 mV p p 40 MHz signal If the voltage at TP27 is around 23V remove the shorting jumper connecting TP40 TP41 and connect a variable power supply to TP41 being careful not the short to TP40 which could destroy U34 This opens the loop and allows the frequency ofthe Sub Synthesizer VCO to be controlled directly Use a spectrum analyzer or counter connected to the undivided Sub Synthesizer VCO output A3 J3 to monitor the frequency Adjust the power supply so that the frequency tunes from approximat
304. ivider combination TROUBLESHOOTING AND REPAIR FREQUENCY AND PHASE MODULATION RSIG Rck VSIG Vck1 Vck2 DAC Coin OVIp DAC OVIp NO COINCIDENCE COINCIDENCE Figure 6E 3 Divider Phase Detector Timing Diagram The phase detectors operate at the phase detector reference frequency to produce output signals that are related to the phase relationship of the FM oscillator divider combination to the phase of the reference frequency divider combination One of the phase detectors is programmed active The output of the active phase detector is selected with the analog switch U24 This signal from the analog switch is amplified in the integrating loop amplifier 025 The result is filtered in the low pass filter L5 7 and associated capacitors to reduce the modulation of the 80 MHz FM oscillator by the phase detector reference frequency The filtered output drives the VCO CONTROL port of the 80 MHz FM oscillator to achieve phase lock and maintain correct center frequency In the standard phase detector U21 one of two outputs is a pulse having a duty cycle which is related to the phase relationship of the inputs The other output becomes active for wide phase deviation These output signals drive the voltage level shifter circuits Q10 Q11 and the connected resistors which drive diode CR20 24 switched resistor current sources These currents pulses are passed through the analog switch p o U24 to the loop amplifier U25
305. l for either HI DEVIATION or not The remaining sections of 05 provide the temperature compensation signal V TCCOMP 9 is a temperature sensitive resistor Divider Section 6E 5 The divider section consists of two programmable divider sections the reference frequency divider and the variable frequency divider The reference frequency divider consists of U7 U8 09 010 and U13 The variable frequency divider consists of U12 U14 015 016 017 and 049 Each divider section respectively divides the referency frequency and the variable frequency by the same division The divider sections receive 20 MHz and divide to one of the following frequencies 5 MHz 200 kHz 50 kHz which is a division by 4 100 or 400 from the 20 MHz or it is 16 400 or 1600 from the 80 MHz FM oscillator Both dividers are programmed to divide the same by the control logic Each divider consists of three parts a divide by four section a divide by four section and a divide by 25 section Multiplexers U13 and U49 control each divider section for the correct division A division by 4 5 MHz usesjust the first divide by four A division by 100 200 KHz uses the first divide by four and the divide by 25 A division by 400 50 kHz uses all three divider sections Each ofthe divider sections has different outputs The reference divider section has two outputs a signal called RSIG and a signal called Rck The variable frequency divider has three output si
306. l reference Either a 10 MHz or 5 MHz external reference may be selected by special function A 1 2 MHz reference may also substituted for the 5 MHz reference by setting a switch on the Coarse Loop PCA The 40 MHz reference frequency is doubled to 80 MHz This is used as the local oscillator for the HET band and is divided down to 20 MHz for use as the reference for the Al4 FM PCA The coarse loop generates the 576 to 960 MHz signal using a combination of phase lock and delay line discriminator frequency control circuitry to produce a low phase noise signal The delay line is a 125 ns cable contained in the module The sub synthesizer generates a 16 to 32 MHz signal with 1 Hz resolution This is further divided on the Sum Loop to 8 to 16 MHz The sub synthesizer generates the fine frequency steps using a modified N divider loop with a single sideband mixer SSB in the feedback path The sub synthesizer VCO runs from 160 to 320 MHz The reference frequency for the loopis 1 MHz which would normally provide 1 steps in a conventional N divider loop However by using pulse deletion which is controlled by a rate multiplier the resolution is extended to 10 kHz Additional resolution is gained by introducing a 10 to 20 kHz signal in a SSB mixer This signal is produced by a gate array which contains a 14 bit rate multiplier The A14 FM PCA also generates an 80 MHz signal that can be frequency modulated These signals are combined i
307. ll variation and thereby minimizes loop gain variation and consequently minimizes bandwidth variation C7 is adjusted adjusted to give the optimum level out of the Premodulator PCA at 1056 MHz 1 Remove bottom instrument cover and bottom module plate cover 2 Program UUT to SPCL 01 800 MHz and 7 dBm Measure the output power of the Premodulator PCA by disconnecting the cable from J16 on the Premodu lator PCA and connecting the power meter Adjust R51 for 3 5 dBm 3 Editthe frequency to 1056 MHz and observe the power again Adjust C7 to obtain 4 5 dBm 4 5 dB 4 Repeat steps 2 through 4 5 Remove the power meter and move the cable from the output board to J16 on the Premodulator PCA 6 Reinstall the bottom module cover and the bottom cover Output PCA Q16 Bias Adjustment R96 6D 21 The following procedure covers the adjustment of R96 on the Output PCA TEST EQUIPMENT REMARKS This adjustment is required only if Q16 or any associated parts are replaced This adjustment sets the bias current in the output transistor for designed operating conditions PROCEDURE R96 is adjusted for 1 355V DC between TP1 and TP2 Remove the bottom cover of the instrument the bottom module cover and the pulse cover This allows access to both the test points and R96 2 Place the positive lead ofthe DVM on and the negative lead on TP1 Set the DVM to VDC and the 2 volt range 3 Turn the signal generator
308. loop Table 6C 11 presents the nominal characteristics ofthe signals at the various test points on the A12 Sum Loop PCA The normal range ofthe signals along with specific values for the instrument diagnostic state SPCL 909 are listed SUM LOOP ASSEMBLY ADJUSTMENTS 6C 33 The following procedures cover the five potentiometer adjustments on the 12 Sum Loop listed below R112 Steering Level R121 Buffer Gain Match R116 FM Null R167 Loop Gain R132 Acquisition Oscillator Level NOTE These adjustments are not routine and are required only when associated components have been replaced or when the adjustment has been changed Steering Level Adjustment R112 6C 34 TEST EQUIPMENT REMARKS The Steering Level Adjustment is normally required only when U103 or any associated components are replaced or when the adjustment has shifted 6C 41 TROUBLESHOOTING FREQUENCY SYNTHESIS AND REPAIR PROCEDURE The Sum Loop VCO steering voltage is adjusted to 26V DC with the Sum Loop VCO steering DAC set to full scale 1 Program the UUT to SPCL 909 2 Program the UUT to SPCL 943 This special function programs all DACS to full scale 3 Connect the DVM to measure the voltage between and 15 ground 4 Adjust R112 for 26 00 x 02V 5 Program the UUT for SPCL 00 This clears all Special Functions Buffer Gain Match Adjustment R121 6C 35 TEST EQUIPMENT REMARKS
309. ls WRU and WRL are write enables for the upper byte and lower byte respectively Front Panel Interface 6B 6 Data is transferred to and from the front panel circuitry through tri state bidirectional data buffer U31 The corresponding address signals are transferred through tri state buffer U32 These buffers are active when a front panel latch is addressed and the buffer control signal from U43 is low Otherwise the buffer is in the high impedance state To reduce RF emissions from the Generator low pass filters and bypass capacitors are used on all data and select signals to the front panel The front panel interrupt rate is determined by the binary dividers U14 and U20 Under normal operation the system clock is divided by 8192 to generate a front panel interrupt every 540 microseconds When the display is blanked by special function the interrupt rate is divided by an additional factor of 32 to reduce the burden on the microprocessor thus reducing the software response time IEEE 488 Interface 6B 7 All IEEE 488 communications are handled 028 an NEC wPD7210 talker listener IC The 7210 is connected directly to the system address and data bus and communicates with the microprocessor as a memory mapped 1 device The active low interrupt signal IEINTL is connected to the level two interrupt on the microprocessor Tri state bus drivers U29 and U30 interface the 7210 directly to the IEEE 488 bus Attenuator Control Interface 6B 8
310. ltages LOCATION VOLTS DC ON bias transistor collector Q4 Q5 or Q6 depends on band 14 3 OFF bias transistor collectors 0 ON oscillator transistor collector Q1 Q2 or Q3 depends on band 48 3 OFF oscillator transistor collectors 49 6 U1 U2 outputs 444 CR7 CR8 CR9 node 49 9 6 32 FREQUENCY SYNTHESIS TROUBLESHOOTING AND REPAIR VOd YAZISSHLNAS GNS V ZHW 26 91 HO sn 6 Y01930 3svHd 019 60 dd 211 ZHN9L ZHW 8 en db OY ES 1 ddl HIOAWNS 0141 841 Z 0HdWOONnS 1 1 Sin HOLVHVdWOO HOLO3Q 550 7 oianvWwns X20 INn 3901Nn HOlVTII2SO NOILISIQOOV orn dV 400141 HOLVN and 391 60180101 3001 NOILISINDOV 2 1 N 9 dOO1 JH 1 OOAWNS doo1 H3aisWns dV 40193130 3SVHd ONIH33IS st HM r gt ONIH331S in L H3XIN er 141 oMP du eonan NUI dWV 14 XE nn ZHN 896 925 4001 dSuvoo sv Figure 6C 8 Sum Lo
311. luke Mfg Co Inc Some semiconductors and custom IC s can be damaged by electrostatic discharge during handling This notice explains how you can minimize the chances of destroying such devices by 1 Knowing that there is a problem 2 Learning the guidelines for handling them 3 Using the procedures and packaging and bench techniques that are recommended The Static Sensitive S S devices are identified in the Fluke technical manual parts list with the symbol The following practices should be followed to minimize damage to S S devices WM Mh 2 3 3 DISCHARGE PERSONAL STATIC BEFORE HANDLING DEVICES USE A HIGH RESIS 1 MINIMIZE HANDLING TANCE GROUNDING WRIST STRAP 2 KEEP PARTS IN ORIGINAL CONTAINERS UNTIL READY FOR USE 4 HANDLE S S DEVICES BY THE BODY Page 1 of 2 5 USE STATIC SHIELDING CONTAINERS FOR HANDLING AND TRANSPORT 6 DO NOT SLIDE SS DEVICES OVER ANY SURFACE 7 AVOID PLASTIC VINYL AND STYROFOAM IN WORK AREA WHEN REMOVING PLUG IN ASSEMBLIES HANDLE ONLY BY NON CONDUCTIVE EDGES AND NEVER TOUCH OPEN EDGE CONNECTOR EXCEPT AT STATIC FREE WORK STATION PLACING SHORTING STRIPS ON EDGE CONNECTOR HELPS TO PROTECT INSTALLED SS DEVICES HANDLE 5 5 DEVICES ONLY AT A STATIC FREE WORK STATION ONLY ANTI STATIC TYPE SOLDER SUCKERS SHOULD BE USED ONLY GROUNDED TIP SOLDERING IRONS SHOULD BE USED PORTIONS REPRINTED WITH PERMISSION FROM TEKTRONIX INC AND G
312. med at a high deviation The second tests is performed with the High Rate 6M mode enabled Table 6 6 lists the test conditions 6 9 TROUBLESHOOTING AND REPAIR Table 6 5 FM Tests EXPECTED STATE CODE FM DEV MOD FREQ LOW RATE FM OF FM LOOP 310 100 kHz 1 kHz Off Locked 311 4 MHz 30 Hz Off Unlocked 312 4 MHz 63 Hz Off Locked 313 20 kHz 1 kHz Off Locked 314 10 kHz 1 kHz Off Locked 315 10 kHz 1 kHz On Locked RF Frequency 640 MHz RF Amplitude 0 dBm Mod Frequency 1 kHz Internal FM On Table 6 6 Phase Modulation Test Conditions EXPECTED STATE CODE PM DEV MOD FREQ HIGH RATE 2M OF FM LOOP 316 100 rad 1 kHz Off Locked 317 10 rad 20 kHz On Locked RF Frequency 640 MHz RF Amplitude 0 dBm Mod Frequency 1 kHz Internal OM DCFM Test 6 28 The DCFM Test see Table 6 7 verifies the operation ofthe DCFM status indicator This low indicator reports the relative position of the DCFM DAC setting to the corresponding ACFM control voltage When the DCFM DAC is set to zero the indicator should report that it is too low Table 6 7 DC FM Tests CODE DCFM DAC EXPECTED STATE OF DCFM HI LO INDICATOR 318 0 Low RF Frequency 640 MHz RF Amplitude 0 dBm TROUBLESHOOTING AND REPAIR Coarse Loop Tests 6 29 The first three Coarse Loop Tests see Table 6 8 program a frequency in each of the three Coarse Loop VCO bands with the normal
313. must be done in the sequence presented If more than one adjustment is necessary do them in the sequence presented Mod Control PCA Level DAC Offset Adjustment R23 6D 11 TEST EQUIPMENT DVM REMARKS The level DAC offset adjustment is normally required only when U4 or any associated components are replaced CAUTION This adjustment directly affects the output level and should not be made indiscriminately PROCEDURE The level DAC offset R23 is adjusted for 0 0 5 mV at TP7 with the RF OUTPUT off TROUBLESHOOTING AND REPAIR RF LEVEL AM Access R23 by removing the bottom instrument cover and removing the bottom module cover Program the UUT to SPCL 01 and program the RF OUTPUT to OFF Connect the DVM to measure the voltage between TP7 and ground on the module plate Adjust R23 for an indication of 0 mV 40 5 mV Program the UUT RF OUTPUT to ON Reinstall the module plate cover and instrument cover when the adjustments are complete Mod Control PCA DAC Offset Adjustment R8 6D 12 TEST EQUIPMENT REMARKS The AM DAC offset adjustment is normally required only when US or any associated components are replaced CAUTION This adjustment directly affects the output level and should not be made indiscriminately PROCEDURE The AM DAC offset R8 is adjusted for 0 0 5 mV at TP6 with AM off 1 Access R8 by removing the bottom instrument cover and the bottom module plate cover
314. n The Z5 U35 combination is also selected relative to ACFM or PHASE MOD Table 6E 1 shows the relationship between selected modulation ranges and functions for inputs controls and outputs Table 6E 2 shows the relationship between the modulation ranges and the FM DAC values Table 6E 2 Modulation Ranges and FM DAC Values FM DAC FM Deviation Mult 1 111 512 1056 256 512 128 256 64 128 32 64 15 32 and 01 15 6 4 00 MHz 2 00 MHz 1 00 MHz 500 kHz 250 kHz 125 kHz 1 01 MHz 501 kHz 251 kHz 126 kHz 62 6 kHz 31 3 kHz mult 1 mult 2 mult 4 mult 8 mult 16 mult 32 5 1 00 MHz 500 kHz 250 kHz 125 kHz 62 5 kHz 31 2 kHz 251 kHz 126 kHz 62 6 kHz 31 3 kHz 15 7 kHz 7 82 kHz mult 4 mult 8 mult 16 mult 32 mult 64 mult 128 4 250 kHz 125 kHz 62 5 kHz 31 2 kHz 15 6 kHz 7 81 kHz 62 6 kHz 31 3 kHz 15 7 kHz 7 82 kHz 3 91 kHz 1 96 kHz mult 16 mult 32 mult 64 mult 128 mult 256 mult 512 3 62 5 kHz 31 2 kHz 15 6 kHz 7 81 kHz 3 90 kHz 1 95 kHz 15 7 kHz 7 82 kHz 3 91 kHz 1 96 kHz 977 Hz 489 Hz mult 64 mult 128 mult 256 mult 512 mult 1024 mult 2048 2 15 6 kHz 7 81 kHz 3 90 kHz 1 95 kHz 976 Hz 488 Hz 3 91 kHz 1 96 kHz 977 Hz 489 Hz 245 Hz 123 Hz mult 256 mult 512 mult 1024 mult 2048 mult 4096 mult 8192 1 3 90 kHz 1 95 kHz 976 Hz 488 Hz 244 Hz 122 Hz 0 Hz 0 Hz 0 Hz 0 Hz 0 Hz 0 Hz mult 1024 mult 2048 mult 4096 mult 8192 mult 16384 mult 32768 0 CW MODE 6E 9 TROUBLESHOOTING AND REPAIR FREQUENCY
315. n a response is received the controller gets a mod meter reading and sends it to the signal generator with the command The program remains in the main loop until the signal generator returns the end code 9E 09 Hz in response to the CC FREQ command The main loop is then exited and the data is saved with the CC SAVE command Each time the signal generator receives a reading from the controller it adjusts its internal settings and programs the new AM depth When the signal generator receives two consecutive readings within 0 196 of the target value 50 096 it considers the adjustment value correct and returns the end code The controller program must ensure that each mod meter reading is settled before sending the reading to the 6080A AN The program listing in Appendix G uses a simple but effective method to obtain valid mod meter readings The programming commands used in a remote AM calibration procedure are listed in the Table 3 2 See Table 5B 3 in Section 5B of the Operator Manual for a complete syntax description of each command CLOSED CASE CALIBRATION Table 3 2 Remote Programming Commands for AM Calibration Procedure COMMANDS DESCRIPTION CAL AM Initiate the remote AM calibration procedure CC RDAM Send the mod meter reading to the 6080A AN CC FREQ Request the RF frequency CC TARGET Request the target value RFOUT Program the RF output on off CC SAVE Save the measured data CC EXIT Ab
316. n outputs include Sum Loop VCO steering port and phase lock port voltages and a phase lock status indicator for the controller These circuits are described in the following paragraphs 6C 35 TROUBLESHOOTING AND REPAIR FREQUENCY SYNTHESIS 6C 36 LOOP AMPLIFIER The loop amplifier consists of a low frequency path and a high frequency path connected in parallel and 18 driven by the phase detector voltage at the loop filter output L26 This configuration was chosen to minimize noise and phase shift at frequencies around the unity loop gain frequency of 500 KHz The low frequency path is operative from DC to about 30 kHz and includes OP AMPS 0104 0105 and associated components 0105 is also configured to act as a Wien bridge type acquisition oscillator When the sum loop is unlocked U105 oscillates at either 800 Hz or 14 kHz depending on switching FETs Q106 107 which switch capacitors C127 and C131 Potentiometer R132 sets the amplitude of oscillation U105 stops oscillating and acts as a gain of 3 amplifier when phase lock is obtained due to loop dynamics The high frequency path is operative for frequencies greater than about 30 kHz and includes 0108 and associated components 0108 is a low noise high f transistor configured as an emitter follower An R C circuit sums the outputs of the two paths with C137 and C138 providing high pass and low pass characteristics respectively Loop gain adjustment is provided by R167 The
317. n path consists of Z7 U32 U38 U36 Z5 and U35 and associated components This path operates in all modes of modulation except in the DCFM mode and the CW mode The modulation range is determined by a range network and switch Z7 and U32 in conjunction with a range network and switch Z5 and U35 relative to the reference frequency The modulation signal is applied to the range resistor network Z7 selected by analog switch U32 and applied to the virtual ground input of a first section of dual op amp U38 The selected feedback network determines the gain and function The output of the first op amp U38 is processed by the range network Z5 and arange switch U35 The resistors R102 and R145 determine the gain of the low rate path for and PHASE MOD respectively The selected feedback network consists of capacitors and resistors C70 and R95 for ACFM R98 and C71 for PHASE MOD and R146 R147 and C76 for high rate PHASE MOD 6E 7 TROUBLESHOOTING AND REPAIR FREQUENCY AND PHASE MODULATION Table 6E 1 Modulation Control Table 800 MHz RF Frequency OOO AN lt gt lt gt lt gt lt gt lt gt 600000 58444566 I ai 0 0 10 10 10 QN QN gt lt gt lt gt lt gt lt QN QN QN 2
318. n the Sum Loop PCA The first mixer combines the the sum loop VCO output the fundamental frequency 480 to 1056 MHz with the coarse loop frequency 576 to 960 MHz to produce a signal of 88 to 96 MHz This signal is subsequently mixed with the 80 MHz signal from the FM PCA to produce 8 to 16 MHz This is compared with 8 to 16 MHz from the sub synthesizer to generate a DC control voltage that locks the loop 2 3 2 4 Frequency Modulation 2 8 Frequency modulation FM is programmable with three digits of resolution in six ranges The deviation is programmed using the 12 bit FM DAC and three FM range bits The FM DAC and range settings are dependent on the programmed deviation and the RF output frequency The FM DAC and FM Range settings for each frequency band and FM deviation range are shown in Table 6E 2 in Section 6E The FM M modes are selected by the control bit PMODL The maximum programmable FM deviation is dependent on the RF output frequency FM deviations up to 4 MHz may be entered regardless of the output frequency However the STATUS indicator is flashed and the FM DAC is clamped at full scale if the entry is beyond the allowed upper limit for that frequency band The maximum programmable deviation in each frequency band is depicted in Section 4C Modulation in the Operators Manual The FM oscillator loop runs at 80 MHz with several modes of operation In the low deviation low noise mo
319. nS OL ZHW Ov uad4na N 2090 123 2 gt Le pa kad 6090 OL Loon 4020 OL 950 NOILOAS 170 30N3u333uU 1ndino OL ZHW 08 1090 398 N 2080 O d S0SO P0SO 8081 018 2 11819081 91901 739339 384 1X3 0 9 bz dOO1 80sn lt 6090 01811 7ALLOV 4 lt 15 HOIH Y3ZISSHLNAS 8NS OADL A Figure 6 6 Reference Section Block Diagram 6C 18 TROUBLESHOOTING AND REPAIR FREQUENCY SYNTHESIS The 40 MHz voltage controlled crystal oscillator VCXO consists of the 40 MHz third overtone crystal Y601 a grounded base stage Q606 and associated com ponents a low Q tuned circuit to ensure the crystal operates at the third overtone L601 C604 5 R602 and varactors CR603 5 This oscillator can be tuned approximately 1 kHz The feedback is from the collector to the emitter The output from the collector tuned circuit is lightly coupled C607 to a buffer amplifier 0601 The output ofthe buffer is connected to the 80 MHz section R606 R617 C610 and another pair of grounded base stages Q607 8 The outputs of these buffers are low pass filtered C616 17 L604 and 622 23 L605 One output is converted to ECL U602 and the other output drives the main loop phase detector buffer amplifier Q205 One output of U602 provides
320. nal at the output ofthe triple modulus prescaler TP33 should be an approximately 15 MHz TTL signal The signal at the output of the N divider gate array TP34 should be approximately 1 MHz As the 1 MHz digitis programmed this frequency should change since the divide ratio is changing To troubleshoot the low order digit generator check the signal at TP3 and TP4 There should be a 2596 duty cycle active high 20 MHz TTL signal Program the signal generator to 800 000000 MHz The signal at TP5 should be 10 MHz TTL As you program the UUT to 1 Hz 10 Hz and 100 Hz digits the frequency at TP5 should change by 20 kHz 200 kHz and 2 MHz respectively When the UUT is programmed to 800 000499 MHz the frequency at TP5 should be 19 98 MHz The outputs of the two divide by 10 U60 U61 should be 1 998 MHz and 19 98 kHz respectively The output of the active quadrature generator U59 at TP37 and TP38 should be approximately 450 mV p p 19 98 kHz sine waves Monitor the frequency at TP21 as you tune the power supply Ifthe frequency is below 240 MHz the frequency at TP21 should be below 1 MHz There should be a TTL signal at TP24 that is predominantly low with very thin pulses going high There should be a similar signal at TP25 except the low voltage is approximately 0 5V and the high voltage is 42 8 V The voltage at TP40 should be about 28V Ifthe frequency is above 240 MHz the frequency at TP21 should be above 1 MHz The signal levels at TP
321. nalyzer The change should exceed 35 dB Deactivate external pulse by pressing the External Pulse key on the UUT and repeat steps d through f for UUT frequencies of 950 850 700 640 550 400 320 250 160 100 80 60 40 30 20 14 MHz 2 Dynamic Test a b Program the UUT to 640 MHz 10 dBm and external pulse modulation Connect the pulse generator to the UUT pulse input connector Set the pulse generator to a repetition rate of 50 kHz 43V pulse level and roughly 5096 duty cycle Connect the output of the UUT to the detector Terminate the detector into 50 ohms at the oscilloscope input Set the time base of the oscilloscope to 1 0 microsecond division Use the oscilloscope channel to invert the detector output signal Trigger the oscilloscope on this signal Set the variable position and gain on the oscilloscope so that the signal extends from 096 to 10096 on the graticule Measure the rise fall time from the 9096 to the 1096 coordinates Verify that the rise fall time is 1 microsecond 4 25 PERFORMANCE TESTS 4 26 1 Repeat steps fthrough at 320 MHz The time base of the oscilloscope should also be readjusted if necessary Remove the detector and reconnect the UUT directly into the oscilloscope Change the repetition rate of the Pulse Generator to 5 MHz Verify that the rise fall time is 1 microsecond for RF frequencies of 100 and 50 MHz static awareness A Message From John F
322. ncy modulation and amplitude These enclosures provide the necessary circuit to circuit isolation to prevent the generation of spurious signals The enclosures serve to isolate the generator circuits from the outside environment Rear Panel Section 2 5 The rear panel section includes the power supply the cooling fan various external connectors and the IEEE 488 Interface connector FUNCTIONAL DESCRIPTION 2 6 The key functional blocks of the signal generator described in the following paragraphs are Frequency Frequency modulation Phase modulation Level Amplitude modulation Pulse modulation Internal modulation oscillator Power supply Software Frequency 2 7 The output frequency Fo is programmable with 1 Hz resolution from 0 01 MHz to 1056 MHz The band controls are programmed in seven bands that are determined by the output frequency Fo A coarse loop and sub synthesizer frequency are determined for each band The programming of the coarse loop steering digital to analog converter DAC compensation DAC and VCO control bits are determined from the coarse loop frequency and the instrument specific compensation data The programming of the sub synthesizer compensation DAC 18 determined from the sub synthesizer frequency and the instrument specific compensation data The programming ofthe sum loop steering and compensation DACS are derived from the output frequency and the instrument specific compensation dat
323. ncy to 100 kHz and read the change in level in AM in dB Verify that the reading is greater than 3 0 dB Repeat steps a through c at 14 20 30 40 60 80 160 250 320 400 550 640 700 850 950 1056 MHz Repeat steps a through d at 3 dBm 5 Incidental FM Test a b Program the UUT for 50 INT AM at kHz at 640 MHz and 2 dBm Program the modulation analyzer to measure peak FM deviation in a 0 3 to 3 kHz bandwidth Connect the HFSSG to the external Local Oscillator input Verify that the incidental FM is less than 200 Hz NOTE It may be necessary to compensate for residual noise effects using the procedure presented in the manual provided with the Modulation Analyzer d Repeat step c at frequencies of 320 160 80 40 20 14 MHz 6 Residual AM Test a b Program the UUT to 640 MHz 13 dBm and no modulation Connect the UUT RF OUTPUT to the diode detector to the phase noise test set Calibrate the system by setting the UUT to 10 AM measure with modulation analyzer Verify that the residual AM is less than 0 01 using the integrated noise mode of the phase noise set 7 Accuracy and Distortion Test a b Connect the modulation analyzer to the UUT RF OUTPUT Program the modulation analyzer to measure peak FM in a 0 3 to 3 kHz bandwidth Program the UUT frequency to 640 MHz 7 dBm 20 kHz deviation INT FM and 1 kHz modulation rate PERFORMANCE TESTS d Set the d
324. nd CR6 for VT less than 7 5V and enables the high band filter between CR7 and CR8 for VT greater than 7 5 The switching voltage 7 5V corresponds to about 230 MHz The filtered signal is next applied to resistive splitter R13 R17 One output drives monolithic amplifier U2 which provides isolation and boosts the signal to about 7 dBm This signal connects to the A4 Sub Synthesizer PCA by a through the plate coaxial connector at P1 The other splitter output drives ECL frequency divider U3 which is configured to divide by ten The divided output signal from U3 is filtered by a five element low pass filter L5 L6 C27 C29 and connects to the A12 Sum Loop PCA at J2 by a coaxial cable This signal ranges in frequency from 16 to 32 MHz SUB SYNTHESIZER VCO TROUBLESHOOTING 6C 12 6C 16 A problem in the Sub Synthesizer VCO can cause uncal status response 242 Sub Synthesizer unlock and can also cause self test failure 324 To test the VCO independent ofthe Sub Synthesizer PCA a voltage source such as alab power supply can be connected to the phase lock port at J1 pin 4 This will override the voltage supplied by the Sub Synthesizer PCA and won t cause damage Vary the phase lock voltage from 2 to 23V and observe the signal at connector J2 on a spectrum analyzer The frequency should vary from about 16 to 32 MHz and the level should be about 2 dBm If the signal is not as described the VCO is likely faulty As a first step in troubleshoot
325. nd resume the procedure Abort the Cal Procedure Press once the prompt Clr is displayed Press again to abort the procedure The message Clr is displayed to confirm the selection All measured data is discarded and the previous instrument state is restored Press any other key to resume the procedure CLOSED CASE CALIBRATION Remote Level Calibration Procedure 3 13 The following paragraphs describe the remote level calibration procedure the remote commands used in the procedure and the elements required to build a functioning controller program Refer to the heading Remote Calibration earlier in Section 3 for general information relating to all remote calibration procedures A complete program listing that runs on a Fluke 1722A controller is provided in Appendix G The basic structure of the level calibration program is shown in Figure 3 4 initiate the level calibration procedure with CAL LEVEL initialize power meter MAIN LOOP request the RF frequency with CC FREQ if frequency 9e9 goto DONE read power meter send reading to 6080A AN with CC RDOWER gotoMAIN LOOP DONE store new data in calibration memory with CC SAVE end Figure 3 4 Basic Structure of Level Calibration Program The procedure is initiated by the command LEVEL The controller requests the signal generator s center frequency with the command CC FREQ and waits for a response When a respo
326. ne Power Cord 284174 1 BNC Dust Cap 478982 2 Table 1 2 Optional Accessories DESCRIPTION ACCESSORY NO Rack Mount Kit Includes M05 205 600 5 1 4 inch Rack Mount Ears Y6001 and 00 280 610 24 inch Rack Slides IEEE 488 Shielded Cable 1 meter Y8021 IEEE 488 Shielded Cable 2 meters Y8022 IEEE 488 Shielded Cable 4 meters Y8023 Coaxial Cable 50 ohms 3 feet BNC m both ends Y9111 Coaxial Cable 50 ohms 6 feet BNC m both ends Y9112 1 3 INTRODUCTION AND SPECIFICATIONS 1 4 Table 1 3 6080A ANSpecifications NOTE Unless otherwise noted the following performance is guaranteed overthe specified environmental and AC power line conditions two hours after turn on FREQUENCY 10 DIGIT DISPLAY BAND 50 15 2 BAND 15 32 2 BAND 32 64 BAND 64 128 2 BAND 128 256 2 BAND 256 512 2 BAND 512 1024 MHz RESOLUTION ACCURACY REFERENCE REFERENCE AMPLITUDE 1 2 DIGIT DISPLAY ACCURACY Rem SOURCE 5 FLATNESS i etoile etes 0 50 to 1024 MHz in 7 bands 0 50 to 14 999999 MHz 15 to 31
327. nector 2 Raise the synthesizer module Remove the 6 screws holding the bottom synthesizer module cover and remove the cover 4 Remove the 6 screws holding the PCA 5 Carefully remove the A3 Sub Synthesizer VCO PCA 5 4 ACCESS PROCEDURES Removing the A4 Sub Synthesizer PCA 5 8 1 Remove the 6 screws holding the top synthesizer module cover and remove the cover The 10 screws are adjustment access screws and need not be removed 2 Remove the 6 screws holding the PCA 3 Carefully remove the A4 Sub Synthesizer PCA Removing the A5 Coarse Loop VCO PCA 5 9 A WARNING THE SYNTHESIZER MODULE WHICH MUST BE RAISED TO GAIN ACCESS TO THE A5 COARSE LOOP VCO PCA IS HEAVY WHEN RAISING OR LOWERING THE MODULE OBSERVE THE PROCEDURE DESCRIBED UNDER THE HEADING INTRODUCTION AND SAFETY EARLIER IN SECTION 5 Raise the synthesizer module 2 Disconnect RF cable W14 from the connector at the front of the synthesizer module and remove the nut and lockwasher from the connector Lower the synthesizer module 4 Remove the 6 screws holding the top synthesizer module cover and remove the cover The 410 screws are adjustment access screws and need not be removed 5 Remove the 6 screws holding the PCA 6 Carefully remove the A5 Coarse Loop VCO PCA Removing the A6 Mod Oscillator PCA 5 10 1 Remove the 6 screws holding the top synthesizer module cover and remove the cover The 10 screws are adjustment access screws
328. nse is received the controller gets a power meter reading and sends it to the signal generator with the command CC RDPOWER The program remains in the main loop until the signal generator returns the end code 9E 09 Hz in response to the CC_FREQ command The main loop is then exited and the data is saved with the 5 command Each time the signal generator receives a reading from the controller it adjusts its internal settings and programs the new level When the signal generator receives two consecutive readings within 0 01 dB of the target value 10 00 dBm it considers the displayed adjustment value correct and returns the end code The controller program must ensure that each power meter reading is settled before sending it to the signal generator The program listing in Appendix G uses a simple but effective method to obtain valid power meter readings The programming commands used in aremote level calibration procedure are listed in the Table 3 6 See Table 5B 3 in Section 5B of the Operator Manual for a complete syntax description of each command 3 13 CLOSED CASE CALIBRATION Table 3 6 Remote Programming Commands for Level Calibration Procedure COMMANDS DESCRIPTION CAL LEVEL Initiate the remote level calibration procedure CC RPOWER Send the power meter reading to the 6080A AN CC FREQ Request the RF frequency CC TARGET Request the target value RFOUT Program the RF output on off CC SAVE Save t
329. nt software The display is comprised oftwo vacuum fluorescent displays and their associated control circuitry The two displays are refreshed as four groups ofnine display fields usually a digit each The four groups share the digit grid strobes but have individual segment anode strobes Data Communications 6B 28 Display data is sent through a byte wide bidirectional data bus from the Controller and is latched 01 through 05 and 019 The front panel latch select signals DIGIL DIG2L SEGIL SEG2L SEG3L and SEG9L are decoded by U20 These latch select signals determine which latch receives the data Level shifting buffer drivers U6 through U10 interface the latches directly to the 37V grids and anodes of the vacuum fluorescent displays Display Filament Voltage 68 29 The 6 0V AC filament voltage for the display is derived from center tapped winding on the Power Supply PCA transformer T1 The AC filament voltage is biased at 6 2V above ground by circuitry on the A14 Power Supply PCA to provide a cutoff potential for the displays Bright Digit Effect 68 30 The bright digit effect is achieved by providing three extra refresh cycles strobes to the specified digit A grid current limiting resistor R3 ensures uniform digit brightness by controlling electron depletion from the display cathode filaments Switchboard Interface 6B 31 The digit strobe data latched by U1 is buffered by open drain inverters U13 and U
330. o remove the Attenuator RPP assembly from the module leaving the control power ribbon cable attached Connect a grounding lead between the Attenuator RPP housing and the Output Module Program the UUT to 10 dBm and check continuity with an ohmmeter from J1 through to C7 Be sure that the RPP is not tripped Tracing through the Attenuator RPP may find a defective relay contact RPP trip operation can be checked using the test points provided on the Relay Driver PCA Connect a power meter to the UUT RF OUT connector and program the UUT to SPCL 01 and then set level to 10 dBm A momentary short across the terminals of should trip the RPP causing the observed output power to drop by more than 30 dB Failure indicates a problem with U1 A U1 D Q8 Q9 K8 or associated circuitry The RPP can be reset by pressing the RF ON button The RPP itself can be reset by a momentary short across TP2 but this will not reset the rest of the UUT to RF ON Failure indicates a problem with U1 B UI A or associated circuitry Program the UUT to amplitude fixed range SPCL 51 and edit the level to 10 dBm using the knob Place a clip lead short across TP3 This will allow the RPP to trip at low RF levels Now edit with the knob the level upwards in 1 dB steps The RPP should trip prior to reaching 13 dBm Failure indicates a problem with on the Attenuator RPP PCA or with U1 A U1 D Q8 K8 or associated circuitry on the Relay Driver P
331. odulator attenuation is at a minimum and the leveling loop becomes inoperative unleveled This condition could be due to a fault or some abnormal operation such as overmodulation In this case the comparator output UNLVLL goes low The Controller PCA senses this low and causes the front panel STATUS indicator to flash and displays an unleveled status code 241 ifinterrogated 6D 5 TROUBLESHOOTING AND REPAIR RF LEVEL AM 6D 6 Level Control 6D 6 The instrument output level is set by the level control circuit Inputs to this audio signal processing circuit are the internal and external modulation signals a DC reference voltage and the digital control commands The circuit output is the leveling loop control voltage that provides vernier level control and amplitude modulation control of the signal generator output Digitally encoded level modulation depth and temperature compensation information are provided by the A11 Controller PCA External AM signals are cabled to J13 pin 1 on the Modulation Control PCA This point is monitored by an AC peak detecting voltmeter composed of comparator U16 and 017 and associated parts A similar circuit is present to monitor external FM signals and they share a common reference circuit R70 through R74 and CR12 These components provide voltages of 1 02 at U16 pin 8 and 98V at U16 pin 10 When these voltages are exceeded these comparators trip and trigger monostable multivibrators U17A and U17B
332. odule near the attenuator assembly A20 One screw is accessible from the top of the instrument the other from the bottom 2 Disconnect the RF Output cable W1 from the type N RF output connector J1 3 Remove the decals from both front panel handles Removing the decals ruins them Attach new decals when reassembling to maintain proper instrument appearance The part number for the decal is listed in Section 7 4 Remove the five flat head screws from each front panel handle and slide the front panel forward 5 Disconnect the power ribbon cable W20 and the two controller ribbon cables W18 and W36 from the front panel display board Al 6 Disconnect the inner part of the BNC connectors on the Mod Input and Mod Output cables W2 W3 W4 and WS Removing the Rear Panel Section 5 5 1 Disconnect the synthesizer and output module power cables W22 and W23 and the front panel power cable W20 from the 15 Power Supply PCA 2 Disconnect the controller IEEE ribbon cable W17 from the A16 IEEE PCA Disconnect the Ref In and Ref Out RF cables W6 and W7 from the synthesizer module 4 Remove the decals for both rear panel handles Removing the decals ruins them Attach new decals when reassembling to maintain proper instrument appearance The part number for the decal is listed in Section 7 5 Remove the five flat head screws from each handle The rear panel section can now be removed 5 3 ACCESS PROCEDURES Removing the A2 Co
333. ogic low to the pulse modulator therefore the pulse modulator will attenuate the RF output and the RPP indicator will not trip The second test configures the mod oscillator to send a steady logic high to the pulse modulator therefore the pulse modulator will not attenuate the RF output and the RPP indicator will trip Table 6 12 Pulse Modulator Tests PULSE CONTROL EXPECTED STATE CODE RF FREQUENCY AMPLITUDE LOGIC LEVEL OF RPP INDICATOR 337 800 MHz 16 dBm Low Not Tripped 338 800 MHz 16 dBm High Tripped Filter Tests 6 34 The Filter Tests see Table 6 13 verify the selection and operation of each of the output filter and divider sections The first 12 tests program a frequency within the band of interest and programs the correct filter and divider settings The ALC loop leveled indicator should report that the loop is leveled The next six tests program filter settings that do not correspond with the programmed frequency The ALC loop leveled indicator should report that the loop is unleveled TROUBLESHOOTING AND REPAIR Table 6 13 Filter Tests EXPECTED STATE CODE FREQUENCY FREQ BAND OF ALC LOOP 339 20 MHz 15 22MHz Leveled 340 30 MHz 22 32MHz Leveled 341 40 MHz 32 47MHz Leveled 342 60 MHz 47 64MHz Leveled 343 100 MHz 64 128 MHz Leveled 344 150 MHz 128 180 MHz Leveled 345 200 MHz 180 256 MHz Leveled 346 300 MHz 256 350 MHz Leveled 347 400 MHz 350 512MHz Leveled
334. oints for the A2 Coarse Loop PCA The following procedures cover the five adjustments on the A2 Coarse Loop PCA R102 Discriminator Video Amplifier Offset R221 Steering Gain R227 Acquisition Oscillator Level L601 40 MHz Oscillator Tuning 1612 3 80 2 Filter Tuning R617 80 2 Level L205 2 MHz Notch Adjust SW502 Alternate Reference Frequency Selection These adjustments are not routine and are required only when associated components have been replaced or when the adjustment has been changed or has shifted Discriminator Video Amplifier Offset Adjustment R102 6C 18 TEST EQUIPMENT DVM REMARKS Discriminator Video Amplifier Offset adjustment is normally required only when 0102 or any associated components have been replaced or when the adjustment has shifted PROCEDURE TROUBLESHOOTING AND REPAIR FREQUENCY SYNTHESIS The output ofthe Discriminator Video Amplifier TP9 is adjusted to OV DC 1 Program the UUT to SPCL 909 2 Connect the DVM to measure voltage between TP9 and ground 3 Adjust R102 for OV 10 mV Table 6C 6 A2 Coarse Loop PCA Test Points TEST SIGNAL RANGE TYPICAL SIGNAL DESCRIPTION POINT TYPE 1 ECL 40 MHz 800 mV p p N divider Output TP2 ECL 0 16 MHz 2 MHz 25 ns AH Rate Multiplier Output RF ECL 120 240 MHz 162 MHz 5 Divide by 4 Prescaler Output TP4 AC 40 MHz 1V p p 40 MHz Oscillator Output TP5 AC 40 MHz 1 2V p p 40 MHz Reference Am
335. op Block Diagram 6C 33 TROUBLESHOOTING AND REPAIR FREQUENCY SYNTHESIS 6C 34 SUM LOOP A12 CIRCUIT DESCRIPTION 6 29 The A12 Sum Loop generates the fundamental frequency band 480 1056 MHz by combining signal frequencies from the FM the Sub Synthesizer and the Coarse Loop PCAs The sum loop was designed for spurious signal generation of less than 100 dBc and for low phase noise contribution The relation between sum loop output frequency and the input frequencies follows For f sum 760 MHz f sum f coarse f FM f sub synth For f sum 760 MHz f sum f coarse f sub synth The 12 Sum Loop PCA includes a phase locked loop circuit that steers the frequency of the A9 Sum Loop VCO PCA to the correct value according to the above relations The loop includes an RF section with two stages of heterodyne frequency down conversion a phase detector circuit and an audio section containing the loop amplifier acquisition circuits and VCO coarse steering circuits These sections will be discussed in the following paragraphs The output signal from the A9 Sum Loop VCO PCA is coupled into the Output Section where the signal is further processed to generate the instrument output signal RF Section 6C 30 The RF section contains the RF amplifiers mixers and filters required to process the Sum Loop VCO signal through three successive stages of frequency down conversion The first stage subtrac
336. or TP1 and R71 2 Connect the DVM to and ground 3 Setthe UUT to SPCL 01 and observe the DVM 4 Adjust R71 for 0 980 volts 5 Reinstall the access screws and bottom cover Mod Control PCA Sum Steer Gain Adjustment R99 6D 17 TEST EQUIPMENT REMARKS The Sum Steer Gain Adjustment is normally required only when U32 U36 or any associated components are replaced PROCEDURE The sum steer voltage is adjusted to 10 24V with the Sum Loop VCO steering DAC set to full scale 1 Program the UUT to SPCL 01 2 Program the UUT to SPCL 942 This Special Function programs all DACS to full scale 3 Connect the DVM to measure the voltage between J2 pin 14 and module ground 4 Adjust R99 for 10 24V 01V 5 Program the UUT for SPCL 00 This clears all Special Functions 60 15 TROUBLESHOOTING AND REPAIR RF LEVEL AM 6D 16 Output PCA Het Mixer Level Adjustment R72 6D 18 TEST EQUIPMENT Power meter e Power sensor High Level Spectrum analyzer REMARKS The UUT must be operated at room temperature for at least one hour with the module covers in place before continuing with this adjustment procedure This adjustment is normally required only when mixer U4 or het band LO circuitry is replaced When adjusted an interaction with R10 exists therefore R10 adjustment is included in this procedure CAUTION This adjustment directly affects the output level and should not be made indi
337. or tolerance is defined for each procedure as a range of readings around the target value that the signal generator expects to receive when the adjustment is correct The division of responsibility between the controller and signal generator allows measurement equipment from various manufacturers to be used Adding a different meter to the system requires only that a new driver module be written for the controller NOTE The design ofthe controller software has a major impact on the accuracy realized One must carefully determine when the readings are settled and average several readings before sending the result to the 6080A AN Where applicable the meter specific calibrationfactors should be applied to the readings A sample program for each of the remote procedures is included in Appendix G The programs are written in Fluke BASIC and run on a Fluke 1722A controller Calibration Data 3 4 The calibration data is stored along with the compensation data in non volatile memory A redundant storage scheme enhances the integrity of the data One copy of the data is stored in the battery backed RAM and an identical copy is stored in the EEPROM The rear panel slide switch labeled CALICOMP must be set to the 1 ON position before a calibration procedure can be initiated The CAL and COMP annunciators flash when the switch is in the 1 ON position When a calibration procedure is initiated the CAL and COMP annunciators stop flashing and the
338. ort the cal procedure immediately ERROR Request the rejected entry status STATUS STATUS Load Request the overrange uncal status FM CALIBRATION 3 8 The FM calibration procedures allow a single point calibration ofthe FM deviation to be performed An RF modulation meter is connected to the 6080A AN s RF output and the FM calibration factor is adjusted based on the meter reading The procedure specific parameters are as follows Adjustment Range 10 kHz Adjustment Resolution 0 1 kHz Target Value 100 kHz Frequency 640 000000 MHz RF Level 10 0 Internal AM ON Modulation Frequency 1 kHz External Equipment RF Modulation Analyzer HP 8901 or equivalent When performing the front panel procedure use the edit knob to adjust the FM deviation until the measured FM deviation matches the target value When the remote procedure is performed the process is under the control of a program running on an IEEE 488 bus controller The front panel display is reconfigured during the procedures The target level is displayed in the modulation field the RF frequency is displayed in the frequency field the adjustment value is displayed in the amplitude field and the CAL annunciator is lit The display is consistent for the front panel and remote procedures All adjustments update a temporary copy of the FM calibration factor The copy in the calibration memory is updated only after the store command is given explicitly After the s
339. ot present is distorted or is of the wrong amplitude check level DAC U8 and If U8 and are OK it could be a write data error that could result from a faulty 01 or an interface bus fault 10 Using an oscilloscope verify the presence of a zero centered 8V p p sine wave at 5 If the signal is distorted check U11B and associated resistors R11 R12 R13 and switches S3 S4 With an AC voltmeter check for 2 8284 V rms 40 1 x2 8mV If the signal not within specified accuracy recalibrate R13 using normal calibration procedures 51 56 refer to analog switches on the Modulation Oscillator Pulse Generator Troubleshooting 6 8 To troubleshoot the pulse generator proceed as follows SETTING UP 1 Put instrument into preset default state by selecting entering SPCL 758 2 Setup the instrument for internal pulse operation SPCL 741 3 Enable INT AM modulation 4 Enter MOD FREQ of 10 kHz 100 us period 5 Setthe pulse width to 25 us SPCL 759 TEST PROCEDURE NOTE Modulation level control has no effect in pulse mode 1 Verify the presence ofa 10 0 MHz logic signal at TP10 If no signal is present at this point or the signal is the wrong frequency either U1 is faulty a data write error has occurred or the 20 MHz signal is inadequate 2 Using an oscilloscope connected to TP11 verify that the TTL level PULSE signal from Ul is at 10 kHz and that it has a positive pulse width of 25 us If not it i
340. output drives the IF2 amplifier which includes Q9 and Q10 and is configured for 21 dB gain 010 drives the RF port of mixer U3 with 7 dBm which is used as a phase detector The IF2 low pass filter also provides a DC path for 15V power for the IF2 amplifier The LO port of phase detector U3 is driven by a signal derived from the Sub Synthesizer PCA as follows 710 is connected to the 16 10 32 MHz signal from the A3 Sub Synthesizer PCA This ECL level signal is converted to TTL Q11 and related parts The TTL signal then drives U5 a D type flip flop that is configured to halve the input frequency The resulting 8 to 16 MHz Q and Q compliment outputs of U5 drive the LO port of U3 The IF output of U3 drives the loop filter a 13 element low pass type with input at R56 and output at L26 This filter allows audio frequency components to pass with minimum phase shift while adequately attenuating RF mixer products The loop filter output voltage is proportional to the phase difference between the RF and LO ports of U3 This signal drives the Audio Section which is described in the following paragraphs Audio Section 6C 31 The Audio Section contains the circuits required to acquire and maintain phase lock Inputs to this section include the phase detector voltage Sum Loop VCO coarse steering voltage SUMSTEER FM modulation signal SUMAUDIO FM range switching signals SUMVCO4 6 and Sum Loop VCO Kv information SUMCOMPHO 7 Audio Sectio
341. ow an edit up request is generated This information is transmitted to the Controller PCA by setting the knob interrupt signal KNOBINTL low and the knob direction signal KNOBUP high If the trigger signal makes a low to high transition while the window signal is low an edit down request is generated This information is transmitted to the Controller PCA by setting the knob interrupt signal KNOBINTL low and the knob direction signal The trigger signal is ignored when the window signal is high After servicing the interrupt and reading the directional information the controller resets the knob circuitry by toggling the reset signal KNOBRSTL Display Blanking 6B 34 Monostable U11 and NOR gate U12 clear the display if new field or segment strobes are not received This protects the display if the microprocessor stops refreshing Operate Standby Selection 6B 35 The front panel POWER switch selects the operate or standby modes When in the standby position the switch is closed the STANDBY signal is set high and LED CR1 is lit When in the operate position the switch is open the STANDBY signal is pulled low and LED CRI is off FRONT PANEL TROUBLESHOOTING 6B 36 Display and Controls 6B 37 If the display shows signs of activity but has missing or bright digits or segments the problem is most likely one ofthe data latches or drivers on the A1 Display PCA Ifthe display is blank and the controller is operation
342. ower meter PROCEDURE 1 2 10 Program UUT to SPCL 909 10 MHz and 67 dBm Calibrate then connect the power meter with a low level power sensor to the UUT RF OUTPUT Zero the power meter With the power meter measure the UUT output power dBm and record the measurement as the variable P Connect UUT RF OUTPUT through the 50 dB attenuator and the wideband amplifier to the input of the RF spectrum analyzer Use well shielded cables to avoid leakage that could affect the measurement Adjust the RF spectrum analyzer to display the signal using a resolution bandwidth of 1 kHz and a vertical display of 1 dB Div Adjust the reference level so that the response is at a convenient reference point on the display e g 2 dB below top scale This signal response corresponds to alevel of P A dBm where A is the value of the 50 dB attenuator Program the UUT to a level of 117 dBm remove the 50 dB attenuator and note the difference in the resulting response on the RF spectrum analyzer from the previous response P A The actual UUT output level is P A plus this difference and should agree with the programmed level to within the requirement Repeat steps 4 through 8 adding an additional 20 dB attenuator total 70 dB to the UUT RF OUTPUT and dial the signal generator level to 137 dBm It may be necessary to reduce spectrum analyzer resolution bandwidth Repeat steps 4 through 9 for frequencies of 14 20 40
343. pared to 1 reference established at each reference frequency The two turn loop must be 1 inch away from any surface of the UUT REQUIREMENT Radiated emissions induce lt 1 uV ofthe signal generator s output signal TEST EQUIPMENT 0 1 to 1050 GHz amplifier RF spectrum analyzer Two turn loop Type N termination A screen room may be required depending on the RF environment REMARKS If the UUT fails this test a feed through filter is probably broken or an improper mechanical assembly ie loose screws and or damaged or misplaced gaskets is indicated PROCEDURE 1 Connectthe UUT RF OUTPUT to the wideband amplifier input and connect the wideband amplifier output to the RF spectrum analyzer input Use well shielded cables to avoid leakage that could affect the measurement 2 Program the UUT to SPCL 909 3 Program the UUT to 107 dBm 4 Adjust the RF spectrum analyzer to display the UUT signal for a convenient reference Make this adjustment using a vertical scale of 10 dB division a resolution bandwidth of 3 kHz and a span division of 5 kHz division 5 Disconnect the wideband amplifier from the UUT and terminate UUT OUTPUT with the type N termination 6 Connect the two turn loop to the wideband amplifier input 7 Program the UUT to 13 dBm 8 Verify that the leakage indicated by the RF spectrum analyzer is less than 107 dBm 1 uV by moving the two turn loop over the UUT surface at a distance of 1 inc
344. pensated 1 AM signal multiplied by a factor proportional to the 14 bit level control number provided by the Controller PCA The signal generator RF output level adjustment is provided by potentiometer R20 and DAC offset voltage adjustment is provided by potentiometer R23 RF LEVEL TROUBLESHOOTING 6D 7 If the signal generator level is inaccurate or an unleveled condition exists the Output assembly 10 11 or the A20 Attenuator RPP Assembly is probably at fault If an unleveled condition exists the problem should be in the RF circuitry prior to the detector the detector circuitry or the DC part ofthe leveling loop circuitry Go to the heading Unleveled Condition later in Section 6D If there is no unleveled condition the problem is likely in the circuitry following the detector which includes the buffer amp Q7 the heterodyne circuit the pulse modulator the output amplifiers Q9 and 016 and the A20 Attenuator RPP Assembly Ifthe level problem exists only below 15 MHz troubleshoot the heterodyne circuitry If the level problem exists only in a specific frequency band check TROUBLESHOOTING AND REPAIR premodulator operation and switched filter operation controlling that band as shown in Table 6D 1 If the problem is not frequency dependent and if the level is accurate above 7 dBm but inaccurate below 7 dBm the Attenuator RPP Assembly is likely at fault Ifthe level problem is notin a particular frequency band it is ad
345. perates in the differential voltage mode If the frequency phase of the V input U503B 11 is greater than the R input U503A 3 there will be a net positive voltage from U503A 6 to U503B 8 The loop amplifier integrator U508 and associated components which drives a lead lag network R532 R530 C546 Q502 integrates the phase detector voltage and causes the voltage on the control line to the varactors CR603 5 to drop until the two frequencies match and the loop is locked Consequently if the frequency phase ofthe input is greater than the V input there will be a net negative voltage and the control voltage will rise until the loop is locked A small phase offset is set R512 to keep the phase detector in its linear region The bandwidth of this reference loop is changed by switching in various lead lag networks R505 R510 R530 R532 C530 C547 C549 C546 When in internal TCXO or external 10 or 5 MHz Q506 and Q502 are on and the loop bandwidth is approximately 30 Hz When the external reference is 1 or2 MHz Q506 is on and Q502 is off By turning Q502 off the gain is increased 5 times but since the division factor is 5 times greater the overall loop gain remains approximately constant The loop control voltage U508 6 is sensed by two comparators U509A B Ifthe voltage is below approximately 1 2V and above approximately 11V or there are pulses this indicates the loop is unlocked A one shot U512 converts these pulses into a lo
346. plifier Output TP6 DC 1V Varies Loop Amplifier Acquisition Oscillator Output TP7 DC 0 1V Varies VCO Phase Lock Port TP8 DC 2 22V 11V VCO Steering Port TP9 DC 50 mV Varies Discriminator Loop Amplifier Output TP10 Input for test TP11 DC 50 mV Varies Low Pass Filter Output TP12 Ground TP13 Shorting connection to disable acquisition oscillator TP14 Ground TP15 TTL 10 MHz 150ns AL Reference Loop Phase Detector Output TP16 AC 20 MHz 1V p p 20 MHz Reference to Modulation Oscillator TP17 AC 40 MHz 800 mV p p 40 MHz Reference to Sub Synthesizer TP18 DC 12 7 0 2V Constant On when internal TXCO 0 8 0 2V Constant Off when external or high medium stability option TP19 DC 1 11V 5 6V Reference Loop Amplifier Output TP20 Shorting connection to open reference loop for troubleshooting TP21 As measured with 500 ohm 10X RF probe TEK 6156 Actual level as displayed on spectrum analyzer will be approximately 20 dB lower 6C 27 TROUBLESHOOTING AND REPAIR FREQUENCY SYNTHESIS Steering Gain Adjustment R221 6C 19 TEST EQUIPMENT REMARKS The Steering Gain Adjustmentis normally required only when U207 or any associated components are replaced or when the adjustment has shifted PROCEDURE The Coarse Loop VCO steering voltage is adjusted to 24V with the Coarse Loop VCO steering DAC set to full scale 1 Program the UUT to SPCL 909 2 Program the UUT to SPCL 943 This Special Function programs all D
347. plus PEAK 2 using the modulation analyzer Refer to Table 4 5 for AM test conditions Program the UUT for a frequency of 640 MHz 0 dBm level INT AM at 50 AM depth and a modulation rate of 1 kHz Connect the modulation output ofthe modulation analyzer to the input of the distortion analyzer Verify that the mean AM depth plus PEAK 2 is between 43 0 and 57 PERFORMANCE TESTS e Setthe distortion analyzer to measure the total harmonic distortion THD of the 1 kHz modulation signal f Verify that the THD is less than 5 g Program the remaining combinations of RF frequency level and AM depth listed in Table 4 5 h Repeat the test in step g at levels of 2 dBm and 3 dBm which represent the extremes of internal circuitry operation i Verify that the mean AM depth for each combination is between the allowed limits and that the THD is less than the allowed limit Table 4 5 AM Test Conditions FREQUENCY LEVEL AM dBm 9 1056 0 30 50 90 950 0 30 50 90 700 0 30 50 90 640 0 30 50 90 550 0 30 50 90 320 0 30 50 90 160 0 30 50 90 80 0 30 50 90 40 0 30 50 90 20 0 30 50 90 14 0 30 50 90 4 19 PERFORMANCE TESTS 4 20 4 AM Bandwidth Test e Program the UUT for 5096 INT AM at 1 kHz rate at 100 MHz and 2 dBm With the modulation analyzer reading AM press the RATIO DB key to normalize the reading to 0 0 dB Set the modulation freque
348. power supply cable W22 from the A13 Controller PCA Disconnect the relay driver ribbon cable W19 from the A13 Controller PCA Remove the 6 screws holding the PCA Carefully remove the A13 Controller PCA 5 7 ACCESS PROCEDURES Removing the A14 FM PCA 5 17 LN waRNING THE SYNTHESIZER MODULE WHICH MUST BE RAISED TO GAIN ACCESS TO THE A14 FM PCA IS HEAVY WHEN RAISING OR LOWERING THE MODULE OBSERVE THE PROCEDURE DESCRIBED UNDER THE HEADING INTRODUCTION AND SAFETY EARLIER IN SECTION 5 1 Raise the synthesizer module 6 Remove the 6 screws holding the top output module cover and remove the cover The 10 screws are adjustment access screws and need not be removed Disconnect the FM Sum Loop ribbon cable W32 from the A14 FM PCA Remove the plug in capacitor C2 between the A12 Sum Loop and the A14 FM PCA Remove the 6 screws holding the PCA Carefully remove the A14 FM PCA Removing the A20 Attenuator RPP Assembly 5 18 Row WARNING THE SYNTHESIZER MODULE WHICH MUST BE RAISED TO GAIN ACCESS TO THE A20 ATTENUATOR RPP ASSEMBLY IS HEAVY WHEN RAISING OR LOWERING THE MODULE OBSERVE THE PROCEDURE DESCRIBED UNDER THE HEADING INTRODUCTION AND SAFETY EARLIER IN SECTION 5 Raise the synthesizer module Disconnect the RF Output cable W1 at the Attenuator Disconnect the Controller Relay Driver ribbon cable W19 from A20 Remove the 13 6 screws holding the Attenuator Removing the A22 Delay Cabl
349. put U1 RF amplifier 44 7 U8 output U1 RF amplifier 44 7 5 collector IF1 amplifier 49 5 collector IF1 amplifier 43 5 Q8 collector FM amplifier 49 8 Q9 collector IF2 amplifier 46 4 Q10 collector IF2 amplifier 48 5 Q11 collector ECL TTL buffer 41 0 Table 6C 11 A12 Sum Loop Test Points TEST SIGNAL RANGE TYPICAL SIGNAL DESCRIPTION POINT TYPE TP1 DC audio 4V OV Loop amp low frequency output TP2 audio 0 to 3 0V RMS OV SUMAUDIO buffer amplifier output TP3 DC audio Oto 26 0V 15V Sum Loop VCO steering voltage TP4 DC audio 8V oV Sum Loop VCO phase lock voltage TP5 DC audio 150 mV OV Phase detector voltage TP6 N A This test point is an input for sum loop test and alignment TP7 TTL TTL high low TTL high Loop disabling one shot output signal TP8 TTL TTL high low TTL high Acquisition oscillator switching signal DC audio 4V 0V Filtered loop amp LF output TP10 N A This test point is shorted to ground for sum loop test and alignment TP11 N A This test point is shorted to ground for sum loop test and alignment TP12 RF 20 to 28 dBm 24 dBm Buffered Sum Loop VCO signal 480 1056 MHz 600 MHz TP13 RF 210 4 dBm 2 dBm Amplified Coarse Loop VCO signal 576 968 MHz 696 MHz TP14 RF 13 dBm 13 dBm Buffered FM oscillator signal 80 MHz 80 MHz TP15 Ground RF Levels are approximate and are measured using a 500 ohm probe with a spectrum analyzer TROUBLESHOOTIN
350. r Inc Lincolnwood IL 79727 C W Industries Southampton PA 8C798 Ken Tronics Inc Milan IL 80031 Mepco Electra Inc Morristown NJ 80294 Bourns Instruments Inc Riverside CA 83330 Kulka Smith Inc A North American Philips Co Manasquan NJ 84411 American Shizuki TRW Capacitors Div Ogallala NE 86928 Seastrom Mfg Co Inc Glendale CA 89536 John Fluke Mfg Co Inc Everett WA 9W423 Amatom EI Mont CA 91293 Johanson Mfg Co Boonton NJ 91502 Associated Machine Santa Clara CA 91506 Augat Alcoswitch North Andover MA 91637 Dale Electronics Inc Columbus NE 95146 Alco Electronic Products Inc Switch Division North Andover MA 95275 Vitramon Inc Bridgeport CT 96881 Thomson Industries Inc Port Washington NY 98159 Rubber Teck Inc Gardena CA 98291 Sealectro Corp BICC Electronics Trumbill CT MANUFACTURER S FEDERAL SUPPLY CODES 00199 Marcon Electronics Corp Kearny NJ 00779 AMP Inc Harrisburg PA 01121 Allen Bradley Co Milwaukee WI 01295 TX Instruments Inc Semiconductor Group Dallas TX 02113 Coilcraft Inc Gary IL 02114 Amperex Electronic Corp Ferrox Cube Div Saugerties NY 02660 Bunker Ramo Eltra Corp Amphenol NA Div Broadview IL 02735 RCA Solid State Div Somerville NJ 03508 General Electric Co Semiconductor Products amp Batteries Auburn NY 03888 KDI Electronics Inc
351. r withdifferent feedback paths selected to change the division It is programmed with the bits to a steady state value of N 3 4 5 or 6 A toggle line TP2 allows the divider to be programmed to one more than its steady state value N 1 The rate multiplier generates a sequence of 0 to 19 pulses within a40 MHz frame The output of the rate multiplier drives this toggle line Consequently the divider divides by N part of the frame and N 1 for the remainder of the frame Depending on how the rate multiplier is programmed fractional division with a 2 MHz step size is obtained Because of the divide by 4 pre scaler this corresponds to a 8 MHz step at the Coarse Loop VCO frequency The output of the N divider U308 15 9 is connected to the mixer phase detector U203 The 40 MHz from the reference section is buffered in acommon base stage Q205 and amplified Q206 to provide the other input to the phase detector The output of the phase detector is low pass filtered C212 16 L204 5 with notches at 2 and 4 MHz to suppress the rate multiplier spurs A lead lag network R210 11 C211 provides proper high frequency termination for the mixer The output of the filter is connected to a loop amplifier U205 This amplifier provides lead lag compensation for the phase lock loop The output of this stage is fed into the acquisition oscillator state U206 This is set up as a Wien bridge oscillator R225 28 C228 29 at a frequency ofapproxima
352. reading the 6080A AN End loop Save calibration data Exit calibration procedure Figure 3 1 Basic Structure of Calibration Program The controller initiates the calibration procedure and initializes the measurement equipment Then it requests the signal generators RF frequency and waits for a response When a response is received the controller gets a reading from the measurement equipment and sends it to the signal generator The program remains in the loop until the signal generator returns the end code in response to the frequency query The loop is then exited and the data is saved in the calibration memory The controller queries the signal generator s RF frequency at each step to synchronize its actions with the signal generator and to determine when the procedure is complete When the signal generator receives a reading it updates its internal settings and does not respond to the next frequency query until it is ready for another reading The controller must wait for the signal generator s output to settle before it is allowed to take another reading The signal generator continues to receive readings and make adjustments until it gets two consecutive readings within the error tolerance for the procedure at which time the adjustment is considered valid The signal generator notifies the controller of this by returning the special end code of 9E 09 Hz in response to the next frequency query CLOSED CASE CALIBRATION The err
353. red by a 10 element 100 MHz low pass filter with input at L3 and output at C27 The filter is contained within a channel in an aluminum cover piece that improves high frequency attenuation This cover also shields the IF1 amplifiers and the IF2 low pass filter The 14 dBm IF1 signal at the filter output is amplified by Q5 configured for 21 dB gain Q5 drives level detector diode at 7 dBm U4 and associated components form a level control loop that holds RF level constant at CR1 by adjusting modulator PIN diode CR4 bias current This action also holds the signal level at 01 RF port to a constant value Accurate RF port level control is necessary to control mixer intermod spurs and noise floor The leveled IF1 signal at is next applied to 6 dB attenuator R25 27 and then to Q6 which is configured as a 20 dB amplifier Q6 drives the LO port of double balanced mixer U2 with about 20 dBm The 80 MHz signal from the A14 FM PCA is applied to the RF port of U2 This signal is coupled via a capacitor at J17 Q8 and associated components buffer and low pass filter this signal which is then applied to U2 at a level of 8 dBm U2 generates the IF2 signal at the IF port This signal is filtered by a nine element 20 MHz low pass filter with input at L9 and output at L23 Like the filter this filter is contained within a channel in an aluminum cover piece that improves high frequency attenuation The 14 dBm signal at the filter
354. regulator to 1 3V and turns off the 37V supply With the 37V supply off the 30V and the 5V reference supplies are turned off which forces the 5 1 15V and 15V to turn off The 24V fan supply is not turned off on this current limit Q4 acts as a memory element which requires resetting after it is turned on This can be done by turning off the front panel power switch The 15V supply is a low noise low ripple design that utilizes a high gain low noise amplifier U1 in a closed loop circuit with a conventional three terminal IC regulator U6 which provides current limit and temperature protection Both the 15V and 15V regulated supplies have reverse voltage protection diodes 12 and 14 The 5 1V supply has both reverse voltage and over voltage protection CR20 The 5 1V 15V and 15V supplies are tracking and are adjustable via the 5V reference supply adjustment R41 It is recommended that R41 be adjusted for 5 10V at A 6 2V supply is developed from the 37V supply through resistor R34 and zener diode CR15 The 6 2V supply is then applied to the center tap ofthe 6V AC filament supply This provides the necessary grid bias for the front panel displays All regulators have their common reference terminals brought out to an external ground point P2 on the module section to reduce power supply ripple Grounding all GND lines and the GND SENSE line at the chassis is required to prevent damage to the power
355. resolution 5 Adjust L601 for 40 MHz 10 kHz 6 Replace the jumpers to original positions 7 Set the frequency counter for 1 Hz resolution Verify the frequency 1540 1 count on the frequency counter 8 Measure voltage at TP19 It should be between 4 5 and 7 5V DC 80 MHz Filter Tuning L612 and L613 6C 22 TEST EQUIPMENT Spectrum analyzer REMARKS The 80 MHz Filter Tuning is normally required only when components in the doubler section have been replaced Q609 Q610 etc or when the adjustment has shifted PROCEDURE The 80 MHz output from the coarse loop is adjusted for maximum l 2 Program the UUT to SPCL 909 Remove the cable and connect the spectrum analyzer to A2 J5 Set the spectrum analyzer to 80 MHz 1 MHz span and 10 dBM reference level Adjust L612 for maximum level Adjust L613 for maximum level Repeat steps 3 and 4 until the level no longer increases Reinstall the cable 6C 29 TROUBLESHOOTING AND REPAIR FREQUENCY SYNTHESIS 6 30 80 Level Adjustment 8617 6 23 TEST EQUIPMENT Spectrum analyzer REMARKS The 80 MHz Level Adjustment is normally required only when 0606 0609 0610 U601 and associated components have been replaced or when the adjustment has been changed or has shifted This adjustment should be done after L612 and L613 have been adjusted PROCEDURE The 80 MHz Level from A2 J5 is adjusted to 4 dBm 1 Program UUT to SPCL 909 2 Remove the
356. ring the tests the RPP relay is opened to protect instruments connected to the RF output from possible damage Special Function 904 runs the self tests in a troubleshooting mode It stops after each test that fails leaving the hardware in the test configuration and the error code in the display The RF output is enabled so measurement equipment can be connected Press any key to continue the test The self test results see Table 6 2 can be displayed by entering Special Function 03 Status code 00 indicates that there were no failures Status code 301 indicates that the tests were aborted before completion and that the reported results may be incomplete Table 6 2 General Self Test Results Digital CODE DESCRIPTION 00 No self test Failures 301 Self tests Aborted Tests 6 24 The digital tests see Table 6 3 perform basic checks of the circuitry on the 13 Controller PCA The calibration compensation memory test verifies the CRC checksums of each of the calibration compensation data segments in the battery backed RAM U8 and in the EEPROM 09 If any of the tests fail status code 302 is reported See Calibration Compensation Memory Status in Section 6B for further details TROUBLESHOOTING AND REPAIR The system RAM 06 and 07 is tested by writing data to each memory location and verifying that the same data can be read back The RAM test is only done at power up The two program EPROMs U2 and U3 are teste
357. riple modulus prescaler divide by 16 17 118 056 057 and 058 and the N Divider Custom Gate Array U62 The triple modulus prescaler see Figure 6C 3 consists of a divide by 8 9 058 divide by 2 U57A synchronizing flip flop 0578 and quad NOR gates U56 If all the inputs El E2 E4 and E5 to 8 9 divider low the prescaler divides by 9 and the total division to the output U58 pin 7 TP33 is 18 Ifinputs 1 and are low the modulus ofthe 8 9 divider is controlled by the output ofthe divide by 2 U57 A Consequently the prescaler divides by 8 halfthe time and by 9 the other half resulting in a divide by 17 U57B synchronizes the changing of the modulus with the clocking of the subsequent stages The N divider gate array is clocked by the composite prescaler output U18A via the ECL to TTL converter contained in U58 The N divider gate array Figure 6C 4 contains two 5 bit binary counters A and N a BCD two decade rate multiplier and latches to interface to the controller The operation of the N and A counters is described in the following paragraphs At the beginning ofa count cycle a number is loaded into the and N counters The A counter is not at its terminal count so the output is high and the mode line MODE L is low This causes the prescaler to divide by 17 or 18 TRMODL low The mode line stays low for 31 A counts where A is the programmed number The mode line goes high and the prescaler divides by 1
358. rom the Premodulator PCA through W1 The modulator is a voltage controlled variable attenuator that provides AM and output level control Modulator control voltage is determined by the leveling loop circuitry The leveling loop is described later in this section Q5 U8 01 and associated components follow the modulator in the signal path and form a three stage 17 dB gain 15 to 1056 MHz amplifier This gain stage is followed by a 4 band switched filter to remove harmonics in the 15 to 27 MHz 27 to 32 MHz 32 to 47 MHz and 47 to 64 MHz frequency bands For frequencies below 64 MHz is on to direct these signals to the filter bank The appropriate filter is selected by CR6 CR13 and the result is returned to the signal path by 16 Signals above 64 MHz proceed to this point via a high frequency switched filter CR14 CR15 C38 C39 and circuit traces This is a LPF for frequencies below 625 MHz to further reduce harmonics The 64 to 1056 MHz signal 15 recombined with the 15 to 64 MHz signal at C180 This signal then drives a 3 dB power splitter that consists of resistors R63 R30 R31 and R32 and the associated transmission lines One power splitter output drives the leveling loop detector diode CR20 The other output goes to a 5 5 dB pad followed by a 7 dB amplifier Q7 and associated components The HET band switch follows the buffer amp and consists of PIN diodes CR18 CR21 24 and biasing components In the 15 to 1056 MHz position
359. rors at low modulation frequencies check the M circuits associated with U38 For errors in Special Functions LORATE and M check the circuits associated with U40 and U38 For errors in check circuits associated with FM Steer and U5 and circuits with the loop amp 025 and relay K4 and the LODCFM detector 027 Also check the FM Steer circuits on Modulation Control PCA The process is implemented by the controller Input Signals and Control Input Signals Checks 6E 15 Check the input signals and control input signals as follows 1 If the modulation signal is not present at J FM check the Modulation Control PCA A11 for the FM DAC and amplifiers and switch inverter Ifthe 20 MHz is not present from the Output 8 check the switched 5 Vsw on 74 and the 5V DC on J7 to the Output PCA If the control signals are not correct on J1 according to the Modulation Control Table Table 6E 1 check the latches on the Modulation Control PCA A11 TROUBLESHOOTING AND REPAIR FREQUENCY AND PHASE MODULATION FM ADJUSTMENTS 6E 16 This alignment includes the following PCAs All 6080A AN 4048 MOD CONTROL The FM modulation section e 14 6080A AN 4045 FM Oscillator The following equipment is recommended to make FM adjustments DMM Fluke 8840A Modulation meter HP 8901A LFSSG Fluke 6011A Spectrum analyzer HP 8586 Oscilloscope Tektronix Adjustments on the Modulation Control PCA A11
360. rs U45 and U46 The modulation signal is also amplified by U41 which drives a analog multiplier U42 to generate a second harmonic The second harmonic is added to the fundamental modulation signal for predistorting the signal to the modulation port of the 80 MHz VCO This predistortion cancels the distortion ofthe VCO The analog switches in U43 along with the associated resistors control and adjust the correct amount of predistortion for each range The output of the range network and switches and the output ofthe predistortion network are added in the summing resistors R126 and R127 The relay shorts out the large resistor R127 forthe low deviation ranges high Q mode The 49 9 ohm resistor R126 is for low noise performance The ranges are labeled for FM modulation however there are corresponding phase modulation ranges i e 4 MHz is 400 40 radians etc The range and predistortion paths are interactive and require interactive adjustment for each range range match R139 R140 or R141 distortion match R115 R117 or R119 respectively The high rate modulation signal and some ofthe range control logic signals are sent to the Sum Loop PCA to maintain correct operation there Since this causes an interaction between the Sum Loop and the FM PCA alead lag compensation is made with R120 and C99 controlled by analog switch Q15 and translator U45 The lead lag compensation is controlled by the range bit FMRN2H The low rate modulatio
361. s Acquisition Oscillator Level Adjustment R132 6C 38 TEST EQUIPMENT REMARKS The acquisition oscillator level adjustment is normally required only when U105 or any associated components are replaced or when the adjustment has been changed or has shifted PROCEDURE Acquisition oscillator level at TP1 is adjusted for 2 82V RMS with the phase locked loop disabled 1 Connect 5 to 15 with a clip lead Connect TP8 to TP15 with a clip lead 2 Connect the DVM to measure the AC voltage between and 15 ground 3 Adjust R132 for an indication of 2 83V RMS 05V SUM LOOP VCO A9 CIRCUIT DESCRIPTION 6 39 44 The A9 Sum Loop is controlled by the A12 Sum Loop and produces the fundamental band signal that is further processed in the Output Section to become the signal generator output This assembly includes four varactor tuned oscillator circuits that cover the frequency range 480 MHz to 1056 MHz programmed by binary control signals SUMVCOOH and SUMVCOIH as follows BAND FREQUENCY RANGE SUMVCOOH SUMVCO1H 1 480 624 999999 0 2 625 759 999999 0 3 760 894 999999 1 4 895 1056 1 2 The four oscillator circuits are of similar design but with different element values and printed transmission line lengths to cover the four bands In the following discussion reference designators for the band 1 oscillator will be specified Corresponding elements for the other
362. s ACCURACY costes eb 5 10 Hz measured vs indicated deviation 1 kHz rate DISTORTION lt 5 THD for rates of 0 1 1 and 50 kHz does not include effects of residual FM lt 2 THD for deviation lt 20 kHz and 1 kHz rate INCIDENTAL 196 AM 1 kHz rate for peak deviation 100 kHz PULSE MODULATION RF Frequencies from 10 to 1024 MHz ON OFF 35 dB minimum RISE amp FALL 15 PULSE Minimum least 5 us RATE e Ete Minimum at least 50 Hz to 50 kHz EXTERNAL PULSE MODULATION The pulse input is TTL compatible and 50 ohm terminated with an internal active pull up It can be modeled as 1 2V in series with 50 ohms at the pulse modulation input connector The signal generator senses input terminal voltage and turns the RF off when the terminal voltage drops below 1 0 1 V Max allowable applied voltage 10V NON VOLATILE MEMORY 50 instrument states are retained for typically 2 years even with the power mains disconnected REVERSE POWER PROTECTION PROTECTION LEVEL Up to 50 watts from a 50 ohm source Up to 50V DC Signal generator output is AC coupled Protection is provided when the signal generator is off ttt
363. s probable that U1 is faulty 3 Using an oscilloscope verify that the TTL level PULSE described in step 2 above is present at TPS 4 Using an oscilloscope to observe verify that the same pulse shape described in step 2 is zero centered with an amplitude of 2V 10 p p If either the amplitude or wave shape is incorrect check 75 and the associated resistors R22 R23 R24 R25 6F 5 6F 6 Section 7 List of Replaceable Parts TABLE OF CONTENTS ASSEMBLY NAME TABLE PAGE FIGURE PAGE NO NO NO NO 6080A AN Final PELE 7 1 7 4 7 1 7 7 AT Display PCA had ean Be 7 2 7 19 7 2 7 20 A2 Coarse Loop 7 3 7 21 7 3 7 25 Sub Synthesizer 7 4 7 26 7 4 7 27 A4 Sub Synthesizer 7 5 7 28 7 5 7 31 5 Coarse Loop 7 6 7 32 7 6 7 33 Mod Oscillator TE 7 34 7 7 7 35 A8 Output 7 8 7 36 7 8 7 39 A9 Sum Loop VCO 7 9 7 40 7 9 7 41 A10 Premodulator 7 10 7 42 7 10 7 45 All Modulation Control 27 1 7 46 7 11 7 49 A12 Sum Loop sou ed sei ee 22 12 7 50 7 12 7 53 A13 Controller PCA 7 13 7 54 7
364. s signals are indicated accurately For best accuracy to use the phase noise measurement system to locate spurious signal frequencies that appear greater than 106 dBc then verify the amplitude using the spectrum analyzer in a coherent narrow scan Typically the spectrum analyzer is set 20 dB off scale causing the 50 dB reference line to be 70 dBc With sufficiently narrow bandwidth a 110 dBc noise floor can be obtained PROCEDURE 1 Connect the UUT RF OUTPUT to the phase noise measurement system Connect the HFSSG to the LO INPUT 2 Program the UUT to 13 dBm and 640 MHz Measure phase noise at 20 kHz offset Note the amplitude and offset frequency of spurious signals larger than 106 dBc for later verification 3 Repeat step 2 at the following frequencies 1024 950 850 700 550 400 320 250 160 100 80 60 40 30 20 14 MHz 4 Connect the UUT to the RF spectrum analyzer and verify the amplitude of the recorded spurious signal by programming the spectrum analyzer step size to the measured offset frequency step 2 and stepping the analyzer plus and minus about the carrier PERFORMANCE TESTS MODULATION TESTS 4 14 The following tests use a modulation analyzer to verify modulation accuracy and residual and incidental modulation ofthe UUT The modulation distortion is verified by measuring the demodulated output of the modulation analyzer with a distortion analyzer The internal modulation oscillator frequency is mea
365. scriminately PROCEDURE With the UUT programmed to 16 dBm and 14 9 MHz the worst in band spur is adjusted to be well within specification A lower level of this spur degrades the broadband noise in the het band The het level is then appropriately readjusted 1 Remove bottom cover and appropriate access screws on bottom module plate for R10 and R72 2 Program UUT to SPCL 01 15 MHz and 16 dBm Connect the power meter to the output of the UUT Edit the level to 16 dBm Set the power meter to dB ref 3 Edit the frequency to 14 9 MHz and adjust R10 for 0 dB REL 4 Connectthe spectrum analyzer to the UUT and observe the spur at 5 5 MHz This spur should be observed with high spectrum analyzer attenuation typically 30 dB to avoid internal analyzer spurs The resolution bandwidth and span should be narrow typically a span of 1 kHz and resolution bandwidth of 10 Hz to allow the spur to be seen clearly 5 Adjust the spur to a level of 89 dBm 2 dB with R72 This has changed the adjustment in step 3 above so steps 3 through 5 must be sequenced again until level 15 0dB REL 1 dB 6 Reinstall the access screws TROUBLESHOOTING AND REPAIR RF LEVEL AM Output PCA Het Level Adjustment R10 6D 19 TEST EQUIPMENT e Power meter e Power sensor High Level REMARKS The UUT must be operated at room temperature for at least one hour with the module plate covers in place before continuing with this adjustment procedure Th
366. se lock port ofthe VCO with a clip lead Next measure the DC voltage at J6 with the UUT programmed to SPCL 943 All DACS to full scale The reading should be 24 00V Next program the UUT to SPCL 942 DACs to half scale The reading should be 12 00V This tests the VCO steering voltage circuit With J5 still grounded examine the output at connector J8 with aspectrum analyzer as frequency is stepped in 8 MHz increments from 512 MHz to 1056 MHz The frequency should always be within about 2 MHz of expected coarse loop frequency and the level should be approximately 5 dBm Note that the expected coarse loop frequency can be displayed by entering SPCL 946 If the signal is good the problem is likely in another PCA If the signal is faulty only over a frequency band corresponding to one of the VCO bands the associated VCO circuit is likely at fault If the VCO appears to be faulty DC voltages can be measured at various circuit nodes with the UUT programmed to frequencies corresponding to the three VCO bands UUT frequencies of 600 700 and 1000 MHz will enable each ofthe three bands Refer to Table 6C 7 for expected approximate voltage measurements These measurements should help isolate the faulty circuit SUM LOOP BLOCK DIAGRAM 6C 28 Refer to the Sum Loop Block Diagram see Figure 6C 8 for help in identifying the major functional sections and following the signal paths of the sum loop Table 6C 7 A5 Coarse Loop VCO PCA Expected DC Vo
367. se of the volume of activity at any given time However one can systematically verify the independent circuit functions and quickly spot some of the most obvious problems Read the following paragraphs and verify the related circuitry Clock 6B 14 Connect an oscilloscope probe to the clock oscillator output U18 pin 4 There should be a symmetrical 8 MHz square wave with adequate logic levels If the signal appears abnormal determine ifthe problem is with the oscillator circuit or the ICs connected to the clock output by checking the input signal at pin 3 of U18 It should be an inverted version of the same 8 MHz square wave It may be slightly distorted due to its loading Power On Reset 6B 15 Connect an oscilloscope probe to the RESET input pin 18 of U1 The signal should generate a low to high transition on power up and remain high during normal operation Turning the power off and on generates an active low reset pulse approximately 200 ms wide If the reset pulse to 01 appears abnormal compare it to the reset output pin 5 of the power supply monitor IC U13 Suspect problems with U13 and all ICs connected to the RESETL and RESETH signals Also check the HALT input pin 17 of U1 it should look like the RESET pin 18 input Unused Microprocessor Inputs 6B 16 Input signals to U1 BR pin 13 and BGACK pin 12 should both be high Ifeither of these signals is not high correct the fault before continuing Bus Error 6B 17
368. solution of 0 1 Hz It is the modulation source for the internal AM FM M and pulse functions The oscillator is based on an algorithmic wave generation method which provides a very accurate and stable signal source of high purity and low harmonic distortion level The main function ofthis systemis implemented in acustom integrated circuit The waveform data is stored in two EPROMs In the pulse generation mode frequency can be set from 10 Hz to 200 kHz which results in a pulse period of0 1 s through 500 us The pulse width can be set from 100 ns to 100 ms with resolution of 100 ns Power Supply Description 2 14 The power supply is a linear design providing 15V 15V 45V 37V 30V 24V 23 4V DC and 6V AC to the signal generator All the power supplies are series pass regulated except the 6V AC display filament supply A fuse filter line voltage selector allows the signal generator to operate from 115 or 230V AC DIGITAL CONTROLLER SOFTWARE DESCRIPTION 2 15 The signal generator software is executed on an 65HCOOO microprocessor located in the A13 Controller PCA The instrument program is stored in 256K bytes of ROM The program stack and RAM variables are stored in 16K bytes of static RAM A battery backed CMOS RAM contains 4K bytes of non volatile memory for front panel setups and 4K bytes of non volatile calibration compensation data An 8K byte EEPROM contains a redundant copy of the calibration compensation data The softwar
369. summing node at is connected to the sum loop VCO phase lock port 76 Six switchable resistors R138 143 also connect this node to ground These switched resistors are used to adjust loop amplifier gain to compensate for sum loop VCO Kv variations Note that Kv is the slope ofthe frequency vs tuning voltage function The switched resistors are programmed by U110 a PROM that contains a look up table SUMCOMP bits 0 7 a binary number proportional to 1 Kv is the input to 0110 The six bit output of U110 functionally related to the SUMCOMP number drives the programmed resistors in a way to compensate for Kv variation with sum loop VCO RF frequency ACQUISITION CIRCUITS The acquisition circuit includes several parts including a two frequency acquisition oscillator an unlock detecting comparator a loop disabling circuit and a dual monostable multivibrator These parts interact as described below When the loop is properly phase locked the phase detector voltage at TP5 stays close to OV because the loop forces equal frequency and nearly equal phase for the phase detector inputs If the loop was opened for instance by shorting the VCO phase lock port at TP4 the phase detector would generate a beat frequency triangle wave signal of about 300 mV amplitude Thus the presence of a voltage above a threshold level indicates loop unlock High speed comparator U115 trips and activates a two stage acquisition sequence when the phase detector
370. sure that the fan is aimed at the power dissipators Q1 Q2 U6 U4 U9 Failure to provide adequate air flow could damage the power supply Troubleshooting Procedure 6A 4 Troubleshoot the power supply as described in the following procedure 1 Set the power supply to the standby mode front panel yellow LED on 2 Verify that the two standby supplies are operating and are within the specified voltage range and verify that the rest of the supplies are turned off The specified ranges are as follows TP2 23 4V supply 24V x 5 14 5Vsupply 5V 8590 TP18 24V supply OV 40 1 TP6 5 1V supply 40 1 11 15V supply OV 0 1V 16 15V supply 0 1V TP20 37V supply x 0 1V TP21 supply OV x 0 1V 15 5V reference 0 1V ho TROUBLESHOOTING AND REPAIR POWER SUPPLY 3 Ifeither of the 23 4V or 5V supplies are not at the specified voltage check the unregulated supply for both TP13 and respectively If some of the supplies that are supposed to be off are partially or fully turned on check the 37V supply TP20 voltage Ifthe 37V supply is partially or fully on check the standby switching circuit and the comparator operation U3 Q5 R52 4 Next switch the power supply on by connecting the STANDBY line pin to GND J6 pin 7 8 5 Verify all supplies are operating and are within the following specified levels 18
371. sured using a frequency counter on the demodulated output of the modulation analyzer The internal modulation oscillator amplitude is measured using an RMS voltmeter Table 4 4 lists the requirements for the modulation tests Table 4 4 Modulation Tests Requirements E t SPECIFICATION MOD FREQUENCY lt 0 1 Hz AM ACCURACY lt 7 AM Amplitude less than 0 dBm AM DISTORTION 596 at 5096 depth at 1 1 and 10 kHz rates RESIDUAL AM lt 0 01 RMS 80 dBc in 0 04 to 15 kHz bandwidth INCIDENTAL FM lt 200 Hz at 1 kHz rate 50 AM FM ACCURACY lt 5 10 Hz for 1 kHz FM DISTORTION lt 2 THD for deviation lt 20 kHz 1 kHz rate lt 5 for rates of 1 5 and 50 kHz RESIDUAL FM RMS 0 3 to 3 kHz band lt 4 Hz RMS in 0 05 to 15 kHz band 8 Hz INCIDENTAL AM 196 AM at 1 kHz rate and for deviation 100 kHz REMARKS If the UUT fails these performance tests calibration and or repair of the associated circuitry is indicated Where residual noise affects the accuracy ofthe modulation analyzer measurements apply correction methods provided by the manufacturer of the modulation analyzer The UUT settings in this procedure are chosen to provide strong confidence in the modulation performance of the UUT throughout its range If desired however performance may also be checked at other instrument settings TEST EQUIPMENT Modulation analyzer Distortion analyzer Frequency counter Low
372. t PCA 016 Bias Adjustment 9 6D 18 6D 22 Output PCA 09 Bias Adjustment 6D 19 6D 23 Output PCA Gain Flatness Adjustment 201 6D 19 6D 24 FM Gain Adjustment R82 on Mod Control PCA 6D 20 6D 25 FM Steer Gain R101 on Mod Control 6D 20 6D 26 FM INV Balance R102 on Mod Control 6D 20 6 27 ATTENUATOR REVERSE POWER PROTECTION RPP 6D 20 60 28 ATTENUATOR RPP TROUBLESHOOTING 6D 21 6E FREQUENCY AND PHASE 6E 1 ENS 6 1 6E 2 BLOCK 6 2 6E 3 CIRCUIT 6E 2 6E 4 Oscillator 222 2 22 2 6E 2 6E 5 Divider Section ai ss ipere ee Bs ade e ete RE SR AME He 6E 4 6E 6 Phase Detectors Loop Circuits and Logic 6E 4 6E 7 Modulation Section 6E 7 6E 8 MODULATION CONTROL CIRCUIT DESCRIPTION 6E 10 6E 9 FM Input Voltage Processing oiii iis ilius id 6E 10 6E 10 FM Steer Voltage 6E 10 6E 11 FM Control Signals 6E 10 6E 12 FM TROUBLE SHOO
373. t ensure that each mod meter reading is settled before sending it to the 6080A AN The program listing in Appendix G uses a simple but effective method to obtain valid mod meter readings The programming commands used in a remote FM calibration procedure are listed in the Table 3 4 See Table 5B 3 in Section 5B of the Operator Manual for a complete syntax description of each command Table 3 4 Remote Programming Commands for FM Calibration Procedure COMMANDS DESCRIPTION CAL FM Initiate the remote FM calibration procedure RDAM Send the mod meter reading to the 6080A AN CC FREQ Request the RF frequency CC TARGET Request the target value RFOUT Program the RF output on off CC SAVE Save the measured data CC EXIT Abort the cal procedure immediately ERROR Request the rejected entry status STATUS STATUS Load Request the overrange uncal status RF LEVEL CALIBRATION 3 11 The RF level calibration procedures allow a single point calibration of the RF output level to be performed An RF power meter is connected to the signal generator s RF output and the level calibration factor is adjusted based on the meter reading The procedure specific parameters are as follows Adjustment Range 1 00 dB Adjustment Resolution 0 01 dB Target Value 10 0 dBm Frequency 300 000000 MHz RF Level 10 0 dBm External Equipment RF Power Meter HP 436A or equivalent When performing the front panel procedure use the edit kno
374. ta segments were generated any other way the corresponding status code is displayed Ifthere are more than four codes the list can be scrolled by pressing the key Referto Appendix F for a complete list of origin codes FRONT PANEL CIRCUIT DESCRIPTION 6B 26 The front panel section is mounted in a sheet metal housing and consists of the A1 Display PCA a switch circuit board elastomeric switches and the edit knob The front panel section also includes the display lens the AM INPUT connector the INPUT connector and the PULSE INPUT connector All front panel control keys except the POWER ON OFF button consist of an elastomeric membrane sandwiched between the switch circuit board and the front panel sheet metal housing The switch circuit board consists of an 8 by 8 matrix of open switch contact pads When a key is pressed a conductive pad on the back of the elastomeric membrane connects a set of contact pads The software senses what row and column ofthe matrix are connected when a key is pressed The two opto interrupter ICs for the edit knob are the only active components mounted on the switch PCA 6B 9 TROUBLESHOOTING AND REPAIR DIGITAL CONTROLLER 6B 10 Display PCA 6B 27 The A1 Display PCA provides a readout ofthe programmed modulation frequency amplitude parameters and status information This displayed information and the bright digit are controlled by the A13 Controller PCA under the direction of the instrume
375. tely 100 Hz Since the phase detector is not a phase frequency detector the beat frequency at the output of the phase detector must be small in order for the loop to lock When the loop is unlocked the Wien bridge oscillator is oscillating and the VCO frequency is slowly swept about its steered frequency This causes the beat frequency to be slowly swept close to 0 When the loop locks there is enough gain around the loop so the oscillation condition for the Wien bridge is no longer met and it stops oscillating A one shot U204 is tripped when the Wien bridge is oscillating which indicates an out of lock condition This signal CORUNLKL is sent to the controller The output of the acquisition oscillator is fed into a programmable lead lag network R229 237 C231 235 Q201 204 Since the tuning slope of the VCO in 2 is not constant this network is programmed to reduce the magnitude of the change The output of this network is connected to the phaselock port of the Coarse Loop VCO J4 This network forms part of the compensation of the discriminator loop A comparator U208 converts the TTL programming input to 0 10V to drive the FETs Another comparator U210 monitors the phaselock voltage It generates signals when the voltage exceeds 5V CORVOLH or 5V CORVOLL This is used for the Coarse Loop VCO compensation FREQUENCY SYNTHESIS TROUBLESHOOTING AND REPAIR 89 269821 S 919 SOEN ALVY 18 89
376. the 40 MHz reference for the Sub Synthesizer via J16 The other output is divided by 2 U506A and buffered by U513 The 20 MHz square wave output is band pass filtered R36 L510 C545 before being sent to the modulation oscillator J8 A second divide by 2 U506B divides the 20 MHz to 10 MHz This ECL signal is converted to TTL Q504 05 and buffered U507C Two inverters in parallel U507A B drive a low pass filter C518 19 C550 L501 whose output is a 10 MHz sine wave This is the reference out for the instrument J7 When in internal reference the 10 MHz signal from U507C is routed through a multiplexer 0504 to the R input ofthe phase frequency detector U503B U511D When in external reference 10 MHz divider 0505 is disabled and the signal from U507C is routed through a multiplexer U504C logic U511 A B to the R input ofthe phase frequency detector When Special Function 761 is enabled the 10 MHz signal is divided down to either 1 2 or 5 MHz U505 depending on how the switches are set S502 The output of the divider is also routed to the phase frequency detector The phase frequency detector U503 U511D compares the phase frequency of the divided down 40 MHz VCXO V input with either the 10 MHz TCXO or an external reference The phase detector normally operates at 10 MHz except when an external reference of 1 2 or5 MHz is used Inthese cases it operates atthe reference frequency The output of this phase detector o
377. the A13 Controller PCA The compensation data is transferred by one of three special functions depending on which of the three assemblies has been replaced Perform the following steps to update the compensation memory with the new module exchange data 1 2 Verify that power to the 6080A AN signal generator is turned off Access the A13 Controller PCA as described by the access procedure in Section 5 Leave the controller in place with all cables attached since it must be operational Install the module exchange EPROM into the socket on the controller labeled 010 Power up the 6080A AN Remove the sticker labeled CALICOMP from the rear panel and set the CALICOMP switch to the 1 position Verify that the CAL and COMP annunciators on the front panel are flashing Enter special function 961 to transfer the Attenuator RPP data special function 962 to transfer the Output data or special function 963 to transfer the Sub Synthesizer VCO data 8 Respond to the prompt Att Sto Out Sto or Sub Sto by pressing the 9 key The message Sto is displayed for 12 seconds for the attenuator and 5 seconds for the output and Sub Synthesizer while the data is transferred CAUTION Do not turn the POWER switch off or change the CAL COMP switch until the store operation is complete Doing so could damage the contents of the compensation memory Set the rear panel CALICOMP switch to the 0 position 10 Verify
378. the assembly shown in Table 6 and identify the assembly as a module exchange part For general parts procurement refer to Section 8 for the part number and other ordering information Paragraphs 6 3 through 6 20 describe the available exchange modules and any necessary adjustments Refer to Section 5 Access Procedures for instructions regarding removal and replacement ofthe modules If any problems occur refer to the appropriate paragraph in this section for instruction on troubleshooting and alignment Module replacement should be followed by related performance tests Section 4 to ensure that the problem s have been fixed Table 6 1 Module Exchange Assemblies ASSEMBLY NO MEC P N DESCRIPTION A1 860853 Display PCA A2 860861 Coarse Loop PCA A3 860866 Sub Synthesizer PCA A4 860874 Sub Synthesizer PCA A5 860879 Coarse Loop VCO PCA A6 860890 Mod Oscillator PCA 860809 Relay Driver PCA A8 860817 Output PCA A9 860820 Sum Loop VCO PCA A10 860841 Premodulator PCA A11 860846 Mod Control PCA A12 860825 Sum Loop PCA A13 860833 Controller PCA A14 861088 FM Board PCA A15 860895 Power Supply PCA A19 860858 Switch PCA A20 860812 Attenuator RPP Assembly A7 A21 A30 A22 860887 Delay Line Assembly A25 A26 Delay Cable Trim Cable TROUBLESHOOTING AND REPAIR A1 Display PCA 6 3 Adjustments None A2 Coarse Loop PCA 6 4 Adjustments None Perform Reference Oscillator Calibration See paragr
379. the following UUT frequencies 14 20 40 80 160 320 550 640 700 850 950 and 1024 MHz SENSOR IN MEASURING RECEIVER HP 8902 UUT 6080A AN SENSOR HP 11722A Figure 4 2 Alternate Level Accuracy Test Equipment Setup PERFORMANCE TESTS FLATNESS TEST 4 10 A power meter and sensor are used to verify the high level flatness of the instrument REQUIREMENT Amplifier flatness is lt 1 dB at 10 dBm over the frequency range of 0 5 to 1024 MHz TEST EQUIPMENT e Power meter Power sensor high level REMARKS If the UUT fails this test calibration see Section 3 or repair see Section 6 is necessary If no power on status codes are present likely problem areas needing repair include the A8 Output PCA the A21 Attenuator or the A7 Relay Driver PCA PROCEDURE 1 Calibrate and zero the power meter 2 Connect the power sensor to the instrument RF Output 3 Program the instrument to SPCL 909 and then to 0 5 MHz and 10 dBm 4 The power meter should read 10 1 dBm 5 Repeat step 4 for the following frequencies a 0 5 to 2 0 MHz in 0 1 MHz steps b 2 0 to 20 0 MHz in 1 0 MHz steps c 20 0 to 200 0 MHz in 10 0 MHz steps d 200 0 to 1024 0 MHz in 20 0 MHz steps 4 13 PERFORMANCE TESTS 4 14 OUTPUT LEAKAGE TEST 4 11 The output signal leakage is verified using a l inch diameter two turn loop The induced signal is measured with an RF Spectrum Analyzer and com
380. ther or shorted to the power supply Also look for ICs that may be driving the data bus If the control and address signals appear normal set the DIP switches to the off position and install U11 Address Decoder 6B 20 6B 6 Several levels of address decoding are used to select the memory and I O devices Figure 6B 2 shows the levels of decoding Decoder PAL U11 generates the major memory segment selects Verify that all of its address and control inputs are working properly The signal CMWRL is the write protection signal for the calibration compensation memory Signal CMWRL is tied directly to the rear panel switch Signals NVWR COMPWR are software controlled write protection signals for the non volatile memory and the calibration compensation memory respectively TROUBLESHOOTING AND REPAIR DIGITAL CONTROLLER chip select for the I O circuitry is also generated by U11 Two additional levels of decoding generate the individual device selects If U11 is operating correctly but the decoded chip select is not properly generated three internal diagnostic tests may be of use l O Diagnostic Tests 6B 21 If the data write selects to the display latches IEEE 488 talker listener IC 028 the module I O control circuitry or the control outputs are not generated properly momentarily ground on the controller This initiates a diagnostic routine that continuously writes the data byte 10101010 binary to each
381. tion range of 0 to 138 dB in 6 dB steps This is accomplished by seven independently cascaded 50 ohm attenuation sections K1 through K7 There are one 6 dB one 12 dB and five 24 dB sections Each section consists of a DPDT relay and a pi attenuator pad One relay position when DC power is applied to the relay provides a low loss through path for the RF signal The other position no DC power applied to the relay inserts the attenuator into the RF signal path Control of the sections is from the Controller PCA through the Relay Driver PCA Attenuation correction data for each attenuator is stored in the compensation memory on the Controller PCA Necessary correction is applied via the leveling loop control voltage The RPP section of the Attenuator RPP PCA protects the attenuator and the output amplifier from excess applied DC voltage or RF power C6 and C7 provide a DC voltage block K8 when in the protect position no DC power applied to the relay protects against long duration excess RF power The detector diode senses excess RF power and trips the latching comparator circuit U1 A on the Relay Driver PCA This change of state of U1 A passes through U1 D Q8 and Q9 to remove the DC power from K8 This puts K8 into the protect state Diodes CR2 through CR9 on the Attenuator RPP PCA form an RF limiter circuit This provides protection against short duration excess power events or until K8 can change state This may take up to 4 ms
382. to SPCL 909 800 MHz 50 kHz dev 70 Hz mod rate INT ACFM Set the 8901A to peak gt 20 kHz filter Adjust R102 for 50 kHz reading on the 8901 Set the UUT to SPCL 909 800 MHz 100 kHz dev 70 Hz mod rate INT Set 8901A to peak gt 20 kHz filter all other filters off Adjust R94 fora 100 kHz reading on the 8901A Set the UUT to 50 kHz dev 5 kHz mod freq INT Set the 8901A to 90 The 8901A should read 10096 Check the mod rates in Table 6E 5 to determine if the UUT is within specification Table 6E 5 FM Mod Rate Specifications MOD RATE Hz SPECIFICATION kHz 1000 100 2 2 500 100 2 2 200 100 2 2 100 100 2 2 50 100 1 5 1 5 6E 15 TROUBLESHOOTING AND REPAIR FREQUENCY AND PHASE MODULATION 6E 16 16 17 18 19 20 21 22 23 24 Set the UUT to SPCL 909 800 MHz 150 kHz dev 25 Hz mod rate INT Connect the oscilloscope to the 8901A MOD OUT Adjust the scope for almost full scale display with one cycle Adjust R88 for a smooth waveform Set the UUT to 800 MHz 5 kHz mod rate 200 kHz dev INT Set the 8901A to FM peak 300 Hz HP 15 kHz LP Adjust R141 for a 8901A reading of 200 kHz 1 kHz Adjust R119 for symmetrical plus and minus readings about 200 kHz 1 kHz Repeat until both specs are met Set the UUT to 200 MHz 5 kHz mod rate 200 kHz dev INT ACFM Set the 8901 to FM peak 300 Hz HP 15 kHz LP
383. to provide indication to the controller that the peak AC voltage is not IV Analog switch U5 selects the internal or external DC or AC coupled modulating signal or selects no modulation The selected modulation signal is buffered by U21 and is applied to pin 19 of U6 a multiplying 12 bit DAC U6 with amplifier U8 A acts asa digitally programmed variable attenuator and controls AM depth The AM signal at TP6 is summed by op amp U8 B with a DC reference current provided by CR7 The output at U8 B pin 8 is called the 1 AM signal This signal with additional scaling is the basis for level and AM depth AM depth adjustment is provided by potentiometer R10 and AM DAC offset by R8 The instrument RF output amplitude is temperature compensated in a frequency dependent manner The 1 signal is applied to the reference input pin 15 of an 8 bit multiplying DAC U11 and to one input of summing op amp U8 D The DAC output at U8 C pin 1 is the 1 AM signal scaled by a factor that is generated from stored constants This voltage is applied to resistor thermistor network that includes R15 R16 R18 and RT17 This signal is also applied to summing op amp U8 D The voltage at U8 D pin 14 is the temperature compensated 1 AM signal This signal is applied to the reference input of level DAC 012 This 14 bit multiplying DAC with op amp U4 generates the leveling loop control voltage at TP7 The leveling loop control voltage is the temperature com
384. tore command has been given the internal calibration factor is calculated from the displayed adjustment value and is stored in the calibration memory Subsequent FM programming commands use the new calibration factor NOTE Set the rear panel CAL COMP switch to the 1 on position before initiating an FM calibration procedure 3 7 CLOSED CASE CALIBRATION 3 8 Front Panel FM Calibration Procedure 3 9 The front panel FM calibration procedure is initiated by the following key sequence 9 2 The display is reconfigured for the procedure Several of the front panel controls are disabled or operate differently than they normally do Table 3 3 shows all ofthe active controls and describes their function while performing the front panel FM calibration procedure Table 3 3 Front Panel Controls for FM Calibration Procedure CONTROLS FUNCTION AND DESCRIPTION lt Bright Digit Editing KNOB Turn the edit knob to adjust the FM calibration factor Use the left right STATUS STO CLRILCL arrow keys to move the bright digit within the adjustment field The bright digit is always located in the adjustment field RF on off Toggles the RF output on off Overrange uncal or Rejected Entry Status Normally displays the overrange uncal status Displays the rejected entry status code if there is a rejected entry Store Measured Data Press once the prompt Sto is displayed Press again to s
385. tore the data The message Sto is displayed to confirm the selection The updated calibration factor is stored in the calibration memory and the last valid instrument state is restored Press any other key to cancel the store operation and resume the procedure Abort the Cal Procedure Press once the prompt Clr is displayed Press again to abort the procedure The message Clr is displayed to confirm the selection All measured data is discarded and the previous instrument state is restored Press any other key to resume the procedure CLOSED CASE CALIBRATION Perform the following to execute the front panel FM calibration procedure 1 Set the rear panel CALICOMP switch to the 1 on position 2 Enter special function 992 to initiate the FM procedure 3 Connect the 6080A AN s RF output to the modulation meter 4 Select the peak mode enable the 50 Hz high pass filter and enable the 3 kHz low pass filter on the modulation meter 5 Use the edit knob to change the adjustment value until the modulation meter reads 100 kHz 6 Press the key twice to store the new data Remote FM Calibration 3 10 The following paragraphs describe the remote FM calibration procedure the remote commands used in the procedure and the elements required to build a functioning controller program Refer to the heading Remote Calibration earlier in Section 3 for general information relating to all remote calibrat
386. trolled by the A2 Coarse Loop PCA and produces a signal that is further processed in the A12 Sum Loop PCA This assembly includes three varactor tuned oscillator circuits that cover the frequency range 576 to 960 MHz programmed by binary control signals CSVCOOH and CSVCOIH as follows BAND FREQUENCY RANGE MHz 5 CSVCO1H 1 576 704 0 0 2 712 824 0 1 3 832 968 1 1 The three oscillator circuits are of similar design but have different element values and printed transmission line lengths to coverthe three bands In the following discussion reference designators for the band 1 oscillator are specified Corresponding elements for the other oscillators are obvious from the schematic Each oscillator uses acommon base transistor Q3 configured for negative resistance at the emitter The emitter is coupled to a resonator that consists of a printed transmission line in series with varactor diodes CR5 CR6 and low loss porcelain capacitors C5 C6 Two tuning voltage lines connect to the varactor cathodes and anodes via RF chokes L6 and L3 respectively The cathode lines connect to the VCO steering port J6 The anode lines connect to the VCO phase lock port J5 These ports are used by the A2 Coarse Loop to control the operating frequency The voltage across the varactors measured between J6 and J5 varies approximately linearly with frequency in each band from about 2V to 20V The 13 dBm nominal signal at the oscillator
387. ts the coarse loop frequency and the Sum Loop VCO frequency to generate a first IF signal referred to as the IF1 signal The second stage subtracts the FM PCA signal from the IF1 signal to generate a second IF signal referred to as the IF2 signal The third stage includes a mixer phase detector that compares the IF2 signal to the sub synthesizer signal and generates the audio frequency phase lock signal that is further processed in the audio section Frequency ranges for these signals are given in Table 6C 8 Note that when FM is on the programmed deviation will appear in the Sum Loop VCO signal the IF1 signal and the FM PCA signal Table 6C 8 Sum Loop Frequencies SIGNAL FREQUENCY RANGE MHz Sum Loop VCO 480 1056 Coarse Loop 576 960 IF1 88 96 FM PCA 80 IF2 8 16 Sub Synthesizer 8 16 TROUBLESHOOTING AND REPAIR FREQUENCY SYNTHESIS The Sum Loop VCO signal at J9 is applied to buffer amplifiers U7 and U8 PIN diode CR4 follows U8 and acts as an adjustable attenuator to control the level at the RF port of double balanced mixer U1 A low pass filter including C81 and C82 precedes 01 RF port and attenuates high order harmonics in the RF signal The LO port of U1 is driven by a two stage amplifier that includes Q1 and Q2 This amplifier accepts the 7 dBm signal from the Coarse Loop VCO at J11 and produces 20 dBm of drive power at the LO port of Ul UI generates the signal at the IF port This signal is filte
388. uivalent When performing the front panel procedure use the edit knob to adjust the AM depth until the measured AM depth matches the target value When performing the remote procedure the process is under the control of a program running on an IEEE 488 bus controller The front panel display is reconfigured during the procedures The target level is displayed in the modulation field the RF frequency is displayed in the frequency field the adjustment value is displayed in the amplitude field and the CAL annunciator is lit The display is consistent for the front panel and remote procedures All adjustments update a temporary copy ofthe AM calibration factor The copy in the calibration memory is updated only after the store command is given explicitly After the store command has been given the internal calibration factor is calculated from the displayed adjustment value and is stored in the calibration memory Subsequent AM programming commands use the new calibration factor NOTE Set the rear panel CAL COMP switch to the on position before initiating AM calibration procedure Front Panel AM Calibration Procedure 3 6 The front panel AM calibration procedure is initiated by the following key sequence ea o The display is reconfigured and several of the front panel controls are disabled or operate differently than they normally do Table 3 1 shows all ofthe active controls and describes their function while the
389. utput MOD OUT The two switches associated with U4 and 05 55 S6 U6B and U6D facilitate the connection ofthe pulse generator to both the modulation output MOD OUT and to the internal modulation source INT MOD eF 3 TROUBLESHOOTING AND REPAIR INTERNAL MODULATION OSCILLATOR 6F 4 MOD OSCILLATOR TROUBLESHOOTING AND ADJUSTMENTS 6F 6 Direct Since both the direct digital synthesizer DDS and the pulse generator sections are clocked by the same clock the first signal to verify is the input 20 MHz In the absence of this clock no function on the assembly will operate The amplitude of this wave should be at least 300 mV p p Digital Synthesizer Troubleshooting 6F 7 To troubleshoot the direct digital synthesizer proceed as follows SETTING UP 1 Put the UUT into the preset default state by selecting SPCL 909 This sets the DDS to generate a sine wave 2 Enable INT AM modulation 3 Set MOD LEV to a modulation output level of 4V pk 4 Enter MOD FREQ of kHz 5 Connect a 600 ohm load at the MOD OUTPUT connector TEST PROCEDURE 1 Check U1 output clock CLKO at TP10 This logic level signal should be at 3 33 MHz If there is no signal at this point or the frequency is wrong either Ul is faulty wrong data is written to it or the 20 MHz signal is inadequate With the absence of this signal the DDS sections will not operate 2 Using an oscilloscope verify that the most significant bit MSB of the phase accumul
390. ve Adjustment L56 10 kHz Notch Adjustment Note that these adjustments are not routine and are required only when associated components have been replaced or when the adjustment has been changed or has shifted Steering DAC Full Scale Adjustment 6C 6 TEST EQUIPMENT REMARKS Steering DAC Full Scale adjustment is normally required only when 05 U6 or associated components have been replaced or when the adjustment has shifted PROCEDURE The Steering DAC voltage is adjusted to 10 23V with the Coarse Loop Steering DAC set to full scale 1 Program the UUT to SPCL 909 2 Program the UUT to SPCL 943 This Special Function programs all DACS to full scale 3 Connect the DVM to measure voltage between TP6 and ground 4 Adjust R5 for 1023V 0 01V 5 Program the UUT to SPCL 00 This clears all Special Functions Lower Clamp Adjustment R99 6 7 TEST EQUIPMENT e Frequency counter REMARKS The Lower Clamp Adjustment R99 is normally required only when U35 U36 or associated components have been replaced when the Sub Synthesizer VCO A3 has been repaired or replaced or when the adjustment has shifted 6C 13 TROUBLESHOOTING AND REPAIR FREQUENCY SYNTHESIS 6C 14 PROCEDURE The Lower Clamp frequency is adjusted to 15 MHz with the reference to the phase detector disabled 1 Connect output J4 ofthe Sub Synthesizer VCO A3 to the frequency counter Set the frequency counter to measure with 1 kHz
391. visable to troubleshoot at alow frequency where an oscilloscope is useful Putthe instrumentin aknown state by selecting SPCLO1 the frequency to 88 MHz and set the amplitude to 13 dBm The voltage at TP8 on the modulation control PCA should be 1 3 5V DC Ifthis voltage is correct the problem is localized to the Output PCA following the detector diode CR20 or the Attenuator RPP assembly The appropriate signal levels following this point are R121 0 9V p p Q7 base 0 4V p p Q7 collector 0 85 CR23 cathode 0 82V At 88 MHz Q9 base 0 6V p p Q9 collector 1 5V p p Q16 collector 3 0V p p These voltages are approximate and are as measured with a 10 megohms 8 pF oscilloscope probe using a ground connection made at the probe tip with less than 1 inch of lead Table 6D 1 Band Filter and Frequency Programming Data 7 FGGGGi1 23 4 4 7 TT TH HHH 7612 6 D 6 4 8 5 4 0 6 5 NNO ENN FREQUENCY MHz 01 14 999999 15 21 999999 22 31 999999 32 46 999999 47 63 999999 64 127 999999 128 179 999999 180 255 999999 256 349 999999 350 511 999999 512 624 999999 625 729 999999 730 1056 000000 0000000 gt A A EC 20
392. y displays the overrange uncal status Displays the rejected entry status code if there is a rejected entry STO Store Measured Data Press once the prompt Sto is displayed Press again to store the data The message Sto is displayed to confirm the selection The updated calibration factor is stored in the calibration memory and the last valid instrument state is restored Press any other key to cancel the store operation and resume the procedure Abort the Cal Procedure Press once the prompt Clr is displayed Press again to abort the procedure The message Clr is displayed to confirm the selection All measured data is discarded and the previous instrument state is restored Press any other key to resume the procedure CLOSED CASE CALIBRATION 3 16 Perform the following to execute the front panel reference oscillator calibration procedure 1 Set the rear panel CALICOMP switch to the on position 2 Enter special function 994 to initiate the procedure 3 Connect the 6080A AN s RF output to the FLUKE 1953A s FREQA input 4 Select the FREQA input 1 second gate time and the continuous trigger mode 5 Usethe edit knob to change the adjustment value until the counter reads 100 MHz 6 Press the key twice to store the new data Remote Reference Oscillator Calibration Procedure 3 16 The following paragraphs describe the remote reference oscillator calibration procedure t
393. y explains the functions and components of the four major sections of the Generator Functional Description Describes the functional blocks of the signal generator and their relations to the main output parameters amplitude frequency and modulation Digital Controller Software Description Describes the software and how it affects the hardware GENERAL DESCRIPTION 2 2 The 6080A AN Synthesized Signal Generator has four major sections The front panel section includes the keyboard and display for local control The upper synthesizer module section includes the coarse and fine loop synthesized signals and the synthesized modulation oscillator The lower output module includes the sum loop FM oscillator and the level modulation and control circuits The rear panel section includes the power supply cooling fan and assorted external connectors 2 1 THEORY OF OPERATION 2 2 Front Panel Section 2 3 The front panel section of the signal generator provides the operator interface including the primary controls connectors and indicators All front panel keys and displays except the power switch that directly controls the power supply are monitored and handled by the A13 Controller PCA which is located in the output module section Upper Lower Module Sections 2 4 The two module sections are multi compartmented shielded enclosures that contain the circuits that generate the instrument stimulus functions freque
394. y of 640 MHz and no modulation Program the HFSSG to 641 5 MHz and 1 0 dBm Connect the HFSSG output to the modulation analyzer external LO input connector Program the modulation analyzer to measure average FM in the 50 Hz to 15 kHz bandwidth Verify that the modulation analyzer reading is less than 8 Hz RMS Verify that the modulation analyzer reading is less than 8 Hz average at the following UUT frequencies 1024 950 850 700 640 550 400 320 160 100 80 60 40 30 20 14 Program the external LO to a frequency 1 5 MHz higher than the UUT frequency in each case PERFORMANCE TESTS VOLTAGE STANDING WAVE RATIO VSWR TESTS 4 15 The Voltage Standing Wave ratio VSWR tests use a VSWR bridge and a spectrum analyzer to verify VSWR of the UUT REQUIREMENTS The output VSWR is less than 1 5 1 for output levels 10 dBm 2 5 1 elsewhere EQUIPMENT REQUIRED e VSWR bridge RF spectrum analyzer e High frequency synthesized signal generator FSSG REMARKS The UUT settings in this procedure are chosen to provide confidence in the VSWR performance of the UUT throughout its range However performance also may be checked at other levels VSWR problems are most likely to involve the A8 Output PCA orthe A21 Attenuator PCA NOTE Thefollowing procedures must be done in sequential order to ensure that the proper equipment is connected and appropriate programs are enabled PROCEDURE 1 Low Level Test a With the

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