42” Plasma Color Television Model: PLA
Contents
1. GRE1 GREG iss DREE DcE3 pego apes 19 by cRos CREJ paeo 20 13 25 33 vss len 15 oot seca vs fones orea vss nes ws 0 e MODE o CPU s ves PP ung veux vss 9 for 25 33 mmo peo oo ce VCD _ poos ps ur Wu m 0 y VEU T1 2088 CPU MODE PORT PORT PORT PORT PCRT PORT VHB Bi ET Ab REPERE EEEE E E fmf o EE 85550000595850009055 C D E F J K L P R OW Y i3 L Fig11 PW166 Pin Diagram Top View 3 PDP TV SERVICE MANUAL ImageProcessor Pin Descriptions Name Pin s Type Function raphics P ort Graphics part pixel clack input Typically driven by an extemal PLL GPort Clock The GCLK pin can be selected to the source for tha intemal GCLK that is used for GPort image capture and for the PLL divider sae GCKPOL A GCKSRC bits Graphics port pixel enable input Used for external flow control when EXTFCE 1 When GPENSOG is high input RGB pixel is valid Using GPENSOG allows capture af non contiguous data When 0 this is the Graphics port Sync On Green S0 G input Driven by external sync stripper circuit this pin 6 monitored SOGACT status bit and can supply composite sync information on amp2. speaker speaker modulator rocessin Sound Sound IF2 g Processing a Subwoofer E Headphone 51 o a 552 Ge n SCART1 SCART2 SCART 1 3 SCART Output SCART4 Select MONO SCARTZ Fig 4 Simplified functional block diagram of the MSP 3450G 21 PDP TV SERVICE MANUAL 3 VPC3230D PRELIMINARY DATA SHEET Comb Filter Video Processor Introduction The VPC 3230D is a high quality single chip video front end which is targeted for 4 3 and 16 9 50 60 Hz and 100 120 Hz sets It can be combined with other members of the DIGIT3000 IC family such as DDP 331x and or it can be used with 3rd party products The main features of the VPC 3230D are high performance adaptive 4H comb filter Y C separator with adjustable vertical peaking multi standard color decoder PAL NTSC SECAM including all substandards four CVBS one S VHS input one CVBS output two RGB YCrCb component inputs one Fast Blank FB input integrated high quality A D converters and associated clamp and AGC circuits multi standard sync processing linear horizontal scaling 0 25 4 as well as non linear horizontal scaling Panoramavision PAL preprocessing line locked clock data and sync or 656 output interface peaking contrast brightness color saturation and tint for RGB YCrCb and CVBS S VHS high quality soft mixer controlled by Fast Blank PIP proces
3. Enables or disables all inputs except CLK and DOM Selects bank to be activated during RAS activity Selects bank to be read written during CAS activity Row Address RAO RAT Column Address CAT Auto precharge flag 10 RAS CAS and WE define the operation Refer function truth table for details Controls output buffers in read mode and masks input dala in write mode Multiplexed data input output pin Power supply for internal circuits and input buffers Data Output PowerGround Power supply for output buffers 27 6 TDA8944J PDP TV SERVICE MANUAL STEREO AUDIO AMPLIFIER 1 General description 2 Features 3 Applications The TDA3944 15 a dual channel audio power amplifier with an output power of 2 x 7 Wat an 8 load and a 12 V supply The circuit contains two Bridge Load amplifiers with an all NPN output stage and standby mute logic The TDAS944 comes in a 17 pin DIL bent SIL DBS power package The 048944 15 printed circuit board PCB compatible with all other types in the T DAS84x family One PCB footprint accommodates both the mono and the stereo products Few external components Fixed gain standby and mute mode No on off switching plops Low standby current High supply voltage ripple rejection Outputs short circuit protected to ground supply and across the load Thermally protected Printed circuit board compatible B Mans fed applications e g
4. The PW166 PW 16668 provides a Pulse Width Modulation PM output for low cost backlight or audio control With reference source code and an on chip microprocessor manufacturers can develop feature rich products with rapid time to market Programmable features include the user interface custom start up screen all automatic imaging features and special screen effects second Generation Image Scaling second Generation Automatic Image Optimization Video Processing Picture in Picture PIP Frame Rate Conversion Multi region non linear scaling Color Matrix for improved color temperature adjustment On board PLLsto generate MCLE and DELK PWTGGB only On Screen Display On Chip Microprocessor Debugging Port Hardware Output Applications Flat Panel Monitors Digital Projection Systems Multimedia Dis plays Appica on PW185 10T Upto SXGA SVGA XGA PW1S58B 1 T keystone PW166 10TK Upto SXGA in SVGA XGA PWTSBB T TK with keystone 256 PRGA PW166 20T Upto UXGA in SXGA out PWi166B 20T no keystone PW166 20TK Upto UXGA in SXGA out PWi66B 20TK with keystone 30 uci cm Feo 1 PDP TV SERVICE MANUAL V PS L 5 m V d s I VOD f d V GELK um L T P D i GBES ot GEI SHS ect GGES
5. 6 jon o RTC RAM YAN ARIA FFIE AS GF FFRSTWIN VGAV VSUPCAP TEST VSLIPD RESO SDA SCL Fig 6 80 pin PQFP package 23 PDP TV SERVICE MANUAL 4 Z86229 NTSC LINE 21 CCD DECODER FEATURES Speed Pin Count Standard Devices Package Types Temp Ranke 786239 12 01 to IPC Complete Stand Alone Line 21 Decoder for Closed Captioned and Extended Data Services XDS Preproerammed to Provide Full Compliance with EIA 608 Specifications for Extended Data Services Automatic Extraction and Serial Output of Special Packets Time of Day Local Time Zone and Program Blocking Programmable XDS Filter for a Specific Packet Cost Effective Solution for NTSC Violence Blocking inside Picture in Picture Windows Automat Data Extraction Qn Screen Display Program amp Closed Captioning Rating Time of Day Yes Yes Yes Minimal Communications and Control Overhead Pro vide simple Implementation of Violence Blocking Closed Captioning and Auto Clock Set Features Programmable On Screen Display OSD for Creat ing Full Screen OSD or Captions inside a Picture in Picture PIP Window User Proerammable Horizontal Display Position for easy OSD Centering and Adjustment Serial Data and Control Communication Supports 2 Selectable IC Addresses GENERAL DESCRIPTION Capable of processing Vertical Blanking Interval VBI data f
6. Check IC U3 Whether input 60 output 27 28 signal is OK no output Check and exchange no input 17 PDP TV SERVICE MANUAL Check whether there is Check and exchange the connector audio output in connector which is not good CN1 CN2 40 pin Check whether there 15 audio output in tuner board U5 14 Exchange the tuner board or the tuner 18 PDP TV SERVICE MANUAL 8 Description of main ICs and components 1 M52790SP FP AV SWITCH with BUS CONTROL DESCRIPTION The 52790 is switch semiconductor integrated circuit with bus control This IC contains 2 channels of 4 input audio switches and 2 channels of 4 input video switches Each channel can be controled independently The video switches contain amplifiers can be controled a gain of output OdB or 6dB FEATURES eVideo and stereo sound switches in one package Wide frequency range video switch DC 20MHz eHigh separation video switch Crosstalk 60dB typ at IMHz Two types of packages are provided SDIP with a lead pitch of 1 778mm 527905 and SSOP with a lead pitch of 0 8mm M52790FP APPLICATION Video equipment RECOMMENDED CONDITION Supply voltage 4 7V 9 3V Rated supply voltage 5V 9V Maximum output current 63mA at 9V OPERATING PIN CONFIGURATION TOP VIEW vec E VIDEO 2 IN Leh 2 IN Outline 36PAE TUNER IM 35
7. E SAMP S VHS IN as U301 U302 J3 i Y VIIN VPC3230 PW1230 V2 IN Decoder De interlace AC Card 5 9 12V YCbCr IN SS Ul Zilog Z86229 MEMORY U303 R CCD V Chip BUFFER gt TCPN9082DC U3 U4 MTS Process gt Audio Amp _ Speaker ALIN EXT Audio IN A2IN EXT Audio IN 12V gt 45V DC DC 3 3V PDP TV SERVICE MANUAL B PDP DISPLAY SCREEN BLOCK DIAGRAM LOGIC CONTROL _ THOLEQUT IRX CLKIN LVDS signal OUT A i DOUT E S IRINT C 852 480 Pixels TXOUT2 s 852x 3 480 Cells gx 3 d TOUT3 S z 28 OUER amp 5 18 AU Ydd Va Ve Vset Ver Ve Heterence Ver Voltage for operating Logic Ydd Voltage for FET driver Va Voltage for column pulse f Y5 Voltage for display driver Ver Voltage far display dryer Ye Voltage for display driver Vset Voltage far display driver PDP TV SERVICE MANUAL 4 Part list Part Number Description Qty SPW5 069 166 Polaroid PLA 4200M YPbPr Circuit Board 1 SPW5 969 003 Polaroid PLA 4200M Remote Control Circuit Board 1 A920008 Polaroid PLA 4200M Zinnia PDP Control Circuit Board 1 B135011 Polaroid PLA 4200M 5W 8Q Speaker 8 SPW8 339 008 Polaroid PLA 4200M Main Power Button 1 E143221JF Polaroid PLA 4200M Tapping Screw ST3 8F 2 E143222JH Polaroid P
8. Panel SPW 5 969 003 6 15 Connector S42SD YD CNI i ot LAM ML MIU Sr Tuner board n 9 Power filter board 5 3 CN6 CN8702 DV1 d 12 1 gt FE CN8701 CON8002 He E Right SWITCH 5 3 Speaker Left YPbPr Board na Speaker YPbPr Socket 16 1 220N IN SPW5 069 166 Power supply socket 11 PDP TV SERVICE MANUAL A Specifications for the data signal of Plasma display panel Input signal name and Pin assignment Pn 1103 Fei 4 1 A PDP TV SERVICE MANUAL B Input Power Voltage Source and Pin Assignment Connector Name SA J1 W4 to The Image Board Voltage Source Vcc5 SB PDP GND C ND ND N Vcc5 PDP to The Audio Amp Board Pin no Voltage Source Usage Vcc5 PDP 13 PDP TV SERVICE MANUAL Connector Name SPEAKER W3 Pin no Usage SPEAKER SW Connector Name OSD W17 Usage Vees KPAD3 LED RED SPK OUT2 Vcc5 SB GND 10 POWER SW 13 KPAD5 KPAD7 ON 14 PDP TV SERVICE MANUAL 7 Failures analysis Without raster Judge input voltage input the voltage and and frequency whether frequency according to the they are right Specification Judge whether this Press power key to product is in standby turn on mode by remote control NO Check the external signal Check whether current received the signal is right so
9. ch T IN T IM E WV 1 OUT Leh 1 OUT 1 OUT Reh 1 OUT Y 1 OUT Y 2 OUT Leh 2 OUT C2 OUT Reh 2 OUT Y 2 OUT BIAS CHIP SELECT Lead pitch 1 77 8mm PIN CONFIGURATION TOP VIEW Outline 368P2R D is TUNER IN 35 Leh TIN Rech TIN 1 OUT Leh 1 OUT C 1 OUT 1 OLIT Y 1 OUT Leh 2 OUT C2 OUT Rch 2 OUT TY 2 OUT BIAS CHIP SELECT GND Lead pitch 0 19 PDP TV SERVICE MANUAL BLOCK DIAGRAM d TUNER IN VIDEO 2 IN XS rz T VIDEO AN tTH V1 OUT VIDEO 4 IN Y 2 IN Lait T Y 1 OUT Y3IN 2 YAIN O Y 2 OUT V 2 OUT C 2 IN porca C 1 OUT CAN C 2 OUT Rch T IN Rch21N E RHODE Reh 3 IN Rech 1 OUT Rch 4 IN Rch 2 OUT Lch T IN Lch 2 IN Lch 3 IN Lch 1 OUT Leh 4 IN Lch 2 OUT BIAS 2 SDA HO Control T SCL 19 d GND CHIP SELECT 20 PDP TV SERVICE MANUAL 2 MSP3450G Multistandard Sound Processor Family Release Note Revision bars indicate significant changes to the previous edition The hardware and software description in this document is valid for the MSP 3450G version 5 and following versions Introduction The MSP 3450G family of single chip Multistandard Sound Processors covers the sound processing of all analog TV Standards worldwide as well as the NICAM digital sound standards The full TV sound processing starting with analog sound IF signal in
10. down to processed analog AF out is performed on a single chip Figure4 shows a simplified functional block diagram of the MSP 3450G This new generation of TV sound processing ICs now includes versions for processing the multichannel television sound MTS signal conforming to the standard recommended by the Broadcast Television Systems Committee BTSC The DBX noise reduction or alternatively MICRONAS Noise Reduction MNR is performed alignment free Other processed standards are the Japanese FM FM multiplex standard and the FM Stereo Radio standard Current ICs have to perform adjustment procedures in order to achieve good stereo separation for BTSC and EIA J The MSP 3450G has optimum stereo performance without any adjustments All MSP 3450G versions are pin and software downward compatible to the MSP 3450D The MSP 34x0G further simplifies controlling software Standard selection requires a single I2C transmission only The MSP 34x0G has built in automatic functions The IC is able to detect the actual sound standard automatically Automatic Standard Detection Furthermore pilot levels and identification signals can be evaluated internally with subsequent switching between mono stereo bilingual no D2C interaction is necessary Automatic Sound Selection The ICs are produced in submicron CMOS technology The MSP 34x0G is available in the following packages PLCC68 PSDIP64 PSDIP52 PQFP80 and PLQFP64 sounel IF1 Lond 2
11. fall it may result in personal injury When you draw or insert the PDP s cable you must turn off the power supply and do it with holding the connector If you draw the cable the electric wire in the cable could be exposed or broken It may result in fire hazard or electric shock To carry the PDP module it be done by two workers in order to avoid unexpected accidents The PDP module has a glass plate If the PDP module is inflicted with excessive stress for example shock vibration bending and heat shock the glass plate could break It may result in personal injury And also do not press or strike the glass surface If the glass plate was broken do not touch it with bare hand It may result in a cut injury Do not place any object on the glass plate It may scratch or break the glass plate Do not place any object on the PDP module It may result in personal injury due to its fall or drop PDP TV SERVICE MANUAL 2 Specifications NTSC M Cable CATV1 to CATV125 DE Input impedance gt 10k Q Speaker output Size of screen PDP TV SERVICE MANUAL 3 Signal processing and system block diagram A Image signal processing block diagram 7201 U202 0101 0531 Digital RGB R 0 7 voan ROBEY AL9883A Y PW166B G 07 THC63LVD823 A D Convertor UV gt scale BOM LVDS J Panel SST39VF800A J4
12. these conditions Do not disconnect or connect the PDP module s connector while the power supply is on or just after power off Because the PDP module is operated by high voltage and the capacitors in drive circuit remain temporarily changed even after the power is turned off If you need to disconnect it you have to wait at least one minute after power off 7 Do not disconnect or connect the power connector by wet hands The voltage of the product may be strong enough to cause an electric shock 8 9 PDP TV SERVICE MANUAL Do not damage the power cable of the PDP module also do not modify it When the power cable or connector is damaged or frayed do not use it 10 When the power connector is covered with dust please wipe it with a dry cloth before the power on B Caution If you don t consider the following cautions it may result in personal injury or damage to the product C1 2 C3 4 5 6 C7 C8 Do not set the PDP module on an unstable place vibrating place or inclined place The PDP module may fall or drop and it may cause serious injury to a person and serious damage to the product If you need to remove the PDP module to another place you must turn off the power supply and detach the interface cable and power cable from the PDP module and watch your steps during the work If the cable has a damage it may result in fire hazard or electric shock Also if the PDP module drop or
13. touching the module If the remainder of voltage is strong enough it could result in electric shock Do not use any other power supply voltage than the specified voltage in this product specifications If you use deviated power voltage from the specifications it could result in fire hazard or product failure Do not operate or install under the deviated surrounding from the environmental specification such as in moisture or rain near water for example bath tub laundry tub kitchen sink in a wet basement or near a swimming pool and also near fire or heater for example near or over radiator heat resistor or where it is exposed to direct sunlight or somewhere like that If you use the PDP module in places above it could result in electric shock fire hazard or product failure If any foreign objects e g water liquid and metallic chip or dust entered the PDP module the power supply voltage to the PDP module must be turned off immediately Also never push objects of any kind into the PDP module as they may touch dangerous voltage point or make short circuits that could result in fire hazard or electric shock If smoke offensive smell or unusual noise should come from the PDP module the power supply voltage to the PDP module must be turned off immediately Also when the PDP screen cannot display any picture after the power on or during operation the power supply must be turned off immediately Never continue to operate the PDP module under
14. 42 Plasma Color Television Model PLA 4200M Service Manual Polaroid PDP TV SERVICE MANUAL Contents Salery IBS UCU 2 Se WC ha 4 3 Signal processing and system block diagram 5 EP P 7 5 General assembly drawing 10 6 General connection 11 SARA SAS ee a 15 8 Description of main ICs and 19 PDP TV SERVICE MANUAL Notice This service manual is only read and used by professionals The repairman should review the part of safety precaution before work 1 Safety instruction TO PREVENT POSSIBLE DANGER DAMAGE AND BODILY HARM PLEASE CONSIDER AND OBSERVE ALL CAUTIONS CONTAINED IN THIS PARAGRAPH A Warning If you don t consider the following warning before maintenance it could result in death or serious injury 1 The PDP module is controlled by voltage about 350V If you need to handle the module during operation or just 2 3 4 5 6 after power off you must take proper precautions against electric shock and never touch the drive circuit portion and metallic part of PDP module The capacitors in the drive circuit portion remain temporarily charged even after the power off After turning off the power you must be sure to wait at least one minute before
15. C SEL g1 RED MRNA GREEN 2 BOX 1 WC Address Selection Input BLUE d 00 2 GREN Vid oOuput Opt en 2 3 HUE Video Out Wer SMS de Vy INTRO 4 SEM Serial Enable Iripit VIDEO B 7 Von 5 HIN Horizontal In Input CSYNC 93 Veo Al 6 SM3 serial Mode Sekt Input LPF 99 RREF 7 VIDEO Composite Video Input 8 Composite syng Output Figure 2 66229 Pin Configuration 9 UE Loop Filter Output 10 RREF Resistor Reference Input 11 Ves Pwr Supply Arakg GND 12 Power supply 13 Vertical In lniterrupt 14 SDA Serial Data IniOutput 15 SCR Serial Clock Input 16 SDO Serial Data Out Output 17 BOX OSD Timing Signal Qutput 18 RED Video Output Note DIP and SOIC pin configurations are identical ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit Von DC Supply Voltage 9 5 to 6 0 V DC Input Voltage 0 5 t Von 0 5 DE Output Voltage 0 5 t Von 0 5 DC Input Current per Pin 19 Ei DE Output Current per Pin 20 mA lg DC Supply Curette Pn Power Dizapation per Device 300 mW Teta storage Temperature 65 to 150 T Lesd Temperature mm from Case for 10 seconds 00 Notes Voltages referenced to Vas Values beyond the maximum ratings listed above may cause damage to the device Functional operation should be restricted to the limits specified in the DC and AC Characteristics tables or Pin Description sect
16. IALN P3 D Crystal input for PLL or Clock input if QSC is disabled PW1G66B only U rystal output PW TGBB only Microprocessor Debug Port CPUTMS Di D input Test Mode Select Active high to enable JTAG test for CPU debugger EE JTAG Test Clock for CPU debugger mode est Data Output CPU debugger mode Power and Ground 2 5V digital power VDD2 5P 2 5 analog power Connect to 2 5V supply through 27 ohm resistor 020 V3 12 3 3V digital power v18 YG 37 PDP TV SERVICE MANUAL ImageProcessor Pin Descriptions continued Name Pin s Type Function 04 010 014 D17 G4 317 17 L4 17 119 04 LI LIB U11 012 114 UT W4 WG W14 W17 38
17. LA 4200M Tapping Screw ST3 8 black 6 E143461 Polaroid PLA 4200M Tapping Screw ST4 16 16 E143463 Polaroid PLA 4200M Tapping Screw ST4 16 black 6 E144231 Polaroid PLA 4200M Tapping Screw ST3 10 30 E144431 Polaroid PLA 4200M Tapping Screw ST4 10 3 E690220 Polaroid PLA 4200M SEMS Screw 3 8 16 E690221 Polaroid PLA 4200M SEMS Screw M3 8 black 6 E690223 Polaroid PLA 4200M SEMS Screw M3 8 black 15 E690230 Polaroid PLA 4200M SEMS Screw M3 10 2 E690420 Polaroid PLA 4200M SEMS Screw M4 8 14 E690660 Polaroid PLA 4200M SEMS Screw M6 16 black 10 E690670 Polaroid PLA 4200M SEMS Screw M6 20 black 4 5070183 Polaroid PLA 4200M Power Switch KDC A04 1 1 G330170 Polaroid PLA 4200M Remote Control 1 PDP TV SERVICE MANUAL This page left intentionally blank PDP TV SERVICE MANUAL This page left intentionally blank PDP TV SERVICE MANUAL 10 PDP TV SERVICE MANUAL 6 General connection diagram W2 7 31 D 4 D 2 E ur J5 LVDS ut i LAO03 1 31 WA 2 13 CN UN CON8011 TTL Power 8 1 WS Main board 1 9 X1001 Power a CON8009 Receiving Unit for W3 m CNG Remote control OSD J7 MI NE 4 6 Plasma Display
18. bits rtornally polarity corrected and monitored for amet Sync content HPOL amp COMP status bits GHS can supply horizontal sync information or digital composite syne information depending on bit GHS is also used as the input to the clock phase delay circuit that produces the GREF signal Graphics part feedback line advance input This pin has three different functions depending the register settings for EXTFBK and GFBK Function GFBKOUT output from the intemal PLL divider GFBKIN An input to the feedback pulse from an external PLL divider In free running capture mode this signal is used to define the horizontal capture region along with and CAP and advances the capture controller to the next input line The LAVPOL bitis used to select the polarity of GF EKIN E An input to the graphics port line advance Used in extemal flow control capture moda When GLAV transitions depending on LAVPOL op the GPort capture controller advances to the next input line RET E NE MELLON Graphics port red even data sub pixel input Red channel data for single pixel mode or evan red pixel e data for dual pixel input made Pr channel data for YPbPr inputs Do gus vo 0 gu 0 aue pM GGES 18 ID Graphics port green even data sub pixel input Green channel data for sin
19. ctive low vo niles read extemal RAM external H C81 Miscellaneous Chip Select 1 Active low output selects extemal devices Each Chip select decodes a 256 byte block of CPU address space location of block is programmable xternal interrupt request 0 Gan be CPUTDI input when the JTAG debugger is enabled 39 ImageProcessor Pin Descriptions continued Name Pin s Type Mo J 0 Y d 0 T TO Function PDP TV SERVICE MANUAL 36 PDP TV SERVICE MANUAL ImageProcessor Pin Descriptions continued Name Pin s Type Function A IU ORTB1 PORTE General Purpose 1 0 Port operate in three different modes Le 8 bits of SPIO in VPort 4 22 mode PORTES B4 VO vivid Data in VPort 4 4 4 mode Red Video Data VPort 24 bit RGB moda R 38 5 E RL E 1 10 rans mit data from the on chip serial part Miscellaneous RESET Master reset A high input initializes all internal logic ILI Mode Description JTAG m PLL 080 o poo ____ _ _ 0 LE p Ye qoe Pn tesl made VI D Output se oro o 0 MODEU 13 PLL and DEC ESE only Tee CE LEE NOTE 101 is normal operating mode for PW166B X
20. gle pixel mode or even GGE4 HO D green pixel data for dual pixel input mode Y channel data for Y PbPr inputs NEN 22 PDP TV SERVICE MANUAL ImageProcessor Pin Descriptions continued Name Pin s Type Function D Graphics part red odd data sub pixel input Mot used for single pixel mode odd red pixel data for dual ELM GRO 10 D moto GEES Wr GR D ea ET D E 2 E Graphics port green odd data sub pixel input Not used for single pixel mode odd green pixel data for San Fi Dal pt nt mode 6595 rr 0 SS ee iD EE S mor LE aps part blue odd data sub pixel input Mot used for single pixel mode odd blue pixel data for during vertical blanking Used to prevent the PLL from reactin to extra or missing us tbe eo vertical blanking Coast enable and duration is programmable PLLCM PLLCB amp Video TT Sync IT start e next or frame of data from TT video decoder VM be either actve high or active low as determined by VPOL VYS is not used when a composite digital sync source is used 33 PDP TV SERVICE MANUAL ImageProcessor Pin Descriptions continued Name Pin s Type Function RRE me U Data n YUV 444 mode Green Data in 24 bit RGB mode t Video Part UV Pixel Data Can operate in
21. ion 25 PDP TV SERVICE MANUAL 5 HYS7V641620HG DRAM DESCRIPTION The Hynix HY57V641820HG is 67 108 864 01 CMOS Synchronous DRAM ideally suited for the Mobile applications which require low power consumption and extended temperature range H 57V641620HG is organized as 4banks of 1 048 576x16 HY57V641620HG is offering fully synchronous operation referenced to a positive edge of the clock All inputs and outputs are synchro nized with the rising edge of the clock input The data paths are internally pipelined to achieve very high bandwidth All input and output voltage levels are compatible with LVTTL Programmable options include the length of pipeline Read latency of 2 or 3 the number of consecutive read or write cycles initiated by a single control command Burst length of 1 2 4 8 or Full page and the burst count sequence sequential or interleave burst af read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle This pipelined design 15 not restricted by 2 rule FEATURES Single 3 3 0 3V power supply Note Auto refresh and self refresh device pins are compatible with LVTTL interface 4086 refresh cycles 64ms JEDEC standard 400mil 54 TSOP Il with 0 8mm Programmable Burst Length and Burst Type of pin pitch 1 2 4 Full page for Sequential Burst s All inputs and
22. outputs referenced to positive edge of system clock 1 2 4 or 8 for Interleave Burst Data mask function by UDOM or Programmable CAS Latency 2 3 Clocks I ntemal four banks operation ORDERING INFORMATION HYSTVE41620HGT SU55V6I71 200 182 186 143 HY57V641820HGT Kl 133MHz HY57V641820HGT HI 133MHz Mormal HY57V641620HGT 8l 125MHz HY57V641820HGT Pl HY57V641620HGT Sl HYSIVEMI820HGTSI 4Banks x 1Mbits 400mil 54pin TSOP HY57V641820HGLT 51 551 6L7 200 183 166 143MHz x16 H1 57V6418520HGLT KI 133MHz HY57V641820HGLT HI 133MHz Low power HY57V641620HGLT 8l 128MHz HY57V641620HGLT PI HY57V641620HGLT Sl Note VDD Min of HY57V641620HGILJT 5l 55I 6l is 3 135V 26 PIN CONFIGURATION PIN DESCRIPTION PDP TV SERVICE MANUAL Ce VS 53 0015 52 VS 51 50 DO13 49 VO 48 0012 47 DO11 45 VSS 45 0010 44 008 43 VO TSOP DQB 400mil x Bien 41 VSS CL mm pin pitch AD 38 UDOM 38 CLK 37 CKE 36 NC 35 A11 Ag 33 AB 32 Ky AB 30 5 29 4 zB VSS The system clock input All other inputs are registered to the SDRAM on the CLK Clock VI eee Row Address Strobe RAS CAS WE Column Address Strobe Write Enable LOOM UDOM Data Input Output Mask 000 015 Data Input Output Power Supply Ground rising edge of CLK Controls internal clock signal and when deactivated the will be one af the states among power down suspend self refresh
23. rom both fields of the video frame in data the Z86229 Line 21 Decoder offers a feature rich solution for any television or set top application The robust nature of the Z86229 helps the device conformto the transmission format defined in the Television Decoder Circuits Act of 1990 and in accordance with the Electronics Industry Association specification 608 608 The Line 21 data streamcan consistof data fromseveral data channels multiplexed together Field 1 consists of four data channels two Captions and two Texts Field 2 consists of five additional data channels two Captions two Texts and Extended Data Services XDS The XDS data structure is defined in EIA 608 The 786229 can recover and display data transmitted on any of these nine data channels The 786229 can recover and output to a host processor via the I2C serial bus The recovered data packet 15 further defined in the 608 specification The on chip XDS filters in the 786229 are fully programmable enabling recovery of only thoseXDSdata packets selected by the user This functionality allows the device to extract the required XDS information with proper XDS filter setup for compatibility in a variety of TVs VCRs and Set Top boxes In addition the 786229 is ideally suited to monitor Line 21 video displayed in a PiP window for violence blocking CCD and other XDS data services 24 PDP TV SERVICE MANUAL PIN DESCRIPTION Table 1 256229 Pin Identification P
24. s Display Video The PW166 PW166B includes advanced second generation PW166 166B image scaling that provides completely programmable System Block Diagram horizontal and vertical image scaling Keystoning allows vertical keystoning effects In addition non linear scaling is supported for precise scaling control with 16 9 aspect ration sources and Features displays This high quality scaling coupled with Auto Image Optimization circutry provides sharp full screen images centered onthe screen with no manual adjustments required The PW166 PW 1666 also includes advanced second generation syne decoding which provides full support for a wide variety of syne types This includes interlaced progressive sync on qreen and TMS DE Data Enable only The PWTGS PWTGGB ImageProcessor supports NTSC or PAL video data with a 4 3 aspect ratio and 16 9 aspect ratio sources such as D VD or HDTV Monlinear scaling and separate horizontal and vertical scalers allow these inputs to be resized optimally for the native resolution and aspect ratio of the display device The PW166B uses an integrated PLL to synchronize the display interface timing to the input timing This requires only a single external crystal to generate all necessary clocks for the system only An integrated OSD controller provides bit mapped based 0505 with 16 colors from a 64K color palette The OSD controller supports transparent and translucent functions
25. sing for four picture sizes 1 4 1 9 1 16 or1 36 of normal size with 8 bit resolution 15 predefined PIP display configurations and expert mode fully programmable control interface for external field memory C bus interface one 20 25 crystal few external components 80 pin PQFP package System Architecture Fig 5 shows the block diagram of the video processor GIN Analog Adaptive Color Mixer 20 Scaler Output VIN Front end Comb Decoder Formatter VIN2 NTSC Panorama ITU R 656 PAL Mode ITU R 601 NTSC PAL Co ntrast Memory Saturation Brightness Control vic IT Tint Peaking RGB a Processing Syne Matrix FRO Contrast Glock Saturation Generation RGB Brightness YCrCb Tint 20 25 MHz FC Bus Fig 5 Block diagram of the VPC 3230D 22 Y OLIT OLT FIFO CHTL LI Clock H Syne V Syne PDP TV SERVICE MANUAL Pin Configuration IH TLC VELIPSY AVO CHEN FEYIMCIHEYA oo MSYMS C1 FPDAT A SY A C3 VSTBY GNDC VSUPC MC XTAL 1 E XTALZ CE GF 64 63 62 61 60 59 5B 57 66 65 54 63 62 50 49 48 47 46 45 44 43 42 41 CHE d r I2CSEL v2 v3 VSUPF VSUPY VOUT EE CH V i pie be VPC 323xD a VINZ VIN YT VINA GNDLLC VSPA VSUPLLE GNDAI LLC VREF Lice FB1IN VSUPPA AISGND GNDPA 10 11 12 13 14 16 16 17 FFRST FENTE Ii
26. sound PC audio B Portable audio Table 1 Quick reference data Ver supply voltage b 12 18 V n quiescent supply currant Veg 12 V Rp 24 46 m lab standby supply current 101 WA 28 PDP TV SERVICE MANUAL Table 1 Quick reference data continued Pa output power THD 1095 8 0 7 W Ver 12V THD total harmonic distortion Py 1 WW 008 010 voltage gain 31 32 3 dB SVRR supply voltage ripple 50 65 dB rejection 9 Ordering information Table 2 Ordering information TDA amp 8944 DBSI7P plastic DIL bent SIL power package SOT 243 1 17 leads lead length 12 mm 6 Block diagram OUT 1 OUT 1 OUT 2 OUT 2 SHORT CIRCUIT AMD TEMPERATURE PROTECTION MEKI GNDZ Fig 9 Block diagram 29 PDP TV SERVICE MANUAL 7 PW166 ImageProcessor XGA SXGA Flat Panel Display Controller IC General The PWI66 PW166B ImageP recessor is a highly integrated system on a chip that interfaces analog digital and video inputs in virtually any format to a digital projection system or multimedia display The PW T66 PW 166B is pin compatible with the PW 164 embedded SDRAM frame buffer and memory controller perform frame rate conversion Computer images from VGA to UXGA at almost any refresh rate be resized to fit on a fixed frequency target display device with any resolution up to SXGA with full 24 bit color Computer Clocks
27. three different modes V Data in UV 4 4 4 moda Blue Data in 24 bit RGE moda 1 0 VUV6 C12 D 8 DD L VW DELK W12 TOITS clock output Enabled when DOT KENG Polarity is inverted when DCPOLz1 Runs at gt EMT rate wel 2 1 mae Display pre enable M 0 te Oo DRES 17 0 Displayred even data sub pixel outin dual pixel output mode LL Display red data sub pixel out in single pixel output mode DRES CH 5 ML M DGE3 W19 O Display green even data sub pixel out in dual pixel output mode DGEF 70 O Display green data sub pixel out in single pixel output mode vm 0 DCE Us 0 MEIH 7 Wl pe DBES Ulis O Display blue even data sub pixel out in dual pixel output mode Dis play blue data sub pixel out in single pixel output mode Ds vie 0 DES 34 PDP TV SERVICE MANUAL ImageProcessor Pin Descriptions continued Name Pin s Type Function Y WE Display red odd data sub pixel out in dual pixel output mode Unused in singe pixel output moda e nft AE E CH ro 035 Ww 0 DGO3 U8 O Display green odd data sub pixel out in dual pixel output mode Unused in single pixel output moda BHEN High hyte enable RAMOE RAM enable A
28. urce Turn off for 2 minutes then if it is ok maybe failure turn on again to check whether results from poor contact the picture emerges 9 Open the rear cover then enter NO Replace power supply power on mode to check the switch or filter with CON8002 220v voltage of PDP poor performance 15 PDP TV SERVICE MANUAL y YES Check the output voltage NO Check repair 8011 CONS009 of display screen power power board board voltage YES Check the input voltage J1 Check and transpose the J3 connector of main line of connector board YES Check the supply voltages of NO Check OR transpose U15 1 4IN D1 CE21 CE26 mainboard Vec5 SUB IC U 15 4 Vec3 IC U8 2 U8 2 IN C198 CE33 YES Check or transpose the signal data line of connector check and transpose the main board check the driver board of PDP display screen and the slices LC ere Check the other circuits 16 PDP TV SERVICE MANUAL Display image but without sound Turn on to check exchange tuner board whether there is noise Read the Operating Check whet her the instruction and set the volume is correctly set volume again Check 7 waveform Check and exchange of Speaker s audio speaker Output Check IC U4 whether no output Check and exchange IC U4 input or output signal is ok no input
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