RML 480Z Service Manual
Contents
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3. JE 4611 crc ew TD TPC PodZut H RP 2 kdRMS AN NI RMOHRTI M Ryfoti ao WAPAT A2 APolT2 At Ao LIK EUT f DRAWING NO D120502 pnd D b Sur TUER Ce tee EE Mu food TI 3 ER uud z RAS J ma CR 1 ta 1 Hi Set 4 ENE gie gear 4 wa m DN SV u i RNB RE s ACH 4 d ues ans Mer Ch 402022 mai 2 al 2 KAS EE L 15 QE 15470 4 M s MAIS duis 4 i Tok AA Q Val E 36 mir w ZArSH 22e Al 4 RAMEN Za fALEO RESH s 6 P Ibi nns N P ol AAA MTA E 8 9 6 7 mA ATA meta C aap ad TX Tres Sngt Tp Ce e n 196 Au gl MRING 2 Rolt J 3 MIA SA MMTAL Ligua T 25 MEG CHECKED BY DSD DRAWN BY C As DRAWING NO OOR SHT 2 0F7 MODIFICATION pL iii pipa s s 2 oub en Me sx b n o ox s JE dta 0 PP gv f 3940 MMJ T SOL V 4 uv 150 LA EER 45v Sos TU len T Bou ETT OU 4 164 164 Q 164 ly by vd HILH 61 cos Ov ung essa P H aa P ee Ka MAD ann AL nr fas A id I Of 5 DS 39 3 3431 E ACH iC gS
4. ma vyop 7 m Mik ii al THW y 3 4 4802 Option PCB 9x91 vary Sun Tolo i 9 d V 4 9j 94H Burddeu q Azowep m N Tel 4802 Option PCB During field blanking IDO to ID3 are enabled through to LAO to LA3 If LKWR is activated at this time data latched in WRO can be written to the lookup table The CPU can only access HRG memory when VMEME is active i e during line blanking field blanking or when the screen is open Read port 2 allows the CPU to monitor these three conditions SHEET 3 Once a byte of data has been read from HRG memory which occurs every 500ns during normal screen refresh it must be divided into individual pixels This action is best understood by considering the relationship between pixel time and byte time across the screen see figure 3 3 In extra high resolution mode the shift register is enabled by HIRES memory data is parallel loaded and clocked out at 16MHz to give a row of black and white pixels This action shown in figure 3 4 is identical to text output on the main PCB In high and medium resolution modes shift registers EV and DV are used to pick out the appropriate pixel bits two for high resolution and four for medium resolution see figures 3 5 and 3 6 The speed of the clock going to these shift registers is controlled by VSCALE using 4M
5. RpPoR12 RoPor13 S ACSCT AEN APORTE KD o414 17 l a di NETOUT1 107 ud 34 E u bal 197 34 21 vou T 196 H KAESET IDL 1 ALTCHK TDL IL ak 5 34 8 0 16 vouTS U do o 6 2 VHT TDE N LSPCAK 105 Tof T LSIN a 5 15273 T YHOVTE TOI 52001 93 192 r REIWEN 192 C ASM 4 15374 mw a 4 AD vou gt 1 34 k Vout 11 tk 7 2 101 UooT 199 101 NNI S ER PAI 41 i GA CAMI Tpi sv d in 104 JA SS pl PACED TOP a 2 cesogcv 194 E de WwRPoMTI ROTI URP RTI l RPPORIS 4D 3 Die 7 Sur po gt sar 2 2 to 5 vwb 1 1 Tos Ling S2RxD 10 vink UM u12 S1 524175 Tp3 uvm vis U han 4 S2EARTM Sows Tic 2 102 202 ATI R31 Ae Mi oGavT BUTT04 1 31 4 D10829 s r ses 580 oa BAN amp 1 2431001 15 4 19226 43057 7 1p7 LVS p ti o bt A sa HAAS DCA 201 ip HA AITA Zm 2 91 d 2 5 Di yaq YA gns Al RIA 7 80 0 MAP S o ef DO MERS EE 1 Di Bla RADA CIS n p
6. 4907 SERVICE MANUAL October 1984 3802 AND 4802 SYSTEMS SERVICE MANUAL PN 13821 Copyright 6 1984 by Research Machines Limited All rights reserved Copies of this publication may be made by customers exclusively for their own use but otherwise no part of it may be reproduced transmitted transcribed stored in a retrieval system or translated into any language or computer language without the prior written permission of Research Machines Limited Mill St Oxford England OX2 OBW Tel Oxford 0865 249866 Research Machines has a policy of continuous development and improvement of its products and services and the right is reserved to revise this manual or to make changes in the computer software it describes without notice Research Machines endeavour to ensure the accuracy of this manual and that the products described perform correctly according to their descriptions However Research Machines Limited do not accept liability for the consequences of any error or omission Additional copies of this publication may be ordered from Research Machines Limited at the address above Please ask for the title as given above a TAA SECTION SECTION SECTION SECTION FIGURES CONTENTS KEYBOARD MAIN PCB 80 Character Mode 40 Character Mode System Read Ports System Write Ports OPTION PCB High Resolution Graphics POWER SUPPLY General Mains Filter and Rectifier Flyback Convert
7. DRAWING NG D10829 s r 2 or 6 MODIFICATION malo 2 N 18 o1 vp PAY YA vor d 0 vc c aan 5 v c 1 ov 3 4 vat q vaa va 04 ve kad assa 4 im cat 4 d CM el vss E I AL mamta 124 mm TR lle m TI MOT Ai mm Ad de 5V fo aL A AT Ab AS Ay A3 Pa AI AO 20 zD2 MODIFICATION 100 4 116 ot NI mat 086 zp1 45V Rom el H EN AS A RomatC ROMAEN Du ROMALD 2p7 206 26 29 293 4 Wb ot ELA mA man zp2 zp3 zpy ZPS ls EE 5 Rom no AEN 2 ol Romall RomaLl Lo of Au I ou 2 kamal 1 Romat A I ol2 QomaEN Rom EPROM LINKS A HERE ARE A SOCKETS koh KOM oR EPAoMi CONTAINING SYSTEM OR APPLICCATION Sor TAKE EACH oF THESE SOCKETS HAS ASSOCIATED un i A SET OF Liex PINI BY SUITAALE CONNECTION of THESE A LARGE VARIETY OF tom OR EPROM oc THE EV ontY VARIETY MAY GE VIED RANGING Id SIZE FROM dx ua L 8 Bytes NB WHEN STALLING 24 PIN DEVICES PINS 1 26 of THE SAKCT SHOMD ga USED Z b LS L3 LT T Lu ES LV Lb zp A Two Gaaxs or RAM mad 7 MAAT Lien BANK CAM CONTAIN LUTHER 8 x Aub oR 8 gt KALA me TYPES OF CHIP INSTALLED IN A PARTUWAR RAM BANK S SELECTED Gun THE Row
8. q Rolt A u p UP 7 i I u PAE KL 15393 IQ 8 gt p LS JP rc DI i mi 1 LSt t EUN Ml A aa Qc QD di ep 4 a ju Y cp cb Cd EMHZ miu 16 N Duntc R gt CALL S287 r amp et HQ CELE CCL 15371 FP t D u 4 a a 6 at 47 tcik _ upio OUT Aupio VMA2 C Put 4 MHZ L LNk m YywC F VK Pimi Sieg FSYNC x9V Connecreo AcRoss RC tt Com esS Sit1 v pEo vae may vaas VAAT ali R4 vanme vrat veras IV41 Vim X2 Di vas ASTCC UMWNEIL mpi VINA VAAO D10829 sur or 0 2 Tya Ja py 1 METIND ip E aa 310 da T Gw dt TOA E 31 o got h 1 18 yi 11 Ad 3537 To k T 33 1 kePf d Imapstgi ee 544 2 0 2 kev 157 310 1 1603 ER N mx vol SH cason n VOL s 194 L 5211 E Es 102 4 Hes Kapit APY 192 BT 4p n 5 OI NK 10 y TV3 UH ui 194 K am JOH sinw Tr CASVOL 10 s EE wel ec Av n YH c 161 NK 194 CASI 194 a 75 9 kv 2 i t ER R B 7 00012 8 0 DIL senden
9. Use scope to observe test Diagnose and repair RAM Garbage on Screen Insert RAM test PROM Screen clear Suspect mapping paging ports Figure 3 1 Diagnosing a Garbage Fault WA M M C SECTION 4 4802 Fault Diagnosis Guide FAULT AREA CORRELATION Use this section to identify areas of the circuit likely to be responsible Refer to the following table for fault symptoms Fault Symptom 1 4 5 No Keyboard Response No Cassette Send Rec No Front Panel Garbage on Power up No display Locks up CONCLUSION Suspicious Areas Keyboard CTC RDPORT3 Memory Int ROM CTC IC CP RDPORT2 RAM System RAM System ROM ZDBUS TDBUS ZABUS ABUS RAM Mapping Paging VDU memory amp addressing processor Clock PSU video o p stages Check earthing revision INT RAM processor Diagnostic Procedure Check KBD ready ICs BP GW DP look for keyboard strobe processor generally enters for keyboard INT Test memory check signal path for fault Test memory Follow flow diagram Check processor state Use test PROMs Check suspicious areas in turn Check suspicious areas Test memory This supplement makes no attempt to be a comprehensive guide to service on the 4802 Experience has shown from production servicing that system RAM is fundamental to operation and almost any symptom can be attributed to
10. 442 191 Ai Tp Ayi 196 Ad MAD MA mat ea MAL MAS MAS Tad Ar ai ai A AC Ab 101 1 por LEL 101 TPS TPG 10 e imu ER meres p 0 z p Ips ros Ips Y 196 5 201 193 ii fp 193 9 3 Z Pl 791 102 In 12 pu 194 0 6 191 291 Ipi 299 15 i 192 17 121 RAS ens RIG 2 2 da 4 1 A 1P7 MAAS MCAS veel TOL SN DDC We 195 VAC BLC IP tc G m 194 M RES FCE 124 1 LAI ID CFA MAM op lt 102 56 7 HEC IN 1y1 AA ORAWN BY CHECKED BY DRAWING NO INK OPTION BOARD D10830 sur 2065 HIGH RESOLUTION GRAPHICS 1 BUS INTERFACE amp MEMORY A Hi Gi NK Hi Gi an Heid 2mHz MEME HLoRDt G amp LAWW VRAS e Lr Luz T L NM YC PIL sg gt RS fam kan DR 221 macs LCT uch GA bawi E Teb ua V iyi e opt du V SIL HL LNK N od DR MPT7 VSCALE IS MPTE ls mpu He 7 7 DAC 4x7 nm upp EV vipc ATH META 3 neam Far NK 1 4 A nn 4567 TI E LM 1 g
11. e IDT ie geseT 196 106 gt t y en 102 I pi 10 Cop K QC KC L 7 parc ton top DRAWN BY CHECKED Research Machines Ltd N TITLE DRAWING D10830 sar sors o H lt o v a o z KEE DRG No D12794 Sht1of 4 Es LKB Bern een T n wi po pM 19 11 12 cl ls o O A pm 1 11 Ig x 0 9 A3 2 1 0 MAP DECODE WI PAL 1216 2 al E as 13 j LJ UNLESS OTHERWISE STATED ASSUME THIRD ANGLE PROJECTION 6 N de ANGULAR TOLERANCE 12 WHOLE UNITS 5mm 1 DECIMAL PLACE O 1mm ES GEOMETRICAL TOLERANCES SEE BS 308 METRIC TITLE lt CIRCUIT DIAGRAM IDC 4807 BUS INTERFACE amp DECODE RESEARCH MACHINES LTD Mit t Oxford OX2 08W EARLY ie NO PRE COMPENSATIUN UN De 3 18 106 MDS 84802 VERSIONS 3802 480Z P BMH2 ipi LAIERUe WITH PRE COMPENSATION ON RER IMDS amp 4807 VERSIONS 16 102 380Z MDS MDS 2K MDS BK 4807 L PHI n L 3802 FDS FDS 2K FDS 8K L BMHz ku PHHH 103 ISSUES 3802 2K use le 5 3802 amp L xax bs LU 105 m SEE ECN160 FOR WER FULL DETAILS OF ANNI EARIY amp LATER e TLL m IWD 2 092 wp DWD R 20wD WD DWD DAE e b parte MOTOR ATE 6 74ALS576 15 DTIMED amp Ge ahi DROWT H HUR E DHW 55 CTCEN DwRwT
12. 12094 BREMEN EE e 5 Na age LE A a Lomfon nis OH Was ke q JT 3 E LC q gio 112 10 Mbi a TRY D3 De pS LUMC 496 A d Dunta t W 1 v Du iH bu Ko d p d 6287 FRAME 4 x iC 54 Gl Pi va 93 ea ta m e 1 U ci lt o x RO E 1 CB c2 L INK S 3 days 4 v 1 ET fet a e n da FR PLAK YA px z ic d FT nr TE m YwC ERL K Dmi AS TC FSC ii 42 41 A3 DL TC wg 43 A RI A eu I vi 8 L 1 Y tamil 41 tot Comes TE viDEO NAC wma AT nn vmAb vaal 1 ORE FRA Sen vid o Ak ING M g mei ViDm x2 dodi 6 Unt Tak A A k 57 ASTCC vaoco va t 3 umune 36 s mp1 vend ve a D h Vra dic v DC ARTA cueckeo BY DSP DRAWING NO LOD SHT amp OF 7 MODIFICATION w p 1001 25 fisu 1 i e E i 1 1 1 v E fr Mha ceo TU EE ib 7 au u pes WE TIME T T 3 4 262 TO 2 244 1 2 V lu 1 A 43 SE d 17 MA 4 T 1 4r e it 9 vb WE mm Mi lundi T x Gb Yu 4 ntvl taps TA 34 11 iod 1C 38 1960 n 1 1 me
13. 450Z Main PCB generate pulses JT and JT2 which are proportional in width to the position of the joystick i e value of resistance Both outputs can be monitored by the program using read port 2 SHEET 6 The SIO is set up during initialization so that channel A is used for the network interface this requires a network transceiver board to interface to the coax Channel B is set up by the monitor program as the SIO4 interface and it has several baud rate options The CTC ports are set for the following use Cho This is clocked at 2MHz and is used either as the SIO4 TX RX clock or as a timer for detecting the freguency of cassette input Chi Has three uses to detect edges on cassette input the time between edges then being measured by Ch0 to generate cassette output frequency and to time output for the SIO2 interface These three functions are mutually exclusive Ch2 Is used purely to generate interrupts from KBDSTB1 Ch3 Clocked at 50Hz field blanking signal sheet 4 this channel is enabled when the repeat key is pressed to generate interrupts at the repeat frequency Interrupt daisy chain is such that the SIO has top priority for network use with the CTC second The option PCB has lower priorities When writing to cassette the output of CTC Ch is divided by two and fed through an op amp filter circuit to produce an approximate sine wave suitable for cassette recorder input Signals from the recorder are fe
14. MHz cp sauek H MOTE DACOUT 019 A MPT2 DRAWN BY CHECKED BY DRAWING D10830 s r 3 ors MODIFICATION KE VIDE o ESA 5 10 ans ss RR 4 low oo 1 hihi wore CQ 77 UL ut RED DAC Gut GREEN HIKESOUT LINE SYNC MSYNC LINE SNC uan HEG IM FLAME SYNC R3 560 GaP v DeAc n SV Research Machines Ltd THE DRAWING NO D10830 snr o5 MODIFICATION pT Zyl 20 20 203 272 es 207 1 2 DK z o 201 zp Sy ACK 5168 END Sw ANT t yt 704 tog Mi RD II y 314 2 jus 1 pt D2 26101 104 Ig co Ol q 06 ml wi KJ Ap mv a EN D 7 IacieT 280A CTC Cin her 4142 TEE INT 2c Ho L uxeci 9511 107 zc fre Cuk betan H 9 214 102 C lt reca J 5 V 7p7 zpk 295 203 292 191 294 Hi CON A2 ar 40 7 T m al Biase BS A a L prol 37 15 9107 STI Diet 51 14 PloS plot ya 1 Prot vlo 010 52 10 SEN Zyl IEEE i T d ui Bx 60 MAL 5 EE i 7 er wi EEG 2 qn EE ZT JAESET di Pa ZR T 39 T amp
15. PROCESSOR 4MHz 280 One wait state every memory cycle as in the 3802 and each VDU access RESET Reset logic pulses reset the processor during power up and while the RESET button is pressed Reset is active for 128us and inactive for 512us and is synchronized with M1 to preserve memory contents during reset Keyboard reset is automatically activated on power up or after reset and must be cleared during ROS initialization by setting bit 6 on port 1 SINGLE STEP Single step logic is as on the 380Z An NMI is generated following the eighth M1 cycle after NMIEN goes active high Note that NMIEN is inactive on power up or after reset so that it need not be de activated as on the 3802 MEMORY e ROM There are sockets for 4 ROM EPROMs each of 2 to 8 Kbytes Mapping of the ROMs is controlled by a PROM 2K resolution which allows for four entirely independent maps selected by two bits in a port PAGE 0 and PAGE 1 Map 0 is automatically selected on power up and reset For any given map any address space which is not occupied by ROM is occupied by RAM 2 1 4802 Fault Diagnosis Guide e RAM RAM mapping is controlled by a writable lookup table This takes the top two bits of the processor address bus A15 and A14 and separates four address bits MA14 MA17 Of these MA16 and MA17 select which of the four banks of RAM is to be accessed while the remaining two bits are used to select which of the four 16K pag
16. faulty system RAM m moon 6 AP L MI LLCh o NMIEN De ore m 4 H 5 U 11 dA 1 15390 ah X ap oc i WANTEN LMR VOULCN MILK 45V 14445 P7 RSTPOR B d GO Yu I c23 Gris SU paqu c GW N R3 mi 313o 45 V Rsi ZCLCK VDUEN CTLEN SIOEN 49511 crc Ew IEEE EN HRLE MT Pot TEN TPEUSEA ZINT T INT H V RD VDvAD VPUACC PROCESSOR SUPPOR 196 Research Machines Ltd DECODING 2 RP 5V 2 Al AO Peg TC wR 15V A2 Ao TPT TPC TPS 0 Ty3 TD2 TP DRAWN BY CHECKED BY DRAWING RD Poet G RIPT 3 RPRRT1 RPtoti Rfe LIRP LTS LRP ART F RPT CKe6QTI D10829 sur 1 oF6 52 a MA Viv RAS3 CAS 6 ZRFSH RAS2 ALI 22 RSP RAS O 22 K RASI AS ZAFSH Ark 41 MAIS Qmm An RAMEN 45V b MAI Au Komite ZRP RoMIEN PAGE Rom 1EN RAMEN Rom EN 5V AT 228 s P U E Ap Kran E L 193 792 AL CACA des m Ao A3 Au De I mi red MMTAL mmas fv Pei ZA MATAS
17. kapa ere en nun seamos avm as d k 5 O DEPRESS x SLI W 7 31 ICCd actae hosce m w ae ex rat Y maes D4 ui TEV 27 V 4 r i Mb th RESET A 0 12 da a Pa 3046 TRANSISTOR ARRAY N 2080 alpham eric Alphameric Keyboards Limited Menor Way Old Woking Surrey QU 22 9JX Riitit preragrrl M d RE GODE N TE mi Custome EE aisti er A
18. vw 9 12 7 HSTRD D DHST SIOEN TRD HSTRD gt HRD HWR APRD dls x ORG No D127 Sht 1of 4 5 40 44 EL DO NUT SCALE HEMOVE ALL BURRS ORG No 17 4 Sht 2 of amp u a AN V A N TXDA sax IN 5 El 9 28 MIS RFSH HALT PVSAK BV 107 A AL Jo AY Vee Mi 10 Et IWAIT1 GAS 4 104 E ER 1C44 e sl eis _ 1 1 Bj ZBOACIC 103 m DFRA lt AM IC46 103 SR 40 2 4 7 A C HI ZBOACPU 102 u 112 28210 US A9 101 De DIA JENE RXDA TRG2 i AB 38 IDo IDO DE 34 16 MBA IA1 t nn AS Ad m lao 33 DI DIRA pl opa DA aa A2 32 IM1 1 1 By E RADE SIOEO ij 2 LIORA Wm Sa 26 TXDB 0 N ag 2 IRD IRD Za DEI RT CS i 0C Lei DCDB Xe RESET CTSB JTXCA YXCA JRXCA RXCA UNLESS OTHERWISE STATED ASSUME ANGULAR TOLERANCE 1 2 WHOLE UNITS t 0 6mm 1 DECIMAL PLACE t O 1mm GEOMETRICAL TOLERANCES SEE BS308 METRIC THIRD ANGLE PROJECTION 6 m RESEARCH MACHINES LTD Miti St Ontord Ox2 oew A CIRCUIT DIAGRAM IDC 4802 CPU SERIAL INTERFACE amp CLOCKS DRG No D12794 Sht 2 of Fi ar TA 603602 rA x ORG No 012794 Shi 3 ot 4 kp LINK PINS FOR LK 2 E 2K LK9 ROM SELECT LINKS LK9 50 PRE LIN
19. 1 0 1 l lt EN E 7 2 b v ISOLATED exe 343 FEEDBACK ms seor gt Ov Now T o ATED DATE DRAWN BY CHECKED BY Research Machines Ltd Travsceiven Power Sueri r Sht let 2 zi o lt E 5 O z w P 1001 E Tx DAT 37 13 CLEAR DATA RDAT 2 1586 _ amp DAT 2 A lt CARRIER we Inn WV ott Je TR3 E A TRE BAW 62 S zemmer sor di Ka i Hp r 85x20 Tez a TRI Coxu J 0 D3 257 CABLE Ov IsoATEP P Sv now Tse ATED moe 9 0 i Research Machines Link 4802 Skt dof 2 TRANECE WER MODIFICATION lt ole uf fof 3 xi Wf AOT orawn BY CHECKED Bv 5 D ACE anr ii e dee jak a En 1255 4 LAND 1C 50 Que 5 Tau eb Q J WALEN VUEN lg 3 MACK i L 46v RSS 3 TINT 7 RESET 4 BuTTan MODIFICATION 24 Gant 15 Qus A 23 a uel Z80R CPU d int 16 IC 63 d GUSAK mi HI 1078 pie TE p GT 23 AAA A a EEE jea D URLEN Pon ICAN Tout 4 7 20 f3 LALLA ur mi Mi todd T 6v 4
20. OF LINK Pins ASSOCIATED GAM THAT BANK KE Fel BANK d map 17 FoR BANK 1 FoR HULS KINK PINS 1 2 3 4 7 8 FoR Loan DPevS 2 3 4 5 6 7 ceg 6 O CDT 1 45V o CGENC o ALTcH amp 4 eea 4 10 CGO A 6 O L2 AS YTM THE Rom SOCKCTS Tue CHARACKA CC CAG SOCKET CAV SINT MOST TYPE or Rom feetom CHIP 1516 mb 15372 17372 15 bl 2761 b esearch Machines 3 5 3 5 5 4 2 1 1 4 Cew CCT crm 8 10 6 8 8 10 5 1 6 8 92 1f0 S L 7 9 6 10 6 8 Sv CGEAA lt c03 cp2 11 Coo RI 42 RI Re SRY 46 6 av CD 2 12V HV 4 SV YI OCE TY an by m 12 ALL Pouch SUPPLY LINES anv 48V ev 6 v 12v AKE prc 00 ED WITH A MaTVRE OF CERAH CAPE Co kup TANTALUM acaps Ct fon SV Cu fot a Co tden THE Sof Y To GROUND Ence er FOR 48V oun IS DECOUPLED To VIPEARTH g V BT CENE SV 35 C C94 eb CHARACTER 5 2 Gn GENERATOR 2 co L Y l 199 gay 8 sat I sag 15 503 DRAWING No D10829 s r 3 or 6 nii RIO At Li M 41 43 Pu EEEN 7 Ly ANG A 3 AN Cy An Cs o JA TE K fan Z d Al S 7 f m 3 W
21. ROS to operate giving access to the Front Panel for diagnostic procedures These include faults such as SIO port failure cassette port failure etc This type of fault is the easier to diagnose yet may still require software routines to be written to test the failing circuit Programs may be entered using a ROM Pack the Front Panel or cassette 2 Faults which do not permit ROS to operate sufficiently to be able to use the Front Panel and or the cassette interface to enter diagnostic software Faults include garbage when switching on no keyboard response etc The 4802 differs substantially from the 380Z in circuit operation and in fault finding technique because it is designed as a one board not modular system Therefore it is essential to understand the operation and deduce the faulty condition from within the faulty system this is particularly relevant to the second category of faults The problems encountered at RML with repair of production failures led to the invention of small diagnostic routines blown into EPROMS which do not require the operating system or RAM to be functional They provided RAM screen and port testing and also set up diagnostic loops in suspect parts of the circuit This approach is recommended for fast diagnosis A flow diagram for diagnosing a garbage fault is shown in figure 1 3 1 4802 Fault Diagnosis Guide Suspect address data buses processor etc Insert RAM diagnostic PROM
22. each byte represents 4 pixels 2 bits each th s gives only 320 horizontal x 192 vertical pixels on the screen However each one now has four possible values 3 Medium Resolution This mode uses 4 bits per pixel each having 16 possible values Vertical resolution is also halved giving 160 horizontal x 96 vertical pixels on the screen This only uses half of the 16K memory and so two pages are available allowing the CPU to modify one page while the other is being displayed In modes 2 and 3 the pixel value goes to a lookup table which is programmed by software This is a 16 x 8 register and allows each pixel value to be converted to any 8 bit value from 0 to 255 The output is passed to a DAC to give the desired pixel intensity which can then be mixed with text on the normal black and white monitor output Three bits of the lookup table output are also passed to the RGB output driver allowing the use of a colour monitor As with the black and white output text can be mixed with graphics under software control The three colour bits chosen from the eight bits are those which will give a sensible relationship between colour and intensity Although sixteen intensities are possible in 4802 Option PCB medium resolution only eight colours can be displayed on the RGB output TTL levels SHEET 2 HY buffers the Z data bus to the I data bus when accessing the HRG ports HRGEN active The direction of data is control
23. line FR is clocked by LCLCK and reset by FRESET both from the main PCB to give a line count which is synchronized with the normal text output The column count goes to the memory via FU and the line count goes via FS both are enabled by VMEME In medium resolution all even lines are page 0 and all odd lines are page 1 In this mode LC 1 is set by the state of FORCE i e page select via EP thus reading alternate lines of memory on two consecutive scan lines VMR W is set high by EQ VMEME high to disable writing and VRAS is developed by the HRG timing chain sheet 3 The address line multiplexers and subsequently MCAS are switched by 2MHZ from the timing chain HRG port 2 is used for control and status OPEN stops screen refreshing and allows the CPU unlimited access to memory dynamic RAM refreshing is the responsibility of the CPU during this time VSCALE and HIRES FORCE VIDINH HRGINH 4802 Option PCB pene the mode of operation VSCALE HIRES Extra high resolution High resolution Medium resolution Not valid O as a sets the page to be displayed in medium resolution inhibits text on the RGB output inhibits graphics on the black and white output 3 3 4802 Option PCB DUH DUTITIM sy2w m madamu ssamppo SAUPTMS wa SVAW SVY SIM sng wen I a q pres za
24. output Field RESET FR is used to trim the field time to the required 20ms 50Hz by resetting and row counters during line count 31 If these were not reset the field time would be 32 max line count x 10 max row count x 64us line time 20 48ms which might cause instability During normal screen refreshing the 7 character count bits C0 C6 and 5 line count bits LO L4 define the character position in RAM with some redundant addresses The 2K RAM used although being of adequate capacity for the display only uses 11 address lines with no redundancy and is not compatible with the 80 x 24 screen format in other words the RAM is too square and so some juggling of address space is needed In 40 character mode no problem arises but in 80 character mode addresses greater than 63 are mapped down to the redundant lines 24 to 31 in three groups because CC6E is active column count C6 via GP and HP and switches the multiplexer MP This is illustrated in figure 2 6 Access to the video RAM is divided into two equal time slots by the 2 MHz signal VDUACC CPUACC so that the CPU can write to the screen without any timing restrictions and without disrupting screen refresh During screen refresh VDUACC high the character and line counts are selected by the multiplexers KP GQ and GP and are latched into LP MP and KP on the falling edge of 4 MHz i e half way through VDUACC When EOC is active the data addressed is latched int
25. 14 RE Ajo La C G OG lt c6 cB cat CW 36 di 49 JOO Di DL TR TRY TRS Sy BIOR SV d Ra Tse ATED Gaz Ov Isosatep CHECKED BY psp DRAWN BY CAS DATE 2 9 83 DRAWING m D2093 SHT 7 67 ri AN 43 0 G18 ar N Mot GS s 899 3 422 CT 898 3 22 3 V Y V L o O S 113 8 GSS T CAS TAL TAS TAG 183 TAI TAA MODIFICATION _voo3 d TALI ad J Jes qut 4 MAD amp 16 y l m d gil hebt MAI 4 1 4164 64 4 tbl mA Ln L HATT MAI UG U MER ET 2 A ul ich mat 20 M s mr ub A 164 Al MAS MAG P po pi ge D4 zp s all Po ub ANI Lub MYYN MAS mtb Machimes Ltd 4118 MA 46 4154 n 677 DRAWN BY CHECKED BY D10830 ser 1 ors cci mi 1 ME N Gl t L AUT CS AA H mag N A MAL LY 6 cy ib Laus 17 3A iQ TAY nd 15v M ET IL e A e N diu A b Ae U Aen K i lt wi 2 f m 1 old maz 3 1 mAb 191 i E E gt 1 EC LA 48 H S lue d AD3 192 ko t 1 4 mal 40 4S Vy h
26. 308 METRIC THIRD ANGLE PROJECTION 6 CL RESEARCH MACHINES LTD Mm si Ontara Ox200w TITLE CIRCUIT DIAGRAM IDC 4802 MEMORY WAIT STATE amp INTERNAL DECODE DRG No 012794 Sht 3 o 4 2 pame AA i U DEE ARC MACHINES ws an se 1094 LII Ol A e lt En krw lt ew amp E py amp L JRG No D12794 Sht 4 ot 4 Va IWAIT 1 134 n RN1 N 150R AT REV5 PH 12V Va mane q EREADY 1 EE Y READY1 2 W 2 REV S XCLK gm L GH 7 rev 3 R y 07 Y 32 RDY DIRC 2 2 26 TRO REV 3 RDY ne H LS HLD aa g EE SO DER REVS BHHz ps A IWO RAWREAD 32 30 RDD REV 3 XRDY DA N 3 AD WG INDE X 32 N BINDX BINDX 1 039 meseta 52 rpcEN STP SECTOR 22 4 BSECT p2 HEADS READY a O 2MHz 7 MONO Do BINT XCK5 IC 31 ROATA Zo mad REV 5 XRDY 1415151 RCLK REV 3 ROY LK6 WHEN USING SMC CHIP 4MHz So 1 DRV2 Kee CUT LINKS 7 8 4 5 Gel vs READY1 La a MONOS lol XRDY sun 19 Cr BG b 1 monos 2 LINK PINS1 amp 2 WHEN USING 8 DRIVES amp BASF mal lt INTRO 39 5y DRIVES LINK PINS283 IF USING YDS DRIVESJ R pag CB Le Aa ER e dah oes asin whch HA AAA P yq LATE E
27. 5 This sheet shows two dedicated ICs and a CTC BS is an IEEE interface controller enabled by IEEEEN from the main PCB for programming and provides all the control functions necessary for the interface Processor interrupts are generated via the CTC channel 0 The IEEE address can be read as a status in HRG port 0 RD0 AQ and BT are interface buffers BU is a maths IC providing maths functions vith a minimum of softvare Processor interrupts are generated via CTC channel 1 The CTC 9511 EN is a shared group of ports and chip select is controlled by A2 CTC channels 2 and 3 are used as a real time clock Ch 2 provides interrupts every 8ms if required Ch 3 counts the outputs of Ch 2 to generate interrupts at 1 second intervals so that the processor can update the time counter in main memory 4802 Power Supply SECTION 4 POWER SUPPLY GRESHAM LION TYPE 32047 This is a copy of the technical description supplied by Gresham Circuit ref Gresham Lion Drawing No 320470 1 030 GENERAL The mains input is rectified and smoothed to give a nominal 320V d c supply This powers a single transistor flyback converter operating at between 30 kHz and 100 kHz depending on output loading Regulation of the main V rail is achieved by opto coupler feedback controlling the on time of the converter while the 12V and 12V rails are controlled by low drop series regulators MAINS FILTER AND RECTIFIER RFI generated by t
28. DIL switch 3 3 MA 17 DIL switch 2 2 MA16 DIL switch 1 1 MA 15 DIL switch 0 0 MA 14 On writing to port 0 the least two significant bits in the B register contain the address within the lookup table to which the data is written Port 1 NUM A Read Bit Write Network 7 Network Network 6 Keyboard Reset Network 5 Soft UHAND3 Hard USERIO Ready 4 Soft UHAND2 Soft UHAND 3 Soft UHAND1 Keyboard Ready 2 NMIEN Frame Blank 1 Page 1 Line Blank 0 Page 0 515 4802 Fault Diagnosis Guide Port 2 Read Bit Write JB2 7 80 40 Select JB1 6 ALT CHAR SET JT1 5 LSPEAK JT2 4 JTRIG SIO2 RXD 23 SIO2 TXD SIO2 HAND 2 CASM2 CAS VOL 1 CASMI CASS IN 0 CASVREN e Port 3 Read Keyboard data Write D A Converter CTC USAGE CHANNEL 0 SIO4 clock Input 2MHz Clocks suitable for all baud rates from 110 to 9600 may be obtained using 2MHz in counter mode and a 4MHz system clock in timer mode CHANNEL 1 Timing Input 125KHz Provides frequency generation for the cassette system and can be used for general purpose timing CHANNEL 2 Keyboard Input keyboard strobe Generates interrupt on pressing or releasing a key CHANNEL 4 Repeat Input Frame Blanking Generates interrupts for repeat key SIO USAGE CHANNEL A Netvork CHANNEL B SIO4 RS232 Port vomitum ra 4807 Fault Diagnosis Guide DIAGNOSTIC ROUTES Faults in the 4807 can be broadly categorized as follows 1 Those faults which allow the processor and
29. HZ for medium resolution and 8MHZ for high resolution Each pixel value is input to the programmable lookup table as LAO to LA3 so that each value 0 to 15 may appear via the DAC as any intensity from O black to 255 white Although only LAO and LA1 are valid in high resolution mode 2 bits per pixel the action of the shift registers causes spurious information to appear at LA2 and LA3 and the lookup table must be programmed to ignore these Lookup table outputs are clocked through ES to the DAC which produces grey scale graphics at DACOUT ES is disabled during line blank field blank and in extra high resolution mode The lookup table is programmed by latching the required eight data bits in WRO normally the Y address then setting the address to be programmed in the lower 4 bits of WR2 During field blanking this address is enabled through to LAO LA3 EV and DV outputs are disabled by FBLANK at which time LKWR in WR2 may be activated to load the register Note that LKWR is used as a strobe on the register write lines and must return to its high state while address and data lines are still valid The 16MHz signal from the main PCB is used to clock the HRG timing chain which is further synchronized by using EOC This allows graphics and text to be mixed if required During normal screen refresh data is read out of HRG memory by 2MHZ one byte every 500ns which is also used to generate VRAS HLOAD is used to synchronize loading of
30. K FOR 2764 OR WR LINK FOR DEVICES AS Vct Vcc Va Vcc SHOWN Ma WR ROMOLA ROMOLB Hp BI rome IPnito Pal DEVICE een LEI 2565 e a AT ON BCARD EPROM ME Sh tar 5 2516253272716 A6 AB m NS 1 47 AB PHI E HK4802 1 WR 2764 el 2171260 7 Ac 1855666 EN AS A9 d ROM LD B 253212564 RAMLK LK1012 2 12716 25 12732 AL o AL ap ROMOLC ROMOLA R ROMEN 10 12564 A3 RAMEN EI A3 ROMEN WORKING mm ee A2 A10 AN A2 A10 INUSE A RAMEN Al ROMOLD Ao D7 A0 07 ENCOMP 09 D6 DO D6 ENCOMP D1 05 01 1 05 DOEN D2 Di 02 D4 DDEN D3 D3 BINCH Vcc BINCH 07 TORQ SEN MIT gt 067 MREO BOINT PHI en lt 2 WAITO WAIT r os In DE WR CTLWR ROMEN Ta gt Vec gend pu 139 mnp RD _ DWR u ENCOMP EARLY 7415377 mi T D3 DR3 A15 DRD Se Jawa Ao va p JFDCWT MA 6 ORI Alh DSTRD BEE 05 NT i ss 01 amp 2 081 A13 FDCEN 3 2 H DWD 00 DRO A7 RAMEN INTRO 6 FDCWT DRA 41 36 P 11 A3 ROMEN DSTRO ol CTLWR A2 Ao IC N DEVICE IWD I 40 O TP6 2 15244 B 7416 ENCOMP 29 Sf 1 R 35 71500 Hm id 36 1527 I 1509 UNLESS OTHERWISE STATED ASSUME ANGULAR TOLERANCE 1 2 WHOLE UNITS 1 0 mm 1 DECIMAL PLACE t 0 3mm GEOMETRICAL TOLERANCES SEE 85
31. SANSTA n E Qu A A menung ad o s emm w el iL DT LH osaw NIWYN Siv dv 2375 2 2 7 4802 Main PCB SHEET 3 This describes the regulated DC power entry to the board 9V is developed onboard from 12V as is 5V from 12V both being lov current requirements There are two banks of RAM on the main PCB and a further two on the option PCB Each bank can contain either 4116 ICs 16K or 4164 ICs 64K and link pads are provided to cater for the different pin reguirements A 64K system may consist of 4 banks of 4116 or 1 bank of 4164 and memory may be expanded up to 256K Different firmware and mapping PROMs are available to suit the different options Four ROM sockets are provided enabled by ROMOEN through ROM3EN from the mapping PROM and most types of ROM or EPROM can be accommodated by altering the link pad BASIC in ROM is available as an option with its associated firmware and mapping PROM A similar range of ROM EPROMs be accommodated in the character generator position making a variety of character fonts available to the video circuitry SHEET 4 The video circuitry is dual mode i e 40 or 80 characters wide by 24 lines It is selectable by software using write port 2 For clarity 80 character mode will be dealt with first 80 Character Mode The 16MHz oscillator is used as the dot clock for video output and is divid
32. T button signal is gated with R3 part of the row counter in video circuit which happens to be a convenient frequency and synchronized with M1 This results in RESET being active for 128us and inactive for 512us while the button is pressed allowing sufficient time to 4802 Main PCB refresh the whole of memory 1 ML SYDOTI pue eT242 LW oTSeg Ti 2 SANTA n LIVAT 10 D i9 LW daywz 29vn42 99vn0A 912012 HU k KT AKS EI I ZHW 9 ZHW 91 2 2 4802 Main PCB Burddey 3104 Z Z sandra tv y N3sN901 N3 Lu Od N 39wH WONG BETSTL Tonpu jou s d rox aro umoys cqus1uo 2 4802 Main PCB SHEET 2 JV is the memory map PROM that decodes the top address lines to enable RAM or ROM during MREQ cycles It functions in the same way as the port mapping PROM This map can be modified by signals PAGE 0 PAGE 1 and ZRD so that the monitor program appears at address 0000 after a reset during memory read this is necessary as the 280 always looks at 0000 for its first instruction after reset During initialization PAGE 0 and PAGE 1 are changed by writing to port 1 so that in normal operation RAM appears at address 0000 as required by CP M ER is a 4 x 4 bit register used for RAM mapping in a similar way to JV except that it can be altered under software control by writing to port O0 Figure 2 3 shows the operation of ER The contents of this r
33. als During I O cycles lines A0 to A6 contain the port address and the most significant lines A2 to A6 are decoded by JS the port mapping PROM when enabled by IORQ In this system the 280 operates in interrupt mode 2 and no port is enabled during interrupt acknowledge cycles as the interrupting device is automatically enabled by the combination of ZMI and ZIORQ being active Figure 2 2 shows the operation of JS If the group of system ports is selected PORTEN low the address is further decoded A0 A2 by CU and DR giving 5 read and 5 write ports which are used for control and status information etc as shown on sheet 5 The Z data bus is used directly by ROM and RAM and is buffered to give a T data bus when TDBUSEN is active This is used mainly by I O ports and is further buffered by DQ write and CQ read for use by VDU circuitry When NMIEN goes active by writing to system port 0 an NMI will be generated during the eighth successive instruction This is used by the ROS monitor for single stepping through programs The power up circuitry 23 GW etc holds the CL line of GU low and so holds RESET low until the power rails have stabilised Memory contents can be corrupted during reset in two ways 1 While RESET is active no refreshing takes place 2 If RESET goes active during T3 of an M1 cycle a short MREQ pulse can be generated vhich may destroy data Thus in order to preserve memory contents the RESE
34. aphics circuitry on the option PCB and allows mixing of text and graphics on one monitor this can be disabled by software DIM indicates that the character displayed is one of the grey graphics symbols 70 BF H and reduces the amplitude of the video signal A modulator is also included to produce a UHF output 2 13 4807 Main PCB SHEET 5 This sheet shows all of the system ports except write port 0 the mapping register sheet 2 The group is selected when PORTEN is active and the separate ports are decoded sheet 1 Data transfer is via the T bus which is enabled by TDBUSEN at the same time as PORTEN is active Read Ports Read ports 0 1 and 2 are 74LS244 buffers enabled directly onto the bus and are thus time dependent e Read port 3 is a latched port used for keyboard data KBDSTB clocks data into the latch and generates KBDREADY which inhibits further data strobes from the keyboard KBDREADY is available as a status bit in read port 1 KBDSTB1 goes to the CTC sheet 6 to generate a program interrupt The monitor program reads the data during the interrupt service routine and stores it in a buffer area of main memory for later use by the user program Reading port 3 clears KBDREADY and allovs the keyboard to send further data e Read port 5 is also a latch and is used as the parallel input USTBIN clocks data in generating UINRDY which is available as a status bit in read port 1 along with its associated hands
35. d to two op amps the first checks the amplitude against a reference and outputs signal CASVOL to read port 2 if the volume is insufficient for reliable reading the second one squares the sine wave input to give a TTL signal CASIN on read port 2 Another amplifier circuit is included to drive the internal loudspeaker This is fed by LSPEAK write port 2 enabling the program to generate a tone in the speaker The amplifier can also be fed from the DAC sheet 5 to produce sounds at various intensities 2 15 4802 Option PCB SECTION 3 OPTION PCB Circuit ref D10830 Sheets 1 to 5 SHEET 1 The two extra banks of RAM sockets are shown which as with the main board can be linked to accept either 4116 or 4164 ICs This allows memory to be expanded to 256K High Resolution Graphics An extra 16K block of memory is included on the option PCB which is dedicated to graphics This is configured as 192 rows each with 80 bytes and allows pixels to be plotted on the screen using X and Y coordinates The HRG memory is separate from main memory and is accessed via the HRG ports 4 read and 4 write There are three levels of resolution selectable by software 1 Extra High Resolution In this mode each of the 80 bytes per row represents 8 pixels giving 640 horizontal x 192 vertical pixels on the screen Each pixel can have only two possible values 1 white or 0 black 2 High Resolution In this mode
36. data into the shift registers The line blanking signal LBLNK is taken from the main PCB and used to generate VMEME the signal which enables the CPU to access HRG memory In 80 character mode VMEME is delayed by two extra clock pulses again to provide text graphics synchronization FBLNK from the main PCB is 3 6 4802 Option PCB gated with LC6 and LC7 to give FBLNK and is used to reserve the bottom area of the screen scan lines 192 239 for text only BLANK is a derivation of FBLNK and is used to disable the lookup table outputs high and medium resolutions during line and field blanking this signal is always in extra high resolution mode 480Z Option PCB 62ans 16 AHZ Extra High Res Pixels 125ns 8MH2 4 High Ras Pixels I Medium Res Pixels Figure 3 3 HRG Modes 4802 Option PCB N33498 AVOWIW UOTINTOSIN UBTH PIIXA Pre eanbty Mm uv 2 gt LNO SIVIH Law afus afrys as afrus ans afrus afrus Fee EEDE tit mm F o Ek L 2 LOW afus 3 9 4802 Option PCB uoT3nTos u U TH ert Sandra i 9 afus afus z dus o daw peo gene uang en IVI OVI 3 10 zxw8 afus 4802 Option PCB uoT3nTos q unrpew 9 dus pue 3 11 DIRECTO A MOURW 4802 Option PCB SHEET
37. ed into character cells by JP which also outputs the 4MHz system clock This counter is preset to 8 and then incremented to 15 whereupon EOC end of character goes active and 8 is reloaded on the next clock pulse EOC occurs every 500ns and clocks IP to produce a character count of 0 to 127 although only 0 to 79 represent valid addresses This count takes 64ns i e one line scan time for a VDU and is fed to PROM GR which maps out the line waveform as shown in Figure 2 5 To restrict the number of lines of this PROM CO is not used and C6 is routed via HP i e the PROM receives even addresses 0 to 126 This PROM outputs LBLNK to give a blank area on both sides of the screen and line sync pulses The LCLK output clocks the row counter HR giving line slice counts O0 to 9 These are fed to the character generator IC to select the appropriate character slice R3 is a convenient waveform active 128 us inactive 512 us for use in the reset circuitry sheet 1 The falling edge of R3 clocks IQ giving line counts to 31 of which 0 to 23 represent valid data addesses The field waveform is mapped out by PROM HQ in the same way as the line waveform Output FBLNK1 blanks scan lines between text lines by 4802 Main PCB inhibiting LOAD to the shift register and FSYNC1 is the separate field sync output FS is fed back to GR which in combination with LSYNC1 generates mixed sync MSYNC and is used to produce the composite video
38. egister will vary depending upon which type of RAM ICs are used 4116 or 4164 Lines MA16 and MA17 define the physical bank of memory and are decoded by JT to generate the appropriate R RAS during MREQ cycles RASO and RAS go to RAM on the main board and RAS2 and RAS3 go to the option PCB Lines MA14 and MA15 are used when 4164 64K RAM ICs are installed and they select the required 16K block within a 64K bank The Z80 can only directly address 64K of memory 16 address lines and so it is the responsibility of the program to change the contents of ER to make full use of 256K memory if this is installed MR KR and HT are used to multiplex 14 address lines into 7 pins on the dynamic RAM ICs 16 lines into 8 for 4164 s and HT also generates CAS Figure 2 4 shows an MREQ cycle involving RAM this is started when the 280 puts a valid RAM address onto the bus which is decoded by JV to give RAMEN Address lines A0 to A6 and MA14 are connected through the multiplexers to RAM i e the row address When MREQ goes active JT decodes the top two address lines and generates a RAS on the appropriate bank At the start of the next clock cycle the multiplexers are switched to connect A7 to A13 and MA15 to the RAM column address and RAMEN is connected to CAS delay circuit R44 C20 After about 40us to allow address lines to settle a CASO and CAS1 go active both signals are identical and CAS 1 goes to the option PCB The cycle ends when MREQ g
39. en t i CC E L o 73 cz cn O p 3 v Oa CZ 3396 BEL ha Ce S Of 256 C7 dee Sew TA 2 1 ics 2 z Gpe SC i NZ Cro 0 0 2 1 104 COS CIOe COD zeeer ta COI O lt 3 t cre 330 rat 11 CO AJOH It cog 2 MOT 1 Rios tol SO A t 4722 220 Fst Fuse WA S ZC N Estos LIGA 2O F Faro S 20 t ESOS H 0 24 besok D zur Tego Gutt wT TOT 1 Lito REIS TOR 4702 WS TRA oua 1 TR OG zz 1 ma ej sten 1 1 TRIO 203058 801 1 d oct OC BA 1 SER vara A TOR MER 106 t EN Ict Lic Mc 296 ica 4 Mm 368L t x 210 Ly soe ik lt t i 14 Cantik or Esse g Won 1 NS CHOP Cu Rios Riit NOT PITTED i i NEP OI a 2 le gt v i AM 2009 1 1 7 6 148 2 01 DATE CHANGE LION SCALE N TITLE 320470 1 030 IT s y PART we DRAWN APP TOL or 4 35 00 ALL DIMENSIONS IN m m CARAT DIAGRAM Res CA Macnines PSU yos l i 5 1 uuus easy naa i AAA AA AA AA 55 PC viin 72 Dy s 101 4051 673 16 C2 3046 13 1 2 Ics 4013 Ic 031 109 1030 257 IG 1028 IC8 koko e e A 4
40. epa Pyf SCA H did CE SIOEN BU 1075 log mi N tSv vee ECN E gt o t Y lt 2 Date wP 1001 SE 201 705 2 0 206 Al Ad Reset CICEN _ 17 26 493 p Je 5114 Al 1 4 pg d SET A 1546 lo amp 3 Rp SUSANTI 35 y 2800 L K S EARTA Vee Cik his oe es Cik hic 2 zc bei Cik h c P zc vo1 Ci ACH SV Gx 9 K ps18 CASIN fa TOR 1 CAS 13 CAS M CAS voL 4v7 CASIN CASI REN IE VPUACC g RIT CH Td T met out RE zen RIC 3x2 l R o o Jawi TAPE EARTH rn PRA 22K 22K AMI Ko er 3t AL 4X1 aupio CIS cum RIS IKP Ind Ing T L 2 NLESS Gu p Z n DRAWN BY CHECKED BY TDRAWING no D10829 sur sors 4444 D a 7o eyil 604 2 9p 60 4 4 on VH TAC l cl CTO m pe ag 2e Ze GER jus me wem oe we wm em ol C 8 10 V sii u Dv wad y 50 ATED V li o Pu PAANS 31 T 35 17 D4 ERA CEE TA 12 TIsotavrp BYV ISA 12 NI 150 12 x Sv IsosaTEb gt 2 4 222 72 12v wow xsosATE D 50v TILIN n
41. er Snubbers Secondary Operation Switching PSU Load Box Keyboard Timing Basic M1 Cycle and Clocks Port Mapping RAM Mapping RAM Access Cycle Line Waveform Video RAM Video Timing Writing to HRG Memory Memory Re mapping HRG HRG Modes Extra High Resolution High Resolution Medium Resolution Power Supply i 4802 Service Manual 1 1 2 8 2 13 2 14 2 14 4802 Keyboard SECTION 1 THE KEYBOARD Circuit ref Alphameric Drawing no 146 1710 There are 64 keys each generating a distinct 8 bit code not ASCII whenever it is pressed or released accompanied by a strobe pulse In fact only 6 bits are used with bit 8 indicating key position 0 down 1 up The keyboard consists electrically of an 8 x 8 matrix which is scanned to check key status up or down This scanning is accomplished by 3 IC s 1 IC 8 is a 12 stage binary counter clocked by oscillator IC5b IC6a at about 500 kHz The clock is divided by 8 Q0 01 and Q2 are not used and then again by 8 Q3 Q4 and Q5 are used for strobe functions to give a 6 bit key address count which is placed on the data bus This forms part of the data byte sent to the processor and is accompanied if a key has changed state by a strobe pulse and DEPRESSION signal 2 IC 7 is a decoder which takes the three most significant bits of the key address and enables the appropriate row of the matrix provided that the D input is low As D i
42. es within a bank of 64K RAM is to be used This allows any of the Sixteen 16K pages to be mapped into any of the four 64K pages of processor address space The RAM mapping is controlled by writing to port 0 see later VDU The VDU is transparent for both reading and vriting except that one vait state is added to all accesses The VDU is svitchable under softvare control betveen 40 and 80 characters Hovever the screen contents will be jumbled on changeover and so the screen should be cleared first The VDU is mapped as I O ports and should be accessed using IN r C OUT C r OTI OTIR INI INIR In all of these cases the value in C vill be the Y coordinate of the character on the screen range to 17H and the value in B vill be the X coordinate range 0 to 50H Character 0 is at the top left The value in r vill be the character output from reading back the screen Characters 128 to 191 are dim KEYBOARD The keyboard is of the key dovn key up variety This means that vhen a key is pressed or released the keyboard generates a character The keyboard will return an 8 bit number of which 6 bits identify the key a seventh bit is available for future expansion and 1 bit identifies the direction of travel The number has no correspondence vith ASCII SHIFT CTRL REPEAT etc are treated as ordinary keys The decoding of function keys including the REPEAT key is done under softvare control A keyboard ready bit is avai
43. hake UHIN1 INRDY is a status signal going back to the inputting device which goes low while data remains in the latch and is reset to a high when the port is read Write ports Write ports 1 2 and 5 have latched outputs e Port 5 is used as parallel output with its associated handshaking signals UHOUT1 3 from write port 1 Write ports 1 and 2 contain various control signals all of which are cleared during reset This is important as the keyboard must not be allowed to generate an interrupt until the CTC has been set up and so KRESET remains lov until changed by the initialization firmware Another important part of the power up procedure is that PAGE and PAGE 1 are lov to enable the Z80 to fetch its first instruction from ROMO at address 0000 memory mapping sheet 1 During initialization this is changed so that RAM is addressed at the bottom of memory NMIEN is used by the monitor for single stepping through programs and enables an NMI to be generated sheet 1 80 40 selects the screen format and ALTCHR goes to the character generator sheet 4 to select one of two fonts Write port 5 is a DAC the output of which can be connected to the loudspeaker sheet 6 and is available as ANALOGOUT The SIO2 interface is software controlled using port 2 read and write CR provides an interface for joystick potentiometers for games etc The monostables are triggered by the program via HTRIG write port 2 and 2 14
44. he current through TR2 oscillates in anti phase and an amplified 500 kHz signal appears at the collector C1 prevents the oscillation from affecting the base of TR2 During negative half cycles C3 pulls the emitter of TR3 lower than its base held by C4 and it then starts to conduct charging C3 During positive half cycles the charge on C3 flows through D3 TR3 now turned off to carge C4 and provide a base current for TR5 Thus TR5 collector is low Once a key address has been set in IC 8 some time elapses to allow a charge to build up on C4 if the key is pressed see timing diagram figure 1 the state of TR5 collector is then clocked into IC 3a The output of this represents the state of the key and forms part of the data byte sent to the processor as DEPRESSION At the start of each key address cycle the Q output of IC 3b turns on TR for a short period to ensure that no residual charge remains on CA from the previous cycle As the keyboard must only generate strobe pulses when a key changes state some sort of memory is required this is IC 4 a 64 bit shift register At the start of each address cycle the state of the previous key latched in IC 3a is clocked into IC 4 an action which continues as the keyboard is scanned Ae IC 4 is clocked the state of the currently addressed key during the last scan appears at the output and is compared with its present state by IC 5a If a change has taken place a strobe is generated near t
45. he end of the cycle by IC 6b and IC 6d Holding RESET low has the effect of clearing the shift register to all 1 s and not allowing any key depressions to enter IC 3a Keyboard scanning is inhibited as are strobe pulses by taking the READY line low stopping 500 kHz oscillator this happens automatically when the 480Z receives a strobe and is returned to normal when the CPU reads the keyboard data 1 2 4802 Keyboard PIPOJ SN 1 Sandra 290418 i HN bn ag Er oop vor aran de f n ae sat ep To Deal 8 969 q v 1 b 9591 1 1 2 9601 p l pty BEEN 1 so ro I m 60 821 1 3 4802 Main PCB SECTION 2 MAIN PCB Circuit ref D10829 Sheets 1 to 6 SHEET 1 The Z80A microprocessor is the heart of the system It is clocked at 4MHz from the oscillator sheet 4 and all signals directly connected to this are prefixed by Z e g ZWAIT To save using high speed memories one wait state is inserted in each memory cycle by GT One wait state is also inserted into each video access to be described later to make this transparent to the user Figure 2 1 shows the relationship between the various derivations of the 4MHz clock and the timing of GT All address lines go through buffers which are permanently enabled as do some control sign
46. he power converter is suppressed by the mains filter C12 T1 C1 C2 and C3 which reduces the RFI to below that required by BS800 R1 is included as a discharge path for C12 and C2 The mains input which is isolated by SW1 and protected by FS1 passes through THT1 a 70 C thermal output it is then rectified by D1 D4 to give 320V d c nominal on C4 and C5 Resistor R13 limits the switch on surge as C4 and C5 are charged initially The series choke L2 and C5 filters the switching frequency current and reduces the high frequency noise reflected into the mains supply FLYBACK CONVERTER At switch on R7 provides bias to TR3 which starts to turn on Positive feedback via T2 pins 11 12 R11 R2 D7 and D8 turns TR3 on fully and the current through TR3 rises linearly from zero as energy is stored in the core of T2 To prevent TR3 from saturating D11 conducts when the collector voltage of TR3 approaches 1 5 volts and diverts current from the base of TR3 so that the collector voltage remains at 1 5 volts during the on period TR3 collector current flows through R9 and causes a voltage ramp to appear at the emitter of TR2 The voltage level at TR2 base is set by R8 and by the current flowing through the transistor of 0C1 when the voltage at TR2 emitter exceeds this level by more than 0 6V approx TR2 is turned on causing TR1 to turn on Base current is drawn from TR3 via D6 causing TR3 to turn off As TR3 turns off positive feedback
47. iC 81 C 79 1C 16 1c 67 1065 1656 v EE EE WA PUR g tv Mamas Tac Tu IAs T 78 09 9 e may 1692 ce2 Cic8o C c ice8 1067 er 1210 f meta 4 v m na 1 nu m n1 Ai a mm1Ad Ad Juf3te Mu SEE 1 21 ce E re IN 4 p 8 p Q 9 lt 2 i 1 LI 1 I 2 ME 1 LJ I 2 E i 7 Ov j M DIE 30 ena i T 9 Dj 1 T SE d N CSA C51 ej 94 D x Wl E OF ba TRB EE EE SV RE ER KY SV A12 2 27 AIL Ku ALT CAR ii 5 E Y Alg Al 2 An AI A13 20 3 126 SV al Se 3 Ab 4 25 AB Ae AB 0 CPI x D CDE AS 5 CT A9 AS As c91 SI A A DEE ee sos A CHARACTER A Cover o ver mi KI 4 007 iC 5C Ps o SR GENTRATOR CS e 1 2 A3 243 eni E LSe te LS N 1 d 2728 AZ Avo B a Q A ty 26 RE d a s i lt esi V 63 HE 10 93 _ 39 ag SAD ab COS 9 gr ic csv Bo css IDP u 128 204 268 106 SRE 8 SRL lt cse is C r gt 457 20 4 208 ZDI 205 Sa 2 u SRS Ies 57 1 65 3 j 2 204 b _ 4 L9 16 LE aan 49 1 d 763 15 1 lt 92 20 SKI 2 d 1093 JB 39 ho 38 Ju Ja 1 0 a nue X Aar OPT 990 neate PRA E DATE DRAVVN BY CHECKED BY che p SP z o H lt DRAWING NO
48. ide 4802 FAULT DIAGNOSIS GUIDE CONTENTS Page SECTION 1 INTRODUCTION 1 1 SECTION 2 BRIEF CIRCUIT DESCRIPTION 2 1 Processor 2 1 Reset 2 1 Single Step 2 1 Memory 2 1 Keyboard 2 2 Cassette System 2 3 Joystick Interface 2 3 Serial Interfaces 2 3 Parallel Port User Port 2 3 Control Ports 2 4 SECTION 3 DIAGNOSTIC ROUTES 3 1 SECTION 4 FAULT AREA CORRELATION 4 1 FIGURES 3 1 Diagnosing a Garbage Fault i 480Z Fault Diagnosis Guide SECTION 1 INTRODUCTION At the most basic level the LINK 4802 microcomputer consists of one mainboard a separate switch mode PSU and an internal keyboard An optional add on board and provision for use as a network station are also available This guide is intended to supplement the RML servicing course for a basic LINK 480Z system It serves to e introduce the 4802 with a brief functional description including block diagram principles of operation options and essential circuit diagrams e explain the problem of dealing with a non functioning unit i e one that is unable to self diagnose and methods of introducing diagnostic software via PROMs suggest diagnostic routes flov diagrams and fault area correlators conclude with experience gained on fault types and symptoms 4802 Fault Diagnosis Guide SECTION 2 BRIEF CIRCUIT DESCRIPTION Circuit LINK 4807 MAIN BOARD DI0829 SHTS 1 6 LINK 480Z MAIN BOARD MKII DI2093 SHTS 1 7
49. lable in one of the ports and keyboard strobe is connected to channel 2 of the CTC Characters are read from the keyboard port during interrupt servicing and this clears the ready flag On pover up the keyboard reset vill go active Once the CTC etc is set up and it is safe for the keyboard to interrupt this rail should be taken inactive and the keyboard vill then list all the keys currently pressed 4802 Fault Diagnosis Guide CASSETTE SYSTEM The input section of the cassette system is identical to that of the 3802 Thus there is one bit for volume and one bit for data in a port The data bit is connected to one channel of the CTC so that it can generate an interrupt Not used at present On output the final stages of the frequency generation are performed by the CTC channel 1 This is fed with 125kHz which can be divided by 26 or 52 to generate 4800Hz or 2400Hz pulses These are then fed through a divide by two stage to generate a 2400Hz or 1200Hz square wave which is filtered and fed to the cassette recorder For this signal to reach the cassette recorder the CASWREN bit must be 0 The cassette output bit after the divide by two used to generate an equal mark space ratio is readable in a port so that the output phase may be determined JOYSTICK INTERFACE The joystick interface consists of two monostables whose timing resistor consists largely of external potentiometers within the joystick These monostables can be t
50. led by RD CT is also enabled at this time and decodes the lower two address lines to strobe the appropriate HRG port RD RD3 WRO WR3 CP keeps data stable in HY until the next rising edge of 4MHZ after HRGEN and WR go high allowing the rising edges of WRO WR3 to be used as strobes When writing to HRG memory the CPU puts the Y address out via WRO and the X address out via VR1 These are latched into FW and GR respectively During line blanking VMEME is low putting the latched X and Y addresses through to the memory at which time the CPU can put pixel data out through WR3 Whenever HRG port 3 is accessed CRAS goes active giving MRAS via EQ the next rising edge of 4MHZ puts CAM and MAM low to switch the address line multiplexers GQ and FT After a short settling period governed by R11 C1 MCAS goes active to enable the RAM data lines Timing is shown in figure 3 1 During memory writes WR3 is active putting VMR W memory read write line low via EQ During memory reads DW is enabled by RD3 putting memory data onto the I bus The 16K RAM is not directly compatible with the 80 x 192 format used in this circuit and has to be configured in a similar way to the video RAM on the main PCB This function is performed by ET which re positions columns 64 to 79 i e C6 is active Figure 3 2 shows this action During normal screen refresh counter EU is clocked by 2MHZ to give the column and is reset by VMEME at the end of each
51. o MQ on the rising edge of 16 MHz i e half way through EOC and is presented to the character generator At the same time the outputs SRO to SR7 from the previous character are loaded into the shift register JQ provided that valid data exists i e LBLNK and FBLNK are inactive This data represents the dot format of the selected character slice and is shifted out at 16MHz as VIDEO Figure 2 7 shows the timing 2 9 4802 Main PCB UIOj9APM SUIT 6 eanbTa LINASW 53 194781 INASW 52 LINIE I 3757 1 2NAST Vauv vivo ol ssavaav wovd suhe prong bound sam vroa bunma 2 10 4802 Main PCB 2 69 97 KUKO XXX 10 heroes 8 291 Varo pasnun ER wes 77 YA pn 5 7 9923 v iit ha ps 000 0111001 0000001 0000110 0000000 111110 1110010 93 93 2 11 4802 Main PCB BuTuTL oepTA 2 210674 OF am perve qeuuof op Br Qu papvo 144 arar qouual qop u peu Qvo or wyop fuounu zu 19770104 BENE N ara 2 bw ann papo I ZHW9 ZHW9I 5 MO nyaron 4802 Main PCB The CPU writes to video RAM by means of an OUT C instruction using ports 0 to 17H i e one port for each of the 24 display lines An output instruction has one wait state inserted by the Z80 and one additional wait State is inserted by VDUEN sheet 1 This ensures tha
52. oes inactive H During refresh JV is disabled and RAMEN is not generated this inhibits CAS ER is also disabled allowing JT to generate RAS on all banks of RAM simultaneously As the 280 only supplies 7 address lines during refresh one extra line is needed to allow 4164 ICs to be used This is derived from the VDU line count using L which changes approximately every 1 5 ms L1 is synchronized with ZRFSH to give 8RFSHB which is gated through HT during refresh cycles this allows each half of the 4164 s to be refreshed within the 2ms limit The two latches GT and GV are included to overcome a timing restriction of dynamic RAM known as RAS precharge this is the minimum time that RAS must be inactive between memory accesses This is at its limit between MI and refresh cycles where ZMREQ goes inactive slightly after the rising edge of d 4802 Main PCB T3 clock and active again on falling edge GV terminates RAS by MRINH to JT and CAS by disabling MREQ1 on the rising edge of T3 clock so overcoming any delay in ZMREQ going high 4802 Main PCB Burddey WA g z sandra 0 Hod g buque hq powunubad 61 01957 TL LSIS vL so dura MV umoys KJU2JUO pes sf s n rar LLLIL O YUVQ veg wuog 1409 0 951 SVY 5270424290 BEISTL VIVI SIVZ 891 3 49 RM elig 191 8799796 uvg qenishug spas 4802 Main PCB EL om lt ML STOAD sseoov pz
53. of IC will be lov and the current in OC1 will be lov This gives rise to an increase in output power which tends to correct the initial error condition R102 and C101 are compensating components which stabilise the loop Inductors L101 and L102 are part of P1 type output filters which reduce the high frequency ripple at the output terminals 101 and TR102 are the series pass transistors for the regulators on the 12 and 12 rails respectively These are driven by their associated op amp which compares the rail output voltage with the 5 volt output and adjusts the drive to the series transistor to maintain the required output voltage In the event of the voltage on the 5 volt rail exceeding 6 volts approximately Zener diode D108 conducts and provides gate drive for SCR101 SCR101 turns on and crowbars the 5 volt output blowing fuse FS102 and removing the 5 volt and 12V output SWITCHING PSU LOAD BOX Function To provide an effective load on the PSU for testing and repair without the risk of having the main circuitry connected Loads on each rail are switchable between typical and maximum loads Test points are provided to quickly check the voltage of each rail and current drawn PSU Spec RAIL TYPICAL LOAD MAX LOAD 5V 2 5A 3 5A 12V 0 25A 0 82A 12V 0 05A 0 1A 4802 Power Supply ATddns P Sid 92d Nid S T sandra Ti tt O s 4 4 4802 Fault Diagnosis Gu
54. riggered by a positive edge on JTRIG and their outputs can be read as JT and 2 The monostable time constant is about 1ms centre position There is also provision for two push buttons which are read through JB and JB2 SERIAL INTERFACES There is a software SIO2 RS232 interface consisting of two bits in an input port RXD and handshake CTS and an output bit TXD There is also a hardware SIO4 RS232 using the Zilog SIO channel B PARALLEL PORT User I O Port Control Status port 5 is the USERIO port There is a hardware handshake provided on the USERIO input port Data is latched into the port on the positive edge of the strobe line and sets a ready bit which can be ready by the computer and a busy bit for the peripheral When the USERIO port is subsequently read by the computer these bits are cleared Note that the USERIO port is transparent and behaves as in a 380Z if the strobe is held low by default In addition to the hardware handshake there is a software handshake 3 output bits 1 input bit 4802 Fault Diagnosis Guide CONTROL PORTS o I O port map Device Port Address VDU 0 to 17H Control Status port O0 18H Control Status port 1 19H Control Status port 2 1AH Control Status port 3 1BH Control Status port 5 1DH CTC 20 to 23H SIO 24 to 27H Port O0 Read DIL switches Write RAM mapping lookup table Read Bit Write DIL switch 7 7 x DIL switch 6 6 x DIL switch 5 5 x DIL switch 4 4 x
55. rs Tie KI 192 34 vw UHouT 4 Denen 101 3 vin pal o fo co d MENT A IC 3L IT Vie K DY USTO IN By CHECKED BY 2k lis ka D OA gt 5 BONN eneen mn 59 2 METER 1 207 T vee KA EE EN casa 355 179 motor vA 69 229 16 29 AE S D 3 QM gun Sv fe 5 201 pe VSS Cheam 205 n oi m 9 291 in CAS VOL 205 n 363 294 17 P Dio 20 4P2 as pat T FOLNK Ja s A ZOS 23 y OT EI 0 201 CAS N Loue 95381 Zp 2 0 40 CAS N e Yeh 7 11 pian o VRA leset d KE Ctx bac 1 CAS W mn 35 29 TAPE IN 750 A 7 GED pa Me app 2204 CTCEN d EN 2 101 15 ent L 15310 4 PDA 49 Dep A AG m DAN 144 11444 YDUA RESET d cse 5 val AL QD zc To KA n C 2 x Se SIOEN JS 4 CE t R 4 IK x m1 den Lo 4q NA 1 1085 E wT o 2181 in 8 M SC C49 v E 3 Ter t Ry d ap E CTCIEO 9 G 1 Ee WAAG m E SANTI CRS Sun RT C F 00 Daas rs See N 35 1 8 TAPE EARTH Vee y UK tSv FA g
56. s connected to the 500 kHz clock each row in turn outputs a 500 kHz signal 3 IC 1 is an analogue type multiplexer each of the inputs 0 to 7 is at high impedance except for the one selected by pins 9 10 11 which is connected via a few hundred ohms resistance to the Z output Input selection comes from the three least significant bits of the key address and so this forms the rest of the scanning operation Each key provides a capacitance coupling between its row and column and when pressed couples the 500 kHz clock to the Z output of IC 1 at the appropriate point in the scanning cycle The function of the circuitry around IC 2 is to detect whether or not the selected key is pressed It operates as follows N B IC 2 transistors will be referred to as TR to TR5 from left to right e Selected key not pressed R9 and D1 D2 provide a 1 5V reference for the base of TR2 and for each of the matrix columns via Aki resistors The output of IC 1 is at high impedance and so a small DC current flows into TR1 via L1 and TR2 bases As TR2 collector is stable no current flows through C3 TR3 has no base current and is turned off and any small residual charge on C4 is insufficient to drive TR5 base Consequently TR5 collector is high 4802 Keyboard Selected key pressed There is nov a 500 kHz signal from IC 1 referenced to D2 which is amplified by the resonant circuit L1 C2 causing the current through TR1 to oscillate T
57. t a valid address on the bus during the instruction is coincident with the falling edge of 4MHz during CPUACC and is latched into KP LP and MP LP also latches the VDUWR signal to allow data on the M bus latched during CPUACC sheet 1 into the RAM During the instruction A0 to A6 contain the port number i e line number from register C A7 to A15 contain the character number from register B and the data bus contains the character from register A The CPU can read the contents of video RAM in a similar way using IN C instructions 40 Character Mode a In 40 character mode the counter JP is preset to 0 and so EOC now occurs every lus giving twice the character width of 80 mode C6 is not used and so IP outputs counts 0 to 63 in the 64us line time C0 is gated to the line PROM GR via HP and a different map is used 80 40 high to allow for the different inputs The frequency of the least significant bit of the count on GR CO or C1 depending upon screen width remains the same at 1 MHz The remainder of the counting circuitry works the same as in 80 mode and as no juggling of RAM space is now necessary CC6E is disabled by HP In this mode the shift register JO is inhibited on each alternate clock to give a half speed dot rate The various video signals generated on this sheet are mixed at the base of TR1 to produce a composite video signal Separate sync signals are made available VIDMIX2 comes from the high resolution gr
58. t falls to zero before the collector voltage has reached a critical value approximately 400 volts This is accomplished by diverting the current vhich is floving in the primary inductance of T2 into C10 via diode D13 R10 allovs C10 to be discharged without subjecting TR2 to a high pulse loading At turn off the collector voltage of TR3 could rise to a high value due to the leakage inductance betveen the primaries and secondaries of T2 but this is prevented by a clipping circuit D22 R12 and C11 The voltage on C11 is approximately constant during each cycle at the required maximum TR3 collector voltage If the voltage exceeds this value D22 conducts and the resultant energy stored in C11 is partly fed back to the supply and partly dissipated in R12 M i SECONDARY OPERATION When TR3 turns off all the secondary diodes conduct and pass the energy stored in T2 to their respective capacitors C104 etc Because these windings are closely coupled the voltages on the capacitors are proportional to the turns ratio of the secondary transformer windings The 5 volt rail voltage is monitored by IC via R104 IC contains a reference of 7 1 volts nominal on Pin 6 and this reference is divided by RV101 and R105 to give 5 volts at Pin 4 the inverting input of an amplifier Pin 5 is the non inverting input and Pin 9 is the output of J M TG 4802 Power Supply this amplifier If the output voltage is low the output
59. via T2 R11 R2 D9 and D10 keeps TR3 off The negative voltage 4802 Power Supply a applied to D5 cathode charges C65 to provide a negative auxiliary supply which is used to turn off TR3 and bias TR2 base As TR3 turns off its collector voltage rises until it is clamped by the secondary windings of T2 Shortly after TR3 turns off TR2 turns off due to lack of signal input and the charging of C9 TRI then turns off as well and C9 resets to its normal level ready for the next turn off sequence The collector of TR3 remains high until all the energy stored in the core of T2 has been discharged into the secondary circuits When this is complete the collector voltage of TR2 starts to fall at a rate determined by the snubber components and the primary inductance when this voltage is equal to the supply voltage a new cycle is initiated via R7 as before If there is no feedback signal via OC1 the peak current at which turn off occurs is determined by the voltage on the negative auxiliary rail which in normal operation is approximately equal to the breakdown voltage of Zener diode D12 When turned on or off and under secondary short circuit conditions the voltage on C6 is reduced due to decreased drive from T2 The peak collector current is therefore reduced to ensure reliable operation under all conditions SNUBBERS Vhen a high voltage pover transistor is turned off it is necessary to ensure that the collector curren
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