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SERVICE MANUAL LCD DISPLAY LCD1550X

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4. To DVI D Sub connector PWB MAIN block diag ram A A Video clock Panel clock I r I To panel module eee geese DVIA RED R IN1 16 5 _ R IN2 o AD 8 16 DVI A GREEN gt a gt 7 gt sbit x2 I G IN1 u DVI A BLUE gt PO gt AD 8 8 G IN2 g 16 Ges a 5 gt x 2 BNI a 2 8 I 1 O AD a D Sub RED 1 gt B IN2 o gt 2 D Sub GREEN e l i i gt 0 D Sub BLUE ASIC gt QVD M64539FP MAURICE2 gt QHD Microcomputer EE rocompl SEL 1 DVIA SEL 2 ki 2 QVD M 9 XIN A VSYNC H SG 5 FS 2 0 I gt synchronization separation x I SEL_HS1_GS I C S H1 gt LPF gt 5 V1 I 5 S G I I To SW board 5 9 Vi I LED_P_G 2 LED_P_G D Sub HSYNC LED_P_U r gt LED_P_U 8 D Sub VSYNC SW 7 0 5 swr7 0 SG I L _ synchronization PO separation SEL 52 052 C S H2 gt LPF gt 5 2 I I S G H2 I I gt LPF gt S G V2 I I DRIZ 0 8 DVI RX2 gt TMDS 2 SCL I DVI RX2 recei
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7. 1531 Gy 1531 1 ty AGSIANVd AST3NVd ev AS T3NVd uolo uuoo 4 JASTANVdI S 0 00 9 dOd 66 L 00 L 200 8 dOd 46 00 6 GND 95 vH SE 00 dOd re S 00 L dOd 66 9 00 4H 209 QNO LE GND 09 GOd 06 0 20 Add 06 0 LO L GND V so 62 62 L 20 IH Add 62 LO 2 ONASH V 0 82 82 Add 82 219 anid v 20 22 29 z ZO Add 22 10 Y v _ 20 92 GND 92 GND GND 92 GND G G3H v 19 SZ PD Se Add Se y LO 9 70010 vz GO ve S 20 GY Add vc S LO L 40010 OXH 62 90 62 9 zo Add 62 9 LO 8 GND 22 29 22 229 LH Add 22 110 6 Le GND 2 GND QNO te GND OL ON 02 0 ro 09 3 02 0 LL 61 La dOd 61 L tO LO Add 61 50 21 ana oxu 81 8 270 Add 81 260 oxu LL dOd 41 to 11 bl ON1dLH 9L QNO 9L QNO QNO 9L GND SL GND GL vH SL Y YO Aad SI 9L OGAS bl 004 1 6 GO Add vi 6 LL ON L 9d L 9 vO 95 A3d L 9 20 8 ON 21 7 8 GOd 270 Add ZL 1 60 61 LL GND LL QNO GND LL GND 02 N3au5 ixH 01 ON 01 Add
8. lt INOH49 ra I ot A LNIOT ra N Y d 82 lev xu 82 e lev 2 NI NOISN3WIG 8 1 37725 NMOHS 40109 14989 TVIH3LVIN HO 80100 NOLHV X0SSLGO I v9 bi NOILVOIJILH3O 40 MHVW 3009 301AH3S lt LNOdd gt 105659608 uonensiGanonpoud ye 33npoad anok 1235152 s4340 eads 1340 3noqe uiea 021 131 20109 anal 9215 ajqemat O GI 9010 31 XIGWVY HLIM XoSSt 9 1 _ 25 yanpoud ANOA sajjo oads ynoge Weal JOMUOW 131 141 2010 9215 ajqemat O GI A9010NHO3L XI8NV HLIM 0891491 ou snnw m e 15 nusjuo3 IIN OUL JAN 9909494519 JAN JAN JAN uo INES j A49010NH231 XISWV HLIM nad puras aant sipuey an quessney uawop no zuessney o nd ed a42n0 PNO anasusose 39 3502 29 ans Jo pue p Sue 077 ap ne
9. 65394909 ON b ede JON 65394909 95 Bada soedS 664GO00 664GO00 ON A3H I8PON SWEN JOPOJN See Wa 022500 98750 8 90000 LLCS NS OF ON 161495 XOSSLGO l dL Nd 65394909 SWEN 65394909 ee 4S 6 4009 Mm T JO 1002 8PpOW AION 30044 cL L0 Uluoj dO AV1dSIQ SOINOHIO3 T3 IHSIBNSLIW D3N 0 I HOHESMISSEIS IHSIENSJIN DAN 0 00000 ur RD MA UE EM ON WIGS i NI NOISN3WIG 06 HL TIVOS MOV I8 90109 ONIYSLLAT JLIHM 90700 MOVE 4 09 HV8 XOSSLQJT MultiSync LCD1550X User s Manual U ivatelsk priru ka Bedienerhandbuch Odnyies Xprjons Manual del usuario Manuel Utilisateur Manuale utente Gebruikershandleiding Podrecznik uzytkownika Kullanici Klavuzu ru ABU EST Declaration Declaration of the Manufacturer We hereby certify that colour MultiSyme LCD1550X LCD1550X is in campliance with Council Directive 73 23 EEC EN 20950 Council Directive B9 336 EEC EM 55022 EM amp 1000 3 2 EM 61000 3 3 55024
10. dE i 2508 AHNLVHAddNAL 2 M AOS 0S 000 ALINEV S L3M9Vf 318VO IVNDIS X0SSILGO 1 912 01 014 4 uio tustqns3luau MMM 19161 suayo el2 ds 3noqe OL 9010 31 XIAWV HLIM xoS51021 JU SHINW IVANVW 5 4350 NI NOISN3WIG SIN FIVOS MOV18 90102 DNIHALLIT 3LIHM H3dVd ATOAO3H TVIHALVW yous 5 5 445 X0SSLGO I vLL GiH dvdd INOH4 SAV 1dSIQ LIVULUOd SAWIdSIQ LIVYLHOd M3TAGINOIT HLIM V W4U388 U S343 YNOA 3AT9 17 DISPLAYS Easy tous Liquid ent LIQUIDVIEW TAKING THE STRAIN OUT OF SMALL ICONS Ge pinbr NOILIGNOO TVNId Och Standard Desktop and Application User Interface u LiquidView icons test and gagi are smaller at high resolution Surface de bureau standard et interface utilisateur pour les applications LiquidView SAV Lesic nes le tent et ks graphiques sont plus sur un eran haute dition LIVHLHOd Standard Desktep und Amwendungibenutzeroberflche c LiqudView
11. u COM Pin No Signal name Function Remarks 62 EEP_SDA Initialization EEPROM communication data 24LC64T I SN 61 EEP_SCL Initialization EEPROM communication clock 24LC64T I SN Function This is an interface with the initialization EEPROM 1C100 and the data is read written with 122 communication The microcomputer IC102 has two I F ports of bus DDC communication is carried out using these ports This LCD monitor has specifications to support DDC2BI DDC CI and is adjusted to the DDC CI I F specifications as the default The communication speed is 100kbyte sec max 61 IC100 22 scL EEP SCL 24 ceaT I SN 62 23 SDA p DDC SDA EEP_SDA IC102 MPU 1 28 1 5 3 EDID data write protect control function List of control signals u COM Pin Signal name Function Remarks 37 MP EDID data write protect setting Lo Cancel Hi M24CO2WMN6T 43 P IDO LCD panel module setting Pull up Pull down 42 ID1 41 P 102 40 P ID3 Function An EDID data write protection function is provided to prevent the monitor s EDID data from being damaged by an external source However to enable writing of the EDID data in the production process the EDID data write protection can be set or canceled only when the monitor power is ON by using the DDC2BI or DDC CI function with the DDC comm
12. 13 SUEDE SIME M E ce Ud 13 J Drop Tiel L reed ene eL cro eed 54144 epe ute fa id a 13 A GD Piel etti A Pete ee eL eara eR UAE EE Rena Eee de PR MIR Pd de RR 14 STET LOD Panel SDOCHICIHIOoIS OA en ARR Ub A 14 o2 Daler Serate and DUS MERE 17 O EE SEA EEE E a E 18 Te E 22 Appendix Preset Signal Timings eee eee eee eee aaa aaa aaa aaa n nsn 23 Appena U Rif RHET 24 Appendici Preset Timing CHAN ao rr tn e eter tae eine a cae ee du erue eat iR LR kukaa 28 Append N bt qe Rue 29 Attached Fig 1 Fig 13 3 Document No VSPF A028 1 Foreword This specification defines LCD1550X 15 0 TFT active matrix LCD monitor LCD1550X color monitors wide compatibility makes it possible to upgrade adapters or software without purchasing a new monitor The LCD1550X color monitor has a wider viewing angle with XtraView technology accepting analog signal inputs the LCD1550X color monitor can display an 16million of colors depending on the graphics adapter and the software being used The LCD1550X color monitor is designed to meet AC 100 240V input The LCD1550X color monitor is microproce
13. 2 7 2 7 Configuration of DDC EDID 2 8 2 81 ott a B RE e datus 2 12 2 8 1 Electric 2 12 2 8 1 1 Confirming the operation of operation 2 12 2 8 1 2 Frequency change 2 12 2 8 1 3 Confirming frequency range Confirming preset timing 2 12 2 8 1 4 Confirming automatic adjustment function ss 2 12 2 8 1 5 Confirming composite sync 2 12 2 8 1 6 Confirming Sync On Green signal 2 12 2 8 1 7 Confirming digital input anna 2 12 2 8 1 8 Confirming D SUB input connector nn 2 12 2 8 1 9 Confirming power management function nn 2 13 2 81 10 Isolation voltage is vase oett ciet ee nete ete Pv d eden 2 13 2 8 1 11 Ground resistance snanar nanna 2 13 2 8 1 12 Shock test uoto RE rte I re SURE 2 13 2 8 1 13 Confirming color selecting AccuColor function 2 13 2 8 2 Picture performance ddr etie tet tt i e ai ne Ee tds 2 14 2 8 2 1 Picture performance inspection 2 nn 2 14 2 8 2 2 Confirming color coordination nanna 2 15 2 8 2 3 Panel inspection luminance color coordination defect 2 15 2 9 Liquid crystal display defect 2 16 2 9 1 Condition of appe
14. 2 881 OV 1 ALIIIBV P AVHD LHDIT HO100 LHAOVT 3215 318VO L ados HHMOd X0OGGSIGO I 1 6 014 9 7 068G 0S NOILVHOdHOO SIN31SAS TVNSIA 21919919 IHSIANSLIN OHN u pejuud SI peuonueuuepun SUL O 9l 6 gu O pl 2446 gt 0L M posais oll yi fen UOISUSLUIC gt 901 wug0 0 8894 0 L puo ee b 044 u ul lod A B FL 1 0 O 8 jenos 2 O O 1 ouKs 10 ous O po pub Be 8 O Be 6 5 2 Oto puo e 1 nt 5 9150909 zo 10 U88J5 9 puo 9 9 OF 0 GO pay O A O12 2 59 UIA me 1511 DNIHIM 52 0199 euojueg 0100 SHUM 7740102 Saeed Or v ON MAHOS N MAES ol 5 c 2508 AHNLVHAddNAL 2 AOS 05
15. 0121 10824 0080 AS H3HSVM Y JINNAS 31V1d LINN 3Sva 318VO H3AOD HIMOd H3A0O 5 VS3A H3AOD l d HOLO3NNOO QV31 VSdA H3AOD q31naow ao1 044101927 MS dMd 1INN 13238 7 dO1 HOLV1NSNI WOLLOd HOLV INSNI SHEET CAUTION EU Version only SIGNAL CABLE S DVI A AC POWER CORD SIGNAL CABLE DVI D b Pa LCD1550X Packing view CUSHION SET TOP DISPLAY MONITOR SHEET SETUP PACKING BAG MASKING MASKING TAPE CUSHION SET BOTTOM PACKING CASE PACKING SHEET ACCESSORY CD ROM FRONT CARTON TAPE lt lt CARTON TAPE 2 SHIPPING LABEL FRONT 274 9 SERIAL NUMBER INFORMATION Refer to the serial number information shown below Ex Rating label Model name LCD1550X Serial No Manufactured Manufactured Year 0 to 9 Last digit Manufactured Month 01 to 12 Control Code 0 to 9 or A to Z It is possible to use fixed no for same destination if model name is same Running No 00001 to 99999 NIEC MITSUBISHI NEC MITSUBISHI ELECTRIC VISUALSYSTEMS Technical Specification For 15 TFT COLOR LCD MONITOR Model MultiSync LCD1550X LCD1550X LCD1550X BK DATE Oct 4 2001 Drawn by Checked
16. 9 0000 WSO 13534 104 1X3N Asnrav 1041802 1IX3 4 Da ACZ MOLEJIX NOLLNa WSO 19584 38V xIqwy LNaNI LXAN T38gVv 15 SNOLLNG NOLLNG LIX3 ww 9 x pz 3215 0907 3oava 21 PUASIJIW NI NOISN3WIG G L TIVOS 0620 03 H3MIS AVHD 1131 JO OSO T LNOHH NOILVOOT X0SSLGO I HOLO3NNOO HOLO3NNOO INdNI 91 680 ans a INdNI IAG HOLO3NNOO H3MOd OV CJ G 8 x Ze 371 0907 ali J 1 940 4 1OH 3901 A3 ALIWNOAS lin ji ONILVH 14dV 1 NOLLNVO DIVINOMMILS 130807 53140311 NN YW 11 V8 vdd JISHVAQV YHBALYN LLI TILL SINISNY LVGHOF TILL SVLNISNV TIWAS NALVUVAAV ONINYYA NIGNVHHOA 1V439 WI 31131 NIHVSTASHJIMSNV HAZLANAA Nad HOHNQ GNIS 53 NAN440 LHJIN LVH39 N3H3IZ NZ 35009315 SNY H3931SZ13N 430 151 ZLIN WOA SNNNN3HL YNZ 5Nf LHDV HNaLYSTIILN 1 33
17. pi Brightness Contrast Controls tt BRIGHTNESS Adjusts the overall image and background screen bnghtness CONTRAST Adjusts the image brightness in relation to the background AUTO ADJUST Analog input only Adjusts the image displayed for non standard video inputs Auto Adjust Analog input only Automatically adjusts the Image Position the H Size and Fine setting Position Controls Analog input only LEFT RIGHT Controls Horizontal Image Position within the display area of the LOD DOWN UP Controls Vertical Image Position within the display area of the LCD H SIZE Adjusts the horizontal size by increasing or decreasing this setting FINE Improves focus clarity and image stability by increasing or decreasing this setting Colour Control Systems Six colour presets select the desired colour setting sRGB and NATIVE colour presets are standard and cannot be changed Colour temperature increases or decreases in each preset English 10 10 ABU EST R Y G C B M S Increases or decreases Had Yellow Green Cyan Blue Magenta and Saturation depending upon which is selected The change in colaur will appear on screen and the direction increase decrease will be shown by the colour bars sRGB sRGB mode dramatically improves the colour fidelity in the desktop environment by single standard RGB colour space With this colour support
18. myjmim 3g 225 w UJO 2 900 442 004 02 901 442 004 02 90 442 004 02 FG801 CP246C365 02 26802 CP246C365 02 4017 ___ CP442P001 01 902 442 001 01 100 CP285P030 01 27 CH330H509 09 ________ CH330H509 09 CH600H179 09 ________ CH650H209 09 CPO81P001 01 _________ CP096P004 01 CPO96PO04 01 CP096PO12 01 _________ 96 12 01 CP210A271 01 _________ CP210B096 01 CP210B097 01 CP210C100 01 CP223B007 01 _________ CP223B008 01 ________ CP242C203 03 ________ 2420294 02 246 428 02 _________ CP246C428 03 ________ 246 428 04 ________ CP246C434 02 ________ 246 439 01 _________ 442 004 02 CP 479P050 01 5400077 01 5530007 04 5540027 01 ________ CP554D028 01 27 CP554D029 01 _________ CP580A118 01 5900099 01 164 01 _________ CP669D016 07 6690041 01 _________ CP669D074 01 _________ CP669D089 01 _________ CP669D094 04 ________ CP669D104 02 CP669D104 02 CP669D113 01 _________ 690 114 01 CP669D118 04 _________ CP669D502 02 ________ 770020 01 CP677D020 02 _________ CP680D009 01 CP775C370 03 Po 775 370 04 RATINGLABEL LCD
19. Is DC3 3V M3 3V D3 3V output from 1 of IC609 M3 3V D3 3V line may have any problem Please check the parts below MAIN Power Controller IC IC608 MAIN Power M3 3 D3 3V controller Tr Q602 MAIN M3 3 D3 3V generator IC IC609 MAIN D2 5V generator IC IC602 MAIN A2 5V generator IC IC604 MAIN P2 5 generator IC IC606 MC EEPROM for adjustment IC100 Sync D SUB IC IC303 M3 3V D3 3V Line Circuit Voltage M3 3V D3 3V Line Circuit D2 5V A2 5V P2 5V Asset 5V Generating Generating Generating DDC Detecting SW LED DC3 3V Circuit Circuit Circuit Circuit Circuit Circuit M3 3V MAIN MC generating generating generating DVI A DC3 3V Circuit Circuit Circuit Circuit D3 3V Is 100MHz clock pulse input into 12 of IC102 MPU Control circuit may have any problem Please check the parts below Crystal oscillator X100 1 102 MPU may have anypobem ____ 0102 2 Picture 2 1 Back Light Does Not Turn On POWER ON INDICATOR Green Is Blinking Is control pulse for back light output from 8 of below MAIN Power D2 5V generator IC IC602 D2 5V Line Circuit ASIC ASIC 12400 Voltage D2 5V Line Circuit Schematic Diagram IC602 MAIN ASIC ASIC may have any problem ASIC ASIC IC400 Please check the parts below back light Inverter Output Tr Q701 Inverter Output
20. Notes 6 Typical values are for Ta 25 C and nominal supply voltage 7 This parameter is periodically sampled and not 100 tested 8 Ml in the A C timing diagram refers to the minimum incremental change in the Vw output due to a change in the wiper position The MODE SELECTION for the 3 Wire Serial Interface is shown below Wiper Up Wiper Down Store Wiper Position Standby Current No Store Return to Standby 1 26 DVI SELECTION DIGITAL ANALOG SEE USER S MANUAL FOR MORE INFORMATION Key operations Selects an item downward Moves upward when at last line 4 Selects an item upward Moves downward when at top line Invalid Invalid NEXT Invalid RESET Invalid EXIT Exits the OSM menu The DVI SELECT menu for the OSM function is shown above The DVI I DDC is changed on this screen The Ch is saved in the initialization EEPROM IC100 when selected and the EEPROM IC104 or IC105 in which the EDID data for analog digital to be selected is stored can be accessed When DIGITAL is selected the DVI I D EDID data will be read in immedi ately after selection and when ANALOG is selected the DVI I A EDID data will be read in The above OSM menu will open when or is pressed while the DVI NO SIGNAL or OUT OF RANGE is displayed for OSM and the current setting state can be confirmed In addition if the setting value does not match the PC and
21. 2 BO GND G7 66 PEV G5 MO G4 GND 63 PEV G2 61 GO 5 GND PEV R7 Q3 R6 R5 05 RA GND PEV R3 PEV R2 PEV R1 RO FPC 0 5mm pitch 0 3mm thickness Port No Pin name Appendix Table 2 Microcomputer port assignment table Pin assignment U D Details DVI I connector DDC switching control signal 0 Dec digital 1 Inc analog Default value Place of use X9116WM INC DVI I connector DDC switching control signal Tap slide at each falling edge X9116WM PD TMDS receiver power save mode 0 At TMDS power down 1 When normal Sii143 SCDT TMDS receiver DE detection 0 No svnc Svnc Sii143 TMDS receiver output enable 0 At TMDS output open 1 When normal Sii143 EEP SDA EEPROM bus data input EEPROM EEP_SCL EEPROM I F bus clock output EEPROM P_ON ASV circuit power control 1 Power ON 0 Power OFF PQ1U501M2ZP PRO_DLY For inverter sequence control Inverter board P_PANEL FET SW output control for panel power 1 Output ON 0 Output OFF FET SW for panel power P_INVT Inverter lighting control 1 On 0 Off Inverter board P_SUSP1 A2 5V circuit power control 1 Power ON 0 Power OFF ASIC analog circuit P_SUSP2 D2 5
22. Tap position store 1 25 The DDC switching circuit can operate when either the A5V monitor synchronizing signal DDC system power or DVI connector pin 14 5VDC external power from PC is turned ON A5V_OR_DVI power The tap position information equivalent to DVI SELECT results stored in the X9116WM 2 7 s non volatile memory is automatically loaded when the power is turned ON Thus even if the monitor power for the asset management function is turned OFF micro computer is also OFF the EDID data to which DVI SELECT results set previously have been reflected can be sent to the PC The AC timing for the 3 Wire Serial Interface is shown below A C OPERATING CHARACTERISTICS Over recommended operating conditions unless otherwise specified Simbol P i Limits dins did Min Typ Max Units CS to INC Setup 100 ns tio INC HIGH to U D Change 100 ns tpi U D to INC Setup 2 9 us ti INC LOW Period 1 us INC HIGH Period 1 us tic INC Inactive to CS Inactive 1 us CS Deselect Time STORE 10 ms tw INC to Vw Change 1 5 us tcvc INC Cycle Time 4 us tr te 7 INC Input Rise and Fall Time 500 us tPU 7 Power up to Wiper Stable 5 us tr Voc 7 Vcc Power up Rate 0 2 50 mV ms twn Store Cycle 5 10 ms A C TIMING CS lt tcyc STORE tic tcPH z 90 90 ING 7 1096 U D Jf tw lt gt m E 8
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25. 2 H15 10W 2 7K F Vi 2 H15 4 F3 2 4 F3 AH2 1 E4 E4 gt 5 6_V2 C S_H2 1 04 1 04 g Cs L WN s L TUYN Mv L MOL L L woz X 017 A068 LZ LSH809 LH gt 25 2412 8 1 16W_0_JUMPER 5 2 g 21 WLS LLOVYL 1 16 410 1 16W_0_JUMPER 2962418 R409 100 J ne I AZIMOL L ISMN LON ezeo Lanes a 5 vi 1716W_100 SEL_HS2_GS2 gt 1 54 HS2 gt 2 615 652 2 G15 2 015 LCD1550X SCHEMATIC DIAGRAM PWB MAIN SYNC B1 9 503 J CH 816 464 ri tk CHp5V 10Q0P LCD1550X SCHEMATIC DIAGRAM PWB MAIN TMDS RX2 D gt RX2 r gt 2 A15 2 A15 RX1 r gt 2 A15 RX1 IP 2 A15 RX0 r gt 2 A15 RX0 Dr 2 15 RXC r gt 2 A15 RXC gt 2 A15
26. Power voltage 4 5 5 0 5 5 V Power current 800 1150 mA Tolerable ripple current 200 mV Maximum LCD power current value Fv 60Hz Fclk 40 0MHz full white 1 31 MSGIO lt 8670 XEJN SSO 10129105 ejqeJojo L AYO xBIN Indinonndui usamjeg JEHUSJOA LUNWILIJA A06 7 Indino 934 NOS G 1ndino A00 S dA ALL S dA 1ndino 99 00 AOL S xe 1ndino 938 AL6 S xe 96 0081 JOMOJ 10151591 1ndino 24 lLF 0589 jeddn 2015159 1ndino LH 052 10 SIS91 S EJJOA 960 AVS L ubiseq suoneoyioeds 21 dZZWLOSNLOd ASY ubiseq suoneouyioeds 21 11921 OG Od 1ndino ueis s AS G pue adAjojo d NOL AG E d OFLA 70951 20991 51920615 AL S 0 A9 0 2 S 20601 LWY AC v 0 A9 0 00751 WAJSAS 2157 N gt l 44 772 901201 Z Z INM9 l L6X AL Indino ASL Avl 0 20101 062 Neve 1ndino N G 0 NE9 26 2 001 SSE 7 OOM xe 1ndino oq od NBL 21 0 10121 d
27. The size of each point is 25mm x 25mm setting ratio luminance at point A luminance at point A 300cd m or less BRIGHT Luminance at point NATIVE CENTER 175 ormore _______ variable MAX value and MIN 5 lue Ki to 30 of BRIGHT MAX value range judgement 1 minute or more should be passed after BRIGHT was changed point A X value point A Y value The criterion of 1cd m or less are executed by the blink of the measurement value the measurement value is regarded as reference 2 15 2 Liquid crystal picture defect Input the confirmation timing with signal generator Visually check for the defects in each full mono color pattern of white black red green and blue Carry out the measurement where there is little effect from outer light in a dark room etc Criterion Must follow the details of 2 9 Liquid crystal display defect standards 2 9 Liquid crystal display defect standards 2 9 1 Condition of appearance inspection 2 9 1 1 Scope of inspection 1 Visual check must be carried out for appearance inspection 2 The inspector eye point and the point to be inspected must be located as the picture shown below 45 Appearance inspection when turning OFF the back light 5 Appearance inspection when turning ON the back light Scope of inspection Outer light Approx 300mm 1 STFT LCD module 2 9 1 2 Environment for
28. 117 ____ CP103P493 06 118 CP103P493 06 R 119 CP103P102 01 R 121 CP103P494 04 122 ____ CP103P492 01 123 CP104P003 03 124 CP103P492 01 125 ____ CP103P492 01 126 CP103P492 01 127 ____ CP103P492 01 128 CP103P492 01 129 ____ CP103P492 01 R 130 CP103P492 01 131 CP103P494 04 R 132 CP103P494 04 133 ____ CP103P497 01 134 CP103P497 01 135 ____ CP103P497 01 R 136 CP103P491 06 137 CP103P491 06 138 CP103P494 04 139 CP103P494 04 140 103 494 04 R 141 CP103P494 04 142 CP103P493 06 143 ____ CP103P492 01 144 CP103P497 O1 145 CP103P492 01 146 CP103P113 08 147 CP103P107 02 R148 CP103P491 06 149 CP103P491 06 150 103 494 04 R 151 CP103P494 04 152 CP103P491 06 153 CP103P497 01 154 CP103P497 01 155 103 497 01 156 CP103P114 01 157 CP103P102 08 158 CP103P107 02 159 CP103P491 06 R 160 ____ CP103P102 01 R 161 CP103P492 01 162 ____ CP103P497 01 163 ____ CP103P107 02 164 ____ 103 104 04 165 CP103P107 02 167 ____ CP103P491 06 169 ____ CP103P494 04 R 170 CP103P494 04 R 171 CP103P494 04 172 ____ 103 491 06 1 3 103 491 06 174 CP103P4
29. 2 ES 5 E 2 NI 4 1 H L igi RS s NET a a E gt u a 86 44 1 A068 6 x RM guo 3 Ux Dom 4 25 gt Sas V 7 3 36 MOL L 42 50 HERZ 5 5 858 2 953 E L 8 3 00 3 01 E 3 301 MOLL 0212 SZLO ZULU n ano zuo t 27100 VINO L L I l l l a 3 2 E X 9017A018 0427 91 1 5547 T RS g RS S U MGLZL gt 2 2 T 5 5 z 5 a 2 m 6 55 7 l 20 L L LAG LA n 7 z L 2 R ba 8 l 10 L MOL L 5 9 i lt 5 RPN 8 v SVGQU2 LOLHL 5 4703 878 5 DUTVC INV LCD1550X SCHEMATIC DIAGRAM INVERTER MS dMd NVHDVIQ OLLVINIHOS X0SSLGOT ONO A A e gliH4S 0098 5 Eg LOBMS L O o 9 5 811 35 208 5 E t e wo 811HMS 08MS 2 09 O MN p 13534 911HMS 9 0 MS 43MO4 ES 8 911HYS G09MS 2 4 811 5 909MS Hold S 9 8 2 g11H4S Q8MS 0 O v 2 1
30. 23 3813 1134 3NH31NI 32314 INNINV 4311109 32 SVd ZAWANOJN 300112313 JOHI NA ALIA NHY SJAW IQISNI 519 318V321AH3S 43S ON IHNSOTINA LON 21812313 1 01 NQILNV9J NI NOISN3WIG L 5179 0c X 08 371 0901 0907 AO NOILVIOT X0SS1GO I 01 SS NI3QVIN NvdVf 200 80L OAMOL NY OLVNIW VH V8lHS 62 61 NOILVHOdHOO SWALSAS IVNSIA 21919913 IHSISISLIIN O3N 0881031 ON 13001N 3Sn 321530 HO 803 5 324 5 1 2028 59 v i 9 3 00 960 10 Wr sn C dis m 6 0F 9 06 VavNv d3TTinoss 13143 1 31 UNS 143131934 S39N39IX3 31 531001 31939539 8 ISSV19 1 30 ANOIHJWNN Tl34VddV 139 SNOILVINDIY LNAWdiN04 9NISQV9 39N3833H831NI NVIGVNVI U JHL 40 51 038 TIY SL34W SALVUVddV 1 11910 8 55413 SIHL 2 Vt o LO ZHO9 0G A0bZ 0ZZ 0Z1 001 XOSSLQIT 2uKsgjnw DAN 90 6 66 NI NOISNSWIG UL 31 05 40888 AVHO 1V3H MHVQ SNIH3LL3T 3LIHM LSIN 40109 13NI4V0 90702 MOVE 138V1 9NILVH XOSSLQIT vS bi 082 X 09r X M NOISNSWIG YANNI NOISN3NIG H1LNO
31. 4 HL L Nett 8WEU 009 LO6r Loor 1d1 WS Hd de a jou 1ojsiuuauj JBUJ9 X9 ute N d8 NOS l18 l 8AS Hd d88 pieoq Jamod 1ueuiuBisse 10199UU09 L 1 14 Video input signal specifications eTvpes of signals Video signal Analog RGB video signal 0 7Vp p digital signal TMDS Synchronizing Composite synchronizing signal TTL level positive negative polarity signal Separate synchronizing signal TTL level positive negative polarity Composite image synchronizing signal 0 3Vp p Sync On Green negative polarity Analog input signal rating Specifications Signal name Min Typical Max Unit Remarks Horizontal synchronizing signal frequency range 30 0 60 kHz Vertical synchronizing signal frequency range 50 75 1 Hz Video clock frequency 25 1 78 8 MHz Separate composite synchronizing signal Hi level 2 5 5 0 Volt Impedance 2 2kQ Separate composite synchronizing signal Lo level 0 0 8 Volt Analog video signal level 0 6 0 7 1 0 Vp p Impedance 75kQ Digital input signal rating Specifications Signal name Min Typical Max Unit Remarks Horizontal synchronizing signal frequency range 30 0 60 kHz Vertical synchronizing signal
32. CH330H509 09 CH330H509 09 2 01 CP096P012 01 CP096P012 01 _________ 2104271 01 CP210B096 01 ________ 210 097 01 CP210C10001 ________ CP223B007 01 CP223B008 01 ________ CP231D013 01 CP242C293 02 ________ CP242C294 01 CP246C428 02 ________ CP246C428 03 ________ CP246C428 04 ________ CP246C434 02 CP246C439 02 __________ 442 004 02 ________ CP540D077 01 5530007 04 CP554D027 01 ________ CP554D028 01 _________ 5 118 01 CP590D099 01 CP593A164 01 CP669D016 07 CP669D04101 _________ 6690074 01 CP669D089 01 CP669D104 02 CP669D104 02 CP669D113 01 690 114 01 _________ CP669D118 04 _________ 690 118 04 CP669D502 02 770020 01 ________ CP677D020 02 CP680D009 01 _______ CP775C370 01 CP775C370 02 ___________ CP803A109 01 8290019 01 CP831C047 01 QX0962462 07 SUMBOL PART NO DESCRIPTION SPECIFICATION ______ QX0962466 07 CARTON TAPE 75X50 096N010A 75X50M CLARITY QX669D204 06 SCREW SEMS W M4X0 7 16 6690220 02 SCREW TB 3X8 LCD1550X US _______ CP242C229 06 AC POWER CORD MT CP720B107 01 BEZEL UNIT CP700A270 1 LCD1550X US MI 802 393
33. Nearby 5X5 pixels pcs Notes 8 Nearby _ in 5X5 pixels Total Total Luminous dot R G B Dark dot R G B pcs Faul Total Luminous G Dots No Mura with line shaped contrast Perceptible at Notes Mura Stain full white 11 12 Dust Stain W 0 02 L O with Line Shape W 0 04 W Width mm L 20 pcs INotes 13 L Length mm W 0 08 L 10 10 L 1 0 0 W 0 08 Refer to Dot Shape ARA POZNA with Dot Shape D Average Diameter mm Scratch on Polarizer with Line Shape W Width mm L Length mm L N A 10 L 40 0 a W 004 pm rj mm n with Dot Shape 10 Notes 14 D Average Diameter mm Polarizer Notes 14 with Bubble Peel off pes Polarizer Wave 18 Document VSPF A028 Notes 9 1 Dot defect Defective part exceeds 30 of area at one dot 2 Dot defective with luminous mode Luminous dot which bright more than 30 when display the screen with all black pattern 3 Dot defective with dark mode Luminous dot which bright more than 70 cwhen display the screen with all white pattern 4 One dot defect The defective isolated dot Start that it is not adjacent to other defective dots 5 Linkage Adjacent dots To defined as linked two or more adjacent defect dots 6 Average Diameter defined as follows D Average Diameter D a b 2 Definition of defect dot Defect area is ou
34. 3 113 Bi pm 5 2 HP m HP 5 8 Be b 3 P P3 S 28 i i i 3 1 5 4 1 8 s 13 13 8 3 8 3 18 REJ i E s NIS NES FE 3 E E 8 8 5 g 5 mu DERI PERS g STE gee PERS WO oM ore 5 5 ore 5 ore 5 5 proa sten 5 IK a pry I GL ZAS j 1 ee 8 Be ML x RL 3 ew d Td de WAS RA as idi Pro gy 113175401 i 113175201 g 208 7 ML m3 zu 11175400 818 Sie ale SLE 518 818 55 i ifa KIE WIS jer 5 T 3 8 8 a E E 5 5 RZ 5 8 8 E 3 09 69 88 s SP eas og 25 8 aa zug 5484 882403 620889 28888529 8926 ou 6 69 338 888514 348884 8 885 409 85285 44483988 Lt 88488 885142 44 j 9 NE 4 4 88 SCHEMATIC DIAGRAM PWB MAIN INPUT 3 tr 5 8 ee 04 0 i j o jo o Jo Jo To L MOL L TYS TAD PMOL L T IIN L P W L MOL L 7 rco 8 soso LZ LSH809 g r yo 1 Y 0 74058 28 LZ LSH809 36 2057 1 1 6W_0_JuMPER 2301 1 838 1 16W 1 SEL_HS1_GS1 L gt 1 04 Foo E 2 615 651 gt
35. 5 i ae Q O OCP FB Icont 1 Vth 0 73V i 5 L 3 e Functions of each terminal Terminal No Symbol Name Function 1 D Drain terminal MOSFET drain 2 5 Source terminal MOSFET source 3 GND Ground terminal Ground 4 Vin Power terminal Control circuit power input 5 O C P F B Overcurrent feedback terminal Overcurrent detection signal and constant voltage control signal input 1 3 1 31 PWB MAIN basic specifications Basic specifications Two analog image system and one digital image system input compatible AMBI X Compatible synchronizing signal Analog 2Ch SEPARATE COMPOSITE SYNC ON GREEN Digital 1Ch TMDS Compatible with signals not displayed or selected Input signal presence judgment and automatic switching function VIDEO DETECT DDC switching control function DVI SELECTION DDC2Bi DDC CI compatible EDID data write protect control function EEP WRITE PROTECT Narrow bezel wide angle S IPS LCD panel Hitachi TX38D26VCOVAA interface Maurice2 incorporated for ASIC Auto Adjust function brightness contrast 5 curve color temperature color control adjustment function 1 3 2 PWB MAIN circuit block diagram
36. V Sync lt 38W N A On ON ON Active OFF No Display Amber No Pulses Complete No Display 6 Document No VSPF A028 4 Functions 4 1 Front control SW CONTROL ADJUST NEXT 42 RESETIL I BT INPUT OSD O EXIT 2 5415 17507 52 4 2 OSD function 4 2 1 OSM Control The various functions are controlled by 7 buttons on the front bezel using OSM On Screen Manager 4 2 2 OSM USER Menu Group Menu Adjustment Item Description Bright Brightness LCD back light brightness adjustment Contrast Input video gain adjustment Auto Adjust Contrast Automatic Contrast adjustment Analog input only Auto Adjust Auto Adjust Analog Automatically adjust the image position H size and fine setting input only Position Controls H Position Horizontal position control V Position Vertical position control H Size Horizontal display size adjustment Fine Clock Phase adjustment Color1 Default Color 9300K Custom 5000k to 9600k Color Setting Color2 Default Color 8200K Custom 5000k to 9600k Color3 Default Color 7500K Custom 5000k to 9600k sRGB Default Color 6500K Color5 Default Color 5000K Custom 5000k to 9600k Native Panel Native Color Color Control RGBYMCS Sharpness Image Enhancement Tool Expansion Mode Expanding image VIDEO Detect Video detection priority DVI SELECTION EDID Data Selection on DVI
37. 1 Electrostatic discharges may cause damage to a LCD Therefore the user should be handle a LCD with care 2 The LCD display surface is made from a fragile glass material Impulse or pressure to the LCD display surface should be avoided Shock lt acceleration 30G X 7msec 3 The surface of the polarizer is very soft and easily scratched Do not touch push or rub by hard thing more than HB of pencil hardness Even if using tissue paper the surface of protection panel may be scratched Also please do not touch it by bare hand Use a soft dry cloth for cleaning if there is dirt on surface of panel If dirt on surface is hard to remove please wipe it with absorbent cotton chamois or other soft materials absorbing Normal Hexane recommended as cleaning chemicals If using another type solution there is a possibility that the surface of the panel may become discolored If a dirty cloth is used there is a possibility that dirt from cloth may adhere to the surface of panel Use a clean cloth only A pressure onto the surface of protection panel may cause the obstruction for display 4 An atmosphere with high humidity should be avoided If dew appears on the LCD monitor the monitor should be stored for over 30minutes in dry room prior to operating 5 Do not store and or operate the LCD monitor in areas of high temperature and or high humidity Pack the LCD monitor in electro conductive pouch and store it under relatively low temperature a
38. 2 7 2 1 HZ 2 MD 4 d ER y 3 4 8 gg gt m 81 P 8O X WL 707106 gt 9 Mb L 5 P Ad Li X aed grum 72 ZZASTLId m 068 vied 4 a Hr 58 E INS 2 ZN ed 2 d s 5 22 1 0 e QNO 6 LTAT ao E 8 1 91 677771 m a 1 5 yz V 5 8060 TM 8 ANI d i 7153 eu 9264 P s 28 uf n g9s Nz L 1 2 S i AZ U Mb L Od lt A Z S nd T ING 4 5 6 88 9 2 a Ha 4 906 ANIDALAG 5 1060 A 8 LEG 22 S H wee T 2 EN 12 Tj s o H3INSANI OL Sty eeLr eeer d t S W Hd 848 ES 2 1 0 006 a w p2 59 ARS Fs MOLETMZ ZL 5 nazJNLA a 9 na 4 NE ms 6 _ aa Soc Lig N E pagan ouai E 513 TIT m 1 L 2067 9062 a 58 ws HOSS LL d28 Ja 23 ONS 9961 ano 5 1 8860041 293 2 p 0063 9 Dh fit 4 amp ko ode 8 8 Ne 24818825 s fa b ACIE rt ei 228 I7 lt uA 2 ii 1 2 Nate AZL 5 z wits TER 8 E 7 3 ano HOSS 11 4995 00152 VL 100157 22 Ej E S p 2 gt 1061 1183 td g gt 8 0061 e S 6 106
39. 3 Confirm that Power On Indicator is lit in green 4 Press button to display the OSM picture 5 Select OSM POSITION with OSM and press button to confirm that OSM picture moves 6 After pressing RESET button press NEXT button to confirm that the OSM picture returns to the appointed position 7 Press EXIT button and confirm that OSM picture disappears 2 6 1 2 Inspection of picture 1 Check the picture position and the inclination according to 2 5 2 Mechanism and appearance inspection 2 Check the picture defect according to 2 9 Liquid crystal display defect standards 2 6 2 6 1 3 Aging 1 Set to aging mode with OSM 2 Carry out heat running for 30 minutes or more in the no signal state 3 Cancel aging mode with OSM lt How to enter aging mode gt To enter aging mode press and buttons simultaneously holding down RESET button when OSM is displayed in NO SIGNAL state Set OSM GAIN to MAX 255 using and buttons during heat running lt How to disable aging mode gt To disable aging mode press EXIT button when OSM is displayed Note that turning power ON and OFF can not disable the aging mode 2 6 2 Main adjustment 2 6 2 1 Confirming OSM picture during heat running 1 Confirm the ADC MAX value is 190 or less during heat running 2 Confirm that background of ADC MAX value indication is not red colored The color of the background changes in the following order WHITE gt YE
40. CP210C100 01 AYER CP210P002 PWB SW MI CP223B007 01 INSULATOR TOP N 7 0 5 LCD1550X MI CP223B008 01 JINSULATOR BOTTOM N 7 0 5 LCD1550X MI CP242C293 03 SC D801 LCD1550X BK CP242C294 02 SD D830 LDX1550X BK CP246C428 02 12P LCD1550X MT CP246C428 03 FFC CABLE 30P LCD1550X MT CP246C428 04 CP246C434 02 CP246C439 01 LEAD CONNECTOR SW LCD1550X MT CP442P004 02 JEARTH TERMINAL TP00385 41 479 050 01 JCD ROM CD ROM US _LCD1550X 5400077 01 LEAD CLAMPER LWS 1 5SLVOBK LCD1550X CP553D007 04 5 48140 LCD1550X 5540027 01 5 LCD1550X 5540028 01 z LCD1550X MI CP554D029 01 LCD1550X MI CP580A118 01 SECC C E16 16 10 8 LCD1550X CP590D099 01 60635 5 LXA595W CP593A164 01 CP669D016 07 CP669D041 01 CP669D074 01 CP669D089 01 SCREW SEMS 4 8 LXA550W CP669D094 04 CP669D104 02 CP669D104 02 lt gt gt 010 zjz 010 4 4 gt gt 0170 mimi o z gt P gt w w m o 2 gt E gt w w m Om n Q gt fm m Q gt fm 4 m EEEE mmole 9 x ol g lt m 2 01010 20123120 m m m WO 00 0 2 2 2 9 CP669D113 01 CP669D114 01 CP669D118 04 CP669D502 02 6770020 01 6770020 02 6800009 01 CP775C370 03 14 15 010
41. EAT n ie s Hu z 24 2201 fi wzisyaesina oor 7 4 e 8 8013 ZBLSHAI FO 2 d 9015 ZeisHaderatT zg LL 31789 47113175201 15 sid LL 31789 97113175701 Pans ZI 88918 KANT LL 31789 67113175701 Puno ze RAT ces LL 31789 97113175201 sew LL 31789 57113175201 Ps za KANT sets LL 31789 97103175201 3 201 je ze seed FR PE Drama 51 LL 31 89 97113175201 E RNC Ted TE 1zisHgegixg 171 osz 1 ZGBZG 2 1 OW NIVW dMd INVHOVIG OLIVWAHOS 088 091 07 20191 85 60191 96 20191 86 00191 gee i A s mig S 26 2019 06 20101 82 20101 92 20101 cM i Ce i rem 20131 20 20191 02 20121 2100121
42. FACTORY PRESET Executes Moves up Changes OSM display position horizontally 0 Changes OSM display position vertically 0 Select how long the monitor waits after the last touch of a button to shut off OSM control menu The preset choices 45 SEC are 10 20 30 45 60 and 120 seconds Locks out cancels OSM control Press both control keys for LOCK OUT then press both Cancel control keys again for cancel Select RESOLUTION NOTIFIER ON OFF DISPLAY MODE Indicates information about input timing used etc MONITOR INFO Indicates model name and serial number Resets all OSM control settings back to the factory settings Except for bel 2 23 lt Factory mode gt Adjustment Default OSM item Setting or circuit operation range value BRIGHTNESS Darkens Brightens Modulates inverter back light 222 BRIGHT_MAX BRIGHT_MAX CONTRAST Changes output data with digital contrast 30 225 CONTRAST AUTO Automatically adjusts contrast RENE AUTO ADJUST Executes Automatically adjusts H position V position clock and clock Y phase LEFT RIGHT Moves to the left Moves to the right Changes horizontal image position to where image data taken 512 1023 Adjustment of horizontal position DOWN UP Moves down Moves up Changes vertical image position to where image data taken 10 100 Adjustment of vertical position H SIZE Narrows to the left Expands to the right Changes setting of PLL divi
43. Input signal PD Order of priority DVI I A Hi 2 DVI I D Hi 1 During PMS Cycle pulse 2 1 50msec interval Hi for both input 1 and 2 Control is carried out at an intermittent interval such as 450msec interval Lo 1 23 1 5 DDC interface peripheral circuit DDC interface peripheral circuit A5V Avo or DVI P J200 X91 2 7 A5V or DVI DVI I connector M24CO2WMN6T RX2 RED TI RX2 RED qu 6 SCL DDC AH SDA DDC Dec DVI I for Digital Ch M24CO2WMN6T 4 5VDC J HTPLUG ASV or DVI IC102 MPU M30625 or DSUB J201 M24C02WMN6T 72 D Sub connector gt HK swo SCL DDC mm L 34 l SDA DDC 1 24 1 5 1 DDC switching control function List of control signals u COM Pin No Signal name Function Remarks 67 U D UP DOWN CONTROL OUTPUT X9116WM 2 7 66 INC INCREMENT CONTROL OUTPUT X9116WM 2 7 1 O CS CHIP SELECT OUTPUT X9116WM 2 7 21 A2_DIG EEPROM for DIGITAL A2 ADDRESS SENSE NJM319V 28 2_ EEPROM for ANALOG A2 ADDRESS SENSE NJM319V Function When the OR DVI power refer to next page DVI SELECT in OSM function is changed the X9116WM 2 7 106 pin 5 Rw Wiper Terminal output NJM319V pin 12 OUT PUT 1 output A2 DIG and pin 7 OUTPUT 2 output A2 ANA are set to the following values The DIGITAL EEPROM or ANALOG EEPROM slave address is set with
44. LED_P_G LED control signal green SW board 5 5 Mode switching signal for onboard writing Serial writer P5 6 SEL 1 DVI A video input buffer output enable signal 0 Output disable 1 Output enable P5 7 CLKOUT P6 0 CTSO RTSO PIVOT SENSE TMDS CTL3 Inclination sensor signal detection unused TMDS receiver CTL3 signal 0 When normal Inclination sensor Sii143 P6 1 CLKO TMDS CTL2 TMDS receiver CTL2 signal 0 When normal Sii143 P6 2 RXDO TMDS CTL1 TMDS receiver CTL1 signal 0 When normal Sii143 P6 S TXDO A2 ANA DVI I for analog Ch EEPROM 2 address detection 1 address 0 0 A2 address 1 EEPROM P6_4 CTS1 RTS1 CTSO CLKS1 BUSY BUSY signal for onboard writing Serial writer P6 5 CLK1 SCLK Clock data for onboard writing Serial writer P6 6 RXD1 RXD Reception data for onboard writing Serial writer P6 7 TXD1 P7 0 TXD2 SDA TAQOUT TXD DDC SDA Send data for onboard writing Data signal for DDC communication Serial writer P7 1 RXD2 SCL TAOIN TB5N DDC SCL Clock signal for DDC communication P7 6 TASOUT DVI I for digital Ch EEPROM A2 address detection 1 A2 address 0 0 A2 address 1 EEPROM P7_7 TASIN P8_0 TA40UT SEL_2 V measurement at C S for D SUB connectors D Sub video input buffer output enable signal 0 Output disable 1 Output en
45. Symbole und Graphiken sind bei h herer Auflosung kleiner LiquidView software scales both desktop M3TAGINOIT HLIM HU3HO 5343 YNOA 3AT9 www portrait com navigational 100k are larger and easier 10 see Affichage et applications par LiquidView Ala m me haute d finition les ic nes le texte et les aures de navigation sont pls grands c pls faciles a voir Liquidiew optimierte Anzeige und Anwendungen SAV IdSIQ at g a ect br a Sanh td oregon gal PIDB T LIVYLUOd ENT NI NOISNIWIO SIN 37725 P 762 3Hf1HOOHS X0SSLGO I dvdd d YAN z99b 2 9 008 10 14044 Apjdsig 210432213 LUSIGNSILW JIN 243 3203 02 40 5 ay 0142 24 aspajd 127 anok fo 5 ay suoizsanb Aun nok UOJUNJ 1011295 51043405 uonisog 54043102 jeNUEW 5 195 XOSSTQII IUASQINW JIN 993 03 se d jenuew 4935 F 4235 03 aspajd 51 3sn py BurpAmop fT 1snrav 01 55384 isnrav olny nua WSO 993 9500 01 UONG LIX3 55944 3snfpy OJNV 500204 LSNEAV 993 Jo euo 12995
46. and marked with CE NEC Mitsubishi Electric Visual Systems Corp MS Shibaura Bldg 13 23 Shibaura 4 chome Minato Ku Tokyo 108 0023 Japan VOCI Statement OES _ R EEJ EERAHCIEFH TIELEEBALLTIET eS sy SEBESZSIERCTCOCSUBU wd TAHR Eo TEL lt CELU Dk pas a I 9 21 am LI TCO 99 MultiSync LCD1550X LCD1550X Congratulations You have just purchased TCO 99 approved and labeled product Your choice has provided you with a product developed far professional use Your purchase has also contributed to reducing the burden an the environment and also to the further development of environmentally adapted electranics products Why do we have environmentally labelled computers In many countries environmental labelling has become an established method for encouraging the adaptation of goods and services to the environment The main problem as far as computers and other electronics equipment are concerned is that environmentally harmful substances ara used both in the products and during the manufacturing Since has not been possible for majority of electronics equipment to be recycled in a satisfactory way most of these potentially damaging subslances sooner or later enter Matura There are also other characteristics of a computer such as energy consumption levels that are important from t
47. cause alectic shock Thenelorg i is dangerus 2 maka kind of contact with any part irede this unit This symbol alerts ne usar That important Hharatuna conceming tha operation And mainienance of This arit has been induded B res caretully in order 16 avoid any problems Caution When operating the MultiSync LED1550X ILED155OX with a 220 2407 AC power source In Europe usa the power cord provided with the monitor in ihe UK a BS approved power cord wath moulded plug a Black live Amps fuse installad for use with this equipment a power cord is mot supplied with this aquigment please your supplier When operating the LCGD1550X with a e20 e40V AC power source in Ausiraba use the power cond provided wilh the manitor For all ather cases ise a power That malcnes ihe AC voltage of ihe power and has bsan approved by and complies with tha sa aty standard of your particular cauniry 6 A LIS badema As an 5 Purtner HEC Misubishi Electronics Display of America Inc nas daterminat that this product macis tha guideknas tor energy efficiency Tha amb am does nat ruprasent EPA andorsemant of any product or service JEM PCIET AT Pa MOGA WGA BS T4 A and XGA negestered trademarks al iniernatonai Business Machines Corporation Apple and Macir osh are ra edered rademaske al
48. quawiauiayd sia a Uo np jaa y 19 10332084 LNVA3Q 235171 LNAWASSILHJAV 3 UAS 1 jn W feu pueis 4 243 JUM acejns ued q LON 00 xj pue au pue ya uo spuey aed inpouu 219 07 prone 531055000 1541 oq 4018 BAR uoi a BROW OL i9NIQ33203d 340338 QV34 NOILNVI Aor yy 14dV 1 3009 uva NI NOISN3WIG 9 1 FIVOS 49V I8 9NILNIHd dO 40100 NOLYVO NOILVOIHIOHdS SNILNIHd XOGGLGO 1 NOLHVO INOHA INOH4 p 14dV 1 4409 uva E 9V8 TANIA 2 NOLHVO XO8 NO1HVO 3HVMLJOS Q9 JHVML4OS pue JVANVIN SHASN WOANVW 5 4450 40 1 4 WOLLO8 weiApinbr1 AdVL DNIMSVW Td ONIMOVd a m 133HS 41185 A W 3dV1 ONDISVIN JO INO 4 PS HOLINOW AV14SIQ 6 0 dO L 133HS DNIMOVd 8 J18VO IVNDIS s P d H3MOd lt gt V IAQ 4 1dVO IVNDIS 31415 9NDIOVd X0SSIGO I NI NOISN3WIG SIN 3179 v8 bi 20 111008 Inoqy SIVAOHddV S 2509 IHNLVHIANAL 6 VOL OV
49. u83 6 ut qe 1snrav OLNY 242 34646 03 uonnq 1 993 329195 WSO 125 JIN 241 dn 03 Joqluow 244 Jo 2794 1504 344 uo suonnq 15 10 103105 991 Jo auo 129 95 501 JIN 991 Jo quaw sn pe dnqes 021 2945 4 04 3snfpy 4935 daqs 03 se d 70u 51 qsn py o3ny ON ayy JI Sui 1544 43 404 si euDis Mau AjUO SL SIUL uorjuny 3snfpy o3ny oN 341 au g9 xtrzor 01 195 st ANO se 1005 sy snfpy o3ny 4935 NI NOISNAWIG SIN 3179 14 INOH4 012 er apis 24224 uo 4215 01 wag mis fiy uonnjosaJ 89 20 Em Se E 344 uorinjosey 9 uM 2 Aejdsig 95004 7 Aejdsiq pue sl ued 051402 8ued 043402 129 95 MON 72 nuaw 31235 a4 950042 uonnanBifuo3 4 dX SMOPULM stanac EZM B E a pr 9 sm E
50. 2 2 O 4 m a E e O I r 212 gt zjzjz m m m ojojo 2m o o zx olo 2 2 2 2 2 2 olojo r lt lt 3 4 rio 111100 OJO x wjw m m 19116 m m 2012 2312 mm ojo IJI 70170 11 11 11 00 00 gt U T m 2 2 m I U m E 11 00 00 11 mjm gt gt olo TIT m m zz 212 ojo w m 2 m 2 2 m 5 wjw m m 19116 m m 2312 2312 m m ojo IJI 70170 w m gt U T m 23 2 4 I U w 1101 CP410P102 01 1102 ____ CP410P102 04 1103 CP410P102 04 1104 CP410P102 01 1106 CP410P102 01 1107 CP410P102 01 1202 CP410P102 01 L203 CP410P102 01 1204 CP410P041 03 L205 CP410P041 03 L206 CP410P072 08 1 207 CP410P102 01 1208 CP410P102 01 L209 410 072 08 L210 102 01 L211 410 072 08 1212 CP410P072 08 L213 410 072 08 124 CP410P102 01 JB 1215 410 072 08 L216 CP410P102 01 L218 CP410P102 01 1221 CP410P041 03 L222 CP410P041 03 L300 CP410P102 01 1301 CP410P102 01 1302 CP410P102 01 L303 CP410P102 01 1 305 CP410P102 01 L306 CP410P102 01 L307 CP410P102 01 L3
51. 47 EU RED 2 4 1 47 GREEN 2 3 l 0 01 47 EU BLUE 2 l 8 ootu E SD TAAS EKA S G synchronization separating circuit 33kQ 22kQ DTA143EKA 5 2 Ce DTC114EUA S G synchronization separating circuit 33kQ 22kQ 4 100 l 22 33kQ 2 2 7 5 100 2503545 1200 100 22 0 33kQ 23 5 109 19 C Cy 2803545 15 1 22 102 Q Js 25 3545 1200 100 P Ch l 15 25 3545 1200 circuit video buffer i SC3545 0 1u 100 RED1 1200 Otu 100 GREEN 018 100 w BLUE1 5 i 0 1u 2503545 100 RED2 2 a 100 P GREEN2 018 100 w BLUE2 Digital signal DVI I D and analog signal DVI I D SUB switching The microcomputer sets the ASIC internal input switching switcher SOURCE register to external digital for DVI I D analog 1 for DVI I A and to analog 2 for D SUB The frequency and resolution for digital signal of the selected input signal are measured by ASIC For analog signal input Pin 148 AH1 Pin 149 AV1 Pin 146 AH2 Pin 147 AV2 For digital signal input Pin 151 DCLK Pin 153 DE Pin 154 DV Pin 155 DH The DVI I D and DVI I A input selection follows the following order of priority Selection of input signal is controlled
52. F B zener diode D718 Inverter Output F B zener diode D720 parts below back light Is approx 3 3V input 5 of J703 Inverter Output Tr Q701 Inverter Output Tr Q702 Inverter Output Tr Q703 Inverter Output Tr Q704 Inverter Output trans T701 Inverter Output trans T702 Inverter Power output IC IC703 2 2 Back Light Is On POWER ON INDICATOR Green is blinking Does OSD NO appear YES Is DC2 5V P2 5V output from 4 of IC606 NO YES Is sync Signal A NO input into each pin of ASIC IC400 YES H DVI A V S S Hs DVI I Hs D SUB Vs Is DC5V NO into 4 of IC6102 VES Is DC5V PANEL 5V A NO output from 1 Is Q600 on of IC6102 YES YES Panel 5V line may have any problem Panel 5V Line Circuit MAIN Power DC 12V 5V convertor Tr Q601 Control circuit may have any problem Please check the parts below PANEL 5V ON OFF Tr MPU Power Q600 IC102 MC MAIN Power PANEL 5V generator IC 12610 p 77 21 Voltage PANEL 5V Line Circuit Schematic Diagram Panel Circuit DC5V MAIN ASIC Panel 2 5V Line Circuit P2 5V Line Circuit Schematic Diagram MAIN ASIC Pin no of ASIC 10400 to which sync signal is to be input Input Connector Pin no Video circuit may have any problem Please check the par
53. Front power switch monitoring Normally 1 Lo when switch is pressed 76 RESET OSM menu selection Normally 1 Lo when switch is pressed 35 O LED_P_G default value Off Lo green LED On 36 O LED U Hi default value Off Lo orange LED On Calculation of LED CP264P480A10 drive current Maximum rating 75mW 30mA Photoelectric characteristics 1 9V LED drive current 3V Vr 2200 transistor s Vcetsat is ignored 6mA lt 30mA LED power M3_3V VF x 6mA 8 4mW lt 75mW z 10kQ x 8 MAIN board SW board mierocomputer POWER SW RESET Layout looking from back of panel 1 41 1 8 Inverter circuit 1 8 1 Basic configuration Oscillation circuit method Self exciting Number of backlights Four Dimming method PWM dimming 1 8 2 Circuit block diagram Resonance circuit 1 Resonance circuit 2 Back light 12VDC input O FET switch 6X 228 oan Latch circuit PWM 4 dimming 7r circuit Timer circuit Overvoltage Transformer ar detection Waveform Voltage shaping comparison inde Waveform p current detection protection circuit comparator shaping 1 42 Input output terminal functions 1 J703 PIN No Name Function 1 12V Power input 2 12V Power input 3
54. R R lt 2sets each color total x 6 sets Combination of different color dots Allowed Combination of bright and dark dots 20 Allowed Document No VSPF A028 Note 6 Example of Distance between each sets of E is as follows a a d lo Bright dot Count Criteria Note 7 Example of Cluster of defect dots is as follows 0 0 0 Bright dot Lo dot Count Criteria When 2 or more defect dot exist in 5X5 pixels the set of the dot defect are counted as 1 cluster 5X5 pixels Defect dots lt 2 cluster 1 cluster Note 8 Example of Adjacent 2 dots 5X5 pixels are as follows 0 Qo Bright dot dot Count Criteria 5X5 pixels 5X5 pixels Allowed RG II Adjacent 2 bright dots s1set Adjacent 2 dark dots siset 5X5 pixels 5X5 pixels Adjacent 2 bright dots 2 2 sets Adjacent 2 dark dots 2 2 sets 21 Document No VSPF A028 9 Notice for Handling A LCD Liquid Crystal Display has the following specific characteristics These characteristics are not indicative of a defect or malfunction a The display condition of an LCD may be affected by the ambient temperature b The LCD uses cold cathode tubes for backlight Optical characteristics such as brightness or uniformity will change during the LCD s life time c Uneven brightness and or small spots may appear depending on different display patterns
55. S s IN 116 8 5 5 ma Q a 4 8 R Ro z 8888888888888 8882229 aaa 7 884 ds da T T 512522555555 95535525522 2222 950978828 00089 oka a 113 9 6 SZNWEsSsS SINBSES 68 8 SS ee eee 303 512821488 SEK RZ 6888 2 1 112 9 z 2 48 M 11228 ji 5 5 113 8 1 a 9 pte 3 i 113 8 eno 5 i I or 4 5 SH HsHsH sa 3 Bs LIO TE IO i HERE x i 5 x 5 E 58 5 5 g 1333333333333 1333333 1333 jj RE P 8 L 5 2 8 E a eal 5 6 bie bo 9 1 1 55 CES 99 1 ar w 9 1 EE 25 9 58 55 2 gt 5 5 gt gt gt 1 i pe P 5 5 i T 5 5 m 5 r X SOLTABLB NI r 85 25 i 80 1 AOL gt 4 099 MOL L RB 3 898 MOL
56. SOLTAS 98 Lzy 9 2288 5 9585 ae 357 LON 5 s L LE VOIAS UE LL 3L1GGESSI E 813 Di Sua RE Y 901A 98 pg E 2 x z Y 5 78 5 al p R3 at 4 pe a g 4 8 H g 9692 Re 4088 x OT nasa 9 5 8 gt 5 3 017A068 5 g E g di ai pg 8089 LITE Li 318 t i SQ 10N 5 5 9 5 8 2 M SBLTAS 98 u 3 S CE 2 5 4 5 c gt 8 gt alls B E P X MOL L LS Um x 5 S 5 amp a L 8 3 a 2 558 Xe 350 LON as 8 Eip lt 5 5 a m TO pozz hot 3800 ES ih T tal 3 0817N9L L p GO 199 9 E UE Sa z Nz gt E 9995 zo 5 16831 718549 98 3 022 W9L L J v0L A918 SE S w 8 p 2 8 990 9092 a9si aniina Wear ASL 892 d 0ee M9L L 4 9 3 8 199121 8 OLE NOL 3 2 MOL L 28 ANT TAT E 28 01 A068 01 W HOL AGZ 8 H I 5 e s 3 g S 3 8 8 8 5 ap 18931 710580 s 850 z 190 19831710542 16883 PS 2190 190 OMO V V 5 3 8598 a l E EJMOL IL I 2 1 1 X v01 A018 692 4 L AS 798 J S01 Ae 98 4 u MO L L Ds rou z LEI MOL L j X08 N9 L L gt
57. __________ ________ 109 01 CUSHION SSET ____________ 5 0 01667 01550 _______ 8290019 01 PACKING SHEET ____ 155 8 1 047 01 PACKING BAG HDPE 10 044 LCD1550X 8500286 01 JLABEL AMBIX 25792581 LCD1550X 0 0962462 07 ________ 0 0962466 07 CARTON TAPE 75X50 7 096NO10A75X50M CLARITY 6690204 06 SCREW SEMS W M4XO7 16 6690220 02 SCREWTB 3988 _______ CP242C229 07 AC POWER CORD MT 7208107 03 BEZEL UNIT CP700A270 2 LCD1550X US MI 802 393 02 PACKING CASE LCD1550X US 859 233 01 ACCESSORY CP871C190 9 LCD1550X US CP870C133 01 SHEET SETUP LCD1550X US LCD1550X BK EU CP720B107 04 BEZEL UNIT CP700A270 2 LCD1550X EU MI 2 1 lt lt 802 393 03 PACKING CASE LCD1550X EU 2 CP859C233 02 JACCESSORV CP871C191 1 LCD1550X EU CP870C133 02 JSHEET SETUP LCD1550X EU CP870C134 01 SHEET CAUTION LCD1550X EU 15 15
58. capacitors Lead damages the nervous system and in higher doses causes lead poisoning TCO 99 requirement permits the inclusion af lead since no replacement has yet been developed ad pas 5 ABU EST 11 Cadmium Cadmium is present in rechargeable batteries and in the colourgenerating layers of certain computer displays Cadmium damages the nervous system and is toxic in high doses TCO SS requirement states that batteries the colourgenerating layers af display screens and the electrical or electronics components must nat contain any cadmium Mercury Mercury is sometimes found in batteries relays and switches Mercury damages the nervous system and is toxic in high doses requirement states that batteries may nat contain any Mercury It also demands that no mercury is present in any of the electrical ar electronics components associated with the display unit CFCs freons CFCs freons are sometimes used for washing printed circuit boards CFCs break down ozone and thereby damage the ozone layer in the stratosphere causing increased reception on Earth of ultraviolet light with consequent inereased risks of skin cancer malignant melanoma The relevant TCO 99 requirement Neither CFCs nar HCFCs may be used during the manufacturing and assembly of the product or its packaging Bio accumulative is defined as substances which accumulate within living organisms Lead
59. t SL 113 8 zw ESL RT 13 9 nu tt 18 Rs ue ha 2 2 258 zd RSS 40222 s RT X 2 1 ER ho gt 5 3 e 192252 k ud 5 B 5881 IA BO AGV RERRER lnu 91 2 _ I 91 2 lt vez 603 63 63 3 62 63 3 63 3 3 02 62 62 2 62 ET L vua 78 2 a r w map B BER 4338888 who ded R ag UR E LL 99295 ot amp zk co 333 sa say c zsa nba ZAW 2 3 5 5 er lt a sa ZEN 3 IS 3 7 9754 f sor lt NSW 04 2 so v om gt osn 8 5 0 0 v 6 ISN BO o lt ir T 26 sor 69 15 xe so r mp Anise aorosszoosn na te al 58 9 sana E 83 9 9 awsa lt gt 3AVSTA O hen 2 a vi 9 95450674 D e 1 ZA f amp 3 ee me 844 2 3 vi 9 lt 20 ssa 4 s F 5 4 Ez 5 fl 9 69 450674 ini b a dia w wars LANITA zz W T 63 TANVAA w ae ea i vO lt 9 P rm 22 pH wa Qs 338512 EAS SBR sor MTS e 6 gt 255 257 785 8 R iz as E Aa x te
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61. 1 913 1 913 1 913 1 913 1 813 1 g4 v 8 3 1 8 4 1 NG Zd 3 2 4 sassa 5 9 u Y A g PA ls sk 9 2 Soy oy 552 g x A l Z 24 um T Bl al 8 51520815 A 15 E 8 ESPEN 90921 Sp Big 3 318 SLE 27 8 575 5 2 2 av 4 T 5 1 z el woven P g LT li 2 am IN d 8 9 a AS V 8 f sa 2 1 1 x Z sa E T s z sa 90 c 198551 2 5 b LJ 5 2 5 1 8 2 fat gt 8 2 s 58428 ah 72252 I 2 E a a 2 b 2 i 2 5 8 w 8 5 Tal 5 9 5 5278 A LI WW mx gifs EDS 8 L SET 5 r 8 5 L Ao EE e giis a 51285 9 E a Ta 955 gt 2 D J sa sa Radi St ESI 8 kal E i 3 E 2 x 215 21e 21e 21e Q9 50 2 52152 8 2 er XD 2 ST ST eg 8 i Ja 358152 ums aL T od 2090 9091 s 28 BAYSTd gs 2 19SLZLdLLNTB T LL ALOSESSL 195121911018 L ATG OUJ ir NN 991 ed 4 ANIDALNG il 90 L ASEH L ni a 50 s FAQ YNa LLOLO Cls 2152 ES 2123 F QNS sa 5a ati a ftira Az i g 2 2 2 2 i
62. 2 I anvs LLH S b 844 BEE sea 1 IET VA EEA w lt l fe pe ita i3 B BEE B LH S s lt m EET H i cee mo lt wys bios eee PERE f lt bias i E 2 8 zz 3 28 Ys 2 55 7 Km bi ELT RA MW CE z 2 B ANISNTLON 3SNTLON iei over Tezz sa Onkol LL 31789 57113175201 L 1331 Pm cesi Ll 31789 97103175701 Ore 3 97113175200 adl 789 G7 I 1HOIM Li 31769 20155554 m 787113175200 TOBIT il 40 Taosa S819 70 RAMA ad Ll 31789 8713175201 DH zara 20 Hi ran Ll 31789 97113175201 NU 4001 4050 sau ee Ll 31789 87LL317SZ0N DH are gt zeke ud Im T 9 d par 0621 29829 zi T izisHeesiya 015 INVHOVIG OLLVW3HOS XOSSLQO1
63. 20 30 45 60 and 120 seconds OSM LOCK OUT This control completely locks out access to all OSM control functions When attempting to activate OSM controls while in the Lock mode a screen will appear indicating the OSM controls are locked out To activate the OSM Lock function press 4 then i and hold down simultaneously To de activate the OSM Lock Qut press 4 then ir and hold down Simultaneously RESOLUTION NOTIFIER This optimal resolution 1024 x 788 ON is selected a message will appear on the screen alter 30 seconds nolifying you that the resolution is not at 1024 x 768 FACTORY PRESET Selecting Factory Preset allows you to reset all OSM control settings back lo the factory settings Individual settings can be resat by highlighting the control lo be reset and pressing the RESET button 1a EST e Information DISPLAY MODE Provides information about the current resolution display and technical data including the preset timing being used and the horizontal and vertical frequencies Increases or decreases the current resolution Analag input only MONITOR INFO Indicates the model and serial numbers of your monitor OSM Warning OSM Warning menus disappear with Exit button pi NO SIGNAL This function gives a warning when there is no Horizontal or Vertical Syne Signal present and advises you ta check all
64. 2B DH DIODE CHIP 0202132 LXA595W DIODE SF15JC10 LCD1550X DIODE SARS01 LXA595W DIODE SARS01 LXA595W FS CSS eI FUSE 251004 4A PROTECTOR 491007 7A IC MOS M24C02WMN6T IC MOS M24C02WMN6T IC LINEAR NJM319V TE1 IC MOS 74ACT157MTCX 5 15 IC REGULATOR SI3025LSA 2 5V IC REGULATOR SI3025LSA 2 5V IC REGULATOR SI3033LSA 3 3V IC REGULATOR NJM2870F25 TE1 2 5 FET CHIP HAT1053M LXA595W IC LINEAR LM2901MX LCD1550X IC LINEAR LM2901MX LCD1550X HIC STR G6452 LCD1550X C903 CP268P017 01 C904 CP263P215 02 IC KIA431A AT C905 CP268P017 01 JPHOTO COUPLER PC123Y22 100 CP452P318 02 CONNECTOR FFC 52852 12900 LXA595W 101 452 311 05 CONNECTOR SR SM10B SRSS TB 1 580 200 452 343 01 CONNECTOR DVI QH11121 CBO MI 201 452 070 01_ CONNECTOR D SUB NFN8715F 400 CP452P310 03 CONNECTOR FFC SMT FH12 30S 0 5SH_ LXM510J 401 452 310 06 CONNECTOR FFC SMT 12 455 0 5 LXM510J 600 452 284 01_ CONNECTOR PH SM3 B2B PH SM3 TB MI 601 CP452P284 07 CONNECTOR PH SM3 B8B PH SM3 TB MI 701 CP452P315 02 CONNECTOR SMT 5 04 9 2 5 1 LCD1550X MI 702 CP452P315 02 CONNECTOR SMT 5 04 9 2 5 1 LCD1550X MI 703 CP452C023 07 CONNECTOR PH B7B PH K S 800 452 268 02 CONNECTOR FFC 52807 1210 900 CP246B185 05 LEAD CONNECTOR J703 J900 LCD1550X MT 901 CP246B185 04 902 452 345 01 CONNECTOR VH B2P4 VH B LCD1550X AC CP452P247 03 CONNE
65. ASZ B 8 3 408 M9 L L M t 5 t h gt SWE 5 l 20 MOL L 8 5 seo HAN V L pg 8 8 8 y sa X FGT A818 5955 LES sek m y 01 A0sa 1 p AGP 5 8 1095 T sss 50 5 W201 A068 T o 1299 Y 20 T T 9292 J 0 17068 F T gt 28 9292 J 0 17068 5 wx gt E 2 2 382 58 U a U a a 1 a a a m g 8 59 pa L u L w u u u gt gt 5 u Hee UES 98462 2 LO IDEE 17552 5 a P PRO DLY DUTYCINV P SUSP1 1 E15 P SUSP2 gt 1 E15 P_SUSP3 r gt 1 F15 LCD1550X SCHEMATIC DIAGRAM PWB MAIN POWER INVHOVIG OLLVW3HOS A 226 I pSHSZ 7 881 T zz xzjz far
66. C CERAMIC CHIP CH50V 47 1 6X0 8 C CERAMIC CHIP CH50V 47P J 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 562 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 562 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 562 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 562 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B50V 102 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B50V 102 K 1 6X0 8 C CERAMIC CHIP B50V 102 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C ELE CHIP 16V 220MF F80 C CERAMIC CHIP B50V 102 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP CH25V 1000P J 1 6 0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X
67. CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP CH50V 100P J 1 6X0 8 C CERAMIC CHIP B6 3V 105 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B50V 472 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B6 3V 106 K 2 0X1 25 C CERAMIC CHIP B50V 472 K 1 6X0 8 C CERAMIC CHIP CH50V 47P J 1 6X0 8 C CERAMIC CHIP CH50V 47P J 1 6X0 8 C CERAMIC CHIP B6 3V 105 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B50V 103 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B6 3V 105 K 1 6X0 8 C CERAMIC CHIP B50V 103 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B50V 103 1 6X0 8 C CERAMIC CHIP B50V 472 K 1 6X0 8 C CERAMIC CHIP B50V 472 K 1 6X0 8 C CERAMIC CHIP B6 3V_106 K 2 0X1 25 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 1 15 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8
68. CP103P494 04 R 141 CP103P494 04 142 CP103P493 06 143 CP103P492 00 144 CP103P497 01 R145 CP103P492 00 R146 CP103P113 08 147 CP103P107 02 R148 CP103P491 06 R149 CP103P491 06 R150 CP103P494 04 R151 CP103P494 04 R152 ____ CP103P491 06 R 153 CP103P497 01 154 CP103P497 01 R 155 CP103P497 01 R156 CP103P114 00 R 157 CP103P102 08 R158 CP103P107 02 R159 CP103P491 06 160 CP103P102 00 R 161 103 492 00 162 CP103P497 01 R 163 CP103P107 02 R164 CP103P104 04 R165 CP103P107 02 R167 CP103P491 06 R169 CP103P494 04 R170 CP103P494 04 R 171 103 494 04 R172 CP103P491 06 R173 CP103P491 06 R174 CP103P494 04 175 103 491 06 R CHIP 1 16W 3 9K F 16X0 8 R CHIP 1 16W 12K F 1 6X0 8 R CHIP 1 16W 12K F 1 6X0 8 R CHIP 1 16W 10 1 6X0 8 R CHIP 1 16W 10 F 1 6X0 8 R CHIP 1 16W 10 1 6X0 8 R CHIP 1 16W 10 F 1 6X0 8 R CHIP 1 16W 10 1 6X0 8 R CHIP 1 16W 10 F 1 6X0 8 R CHIP 1 16W 10 1 6X0 8 R CHIP 1 16W 10 F 1 6X0 8 R CHIP 1 16W 2 2 ___ 1 6 0 8 9 15 R CHIP 1 16W 220 F 1 6X0 8 R CHIP 1 16W 150 F 1 6X0 8 R CHIP 1 16W 2 2K F 1 6 0 8 R CHIP 1 16W 5 6K F 1 6 0 8 R CHIP 1 16W 5 6K F 1 6 0 8 R CHIP 1 16W 150 F 1 6X0 8 R CHIP 1 16W 220 F 1 6X0 8 10 15 R CHIP 1 16W 12K F 1 6X0 8 R CHIP 1 16W 12K F 1 6X0 8 R CHIP 1 16W 12
69. Cadmium and Mercury heavy metals which are Bioaecurulative To obtain complete information on the environmental criteria document arder from TCO Development Unit SE 114 84 Stockholm SWEDEN FAX Number 46 8 782 92 07 E mail Internet development tco se You may also obtain current information on TCO S9 approved and labelled products by visiting their website at http www teo info com ad pas ABU EST English gt gt Deutsch EAAnviKa gt Espa ol _ gt Fran ais _ gt Italiano _ gt Nederlands lt Polski lt Turkce 2 AChaperLicener 1 FAB EST ALhapieri cerner fu EST WARNING TO PREVENT FIRE OR SHOCK HAZARDS DO NOT EXPOSE THIS UNIT MOISTURE ALSO DO NOT USE THIS UNITS POLARIZED PLUG WITH EXTENSION RECEPTACLE OR OTHER OUTLETS UNLESS THE PRONGE BE FULLY INSERTED REFRAIN FROM OPENING THE AS THERE ARE HIGH VOLTAGE COMPONENTS INSIDE REFER SERVICING TO QUALIFIED SERVICE PERSONNEL CAUTION RISK OF ELECTRIC SHOCK D NOT OPEN TS REDUCE THE RISK ELECTRIC SHOCK DO REMOVE CAUTION OR BACK USER SERVICEABLE PARTS INSIDE REFER SERVICING TO QUALIFIED SERVICE PERSONNEL This warre user thal uninsulated voltage wahin the unit may have magnitude
70. Default OSM item Setting or circuit operation range value BRIGHTNESS Darkens Brightens Modulates inverter back light 0 MAX CONTRAST Changes output data with digital contrast 0 MAX CONTRAST AUTO Automatically adjusts contrast 2 2 AUTO ADJUST Automatically adjusts H position V position clock and clock phase A 5 za a H SIZE Narrows to the left Expands to the right Changes setting of PLL dividing ratio Adjustment of Clock 0 MAX FINE Changes flickering of the picture Changes clock phase Adjustment of Clock phase 0 MAX CUSTOMIZE Selects Color1 Color2 Color3 sRGB Color5 Native NATIVE AccuColor COLOR 1 9300K Changes to lower Changes to higher Changes color temperature 5000K 9600 9300K color temperature color temperature K 4 x x M tional ti ti ti LEFT RIGHT Moves to the left Moves to the right Changes horizontal image position to where image data 0 MAX Op taken Adjustment of horizontal position DOWN UP Moves down Moves up Changes vertical image position to where image data taken 0 MAX Optional 3 2 Adjustment of vertical position 2 Op p COLOR 2 8200K Changes to lower Changes to higher Changes color temperature 5000K 9600 8200K color temperature color temperature K COLOR 3 7500K Changes to lower Changes to higher Changes color temperature 5000K 9600 7500K color temperature color temperature K COLOR 5 5000 Changes to lower Changes to higher Changes color temperature 5000K 9
71. KI 2 HJMOd NIVW sa uru tH 9 CI 2 vH 8 wd 1 8 lt A tH 9 Nod 3 2 LH 8 004 12 SAWL s ims gt LH S 0d I sa lt 5 8 gigs 9251 E 4 595 15 HEIR Ha s Da i x 5476 i 8838138128 2 5 53 a a lt I 725 ansa G G 6 6 0 Q Q G 0 LG voca ve z LANI NIVIN 62 02 02 02 62 92 62 Le 15 140 78 2 2 gt a a a 4 23838088 888 GPR 525 2 meee 5 2555 m 3 do On T 350 ION il e 0 0 v 2 3 p are amp 29 5 P OSZE 5 9 Sou d 20121 13534 8 8 sau 4 955 Jasa EM udaj Qi easns 4 A TET ERIT AS i en V V HI 521 3 Vi 5 H i l wa sar 2157 NIVW gt 27186 99 2 00 lt B NIVIA g gt GS vsus H lt ws e avs ws ius ONAS NIVW gt issisicus 123 ws CI Hws Le WS L urs P NZZJMOL L z icit 5 8 5 ie 8 _ HALL
72. N e vogasza 8741 vc nes 2 9 4 rst d 1064 i alts e 5 N gt NTI 194 3 INI d 9 8 50 5 L Hg 21 012 ES 72758 4 lo 812 LZ u 1063 ANIOALNG a See 18 N t 11772 8 Sl 15 W YE 8 m 6v lt o SNO a ga L 600 Lil ALLSS 2 HR S 4 RERS t S e 1067 18 1880041 0 G gadl 25 1 A 5 81 8 HA edZ8 m oM oon 9 S m 20637 LO ON lt H e S 4 4 m owe E 3AVS d m 2101 2001 qub LOBHL du 2 2 RALL NIWA OL ASVONOO23S i AdvWldd T 5 Q 109 106 x 27 2244 8 017 106 MS NIVW 206 96 8 cza 8 ii 8 92 9 5 E SLE 5 a 5 5 8 5 8 5 2 i D 29 N ES 5 GRE 845 8 ng 0 8 51 ra 55 eit Ss 545 238 3 9 5 a
73. No VSPF A028 3 Electrical Characteristics 3 1 Input signals Video signal Analog RGB Digital TMDS Composite Sync Negative Positive Sync signal Separate Sync Negative Positive Sync on green 3 2 Signal level _ Vertical frequency _ 754 Video clock frequency 251 espe Sync TTL High level 25 50 Terminated 2 2K ohm to GND Sync TTL Low level 1 08 Terminated 2 2K ohm to GND Analog video signal 6 07 L0 Terminated 75 3 3 Power Supply Input Voltage 90 to 264VAC Frequency 47 to 53 57 to 63Hz Power Consumption max 38W MAX AC Leakage current 3 5mA Inrush current cold start lt 100 lt 90A p 240 3 4 Power management This function conforms DPMS of VESA and International Energy Star Office Equipment program Table 3 4 1 Power Management condition and status for ANALOG Input mode DPMS Display LED E UE 22 V sync On state normal GREEN lt 38W ON ON No display AMBER lt 3W Approx 3sec OFF ON Active off No display AMBER lt 3W Approx 3sec ON OFF No display AMBER lt 3W Approx 3sec OFF OFF Complete No display OFF ow N A N A N A Table 3 4 2 Power Management condition and status for DIGITAL Input mode Display Power Recovery Signals consumption times W j sec DE H Sync
74. OL 0 50 Le N3399 XH 6 GND 6 GND La Add 6 L GD 22 ONASN V 8 ONASH 8 Aad 8 2 SO oad vas L QNO 2 QNO 8 Add n SO ve oad 10S 9 ONASA 9 GAD QNO 9 GND Ge ON G GND G GND Add G y SO 9c ON v Add Y S SD e GND GND GND Add 9 GD 8c zxu 2 100d 2 390 18 Add 2 1 GD 62 zxu L QNO L QNO QNO L GND 05 002r 9UJEU INO oorr oLvEbEdeSFdO 1019euuoo LLVe8edeSrdO HSS O SSt VcLHJ jaued UIEJN LIV I8ZdeSr dO 59 0 502 jaued uonoeuuoo 8 qEJ uoroeuuoo e qeo 01 INO LL 9 d dil LL ASEN 01 01 19539 01 6 6 MS HIMOd 6 8 8 8 Asna L L 1X3N 2 XIOS 9 9 9 S S S r v 1IX3 Y 18534 1431 55 0 2 2 N L L GND L 1017 008 SWEU 0010 LSY LLEdZStd9 f L SSHS 80LWS A LEVBLEdESvdO 0621 29829 0121 40829 eas pJeoq yams PJEOQ uonoeuuoo ANS d ANISALNG JANI d GN9 100 AS
75. Packaging specifications 1 There must be no remarkable contamination or scratching etc 2 The type name must be accurately displayed 3 The Serial No must be attached it must be the same No as the set 4 The unit must be accurately sealed 2 20 2 11 Timing chart lt Preset Timing List gt Timing i Period Sync Back Display HS VS sh EW porch time name 5 ms Tvb Polarity O O O O ms ms 75 i h 2 pe pr pr pas pepe pu zc Saeed epe ss pr perpe pepe pu 2 ooo on aon es as IKA Shoe oe KA EJ coo pp pw pe 7 Sr 0 4 6 3 29 32 3 59 1 74 0 7 25 95 20 0 393 1 13 0 072 18 4 SIG 28 571 3 5 4 0 19 18 15 0 0 086 2 00 11 428 Composite SUNS7 7425 56 59 17 67 1 83 0 22 1 83 13 79 70 04 14 28 0 106 0 035 0 57 13 57 estimation j Dots 1312 136 16 136 1024 Lines 808 6 2 32 768 Frequency 72 67 13 76 1 28 0 32 1 92 10 24 90 50 11 05 0 04 0 014 0 427 10 57 Frequency 21 053 24 83 40 28 3 04 2 8 4 04 30 4 41 38 19 33 0 322 2 376 0 52 16 112 N N under limit Dots 848 64 59 85 640 Lines 600 8 59 13 400 of the preset shown in the above table indicates the timing for confirmation 2 21 2 12 OSM display matrix lt User mode gt Adjustment
76. Teer en SNe F 110 8 FI m ANTSKINA C irt un s 14848 e e ano sis ar a 113 8 Me TN r ones 1 a 2 8 8H S 0 243 D er s 8 gl Qow D amp 4 9 zine er s H INTE ko l ao pepe H 114 8 E T z Lld G 8888888888888 3882222 aaa ETA 11689 fis es EH 822122522 vum 85558855 0024 4886 6686 2 2 113 9 6 S22 5 585528528 55 8685821852855 51212214858 SEK RZ 68888 2 14 8 2 2 iis e 3 g TE 5 oe i 1 4 z 5 1 hiss p 5 113 8 i z L 5 4 i i 818 T i 5 58 555 wit H 3 HERE z RAR 5 S E SERFS 1 JB 85 5 50 208 5 22 ista sfo 333 293333 H31H3ANI WVHOVIG OLLVINIHOS XOSSLQO1 oy pica prawi pon rr sees L MOL L 1 31 szan A018 velu 3 801 A018 L M9L L 9219 11 31991 31 szan a LL GND L L VWIEPLOL
77. and Dust Conditions These defects are inspected under the following conditions Temperature 77 0 9 degree F 25 0 5 degree C Viewing angle Standard viewing angle refer to below figure 0 45degree for inspection with non lighting screen lt 5degree for inspection with lighting screen 500lux for inspection with lighting screen 1000lux for inspection with non lighting screen Brightness control is at its maximum point Distance 300mm refer to below figure Division of Zone Only display area was specified Display peripheral area and case area are not specified Outside light Viewing angle 300mm N 2 LCD Module A area Display Pixel area B area Periphery area of Display area LCD panel area Exclude Display area C area Case area 17 Document No VSPF A028 8 2 1 Inspection criteria Defect Type Acceptable Unit Note Aa area Adjacent Luminous 2 Adjacent Dot pcs Notes1 2 Fault Dark 2 Adjacent Dot R G Horizontal Adjacent 2 G R Horizontal Adjacent Total 3 Adjacent 3 or more Notes3 Luminous Dot Adjacent 3 or more Dark Dot Dots Fault Dot Fault exclude R G B Dark dots pcs Notes 4 Luminous Dots Neighborin Luminous same color Fault distance 6 5mm Each color 2 set Notes 5 Neighboring Dots Fault Closest distance between Nearby Distance 15mm Notes 6 Fault Cluster 2 or more defect dots in pcs Notes 7 5X5 pixels
78. be 0 CENTER OSM TURN OFF 45SEC 2 4 2 OSM operation method lt User mode gt OSM appears when CONTROL button or ADJUST button is pressed The adjustment items are grouped according to category Select the category with NEXT button and select the adjustment item with CONTROL button lt Factory mode gt For factory adjustment How to enter Factory mode To enter the factory adjustment mode press front keys in order of DOWN DOWN UP UP DOWN UP and SELECT during OSM picture is not displayed In another way select DISPLAY mode of adjustment item in INFORMATION of category press RESET button press RESET DOWN and UP buttons simultaneously with RESET WARNING picture is seen gt WARNING picture with red frame appears press NEXT button With operation above the color of OSM frame changes to magenta from cyan and all indications in the factory mode are in English How to return to User mode To return to User mode turn POWER SW OFF 2 2 2 4 3 Configuration of signal input power input section D SUB 1 pin input connector VIDEO 6 JRG JRedGND JI D SUB Host Receptacle Connector 8 JBG BueGND Input signal cable is detachable DVI I input connector VIDEO Signal T M D S Data 2 T M D S Data 2 T M D S Data 2 Shield N C N C No 1 16 6 DDC Clock 8 Analog Vertical 7 23 T M D S Data Clock 9 TMDS Daa i
79. by NEC MITSUBISHI ELECTRIC VISUAL SYSTEMS CORPORATION NAGASAKI WORKS 1 Document No VSPF A028 Document History This document contains electrical and mechanical specification of LCD1550X Notice Please use this specifications after you confirm it is latest specifications you find the difference between common specification and this specification this specification is given priority Design and Specifications are subject to change without notice Date Page Description Approved Inspected NOTE USE RESTRICTIONS AND LIMITATIONS This product is not authorized for use in life support devices or systems military application or other application which pose a significant risk of personal injury Therefore the product shall not be used for such purpose 2 Document No VSPF A028 TABLE of CONTENTS DFAT LE 4 2 General Description Quick L nte ete ee ete edad ere x d cere 5 SER ISO EIC ISTE 6 6 6 6 3 4 Power management 4 6 uu T E 7 28 Eron eont J DELL 7 o 7 4 2 1 OSM EIER 7 422 OSM USER Men a
80. frequency range 50 75 1 Hz Video clock frequency 25 1 78 8 MHz TMDS signal DVI 1 0 compatible GND for 50Q impedance 1 11 141 Video interface peripheral circuit Video interface periphery D SUB connector R2 J201 G2 R 74F14 SA5V 74LCX14 D3 3V V IC303 A5V 2L Video _02 p i buffer x B2 gt DVI I connector f TM3 3V J200 receiver D3_3V G VIN2 B VIN2 R VIN1 G VIN1 B VIN1 AV2 AH2 AV1 ASIC IC400 T _ P_TMDS ED Micro SCDT computer PDO 1C102 SEL 2 SEL 1 SEL HS2_SG2 C S H2 C S V2 S GH2 C S H1 C S V1 S GH1 SEL HS1_SG1 74LCX14 is used for the waveform rectification and level conversion 5V system to 3 3V system 1 12 1 4 2 Horizontal vertical synchronizing signal input circuit The horizontal vertical synchronizing signal input from an external source is terminated to 2 2kQ and then passes through IC201 74F14 which has hysteresis characteristics The separate sync and composite sync are input into the synchronizing signal 332 HS 22kQ 1000 HSYNC 431 47pF 1000 VS 1000 5 431 22 We 47pF i 1 13 1 4 3 Composite sync V separation circuit V signal sampling circuit Composite sync i HS or GS To microcomputer indicates the input Ch 1
81. function to 100 SHARPNESS Has Adjusts horizontal outineenforementregiter of ASIC horizontal outline enforcement register of ASIC 0 127 EXPANSION Narrows to the Expands to the Changes pixel number for taking picture data Note1 H EXPANSION horizontal direction horizontal direction EXPANSION MODE Narrows to the Expands to the Changes line number for taking picture data 1 to 2 time s Note V EXPANSION vertical direction vertical direction VIDEO DETECT Enters into sub menu Selects FIRST DETECT LAST DETECT NONE FIRST DETECT DVI SELECTION Enters into sub menu Selects DIGITALIANALOG DIGITAL 2 24 OSM POSITION Moves to the left Moves to the right Changes OSM display position horizontally 50 LEFT RIGHT OSM POSITION Moves down Moves up Changes OSM display position vertically _ 50 OSM TURN OFF Enters into sub menu Select how long the monitor waits after the last touch of a button to shut off OSM control menu The preset choices 45 SEC are 10 20 30 45 60 and 120 seconds OSM LOCK OUT Enters into sub menu Locks out cancels OSM control Press both control keys for LOCK OUT then press both Cancel control keys again for cancel NOTIFIER FACTORY PRESET Executes Resets all OSM control settings back to the factory settings Except for LANGUAGE DISPLAY MODE Indicates information about input timing used etc MONITOR INFO Indicates model name and serial number BRIGHT LIMIT Darkens Brighten
82. if i V9 1 2455 ak b s Z z Wet AZ 1 IN SN ga 190599 gt 19SIZIdLINTB 2093 U speres EJ 2 ma e 2091 T 2 a 3 BL EWS Hd 888 gt a 21 2 gt 109 1091 2 _ 58 L BAR 3 19SLZLdLLNTA Se SP Si F NGTANYd 3 2 4 8181 pn rapie oy CZ keta LCD1550X jii dun 53200414 m m mmu O b O Y 228 228 10000000 100000 21411141 8 8 8 8 TED 888 i isses bia i el Ha ez T X88L 9 T X001 MOL L Si 4 P2957 maL L q P 89S MOL L Si 22 ra o CT 1 883 ig i 8 r
83. microcomputer 1 8 4 2 Lamp drive circuit section The lamp is driven with the self exciting resonance circuit royer circuit For dimming the PWM Pulse Width Modulation method that changes the duty ratio by turning the switching transistor base current ON and OFF is used Thus the brightness can be changed with the Duty PWM method of PWM pulse signal J703 pin 7 DUTYCINV from ASIC C704 SL6 3kV 15pF J DUTYCINV 1 44 1 8 4 3 Protection circuit section The protection circuit is configured of a lamp current detection protection circuit lamp current limiter that detects errors by detecting the current in the lamp return wire and setting a threshold for the upper and lower limits of that value In addition this circuit has an overvolt age protection circuit that detects the power voltage value and a fuse A timer circuit is pro vide before the protection latch circuit and malfunctioning of the protection circuit by the transient response and noise is prevented By using individual return wires for each lamp errors can be detected in each lamp This allows the ballast capacitor s short circuits and the open state for one lamp to be detected 1 8 4 3 1 Lamp current detection protection circuit lamp current limiter C703 R713 VY SL6 3kV 15p J R712 IC701 comparator D706 Lamp 1 12V O C PIOS Timer circuit C716 D717 1 Outline of operation The current that flows to lamp 1 s re
84. or 2 74LCX14MTCX 12300 IC303 D3 3V ASV To ASIC 74ACT15 74LCX14MTCX IC301 IC304 1C300 12303 LPF input step HS GS When 74214 0 5V 15 20mA The LPF 74ACT157 and 74LCX14 input impedance is high so if it ignored the current led in at 74F14 will be 4 8mA 5V 1K 33 Q and the maximum value at HS and GS Lo level will be 0 66V 0 5V 75F14 V Max 339 x 4 8mA 74LCX14 V 0 72V Min at VCC 3 3V conversion gt 0 66V 74ACT157 V 0 8V Min gt 0 66V LPF output step 74LCX4MTCX threshold level at VCC 3 3V conversion Min Max 1 38V 2 50V 0 72 1 74V The V signal sampling circuit s constant was set in consideration of the 74LCX14MTCX thresh old level fluctuation Confirmation with the over range of input signal SPEC timing confirma tion with different polarity etc 1 14 1 4 4 Sync On Green synchronization separating circuit S G Sep circuit As comparator decoupling capacity is large For slicing Input capacity ptf must be small Composite sync output 2SK360 s C210 C242 Q204 Q207 47u 2200 D Video input Green 1Vs For bottom 1 36V L clamp dV gt 100KQ 4 pese Sj Sma f characteristics must be good i d slice level 1 36V clamp level Video input cutoff frequency fon 1 2nCR 1 2x 10uF 100kQ 100k
85. power 5VDC Monitor internal power Microcomputer port WP D SUB connector side ANALOG E2PROM Lo Lo Lo s R disabled W disabled Hi Lo Lo R enabled W disabled X Hi Lo enabled W disabled X Hi Hi R enabled W enabled 1 29 1 6 Power peripheral circuit PWB MAIN power configuration 12 0V Vin 14W 5 0V 1 6A PANELSV for panel power 1300mA 3 3V 0 8A PANEL ASV analog synchronizing signal system DDC periphery 200mA TMDS system 300mA 3V ASIC I O system synchronizing system 200mA M3 microcomputer system periphery 90 REG A2_5V ASIC analog system 200mA P_SUSP1 D2 5V ASIC internal logic system 300mA P_SUSP2 Microcomputer D2_5V ASIC PLL system 10mA 10102 P_SAVE PRO_DLY P_INVT 1 30 1 6 1 DC DC converter and panel power specifications DC DC specifications Electrical characteristic Standards Min Typ Max om Input voltage Vin voltage 11 0 12 0 13 0 V Input current Vin current 1200 mA 5V system voltage 5 00 5 25 5 50 Output voltage 3 3V system voltage 3 20 3 40 3 60 5 5V system voltage 5 40 5 70 6 00 5V system voltage 1600 mA Output current 3 3V system voltage 800 mA 5 5V system voltage 200 mA Panel power specifications Electrical characteristic Standards jem Min Tvp Max
86. restarted by turning the AC power OFF and ON eee 8sssssssssssssssss slo TYP l ea Example of waveform of pin 4 at latch circuit operation 1 2 4 2 Overheat protection circuit This circuit operates the latch circuit when the hybrid IC s frame temperature exceeds 135 C MIN The temperature is actually detected by the control circuit element Since MOSFET and the control circuit element are on the same frame this will also function when MOSFET overheats 1 2 4 3 Overvoltage protection circuit This circuit operates the latch circuit when the voltage of pin 4 exceeds 25 5V typ Basi cally this functions as the overvoltage protection for pin in the control circuit Normally the pin is supplied from the transformer s secondary coil This voltage is proportional to the output voltage and also functions for the secondary output overvoltage when the control circuit is open etc 1 UVLO OVP Vin on 17 5V gt Vin off 10V T Vth 255V i Internal Bias m Delay CE TSD tl Ta 155 C REG 1 Tu v1 PWM Latch dg D OSC gt s i Tcoff 5045 2 3 R aedi eu RG gt 1 Drive o l INH Comp 2 2 INH Latch a U 3 5 QR Vth 1 45V 5 Comp Z
87. s LL ILSSESSL ac 7617020 x 8 3 isa E 4 gt 5 e 553 5 ER 1 5 m z H 1 VX3S LVL a t T 4 N AS 17 1 1 s 0 4 2 ax TJ d 3 2513 8 30153428 gt 1 eer 839 5 4 2 3338 88 8 a s fe ef U x gt 8 174109 d 2 8 05256 2542 lala F 2S SIES lt px Sh 2 LQ SNNVH2 d P dGL NIE 91S YOLI gt 845 va 1 9455 Ki x 10H 1 4 34 p 2014 lt 8 4 i A 5 gt 23 3 1 8 8 8 23 8 ong 7749 AXE 976 019 G 845 1 c WYSZYOZN f T EL ed wes 1 8106252 EI tata KL 9 20 0 982 8 1070 w 1 V33evi210 80 09 2 p S 2 n 000 OND ONO 4 5 OND 1 g i 8 5 18 5 2 a 3 lt L lil lant r ezz mori S M Hd 818 sour MS dMd WVHOVIQ OLLVINIHOS XOSSLQO1 ONO A A e 5 8MS 3 3 811HMS O o 9 ee 811 5 Z08MS 9 2 9 te ave 811HMS 08MS 2 09
88. signal presence judgment When using analog signals it is judged that an input is present when the input signal judgment conditions shown below are satisfied The input signal presence judgment is carried out con stantly To comply with automatic input signal Ch switching the input signal presence judg ment of signals not displayed or selected DVI I amp D SUB is also carried out constantly The frequency is measured separately by hardware such as the microcomputer counter and ASIC counter hardware so there is no problem in the processing speed If AV ASIC 10Hz Results of simple frequency measurement by ASIC Then Q or X e If C S H u COM gt 10kHz Free run u COM counter interrupt with 1H Interrupt cycle is e If C S V u COM gt 10Hz Free run u COM counter interrupt with 1V Interrupt cycle is If S G H u COM 2 10kHz Free run L COM counter interrupt with 1H Interrupt cycle is indicates the video input signal Ch The DVI I connector side is 1 and the D SUB connec tor side is 2 Min 2msec Then or X 1V Then Q or X Min 2msec Then or X Input signal judgement condition AV C SH C S_V S G_H Input signal x x 5 x x S G O O x x H V Sep x O x S G 5 x x S G X O C S O O V Sep O 5 Other than the above No input signal 1 18 euis yndu ON D
89. state of the front power switch display input signal Ch and SCDT signal If there is no digital signal input SCDT Lo the display input signal Ch is analog DVI I A or D SUB or the front power switch is OFF the TMDS receiver s output buffer power is low ered PDO Lo excluding the SCDT output by the PDO terminal Normally the input signal presence is judged constantly However during the PMS mode the microcomputer sends the PWM signal to the PD terminal TMDS receiver power down at Lo to control the power con sumption of TMDS receiver so the power consumption can be reduced according to the On duty intermittent control Note OSM cannot be set for the mass production F W The PD PWM cycle is fixed to 500msec and to 50msec for the period PD is Hi The PD PWM cycle and Hi interval are determined considering the fact that for the power consumption during power save the Hi interval rarely drops below 50msec In addition the SCDT software filtering interval feedback time from power save time for SCDT to start after DE is input and the time to start counting after PD is turned ON and PLL starts are also considered Software filtering is used to prevent malfunctioning in the PMS mode considering the possi bility of noise in SCDT signal output of the TMDS receiver Display Microcomputer Microcomputer Microcomputer Microcomputer Front power SW input signal input port output port output
90. this and the EEPROM set in the AO address is validated OSM DVI SELECT Rw A2 DIG A2 ANA DIG EEPROM address ANA E2PROM ADDRESS When DIGITAL is selected Lo Hi Lo AO valid A8 invalid When ANALOG is selected Hi Lo Hi A8 invalid AO valid When the monitor power is ON the value DIGITAL or ANALOG set in the initialization EEPROM is set The X9116WM 2 7 control is set in the following order with the 3 Wire Serial Interface U D INC CS When DIGITAL is selected for DVI I Set value status value Remarks 1 A2_DIG A2 ANA PORT A2_DIG A2_ANA Previously stored value Settling confirmation 2 W PORT U D Lo decrement Tap slide direction 3 W PORT INC Transmission Lo Lclock x 16 times Number of tap slides 4 R A2_DIG A2_ANA PORT A2_DIG Hi A2_ANA Lo Setting confirmation 5 W INC CS PORT INC Hi CS Transmition Hi clock Tap position store When ANALOG is selected for DVI I Set value status value Remarks 1 2 DIG A2 ANA PORT A2_DIG A2_ANA Previously stored value Settling confirmation 2 W PORT U D Hi increment Tap slide direction 3 W PORT Transmission Lo clock x 16 times Number of tap slides 4 R A2_DIG A2 ANA PORT A2_DIG Lo A2_ANA Hi Setting confirmation 5 W CS PORT INC Hi CS Transmition Hi
91. to Portrait ar counter clockwise from Portrait ta Landscape Figure R 1 To toggle the orientation of the menu between Landscape and Portrait modes press the RESET button while OSM menu is aff Tilt and Swivel Grasp hath sides of the manitar screen with your hands and adjust the tit and swivel as desired Figure TS 1 Remove Monitor Stand for Mounting To prepare the monitor for alternate mounting purposes 1 Disconnect all cables 2 Place hands on each side af the monitor and lift up to the highest position Figure RL 1 3 Place monitor face down on a non abrasive surface Place the screen on 50 mm platform so that the stand is parallel with the surface Figure 5 1 4 Press the w portion with your index finger and at same time slide the lower stand cover Figure 5 2 Next lift up the stand remove the lower stand cover then go on ta remove the upper stand cover Figure 5 3 Return the stand to its original position remove the 4 screws that connect the monitor to the stand and lift off the stand assembly Figure 5 4 English 6 ABU EST 5 Reverse this process to reattach stand NOTE Use only VESA compatible alternative mounting method Figure RL 1 Figure T amp 1 English pi Enjih T EST Figure 5 1 Figure 5 2 Figure 5 3 Figure 5 4 Caution Please use the attached screws 4005 when mounting
92. 0 0 03 0 03 Custom 5000k 9600k COLOR setting 5 4 Geometry BEZEL L1 L2 L3 L4 0mm Display area 5 5 Rotations H4 h3 H1 hi Omm H2 h2 Omm H3 h3 Omm 14 Omm Display area 11 Document No VSPF A028 6 Mechanical Specifications 6 1 Cabinet Tilt Base White Cabinet FPC ABS Flame class 5VB Molded Tilt base FPC ABS Flame class 5VB material TA Cabinet FPC ABS Flame class 5VB Tilt base FPC ABS Flame class 5VB Cabinet Mist White iMitsubishi color NO B N CO72 o Dark Roof Gray iMitsubishi color NO 084 j Tilt Swivel Down 5 degree Up 45 degrees Right Left 173 5 degrees Am W 1845 2 H 379 7 434 7 ID E201 7mm See Fig 1A US White Fig 1A BK US Black Fig 1B EU Control Switch See Fig 2A US White Fig 2A BK US Black Fig 2B EU 2A US White Fig 2A BK US Black Fig ig 3A US White Fig 3A BK US Black Fig 6 2 Rating label See Fig 4A US White Fig 4A BK US Black Fig 4B EU 6 3 Carton box Paper material double wall corrugated fiberbord Carton box print See Fig 6A US White Fig 6A BK US Black Fig 6B EU Outer Dimension W 426 mm H 480 mm D 290 mm See Fig 5A Packing style See Fig 7A US White Fig 7A BK US Black Fig 7B EU 6 4 Weight Net with Stand Approx 6 0kg Net without Stand Approx 3 5kg 6 5 Accessories Europe See Fig 8 1B Except U K AC Power code See Fig 8A Se
93. 0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP CH50V 22P J 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 2 15 C CERAMIC CHIP CH25V 1000P J 1 6 0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP CH50V 470P J 1 6 0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP CH50V 100P J 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP CH50V 470P J 1 6X0 8 C CERAMIC CHIP B25V 473 K 1 6X0 8 C CERAMIC CHIP CH50V 100P J 1 6X0 8 C CERAMIC CHIP B25V 473 K 1 6X0 8 C CERAMIC CHIP CH50V 100P J 1 6X0 8 C CERAMIC CHIP CH50V 470P J 1 6 0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP CH50V 100P J 1 6 0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B25V 473 K 1 6X0 8 C CERAMIC CHIP CH50V 100P J 1 6X0 8 C CERAMIC CHIP B25V 473 K 1 6X0 8 C CERAMIC CHIP CH50V 10
94. 00msec PRO_DLY e Power board control The microcomputer pin 53 P_SAVE is used to control the switching of the power board s PRC mode and resonance mode The sequence at the power s rising edge is shown below During power save operation takes place at the PRC mode having good power efficiency However as a high load current cannot be passed maximum approx 1A at 12V the resonance mode in which a load current can be applied is used normally Power ON IPRC MODE RESONANCE MODE MODE RESONANCE MODE Microcomputer signal Sio Full load Starid by J Full load P_SAVE Inverter 1 37 Power management control FET SW and regulator ON OFF control etc 1 At AC power ON System reset Microcomputer initialization P ON P_SUS ON ASIC initialization ASIC power save mode transfer 2 Front power switch ON amp power save recovery P_SAVE ON resonance mode ASIC power save mode cancel P PANEL ON black mask Delay P_TMDS ON Inverter ON control P_INVT ON PRO_DLY output DUTYCINV output Video buffer ON SEL_1 ON or SEL_2 ON during analog 3 Front power switch OFF Video buffer OFF Inverter OFF control P_PANEL OFF ASIC power save mode transfer P_SAVE OFF PRC mode P_TMDS OFF 4 Power save transfer Video buffer OFF Inverter OFF control P_PANEL OFF ASIC power save mod
95. 01 1 102 10204 103 CP410P102 04 1104 CP410P102 01 1 106 CP410P102 01 1107 _____ CP410P102 01 L202 CP410P102 01 L203 CP410P102 01 1204 410 041 03 1 205 CP410P041 03 L206 410 072 08 1 207 CP410P102 01 L208 CP410P102 01 L209 CP410P072 08 L210 CP410P102 01 L211 CP410P072 08 L212 ___ 410 072 08 L213 410 072 08 214 410 102 01 JB L215 410 072 08 L216 CP410P102 01 L218 CP410P102 01 121 410 041 03 122 CP410P041 03 L300 CP410P102 01 L301 _____ CP410P102 01 L302 CP410P102 01 L303 CP410P102 01 L305 CP410P102 01 L306 410 10201 37 CP410P102 01 L308 CP410P102 01 L400 410 079 01 L401 410 79 01 L402 410 079 01 443 CP410P102 01 1404 CP410P102 01 L405 CP410P102 01 COIL CHOKE CHIP 100MH MI COIL RF FLC32CT 1ROM MI COIL CHOKE 7212M 101K LXA595W MI COIL CHOKE 7212M 101K LXA595W MI LINE FILTER SS11V R10093 _ LCD1550X LINE FILTER SS11V R10093 LCD1550X COIL CHOKE SBCP 11330H LXA550W COIL CHOKE SBCP 11330H LXA550W FERRITE CHIP BK1608HS102 TRANSISTOR TRANSISTOR CHIP 25 3545 2 KORR TRANSISTOR 2SA1462 T2B V34 FET MOS CHIP 2SK360 E IGE TRANSISTOR 28C3518 L LXA595W TRANSISTOR 2SC3518 L LXA595W TRANSISTOR DTC143EKA T LXA585W 7 15 TRANSISTOR DTC143
96. 01 CP103P497 01 CP103P114 00 CP103P102 08 CP103P107 02 CP103P491 06 CP103P102 00 CP103P492 00 CP103P497 01 CP103P107 02 CP103P104 04 CP103P107 02 CP103P491 06 CP103P494 04 CP103P494 04 CP103P494 04 CP103P491 06 CP103P491 06 CP103P494 04 103 491 06 R CHIP 1 16W 100 8 15 20 20 20 gt gt gt 20 23 23 00109 z z z 2 gt 20 2 I u R 162 R 163 R 164 R 165 R 167 R 169 170 20120 Bo olojo gt gt gt 20123123 jee 00109 z z z ojojo 70 70 0 172 173 174 175 L100 CP 103P497 01 1105 CP103P497 01 R 100 _____ CP109P183 08 R101 CP109P183 08 R110 CP103P102 00 R111 CP103P103 06 R 112 CP103P102 00 R113 CP103P103 06 R114 CP103P103 06 R115 CP103P103 06 R 116 CP103P102 00 R117 ____ CP103P493 06 R118 CP103P493 06 119 CP103P102 00 R 121 CP103P494 04 122 CP103P492 00 123 03 03 124 CP103P492 00 125 CP103P492 00 126 CP103P492 00 127 CP103P492 00 128 CP103P492 00 R129 CP103P492 00 R130 CP103P492 00 R 131 CP103P494 04 132 CP103P494 04 133 CP103P497 01 134 CP103P497 01 135 CP103P497 01 R136 CP103P491 06 R137 CP103P491 06 138 CP103P494 04 R139 CP103P494 04 R140
97. 01 PACKING CASE LCD1550X US CP859C233 01 ACCESSORY CP871C190 9 LCD1550X US CP242C289 02 JACPOWER CORD CP242C290 02 __________ NSZ2ZJOZU UKIMT 720 107 02 BEZEL UNIT CP700A270 1 LCD1550X EU MI 802 393 03 PACKING CASE LCD1550X EU CP859C233 02 ACCESSORY CP871C191 1 LCD1550X EU 15 15 ALL PARTS LIST MODEL NO LCD1550X BK C CERAMIC CHIP B50V 103 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B6 3V 105 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B6 3V 105 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP CH50V 100P J 1 6X0 8 C CERAMIC CHIP B6 3V 105 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B50V 472 K 1 6X0 8 C CERAMIC CHIP B16V 1
98. 04 K 1 6X0 8 C CERAMIC CHIP B6 3V 106 K 2 0X1 25 C CERAMIC CHIP B50V 472 K 1 6X0 8 C CERAMIC CHIP CH50V 47P J 1 6X0 8 C CERAMIC CHIP CH50V 47P J 1 6X0 8 C CERAMIC CHIP B6 3V 105 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B6 3V 105 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 472 K 1 6X0 8 C CERAMIC CHIP B50V 472 K 1 6X0 8 C CERAMIC CHIP B6 3V 106 K 2 0X1 25 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 1 15 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP CH50V 47P J 1 6X0 8 C CERAMIC CHIP CH50V 47P J 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 562 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 562 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 562 K 1 6X0 8 C CERAMIC CHIP B50V 103 1 6X0 8 C CERAMIC CHIP B50V 103
99. 08 CP410P102 01 L400 79 01 1401 410 079 01 L402 79 01 L403 CP410P102 01 1404 CP410P102 01 L405 CP410P102 01 w COIL CHOKE CHIP 100MH MI COIL RF FLC32CT 1ROM MI COIL CHOKE 7212M 101K LXA595W COIL CHOKE 7212M 101K LXA595W MI LINE FILTER SS11V R10093 LCD1550X LINE FILTER SS11V R10093 LCD1550X COIL CHOKE SBCP 11330H LXA550W COIL CHOKE SBCP 11330H LXA550W ERRITE CHIP BK1608HS102 ERRITE CHIP BK1608HS102 ERRITE CHIP BK1608HS102 2SA1037AK R 25 1037 DTC114EUA DTC114EUA TRANSISTOR CHIP 25 2412 25C2412K R 2 2412 DTA143EKA T LXA585W DTC114EUA FET MOS CHIP 2SK360 E IGE DTA143EKA T LXA585W 2SA1462 T2B Y34 DTC114EUA 25 3545 2 KORR 25 1462 2 34 5 25 360 2SC3545 T2B KORR TRANSISTOR CHIP 2SC3545 T2B KORR RANSISTOR CHIP 2SC3545 T2B KORR RANSISTOR CHIP 2SC3545 T2B KORR RANSISTOR CHIP 2SC3545 T2B KORR RANSISTOR CHIP 2SC2412K R TRANSISTOR CHIP 2SC2412K R 25C2412K R 25 2412 DTC114EUA 25 2412 TRANSISTOR CHIP 2SC2412K R TRANSISTOR 2SC3518 L LXA595W TRANSISTOR 25 3518 LXA595W TRANSISTOR 2SC3518 L LXA595W TRANSISTOR 25 3518 LXA595W TRANSISTOR DTC143EKA T LXA585W CP260P472 01 TRANSISTOR DTC143EKA T LXA585W Q711 CP260P327 01 MOS FET 2SK1133 7115 TRANSISTOR DTC143EKA T LXA585W TRANSISTOR DTA143EKA T LXA585W Q718 CP260P473 01 TRANSISTOR DT
100. 0D2 10LC gt i SUMBOL __ DESCRIPTION SPECIFICATION TH701 CP264P592 01 THYRISTOR CROSAS B LCD1550X LCD PANEL 289 022 01 ILCD MODULE TX38D26VCOCAA _ LCD1550X erezoB sio JASSY PCBPOWER 00 ___ 2 01 ASSY PCBHNVERTER 920 279 01 920 280 01 CP700A271 02 JCOVER REAR PC ABS CU6800 LCD1550X MI CP702B058 02 JCOVER VESA PC ABS CU6800 LCD1550X MI CP702B059 02 PC ABS CU6800 LCD1550X MI CP702B060 02 JCOVER POWER PC ABS CU6800 LCD1550X MI CP702B061 02 PC ABS FR3005 LCD1550X BK ME CP722A008 02 CP722A009 02 CP722A010 02 LCD1550X BK ME 442 004 02 442 004 02 442 004 02 246 365 02 246 365 02 CP442P001 01 USE CLIP 00351 51 CP442P001 01 USE CLIP TPOO351 51 CP285P030 01 RYSTAL 7355 10 0 2 LXA580W CH330H509 09 CH330H509 09 CH600H179 09 CH650H209 09 je lt m 2 gt u ae v Q O lt 2 2 0 m U U gt m o lt c 901 902 5801 6802 2901 F902 X 100 mlm gt gt 232 A3 aa m m 2 2 gt gt rir ojojoj n n v Ojo 70 70 U U m m 212 2012 mim 0 2 iri 0 c CP081P001 01 CP096P004 01 96 004 01 CP096P012 01 CP096P012 01 CP210A271 01 CP210B096 01 2108097 01 AYER CP210P001 PWB INV
101. 0P J 1 6X0 8 C CERAMIC CHIP CH50V 470P J 1 6 0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP CH50V 100P J 1 6 0 8 C CERAMIC CHIP CH25V 1000P J 1 6 0 8 C CERAMIC CHIP CH25V 1000P J _ 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP CH50V 470P J 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP CH25V 1000P J 1 6 0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C ELE CHIP 16V 100MH F55 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C ELE CHIP 16V 220MF F80 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B6 3V 105 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B6 3V 105 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 102 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B6 3V 105 K 1 6X0 8 C CERAMIC CHIP B6 3V 105 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B6 3V_106 K 2 0X1 25 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B50V 333 K 2 0X1 25 C CERAMIC CHIP B6 3V 105 K 1 6X0 8 C CERAMIC CHIP CH50V 330 __ 1 6X0 8 C CERAMIC CHIP B50V 333 K 2 0X1 2
102. 1 Input timing No 14 60kHz 75Hz XGA75 with signal generator and set the pattern to full white 2 Set BRIGHTNESS to MAX 220 and CONTRAST to CENTER 128 with OSM and confirm that the color coordination at the center of the liquid crystal panel is as follows with COLOR COMPENSATION is off NATIVE 0 305 0 03 y 0 324 0 03 3 Confirm that the value of x and y at the center of the liquid crystal panel is within the values specified below with BRIGHTNESS is set to MAX 220 and CONTRAST to CENTER 128 when each COLOR is selected with COLOR SELECTION AccuColor If out of specification compensate with each color temperature Colori 9300 j 0 281 0 015 0 290 0 015 Color2 8200 j 0 290 0 015 0 300 0 015 Color3 7500 j 0 300 0 015 0 310 0 015 SRGB 6500 5 0 313 0 010 0 329 0 010 Color5 5000 5 0 345 0 015 0 352 0 015 2 8 2 3 Panel inspection luminance color coordination defect 1 Luminance and color coordination Input the confirmation timing with signal generator and set the picture pattern to full white 0 7Vp p Measure the luminance and color coordination with a luminance meter and confirm that the values are as shown below For measuring of optical parameters carry out the measurement where there is little effect from outer light in a dark room etc and the panel should be heated run for 30 minutes or more 384 Measurement point 1024 768
103. 1 25 1 5 2 DDC2BI DDC CI function only DVI I connector side 1 28 1 5 3 EDID data write protect control function 1 29 1 6 Power peripheral 1 30 1 6 1 DC DC converter and panel power 1 31 1 6 2 DC DC output voltage design sheet 1 32 1 6 3 Power rising falling edge sequence control function 1 37 TGA RESET CINCU a l l tem t 1 39 1 7 interface aie A A s 1 40 1 7 1 Switch substrate interface nanna 1 41 1 8 Inverter CU 5 1 42 148 1 Basic configuration eee nes epe eu mie d 1 42 1 8 2 Circuit block diagram nanna nanna tarana 1 42 1 8 3 Input output terminal functions nn 1 43 1 8 4 Detailed description of each circuit 1 44 1 8 4 1 Power input section eene 1 44 1 8 4 2 Lamp drive circuit 1 44 1 8 4 3 Protection circuit section nr 1 45 1 8 4 3 1 Lamp current detection protection circuit lamp current limiter L nn 1 45 1 8 4 3 2 Overvoltage protection circuit nn 1 45 1 8 4 3 3 Protection circuit operation timer circuit malfunction prevention 1 46 1 82 Ese hu a RIGA ORNE LARA 1 46 Adjustment 2 1 2 1 APPliGAtiOM A 2 1 2 2 Measureme
104. 1 z 48 z 98620 3 A Ms 5 5 S 49 rz 106009 gt m i575 Y S RIS 5551 S 5 AOSZHVGL i S1Z NI ANIOALNG a Bim RNA FSS xu SNS 6 z Le gt 1102 I Fa VE 8 60 lt osvo j a SE 600 Lil ALLSS 1 eis H S 2 c ss d 5 1061 18 1860041 16 1960081 Bx 458 5 allm id 8 HA dz8 ING LL wy Sao ove lt 5 5 2181 2001 E S lt LOBHL gt 4 NIVW ASVCONOOS AUVWIHd i 5 09 106 0LN LO6P MS NIYW 206 L06r jix i vm m u3MOd NIVA dMd WVHDVIG OLIVW3HOS XOSSLQO1 REMI L eee RE ae leg 8575 d L L idsns d L Le l LAAS A 5 M L a 19SLZ LdLLNTB z ET Tz s STI aj sE de 74 s T 2178 8 8 waal A 9 19SLZLALINIA 8091 A O p M W lt m lO 913 1 913
105. 2 A 5 z RAW sy z 5 8 Bez w Lie ioi HL 05 k al w 25 Za 3 EIS Sax 5 a 5 5 E 7 2855 3 zs 8 s IN WINLY P 1688012010 i g 1 pm 3 83 oozy 809 5 ils 1 3 38 mm 5 i 5 5 2 w lt lt 8 RY 2 5 s 3 ENS 5 z 5 5 480 yw 3 venum b g 853 15 1 0906082 5 4 akeo 2 m myy 1 2 SY 08912818 92 185 E M 120 8027 2 8 3 Y oos e 8 53 MI B ONASH V 5 G 3 gt 2 KIETEN w 2 2 i cus o4 a s T NIIHD A Raq e 2 MME iud 248 gue 000012 oxa 2 49012 42x 12 a QNO Ap pe a be Sesh T iessrszjond 5 1505 50 THOTT 7 7 4 exa fao wh anne oxa 3 8 Di 1 d 3 BONIdLH al sig ee m F 48 11 wo 5 i im is 5 ag IM suos vie 5 Wa s t 5 wm Y sticks s3 v WISK 5 b N3389 23 7 nue ca 8 a d N3389 8 3 7 sige iso aaan omman BYE g G ASAR wee 99 6 vrina tyg z pad vas me wi orina yy 2997195 waa wer 155 2 2 n L MN zx 3 9 UI 5 lt 089 12 v4 8 sone 2020
106. 24 TM D S Data Clock 14 5VPower 5V Power Analog Ground analog R G and B return Ground return for 5V HSync and Vsync Input signal cable is detachable Power code is detachable DVI Compatible Host Receptacle L N Host Receptacle AC inlet 2 3 2 5 PWB mechanism and appearance inspection 2 5 1 Visual and conductivity check 1 There should be no cracks remarkable contamination or solder faults on the PWBs 2 There should be no remarkable lifting or inclination of the parts on the PWBs and the parts should not be in contact with other parts 3 There should be no short circuit across the power supply and GND on the PWBs 2 5 2 Mechanism and appearance inspection 1 All connectors receptacle pins should be clamped firmly and fully inserted 2 Lead wires should not be pressed against any edge of metal parts 3 Lead wires should not be in contact with high temperature components 4 Metal parts should have no scratch remarkable stain dent or bend 5 Liquid crystal display should not be scratched or contaminated 6 There should be no abnormality with the front switch operation 7 There should be no wave patterns seen on the liquid crystal panel when the front switch is pressed 8 The picture position and picture inclination should sa
107. 3 ONASH lt I gt KOGA 1 g 2 65 is a 2 Z 5 Ss s 5 8 822888888 98888 S T T miscisris 9 9 86 8 2 3 E es 9 a 46 Q Q Q Q f e T nk 2 8 a a 3 Siv Z SLv z SLv z Siv Z siv Z siv Z SLv z SLv z OW NIVA 8Md INVHOVIG OLLVW3HOS XOSSLQO1 IIL SSUS 80 LAS 8 d w i S B sow z z z 3 5 5 Ae s s CEG ens ao Fin 218 ie 5 ki g z 3 1 3 2 IAC WO 2 2 na gt L 113 9 u gt
108. 4 02 E 902 CP442P004 02 G801 CP246C365 02 G802 CP246C365 02 F901 442 001 01 F902 442 001 01 100 CP285P030 01 CRYSTAL KCO 735S 10 0MHZ LXA580W CH330H509 09 CH330H509 09 CP081P001 01 CP096P012 01 CP096P012 01 CP210A271 01 CP210B096 01 CP210B097 01 CP210C100 01 CP223B007 01 CP223B008 01 JINSULATOR BOTTOM N 7 T0 5 LCD1550X MI CP231D013 01 TUBE UL LCD1550X MY CP242C293 02 SIGNAL CABLE SC D801 LCD1550X CP242C294 01 JSIGNAL CABLE SC D830 NSZ2102U CP246C428 02 CP246C428 03 CP246C428 04 CP246C434 02 CP246C439 02 CP442P004 02 CP540D077 01 CP553D007 04 CP554D027 01 JGASKET EMI LCD1550X MI CP554D028 01 JGASKET EMI LCD1550X MI CP580A118 01 JSHIELD COVER SECC C 16 16 0 8 LCD1550X CP590D099 01 RADIATOR A6063S T5 LXA595W CP593A164 01 HOLDER PCB SECC C 16 16 8 LCD1550X CP669D016 07 JSCREW TB BIND W 4X10 461 005 CP669D041 01 JSCREW HEX JFS 4S B1WM FS6605K CP669D074 01 JSCREW TB SEMS 3X8 LXM510J CP669D089 01 JSCREW SEMS M4X8 LXA550W CP669D104 02 CP669D104 02 CP669D113 01 CP669D114 01 CP669D118 04 SCREW TB BIND 3X12 LCD1550X CP669D118 04 CP669D502 02 CP677D020 01 CP677D020 02 CP680D009 01 CP775C370 01 CP775C370 02 CP803A109 01 CP829D019 01 CP831C047 01 QX0962462 07 14 15 E900 442 004 02 E901 442 004 02 E902 442 004 02 FG801 CP246C365 02 FG802 CP246C365 02 JF901_ 442 001 01 F902 CP442PO01 01 100 CP285P030 01
109. 40005 ALFIIdv zZ NI NOISN3QMWIG L3MOVf L SIN TIVOS 318VO 1VNDIS X0SSIGO l Ti Ti 0010 Sa w L D A EVA Ha Lor SO WLP 20 17 062 PIOUS S TA dp 22 0 4 1 22 ole ooz pieius 9 0 S a w 610 R 06 0 5 p 8 O ta t 081 red Sawi tt Os 910 09 AS 10 punoo 910 091 9 FLO N 20 pias L ea LL0 RO LL URI 1 ea L 0 0 H N E 00 eea SGW L Bj 80 08 OL 9 o 9 SO os vo Ov pies p z eea SGW O x 9 i z eq sgWil B zo t NZ t Bled sqwi L 7 1511 ONIHIM ANG 9JIUM 7 10 02 Ov v ON M3H9S N Co NI NOISN3WIG SIN TIVOS u u 1 10109 6 014 1080 55 NOILVHOdHOO SINALSAS TVNSIA 21919319 IHSIGNSLIW DAN 4oe q ui SI luajuoo peuonueuuepun 31IHM all HIM wuwc 065XG LP uoisueul e 90 0 SS8UYDIU 9 suoneouioeds JALIA 1 HOLOOS ES euuM 4005 Or v ON M34HOS
110. 5 C CERAMIC CHIP B6 3V 105 K 1 6X0 8 3 15 SUMBOL NO PART NO DESCRIPTION SPECIFICATION C 651 CP156P060 03 C CERAMIC CHIP C 652 CP182P094 06 JC ELE CHIP 25V 470M M C 653 CP156P060 02 C CERAMIC CHIP C 654 CP156P060 02 C CERAMIC CHIP C 655 CP182P092 03 C ELE CHIP 6 3V 100MF C ELE CHIP C ELE CHIP C CERAMIC CHIP C CERAMIC CHIP C M PP C M PP C CERAMIC C CERAMIC C CERAMIC C CERAMIC C ELE CHIP C ELE CHIP C CERAMIC CHIP C CERAMIC CHIP C CERAMIC CHIP C CERAMIC CHIP C CERAMIC CHIP C CERAMIC CHIP C CERAMIC CHIP C CERAMIC CHIP C CERAMIC CHIP C CERAMIC CHIP C CERAMIC CHIP C CERAMIC CHIP C CERAMIC CHIP C CERAMIC CHIP C M P C M P B16V 104 K B50V 103 K B50V 103 K 16V 100MH 16V 100MH B50V 472 K B50V 103 K 100V 0 056M J 100V 0 056M J SL6 3KV 15P J SL6 3KV 15P J SL6 3KV 15P J SL6 3KV 15P J 16V 100MH 16V 100MH B50V 103 K B50V 102 K B50V 103 K B50V 103 K B10V 105 K B10V 105 K B16V 104 K B10V 105 K B50V 103 K B50V 103 K B50V 102 K B50V 103 K B10V 105 K B10V 105 K AC275V 0 33M M AC275V 0 33M M 1 6X0 8 1 6X0 8 1 6X0 8 F55 F55 1 6X0 8 1 6X0 8 LXA595W LXA595W LCD1550X LCD1550X LCD1550X LCD1550X F55 F55 1 6X0 8 1 6X0 8 1 6X0 8 1 6X0 8 2 0X1 25 2 0X1 25 1 6X0 8 2 0X1 25 1 6X0 8 1 6X0 8 1 6X0 8 1 6X0 8 2 0X1 25 2 0X1 25 ECQU2A334ML ECQU2A334ML C ELE KXW400V 150MF _ LCD1550X C CERAMIC 2KV_330P J LCD1550X C ELECTROLVTIC 25V 680 10X20 C 915 CP172P130 07 C POLYE
111. 600 5000K color temperature color temperature K NATIVE Panel color temperature R RED Gets closer to Gets closer to Operates color conversion function 5 100 10 Magenta Yellow 00 0 0 Panel color temp Gets closer to Green Gets closer to Blue Operates color conversion function 100 to 10 Gets closer to Cyan Gets closer to Operates color conversion function 7 100 to 10 Magenta M MAGENDA Gets closer to Blue Gets closer to Red Operates color conversion function 100 to 100 S SATURATION Color lights Color deepens Operates color conversion function 100 to 100 SHARPNESS Adjusts horizontal outline enforcement register of ASIC 0 EXPANSION Narrows to the Expands to the Changes pixel number for taking picture data 0 MAX Ontional H EXPANSION horizontal direction horizontal direction RZE EXPANSION MODE Narrows to the Expands to the Changes line number for taking picture data 0 Optional V EXPANSION vertical direction vertical direction VIDEO DETECT Enters into sub menu Selects FIRST DETECT LAST DETECT NONE Y DETECT DVI SELECTION Enters into sub menu Selects DIGITAL ANALOG Y 2 22 LANGUAGE Enters into sub menu Selects language used at OSM pictures 7 languages OSM POSITION Moves to the left LEFT RIGHT Moves to the right OSM POSITION Moves down DOWN UP OSM TURN OFF Enters into sub menu OSM LOCK OUT Enters into sub menu RESOLUTION Enters into sub menu NOTIFIER
112. 94 04 175 103 491 06 R CHIP 1 16W 3 9K F 1 6 0 8 R CHIP 1 16W 12 1 6X0 8 R CHIP 1 16W 12K F 1 6X0 8 R CHIP 1 16W 10 1 6X0 8 R CHIP 1 16W 10 1 6X0 8 R CHIP 1 16W 10 1 6X0 8 R CHIP 1 16W 10 1 6X0 8 R CHIP 1 16W 10 1 6X0 8 R CHIP 1 16W 10 1 6X0 8 R CHIP 1 16W 10 1 6X0 8 R CHIP 1 16W 10 1 6X0 8 R CHIP 1 16W 2 2 __ 1 6 0 8 9 15 R CHIP 1 16W 220 1 6X0 8 R CHIP 1 16W 150 1 6X0 8 R CHIP 1 16W 2 2K F 1 6 0 8 R CHIP 1 16W 5 6 ___ 1 6 0 8 1 16W 5 6 ___ 1 6 0 8 R CHIP 1 16W 150 F 1 6X0 8 R CHIP 1 16W 220 F 1 6X0 8 10 15 R CHIP 1 16W 12K F 1 6X0 8 R CHIP 1 16W 12K F 1 6X0 8 R CHIP 1 16W 12K F 1 6X0 8 R CHIP 1 16W 12K F 1 6X0 8 R CHIP 1 16W 1 8K F 1 6X0 8 11 15 R CHIP 1 16W 270 F 1 6X0 8 R CHIP 1 16W 5 6 1 6 0 8 R CHIP 1 16W 3 3K F 1 6X0 8 R CHIP 1 16W 330 F 1 6X0 8 R CHIP 1 16W 5 6K F 1 6X0 8 R CHIP 1 16W 1 8 ___ 1 6X0 8 R CHIP 1 16W 220 F 1 6X0 8 R CHIP 1 16W 150K F 1 6X0 8 R CHIP 1 16W 4 7 ___ 1 6 0 8 R CHIP 1 16W 10K F 1 6X0 8 R CHIP 1 16W 15K F 1 6X0 8 R CHIP 1 16W 3 3K F 1 6X0 8 R CHIP 1 16W 3 3K F __1 6 0 8 R CHIP 1 16W 150K F 1 6X0 8 R CHIP 1 16W 4 7 ___ 1 6 0 8 R CHIP 1 16W 10K F 1 6X0 8 R CHIP 1 16W 750 F 1 6X0 8 R CHIP 1 16W 5 6 ___ 1 6 0 8 R CHIP 1 16W 1 8K F 1 6X0 8 12 15 R CARBON 1 4W 6 8K J 682 RD H R CARBON 1 4W 1 2K J 122 RD H R CARBON 1 4W 2 2K J 222 RD H R CARBON 1 4W 3 3K J 332 R
113. 9945 Indino 20 24 291 1 32 MB3778PFV G BND EF IC608 Study of DC DC step down circuit design IC607 L610 Input voltage Vin12V Output voltage Vout Ch1 5 25V Output voltage Vout Ch2 3 40V Output voltage V specification Va Ch1 5 25V OUT OUT Ch2 3 40V Typ design value 2 1 R1 R2 Voer 2 46 2 Vou Ch1 2 46V 2 1 5 6 0 3300 1 8 5 28V Ch2 2 46V 2 1 5 6kQ 270Q 3 3kQ 3 42V e Output current lour specifications lour Ch1 1 6A MAX lour Ch2 0 8A MAX Ripple current Al specifications Al Ch1 0 146Ap p Set to 10 of loy Ch1 Al Ch2 0 121Ap p Set to 15 of Igy Ch2 Generally set to 3096 or less e Choke coil L Vin Ros on lour Vour our Al fs Vin L610 Ch1 12V 0 0380 1 6A 5 25V 5 25V 0 146Ap p 200000Hz 12V 100uH Sagami Elec product 7B12N Tolerable current 1 7A direct current resistance 0 170 1603 Ch2 12V 0 0380 0 8A 3 40V 3 40V 0 121Ap p 200000Hz 12V 100uH yuden product NO8DP A Typ Tolerable current 1 05A direct current resistance 0 350 Maximum power consumption P 5 25V x 1 6A 3 40V x 0 8A efficiency 0 8 13 9W 80 efficiency is value generally used for DC DC design e Maximum input current 13 9W 12V 1 15A Input fuse selection 1 6A part x 97 x 75 1 16A gt 1 15A g
114. A143EKA T LXA585W Q 901 CP260P359 01 100 CP103P497 01 105 CP103P497 01 R 100 CP109P183 08 101 CP109P183 08 R 110 CP103P102 00 111 103 103 06 CP103P102 00 103 103 06 CP103P103 06 103 103 06 CP103P102 00 CP103P493 06 CP103P493 06 x z z 2 2 olo 70 D OO gt gt DI 07 00 O O 212 113 114 R115 20 20 20 20 olololo gt gt gt gt 20 20 20 2 vv 2 2 gt 117 118 119 CP103P102 00 1 10W 220 J CP103P494 04 1 16W 22K J 2 gt 20 2 I u R 122 R 123 R 124 R 125 R 126 R 127 R 128 R 129 R 130 R 131 R 132 R 133 R 134 R 135 R 136 R 137 R 138 R 139 R 140 CP103P492 00 CP104P003 03 CP103P492 00 CP103P492 00 CP103P492 00 CP103P492 00 CP103P492 00 CP103P492 00 CP103P492 00 CP103P494 04 CP103P494 04 CP103P497 01 CP103P497 01 CP103P497 01 CP103P491 06 CP103P491 06 CP103P494 04 CP103P494 04 CP103P494 04 CP103P494 04 CP103P493 06 CP103P492 00 CP103P497 01 CP103P492 00 CP103P113 08 R 142 R 143 R 144 R 145 R 146 R 147 R 148 R 149 R 150 R 151 R 152 R 153 R 154 R 155 R 156 R 157 R 158 R 159 R 160 23123 gt gt 2012 W W OjO 212 70170 CP103P107 02 CP103P491 06 CP103P491 06 CP103P494 04 CP103P494 04 CP103P491 06 CP103P497 01 CP103P497
115. Appendix IV Regulation ck Regulation Co miryry Version Comments B c EU China i UL 1950 UIBSAA i CSA C22 2 No 950 Canadaadja i TUV GS EN60950 ZH1 618 Germ symany i EN60950 EWU SEMKO NEMKO North DEMKO FIMKO Europe Safety i PSB Singapore i AS Kustinadli a i CCIB Chh naa i GOST Rinssdad i PCBC i Korea i FCC Class Aj Class B i DOC Class Class B Catradeda i VCCI Class Aj Class B i 55022 Class A jClass B EN61000 3 2FN A i EN50082 1 EMS EU due to Power EN61000 3 2 Consumption i EN61000 3 3 less than 50W AS NZS 3548 EMC Framework Australdaralia i Ctick A gbra i h i BSMI waan i CCIB Chh naa i GOST i Korea VLF ELF i MPR 11 i TCO91 Ergonomj i 15013406 2 TUV ISO ics iTUV ERGO 11 15013406 2 Energv2000 Power i EPA 01 55 Save jInternational Energy Star Offjice Equipment program e EU i TUV ERGO MPR 11 1S013406 2 TCO92 EN60950 TC091 NUTEK CERES i TCO95 TCO92 Erggnvironment Black cabinet i TCO99 TCO954 Er invironment Exclude for Bla cabinet 29 Document No VSPF A028 V L I4
116. Apple Computer Inc Microsol and Windows are Irademarka of Ihe Micrasotl Coracealion ragestered trademark af MEC All olhar trademarks ragisbarad tragamarks are property oi their respacbys zwnarz English 1 pi 1 EST 11 Contents Your new MultiSync LCD monitor box should contain the following MultiSync LCD1550X monitor with tilt base Power Cordis Video Signal Cable 15 pin mini D SUB male to DVI A Video Signal Cable DVI D to DVI D Cable User s Manual NEC LOD Setup Software Pivot Software User s Manual and other helpful files To see the Users Manual Acrobal Reader 4 0 must be installed on your PG Video Signal Gable 15 piri mini D SUB male to CMI A i m gt User s Manual fi CD Video Signal DVI D to DVI D Remember to save your original box and packing material to transport or ship the monitor English 2 ABU EST Quick Start To attach the MultiSyne LCD monitor ta your system follow these mstructions 1 Turn off the power to your computer 2 For the PC Mac with DVI digital output Connect the DVI D ta DVI D signal cable ta the connector of the display card in your system Figure A 1 Tighten al screws For the PC with Analog output Connect Ihe 15 pin
117. C DIAGRAM PWB MAIN SVNC LCD1550X SAWL NIVW 4Md INVHOVIG OLIVW3HOS 088 091 53 95 g2 v g2 v g2 v 8 v 8 v 8 v 8 7 8 v 8 7 SLI L SLI L 811 1 0 3 7 a T A GAL P dbLv eu 065 c y r f ho La ASZHO ep 1052 yof oa oe fh D 232033 f 4 11 0 D U D O o Q 0 U UO UI Q a Q U Q G OU 0 a 888888 8888888838 gt EE BE BE EE 8 WN u A W b 3 N N 0 A To F Jo Ja Je To Suey sia i 90 sl b 5 3 gt Zo H g sre 5 v01 A918 Mga 9 8 ry ii LEGO a 6292 agso 2 E 8292 1 sto g T S 210 29 Sa U i g 20 I gt a la la la la 2 la la la la la z 5 b 373 B ala lala ala a 8 a ja S je 9 5 IS Ic 4 4 N STs SS oS EIE S SI S SI Rd xj RI SISISISISISISI Fa 4 i dl
118. CH50V 470P J 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP CH25V 1000P J _ 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C ELE CHIP 16V 100MH F55 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C ELE CHIP 16V 220MF F80 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B6 3V 105 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B6 3V 105 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 102 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B6 3V 105 K 1 6X0 8 C CERAMIC CHIP B6 3V 105 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B6 3V 106 K 2 0X1 25 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B50V 333 K 2 0X1 25 C CERAMIC CHIP B6 3V 105 K 1 6X0 8 C CERAMIC CHIP CH50V 330 __ 1 6X0 8 C CERAMIC CHIP B50V 333 K 2 0X1 25 C CERAMIC CHIP B6 3V 105 K 1 6X0 8 3 15 SUMBOL NO PART NO DESCRIPTION SPECIFICATION C 651 CP156P060 03 C CERAMIC CHIP C 652 CP182P094 06 JC ELE CHIP 25V_470M M C 653 CP156P060 02 JC CERAMIC CHIP 654 CP156P060 02 JC CERAMIC CHIP C 655 CP182P092 03 JC ELE CHI
119. CTOR B2P3 VH B MI 101 CP410P102 01 JBEAD FERRITE CHIP BK1608HS121 102 410 102 04 FERRITE CHIP 1608 5102 103 410 102 04 FERRITE CHIP BK1608HS102 104 410 102 01_ BEAD FERRITE CHIP BK1608HS121 106 410 102 01 1608 5121 107 410 102 01_ BEAD FERRITE CHIP 1608 5121 202 410 102 01 BEAD FERRITE CHIP 1608 5121 203 410 102 01_ BEAD FERRITE CHIP 1608 5121 204 410 041 03 FERRITE CHIP 2125 5431 205 CP410P041 03 2125 5431 206 CP410P072 08 BLM21B750SPT 207 CP410P102 01 EAD FERRITE CHIP BK1608HS121 208 CP410P102 01 EAD FERRITE CHIP BK1608HS121 209 CP410P072 08 ERRITE CHIP BLM21B750SPT 210 CP410P102 01 EAD FERRITE CHIP BK1608HS121 211 CP410P072 08 ERRITE CHIP BLM21B750SPT 212 CP410P072 08 ERRITE CHIP BLM21B750SPT 213 CP410P072 08 214 410 102 01 BEAD FERRITE CHIP 1608 5121 215 410 072 08 216 CP410P102 01 218 CP410P102 01 221 410 041 03 222 410 041 03 FERRITE CHIP BK2125HS431 300 CP410P102 01 301 CP410P102 01 302 CP410P102 01 303 CP410P102 01 305 111 00 Tl m w 00 a M w CP410P102 01 306 CP410P102 01 307 CP410P102 01 308 CP410P102 01 400 CP410P079 01 401 CP410P079 01 402 403 410 079 01 410 102 01 BEAD FERRITE CHIP 1608 5121 404 CP410P102 01 405 410 102 01 6 15 L101 CP410P102
120. D H R METAL S 1 4W 2 2K F 222 RN H R CARBON 1 4W 1K J 102 RD H R CARBON 1 4W 390 J 391 RD H R CARBON 1 4W 1K J 102 RD H R CARBON 1 4W 56K J 563 RD H R METAL S 1 4W 150 F 151 RN H R METAL S 1 4W 8 2K F 822 RN H R CARBON 1 4W 1 2K J 122 RD H VARISTOR SWITCH SW TACT SKHLLB LCD1550X SW TACT SKHLLB LCD1550X SW TACT SKHLLB LCD1550X SW TACT SKHLLB LCD1550X SW TACT SKHLLB LCD1550X SW805 CP432P029 01 SW TACT SKHLLB LCD1550X CP432P029 01 SW TACT SKHLLB LCD1550X CP432P029 01 SW TACT SKHLLB LCD1550X 1515 o x CP409P096 01 TRANS INVERTER ETJ20K29AM LCD1550X MI CP409P096 01 TRANS INVERTER ETJ20K29AM LCD1550X MI CP350P103 01 TRANS POWER ETS33BG155AH _ LCD1550X NIN SUMBOL PART NO DESCRIPTION SPECIFICATION TH701 CP264P592 01 THYRISTOR CROSAS 4 B LCD1550X LCD PANEL 289 022 01 LCD MODULE TX38D26VCOCAA 1 01550 erezosestot 01 ASsY PCBINVERTER 920 279 01 920 280 01 CP700A271 01 COVER REAR PC ABS CU6800 LCD1550X MI CP702B058 01 JCOVER VESA PC ABS CU6800 LCD1550X MI CP702B059 01 COVER CABLE PC ABS CU6800 LCD1550X MI CP702B060 01 JCOVER POWER PC ABS CU6800 LCD1550X MI CP702B061 01 JCOVER HINGE UP 5 LCD1550X MI CP722A010 01 JPLATE SV UNIT LCD1550X MI CP722A008 01 JSTAND UNIT LCD1550X MI CP722A009 01 LCD1550X MI E 900 442 004 02 901 442 00
121. D61 4 D615 3div idiv 3div qow 0 3V Typ BW FULL oe 000 Zoom 400 x CHI rm When switching is On the power MOS FET gate charge is pulled by the open collector transis tor base Hi built in the DC DC IC MB3778 to set the gate voltage Vos to 12V The DC DC open collector transistor operates actively so the power MOS FET turns ON at a high speed On the other hand the turn OFF time slows during OFF due to the open collector s pull up resistor R1 base To charge the power MOS FET gate Tri in this drive circuit turns ON when the base voltage has been increased by 0 6V in respect to the emitter by the pull up resistor R1 It then turns OFF at a high speed as the power MOS FET gate is charged by Tr1 s active operation Tr1 can be turned OFF at a high speed because the pull up resistor is bypassed The drive circuit consumes power only when the consumption power is turned ON and OFF by the Tr1 and R2 and thus can be ignored When the power consumed by the pull up resistor R1 during ON is considered the following is attained Current consumption during ON 12 V 3 3kQ 3 3mA Power consumption 3 3mA at ON x 12 Vcrcsaj V x 0 5 On Duty 18mW The DC DC IC MB3778 used with this circuit has a two channel output so there are two driver circuits The of the DC DC IC is 2 4mA so the power consumption is 28 8mW 2 4mA x 12V and the total power consump
122. DID DATA DUMP Manufacturer Code NEC Product Code HEX 65C8 Product Code DEC 26056 Microsoft INF ID NEC65C8 Serial Number HEX SN Week of Manuf WW Year of Manuf YY EDID Version 1 EDID Revision 3 Extension Flag 0 Video Input Signal ANALOG Setup NO Sync on Green YES Composite Sync YES Separate Sync YES V Sync Serration NO V Signal Level 0 700V 0 300V 1V p p 30 23 Max Image Size H Max Image Size V DPMS Stand By YES DPMS Suspend YES DPMS Active Off GTF Support NO Standard Default Color Space Preferred Timing Mode YES RGB Color YES YES Display Type Color Gamma 2 20 Red x 0 620 Red y 0 340 Green x 0 290 0 600 0 150 0 100 0 310 0 340 Green y Blue x Blue y White x White y 24 Established Timings 720x400 70 640x480 60 640x480 67 640x480 72 640x480 75 800x600 56 800x600 60 800x600 72 800x600 75 832x624 75 Standard Timing 1 NOT USED Standard Timing NOT USED Standard Timing NOT USED Standard Timing NOT USED Standard Timing NOT USED Standard Timing NOT USED Standard Timing NOT USED Standard Timing NOT USED Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz 1024x768 60 Hz 1024x768 70 Hz 1024x768 75 Hz 2 3 4 5 6 7 8 Document No VSPF A028 SN WW YY S2 tailed Timing block 1 Preferred de Pixe
123. EKA T LXA585W TRANSISTOR DTA143EKA T LXA585W Q 718 260 473 01 TRANSISTOR DTA143EKA T LXA585W Q 901 CP260P359 01 100 CP103P497 01 105 CP103P497 01 R 100 CP109P183 08 CP109P183 08 CP103P102 01 CP103P103 06 CP103P102 01 CP103P103 06 CP103P103 06 CP103P103 06 CP103P102 01 CP103P493 06 CP103P493 06 CP103P102 01 103 494 04 CP103P492 01 CP104P003 03 103 492 01 CP103P492 01 CP103P492 01 CP103P492 01 CP103P492 01 CP103P492 01 CP103P492 01 CP103P494 04 CP103P494 04 103 497 01 CP103P497 01 103 497 01 CP103P491 06 CP103P491 06 CP103P494 04 CP103P494 04 103 494 04 103 494 04 103 493 06 103 492 01 103 497 01 103 492 01 103 113 08 103 107 02 103 491 06 103 491 06 103 494 04 103 494 04 103 491 06 CP103P497 01 CP103P497 01 103 497 01 103 114 01 103 102 08 103 107 02 103 491 06 103 102 01 103 492 01 103 497 01 103 107 02 CP103P104 04 103 107 02 103 491 06 103 494 04 103 494 04 103 494 04 103 491 06 103 491 06 103 494 04 103 491 06 1 16W 100 8 15 L100 103 497 01 L105 CP103P497 01 100 109 183 08 R 101 CP109P183 08 R 110 103 102 01 111 103 103 06 R 112 CP103P102 01 R 113 CP103P103 06 R 114 CP103P103 06 115 CP103P103 06 R 116 CP103P102 01
124. EL5V Interface signal 3 3V system The following is set to satisfy the following panel AC timing with the microcomputer timing control s 40ms Oms lt 2 lt 50ms Oms lt 3 3ms Oms lt 4 3ms Oms lt t5 5 50ms Oms lt t6 31s t7 2 0 25 DC characteristics of interface signal The ASIC Maurice2 clock delay time is set so that the panel clock s falling edge hits at the center of the data QCLK THIC QDE QHD 4 5 5 DATA jsw 1 5V The timing reference is 1 5V Note that the panel input Hi level voltage VIH and panel input Lo level voltage VIL are as follows VIH 2 2 0V VIL 0 8V TTL level Maurice2 s panel output level is gt D3_3V 0 05V and VOL 0 05V and thus direct connection is possible D3 is Maurice2 s I O power 3 3V 1 40 1 71 List of control signals Switch board interface u COM Pin No Signal name Function Remarks 68 LEFT OSM menu selection Normally 1 Lo when switch is pressed PWB SW 69 EXIT OSM menu selection Normally 1 Lo when switch is pressed 70 OSM menu selection Normally 1 Lo when switch is pressed 71 RIGHT OSM menu selection Normally 1 Lo when switch is pressed 72 OSM menu selection Normally 1 Lo when switch is pressed 73 OSM menu selection Normally 1 Lo when switch is pressed 74 SW DET
125. Fine Clock phase cannot setup perfectly at some PCs In this case the fine turning of H size and Fine by manual are necessary If you proceed the Auto setup on character mode such as Dos Prompt mode you also cannot setup perfectly We recommend to indicating the bright and full window pattern such as Windows back ground or use test pattern in the CD ROM comes with this monitor for Auto setup Contrast Black level are set up by AUTO function 9 Document No VSPF A028 5 Screen Performance 5 1 Test condition 40 780 Brightness 100 Contrast and Display Image must be set by Auto setup with test pattern on the screen Black Level 50 Color NATIVE Ambient luminance 200 150 cd m Luminance meter Topcon BM5 7 Prichard 1980A or same equivalent 5 2 Luminance more than 160 cd m2 L3 Center point of TFT panel more than 65 L min L max 100 More than 160 note 4 Judge point for brightness uniformity Brightness uniformity is judged at nine 9 points on display area The brightness uniformity Buni is defined as the following equation Setting Bmax or Bave b 100 Qa Bmax Maximum brightness among nine 9 measuring points Bmin Minimum brightness among nine 9 measuring points Bave Average brightness of 1 to 9 10 Document No VSPF A028 5 3 Color temperature NATIVE X 0 310 0 03 0 03 Y 0 34
126. GND GND 4 GND GND Inverter power control input 5 P_INVT Power ON HIGH OFF LOW 6 PRO_DLY Protection circuit control input Protection circuit valid HIGH invalid LOW 7 DUTYCINV Dimming PWM signal input Resonance circuit active HIGH inactive LOW Sequence at inverter ON P_INVT T a 1 1 lt gt lt gt DUTYCINV b PRO_DLY Limit Minimum Typical Maximum a 20msec 100msec 200msec b 400msec 600msec or less b or more 1300msec Each terminal turns to LOW simultaneously when the power is turned OFF 2 J701 J702 PIN No Name Function 1 HOT_1 HOT_3 High pressure output 1 3 2 HOT_2 HOT_4 High pressure output 2 4 3 No connection 4 COLD_1 COLD_3 Ramp return 1 3 5 COLD_2 COLD_4 Ramp return 2 4 1 43 1 8 4 Detailed description of each circuit 1 8 4 1 Power input section Oscillation circuit 1 lin J703 Source R702 1 16W 4 7K J Oscillation circuit 2 R701 1 16W 4 7K J IC703 HAT1021R P INV q Q705 RADE NE DTC143EKA T 1 16W 220 J The 12VDC output from the power board is turned ON and OFF with the FET switch IC703 and is supplied to each oscillation circuit The IC703 FET switch is turned ON and OFF by turning Q705 digital transformer ON OFF with the signal P_INVT from the
127. I M 5 I 01 5 NG ITMOL L 8 SSL LYST L 1 VX3ev1V10 tangane piens 11 31886551 5 dvio XNLOGZNI LA E 20121 esa yoreuedwog 2254 an B 8 ag 2 33 z as ES 1 M gt 3 3 3 s SW T 5 27 2 b 83 832 g a e leTelts 5 9105 8 8 Z lx 513175 lt 5 2 a 8 524 24 8 Ber 24828 AS voo 82 20935 Me 8 dS LANE 7915 902 ds gt gt 3 847 1 in 1 LOH ij H 10H T uu 229 L SHS 8 23 6 vans 7749 ANE 91S BLO 848 i N 2 o lt ol 4911 9 WVEZXOZP L3 58 M s 87 401 Jeduo 1 8166252 E X10 WzLZL d ERRER 5 5 8 a 5 QNS A E 9 T 8 2 2 4 is 1 Vy3ev1210 W gt E 2 59 L 1 93691010 1016 2 2 82 say 909 5 aw 2 2 N gt T ES nig 2 3 R 1 i MES 29 11 3188655 2277 g 33 CS A 5 1 za
128. K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP CH50V 22P J 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 2115 C CERAMIC CHIP CH25V 1000P J 1 6 0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP CH50V 470 __ 1 6 0 8 C CERAMIC CHIP B6 3V_106 K 2 0X1 25 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP CH50V 100P J 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP CH50V 470P J 1 6X0 8 C CERAMIC CHIP B6 3V 105 K 1 6X0 8 C CERAMIC CHIP CH50V 100P J 1 6X0 8 C CERAMIC CHIP B6 3V 105 K 1 6X0 8 C CERAMIC CHIP CH50V 100P J 1 6X0 8 C CERAMIC CHIP CH50V 470P J __ 1 6 0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP CH50V 100P J 1 6 0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B6 3V 105 K 1 6X0 8 C CERAMIC CHIP CH50V 100P J 1 6X0 8 C CERAMIC CHIP B6 3V 105 K 1 6X0 8 C CERAMIC CHIP CH50V 100P J 1 6X0 8 C CERAMIC CHIP CH50V 470P J __ 1 6 0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B6 3V 106 K 2 0X1 25 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP CH50V 100P J 1 6 0 8 C CERAMIC CHIP B6 3V 106 K 2 0X1 25 C CERAMIC CHIP CH25V 1000P J 1 6X0 8 C CERAMIC CHIP CH25V 1000P J 1 6 0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP
129. K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 562 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B50V 102 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B50V 102 K 1 6X0 8 C CERAMIC CHIP B50V 102 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C ELE CHIP 16V 220MF F80 C CERAMIC CHIP B50V 102 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP CH25V 1000P J 1 6 0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B16V 104
130. K F 1 6X0 8 R CHIP 1 16W 12K F 1 6X0 8 R CHIP 1 16W 1 8K F 1 6X0 8 11 15 R CHIP 1 16W 270 F 1 6X0 8 R CHIP 1 16W 5 6K F 16X0 8 R CHIP 1 16W 3 3K F 1 6X0 8 R CHIP 1 16W 330 F 1 6X0 8 R CHIP 1 16W 5 6K F 1 6X0 8 R CHIP 1 16W 1 8K F 1 6 0 8 R CHIP 1 16W 220 F 1 6X0 8 R CHIP 1 16W 150K F 1 6X0 8 R CHIP 1 16W 4 7 __ 1 6 0 8 R CHIP 1 16W 10K F 1 6X0 8 R CHIP 1 16W 15K F 1 6X0 8 R CHIP 1 16W 3 3K F 1 6X0 8 R CHIP 1 16W 3 3K F 1 6X0 8 R CHIP 1 16W 150K F 1 6X0 8 R CHIP 1 16W 4 7K F 16X0 8 R CHIP 1 16W 10K F 1 6X0 8 R CHIP 1 16W 750 F 1 6X0 8 R CHIP 1 16W 5 6K F 1 6X0 8 R CHIP 1 16W 1 8K F 1 6X0 8 12 15 R CARBON 1 4W 6 8K J 682 RD H R CARBON 1 AW 1 2K J 122 RD H R CARBON 1 4W 2 2K J 222 RD H R CARBON 1 4W 3 3K J 332 RD H R METAL S 1 4W 2 2K F 222 RN H R CARBON 1 4W 1K J 102 RD H R CARBON 1 4W 390 J 391 RD H R CARBON 1 4W 1K J 102 RD H R CARBON 1 4W 56K J 563 RD H R METAL S 1 4W 150 F 151 RN H R METAL S 1 4W 8 2K F 822 RN H R CARBON 1 4W 1 2K J 122 RD H VARISTOR SWITCH SW TACT SKHLLB LCD1550X SW TACT SKHLLB LCD1550X SW TACT SKHLLB LCD1550X SW TACT SKHLLB LCD1550X SW TACT SKHLLB LCD1550X SW805 CP432P029 01 SW TACT SKHLLB LCD1550X CP432P029 01 SW TACT SKHLLB LCD1550X CP432P029 01 SW TACT SKHLLB LCD1550X BE Allo 85 255 Alo o TRANS INVERTER ETJ20K29AM LCD1550X MI TRANS INVERTER ETJ20K29AM LCD1550X MI TRANS POWER ETS33BG155AH _ LCD1550X CP265P119 01 THERMISTOR 1
131. L E x 5 5 LOLU g 5 5 58 e 5 5 2 3 2 4 cp z n n Ean 8 5 P WO LMS L L 8 Lg T me e F F P WO L MOL L 5 5 5 5 5 La L 2 r lt lt 3 098 MOL L 67LL 3L die 8L 6 Li 31 SZAN seb Qi 6 Li 317sz0n 7218 ozta T A 6 R sz I SOLA0L8 5 5 v 3 901 A018 58 S 5 8 5 2 M 58 92 2 L8 2 6 S T eae 5 L MOL L 26 71 PW L MOL L PJAN g f W9S0 GTAQQL 1 __ 8 6 LL 317SZ0N P W9G0 0 2 BER zm 2 Td 81 6 LL 31 5701 5 20 2 2 8 5 o T ojm Tas 5 a 2 8 a 56 amp 4 5 ie E 8 006 LVSZ 0 8 4 3 YZ 72 NOL L pa 3 2 006 LVSZ Sota zuo Ll X pes 5 I MZT MOL L U 1995331 ai 11 31886661 x 3017 5 wai 0001 ke x 3 X0L MOL L Sti Z RG L sti 4 YZ Z MOL L aci 7 RS Sta 2 Sti 0217 01 1 J Sta o z 5 gory 12 lt fa 28 pole LO Z lt 4 01 A058 8 55 2H 3 nosa 5 velo a JWOQL ASL 5 ET 5 18 1019 8012 tag lt lt 55 ge RB 22 4 kq 2 5 5 8 3 R 5 8 igi lt KI 8 si 2 58 5 9 6 gt i x 5 J 82 8 1 31 szan lI c m 5
132. LH LA J JAQ D S 5 9 975 A H gt 0 8 5 9 0 8 A 6 0 A pal iH 9 5 Zal 2H D S 9 H HdlI 9 LA S 9 5 0 94 41 8 5 edes CD X Cal LH S O 08D 2H S O ISD ISH 146 259 SH 135 speubis BulziuosyouAs JO gt LHV Boyeue gt LAV ZAV lt ZA 200094009 I IAq D S 10joeuuoo gns a S 2 101 euuoo gns a A H jeubis Bulziuosyouds eoueseud euis UIZIUOJJJUAS 1ndui Jo ojqel CO sf 10 T O 1 19 Digital input signal presence judgment For digital signals the input signals are judged as the following table according to the state of the SCDT signal 64 pin input into the microcomputer IC102 from the TMDS receiver 10500 Microcomputer input port Results of input signal judgment SCDT of digital signal Hi Input signal present Lo No input signal The TMDS output buffer power save signal PDO and internal logic power save signal PD are controlled as the following table according to the
133. LLOW gt MAGENTA gt RED 2 6 2 2 BIAS adjustment 1 Input timing No 14 60kHz 75Hz XGA75 with signal generator then set the pattern to full black with frame and video signal level to 0 7V 2 Select BIAS with OSM and press button Automatic adjustment of BIAS 2 6 2 3 GAIN adjustment 1 Input timing No 14 60kHz 75Hz XGA75 with signal generator then set pattern to full white and video signal level to 0 7V 2 Select GAIN with OSM and press button Automatic adjustment of GAIN 2 6 2 4 BRIGHT LIMIT adjustment 1 Input timing No 14 60kHz 75Hz XGA75 with signal generator then set pattern to full white and video signal level to 0 7V 2 Select MAX in BRIGHT LMIT with OSM and set the value to 220 Measure the luminance at the center of the picture with luminance meter then confirm that it is within the following value range 190cd m 300 2 250cd typ for the specification of Liquid Crystal Panel 3 Select MIN in BRIGHT LIMIT with OSM and set the value to 30 Measure the luminance at the center of the picture with luminance meter then confirm that it is within the following value range 15cd m 30 with BRIGHT MAX 2 6 2 5 Confirming color coordination of Liquid Crystal Panel 1 Input timing No 14 60kHz 75Hz XGA75 with signal generator then set pattern to full white and video signal level to 0 7V 2 Set CONTRAST to CENTER 128 and BRIGHTNESS to MAX 220 3 Set c
134. Number block 4 S2 EDID EDITOR V1 44 010306 Copyright Mitsubishi Electric 1995 2000 C Document No VSPF A028 LCD1550X DIGITAL EDID DATA DUMP TEXT Manufacturer Code NEC Product Code HEX 65C8 Product Code DEC 26056 Microsoft INF ID NEC65C8 Serial Number HEX SN Week of Manuf WW Year of Manuf YY EDID Version 1 EDID Revision 3 Extension Flag 0 Video Input Signal DIGITAL DFP Compatible NO 30 cm 23 cm Max Image Size H Max Image Size V DPMS Stand By YES DPMS Suspend YES DPMS Active Off GTF Support NO Standard Default Color Space Preferred Timing Mode YES Display Type RGB Color YES YES Color Gamma 2 20 Red x 0 620 Red y 0 340 Green x 0 290 Green y 0 600 Blue x 0 150 Blue y 0 100 White x 0 310 White y 0 340 26 Established Timings 720x400 70 Hz 640x480 60 Hz 640x480 67 Hz 640x480 72 Hz 640x480 75 Hz 800x600 56 Hz 800x600 60 Hz 800x600 72 Hz 800x600 75 Hz 832x624 75 Hz 1024x768 60 Hz 1024x768 Q9 70 Hz 1024x768 75 Hz Standard Timing 1 NOT USED Standard Timing NOT USED Standard Timing NOT USED Standard Timing NOT USED Standard Timing NOT USED Standard Timing NOT USED Standard Timing NOT USED Standard Timing NOT USED H2 3 4 5 6 7 8 Document No VSPF A028 LCD1550X Detailed Timing block 1 Preferred Timing Mode Pixel C
135. O31 O 134934 811HMS v08MS 6 MS HUMOd 811HMS GS08MS 8 3 4 x3N 5 908MS HOT 9 8 5 08MS 0 0 v 02011 10889 0080 NO MAO N 5 Schematic diagram POWER PWB MAIN POWER PWB MAIN INPUT PWB MAIN SYNC PWB MAIN TMDS PWB MAIN MC PWB MAIN ASIC INVERTER PWB SW H3MOd NVHDVIQ OLLVINIHOS X0SSrqo1 z N9 8 2 Z aNd 4 5 NE 8 593 SUE 9 Sd P YO A WL 70 gt P 48 9 Mb L R 23 9 L 2 L i k 2 L See mtl P L Mb L a 7063 8162 12 5 22452124 8 23 NEL Er IN 2 D a s A 5 5 5 4 S o m 9 442 7 NL 2 4 Ta QNO Ja a 28 80621 Pra ons E E
136. OLYTIC 25V 680M M 10X20 C 924 CP173P210 05 DC630V 0 022M J OR K C 926 CP182P107 03 C ELECTROLYTIC 50V 10M M 5 11 I DIODES PESE N TUE FOLDER d ZAB CK c sr D 100 CP264P426 03 DIODE ZENER CHIP UDZS TE17 5 68 DH D 101 264 426 03 JDIODE ZENER CHIP 0025 17 5 68 D 102 264 426 03 JDIODE ZENER CHIP 0025 17 5 68 D 103 CP264P426 03 JDIODE ZENER CHIP UDZS TE17 5 6B DH D 104 CP264P426 03 JDIODE ZENER CHIP UDZS TE17 5 6B DH CP264P426 03 JDIODE ZENER CHIP UDZS TE17 5 6B DH CP264P426 03 DIODE ZENER CHIP UDZS TE17 5 6B DH CP264P426 03 CP264P380 01 CP264P360 02 CP264P360 02 CP264P360 02 CP264P426 03 CP264P426 03 JDIODE ZENER CHIP UDZS TE17 5 6B DH CP264P360 02 CP264P360 02 CP264P360 02 CP264P576 01 CP264P310 05 CP264P360 02 CP264P426 03 D 212 CP264P360 02 JDIODE CHIP DAN217 T146 D 213 CP264P426 03 JDIODE ZENER CHIP UDZS TE17 5 6B DH 4115 DIODE ZENER CHIP UDZS TE17 5 68 DH DIODE ZENER CHIP UDZS TE17 5 6B DH DIODE ZENER CHIP UDZS TE17 5 6B DH DIODE ZENER CHIP UDZS TE17 5 6B DH DIODE ZENER CHIP UDZS TE17 5 6B DH DIODE ZENER CHIP UDZS TE17 5 6B DH DIODE CHIP CRS01 TE85L LXA595W DIODE CHIP CRS01 TE85L LXA595W DIODE CHIP CRS01 TE85L LXA595W DIODE CHIP 155357 LXA595W DIODE CHIP 155357 LXA595W DIODE CHIP CRS01 TE85L LXA595W DIODE ZENER CHIP UDZS TE 17 8 2B DH DIODE CHIP 0202132 LXA595W DIODE ZENER CHIP UDZS TE 17 9 1B DH DIODE ZENER CHI
137. P 6 3V 100MF C ELE CHIP C ELE CHIP C CERAMIC CHIP C CERAMIC CHIP C M PP C M PP C CERAMIC C CERAMIC C CERAMIC C CERAMIC C ELE CHIP C ELE CHIP C CERAMIC CHIP C CERAMIC CHIP C CERAMIC CHIP C CERAMIC CHIP C CERAMIC CHIP C CERAMIC CHIP C CERAMIC CHIP C CERAMIC CHIP C CERAMIC CHIP C CERAMIC CHIP C CERAMIC CHIP C CERAMIC CHIP C CERAMIC CHIP B16V 104 K B50V 103 K B50V 103 K 16V 100MH 16V 100MH B50V 472 K B50V 103 K 100V 0 056M J 100V 0 056M J SL6 3KV 15P J SL6 3KV 15P J SL6 3KV 15P J SL6 3KV 15P J 16V 100MH 16V 100MH B50V 103 K B50V 102 K B50V 103 K B50V 103 K B10V 105 K B10V 105 K B16V 104 K B10V 105 K B50V 103 K B50V 103 K B50V 102 K B50V 103 K B10V 105 K B10V 105 K 1 6X0 8 1 6X0 8 1 6X0 8 F55 F55 1 6X0 8 1 6X0 8 LXA595W LXA595W LCD1550X LCD1550X LCD1550X LCD1550X F55 F55 1 6X0 8 1 6X0 8 1 6X0 8 1 6X0 8 2 0X1 25 2 0X1 25 1 6X0 8 2 0X1 25 1 6X0 8 1 6X0 8 1 6X0 8 1 6X0 8 2 0X1 25 2 0X1 25 C CERAMIC CHIP C M P C M P C ELE AC275V 0 33M M ECQU2A334ML AC275V 0 33M M __ ECQU2A334ML KXW400V 150MF LCD1550X C 904 CP156P110 09 JC CERAMIC AC E 2200P M KX C 905 CP156P110 09 JC CERAMIC AC E 2200P M KX C CERAMIC 2 330P J LCD1550X C ELECTROLYTIC 25V 680M M 10X20 C POLYESTER 50V 0 01M K OR J 103 SO C ELECTROLYTIC 25V 220M M 8X11 5 C POLYESTER 50V 0 1M K OR J 104 SO C ELECTROLYTIC 25V 470M M 10X16 C 920 CP156P110 07 JC CERAMIC AC E 1000P M KX C 923 CP182P314 07 C ELECTR
138. P IC611 Study of DC DC step down circuit design Input voltage Vin12V Output voltage Vout Ch1 5 70 C656 i 10611 i PQ1CZ21H2ZP 5 6kQ ana TS e Output voltage Vor specification Vor 5 70V Typ design value Vae 1 R1 R2 1 26 2 1 26V 14 5 6kQ 750Q 1 8kQ 5 71V e Output current lour specifications lour 0 200A MAX Ripple current Al specifications Al 0 171Ap p e Choke coil Al f internal switch s saturation voltage 0 9V L618 12V 0 9V 5 70V 5 70V 0 171Ap p 100000Hz 12V 150uH Taiyo yuden product NO6DB 151K Tolerable current 0 48A direct current resistance 1 00 Maximum power consumption P 5 70V x 0 2A efficiency 0 8 1 43W 80 efficiency is value generally used for DC DC design e Maximum input current 1 43W 12V 0 12 Output smoothing capacitor C657 16V 100M M F55 CP182P093A41 ESR 21 000 MAX 20 C 100kHz Tolerable ripple current 140mArms 105 C 100kHz Tolerable ripple current frequency compensation coefficient 1 5 5V output system Ripple voltage specifications 5 200mVp p Ripple voltage Al x ESR 1 000 0 171Ap p x 1 000 0 171Vp p 5 200mVp p gt Ripple current Al 2 3 0 049Arms 5 Tolerable ripple current 140mArms gt e Input capacitor C656 16V 100M M F55 CP182P093A41 ESR 1 000 MAX 20 C 100kHz Tolerabl
139. P UDZS TE 17 9 1B DH DIODE ZENER CHIP UDZS TE 17 9 1B DH DIODE ZENER CHIP UDZS TE 17 9 1B DH DIODE SF15JC10 LCD1550X SARSO1 LXA595W DIODE SARS01 LXA595W 5558580080 USE SSFC 1 6A FUSE 251004 4A PROTECTOR 491007 7A IC MOS M24CO2WMN6T IC MOS M24C02WMN6T IC LINEAR NJM319V TE1 IC MOS 74ACT157MTCX 5 15 IC REGULATOR SI3025LSA 2 5V IC REGULATOR SI3025LSA 2 5V IC REGULATOR SI3033LSA 3 3V IC REGULATOR NJM2870F25 TE1 2 5 FET CHIP HAT1053M LXA595W IC LINEAR LM2901MX LCD1550X IC LINEAR LM2901MX LCD1550X HIC STR G6452 LCD1550X C903 CP268P017 01 C904 CP263P215 02 IC KIA431A AT C905 CP268P017 01 PHOTO COUPLER PC123Y22 100 CP452P318 02 CONNECTOR FFC 52852 1290 LXA595W MI 101 CP452P311 05 SM10B SRSS TB LXA580W 200 CP452P343 01 QH11121 CBO MI 201 CP452C070 01 CONNECTOR D SUB NFN8715F 400 CP452P310 03 CONNECTOR FFC SMT FH12 30S 0 5SH _ LXM510J 401 CP452P310 06 FH12 45S 0 5SH LXM510J 600 CP452P284 01 B2B PH SM3 TBT MI 601 CP452P284 07 B8B PH SM3 TBT MI 701 CP452P315 02 5 04 9 2 5 1 LCD1550X 702 452 315 02 5 04 9 2 5 1 LCD1550X 703 CP452C023 07 B7B PH K S 800 CP452P268 02 ONNECTOR FFC 52807 1210 900 CP246B185 05 EAD CONNECTOR J703 J900 LCD1550X MT 901 CP246B185 04 EAD CONNECTOR J901 J601 LCD1550X MT 902 CP452P345 01 ONNECTOR VH B2P4 VH B LCD1550X AC CP452P247 03 ONNECTOR B2P3 VH B MI 101 CP410P102 01 EAD FERRITE CHIP BK1608HS121 102 CP410
140. P102 04 ERRITE CHIP BK1608HS102 103 CP410P102 04 ERRITE CHIP BK1608HS102 104 CP410P102 01 EAD FERRITE CHIP BK1608HS121 106 CP410P102 01 BK1608HS121 107 CP410P102 01 BK1608HS121 202 CP410P102 01 BK1608HS121 203 CP410P102 01 EAD FERRITE CHIP BK1608HS121 204 CP410P041 03 ERRITE CHIP BK2125HS431 205 CP410P041 03 ERRITE CHIP BK2125HS431 206 CP410P072 08 ERRITE CHIP BLM21B750SPT 207 CP410P102 01 EAD FERRITE CHIP BK1608HS121 208 CP410P102 01 EAD FERRITE CHIP BK1608HS121 209 CP410P072 08 ERRITE CHIP BLM21B750SPT 210 CP410P102 01 EAD FERRITE CHIP BK1608HS121 211 CP410P072 08 ERRITE CHIP BLM21B750SPT 212 CP410PO72 08 ERRITE CHIP BLM21B750SPT 213 CP410P072 08 214 CP410P102 01 JBEAD FERRITE CHIP BK1608HS121 215 CP410P072 08 216 410 102 01 218 CP410P102 01 221 CP410P041 03 222 CP410P041 03 ERRITE CHIP BK2125HS431 300 CP410P102 01 EAD FERRITE CHIP BK1608HS121 301 CP410P102 01 BK1608HS121 302 CP410P102 01 BK1608HS121 303 CP410P102 01 BK1608HS121 305 CP410P102 01 BK1608HS121 306 CP410P102 01 BK1608HS121 307 CP410P102 01 BK1608HS121 308 CP410P102 01 EAD FERRITE CHIP BK1608HS121 400 CP410P079 01 ERRITE CHIP BLM11P121SGT 401 CP410P079 01 ERRITE CHIP BLM11P121SGT 402 CP410P079 01 ERRITE CHIP BLM11P121SGT 403 CP410P102 01 EAD FERRITE CHIP BK1608HS121 404 CP410P102 01 EAD FERRITE CHIP BK1608HS121 405 CP410P102 01 EAD FERRITE CHIP BK1608HS121 6 15 olo 212 22 mim 2012 glo lt gt
141. Q 0 32Hz lt lt 50Hz Description of operations The Green signal with 1V sync is input into FET 0202 0208 of the source follower circuit This is because it is led in directly from the Green signal line s 750 terminator so the input impedance is increased as high as possible to reduce the effect of noise even if a slight pat tern in led A source follower circuit FET 0202 Q208 with small input capacity 2SK360 is Typ 2 5pF for higher harmonics VHF is used to avoid damping of the signal waveform caused by the input capacity A grade which l ss is between 6 and 10mA is used so that the FET operation point is 0 3V 5mA With this the bias voltage on the polarity side of C210 and C242 is 2 8V A voltage value that does not cause a reverse polarity when the polar capacitor C210 and C242 are in the steady state or power save state is selected The input signal C cut at 47u F is compared at the clamp level voltage 1 36V and bottom clamp comparator 1 202 12203 If the input signal sync negative polarity is lower than the clamp level voltage the transistor Q204 Q207 turns ON during the sync interval and the input signal sync is raised by charging C202 and C236 The input signal is sync clamped with this operation Next the clamped input signal and voltage 1 48V are compared at the slice comparator 10202 IC203 to separate the composite sync from the video The voltage is set so that the slice l
142. S lt A H lt S 9 C gt jeubis 110 e oqe uey 19410 UONBUI WOJ S 9 1ueseid A H 1nduj S 9 lueseud jeuBis S 9 jeubis 1nduj 5 1ueseud eubis jndul S jueseud jeubis 1ndu A H lueseud 1ndu 5 S 1ueseid eubis S 9 1ueseid jeubIs 1nduj A euGis Indu ON H Aluo euGis Indu X X X OJXIO x OOOO x x O x x x O x O x IO OJXIOJXIOIJOO x OI OJO 0 57 esind 81 H 9 5 79 10 AH IE 5 H juawainseaw H 1e Juawainseaw A esind g1 H 9 U9Weunseaw A Av H HV 1210909215290 H JuSWamseew A A S 9 IeuBis 99 LIN J9INAWODOJJILU Aq JUBWA NSESJA OISV Aq luswsunsesjy 14018 5 S 1405 sioejes uotuw YAMS Indu SI LS LSH TAS 6 18D S 1405 2 H elesedas sjoajes UJIUM youms SI 259 25 135 LO Pedas
143. SERVICE MANUAL LCD DISPLAY LCD1550X LCD1550X BK NEC MITSUBISHI ELECTRIC VISUAL SYSTEMS CORPORATION DECEMBER 2001 CBB S5765 Rev A x Gs Following changes are added to Adjustment Procedure 1 1 PC available for DVI PC is added to 2 2 Measurement instrument used Configuration of DVI I input connector VIDEO men tioned in 2 4 3 Configuration of signal input power input section is revised The check item lt Swivel gt is added to 2 5 2 Mechanism and appearance inspection Note 1 is added to 2 6 1 Preparation BRIGHTNESS MAX value of the setting state is changed to 220 from 255 in 2 6 1 Preparation Some confirmation items are added to 2 6 1 1 Confirming operation of operation SW and functions ADC MAX value is specified in 2 6 2 1 Confirming OSM picture during heat running 2 6 2 1 Confirming OSM picture during heat running is revised EDID DATA DUMP TEXT is newly entitled as 2 7 Con figuration of DDC EDID data 10 2 7 1 10 Power voltage fluctuation and 2 7 1 11 Power asynchronous swing are deleted 11 The table in 2 8 2 1 Picture performance inspection is revised 12 The picture and the table in 2 8 2 3 Panel inspection is modified 13 2 9 3 Standards for display conditions is revised 14 BRIGHTNESS MAX value in 2 10 1 OSM default setting is changed to 220 from 255 15 The table lt Factory mode gt in 2 12 OSM display matrix is modified Rev A 2 6 2002 Contents 12 3 Gircuit d scriptiOnu ue
144. STER C 917 CP182P314 04 C ELECTROLYTIC C 918 CP172P134 03 C POLYESTER 50V 0 1M K OR J 25V 220M M 50V 0 01M K OR J 103 SO 8X11 5 104 SO 10X16 C 919 CP182P315 01 C ELECTROLYTIC 25V 470M M C 920 CP156P110 07 JC CERAMIC AC E 1000P M KX CP182P314 07 25V 680M M 10X20 CP173P210 05 C M P DC630V 0 022M J OR K CP182P107 03 C ELECTROLYTIC 50V 10M M 5X11 RG a os scc e d CP264P426 03 DIODE ZENER CHIP UDZS TE17 5 6B CP264P426 03 JDIODE ZENER CHIP UDZS TE17 5 6B 264 426 03 DIODE ZENER CHIP UDZS TE17 5 6B CP264P426 03 JDIODE ZENER CHIP UDZS TE17 5 6B 264 426 03 DIODE ZENER CHIP UDZS TE17 5 6B CP264P426 03 JDIODE ZENER CHIP UDZS TE17 5 6B 264 426 03 DIODE ZENER CHIP 0025 17 5 68 CP264P426 03 CP264P380 01 CP264P360 02 CP264P360 02 CP264P360 02 CP264P426 03 CP264P426 03 51 51 55 D 205 CP264P360 02 JDIODE CHIP DAN217 T146 D 206 CP264P360 02 JDIODE CHIP DAN217 T146 CP264P576 01 CP264P310 05 CP264P360 02 CP264P426 03 CP264P360 02 D 213 CP264P426 03 JDIODE ZENER CHIP UDZS TE17 5 6B DH D 207 CP264P360 02 DIODE CHIP DAN217 T146 4 15 DIODE ZENER CHIP UDZS TE17 5 68 DH DIODE ZENER CHIP UDZS TE17 5 6B DH DIODE CHIP CRS01 TE85L LXA595W DIODE CHIP CRS01 TE85L LXA595W DIODE CHIP CRSO1 TE85L LXA595W DIODE CHIP 155357 LXA595W DIODE CHIP 155357 LXA595W DIODE CHIP CRS01 TE85L LXA595W DIODE ZENER CHIP UDZS TE 17 8
145. T a e FAT 4 PANELSV RIGHT RIGHT PANELY I NEXT kO NEXT os POWER SW p sien sw TEST OF RESET kO RESET J400 5 LED PG LED P G FH12A 30S 0 5SH I GND e kO GND HIROSE GND b 1 057 89 1 ase fb l Z oe E 055 Q5 4 I GND s 053 83 052 051 050 GND 4200 a7 gt QH11121 CBO 6 8 035 d 4 on 08 4 fel GND 2 ass H 2 8 GND J201 2 5 ars NFN8715F as a4 D SUB15P GND 9 ars 5 az B 1 ato 9 1 47 4401 FH12A 45S 0 5SH B2B PH SM3 TBT HIROSE FPC 0 5mm pitch 0 3mm thickness IL FHR 45S HF JAE 4 GND 2 PDCK GND 9 PDENA GND 8 VSVNC GND HSVNC GW PANEL GND 2 PODB7 POD B6 POD B5 45 Pop GND POD B3 POD B2 POD B1 29 POD BO GND 5 POD G7 POD G6 125 POD G4 GND POD G3 28 POD G2 POD G1 POD GO GND POD R7 38 POD R6 POD R5 POD R4 35 GND POD R3 POD R2 POD Rt gt POD RO HQ VDDD VDDD VDDD TEST 1 1 1 1 1 1 1 1 M POD as 1 1 1 1 1 1 1 CN2 Ka SF GND 2 B7 B6 9 85 PEV B4 8 GND WD
146. The energy requirements include a demand that the computer and or display after a certain period of inactivity shall reduce its power consumption ta a lower lavel in stages Tha langth af time to reactivate the computer shall ba reasonable for the user Labelled products must meet strict environmental demands for axample in respect of the reduction of electric and magnetic fields physical and visual ergonomics and good usability Environmental Requirements Flame retardants retardants are present in printed circuit boards cables wires casings and housings In turn they delay the spread ol fire Up to thirty percent of the plastic in a computer casing can consist of flame retardant substances Mast flame retardants contain bromine or chloride and these are related to another group of environmental toxins PCBs which are suspected to give rise t severe health effects including reproductive damage in fisheating birds and mammals due ta the hiaaccumulative processes Flame retardants have been found in human blood and researchers fear that disturbances in foetus development may accur TCO 88 demand requires that plastic components weighing more than 25 grams must not contain flame retardants with organically bound chlorine and bromine Flame retardants are allowed in the printed circuit boards since no substitutes are available Lead Lead can be found in picture tubes display screens solders and
147. The oscillator uses the HIC s internal CI charging discharging Pulse signals are generated to determine the MOSFET OFF time The constant voltage control when the switching power is configured fixes the MOSFET OFF time 50 sec and functions with the PRC operation that changes the ON time and the pseudo resonance operation The operation for no constant voltage is shown in the figure below When MOSFET is ON capacitor C1 in OSC is charged to the constant voltage 5 6V Bv passing the drain current l to R906 a voltage drop VR5 occurs at the pin G OCP FB terminal This voltage has the same waveform l and approximately the same voltage as VRS is applied on the pin When the 1 voltage reaches the threshold voltage 0 76V Comp 1 operates and MOSFET turns OFF when the internal converter reverses The C1 charge is released when MOSFET turns OFF and charging of C1 starts with the constant current discharge circuit The voltage at both ends drops at the inclination determined by the capacitor in the OSC and the constant current discharge circuit When the voltage at both ends of the capacitor in OSC drops to approx 1 2V the oscillator output reverses again and MOSFET turns ON At this time the capacitor in OSC is rapidly charged to 5 6V MOSFET continues oscillation with a repetition of these steps Regi L C OD A PC Oscillator voltage PWM Lat
148. This is a pulse bypass method overcurrent protection circuit that detects the MOSFET drain current s peak value every pulse and reverses the oscillator output The MOSFET drain current is detected by connecting R906 across the pin MOSFET source terminal and pin 8 GND terminal and inputting the drop voltage into the OCP FB terminal The OCP terminal s threshold voltage r h 1 is approx 0 76V typ in respect to the GND R905 R935 and C909 are the filter circuits used to prevent malfunctions by the surge current generated when MOSFET turns ON When the secondary output drops in the overload state the primary auxiliary coil voltage drops in proportion Thus the pin voltage drops to below the operation stop voltage and the operation stops In this case the circuit current drops simultaneously so the pin voltage rises again with the charging current from R903 and R934 and intermittent operation that restarts with the operation start voltage takes place 1 2 4 Protection circuit A fuse is inserted in the 12V line F910 F911 as an overcurrent protection and as a circuit that maintains the oscillator output at the LOW level and stops the power circuit operation when the overvoltage protection OVP circuit or overheat protection TSD circuit operate 1 2 4 1 Latch circuit This circuit maintains the oscillator output at the LOW level and stops the power circuit opera tion when the overvoltage protection OVP circuit or overheat pr
149. To fulfil the safety requirements the monitor must be mounted to an arm which guaranties lhe necessary stability under consideration of the weight of tha monitor The LCD monitor shall only be used with an approved arm e g GS mark English 8 B ABU oF Controls OSM On Screen Manager Controls The OSM controls on the frant of the monitor function as follows To access OSM press any of the control buttons 4 To change DVI D SUB signal input press the NEXT button To rotate OSM between Landscape and Portrait modes press the RESET button NOTE OSM menu must be closed in order to change signal input and to rotate Control Menu EXIT Exiis the OSM controls Exits ta the OSM main menu CONTROL Moves the highlighted area left right ta select contral manus Moves the highlighted area up down to select one of the controls ADJUST Moves the bar leftright to increase or decrease the adjustment Activates Auto Adjust lunelian Enter the sub manu NEXT Movas the highlighted area of main manu right to select one of the controls RESET Resets the highlighted control menu to the factory setting Resets the highlighted control ta ihe factory setting NOTE When RESET is pressed in the main and sub menu a warning window will appear allowing you to cancel the RESET function by pressing the EXIT button English 9 pi B EST
150. V circuit power control 1 Power ON 0 Power OFF ASIC digital logic circuit P_SUSP3 Power control for PLL circuit 1 Power ON 0 Power OFF ASIC PLL circuit P_SAVE PWB POWER PRC mode resonance mode switching control 1 When normal 0 During power save Power board P_TMDS circuit power control ASIC forcible reset signal 1 Power ON 0 Power OFF TMDS Communication I F between microcomputer and ASIC Clock Communication I F between microcomputer and ASIC Data written to ASIC Communication I F between microcomputer and ASIC Data read from ASIC Communication I F between microcomputer and ASIC Enable Panel clock setting signal 0 Set with hardware Refer to separate MODEL1 Panel clock setting signal 1 Panel clock setting signal 2 Panel identification signal input 0 table 1 for details MODEL2 Panel identification signal input 1 Set with hardware MODEL3 Panel identification signal input 2 Refer to separate MODEL4 Panel identification signal input 3 table 2 for details P5_0 CE Chip enable signal for onboard writing Serial writer 5 1 CABLE CABLE detection unused 5 2 EEPROM write protect for DDC communication 1 Write enabled 0 Write protected EEPROM for DDC communication 5 3 LED_P_U LED control signal orange SW board 5 4
151. Video Inputs on the monitor and computer to make sure they are properly connected After power is turned on or when there is a change of input signal or video 5 inactive the No Signal window will appear RESOLUTION NOTIFIER This function gives a warning of use with optimized resolution After power is turned on or when there is a change of input signal or tha video signal doesn t have proper resolution the Resolution Notifier window will open This function can ba disabled in tha TOOL menu OUT OF RANGE This function gives a recommendation of the optimized resolution and refresh rate After the power is turned on ar there is a change of input signal or the video signal doesn t have timing the Qut Of Range menu will appear I B CHANGE DV SELECTION is displayed switch to SELECTION English 14 14 ABU EST Recommended Use Safety Precautions and Maintenance FOR OPTIMUM PERFORMANCE PLEASE NOTE THE FOLLOWING WHEN SETTING UP AND USING THE MULTISYNC LCD COLOUR MONITOR DO NOT OPEN THE MONITOR There are no user serviceable parts inside and opening removing covers may expose you to dangerous shock hazards or other risks Refer all servicing to qualified service personnel De not spill any liquids inta the cabinet use your monitor near waler Do net insert objects of any kind into the cabinet shots as thay may touch dangerous voltage points which can be harmiul or fatal or ma
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153. Y Year of Manufacture S2 ASCII Serial Number CS Check Sum 27 Document No VSPF A028 LCD1550X Appendix III Preset Timing Chart E 5 2 12 2 12 64 64 1 12 64 2 03 64 3 81 108 2 00 72 3 420 128 2 40 120 1 62 80 2 09 136 1 81 136 1 72 134 1 22 96 2 09 0 37 136 24 I427 0 76 40 24 0 34 24 31 26 32 3 59 1 74 864 97 47 Sub 96 3759 224 1 9 4 T 4 3 120 4 5 3 56 128 8 6 EJ 3223 P60 EJ 6 4 2 6 2 7 2 6 4 128 1 27 160 0 1 8 9 8 8 9 4 8 4 0 92 4 05 0 23 6 46 0 06 7 9 75 21 16 640 14 54 832 25 42 640 20 32 640 25 42 720 22 22 800 20 00 800 6 00 800 6 16 800 5 75 024 3565 024 By KL 024 3 00 024 5675 024 20 32 640 14 53 1024 25 95 701 28 Freq FV Hz Vertical Period sv ms 60 1 05 33 0 43 16 1 08 34 0 63 22 0 61 23 0 48 2 0 45 21 0 60 29 02 52 29 0 50 29 0 47 28 0 60 29 0 74 8 0 3 1 13 0 0722 35 806 13 73 520 0 3 08 15 3 0 6 qst 06 20 625 0 3931 m m 3 w w 2 5 w N OY w w w Document VSPF A028 768 12 68 480 14 64 768 B gt H 18 LCD1550X
154. able P8_1 TA4IN C S M1 V measurement at C S for DVI I connector analog Ch P8 2 INTO S G V2 V measurement at S G for D Sub connector P8 S INT1 QVD M Equivalent to vertical synchronizing signal input from ASIC Equivalent to frame signal ASIC P8 4 INT2 S G V1 V measurement at S G for DVI I connector analog Ch P8 5 NMI MNI For onboard writing Vcc Serial writer P8 6 XCOUT SEL HS2 GS2 Input sync switching switch 0 H or C S side 1 S G side P8 7 XCIN P9 O TBOIN CLK3 SEL HS1_GS1 Input sync switching switch H measurement at C S for D Sub connector 0 H or C S side 1 S G side 74F157MTCX multiplexer IC P9 2 TB2IN SOUT3 H measurement at S G for D Sub connector P9 S DAO TBSIN H measurement at C S for DVI I connector analog Ch P9 4 DA1 TBAIN H measurement at S G for DVI I connector analog Ch P9 5 ANEXO CLK4 DVI I connector DDC switching control signal L Normal f Tap position store X9116WM P9 6 ANEX1 SOUTA Internal thermistor circuit A D input 0 Low temp 255 High temp Thermistor circuit P9 7 ADTRG SINA P10 0 ANO OSD menu selection reset the setting value to the default DG hen SW is pressed SW board P10 1 AN1 Front power switch monitoring hen SW is pressed P10 2 AN2 OSD menu selection hen SW is pressed SW board P10 OSD menu
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156. arance 2 16 2 9 1 1 Scope of inspection nanna 2 16 2 9 1 2 Environment for inspection 2 16 2 91 3 Picture in Pte d e das 2 16 2 9 2 Definition of applicable area 2 16 2 9 3 Standards for display conditions standard for errors defects 2 17 2 10 Outgoing inspection tette i e cep ERE bee A ee ded 2 20 2 10 1 0SM default Setting rit dete Pb ep ec siada 2 20 2 10 2 Checking the labels 2 20 2 10 3 Packaging specifications 2 20 2 11 Timing Chart oerte enne nee de sex 2 21 2 12 0SM display matrix itte CR IRR Ttt nt aad ee a 2 22 Trouble shooting Waveform Schematic diagram Attachment Serial number information Specification User s guide All parts list vi 1 Circuit description 1 1 Power circuit 1 The power block is compatible with 100 to 120VAC 220 to 240VAC Automatically tracked 2 The power supply section is a PRC ON width control with constant OFF time during P SAVE and operates as a pseudo resonance circuit in the steady state By feeding back via the photocoupler IC903 from the output voltage with the HIC STR G6452 flyback converter type switching IC IC901 with built in POWER MOS FET and separate exciting control IC the voltage is constantly controlled to prevent output voltage fluctuations caused by AC input vo
157. button is pressed so that AUTO ADJUST can be carried out 2 8 1 5 Confirming composite sync signal Input composite sync signal SUN57 listed in 2 11 Timing chart with signal generator and set the pattern to 1 dot zigzag grid with frame Start up AUTO ADJUST and confirm that the picture appears normally 2 8 1 6 Confirming Sync On Green signal Input Sync On Green signal Timing No 19 and set the pattern to 1 dot zigzag grid with frame Start up AUTO ADJUST and confirm that the picture appears normally 2 8 1 7 Confirming digital input Input timing No 14 to DVI D connector with signal generator and set the pattern to horizontal lamp with frame Confirm that the picture appears normally without out of synchronism picture short vertical noise of chromatic color dot noise jitter and gray scale noise 2 8 1 8 Confirming D SUB input connector Input timing No 14 to D SUB connector with signal generator and set the pattern to 1 dot zigzag grid with frame Start up AUTO ADJUST and confirm that the picture appears normally 2 12 2 8 1 9 Confirming power management function 1 Input the specified timing with signal generator and set the pattern to full white AC240V 50Hz 60KHz75Hz iXGA75 j 38W or less mese oow 2 Input the timings mentioned above and confirm the image display or OSM display Turn the signal generator H sync V sync OFF and turn G signal OFF 3 Confirm that Power On Indica
158. ce capacitor the dv dt of the during turn OFF becomes gradual This series of opera tions is called pseudo resonance The turn ON timing is applied using the signal that has passed through the delay circuit using the flyback voltage waveform of the auxiliary coil lt Circuit and waveform gt gt LpC4 delay time 1 2 LpC4 resonance frequency Vos lower limit VDS gt A OCPIFB terminal threshold voltage 2 1 5 a A OCP FB terminal threshold voltage 1 0 76 1 2 2 Switching circuit operation When actually changing over if the voltage Vth 1 of the pseudo signal applied on the HIC pin 5 OCP FB terminal is nearly equal to 0 76VMIN or more or less than the threshold voltage Vth 2 1 3V the internal Comp 1 operates and PRC operation with a fixed OFF interval takes place at TOFF 50u S When this voltage is more than the threshold voltage Vth 2 1 5V or more Max 6V the internal Comp 2 operates The OFF time generated by the internal transmitter changes at approx 1uS Max MOSFET remains OFF while the voltage is higher than the threshold voltage Vth 1 Pseudo resonance operation refers to matching the timing for turning this MOSFET ON with the bottom point of the voltage resonance after the transformer has discharged the energy and with a cycle one half of the resonance frequency When the voltage resonance capacitor C906 is connecte
159. ch SE is sa 050 s 7 Direct current bias caused by photo transistor Drive 06 A a pm Voltage at both ends of C5 E gt a Fi 1 Comp 1 MU INH Latch 1 9 Oscillator output ON OFF ON SH Vth 2 R MOSFET 2 Oscillation operation during constant voltage control As explained above the time determined by the VR5 1 inclination is the MOSFET ON time This fixed time is adjusted to 50usec by the constant current discharge circuit To control the output the F B current passed to photocoupler IC903 is passed to R905 and R935 and the voltage drop VR4 caused by this is applied on VR5 With this the VR5 voltage value IP peak value required to reverse Comp 1 is used as the control for the current mode controlled by VR4 FB current When MOSFET is OFF the bias amount to just before MOSFET turns ON is lowered to approx half by the active lowpass filter s 0 8mA typ constant current bias circuit As a result the surge noise that occurs when MOSFET turns ON is absorbed by C909 Conventionally the charging current of the oscillator s capacitor was changed by the photocoupler current and the charging time until the threshold voltage Vth 1 0 73 V was changed However with the STR G6452 the DC bias is controlled ON width control Pin G terminal and OCP circuit
160. ch 0 297 H x 0 297 V Surface Treatment Anti glare treatment of the front polarizer asss H 1 t se S LX Viewing Angle 0 degree 0 34 jo NOTE 1 These items are measured using Topcon BM5 BM 7 Prichard 1980A or same equivalent under the dark room condition NOTE 2 The definition of CR Contrast Ratio White Luminance black luminance 14 Document VSPF A028 Notes note 1 Contrast ratio is defined as the following formula Brightness Luminance with all pixels at white Contrast ratio Brightness with all pixels at black note 2 Viewing angle is measured as follows 90 2 o clock 0 7 Eye point 80 9 A 0 3 o clock X TFT LCD Module 270 6 o clock note 3 Definition of response time is as follows When the display data is changed from white to black response time is measured 100 White 90 Luminance 10 Black ton toff Q o o o o coo note 4 Judge point for brightness uniformity Brightness uniformity is judged at nine 9 points on display area The brightness uniformity Buni is defined as the following equation Bmax or Bave b 100 Bmax Maximum brightness among nine 9 measuring points Bmin Minimum brightness among nine 9 measuring points 15 Document VSPF A028 Bave Average brightness of 1 to 9 16 Document VSPF A028 8 2 Defect Scratch
161. ct Specifications MultiSync LCD1550X 15 TFT Color LCD Monitor _____________ Input Digital Input LCD Module Resolution 1024x768 dots XGA Frequency ei A Viewable Size 304 1 x 228 1mm Controllable Function Brightness Contrast Color control etc Input Signal TMDS Video Analog RGB 0 7V p p Input Impedance 75 Composite level Posi Nega Composite sync on Green Video 0 3Vp p Nega video 0 7Vp pPosi Separate level Posi Nega Mini D sub 15Pin DVI I Analog and digital Signal Cable DVI I A to D Sub Cable L 1 8 m DVI D to DVI D Cable L 1 8 m Power Supply Universal 100 240V Current Rating 0 7A 100 120V 0 4A 220 240V Operational Temperature 5 35degC Environment Humidit 10 8096 without condensation Storage Temperature _ 20 60degC Environment Humidity 10 9096 without condensation Dimension 345 2 W x 379 7 434 7 H x 201 7 D mm Gross 426 W x 480 H x 290 D mm Weight Approximately6 0kg Gross Approximately8 5kg Kensington compatible Yes Security Lock VESA compatible arm Yes 75mmx75mm mounting interface ilt Swivel Rotation Up 45deg Down 5deg Complied Regulatory and UL cUL FCC B CE TuVGS TuVErgo Ctick PSB AS TCO99 Guidelines IGOST PCBC EPA VCCI Er Accessaries User s manual Power Cord x 1 2 DVI D to DVI D Digital Signal Cable x 1 DVI D to DVI A Digital Signal Cable x 1 CD ROM Sales Office List B Ver CD ROM 5 Document
162. d between the drain and ground and the delay circuit R907 R909 C914 or D902 is connected between the auxiliary coil T and OCP FB terminal the flyback voltage generated from the auxiliary coil when MOSFET is OFF causes the pseudo resonance signal to operate the IC internal Comp 1 and Comp 2 and starts pseudo resonance operation Even when discharge of the transformer energy has finished with the delay circuit the pseudo resonance signal will not lower to the pin terminal immediately This is because the charge at C909 and C914 rises above the threshold Vth 1 or less for a set time after the charge is discharged by the composite impedance of the IC internal active lowpass filter and R905 lt Waveform at switching gt IC901 pin 5 waveform At standby When normal a 1 Cnr 1 pr fi pc mi Pam jiflu j MESE h sp m i f D 1 4 ik 7 mirusmiu EB rn PA 2 Pim Fir 1 2 3 Description of operation 1 When the power is turned ON C924 is charged by the starting resistors R903 and R934 When this IC901 pin voltage reaches 17 6V the control circuit starts operation After the control circuit starts operation power is attained by rectifying and smoothing the coil voltage at the T901 auxiliary coil 2 IC901 pin G OCP FB terminal oscillator and constant voltage control circuit
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164. ding ratio 0 255 Adjustment of Clock FINE Changes flickering of the picture Changes clock phase Adjustment of Clock phase 3 2 CUSTOMIZE Selects Color1 Color2 Color3 sRGB Color5 Native ATIVE AccuColor COLOR 1 9300K Changes to lower Changes to higher Changes color temperature 5000K 9600K 9300K colortemperature color temperature COLOR 2 8200K Changes to lower Changes to higher Changes color temperature 5000K 9600K 8200K colortemperature color temperature COLOR 3 7500K Changes to lower Changes to higher Changes color temperature 5000K 9600K 7500K colortemperature color temperature COLOR 5 5000K Changes to lower Changes to higher Changes color temperature 5000K 9600K 5000K color temperature color temperature NAT Panel color temperature Panel color temp IVE R RED Gets closer to Gets closer to Yellow Operates color conversion function 100 to 100 Magenta Y YELLOW Gets closer to Red Gets closer to Green Operates color conversion function 100 to 100 EUN G GREEN Gets closer to Gets closer to Cyan Operates color conversion function 7 Yellow 100 to 100 loser to Gets closer to Blue Operates color conversion function 100 to 100 B BLUE Gets closer to Gets closer to Operates color conversion function 100 to 100 Cyan Magenta M MAGENDA Gets closer to Gets closer to Red ates color conversion functio 100 to 100 MER Blue S SATURATION Color lights Color deepens wej color conversion
165. e 82 5 5 3 H LE 5 2 5 AE lt 98 Wd n ered Re vau 43 32 t MSL L 3 02 Z MOL L r mcm 5 B T OLY 9171 924 4 9528 T te 5 i ELv 21 AQSE Lee Pap Re Lee popes 15 sio jc n L amp Iny ly 1821 _ 8823 SRZY ga 1988 BOSU_ D _ nr AER a AE ETT MP um UR i 3 3 4 B 28 28 5 3 f f f a be RE i 3 F 8r 8 cia 18 g a RA 118 45 1 d t S wv j 8 128 id x soL Aada 3 vim 5 5 Sa 2 rx wei 5 i cz 2 CAEM Tash ion ERS cornada no ous P 4 821 171 a non 8 2 d S reci 5 3 S 080 8 33 5 cou 24 5 asnon sizo 5 wei 3 25 5 3 ei Ro i BE asf jal 85 3 H H e RE 5885 A 30 5 Ba 3452 2 8 i 1 5 5 2 89 87 szn d dz 9 s did 81 Be r epwewi 223 888 x i 9220 2121 3 7 1 5 Sr Lzy gt 9r F L z Beta ga 86 4 ne 5 4 r sza Lwa E eza eua ezza 1228 m Al
166. e Fig 8A BK See Fig 8 2B U K See Fig 9 1A See Fig 9 1A BK Fig 9 2 Fig 9 See Fig 9 1A Fig 9 2A Bar Code label See Fig 13A See Fig 13A BK See Fig 15B 11 Languages English German French Italian Spani sh Russian Czech Dutch Turkish Polish Greek See Fig 10B Set Up Sheet See Fig 12A See Fig 13B ei See Fig 11B Caution Sheet See Fig 14B Liquid View A Brochure See Fig 11A CD ROM See Fig 16 Signal Cable 2 Languages English French Uses guide _ See Fig 10 1A 12 Document VSPF A028 7 Environment condition 7 1 temperature Relative Humidity amp Altitude Operating Storage and shipment 5 to 35 degrees C 20 to 60 degrees C i 10 to 80 10 to 90 Related humidity without condensation Altitude 3 000m 10000ft 16 000m 53333ft 7 2 Vibration test Packing Swept Sine Acceleration 4 91m s 0 5G zero to peak Random Vibration 7 3 Drop test Packing 1Top surface 1 Bottom surface Other 4surface 13 Document VSPF A028 8 LCD Panel Specifications 8 1 TFT LCD Panel Specifications LCD Module type 15 0 38 016 cm diagonal 2001 331 6 H x 255 5 V mm x 13 5 D Display Type Active matrix thin film transistor TFT 2221 Display Mode IPS Normally Black Wu WI Resolution 1024 iH j 768 Aspect ratio 4 3 Active Display Area 304 128 H x 228 096 V mm Pixel Pit
167. e monitor near a radiator or athar heat sources Do mot put anything an tap of monitor The power cable connector is tha primary means of detaching the system from the power supply The monitor should ba installed close to a power outlet which is easily accessible Handle with care when transporting Save packaging for transporting CORRECT PLACEMENT AND ADJUSTMENT OF THE MONITOR REDUCE EYE SHOULDER AND NECK FATIGUE CHECK THE FOLLOWING WHEN YOU POSITION THE MONITOR Far aptimum performance allow 20 minutes for warm up Adjust the monitor height so that the top of the screen is al or slightly below eye level Your eyes should look slightly downward when viewing the middle of the screen Position your monitor closer than 40 cm eyes The optimal distance is 58 cm i Rest your eyes periodically by focusing on an object al least 6 m away Blink often Position the monitor at a 90 angle to windows and other light sources ta minimize glare and reflections Adjust the monitor tilt so that ceiling lights do nat rellacE on your screen If reflected light makes rt hard for you ta see your screen use an antiglare Filter Clean the LOD monitor surface with a lint free non abrasive cloth Avoid using any cleaning solutian or glass cleaner Adjust the monitors brightness and contrast controls to anhance readability Use a document holder placed close to the sereen Position whatever you are looking at mast of the time he
168. e ripple current 140mArms 105 C 100kHz Tolerable ripple current frequency compensation coefficient 1 Ripple voltage Don Vin 9 7V 12V 0 48 0 48 1 0 48 0 50Arms lt Tolerable ripple current 140mArms OK Oscillation frequency 100kHz 1 35 MB3778PFV G BND EF 1 608 Study of DC DC power MOS FET drive circuit Power MOS FET Vishay Siliconix product P Channel MOS FET Si3457DV CP260P470A11 IC607 IC609 Rating Vos 30V 1 DC 3 4A Ta 70 C 1 PULSE 10A P 1 3W Ta 70 C Specifications on resistor Roson 0 12 Ves 4 5V 1 3 4A t on 15nsec t off 50nsec Max 11000nsec The turn On turn Off time is 65nsec and is sufficiently small compared to the switching cycle 5000nsec oscillation frequency 200kHz There is little switching loss rce 5V Div 0 5A Div Voltage between Collector Power MOS FET 1C607 1C609 and Emitter Vez 5VDiv 12V Tr1 28C2412K R 0601 Stopped 7001 08 06 16 09 57 A Loo CHIESV 77 CH2ETOmY SM th jus di vem KE MB3778 1 10W 3 3k J lt gt P1 Tr1 2SC2412K R Q601 Q602 j Corrector current Ic 1A Div IC608 oe corrector output 1 IE H v Collector loss Pd Output drive terminal lt LU VO MAX SOmA 1 10W 10 J EJ
169. e transfer P_SAVE OFF PRC mode P_TMDS power save mode transfer P_TMDS OFF when VIDEO DETECT NONE and D SUB Ch is selected EM u s 3 1 38 1 6 4 Reset circuit IC101 M51957AFP Microcomputer reset terminal Power voltage M3 3V 196V DAMIAN TIFLA A 1 25V 0674 Output state non td 0 34 x External capacitor pF uSec 0 34 x 100001 Sec 3 4msec Selecting the reset voltage The operation power voltage range of the microcomputer 10102 is 2 7V to 5 5V Normally the voltage should be reset when the microcomputer power M3 3V drops to 2 7V or less but as the operation could malfunction due to power voltage noise etc the reset voltage is se lected so that resetting actually takes place at 2 1V or less Selection of resistance constant According to the DC DC converter design sheet the power voltage range is 3 3V to 3 5V However if the power voltage drops to 2 1V or less due to an error mode the following will be attained 1 R146 R156 reset voltage 2 1V reference voltage 1 25V Thus R14626 8kO and R156 10kQ are used Oscillation circuit gt With the specifications X100 CP285P030A11 the clock is supplied to the microcomputer s pin 12 with a 10MHz oscillator ASIC multiplies the microcomputer clock in the ASIC and uses it as the system clock 1 39 1 7 Panel interface Timing for panel power and interface signal PAN
170. ective ON Ineffective OFF Note 1 Setting values are different by timing Note 2 It is available with analog input 2 26 3 TROUBLE SHOOTING Contents Page 1 No Power 1 2 No Picture 2 3 Abnormal Picture or Ineffective Adjustment 4 This trouble shooting is premised that monitor has any problem 1 No Power POWER ON INDICATOR is off Is drive pulse Is approx 18V output from input into 4 Power primary circuit may have any problem Please check 1 of IC9012 VCC of the parts below Fuse F901 IC IC901 Trans T901 IC901 2 Protection circuit of power primary circuit or 12V OVP of power secondary circuit may operate Please check the parts below Is DC12V of power secondary circuit output 12V line may have any problem Please check the parts below MAIN Power Control circuit fuse F600 MAIN Power Controller IC IC608 MAIN Power 5 chopper IC IC611 Inverter Controller IC IC701 Inverter Controller IC IC702 Inverter Output Tr Q701 Inverter Output Tr Q702 Inverter Output Tr Q703 Inverter Output Tr Q704 Inverter Output trans T701 Inverter Output trans T702 MAIN Power 5V chopper IC IC611 inverter Controller ______ iczot inverter Controller IC 10702 DC12V Line Circuit Voltage DC12V Line Circuit Schematic Diagram Power Chopper 12V OVP Circuit Circuit Inverter Circuit
171. ed environment the operator could easily and confidently communicate colours without further colour management overhead in most common situations NATIVE Onginal colour presented by the LCD panel that is unadjustable Toolsi 4 4 SHARPNESS This function is digitally capable to keep crisp image at any timings It is continuously adjustable to get distinct image or soft one as you prefer and set independently by different timings EL EXPANSION MODE Sets the zoom method H EXPANSION The horizontal image is expanded to approximately 2 Limes V EXPANSION The vertical image is changeable VIDEO DETECT Selects tha method of video detection when more than ana computer is connecied English 11 pi 11 EST 11 Un 4 FIRST DETECT The video input has to be switched to FIRST DETECT mode When current video input signal is not present then the monitor searches for a video signal from the other video input port If the videa signal 15 present m the other port then the monitor switches the video source input port ta the new found video source automatically The monitor will not look for other video signals while the currant video source is present LAST DETECT The video input has to be switched to the LAST DETECT mode When the monitor is displaying a signal from the current source and new secondary source is supplied ta the monit
172. evel is applied at the center of the analog sync 0 3V LC1550X has two analog inputs DCI I A and D SUB and has the LAST DETECT function as one of the VIDEO DETECT functions The displayed and selected signals and the signals not displayed or selected must be judged so there are two Sync On Green synchronization sepa rating circuits 1 15 Study of S G clamp responsiveness The clamp responsiveness is determined by the response time 80nsec Typ of the comparator 10202 IC203 and the responsiveness of the drive circuit that gives the clamp potential to the video The responsiveness of the drive circuit is explained below The transistor turns ON when the comparator output is Lo At this time the transistor s base voltage is 2 9V due to the voltage dividing of R1 and R2 4 7kQ x 4 7 3 3 When V 0 6V the emitter s voltage is 3 5V and 15mA emitter current flows when the transistor is ON 5 0V 3 5V 100Q When this is expressed as an equivalence circuit it is as shown on the right ASV On Off control gt Tom lt At comparator output Lo 3 5V dota Q204 Q207 Clamp voltage output 10KQ Clamp voltage output et li 104 R1 3 3KQ 4 7KQ 80nsec delay FB 12202 IC203 1 104 At comparator output Lo 2 9V The capacitor C1 is charged with a constant current so as shown below the clamp voltage output s step response is a linear response instead of a prima
173. facture YY Year of Manufacture 52 ASCII Serial Number EDID EDITOR V1 44 010306 Copyright C Mitsubishi Electric 1995 2000 2 11 2 8 Inspection Unless particularly designated the performance is confirmed in 2 3 Standard setting state The display should be set to the full white pattern with signal generator 2 8 1 Electric performance 2 8 1 1 Confirming the operation of operation SW The picture must appear within four seconds after turning power switch ON Confirm that Power On Indicator is lit Synchronization must not flow when power switch is turned ON and OFF OSM must appear when CONTROL button is pressed The setting value must smoothly change and abnormalities such as noise must not occur when button is pressed 6 Press EXIT button and confirm that OSM picture disappears 1 2 3 4 5 2 8 1 2 Frequency change speed Confirm that it does not take so long time to change the picture when frequency is changed Within five seconds 2 8 1 3 Confirming frequency range Confirming preset timing Confirm that the synchronization is not deviated at the designated preset timing No 4 6 10 and 14 2 8 1 4 Confirming automatic adjustment function Input the confirmation timing with signal generator Set the pattern to 1 dot zigzag grid with frame Change the adjustment value of CLOCK intentionally and select AUTO ADJUST with OSM Confirm that the picture is put back to normal when
174. he viewpoints of both the work Internal and natural external environments Since methods of conventional electricity generation have a negative effect on the anvironment acidic and climate influancing emissions radioactive waste etc it is vital to conserve energy Electronics equipment in offices consume an enormous amount of energy since they are often left running continuously What does labelling involve This product meets tha requirements for tha TCO 88 scheme which provides for intarnational and environmental labelling of personal computers The labelling scheme was developed as a joint effort by the TCO The Swedish Confederation of Professional Employees Svenska Naturskyddsforeningen The Swedish Society for Nature Conservation and Statens Energimyndighet The Swedish National Energy Administration Wii 4 ABU EST 11 The requirements cover a wide range of issues environment ergonomics usability emission of electrical amd magnetic fields energy consumption and electrical and fire safety The environmental demands concern restrictions on the presence and use of heavy metals brominated and chlorinated flame retardants CFCs freons and chlorinated solvents among other things The product must be prepared for recycling and the manufacturer is obliged to have an environmental plan which must be adhered to in each country where the company implements its operational policy
175. iming write the default data of preset timing listed in 2 11 Timing chart with an external source by communication jit o RUTO D Hece az Z MODEL LCD1550X Model name SERIAL HUMBER WWW NECMITSUBISHI COM Confirm that the model name shown on the OSM picture in factorv mode is LCD1550X 2 6 General adjustment and inspection 2 6 1 Preparation Note1 Rough adjustment should be implemented with 100VAC 60Hz and aging heat running should be implemented with 240VAC 50Hz Note2 When DVI D is used for input unless particularly designated only Timing No 14 60kHz 75Hz XGA75 should be used for inspection Unless particularly designated adjustment should be carried out with DVI A input in factory mode and the setting state should be as follows To enter factory mode refer to 2 4 2 OSM operation method BRIGHTNESS MAX 220 CONTRAST CENTER 128 SHARPNESS CENTER 64 AccuColor NATIVE or sRGB COLOR CONTROL All of R Y G C B M and S should be 0 CENTER Before aging signal is input for confirmation of each operation switch operation Moreover unless particularly designated Timing No 14 should be used for adjustment 2 6 1 1 Confirming operation of operation SW and functions 1 Input the confirmation timing with the signal generator and set the pattern to OP2 2 Confirm that the picture appears within 4 seconds after turning the vacation switch and the power switch ON
176. input Tool2 Language OSM menus in Seven languages OSD Position Select the OSD position OSM Turn Off OSM turn off time OSM Lock out OSM control lock Resolution Notifier ON OFF Selection Factory Reset Reset all OSM control setting s back to the factory setting Information Display mode current resolution H V frequency Information Monitor Info Model name and Serial number information Document No VSPF A028 4 3 Control Lock Mode This control completely locks out access to all OSM control functions When attempting to activate OSM controls while in the Lock Out mode a screen will appear indicating the OSM controls are locked out To activate the OSM Lock Out function press both of select Left and select Right and hold down simultaneously In this mode only OSD Rotation and Input 1 2 Select function by front button are active and the other items are disable to select To resume back to user mode Press both of select Left and select Right and hold down simultaneously 4 4 Input Signal Connectors 4 4 1 Analog Video Input 15 pin mini D sub Table 3 Pin assignment for analog video input connector PIN NO Separate Sync Composite Sync Sync On Green lt 1 2 GREEN GREEN _ 4 DDC GROUND RED VIDEO GROUND SYNC GROUND async Hvsvc I V SYNC DDC SCL 4 4 2 Digital Interface Signals 4 4 2 1 Video Signals and Sync Signals Signal Format Panel Li
177. inspection 1 Surrounding temperature must be 25 Scope of inspection 2 The outer light except for the back light must be approx 500 1 for the inspection with turning ON the back light The outer light must be approx 1000 Ix for the inspection with turning OFF the back light In addition the outer light must be non directivity 3 The back light must be operated for appearance inspection with turning ON the back light 2 9 1 3 Picture pattern Appearance inspection with turning ON the back light must be carried out with eight colored picture patterns grayscale 0 and 255 2 9 2 Definition of applicable area Liquid crystal display defect standards are only applied to the display part pixel area 2 16 2 9 3 Standards for display conditions standard for errors defects In case the state of the picture displayed is not fully stable when the power switch is turned ON OFF the back light is operating to turn on and so on the following standards should not be applied tem Standard Continuous 2 bright dots R G 2 continued horizontally Note 1 Joined Continuous 2 black dots G B 2 continued horizontally Pairs Note 2 Continuous or more bright dots Both same and different colored Note EI Continuous 3 or more black dots dots should be counted ENIE Dot defects other than 1 and 2 R G B black and bright dots e ECH same colored bright dot Dist bat defect 65 Each color Note 5 defects istance between defect
178. is not displayed on the screen the problem can be resolved by displaying this OSM menu and changing DDC The DDC switching circuit is compatible with the asset management function and the changed settings are saved even when the monitor power is OFF Thus the selected EDID data is read in When considering the asset management function the external power 5V supplied from the signal connector may be lower than the Standards depending on the PC The power is 5V 5 for Standards As a design margin the power should be 3V at the signal connector and at least 2 7V at the V of the DDC peripheral circuit IC after passing through the shot diode Thus the DDC peripheral circuit uses an IC having V that operates at a 2 7V to 5 5V power voltage Voc 2 5V Min EEPROM is used to provide a margin Note that it is 5V 5 for the specifcation of this LCD monitor 1 27 1 5 2 DDC2BI DDC Cl function only DVI I connector side List of control signals Il COM Pin No I O Signal name Function Remarks 23 DDC_SDA DDC communication data DVI I connector 22 DDC_SCL DDC communication clock DVI I connector Function With the DDC2BI or DDC CI function data in the initialization EEPROM can be communicated with multiple functions such as external direct read amp write DDC2BI DDC Cl etc using the DDC communication line This is possible only when the monitor power is ON List of control signals
179. l Clock 65 00 MHz Horizontal Active 1024 pixels Horizontal Blanking 320 pixels Vertical Active 768 lines Vertical Blanking 38 lines Horizontal Frequency 48 36 kHz Vertical Frequency 60 0 Hz Horizontal Sync Offset 24 pixels Horizontal Sync Width 136 pixels Vertical Sync Offset 3 lines Vertical Sync Width 6 lines Horizontal Border 0 pixels Vertical Border 0 lines Horizontal Image Size 304 mm Vertical Image Size 228 mm Interlaced NO Serial number Week of Manufacture Year of Manufacture ASCII Serial Number ANALOG EDID DATA DUMP HEX 00 FF FF FF FF FF FF 00 38 A3 C8 65 SN SN SN SN WW 01 03 OE 17 78 EE C6 A4 9E 57 4A 99 26 19 AF 57 BF EE 00 01 01 0101010101 01 01 01 01 01 01 01 01 01 64 19 00 40 41 00 26 30 18 88 36 00 30 E4 10 00 00 18 00 00 00 FD 00 32 4B 3C 08 00 OA 20 20 20 20 20 20 00 00 00 FC 00 4E 45 43 20 4C 43 44 31 35 35 30 58 0A 00 00 00 FF 00 52 52 52 52 52 52 52 52 52 52 52 52 52 00 CS SN WW YY S2 CS Serial number Week of Manufacture Year of Manufacture ASCII Serial Number Check Sum 25 Timing Image Normal Display Sync Digital Separate Bit 1 OFF Bit 2 OFF Monitor Range Limits block 2 Vertical Rate 50 Hz Vertical Rate 75 Hz Horizontal Rate 30 Horizontal Rate 60 Maximum Pixel Clock 80 MHz GTF Data 00 20 20 20 20 Minimum Maximum kHz kHz Minimum Maximum 20 20 Monitor Name block 3 NEC LCD1550X Monitor Serial
180. lock 1 Preferred Timing Mode Pixel Clock 65 00 MHz Horizontal Active 1024 pixels Horizontal Blanking 320 pixels Vertical Active 768 lines Vertical Blanking 38 lines Horizontal Frequency 48 36 kHz Vertical Frequency 60 0 Hz Horizontal Sync Offset 24 pixels Horizontal Sync Width 136 pixels Vertical Sync Offset 3 lines Vertical Sync Width 6 lines Horizontal Border 0 pixels Vertical Border 0 lines Horizontal Image Size 304 mm Vertical Image Size 228 mm Interlaced NO Image Normal Display Sync Digital Separate Bit 1 OFF Bit 2 Monitor Range Limits block 2 Minimum Vertical Rate 50 Hz Maximum Vertical Rate 75 Hz Minimum Horizontal Rate 30 kHz Maximum Horizontal Rate 60 kHz Maximum Pixel Clock 80 MHz GTF Data 00 0a 20 20 20 20 20 20 Monitor Name block 3 NEC LCD1550X Monitor Serial Number block 4 S2 2 10 DIGITAL EDID DATA DUMP HEX 00 FF FF FF FF FF FF 00 38 A3 C8 65 SN SN SN SN WW YY 01 03 80 1E 17 78 EE C6 A4 9E 57 4A 99 26 19 57 BF 00 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 64 19 00 40 41 00 26 30 18 88 36 00 30 4 10 00 00 18 00 00 00 FD 00 32 4B 1E 08 00 20 20 20 20 20 20 00 00 00 00 4 45 43 20 4C 43 44 31 35 35 30 58 0A 00 00 00 FF 00 52 52 52 52 52 52 52 52 52 52 52 52 52 00 CS SN Serial number WW Week of Manufacture YY Year of Manufacture 52 ASCII Serial Number CS Check Sum SN Serial number WW Week of Manu
181. lock 65 00 MHz Interlaced NO Horizontal Active 1024 pixels Image Normal Display Horizontal Blanking 320 pixels Sync Digital Separate Vertical Active 768 lines Bit 1 OFF Vertical Blanking 38 lines Bit 2 OFF Horizontal Frequency 48 36 kHz Monitor Range Limits block 2 Vertical Frequency 60 0 Hz Minimum Vertical Rate 50 Hz Horizontal Sync Offset 24 pixels Maximum Vertical Rate 75 Hz Horizontal Sync Width 136 pixels Minimum Horizontal Rate 30 kHz Vertical Sync Offset 3 lines Maximum Horizontal Rate 60 kHz Vertical Sync Width 6 lines Maximum Pixel Clock 80 MHz Horizontal Border 0 pixels Data 00 20 20 20 20 20 20 Vertical Border 0 lines Horizontal Image Size 304 mm Monitor Name block 3 NEC LCD1550X Vertical Image Size 228 mm Monitor Serial Number block 4 S2 SN Serial number WW Week of Manufacture YY Year of Manufacture 2 ASCII Serial Number EDID EDITOR V1 44 010306 Copyright C Mitsubishi 19 DIGITAL EDID DATA DUMP HEX 00 FF FF FF FF FF FF 00 38 A3 C8 65 SN SN SN SN WW YY 01 03 80 1E 17 78 EE C6 A4 9E 57 4A 99 26 19 4F 57 BF EE 00 01 01 010101010101 01 01 01 01 01 01 01 01 64 19 00 40 41 00 26 30 18 88 36 00 30 4 10 00 00 18 00 00 00 FD 00 32 4B 3 08 00 OA 20 20 20 20 20 20 00 00 00 00 4E 45 43 20 4 43 44 31 35 35 30 58 00 00 00 00 52 52 52 52 52 52 52 52 52 52 52 52 52 00 CS SN Serial number WW Week of Manufacture Y
182. lt Eds MMMMMS MMMM 54 H 542 2 E 5 acacacaca a a R x D 818 818 1818 8 halide N 1 1 1 Ji D D 1 1 1 1 1 1 RU mn 2 lt ds Sies 3 G Q Q O S SG O 9 9990 a lt noo TM O U jie PRAS T OL WSLAL 9 mm mm m G 0 a G Z lt m 2 L 20 o 9 gt 6 x MOL L 1 ow Kis 2 T 0L NSLAL 6108 I 7168 la e z 8315 S 2 5 1dsizpytujna SA 1 8 a lt 5 ir Rm 8 L b S tua lt 3 1 8 o L 5 i TWAQI 3 5 ia lt 5 Mica S lo i 2 L O Lo La BER NN HA fre 1 O 4068 gt is T o PAP b 1 swa L T GTTMOTAT xa SWALI BTI 2 amp C3 oxi lt 1 TOT 00821 2 248214 1541 3 BOLLOEVLIIS 5 29 oe I ia oS 2 i z L 1 u lt T AT TIMSTAT 771 LILO lt I IX o z L 1 TWKI T IT TIMOTAT Aog 5 2319 kI xi 0 z L R 6119 1 a 5 4 g a 1 2 2 S NIS Lani 1 i T8 8 s porter 20121nd1n0 3230 He 2478 3 s gt 1 5 1 T 2 4 5 2 lt 2 XA 8 H MES 1 DOO 5 i l lt 1 T OTINST 1777 3 S oF ot KI exu 8 ONASA I
183. ltage fluctuations and secondary side load fluctuations 3 Switching of the PRC and pseudo resonance is controlled by inputting to IC901 via IC905 with a microcomputer signal Standby mode Normal mode PRC mode pseudo resonance mode Microcomputer signal J901 1 PIN L H IC901 oscillation frequency Approx 20kHz Approx 50k 150kHz 4 The secondary side output voltage of this power circuit is a single phase 12V Block diagram AC100 120 PRE Rush 220 240 0 EMI filter Rectification prevention Starting resistance I Vcc Transformer e e 12V To inverter To main C901 HIC control IC b Y IC904 T Shunt regulator P SAVE microcomputer signal 1 2 Detailed description of each circuit 1 2 1 Pseudo resonance circuit method With pseudo resonance when the discharge of energy secondary coil current 0 ends on the secondary side of the transformer the transformer ends the transformer connection Pseudo resonance takes place between the primary side inductance and voltage resonance capacitor or parasitic capacity between the drain and source The drain voltage is reduced to the sine wave When the drain voltage reaches the bottom valley of this vibration waveform and the next cycle turns ON soft switching takes place With the effect of the voltage reso nan
184. mimi D SUB to DWI A signal cable to the connector of the display card in your system Figure 2 the Mac Connect the MultiSync Macintosh cable adapter to the camputer Figure B 1 Attach the 15 pin mini D SUB signal cable ta the MultiSync Macintosh cable adapter Figure B 1 NOTE Some Macintosh systems do not require a Macintosh cable adapter 3 Remove connector cover Connect the signal cable to the connector on the back of the monitor Place the video signal cable Figure C 1 Replace connector cover NOTE Incorrect cable connections may result in irregular operation damage display quality components of LCD module and or shorten the madule s 4 Remove power cord cover Connect one and af the power cord to the AC inlet on the back of the monitor and the other end to the power outlet Figure D 1 Replace the power cord cover NOTE Please refer to Caution section of this manual for proper salaction of AC power cord 5 Check the Vacation Switch on the right hand side of the monitor is in the ON position Turn on the monitor with the Power Button Figure E 1 and the computer NOTE There are two swilches one on the right side and one on the front side of the monitor DO NOT switch on off quickly English 3 a ABU EST E 6 complete the setup of your MuliiSyne LCD monitor use ihe following OSM controle Auto Adjust Contrast Analog inpu
185. nk T M D S transition minimized differential signaling architecture R G B color depth 8 bit Dot clock rate 80MHz maximum minimum Hsync width N A DE Only minimum Vsync width N A DE Only 8 Document No VSPF A028 4 4 2 2 Input Signal Connectors Table 4 DVI Connector Pin Assignment Signal Name Signal Name No TMDS Data 0 73 Data Shed 38 TMDS Dala0 ro pec 9 7 T M D S Data Clock Shield 8 AndogVetid Sy 25 TMS r T M D S Data 1 Alea Red ane CS Analog Ground Ground return for 5V HSync and Vsync analog R G and B return DVI Compatible Host Receptacle Connector 4 5 DDC This monitor compliance of VESA DDC 2B See appendix 2 for EDID data 4 6 Other functions 4 6 1 Expand function This monitor can expand the input image when smaller resolution than 1024 768 is input and the expanding ratio is selected by the micro processor correspond to input signal 4 6 2 Auto setup function Auto setup function is performed to detect the input signal format H V frequency video active area sync pulse and back porch by the internal microprocessor Adjustment items are as follows H V position H Size Clock Fine Clock Phase H Size Clock and
186. nt instruments 2 1 2 3 Standard setting State snanar nanna rna 2 1 2 4 Names of each LCD monitor part and adjustment methods 2 2 2 4 1 Configuration of front control panel nanna nanna 2 2 2 4 2 OSM operation method nar enne nennen nennen 2 2 2 4 3 Configuration of signal input power input section 2 3 2 5 PWB mechanism and appearance 2 4 2 5 1 Visual and conductivity 2 nne 2 4 2 5 2 Mechanism and appearance inspection 2 4 2 5 3 PWB adjustment rc e e ER Da RENE 2 6 2 5 3 1 Initial writing in EEPROM data 2 6 2 6 General adjustment and 2 6 2 671 Prepara On uu a dace fett B Ja fa aha 2 6 2 6 1 1 Confirming operation of operation SW and functions 2 6 2 6 1 2 Inspection of picture nanna 2 6 2 6 E o OTe EA ie eti ee UR Rd Rie Hr EH e be Pee us 2 7 2 6 2 Main 2 7 2 6 2 1 Confirming OSM picture during heat running Le 2 7 2 6 2 2 BlIAS djustment ii ae ei a in e tee id oce dr ee 2 7 2 6 2 3 22 45 e L 2 7 2 6 2 4 BRIGHT LIMIT adjustment nanna 2 7 2 6 2 5 Confirming color coordination of Liquid Crystal Panel
187. o a ee 1 1 ced 1 1 1 2 Detailed description of each circuit nanna 1 2 1 2 1 Pseudo resonance circuit method essen 1 2 1 2 2 Switching circuit operation I ra 1 3 1 2 3 Description of operation nara nr nnns nennen 1 4 1 2 4 Protection a ette er ace deese ete n t ed d 1 6 1 2 4 1 Eatchi sitet tete TR etd ED 1 6 1 2 4 2 Overheat protection circuit 1 6 1 2 4 3 Overvoltage protection circuit nn 1 7 1 3 PWB MAIN basic specifications eene 1 8 1 3 1 Basic specifications nanna 1 8 1 3 2 PWB MAIN circuit block eene 1 9 1 3 3 Input output connector pin 1 10 1 4 Video input signal specifications nanna 1 11 1 4 1 Video interface peripheral circuit 1 12 1 4 2 Horizontal vertical synchronizing signal input 1 13 1 4 3 Composite sync V separation circuit nn 1 14 1 4 4 Sync On Green synchronization separating 1 15 US ESOENIBISATE TOC 1 17 1 4 6 Input signal presence judgment function ena 1 18 1 4 7 Input signal switching control function ne 1 21 1 5 DDC interface peripheral circuit 1 24 1 5 1 DDC switching control function
188. olor temperature AccuColor to N NATIVE 4 Confirm that the color coordination is within the following value range at the center of the picture X 0 305 0 03 Y 0 324 0 03 2 7 2 7 Configuration of DDC EDID data The configuration of DDC EDID data is as follows EDID DATA DUMP TEXT ANALOG EDID DATA DUMP TEXT Manufacturer Code NEC Product Code HEX 65C8 Product Code DEC 26056 Microsoft INF ID NEC65C8 Serial Number HEX SN Week of Manuf WW Year of Manuf YY EDID Version 1 EDID Revision 3 Extension Flag 0 Video Input Signal ANALOG Setup NO Sync on Green YES Composite Sync YES Separate Sync YES V Sync Serration NO V Signal Level 0 700V 0 300V 1V p p Max Image Size H 30 cm Max Image Size V 23 cm DPMS Stand By YES DPMS Suspend YES DPMS Active Off YES GTF Support NO Standard Default Color Space YES Preferred Timing Mode YES Display Type RGB Color Color Gamma 2 20 Red x 0 620 Red y 0 340 Green x 0 290 Green y 0 600 Blue x 0 150 Blue y 0 100 White x 0 310 White y 0 340 Established Timings 720x400 70 Hz 640x480 60 Hz 640x480 67 Hz 640x480 72 Hz 640x480 75 Hz 800x600 56 Hz 800x600 60 Hz 800x600 72 Hz 800x600 75 Hz 832x624 75 Hz 1024x768 60 Hz 1024x768 70 Hz 1024x768 75 Hz Standard Timing 1 NOT USED Standard Timing 2 NOT USED Standard Timing 3 NOT USED Standard Timing 4 NOT USED S
189. on AH2 path selection No S Gin DVI I A Lo Don t Care S G present in DVI I A Hi Don t Care No S Gin D SUB Don t Care Lo S G present in D SUB Don t Care Hi If the signal is displayed and selected when changing the path it will be judged that the signal has changed and the mode will be changed Analog signal DVI I A and analog signal D SUB input selection The microcomputer sets the ASIC internal input switching switcher SOURCE register to analog 1 for DVI I A and to analog 2 for D SUB The video buffer output control follows the table below Only the input and displayed Ch side is enabled with this and video is input into ASIC measures for crosstalk during ASIC 2Ch input SEL 1 SEL 2 Video buffer output Lo Disable Equivalent to GND pull down at 1200 Hi Enable video through 1 21 Since the buffer power is decreased when disabled energy can be conserved by disabling both analog Ch video buffer outputs during the PMS mode when the front power is OFF and during digital Ch display Front power switch Display input Ch SEL_1 SEL 2 On DVI I 0 Lo Lo Normal Hi On DVI I Lo During PMS Lo Normal Hi On D SUB Lo During PMS Lo Off Don t Care Lo Lo Analog signal DVI I A and analog signal D SUB input selection SELi L DVI 47u RED 1 3 1 0 01 47 SKT GREEN 1 3 il S 0 01p 47 SKO BLUE 1 L3 l 8 ootu SEL2 D SUB
190. on of all bright or all black dots Pobdgphh pus Not counted as NG Combination of bright and black dots ex x and so on Note 4 The dots for composing 2 horizontal combinations of R G shall be excluded from counting Note 5 Adjacent same colored bright dot defects To be counted as NG Not to be counted as NG R RY R RON R PN 4 4 4 n 7 7 J 1 1 J 1 1 l 1 1 l 1 1 1 lt 6 5mm x lt 6 5mm X lt 6 5mm x NS NA EA NN d Approach of bright Approach of different and black dots colored dots Note 6 Approach of adjacent defects The distance betw een adjacent defects should be longer than 15mm Note 7 A set of 2 or more dot defects in an area of 5x5 pixels If there are 2 or more dot defects 6 in an area of 5 x 5 pixels such a set of dot defects shall be counted as one cluster 5 x 5 pixels Dot defect 5 There should be less than 2 clusters throughout the screen area 1 cluster Note 8 Approach of defects of 1 or 2 in an area of 5 x 5 pixels To be counted as NG 5x5 pixels 5x5 pixels RG RG There should be no approach of zsinanarea of 5 5 pixels Uneven linear contrast Unacceptable if it can be seen 11 Spot stain i 42 Linear dust m contamination W width mm L length mm Appearance According to circle spec inspection Circular dust av during Con
191. or then the monitor will automatically switch to the new video source When current video input signal is not present then the monitor searches for a video signal from the other video input port If the video signal is present in the other part then the monitor switches the video source input port to the new found video source automatically NONE The Monitor will nat search the other video input port unless the monitor is turned on SELECTION This function selects EDID Data for ANALOG signal or DIGITAL signal on the input When the DVI D is connected to DI Selection is recommended to be selected ta DIGITAL When tha DVI A is connected to DVI Selection is recommended to ba selected to ANALOG DIGITAL EDID DATA fer DVI DIGITAL input is available ANALOG EDID DATA for ANALOG input is available English 12 ABU EST Tools 2 2 E pi LANGUAGE OSM control menus are available in seven languages OSM POSITION You can choose where you would like the OSM control image to appear on your screen Selecting OSM Location allaws you to manually adjust the position af the OSM control menu left right down or up OSM TURN OFF The OSM control menu will stay on as long as it is usa In iie OSM Tum submenu you can select how long the monitor waits after the last touch of a button to shui off the OSM control menu The preset choices 10
192. ot zigzag grid Visual check Image noise must not be Sampling noise frame remarkable 1 4 6 10 14 DVI A Picture position 1 dot zigzag grid Vis lch ck Top bottom left and right of difference frame the frame must be seen Picture position bottom left and right of Chromatic colored vertical Horizontal lamp noise dot noise jitter and Gray scale Vista SEK grav scale noise must not be 14 PEP seen 4 6 10 14 Smear WINDOW A Smear etc must not be Pixel cross talk OPTION2 pattern 06 Visual check Video tracking OPTION2 pattern Visual check e 14 DVI A DVI A BRIGHTNESS OPTION pattern 06 Visual check A AA pe carried Horizontal line Horizontal lamp CON with Horizontal line must not be DVI A flickering noise gray scale visual cheek remarkable There should be less than 1 pc of spot on monochromatic picture and the size should be Unevennessispot 128 256 half tone Visual check within 1 2mm 14 DVI A on LCD panel Uneven spot should be less than 10m when it is judged on 128 255 gradation 1 If flickering is still seen in the inspection in timing No 14 with the designated display pattern change the pattern to the below then confirm that the picture is displayed correctly Confirmation pattern Frame H character H character Font size 7 x 9 Cell size 13 x 14 2 14 2 8 2 2 Confirming color coordination
193. otection TSD circuit operate The latch circuit holding current is 70u A max Ta 25 C when the voltage of pin is 10 5V By considering that this increases lightly at high temperatures and by passing a current of 140u A or more to the 4 from the starting resistor the power circuit will maintain the stopped state A delay time is provided with C2 in the hybrid IC to prevent malfunctioning by noise etc If the OVP or TSD circuit operation continues for approx 10 sec or more the latch circuit will operate Note that even if the latch circuit operates the constant voltage power Reg circuit is function ing in the control circuit and the circuit current is high Thus the voltage of pin will drop suddenly When the voltage of pin drops to below the operation stop voltage 10 1V typ the circuit current will drop to 70u A Ta 25 C or less so the voltage of pin 4 will start rising When the operation start voltage 17 6V typ is reached the circuit current will start to in crease again so the voltage of pin will drop suddenly Thus when the latch circuit is oper ating the voltage of pin will rise and lower between 10 1V typ and 17 6V typ and pre vent the voltage of pin 4 from rising higher An example of the voltage of pin 4 waveform during latch circuit operation is shown in the figure below The latch circuit is canceled by lowering the voltage of pin 4 to less than 7 9V and generally it is
194. port output port Ch SCDT PDO PD P_TMDS Hi Hi TMDS receiver output enable Normal Hi TMDS receiver On Hi DVI I D AS on D Lo Lo TMDS receiver output open During PMS PWM TMDS receiver intermittent On Hi Don t Normal Hi TMDS receiver On On DVI I A Care Lo TMDS receiver output open During PMS PWM TMDS receiver Hi intermittent On Don Normal Hi TMDS receiver On FIRST On D Sub an Lo TMDS receiver output open During PMS PWM TMDS receiver LAST DETECT Hi intermittent On NONE Lo Off C Lo Lo TMDS receiver output open Lo TMDS receiver Off Lo are 1 20 1 4 7 Input signal switching control function List of control signals Pin No 1 O Signal Function Remarks 47 51 I O RSTN ASIC control ASIC 7 O SEL_HS1_SG1 H V Sep and C S and S G input switching 74ACT157SJ 8 O SEL_HS2_SG2 H V Sep and C S and S G input switching 74ACT157SJ 33 O SEL_1 DVI I A path video buffer output control Video buffer 19 O SEL_2 D SUB path video buffer output control Video buffer Functions Sep and C S and S G input switching When using analog signals the microcomputer uses the selector to change the signal path input into the ASIC AH terminal according to the input signal judgment results SEL_HS1_SG1 SEL_HS2_SG2 Input signal judgment results AH1 path selecti
195. r CS Check Sum Monitor Name block 3 NEC LCD1550X Monitor Serial Number block 4 S2 SN Serial number WW Week of Manufacture YY Year of Manufacture 52 ASCII Serial Number EDID EDITOR V1 44 010306 Copyright C Mitsubishi Electric 1995 2000 2 9 DIGITAL EDID DATA DUMP TEXT Manufacturer Code NEC Product Code HEX 65C8 Product Code DEC 26056 Microsoft INF ID NEC65C8 Serial Number HEX SN Week of Manuf WW Year of Manuf YY EDID Version 1 EDID Revision 3 Extension Flag 0 Video Input Signal DIGITAL DFP Compatible NO Max Image Size H 30 cm Max Image Size V 23 cm DPMS Stand By YES DPMS Suspend YES DPMS Active Off YES GTF Support NO Standard Default Color Space YES Preferred Timing Mode YES Display Type RGB Color Color Gamma 2 20 Red x 0 620 Red y 0 340 Green x 0 290 Green y 0 600 Blue x 0 150 Blue y 0 100 White x 0 310 White y 0 340 Established Timings 720x400 70 Hz 640x480 60 Hz 640x480 67 Hz 640x480 72 Hz 640x480 75 Hz 800x600 56 Hz 800x600 60 Hz 800x600 72 Hz 800x600 75 Hz 832x624 75 Hz 1024x768 60 Hz 1024x768 70 Hz 1024x768 75 Hz Standard Timing 1 NOT USED Standard Timing 2 NOT USED Standard Timing 3 NOT USED Standard Timing 4 NOT USED Standard Timing 5 NOT USED Standard Timing 6 NOT USED Standard Timing 7 NOT USED Standard Timing 8 NOT USED Detailed Timing b
196. r output can be directly connected e 1 Differential signal RXO BLUE Differential signal RX1 GREEN Differential signal RX2 RED 1 Trigger point Tolerable jitter skew range 640 x 480 60Hz 640 x 400 70Hz 800 600Q60Hz 1024 768 60Hz Typ Max Typ Max Typ Max 3 972ns 2 500ns 1 538ns Tos 1 19ns 0 75ns 0 46ns TpJ 1 59ns 1 00ns 0 62ns Tskew inter 23 8ns 15 00ns 9 23ns Tpixel 39 72ns 25 00ns 15 38ns DVI Ver 1 0 Standards e Clock jitter T 0 3 x Data jitter T inter pair u 0 4 x T The data jitter is specified with the template d Inter pair kew Tasas inter 50 6 1 17 1 4 6 List of control signals Input signal presence judgment function u COM Pin No I O Signal name Function Remarks 47 51 I O MS RSTN ASIC control ASIC 3 C S H measurement at H V Sep and C S DVI I A 18 C S V1 V measurement at C S DVI I A 2 l S G_H1 H measurement at S G DVI I A 5 C S_H2 H measurement at V Sep and C S D Sub 20 5 V2 V measurement at C S D Sub 4 S G_H2 H measurement at 5 D Sub 64 l SCDT TMDS SYNC DETECT Sil143CT100 63 PDO TMDS output buffer power save 1143 100 65 PD TMDS internal logic power save Sil143CT100 52 TMDS TM3 3V power supply OFF Lo ON Hi SI3033LSA Function Analog input
197. rii cas AR RR Few 7 28 L ontrol Lock MOBB uu uuu i iew s a aa b a tecta a den fa ei 8 23 8 44 1 Analog Video Input I5PAMINLPESUB terree nen n pne ERR Rennen pan eR enar nant hh gea een pae as 8 2345 2 Doi eorr RR er eee pec E gue eed ce eng vend eec 8 m 9 28 9 101 18 Mietet a a 9 A C1 Expand L 9 A 02 Auto sop 9 22222222 l dele ee iad 10 MINE dn a 10 2 2 dain tien 10 nia olor temperate 11 SAJDEGME da 11 11 SO NC MIS iic eee ient reticere ta den najd ek 12 6 1 WIC BASE 0 TEE 12 SAIS USA u uuu ra AA 12 EE IUe f POZORNIE R POR NCT 12 12 G 5 ADGBSSOIIBE UR a ER eden 12 L Environment 8 56111611 13 f temperature Relative Humidity amp Altitude ye i EE 13 La sibiglioni tast PARI u ida ese rep e AO
198. ry response As an image this is not a phase control such as with a servo and instead is equivalent to speed control Thus the response is fast When EV then At AV 0 1uF 15mA AV 6 7u AV Example If the minimum value of the H SYNC width is 0 5u sec the maximum voltage fluctuation width that can be compensated at 0 5u sec is 0 075V according to the above formula For CRT FHX7120 this is 0 079V which is approximately the same Study of S G circuit fluctuation and input signal fluctuation The A5V power voltage is 5V 0 1V and the voltage dividing resistor has a 1 fluctuation so the slice level clamp level is within the following range Slice level clamp level Max 0 118V 390x1 01x5 1 12000 120 4700 x0 99 390x1 01 Slice level clamp level Typ 0 113 390 5 12000 120 390 4700 Slice level clamp level Min 0 109 390 0 99 4 9 12000 120 4700 1 01 390 0 99 The S G synchronizing signal amplitude has a 0 25V to 0 35V amplitude fluctuation However the slice level clamp level 0 118V is smaller than this there are no problems design wise 1 16 1 4 5 TMDS receiver The TMDS signal 4Ch differential signal shown below is input for the digital input signal The TMDS receiver IC500 51143 decodes this TMDS signal and generates an 8 bit x 3 RGB data signal VCLK DE HSYNC and VSYNC Maurice2 is compatible with the digital input so the TMDS receive
199. s Decides under limit of variable range MIN BRIGHT LIMIT MMER CONTROL Changes to lower Changes to higher BRIGHT LIMIT MAX when thermal control is completed BRIGHT MIN MER BRIGHT LIMIT MAX BRIGHT LIMIT to BRIGHT MAX MAX MER CONTRO Changes to lower Changes to higher Decides ADC value at starting of thermal control 1 to DEMMER MER START ADC value ADC value END 1 MER CONTRO Changes to lower Changes to higher Decides ADC value when thermal control is completed DEMMER MER END ADC value ADC value START 110 MER CONTROL Small Large 0 caution 0 MER DELTA MMER CONTROL Indicates BRIGHT MAX value controlled thermally BRIGHT MAX DIMMER CONTROL Indicates ADC value detected ADC DIMMER CONTROL Indicates MAX HOLD value of ADC value ADC ADC MAX RESET Resets ADC MAX value BIAS Automatically adjusts RGB clamp voltage GAIN Outputs digital data FFH when 0 7V is input PLL LOCK EDGE FRONT BACK RISE FALL AUTO Appoints basic svnc signal edge PCLK 32 5MHz 35 0 2 37 5 Switches panel lock 325 375 SERVICE INF Indicates lamp operation time MPU operation time and MPU 222000 CLKHDLY Micro adjustment of H clock position of signal input to panel 2 25 CHANGE SETUP OSD EEP WRITE EEPROM write protect EDID Effective ON PROTECT Ineffective OFF Initialize with AC Power OFF of monitor ON POWER SAVE ln fore Power save mode Eff
200. s mm EE Pairs ID Approach of adjacent defects of JDistance of approach x 15mm Note6 6 A set of 2 or more dot defects in 21 89 Defective area of 5x5 pixels inspection proximity 6 in consideration back light in an aria of 5 5 pixels Pairs Note 8 ON Approach of adjacent defects of 2 Total Total numbers of bright dots R G B and black dots R G B numbers Piece of defect Total numbers of bright dots in G Em 9 1 The defective part over 30 compare to area of 1 dot is regarded as a dot defect 2 When the picture pattern is set to black the luminance more than 30 of 1 dot is regarded as a bright mode dot defect 3 When the picture pattern is set to white the luminance below 70 of 1 dot is regarded as a black mode dot defect 4 An independent defective dot not adjoined to other defective dot is regarded as a point dot defect 5 The one composed of pieces of linked defective dots is regarded as points linked dot defect 10 DO NOT use ND filter in counting bright dot s dot Black dot Note 1 R G 2 dots continued horizontally G B 2 dots continued horizontally To be counted as NG Not to be counted as NG Combination of bright Combination other than and black dot 2 horizontal combination RG RG RG RG R G M i and so GB GB Note 2 D 2 x3 dots Note 3 3 defect combination Combination patterns to be counted as NG Combinati
201. screen or relerence material directly in front of you to minimize turning your head while you are typing English 16 pi 18 EST Avoid displaying fixed patterns on the monitor far long periods of time ta avoid image persistence after image effects Gel regular eye checkups Ergonomics To realize the maximum ergonomics benefits we recommend the following Use the preset Size and Position controls with standard signals Use preset Colour Setting Use non interlaced signals with a vertical refresh rata batwean 60 75 Hz Do not use primary colour blue on a dark background as itis difficult ta see and may produce eye fatigue to insufficient contrast English 17 IT ABU EST ALL PARTS LIST MODEL NO LCD1550X C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B6 3V 105 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C CERAMIC CHIP B6 3V 105 K 1 6X0 8 C CERAMIC CHIP B50V 103 K 1 6X0 8 C CERAMIC CHIP B16V 104 K 1 6X0 8 C
202. selection move to next tag hen SW is pressed SW board P10_4 AN4 K10 OSD menu selection R hen SW is pressed SW board 10_5 5 11 OSD menu selection hen SW is pressed SW board P10_6 AN6 K12 Close OSD display hen SW is pressed SW board P10_7 AN7 K13 AVCC OSD menu selection L hen SW is pressed Vcc SW board AVSS D A power supply Vcc CNVSS BYTE For onboard writing Serial writer RESET Reset signal input L Reset normally H VCC Microcomputer power supply 3 5V VREF Reference power for D A converter VSS Microcomputer GND DG XIN Clock input 10MHz XOUT 1 48 N C Panel clock frequency setting separate table 1 FS_2 FS_1 FS_0 0 0 0 30MHz 0 0 1 32 5MHz 0 1 0 35MHz 0 1 1 37 5MHz 1 0 0 40MHz Panel maker identification setting separate table 2 P ID3 P ID2 P ID1 P IDO Panel clock Panel maker Panel type EDID write protect 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 HITACHI TX38D26VCOCAA Invalid 1 49 2 Adjustment procedure 2 1 Application This adjustment procedure applies to the 15 inch LCD1550X LCD display moni
203. ssor controlled with a resident memory base of pre programmed screen and input configurations and also digital user controls The LCD1550X color monitor automatically scans all horizontal frequencies between 30 0kHz and 60 0kHz and all vertical frequencies between 50 0Hz and 75 0Hz The LCD1550X color monitor supports the VGA SVGA non interlaced XGA Apple Macintosh family and the other VESA compatible graphics adapters The LCD1550X color monitor has a maximum horizontal resolution of 1024 dots and a maximum vertical resolution of 768 lines for superior clarity of display The LCD1550X color monitor has a 15 0 diagonally measured LCD The LCD1550X color monitor has a 15 pin mini D sub connector that is configured for IBM VGA compatible adapter And also LCD1550X color monitor has a DVI I connector for Digital video and Analog video signal adapter The LCD1550X color monitor has a ambix Technology Dual input technology allowing both analog and digital inputs of one connector DVI I as well as additional legacy analog support of a traditional 15 pin VGA connector Provides traditional MultiSync technology compatibility for analog as well as TMDS Transition Minimized Differential Signaling based digital compatibility for digital inputs The LCD1550X color monitor has a screen rotation mechanism and this function is more effective with Pivot software 4 Document No VSPF A028 2 General Description Quick Reference Produ
204. t 0 7A gt OK Temperature derating Rating derating The above maximum input current is calculated from the DC DC maximum output current specifications and is not the input current value that flows at the maximum load The DC DC maximum output current value has a margin over the maximum load current value so the actual maximum input current is approx 0 7A 1 33 Output smoothing capacitor C641 C652 25V 470M M ESR 0 150 20 C 100kHz Tolerable ripple current 670mArms 105 C 100kHz Tolerable ripple current frequency compensation coefficient 1 5V output system Ripple voltage specifications 50mVp p Ripple voltage Al x ESR 0 150 0 146Ap p x 0 150 0 022Vp p 5 50mVp p gt OK Ripple current Al 2 3 0 042 Arms Tolerable ripple current 670mArms gt OK 3 3V output system Ripple voltage specifications 50mVp p Ripple voltage Al x ESR 0 150 0 121Ap p x 0 150 0 018Vp p lt 50mVp p gt OK Ripple current Al 2 3 0 035Arms Tolerable ripple current 670mArms gt Input capacitor C604 25V 470M M ESR 0 150 MAX 20 C 100kHz Tolerable ripple current 670mArms 105 C 100kHz Tolerable ripple current frequency compensation coefficient 1 Ripple voltage Don 1 Don Don Vou Vin 5 25V 12V 0 44 0 44 1 0 44 0 50Arms s Tolerable ripple current 670mArms OK e Oscillation frequency 1 x R 1 330pF x 15kQ 200kHz 1 34 PQICZ21H2Z
205. t of 1 3 dot size Defect size is confirmed by using 10 times of loupe Also dot defects include intermittent bright and dark dots which can be recognized with the naked eye A 1 dot 5x5 pixels Note 10 No ND Filter for luminance defects Note 11 A stain on the single color screen specified as follows Number 1 max CSize 1 5mm max Note 12 Spot Mura judged by 128 255gradiation screen Size D 15mm Max Note 13 Ignore the thing that can be wiped out Note 14 Applicable only in A area not in B area 19 Document No VSPF A028 Note 1 Examples of Adjacent 2 dots are as follows Dot defect combination 2 Bright dot d Dark dot Count Criteria R G horizontal adjacent Note1 RG GB Note1 RG GB n I Combination of bright and dark dots RG Allowed Combination of different color Note 2 Examples of Adjacent 3 dots are Dot defect combination as follows Bright dot Lo dot Allowed Count Criteria Adjacent 3 bright dots Note3 1 T Adjacent 3 dark dots Note3 Combination of bright and dark dots IU Allowed Note 4 Defect dots which make up A R G horizontal adjacent are not counted Note 5 Examples of Distance between 2 dots x6 5mm are as follows Dot defect combination dle Bright dot lo dot Count Criteria Combination of same color bright dots R G or B
206. t only s Auto Adjust Analog input only Relar ta the Controls section of this Users Manual for a full description at these OSM controls NOTE l you have any problems please refer to the Troubleshooting section of this User s Manual NOTE Refer to User s Manual in the NEC LCD Setup Software CD case for installation and operation of this software Adapter net included Maciniceh G3 and d do not need a Macintosh cable adapter Figure B 1 English 4 4 1 257 Inputi gt lt input fik Card Cover i L 3 bes Bur P Figure 0 1 Connector Power Gard 9 Figure 1 Cover right Vacation Seach Power Button Figura E 1 English 5 DIE Eng Bh ABU EST pm Raise Lower Monitor Screen The monitor may be raised lowered in either Portrait Landscape mode To raise or lower screen place hands on each side of the monitor and lift or lower ta the desired height Figure RL 1 Screen Rotation Before rotating the screen must be raised to the highest level to avoid knocking the screen the dask ar pinching your fingers To raise the screen place hands on each side of the monitor and litt up ta the highest position Figure RL 1 To rotate screen place hands on each side of the monitor screen and turn clockwise from Landscape
207. tamination lt 0 piece 13 back right D Average diameter mm lt t ta 14 L length Lada t2 9 Circular flaws on mm jj polarizing plate piece 14 D Average diameter mm 04 EET gt gt Appearance Foams peelings on 0505 piece 22 iius during D Average diameter mm D gt 1 0 W back right OFF Polarizing plate undulation if it can be seen 11 There should be less than 1 piece of spot on monochromatic picture and the size should be within 1 2mm 12 Uneven spot should be less than 10mm when it is judged on 128 256 gradation ON W lt 0 01 dab PEDI au C 9 W width mm Viu s s s s 14 13 Removable dusts are excluded 14 This standards should be applied to the display part pixel area 2 19 2 10 Outgoing inspection 2 10 1 OSM default setting Confirm that the OSM setting values are as shown below before outgoing lt OSM default setting gt BRIGHTNESS MAX 220 CONTRAST CENTER 128 SHARPNESS CENTER 64 AccuColor NATIVE VIDEO DETECT FIRST DETECT DVI SELECTION DIGITAL LANGUAGE ENGLISH OSM H POSITION CENTER 50 OSM V POSITION CENTER 50 OSM TURN OFF 45SEC OSM LOCK OUT 3 OFF RESOLUTION NOTIFIER OFF MODEL at FACTORY MODE LCD1550X 2 10 2 Checking the labels etc Rating nameplate and Serial No must be attached at the designated positions 2 10 3
208. tandard Timing 5 NOT USED Standard Timing 6 NOT USED Standard Timing 7 NOT USED Standard Timing 8 NOT USED Detailed Timing block 1 Preferred Timing Mode Pixel Clock 65 00 MHz Horizontal Active 1024 pixels Horizontal Blanking 320 pixels Vertical Active 768 lines Vertical Blanking 38 lines Horizontal Frequency 48 36 kHz Vertical Frequency 60 0 Hz Horizontal Sync Offset 24 pixels Horizontal Sync Width 136 pixels Vertical Sync Offset 3 lines Vertical Sync Width 6 lines Horizontal Border 0 pixels Vertical Border 0 lines Horizontal Image Size 304 mm Vertical Image Size 228 mm Interlaced NO Image Normal Display Sync Digital Separate Bit 1 OFF Bit 2 OFF Monitor Range Limits block 2 Minimum Vertical Rate 50 Hz Maximum Vertical Rate 75 Hz Minimum Horizontal Rate 30 kHz Maximum Horizontal Rate 60 kHz Maximum Pixel Clock 80 MHz GTF Data 00 0a 20 20 20 20 20 20 2 8 ANALOG EDID DATA DUMP HEX 00 FF FF FF FF FF FF 00 38 A3 C8 65 SN SN SN SN WW YY 01 03 OE 1E 17 78 EE 4 57 4A 99 26 19 4F 57 BF EE 00 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 64 19 00 40 41 00 26 30 18 88 36 00 30 E4 10 00 00 18 00 00 00 FD 00 32 4B 1E 3C 08 00 0A 20 20 20 20 20 20 00 00 00 FC 00 4E 45 43 20 4C 43 44 31 35 35 30 58 0A 00 00 00 FF 00 52 52 52 52 52 52 52 2 2 52 52 52 52 00 CS SN Serial number WW Week of Manufacture YY Year of Manufacture 52 ASCII Serial Numbe
209. tion including the driver circuit is 64 8mW 18mW x 2Ch 28 8mW 1 36 1 6 3 Power rising falling edge sequence control function List of control signals u COM Pin No Signal name Function Remarks 53 O P_SAVE PRC mode of power borad Lo resonance mode Hi switching PWB POWER 59 PRO_DLY Inverter protection circuit Invalid Lo Valid Hi PWB POWER 47 51 I O MS RSTN ASIC control for DUTYCINV PWM for inverter royer oscillation ASIC 57 O P_INVT Inverter lighting control Off Lo On Hi PWB POWER 58 PANEL Panel 5V power OFF Lo ON Hi DTC114EUA 56 O P_SUSP1 A2_5V power OFF Lo ON Hi SI3025LSA 55 O P_SUSP2 D2_5V power OFF Lo ON Hi SI3025LSA 54 SUSP3 P2_5V power OFF Lo ON Hi NJM2870F25 60 P_ON A5V power OFF Lo ON Hi PQ1U501M2ZP 52 O P_TMDS TM3_3V power OFF Lo ON Hi SI3033LSA Functions Inverter control The microcomputer pin 57 P_INVT is used to control the inverter lighting and the microcom puter pin 59 PRO_DLY is used to control the validity of the inverter s protection circuit The ASIC PWM output DUTYCINV is used to control the royer oscillation of inverter The micro computer can control panel dimming by controlling the ASIC PWM output frequency The inverter control signal timing specifications at the power s rising edge are shown below P_INVT 100msec Typ 1300msec Typ DUTYCINV 6
210. tisfy the following specifications Check if the picture position is within the following specification with white frame pattern BEZEL Li Omm Displav area L2 Omm L3 Omm 14 Omm Check if the picture inclination is within the following specification with white frame pattern H4 ha hi h2 Hi hi Omm H2 h2 Omm Displav area H3 h3 Omm H4 h4 H2 H1 H3 h4 9 Check the movement of stand without SIGNAL CABLE DVI D DVI A and AC POWER CORD lt Inclination gt Display top unit should move properly without abnormal sound such as clattering or squeaking when it is moved as Picture A below Display top unit should not move when button on the front is pressed lightly with the index finger lt Pivot gt Display top unit should move properly without abnormal sound such as clattering or squeaking when it is moved as Picture B below Confirm that display top unit can be compensated by pivot adjustment lt Up Down gt Display top unit should move properly without abnormal sound such as clattering or squeaking when it is moved as Picture C below lt Swivel gt Display top unit should move properly without abnormal sound such as clattering or squeaking when it is moved as Picture D below Picture A Picture B Picture C za Picture D 2 5 2 5 3 PWB adjustment 2 5 3 1 Initial writing in EEPROM data To initialize the preset t
211. tmosphere 0 35 degree C 60 RH or below in case of a long term storage 6 Do not reassemble and or readjust the LCD monitor 7 Do not display fixed pattern for an extended period of time may cause an after image effect but it will disappear 8 Handle connector and cable with care 9 Light vertical stripes may be appeared depending on different display patterns This is not trouble or inferior 10 Light horizontal stripes may be appeared depending on different display patterns This is not trouble or inferior 11 Lamp start up time also gets longer at lower temperature 12 Saliva and water drop on LCD display surface should be immediately wiped off since they degrade the polarizer 13 Optical performance of the LCD changes by the temperature Response time gets longer at lower temperature 14 Please do not expose the LCD against the intensive light which is likely to degrade the polarizer amp color filter 15 If scratching by on the customer side we don t bear the responsibility 16 The lamp of backlight has a little mercury Please handle it appropriately in case of disposal 22 Document No VSPF A028 Appendix Preset Signal Timings H EZ H active Horizontal lt lt gt H front H back H pulse H total 52 1 55 52 V active Vertical V front V back V pulse V total 23 Document No VSPF A028 Appendix II EDID Code ANALOG E
212. tor 2 2 Measurement instruments used 1 Analog signal generator Astro Design VG 813 or equivalent 2 Digital signal generator Astro Design VG 828D or equivalent 3 DVI D PC DELL PC Carrying GeForce2 Ultra 3D 64MB DELL PC DIMENSION 4200 Carrying GeForce3 64MB DDR or IBM PC NetVista 4 DC voltmeter Digital voltmeter 5 Luminance meter MINOLTA Color analyzer CA 110 or equivalent 6 Oscilloscope Scope with band of 300MHz 7 Voltage converter AC264V range adjustable 8 Auto adjustment inspection machine Which is provided from Nagasaki 9 Isolation resistance tester YOKOGAWA TYPE3213 or equivalent 0 1 10 Isolation withstanding voltage meter KIKUSUI MODEL TOS8650 or equivalent 11 Grounding conductivity measuring instrument CLARE U K product or equivalent 2 3 Standard setting state Unless designated in particular the test is carried out with the following state State for Adjustment Power voltage AC120V 60Hz for North America AC240V 50Hz for Europe Input frequency Timing No 14 60 2 75 2 XGA75 2 1 2 4 Names of each LCD monitor part and adjustment methods 2 4 1 Configuration of front control panel 2 EXIT CONTROL ADJUST NEXT NEU RESET Cd Xr XJ POWER ON INDICATORD LE POWEFSSW Note When the item listed below is selected and RESET button is pressed then the data value is to be set as follows COLOR CONTROL All of R Y G C B 5 should
213. tor by power SW turns to orange 4 Confirm that the picture returns within four seconds when H svnc V svnc and VIDEO signals are input 2 8 1 10 Isolation voltage Confirm that the abnormality is never seen when AC1500V is applied for two seconds across AC earth GND pin to chassis GND Cut off current must be 10mA 2 8 1 11 Ground resistance Confirm that the resistance must be less than 100m ohms or less when 25A is applied across AC earth GND pin to chassis GND 2 8 1 12 Shock test 1 Input confirmation timing with signal generator and set the pattern to 2 pattern 06 2 Confirm that there is no abnormality in the image when shock is applied to the monitor Do not apply shock on the front of the liquid crystal panel 2 8 1 13 Confirming color selecting AccuColor function 1 Input timing No 14 60kHz 75Hz XGA75 with signal generator and input OPTION2 pattern gray scale or full white for picture pattern 2 Confirm that color temperature varies by switching Color No 1 2 3 SRGB 5 and N NATIVE 2 13 2 8 2 Picture performance 2 8 2 1 Picture performance inspection Check the picture performance with the following procedure Confirm that preset symbol P is correctly displayed on the upper right of the OSM picture in correspondence to the preset timing designated in the factory mode Inspection items Display pattern Measurement Criteria Timing No Input method connector 1 d
214. ts below ASIC IC400 EEPROM for adjustment IC100 MPU IC102 P2 5V line mav have anv problem Please check the parts below MAIN Power P2 5V generator IC IC606 ASIC ASIC IC400 check the parts below MC EEPROM for Adjustment IC100 MC MPU IC102 2 3 POWER SAVE Operates POWER ON INDICATOR Orange is blinking Is sync signal o SCDT input into each pin of MPU IC1022 Is DC5V A5V output from 6 of IC601 M M YES YES Pin no of MPU IC102 to which sync SCDT signal is to be input Line Circuit ASV Line Circuit Schematic Diagram DDC Circuit Input Interface Input Interface Circuit Circuit INPUT INPUT INPUT Sync Sync Input connector MAIN SYNC Is DC3 3V TM3 3V output from 8 of IC605 parts below TM3 3V Line Circuit Voltage TM3 3V Line Circuit Schematic Diagram Digital Signal Input Interface Receiver Circuit Circuit MAIN TMDS MAIN INPUT EEPROM DDC DSUB S G DVI A IC S G D SUB IC Sync INPUT IC INPUT DVI A IC INPUT D SUB IC MAIN Power generator C601 DDC circuit IC C106 DDC circuit IC C112 c c C EEPROM DDC DVI C104 c c M DDC DVI M EEPROM DDC DVI C105 C107 C203 C202 C201 C301 C304 TM3 3V line may have any problem Please check the MAIN Power generator IC IC605 TMDS Digital signal recei
215. turn wire is converted into voltage at R706 and is input into IC701 as the DC voltage rectified by D708 and C714 IC701 compares this voltage with the threshold upper lower limit range set by the D706 reference voltage If the lamp current is an abnormal value and exceeds this threshold the IC701 comparator output is short cir cuited the IC701 output type is an open collector The IC701 comparator output remains open while the lamp current is normal and the protec tion circuit does not function 1 8 4 3 2 Overvoltage protection circuit F701 707 12V 6 0 IC703 15 gt FET switch 708 D707 An overvoltage in the power voltage is detected and the timer circuit and latch protection circuit are activated in the same manner as the lamp current detection protection circuit ex plained above 1 45 1 8 4 3 3 Protection circuit operation timer circuit malfunction prevention If detection of an error continues for a set time the protection circuit will function to prevent malfunctions Main substrate IC102 microcomputer 604 1718 PINVT 67 5 lt 9 J703 PRO_DLY 69 3 3V 10 R606 IC701 comparator 12V 21 02 re gt eee 277 dm l C719 R728 1 p C718 R727 22 The protection circuit operation is delayed by the time constants set in R720 R728 and C719 To avoid affecting the time constant FET Q711 is used to drive Q718 and the thyristor TH701 is turned ON latched to stop the s
216. unication line or by using the factory 1 OSM function The DDC2BI or DDC CI function is supported by the DVI I connector D SUB connector supports only DDC2B so the EDID data write protec tion for EEPROM at the D SUB connector side must be set and canceled via the DVI I connec tor Internally by setting the microcomputer s pin 37 WP port to Lo the EDID data write protection will be set This will be canceled when set to Hi WP is fixed to Lo when the moni tor power is OFF The default value for WP when the monitor power is ON is Lo The value is not saved even when changed so once the AC power is turned OFF the value will return to the default value Lo DVI I connector side EDID data R Read W Write ability DVI external power 5VDC Hi Asset management ON Monitor internal power Hi Monitor AC ON Microcomputer port WP Lo Protect ON DVI I connector side DIGITAL E2PROM ANALOG E2PROM Hi Asset management ON Hi Monitor ON Lo Protect ON Lo Lo Lo R disabled W disabled R disabled W disabled Hi L L R enabled when selected JR enabled when selected 9 0 W disabled W disabled Hi Lo R enabled when selected R enabled when selected W disabled W disabled Hi Hi R enabled when selected R enabled when selected W enabled W enabled D SUB connector side EDID data R Read W Write ability D SUB external
217. upply of power to the oscillation circuit 1 8 4 3 4 Fuse A fuse is provided in the input section of each royer circuit F701 Oscillation circuit 1 IC703 FET switch Oscillation circuit 2 1 46 701 SM04 1 9 x gt ga Be 1 DUTYCINV 5 PRO_DLY 1 P_INVT SB PH S K ji direct connection n B 3 12V 9 1 PWB INVERTE I I I i ER 99 4 33 88 I J702 9e SM04 Appendix Table 1 LCD1550X connection diagram J600 pos PWB POWER ES 5 E kdh putycinv 1 2 GND 2 PRO_DLY 4901 J601 Cus SCN 8P B8B PH SM3 TBT G A 12v D 12V 69 12v 12V 12V KO 12 GND KO GND 2 GND pn R ep PWB MAIN a B7B PH K S P_INVT EAN GND 5 DUTYCINV B DUTVCINV 047 G oie E SAVE a 0 GND Q4 E 042 di 041 2 lt 58 RES A SM10B SRSS TB Q27 4 co ACZ 9 as VH 8 lt Q RESET 924 8 KO TxD GND fid 5 2 5 RxD 5 4 KO 922 B 000 5 b 91 8 Q20 8 GND 5 es 5 X 005 rome me 2800 ma Gl PWB SW 52807 1210 52852 1290 GND 1 GND Lal ano Q LED P U gt LED a2 8 LEFT LEF
218. ver DG 7 0 8 GAKBIt SCL 4 gt EEP SDA DVIRX1 1 9143 DBI7 0 2 2 d o HSYNC DVI RX1 LEE DVI DE DVI RXO _ SCDT DVI RXC 4 ______ gt PD 1 DVI RXC lq PDO P_TMDS DVI DDC_SCL 2 DDC_SCL I DVI DDC_SDA DDC_SDA H gt A2 Di I 2 lt EEPROM 4 Switching 4 ics POWER circuit 4 U D I board 2kBit 1 9 I EEPROM 4 9 gt A2 Ana d P_INVT B I PRO DLY D Sub DDC_SCL le 2 4 1 P_SAVE D Sub DDC_SDA i DUTYCINV 5 5V 44 5V 4 4 Power 40 I 1 12V 43 3 lt supply I I 2 5V 4444 odd 125 SL ONASA vi l vas et GND LL 01 INS INS anid 60 00 LOCr 01701096749 OLVSLZANJN ansa 1 euGis uonoeuuoo e qeo 4
219. ver IC IC500 MPU have anv problem Please check the part below 3 Abnormal Picture or Ineffective Adjustment JA2 5V line or control circuit may have any problem Please check the parts below MAIN Power 2 5 generator IC 604 A2 5V Line Circuit Voltage A2 5V Line Circuit Schematic Diagram A2 5V is generated in 1C604 and output from its 8 ASIC ASIC IC400 EEPROM for adjustment 12100 MPU 4 Measurment condition 1 Input timing XGA FH 60kHz FV 75Hz Timing No 14 refer to 2 12 Timing chart in Adjustment procedure 2 Display pattern Full White raster 3 Condition Brightness MAX Contrast CENTER POWER PWB MAIN POWER PWB MAIN INPUT PWB MAIN SYNC PWB MAIN TMDS PWB MAIN MC PWB MAIN ASIC INVERTER PWB SW St Or dx N 1 1 G Yor OILYWAHOS y9 27 Z Uld 455 uoz 1 1 1 I Vo
220. y cause electric shack lira equipment failure Do not place any heavy objects on the power cord Damage to the cord may cause shock ar fire Do not place this product on a sloping or unstable cart stand ar table as the monitor may fall causing serious damage to the monitor Do not place any objects anta the monitor and do not use the monitor outdoors The inside of the flourescent tube located within the LCD monitor contains mercury Please follow the bylaws or rules of your municipality ta dispose of tha tube properly Immediately unplug your monitor from the wall outlet and refer servicing ta qualified service personnel under the following conditions When the power supply cord or plug is damaged ff liquid has been spilled or objects have fallen into the monitor If the has been exposed to rain or water Ff the monitor has been dropped ar the cabinet damaged the monitor does nat operate normally by following operating instructions Do not bend power cord Da not use monitor in high temperatured humid dusty or oily areas Donot cover vent on monitor monitor is broken do not come in contact with the liquid crystal glass is broken Handle with care English 15 pi Enjih 18 EST a CAUTION Allow adequate ventilation around the monitor so that heat can properly dissipate Do not block ventilated openings or place th

SERVICE MANUAL LCD DISPLAY LCD1550X

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