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AN120 - 1ppm Settling Time Measurement for a Monolithic 18

1. Figure H8 Pretty Good Substitute for Figure H6 s Tektronix 109 Constructed from Commercially Available Components Settles 10V Step to 1ppm in 950ns an120f AN120 33 Application Note 120 APPENDIX I Auxiliary Circuits oeveral auxiliary circuits have been found useful in the DAC settling time work described in the text Figure I1 is a simple wideband X10 preamplifier for oscilloscopes lacking the required sensitivity for 1ppm 10pV settling time resolution This preamplifier should be placed directly no cable atthe oscilloscope input and connected via 50 terminated BNC cable to the settling time fixture output IN FROM 50 SOURCE 1 METAL FILM RESISTOR Figure 12 an auto zero circuit locks the sample interval zero value to the non sampled region baseline It elimi nates the need for periodic readjustment of the Sample Interval Zero trim when working at the highest levels of resolution over a protracted time Synchronously switched A1 compares sample interval and non sampled region zero values and applies an appropriate offset closing a correction loop around the LT1228 M1 s extended pulse precludes settling activity from influencing the sample interval zero value The Auto Zero Bias trim corrects Q1 OPTIONAL 14k GAIN TRIM TYPICALLY 150k AN120 FI01 Figure 11 Simple X10 Pre Amplifier for Oscilloscopes Lacking Required Sensitivity for 1ppm 10pV Settling Time Re
2. TECHNOLOGY D Application Note 120 March 2010 lppm Settling Time Measurement for a Monolithic 18 Bit DAC When Does the Last Angel Stop Dancing on a Speeding Pinhead Jim Williams Introduction Performance requirements for instrumentation function generation inertial navigation systems trimming calibra tors ATE medicalapparatus and other precision applications are beginning to eclipse capabilities of 16 bit data convert ers More specifically 16 bit digital to analog converters DACs have been unable to provide required resolution in an increasing number of ultra precision applications New components see Components for 18 bit Digital to Analog Conversion page 2 have made 18 bit DACs a practical design alternative These ICs provide 18 bit performance at reasonable cost compared to previous modular and hybrid technologies The monolithic DACs DC and AC specifications approach or equal previous converters at significantly lower cost DAC Settling Time DAC DC specifications are relatively easy to verify Measure menttechniques are well understood albeit often tedious AC specifications require more sophisticated approaches to produce reliable information In particular the settling time of a DAC and its output amplifier is extraordinarily difficultto determine to 18 bit 4ppm resolution DAC set tling time is the elapsed time from input code application until the output arrives at and remains within a s
3. The most obvious way to handle radiation induced errors is shielding Various following figures show shielding Determining where shields are required should come after considering whatlayout will minimize their necessity Often grounding requirements conflict with minimizing radiation effects precluding maintaining distance between sensitive points Shielding is usually an effective compromise in such situations A similar approach to ground path integrity should be pursued with radiation management Consider what points are likely to radiate and try to lay them out at a distance from sensitive nodes When in doubt about odd effects experiment with shield placement and note results iterating towards favorable performance Above all never rely on filtering or measurement bandwidth limiting to get rid of undesired signals whose origin is not fully understood This is not only intellectually dishonest but may produce wholly invalid measurement results even if they look pretty on the oscilloscope Note 1 War is perhaps a more accurate descriptive Note 2 do not wax pedantic here My abuse of this postulate runs deep Note 3 Strictly considered this technique introduces mis termination originated transmission line reflections but no appreciable error results at the bandwidth of interest Note 4 Distance is the physicist s approach to reducing radiation induced effects Note 5 Shielding is the engineers approach to redu
4. FEEDBACK VERTICAL CHANNEL AMPLIFIER DC OFFSET GENERATOR TRIGGER CIRCUITRY TO HORIZONTAL CIRCUITS AN120 FB1 Figure B1 Simplified Vertical Channel Diagrams for Different Type Oscilloscopes Only the Classical Sampling Scope C Has Inherent Overdrive Immunity Offset Generator Allows Viewing Small Signals Riding on Large Excursions an120f AL Le AN120 15 Application Note 120 The waveform to be expanded is placed on the screen at a vertical sensitivity that eliminates all off screen activity Figure B2 shows the display The lower right hand portion is to be expanded Increasing the vertical sensitivity by a factor of two Figure B3 drives the waveform off screen but the remaining display appears reasonable Amplitude has doubled and waveshape is consistent with the original display Looking carefully it is possible to see small am plitude information presented as a dip in the waveform at about the third vertical division Some small disturbances are also visible This observed expansion of the original waveform is believable In Figure B4 gain has been further increased and all the features of Figure B3 are amplified accordingly The basic waveshape appears clearer and the dip and small disturbances are also easier to see No new waveform characteristics are observed Figure B5 brings some unpleasant surprises This increase in gain causes definite distortion The initial negative going peak although larger h
5. using double expo sure technique compares signal channel rise times for CaBERRATION OpF leftmosttrace and approximately 35pF rightmost trace with the control channel tied high The larger Caperration Value while minimizing feedthrough amplitude see Figure 9 increases rise time by 7x versus CABERRATION OPF The transconductance switches small DC and AC errors nicely accommodate the applications requirements The low feedthrough already sufficient becomes irrelevant because its small time and amplitude error will be buried inthe DAC ring time interval The transconductance ampli fier based switch points the way towards practical 1ppm DAC settling time measurement DAC Settling Time Measurement Method Figure 12 a more complete representation of Figure 3 utilizes the above described sampling switch Figure 3 s blocks appear in greater detail and some new refinements show up The DAC amplifier summing area is unchanged Figure 3 s delayed pulse generator has been split into two blocks a delay and a pulse generator both independently variable The input step to the oscilloscope runs through a section that compensates settling time measurement path propagation delay This path includes settle node amplifier and sample gate delays The transconductance sampling switch sample gate driven from a non satu rating residue amplifier feeds the oscilloscope Placing the sampling switch after the residue amplifier gain
6. waveform is sampled in time as well as amplitude The oscilloscope is never subjected to overdrive no off screen activity ever occurs Note 4 For a discussion of oscilloscope overdrive considerations see Appendix B Evaluating Oscilloscope Overdrive Performance Note 5 Classical sampling oscilloscopes should not be confused with modern era digital sampling scopes that have overdrive restrictions see Appendix B Evaluating Oscilloscope Overload Performance for comparisons of various type oscilloscopes with respect to overdrive For detailed discussion of classical sampling oscilloscope operation see references 17 through 21 and 23 through 25 Reference 18 is noteworthy itis the most clearly written concise explanation of classical sampling instruments the author is aware of A 12 page jewel an120f AN120 3 Application Note 120 OV TO 10V DIGITAL TRANSITION i EET e e w w GENERATOR INPUT STEP TO OSCILLOSCOPE SWITCH OUTPUT TO OSCILLOSCOPE RESIDUE AMPLIFIER AN120 F03 Figure 3 Conceptual Arrangement Eliminates Oscilloscope Overdrive Delayed Pulse Generator Controls Switch Preventing Oscilloscope from Monitoring Settle Node Until Settling is Nearly Complete SIGNAL PATH SIGNAL a 4 gt d gt 4 ALS MOSFET no CONTROL AN120 F04 DIODE BRIDGE Figure 4 Conventional Choices for the Sampling Switch Include JFET MOSFET and Diode Bridge FET Parasiti
7. 5kQ GR 874 50 TERM DELAYED PULSE GENERATOR HP8082A text to measure type 109 fall time purity to microvolts The 109 output trace B moves the final 220uV settling inside 10uV approximately 265ns after the relay contacts open trace A Actual 109 settling time may be faster as the measurement is likely sampling circuit limited Figure H6 is a simplified version of the test circuit which Note 2 A Root Sum Square risetime calculation indicates 720 picoseconds See reference 30 Note 3 Some may find remarkable to be excessively enthusiastic verbiage but these things thrill certain types Note 4 Sampling circuit delay 70 nanoseconds 109 1ppm settling time is probably inside 195 nanoseconds Alt B 50uV D1V J BN A ai AVERAGED REN ms EX Tees ie mm ummg 100ns DIV AN120 FHOS Figure H5 Sampling Switch Techniques Permit Measuring Type 109 Falling Edge Residue to Microvolts in 20MHz Bandpass Trace A is 109 Falling Edge Trace B the Last 220V of Movement Before Settling to 1ppm in Indicated 265ns CLAMPED AMPLIFIER SAMPLER OUTPUT SAMPLE COMMAND AN120 FH06 Figure H6 Simplified Test Circuit Attention to Hg Wetted Reed Relay and Transmission Line Allow 1ppm Residue 265ns After Contacts Open an120f AN120 31 Application Note 120 producedthese results Thetype 109 drives 20 centimeters of 50 GR 874 airline into a high quality GR 874 500 termin
8. 70 C Some amplifiers shown contribute less than 1LSB error over 0 C to 70 C with 18 bit DAC driven settling times of 1 8us available The references offer drifts as low as 1LSB over 0 C to 70 C with initial trimmed accuracy to 0 05 Short Form Descriptions of Components Suitable for 18 Bit Digital to Analog Conversion COMPONENT TYPE 1092757 DAC LT 1001 Amplifier lt 1LSB LT1012 Amplifier lt 1LSB LT1468 L11468 2 Amplifier lt 8LSB LTC1150 Amplifier lt 1LSB LTZ1000A Reference lt 1LSB LM199A Reference 6 95V 4LSB T1021 Reference 10V LT1027 Reference 5V T1236 Reference 10V 16LSB 40LSB compensation Additionally the architecture of very fast amplifiers usually dictates trade offs which degrade DC error terms Measuring anything at any speed to 20 bit resolution 1ppm is hard Dynamic measurementto 20 bit resolution is particularly challenging Reliable 1ppm DAC settling time measurement constitutes a high order difficulty problem requiring exceptional care in approach and experimental technique This publication s remaining sections describe a method enabling an oscilloscope to accurately display DAC settling time information for a 10V step with 1ppm resolution 10uV within 265ns The approach employed permits observation of small amplitude information at the excursion limits of large waveforms without overdriving the oscilloscope ERROR CONTRIBUTION OVER 0 C TO 70 C lt 4 6LSB Gain Drift Ful
9. from the settled region up to the last 100uV or so of amplifier movement so ring time cessation is observable Thesampling based approach provides this capability and itisavery powerful measurementtool Additionally slower amplifiers may require extended delay and or sampling window times This may necessitate larger capacitor values in the 4HC123 one shot timing networks Figure 21 shows DAC settling in an unfiltered bandpass The DAC settles trace B to 16 bits 1 7us after trace A s time corrected input step Sample gate feedthrough is undetectable indicating higher resolution is possible with out overdriving the oscilloscope Noise is the fundamental measurement limit Figure 22 attenuates noise by reducing measurement bandwidth to 250kHz Trace assignments are as in the previous photo 18 bit settling 4ppm requires approximately 5us The reduced bandwidth permits higher resolution although the indicated settling time is likely pessimistic due to the filters lag Figure 23 decreasing bandwidth to 50kHz permits 19 bit 2ppm resolution with indicated settling in about 9us Again the same filtering which permits high resolution almost certainly lengthens observed settling time Note 10 Driving the sample command path 74HC123 B2 input with a phase advanced version of the pulse generator input largely eliminates sample command path delay induced error considerably improving minimum measurable settling time This benefit is not ger
10. further minimizes sample command feedthrough impact Detailed Settling Time Circuitry Figure 13is a detailed schematic of the 20 bit DAC settling time measurement circuitry The input pulse switches all DAC bits simultaneously and is also routed to the oscil loscope via the delay compensation network The delay network composed of CMOS inverters and an adjustable RC network compensates the oscilloscope s input step signal for the 44ns delay through the circuit measurement path The DAC amplifier output is compared against the Note 7 See Appendix C Measuring and Compensating Signal Path Delay and Circuit Trimming Procedures an120f AN120 7 Application Note 120 SETTLE NODE RESIDUE AMPLIFIER SAMPLE MEC GATE DELAY COMPENSATION E OV TO 10V INPUT DAC RESIDUE i AMPLIFIER GATE BET OUTPUT TO OSCILLOSCOPE R c T SAMPLE WINDOW v GENERATOR VARIABLE DELAY Figure 12 Block Diagram of Sampling Based DAC Settling Time Measurement Scheme Placing Transconductance Controlled Sample Gate After Residue Amplifier Minimizes Sample Command Feedthrough Impact Eliminating Oscilloscope Overdrive Input Step Time Reference is Compensated for Settle Node Residue Amplifier and Sample Gate Delays VARIABLE WIDTH PULSE GENERATOR TRANSCONDUCTANCE Lo CONTROL CURRENT SAMPLE COMMAND PULSE J SOURCE AN120 F03 4 99k TIME CORRECTED INPUT STEP TO 500 OSCILLOSCOPE 5V SETTLE NODE RESIDU
11. rising control edge without regard to falling edge characteristics The gm amplifiers transconductance collapse on the falling edge ensures low feedthrough for that condition preventing oscilloscope overdrive Figure details the transconductance amplifier based switch This design switches signals over a x30mV range with peak control channel feedthrough of millivolts and settling times inside 40ns The circuit approximates switch action by varying A1A s transconductance the maximum gain is unity At low transconductance A1A s gain is nearly zero and essentially no signal is passed At maximum transconductance signal A 0 001 1 SIGNAL OUTPUT SIGNAL INPUT L IDLE CURRENT I SWITCHED CURRENT 1000 T CURRENT ON CURRENT OFF _ JL CURRENT SOURCE CONTROL CHANNEL m AN120 F06 Figure 6 Transconductance Amplifier Based Switch Has Minimal Control Channel Feedthrough Wideband Control and Signal Paths Faithfully Track 1000 1 Transconductance Change Resulting in Exceptionally Pure Switch Dynamics JN CONTROL PULSE EDGES IN BAND SS CONTROL PULSE EDGES IN BAND OUT L L J one PULSE EDGES IN BAND m AN120 F05 CONTROL PULSE LEADING EDGE IN BAND V Figure 5 Conceptual Low Feedthrough Electronic Switch Equivalents A and B are Difficult to Implement C and D are Practical C Must be Optimized for Low Feedthrough on Rising and Falling Control Pulse Edges
12. settling time in what should be by additional circuitry This circuitry must provide a start now familiar fashion Figure F3 is a complete processor pulse to the settling time measurementcircuitafterserially software code listing OPTIONAL 4kHz PULSE GENERATOR 20pF 70ns 30us DELAY ADJ PULSE GENERATOR INPUT SEE TEXT FIGURE 13 LTC1799 START 1 4 74HC86 LTC6905 80 H3 c9 f CS LO 5V OUT SCK BAT85 aie 5 sp DAC EXT TRIG 1V OUT TO 50Q TERM LINE LL SANYO OSCON T Do 1 6 74HC04 CY Y Y V COILTRONICS UP3B 101 GND BYP AN120 FFO1 MCLR Figure F1 The Serial Interface Processor Responds to Input Pulse Directs DAC to Perform 10V Steps an120f AL ule AN 1 20 21 Application Note 120 A 10V DIV B 10V DIV C 10V DIV D 10V DIV E 10V DIV AN120 FF02 20ys DIV UNCALIBRATED Figure F2 Serial Interface Operation Includes Input Start Pulse Trace A CS LD Trace B SCK C SDI D and Resultant DAC Output E Digital Data Lines are Static During Measurement Interval Precluding Crosstalk Induced Corruption Serial DAC step program Makes controlling the serial DAC as easy as the old way of tying all the digital lines of a parallel DAC to a pulse generator the serial DAC CS LD signal is the output of an XOR gate edge detector that gives a lus pulse on either the rising edge or falling edge of CONTROL signal Program enters main loop when CO
13. the control input goes high the output reproduces the input with switch feedthrough settling in about 20ns Note thatturn off feedthrough is undetectable due to the 1000x transconductance reduction and attendant 25x bandwidth drop Figure 9 speeds the sweep up to 10ns division to examine zero volt settling detail The output trace B settles inside 1mV 40ns after the switch control trace A goes high Peak feedthrough excursion damped by C Aper RATION IS only 5mV Figure 10 was taken under identical conditions except that Caprrration OpF Feedthrough AN120 6 Application Note 120 ELIA Wee Ed a Sgn Na i IS e c es at oe B 0 005V DIV AN120 F09 10ns DIV Figure 9 High Speed Delay and Feedthrough for 0V Signal Input Output Trace B Peaks Only 0 005V Before Settling Inside 0 001V 40ns After Switch Control Command Trace A CABERRATION 39pF for This Test AN120 F10 10ns DIV Figure 10 Identical Conditions as Figure 9 Except CABERRATION OpF Feedthrough Related Peaking Increases to 0 02V 0 001V Settling Time Remains at 40ns 0 005V DIV E AN120 F11 10ns DIV Figure 11 Signal Channel Rise Time for Cagerrarion OPF Leftmost Trace and 35pF Rightmost Trace Record 3 5ns and 25ns Respectively Switch Control Input High for this Measurement Photograph Utilizes Double Exposure Technique increases to approximately 20mV although settling time to 1mV remains at 40ns Figure 11
14. Component Variations Penalty is Increased Settling Time tsgrric 2 1ps to 0 0004 18 Bits A 5V DIV Sni in B 100uV DIV AVERAGED 1 AN120FD04 500ns DIV Figure D4 Underdamped Response Results from Undersized Capacitor Component Tolerance Budgeting Will Prevent This Behavior tsetrie 2 8ps to 0 0004 18 Bits an120f AL JUS AN120 19 Application Note 120 When feedback capacitors are individually trimmed for optimal response DAC amplifier and compensation ca pacitor tolerances are irrelevant If individual trimming is notused thesetolerances must be consideredto determine the feedback capacitors production value Ring time is affected by DAC capacitance and resistance as well as the feedback capacitors value The relationship is nonlinear although some guidelines are possible The DAC imped ance terms can vary by 50 and the feedback capacitor is typically a 5 component Additionally amplifier slew rate has a significant tolerance which is stated on the data sheet To obtain a production feedback capacitor value determine the optimum value by individual trimming with the production board layout board layout parasitic capacitance counts too Then factor in the worst case percentage values for DAC impedance terms slew rate and feedback capacitor tolerance Combine this information with the trimmed capacitors measured value to obtain the production value This budgeting is pe
15. D s Falling Edge Feedthrough is Inherently Minimized by Attendant Bandwidth Reduction an120f AN120 5 Application Note 120 SWITCH T yrs CONTROL INPUT 15V IBI ae ee OmV TO 30mV 5y 2009 1 6k TLO m O a a OUTPUT OV m 60m 2N3906 H doe OmV TO 30mV 500 SAMPLE 357k 15V TRANSITION 50pF PURITY 7 5K I L ZERO 10M SOpF si MEN DRIVING ISET ABERRATIONS 1 2 L11228 S 500 BACK 500 ik TERMINATED GAIN CABLE 1 METAL FILM 1k 3300ppm C 5 QUALITY THERMISTOR QTG12 103G E AN120 F07 Figure 7 Transconductance Amplifier Based 100MHz Low Level Switch Has Minimal Control Channel Feedthrough A1A s Unity Gain Output is Cleanly Switched by Logic Controlled Q1 s Transconductance Bias A1B Provides Buffering and Signal Path Gain passes at unity gain The amplifier and its transconductance control channel are very wideband permitting them to faithfully track rapid variations in transconductance set ting This characteristic means the amplifier is never out of control affording clean response and rapid settling to the switched input s value A1A one section of an LT1228 is the wideband trans conductance amplifier Its voltage gain is determined by its output resistor load and the current magnitude into its Isgr terminal A1B the second LI1228 section unloads A1A s output As shown it provides a gain of 2 but when driving a back terminated 50Q cable its effective gain is u
16. E DAC OUTPUT If 25uV DIV ON 10V STEP AVERAGED i AN120 BC 2us DIV A part per million is a part per million It s magic It s the brass ring It s the holy grail of every measurement artist It will mesmerize you it will goad you it will drive you crazy and if you re lucky it will reward you A part per million is a part per million Jerrold R Zacharias M I T physicist mentoring a young very naive investigator 1971 an120f LT 0310 PRINTED IN USA Linear Technology Corporation AN120 36 1630 McCarthy Bivd Unda sepe AL Ur 408 432 1900 FAX 408 434 0507 www linear com 6 LINEAR TECHNOLOGY CORPORATION 2010
17. E AMPLIFIER SAMPLE GATE 222880080864 DELAY COMPENSATION OV TO 10V COME TYPICAL CEDE TRANSITION DUT SELECT SEE TEXT SETTE PULSE AUT GENERATOR LT1468 INPUT 10k L4 4 4 44 4 44 11021 10 OUT IN B GND 500 oe tp 44ns IN LINE TERMINATION 7 m AUF sos D RE SEE TEXT AND NOTES T TW E 15V RESIDUE AMPLIFIER A 40 nm TRANSCONDUCTANCE 750Q A2 AMPLIFIER 1802 A3 3 01k A P FA 301k A T A4 500 SETTLE OUTPUT 500 TO 50Q OSCILLOSCOPE 50pF 5602 1mV DIV 50uV DIV 500 AT DAC OUTPUT a GAIN PM 5V ne 10k d BASELINE ZERO Ey ABERRATIONS 1k 5V 1000 1uF iy i SAMPLE INTERVAL I 74HC04 GROUND UNUSED INPUTS WINDOW ZERO 10k 9 7 5k SAMPLE WIDTH 1 6k 2000 4 99k WINDOW SAMPLE OUTPUT pL 14148 100pF WINDOW di TO 500 GENERATOR 2N3906 50p pF 1N5712 5V is SAMPLE OSCILLOSCOPE L 0 024 TRANSITION 1 METAL FILM RESISTOR RCi Ci Q1Q2 CLR B2 AZ 3 57k PURITY QUALITY THERMISTOR QTG12 103G 74HC123 SAMPLE VISHAY S102 0 01 RESISTOR 10pmm MATCHING M Bi CLRI O102 C2 RC2 GND 20k COMMAND USE IN LINE COAXIAL 50Q TERMINATOR FOR SAMPLE 40M PULSE GENERATOR INPUT DO NOT MOUNT jg DELAY 50Q RESISTOR ON BOARD AC 5V CONSTRUCTION IS CRITICAL SEE TEXT DAC CONNECTIONS SIMPLIFIED FOR SCHEMATIC CLARITY SEE THE LTC2757 DATA SHEET AN120 F13 Figure 13 Detailed DAC Settling Time Measurement Circuit Closely Follows Preceding Figure Optimum Performance Requir
18. Large Round Capacitor Near Photo Center are Oriented to Restrict Radiative Coupling While Minimizing Summing Node Capacitance Variable Capacitor Lower Left Center Sets Amplifier Photo Center Compensation Non Saturating Amplifier Appears at Right Shield Bottom Restricts Sampler Digital Section s Radiation Vertically Mounted Board Extreme Upper Left is Optional Serial DAC Interface See Appendix F Coaxial Connectors Center Lower Facilitate High Purity Signal Extraction AN 1 20 26 AL Le Application Note 120 AN120 FG03 Figure G3 LT1228 Sampling Switch Photo Center Is Mounted Upside Down Permitting V Referred Die Backside To Shield Residual Radiative Coupling Reducing Sampling Switch Drive Feedthrough Switch Signal Channel Is Fed From Non Saturating Amplifier Photo Left Sample Command From Shielded Digital Section Lower Arrives Via Coaxial Cable Tunneling Through Shield Lower Center an120f AL ule AN1 20 2 Application Note 120 AN120 FG04 Figure G4 A Dedicated Serially Interfaced Settling Time Breadboard Serial Interface Digital Board is Obscured Beneath Visible Analog Board See Appendix H Figure H7 Note Insulating Nylon Screws Right and Left Lower Corners and Upper Edge Between BNC Connectors Used to Attach Digital and Analog Boards Digital Board Ground is Single Point Connected at Analog Board Ground Entry Point Middle Banana Jack Serial Signals Access Vertical DAC Board Via Coax Photo
19. Left Shields Isolate Sample Switch Digital Section Lower and Summing Node Left Center Non Saturating Amplifier and Sampling Switch are as in Figure G1 Optional Auto Zero Board See Appendix Mounts from BNC Fitting at Center Right Upper Left Corner Components are Input Pulse Time Correction AN 1 20 28 AL Le Application Note 120 AN120 FG05 Figure G5 Serially Interfaced Settling Time Breadboard Signal Path Detail DAC Board is at Left Precision Resistors Feed Summing Node and Non Saturating Amplifier Photo Upper Center Shield Protects Summing Node from Input Pulse Originated Radiation T1228 Sampling Switch Far Right is Mounted Upside Down Permitting V Referred Die Backside to Shield Radiative Coupling Reducing Switch Drive Feedthrough Switch Drive Level Shift Current Source Extreme Right Upper Receives Sample Command Via Coax Partially Visible at Lower Right Large Vertical Shield Confines Sample Command Digital Section Radiation Lower SMA Connector Center Enables Test and Calibration Signal Connection an120f AL ule AN1 20 29 Application Note 120 APPENDIX H HOW DO YOU KNOW IT WORKS Settling Time Circuit Performance Verification High Purity Pulse Generator Any prudent investigation requires performance verifica tion of the test method Strictly considered it may not be possible to furnish indisputable proof that the circuit in question is functioning at its design limits particular
20. NTROL is high When CONTROL goes low the code for 5V is sent When CONTROL goes high the code for 5V is sent Thus the timing of the load pulse accurately follows the input signal by about 20ns A delay of 60us is inserted after the load pulse so that you can look at settling details without having to worry about digital feedthrough x7 include lt 16F73 h gt include pcm73a h use delay clock 20000000 20 meg clock Hfuses HS NOWDT PUT MCLR Defines for DAC addresses define DACA 0 define DACB 2 define DACC 4 define DACD 6 define PM10 0x03 ddefine PM5 0x02 jf Control input define CONTROL PIN C7 void init void void main init set up hardware This just allows the program to sync up to a pulse generator that may not have a clean output on power up You need to see at least one rising and one falling edge before continuing while input CONTROL delay us 2 wait for rising edge while input CONTROL delay us 2 wait for falling edge delay ms 100 while input CONTROL delay us 2 wait for rising edge while input CONTROL delay us 2 wait for falling edge AN120 22 A Application Note 120 Okay now we re all synchronized Since program does not have direct access to the CS LD line you have to rely on the externally applied pulse while input CONTROL delay us 2 wait for rising edge while input CONTROL delay
21. SS Processor Code Directs DAC to Step 10V at Each Input Pulse Transition an120f AL Le AN120 23 Application Note 120 APPENDIX G BREADBOARDING LAYOUT AND CONNECTION TECHNIQUES The measurement results presented in this publication required painstaking care in breadboarding layout and connection techniques Wideband 10uV resolution measurement does not tolerate cavalier laboratory at titude The oscilloscope photographs presented devoid of ringing hops spikes and similar aberrations are the result of an exhaustive and frustrating breadboarding exercise The breadboard was rebuilt numerous times and required weeks of layout and shielding experimenta tion before obtaining a noise uncertainty floor worthy of 20 bit measurement In particular extreme measures were required to minimize sample command signal feedthrough Layout techniques include minimization and restriction of radiative paths ground plane current management and mounting the LT1228 switch upside down allowing its V referred substrate to approximate a monolithic shield for the IC s internal circuitry Ohm s Law It is worth considering Ohm s Law is a key to successful layout Considerthat 1 mA running through 0 1 generates 100yV almost 3LSB at 18 bits Now runthat milliampere at ons to 10ns rise times approximately 5MHz and the need for layout care becomes clear A paramount concern is disposal of circuit ground return current and disposit
22. TO A1 AN120 F19 Figure 19 Output Response Trace B To Sample Command Trace A Turn Off 1000 1 Transconductance Drop Ensures Clean Transition Independent of Trim State Settling Time Circuit Performance Figure 20 summarizes settling time circuit performance The graph indicates the minimum measurable settling time for a given resolution Speed limitations are imposed by Sample command path delays and sample gate switch ing residue profile Minimum measurable settling time below 160ns is available to 16 bit resolution Beyond this point the sample gate s switching residue profile dictates increased minimum measurable settling time to about 265ns at 20 bits Circuit noise limitations are imposed by the DAC amplifier summing resistors and residue ampli fier sampling switch with about equal weighting Because of this resolution beyond approximately 15ppm requires filtering or noise averaging techniques 4 SAMPLE COMMAND 18 PATHDELAYS SAMPLING GATE SETTLING TIME RESOLUTION IN PPM BITS o 1220 40 80 120 160 200 240 280 MINIMUM MEASUREABLE SETTLING TIME ns AN120 F20 Figure 20 Minimum Measureable Settling Time vs Resolution Limits are Imposed by Sample Command Path Delays and Sample Gate Settling Profile Resolution Beyond 15ppm Requires Filtering or Noise Averaging Using the Sampling Based Settling Time Circuit Itis good practice to walk the sampling window backwards in time
23. an be maintained in band that is its transition Note 6 LTC Application Note 74 Component and Measurement Advances Ensure 16 bit DAC Settling Time utilized such a sampling bridge and it is detailed in that text an120f AN120 4 Application Note 120 rate is within the circuits bandpass The circuits wide bandwidth means the switch command transition is under control at all times There are no out of band responses greatly reducing feedthrough Figure 5 lists some candi dates for low feedthrough electronic switch equivalents A and B while theoretically possible are cumbersome to implement C and D are practical C must be optimized for low feedthrough on rising and falling control pulse edges because ofthe multipliers unrestricted wideband response D s falling edge feedthrough is inherently minimized by the gy amplifiers transconductance collapse when the control pulse goes low This allows feedthrough to be optimized for the control pulse s rising edge without regard to falling edge effects This is asignificant advantage in constructing an electronic equivalent switch Transconductance Amplifier Based Switch Equivalent Figure 6 is aconceptual transconductance amplifier based switch The wideband control and signal paths faith fully track 1000 1 transconductance change resulting in exceptionally pure switch dynamics The switched cur rent source is carefully optimized for lowest feedthrough on the
24. as a different shape Its bottom appears 0 5V DIV Eana ete 100ns DIV Figure B2 n fap fhe feet eh 0 1V DIV 100ns DIV Figure B5 100ns DIV Figure B3 100ns DIV Figure B6 less broad than in Figure B4 Additionally the peak s posi tive recovery is shaped slightly differently A new rippling disturbance is visible in the center of the screen This kind of change indicates that the oscilloscope is having trouble A further test can confirm that this waveform is being influenced by overloading In Figure B6 gain remains the same but the vertical position knob has been used to reposition the display at the screen s bottom This shifts theoscilloscope s DC operating point which under normal circumstances should not affect the displayed waveform Instead a marked shift in waveform amplitude and outline occurs Repositioning the waveform to the screen s top produces a differently distorted waveform Figure B7 It is obvious that for this particular waveform accurate results cannot be obtained at this gain Note 4 Knobs derived from Middle English knobbe akin to Middle Low German knubbe cylindrically shaped finger rotatable panel controls for controlling instrument functions were utilized by the ancients 0 2V DIV 100ns DIV Figure B4 0 1V DIV AN120 FB2 B7 100ns DIV Figure B7 Figures B2 B7 The Overdrive Limit is Determined by Progressively Increasing Oscilloscope Gain an
25. ation at the clamped amplifier sampling switch The delayed pulse generator and oscilloscope are set up similarly to the main text description The Tektronix pickoff components noted allow signal extraction from the airline without degrading transmission line integrity It is interesting to note that airline is a non negotiable requirement The highest quality Teflon 50Q cable pro duced impure response albeit minor Figure H7 s photograph shows the high purity step genera tor connected to Figure G4 s settling time breadboard The type 109 photo left delivers its pulse viaa General Radio 20 centimeter airline The Tektronix CT 3 coaxial transformer right end of airline supplies the trigger pick off via the vertically mounted 5002 BNC connector A GR 874 50 load right side of CT 3 terminates the airline and sup plies the pulse to the breadboard Pulse amplitude is set by a DC voltage applied at the 109 via banana inputs The unused 109 contact is terminated with an endline GR 874 fitting All connections must be polished and mechani cally secured to ensure a high fidelity 50 2 environment Any component substitution or mechanical connection imperfection will degrade Figure H5 s results AN120 FH07 Figure H7 High Purity Step Generator Connected to Figure G4 s Settling Time Breadboard Tektronix Type 109 Mercury Wetted Relay Based Pulse Generator Photo Left Delivers Pulse Via General Radio 20 Centimeter Airline Tektronix CT 3 C
26. be damped with large compensation capacitors Such compensation works but results in protracted settling times The key to good settling times is to choose an amplifier with the right balance of slew rate and recovery characteristics and compensate it properly This is harder than it sounds because amplifier settling time cannot be predicted or extrapolated from any combination of data sheet specifica tions It must be measured in the intended configuration Inthe case of a DAC amplifier a number of terms combine to influence settling time They include amplifier slew rate and AC dynamics DAC output resistance and capacitance and the compensation capacitor These terms interact in a complex manner making predictions hazardous If the DAC s parasitics are eliminated and replaced with a pure resistive source amplifier settling time is still not readily predictable The DAC s outputimpedance terms just make a difficult problem more messy Theonly real handle available to deal with allthis is the feedback compensation capacitor Cr Cr s purpose is to roll off amplifier gain at the frequency that permits best dynamic response Normally the DAC s current output is unloaded directly into the amplifiers sum ming junction placing the DAC s parasitic capacitance to ground atthe amplifiers input The capacitance introduces feedback phase shiftat high frequencies forcing the ampli fier to hunt and ring about the final value before settling Diffe
27. c Capacitances Result in Large Gate Drive Originated Feedthrough to Signal Path Diode Bridge is Better Its Small Parasitic Capacitances Tend to Cancel Bridge Requires DC and AC Trims and Complex Drive Circuitry Developing a Sampling Switch Requirements for Figure 3 s sampling switch are stringent Itmustfaithfully pass signal path information without intro ducing alien components particularly those deriving from the switch command channel Figure 4 shows conventional choices for the sampling switch They include FETs and the diode bridge The FET s parasitic gate to channel ca pacitances result in large gate drive originated feedthrough into the signal path Foralmostall FETs this feedthrough is many times larger than the signal to be observed inducing overload and obviating the switches purpose The diode bridge is better its small parasitic capacitances tend to cancel and the symmetrical differential structure results in very low feedthrough Practically the bridge requires DC and AC trims and complex drive and support circuitry This approach incarnated with great care can reliably measure DAC settling time to 16 bit resolution Beyond 16 bits residual feedthrough becomes objectionable and another approach Is needed Electronic Switch Equivalents A low feedthrough high resolution switch can be con Structed with wideband active components The great advantage of this approach is that the switch control channel c
28. cing radiation induced effects Note 6 After it works you can figure out why AN120 24 Application Note 120 Connections coaxially mounting probe tip adapters Figures G1 to G5 restate the above sermon in visual form while annotating All signal connections to the breadboard must be coaxial opi the text s circuits Ground wires used with oscilloscope probes are forbid den A one inch grou nd lead used with a scope probe can Note 7 See reference 28 for additional nagging along these lines easily generate several LSBs of observed noise Use AN120 FGO1 Figure G1 Settling Time Breadboard Overview Pulse Generator Input Enters Top Left 50Q Coaxial Terminator Mounted On Extension Tube Not Visible See Appendix H Figure H7 Minimizes Pulse Generator Return Current Mixing Into Signal Ground Plane DAC amplifier and Support Circuitry are at Left Sampler Circuitry Occupies Board Right Sampler Digital Support Circuitry is Contained Within Large Shield Board Lower Nonsaturating Amplifier Occupies Board Center Partially Visible X10 Post Amplifier See Appendix I is BNC Fixtured Thin Board at Photo Right Auto Zero Circuit see Appendix I Mounted on Thin Strut Lower Right is Not Visible an120f AL ule AN120 25 Application Note 120 oe FS P a AN120 FG02 Figure G2 DAC Amplifier Detail DAC and Output Amplifier are at Photo Center Left Precision Summing Resistors Box Shaped Just Below
29. cts just open Scott Hamilton Manchester University UK has raised the possibility of quantum tunneling across the brief small contact gap a a scanning tunneling microscope operation Comments from the readership are welcome an120f AN120 30 Application Note 120 switched by the relay into a 50Q termination resulting in a 250ps risetime pulse Here charge lines are not employed rather the device is used as a simple switch Advantage is taken of the exquisite care at manufacture to make the relay transparent in a 50Q system Figure H4 s large scale transition reveals 800ps fall time in a 1GHz bandwidth Actual fall time is probably somewhat faster as the monitoring oscilloscope has a 350ps risetime The transition is singularly clean and devoid of discontinuities with the exception of the previously noted pre fall corner rounding Figure H5 s remarkable photograph uses sam pling switch techniques similar to those described in the viv ERR AN120 FH04 500ps DIV Figure H4 High Grade Mercury Wetted Reed Relay Tektronix Type 109 Falls in 800ps Viewed in 1GHz Real Time Bandwidth Strict Attention To Parasitic Minimization in Relay Structure and Transmission Path Produces High Fidelity Transition Without Alien Components GR 874 500 END LINE TEKTRONIX 20cm 509 AIRLINE GR 874 TYPE 109 TEKTRONIX CT 3 TRANSFORMER PICKOFF TEKTRONIX VP 1 PICKOFF N Z AT FREQUENCY 509 TEKTRONIX P 6057 Zo
30. d Watching for Waveform Aberrations AN120 16 Application Note 120 APPENDIX C MEASURING AND COMPENSATING SIGNAL PATH DELAY AND CIRCUIT TRIMMING PROCEDURES Delay Compensation Thesettlingtime circuit utilizes an adjustable delay network to time correct the input pulse for delays in the signal processing path Typically these delays introduce errors of a few percent so a first order correction is adequate setting the delay trim involves observing the network s input output delay and adjusting for the appropriate time interval Determining the appropriate time interval is somewhat more complex Measuring the settling time circuits signal path delay involves modifications to Figure 13 shown in Figure C1 These changes lock the circuit into its sample mode permitting an input to output delay measurement under signal level conditions similar to normal operation In Figure C2 trace A is the n RESIDUE AMPLIFIER A 40 7500 A2 P 560 560 5V tk 10k v 1000 SAMPLE INTERVAL ZERO pulse generator input at 200uV DIV note 10k 1 divider feeding the settle node Irace B shows the circuit output at A4 delayed by about 44ns This delay is a small error but is readily corrected by adjusting the delay network for the same time lag If appendix F s serial interface is utilized 10ns should be added to the delay correction similarly if appendix l s post amplifier is used the delay correction must b
31. e command F and settle signal output G M1 s delayed output maintains the sample interval zero value independent of the settling signature A 10v DIV MM B 10v DIV E c 10V DiV illum D 10v oiv MEE E 10V DIV F 10V DIV G 1mV DIV ee te C ummummm 2us DIV AN120 FI03 Figure 14 is a simple time calibrator used to verify oscil loscope time base accuracy Q1 and Q2 form a 1MHz quartz oscillator The 74090 provides switch selectable output periods of 2us and Sus and the attenuator supplies a DOQ output impedance The period values have been selected for calibration points appropriate for expected DAC settling times Other periods are available by vary ing oscillator frequency division ratio or both 9V battery drain is about 10mA Figure I3 Auto Zero Related Waveforms Include Time Corrected Input Pulse Trace A DAC Output B Sample Delay C M1 s Input D M1 s Sample Interval Zero Pulse E G1 s Sample Command F and Settle Signal Output G M1 s Delayed Output Maintains Sample Interval Zero Value Independent of Settling Signature 1MHz 9V 9V 100pF 1 2N3904 100pF 9V 2us OUTPUT 510 ous PERIOD SELECT E AN120FI04 Figure 14 Battery Powered Oscilloscope Time Base Verifier Has 2ys and 5ps Period Outputs Quartz Oscillator Q1 Is Buffered by Q2 Digital Divider Supplies Outputs Via Attenuator an120f AN120 35 Application Note 120 INPUT PULSE BERE ERR 5V DIV REN
32. e increased by 1 ns A 200uV DIV eS EE EE B 10mV DIV Sess AN120 FC02 20ns DIV Figure C2 Sampling Circuit Input Output Delay Measures About 44ns INPUT STEP REFERENCE TO OSCILLOSCOPE CONNECT SETTLE NODE RESISTORS AS SHOWN SETTLE 10k NODE 10k 5V PULSE INPUT e d 10k pA 19 VARIABLE TRANSCONDUCTANCE AMPLIFIER A3 CFA M soo SETTLE OUTPUT 500 50pF TO 50 OSCILLOSCOPE 1mV DIV 50uV DIV 500 AT DAC OUTPUT GAIN 5V 100k 1k BASELINE ZERO ABERRATIONS tk 5V ME 15V i 7 5k SAMPLE 1 6k WINDOW GENERATOR 2N3906 50pF SAMPLE 0 02uF TRANSITION 3 57k SAMPLE COMMAND DISCONNECT SAMPLE mE ZZ cm T COMMAND LINE AN120 FCO1 Figure C1 Partial Text Figure 13 Schematic Shows Modifications for Measuring Signal Path Delay Changes Lock Circuit into Sample Mode Permitting Input to Output Delay Measurement an120f AN120 17 Application Note 120 Circuit Trimming Procedure The following procedure given in numerical order trims the settling time circuit for optimum performance It is advisable to execute trimming in the order given avoiding out of sequence adjustments 1 Turn off input pulses 2 Trim Baseline Zero for OV out at oscilloscope at 10mV per division or less 3 Disconnect precision 10k resistors and ground settle node via 9 1kQ 4 Setsample delay to mid range sample window width to minimum 9 Drive pulse generator input with 40kHz square
33. es Attention to Layout an120f AN120 8 AL Le Application Note 120 LT1021 10V reference via the precision 10k summing resistors The LT1021 also furnishes the DAC reference making the measurement ratiometric The clamped settle node is unloaded by A1 which takes gain A2 provides additional clamped gain for a total summing node referred amplification of 40 A2 s output feeds the sampling switch whose operation is identical to Figure s description The A1 A2 amplifiers clamping and gain are arranged so saturation never occurs the amplifier is always in its active region The input pulse triggers the 4HC123 dual one shot The one shot is arranged to produce a delayed controllable by the 20k potentiometer pulse whose width controllable by the 5k potentiometer sets sampling switch on time If the delay is set appropriately the oscilloscope will not see any input until settlingis nearly complete eliminating overdrive Thesample window width is adjusted so that all remaining activity is observable In this way the oscilloscope output is reliable and meaningful data may be taken Figure 14 shows circuit waveforms Trace A is the time corrected input pulse trace B the sample gate trace C the DAC amplifier output and trace D the circuit output When the sample gate goes high trace D s switching is clean the last millivolt of ring time is easily observed and the amplifier settles nicely to final value bounded by broadba
34. hops the stabilizing amplifier at about 500Hz providing updates to the hold capacitor offset control every 2ms The settling time of this composite amplifier is a func tion of the fast and stabilizating paths response Figure E2 shows amplifier short term settling Trace A is the DAC input pulse and trace B the settle signal Damping is reasonable and the 10us settling time and profile ap pear typical Figure E3 brings an unpleasant surprise If the DAC slewing interval happens to coincide with the ampliflers sampling cycle serious error is induced In Figure E3 trace A is the amplifier output and trace B the settle signal Note the slow horizontal scale The ampli fier initially settles quickly settling is visible in the 2nd Note 1 This AC processing of DC information is the basis of all chopper and chopper stabilized amplifiers In this case if we could build an inherently stable CMOS amplifier for the stabilizing stage no chopper stabilization would be necessary Note 2 Those finding this description intolerably brief are commended to reference 31 A 5V DIV B 500uV DIV E ani ra AN120 FE02 5ys DIV Figure E2 Short Term Settling Profile of Chopper Stabilized Amplifier Seems Typical Settling Appears to Occur in 10us an120f AN120 20 Application Note 120 vertical division region but generates a huge error 200us later when its internal clock applies an offset correction successive clock cycles prog
35. immediate foreground In keeping with all things monolithic the cost performance trade off of modern high resolution IC DACs is a bargain Think of it An 18 bit DAC in an IC package What Lord Kelvin would have given for a credit card and LTC s phone number Figure A1 Historically Significant Digital to Analog Converters Include Weight Set Center Left 23 Bit Kelvin Varley Divider Large Box Hybrid Board and Modular Types and the LTC2757 IC Foreground Where Will It All End an1 20f AN120 13 Application Note 120 APPENDIX B EVALUATING OSCILLOSCOPE OVERDRIVE PERFORMANCE The settling time circuit is heavily oriented towards eliminating overdrive at the monitoring oscilloscope Oscilloscope recovery from overdrive is a murky area and almost never specified How long must one wait after an overdrive before the display can be taken seriously The answer to this question is quite complex Factors involved include the degree of overdrive its duty cycle its magnitude in time and amplitude and other consider ations Oscilloscope response to overdrive varies widely between types and markedly different behavior can be observed in any individual instrument For example the recovery time for a 100x overload at 0 005V DIV may be very different than at 0 1V DIV The recovery characteris tic may also vary with waveform shape DC content and repetition rate With so many variables it is clear that measurements involving
36. ing Time Due To DAC Dynamics Settling Times Range From 41s to 6ps Fractional LSB Tailing is Evident an120f AN120 11 Application Note 120 REFERENCES 1 Williams Jim Componentand Measurement Advances Ensure 16 Bit DAC Settling Time Linear Technology Corporation Application Note 74 July 1998 2 Williams Jim Measuring 16 Bit Settling Times The Art of Timely Accuracy EDN November 19 1998 3 Williams Jim Methods for Measuring Op Amp Set tling Time Linear Technology Corporation Application Note 10 July 1985 4 Demerow R Settling Time of Operational Ampli fiers Analog Dialogue Volume 4 1 Analog Devices Inc 1970 9 Pease R A The Subtleties of Settling Time The New Lightning Empiricist Teledyne Philbrick June 1971 6 Harvey Barry Take the Guesswork Out of Settling Time Measurements EDN September 19 1985 7 Williams Jim Settling Time Measurement Demands Precise Test Circuitry EDN November 15 1984 8 Schoenwetter H R High Accuracy Settling Time Measurements IEEE Transactions on Instrumentation and Measurement Vol IM 32 No 1 March 1983 9 Sheingold D H DAC Settling Time Measurement Analog Digital Conversion Handbook pg 312 317 Pren tice Hall 1986 10 Williams Jim 30 Nanosecond Settling Time Measure ment fora Precision Wideband Amplifier Linear Technol ogy Corporation Application Note 79 September 1999 11 Wil
37. ion of current in the ground plane The impedance of the ground plane between any two points is not zero particularly as frequency scales up This is why the entry point and flow of dirty ground returns must be carefully placed within the grounding system In the sampler based breadboard the approach was separate dirty and signal ground planes tied together at the supply ground origin A good example of the importance of grounding manage mentinvolves delivering the input pulse to the breadboard The pulse generators 50Q termination must be an in line coaxial type and it cannot be directly tied to the signal ground plane The high speed high density 5V pulses through the 50 termination generate 100mA current spikes current flow must return directly to the pulse generator The coaxial terminators construction ensures this substantial current does this instead of being dumped into the signal ground plane 100mA termination current flowing through 1m of ground plane produces approxi mately 3LSB of error The 50O termination is physically distanced fromthe breadboard via a coaxial extension tube visible in Figure H7 This further ensures that pulse generator return current circulates in a tight local loop at the terminator and does not mix into the signal plane It is worth mentioning that every ground return in the entire circuit must be evaluated with these concerns in mind A paranoiac mindset is quite useful Shielding
38. l Parallel Inputs 1LSB Linearity Current Output COMMENTS Good Low Speed Choice 10mA Output Capability Good Low Speed Choice Low Power Consumption 1 8us Settling to 18 Bits Fastest Available Lowest Error 10ms Settling Time Requires LT1010 Output Buffer Special Case See Appendix E Lowest Drift Reference in This Group 4ppm 1LSB Yr Time Stability Typical Low Drift 10ppm 2 5LSB Yr Time otability Typical Good General Purpose Choice 16LSB Good General Purpose Choice Trimmed to 0 05 Absolute Accuracy Considerations for Measuring DAC Settling Time Historically DAC settling time has been measured with circuits similar to that in Figure 2 The circuit uses the false sum node technique The resistors and DAC form a bridge type network Assuming ideal components the DAC output will step to Vper when the DAC inputs move to all ones During slew the settle node is bounded by the diodes limiting voltage excursion When settling occurs the oscilloscope probe voltage should be zero Note that the resistor dividers attenuation means the probe s output will be one half of the DAC s settled voltage Note 3 This issue is treated in detail in latter portions of the text Also see Appendix D Practical Considerations for DAC Amplifier Compensation AN120 2 Application Note 120 INPUT STEP TO OSCILLOSCOPE OV TO 10V 4 TRANSITION OUTPUT TO OSCILLOSCOPE AN120 F02 Figure 2 Popular S
39. liams Jim Evaluating Oscilloscope Overload Performance Box Section A in Methods for Measuring Op Amp Settling Time Linear Technology Corporation Application Note 10 July 1985 12 Orwiler Bob Oscilloscope Vertical Amplifiers Tek tronix Inc Concept Series 1969 13 Addis John Fast Vertical Amplifiers and Good Engineering Analog Circuit Design Art Science and Personalities Butterworth Heinemann 1991 14 Travis W Settling Time Measurement Using Delayed Switch Private Communication 1984 15 Hewlett Packard Schottky Diodes for High Volume Low Cost Applications Application Note 942 Hewlett Packard Company 1973 16 Korn G A and Korn T M Electronic Analog and Hybrid Computers Diode Switches pg 223 226 McGraw Hill 1964 17 Carlson R A Versatile New DC 500 MHz Oscillo scope with High Sensitivity and Dual Channel Display Hewlett Packard Journal Hewlett Packard Company January 1960 18 Tektronix Inc Sampling Notes Tektronix Inc 1964 19 Tektronix Inc Type 181 Sampling Plug In Operating and Service Manual Tektronix Inc 1965 20 Mulvey J Sampling Oscilloscope Circuits Tektronix Inc Concept Series 1970 21 Addis John Sampling Oscilloscopes Private Com munication February 1991 22 Williams Jim Bridge Circuits Marrying Gain and Balance Linear Technology Corporation Ap
40. lity to overdrive induced errors At 18 bits there is clearly no chance of measure ment integrity The preceding discussion indicates that measuring 18 bit Settling time requires a high gain oscilloscope that is some how immune to overdrive The gain issue is addressable with an external wideband preamplifier that accurately amplifies the diode clamped settle node Getting around the overdrive problem is more difficult The only oscilloscope technology that offers inherent overdrive immunity is the classical sampling scope Un fortunately these instruments are no longer manufactured although still available on the secondary market Itis pos sible however to construct a circuit that utilizes sampling techniquesto avoid the overload problem Additionally the circuit can be endowed with features particularly suited for measuring 20 bit DAC settling time Sampling Based High Resolution DAC Settling Time Measurement Figure 3 is a conceptual diagram of the 20 bit DAC settling time measurement circuit This figure shares attributes with Figure 2 although some new features appear In this case the preamplified oscilloscope is connected to the settle point by a switch The switch state is determined by a delayed pulse generator which is triggered from the same pulse that controls the DAC The delayed pulse generators timing is arranged so that the switch does not close until settling is very nearly complete In this way the incoming
41. ly in a state of the art measurement However a reasonable level of confidence is a realistic goal Performance verification forthe settling time test circuit requires a high purity pulse generator that transitions and settles to 1ppm as quickly as possible This is a high order difficulty requirement and the authoris unaware of any electronic means of achieving this capability Fortunately electro mechanical technology offers a solution Figure H1 shows a conceptual mercury wetted reed relay pulse generator Theoretically when the contacts open an infinitely fast falling edge appears across the 50Q termina tion with zero settling time to OV Figure H2 reveals this to be not the case This photograph taken with a typical commercially available relay shows 5ns transition time with a 500MHz ring off over 10ns These imperfections are not surprising when Figure H3 s parasitic terms are considered Figure H1 s deceptively simple schematic is revealed to have a number of unintentional terms which severely limit performance These terms include but are not limited to parasitic resistance inductance and ca pacitance as well as undesirable field interaction within the relay Additionally the connection through the relay to the outputterminal constitutes an ill defined transmission line which promotes additional vagaries The parasitic terms V OUTPUT 50Q m AN120 FH01 Figure H1 Conceptual Mercury Wetted Reed Relay Pulse Gene
42. mane to the present efforts purposes and was not implemented Note 11 Settling time is significantly affected by the DAC amplifier compensation capacitor See Appendix D Practical Considerations for DAC amplifier Compensation for tutorial an120f AN120 10 Application Note 120 Figure 24 uses noise averaging techniques to measure settling time to 20 bits 1ppm 10uV without the band limiting filters time penalty Photo A shows the DAC amplifier adjusted for overdamped response B and C A 5V DIV pupa mom nana B 500uV DIV AN120 F21 1us DIV Figure 21 OV to 10V DAC Settling in Unfiltered Bandpass DAC Settles Settle Output Trace B to 16 Bits 15ppm lt 2ps After Trace As Time Corrected Input Step Sample Gate Feedthrough is Well Controlled Indicating Higher Resolution is Possible Without Overdriving Oscilloscope Noise Limits Measurement A 5V DIV B 250uV DIV AN120 F22 1us DIV Figure 22 Same Trace Assignments as Previous Photo Measurement Taken in 250kHz Bandpass Settling to 18 Bits 4ppm Requires 5ps Filtering Permits Increased Resolution Although Indicated Settling Time Increases eb dp bea LL pert 1 i E I e a m a D ae i Epi im a a 1 ALL PHOTOS TRACE A 5V DIV TRACE B 25yV DIV AVERAGED HORIZ 1us DIV underdamped and optimum respo
43. nance set and trigger functions must be used to avoid output pulse contamination Figure H9 shows results for the pretty good step generator Its slower settling and alien residue components compared to the Tektronix 109 approach are apparent The event at the 10th vertical division is sample gate turn off feedthrough related 20V ADJUSTABLE SEE TEXT RESONANCE SET VN2222LL 0 1F 1 6 74HC14 L GROUND 5 90Hz UNUSED TYPICAL INPUTS SELECT ON CURVE TRACER FOR 211V BREAKDOWN SEE TEXT SEPARATE 74HC14 PACKAGES FOR RESONANCE SET AND TRIGGER OUT FUNCTIONS SEE TEXT GR 874 3 J MIDTEX 160 151 W00 Circuit calibration involves adjusting resonance set until the relay emits a reasonably pure audible tone Next set the 20V supply to a value which promotes the cleanest settling characteristics Note 5 Footnote 4 s 70ns timing allowance applies here Figure H8 likely settles in 880ns B 50yv DIV BEN OUS UU BER SEDIS PENES a AVERAGED E Er m AN120 FH09 o00ns DIV Figure H9 Pretty Good Step Generator Output Trace A Settles Trace B to 1ppm 10pV in 950ns Ill Defined Relay Impedance Results in Approximately 3 6x Slower Settling and Alien Reside Components Compared to Figure H5 s Tektronix 109 Based Results Event at 10th Vertical Division is Sample Gate Turn Off Feedthrough TEFLON 509 0 5 MAX PATH LENGTH TRIGGER OUT AN120 FHO8 74HC14
44. nd noise When the sample gate goes low the transconduc tance switch goes off and no feedthrough is discernible Note that there is no off screen activity at any time the oscilloscope is never subjected to overdrive The circuit requires trimming to achieve this level of performance Figure 15 shows a typical display result ing from poor Sample Interval Zero adjustment This i i we A 10V DIV ls B 10V DIV T H E P hi C 10V DIV ape ee land D 500uV DIV C AN120 F14 Figure 14 Settling Time Circuit Waveforms Include Time Corrected Input Pulse Trace A Sample Command Trace B DAC Output Trace C and Settling Time Output Trace D sample Window Delay and Width are Variable adjustment corrected in Figure 16 results in a continuous baseline Sample command feedthrough is just visible at trace B s leading edge Figure 17 shows output response trace B to the sample command trace A turn on before trimming aberrations and transition purity Delay is approximately 20ns with aberrations peaking 350uV and Note 8 To maintain text flow and focus trimming procedures are not presented here Detailed trimming information appears in Appendix C Note 9 A1 s positive input was grounded via 5kQ precision 10k resistors disconnected for Figure 17 and 18 s tests B 10mV DIV Ie 2500 V DIV WITH Ems RESPECT TO A1 AN120 F15 Figure 15 Poor Sample Interval Zero Adjustmen
45. ng times complicating amplifier choice and frequency All other trademarks are the property of their respective owners Note 1 See Appendix A A History of High Accuracy Digital to Analog Conversion Note 2 A historical note is in order In early 1997 LTC s DAC design group tasked the author to measure 16 bit DAC settling time The result was published in July 1998 as Application Note 74 Component and Measurement Advances Ensure 16 Bit DAC Settling Time Almost exactly 10 years later the DAC group raised the ante requesting 18 bit DAC settling time measurement This constitutes 2 bits of resolution improvement per decade of author age Since it was unclear how many decades the author born 1948 had left it was decided to double jump the performance requirement and attempt 20 bit resolution In this way even if the author is unavailable in 10 years the DAC group will still get its remaining 2 bits an120f AN120 1 Application Note 120 COMPONENTS FOR 18 BIT D A CONVERSION Components suitable for 18 bit D A conversion are members of an elite class 18 binary bits is one part in 262 144 just 0 000496 or 4 parts per million This mandates a vanishingly small error budget and the demands on components are high The LTC2757 digital to analog converter listed in the chart uses Si Chrome thin film resistors for high stability and linearity over temperature Gain driftis typically 0 25ppm C or about 4 6LSBs over 0 C to
46. nity at the cable s receiving end The back termination enforces a50Q environment Current source Q1 controlled by the switch control input sets A1A s transconductance and hence gain With Q1 gated off control input at zero the 10M resistor supplies about 1 5pA into A1A s Isgr pin resulting in a voltage gain of nearly zero blocking the input signal When the switch control input goes high Q1 turns on sourcing approximately 1 5mA into the Icey pin This 1000 1 set current change forces maximum transconductance causing the amplifier to assume unity gain and pass the input signal Trims for zero and gain ensure accurate input signal replication at the circuit s output The Q1 associated 50pF variable capacitor puri fies turn on switching The specified 10k resistor at Q1 has a 3300ppm C temperature coefficient compensat ing A1A s complementary transconductance temperature dependence to minimize gain drift rre E TT CEEEH N C TOLO T E AN120 F08 100ns DIV Figure 8 Control Input Trace A Dictates Switch Output s Trace B Representation of 0 01V DC Input Control Channel Feedthrough Evident at Switch Turn On Settles in 20ns Turn Off Feedthrough is Undetectable Due to Deceased Signal Channel Transconductance and Bandwidth Caperration 35pF for this Test Figure 8 shows circuit response for a switched 10mV DC input and CagEnnarioN 3opF When the control input trace A is low no output trace B occurs When
47. nses respectively Averaging eliminates noise permitting determination of settling time due to DAC dynamics Settling time ranges from 4us to 6us with fractional LSB tailing evident Note This application note was derived from a manuscript originally prepared for publication in EDN magazine Note 12 Most oscilloscopes require preamplification to resolve Figure 24 s signal amplitudes See Appendix Auxiliary Circuits for an example Note 13 More properly this measurement determines DAC settling time due solely to step input initiated dynamics For this reason Figure 24 s averaged results may be considered somewhat academic Noise limits measurement certainty at any given instant to approximately 100uV It is not unreasonable to maintain that this 100uV of noise means the DAC never settles inside this limit The averaged measurement defines settling time with noise limitations removed Hopefully this disclosure will appease technolawyers among the readership erasian x ox A 5V DIV GF AN120 F23 2us DIV Figure 23 19 Bit 2ppm Settling is Discernable About Quis After Input Command in 50kHz Bandwidth AN120 F24 Figure 24 Noise Averaging Oscilloscope Permits 1ppm 10pV Settling Time Measurement Without Bandlimiting Filter Time Penalty Photo A Shows Overdamped Response B and C Underdamped and Optimum Responses Respectively Averaging Eliminates Noise Permitting Determination of Settl
48. oaxial Transformer Right End of Air Line Supplies Trigger Pick Off Via 50Q BNC Vertical Connector GR 874 Coaxial 50Q Load Right Side of CT 3 Terminates Line And Supplies Pulse to Breadboard Pulse Amplitude is Set by DC Voltage Applied to Tektronix 109 Via Banana Input Adapter Unused Type 109 Contact is Terminated with End Line GR 874 Fitting All Connections Must Be Polished and Mechanically Secure to Ensure High Fidelity 50 Environment Long Coaxial Extension Tube On Breadboard Isolates Input Pulse Termination Tube Top Current from Board Ground Plane see Text and Figure G1 For Commentary Lower Board Contains Digital Serial Interface See Appendix F and Figure G4 an120f AN120 32 Application Note 120 Pretty Good Mercury Wetted Reed Relay Pulse Generator It may be unrealistic for readers to duplicate the Tektro nix 109 based results The specified exotic apparatus is difficult and expensive to obtain and the set up requires arduous labor and almost fanatical attention to detail In this spirit Figure H8 s pretty good mercury wetted reed relay pulse generator is offered Its performance while falling well short of Figure H6 still furnishes a 10V step which settles to 1ppm in 950ns A simple clock resonance set furnishes low frequency drive to the relay via the transistor level shift and the LT1010 power buffer Trigger pick off is provided by the paralleled CMOS inverters Separate packages for the reso
49. oscilloscope overdrive must be approached with caution Why do most oscilloscopes have so much trouble recover ing from overdrive The answer to this question requires some study of the three basic oscilloscope types vertical paths The types include analog Figure B1A digital Figure B1B and classical sampling Figure B1C oscilloscopes Analog and digital scopes are susceptible to overdrive The classical sampling scope is the only architecture that is inherently immune to overdrive Ananalog oscilloscope Figure B1A is areal time continu ous linear system The input is applied to an attenuator whichis unloaded by a wideband buffer The vertical preamp provides gain and drives the trigger pick off delay line and the vertical output amplifier The attenuator and delay line are passive elements and require little comment The buffer preamp and vertical output amplifier are complex linear gain blocks each with dynamic operating range restrictions Additionally the operating point of each block may be set by inherent circuit balance low frequency Stabilization paths or both When the input is overdriven one or more of these stages may saturate forcing internal nodes and components to abnormal operating points and temperatures When the overload ceases full recovery of the electronic and thermal time constants may require surprising lengths of time The digital sampling oscilloscope Figure B1B eliminates the vertical o
50. peci fied error band around the final value To measure a new 18 bit DAC a settling time measurement technique has been developed with 20 bit 1ppm resolution for times as short as 265ns The new method will work with any DAC Realizing this measurement capability and its performance verification has required an unusually intense extensive and protracted effort Hopefully the data converter com munity will find the results useful DAC settling time is usually specified for a full scale 10V transition Figure 1 shows that DAC settling time has three DAC INPUT lt SETTLING TIME gt ALL BITS 9 lt RING TIME d ALLOWABLE OUTPUT ERROR BAND DAC OUTPUT gt DELAY TIME AN120 FO1 Figure 1 DAC Settling Time Components Include Delay Slew and Ring Times Fast Amplifiers Reduce Slew Time Although Longer Ring Time Usually Results Delay Time is Normally a Small Term distinct components The delay time is very small and is almost entirely due to propagation delay through the DAC and output amplifier During this interval there is no output movement During s ew time the output amplifier moves at its highest possible speed towards the final value Ring time defines the region where the amplifier recovers from slewing and ceases movement within some defined error band There is normally a trade off between slew and ring time Fast slewing amplifiers generally have extended ri
51. plication Note 43 June 1990 23 Tektronix Inc Type 661 Sampling Oscilloscope Operating and Service Manual Tektronix Inc 1963 24 Tektronix Inc Type 451 Sampling Plug In Operating and Service Manual Tektronix Inc 1963 25 Tektronix Inc Type 513 Timing Unit Operating and service Manual Tektronix Inc 1965 26 Morrison Ralph Grounding and Shielding Techniques in Instrumentation 2nd Edition Wiley Interscience 1977 2 Ott Henry W Noise Reduction Techniques in Elec tronic Systems Wiley Interscience 1976 28 Williams Jim High Speed Amplifier Techniques Lin ear Technology Corporation Application Note 47 1991 29 Tektronix Inc Type 109 Pulse Generator Operating and Service Manual Tektronix Inc 1963 30 Williams Jim Signal Sources Conditioners and Power Circuitry Wideband Low Feedthrough Low Level Switch pg 13 15 Appendix A How Much Bandwidth is Enough pg 26 Linear Technology Corporation Ap plication Note 98 November 2004 31 Williams Jim Applications Considerations and Circuits for a New Chopper Stabilized Op Amp Linear Technology Corporation Application Note 9 March 1985 AN120 12 Application Note 120 APPENDIX A A HISTORY OF HIGH ACCURACY DIGITAL TO ANALOG CONVERSION People have been converting digital to analog quantities for a long time Probably among the earliest uses was the summing of calib
52. rated weights Figure A1 left in weighing applications Early electrical digital to analog conversion inevitably involved switches and resistors of different values usually arranged in decades The application was often the calibrated balancing of a bridge or reading via null detection some unknown voltage The most accurate resistor based DAC ofthistype is Lord Kelvin s Kelvin Var ley divider Figure large box Based on switched resistor ratios it can achieve ratio accuracies of 0 1ppm 234 bits andis still widely employed in standards laboratories High speed digital to analog conversion resorts to electronically switching the resistor network Early electronic DACs were built at the board level using discrete precision resistors and Germanium transistors Figure center foreground is a 12 bit DAC from a Minuteman missile D 17B inertial navigation system circa 1962 The first electronically switched DACs available as standard product were prob ably those produced by Pastoriza Electronics in the mid 1960s Other manufacturers followed and discrete and monolithically based modular DACs Figure right and left became popular by the 1970s The units were often potted Figure left for ruggedness performance orto hopefully preserve proprietary knowledge Hybrid technology pro duced smaller package size Figure left foreground The development of Si Chrome resistors permitted precision monolithic DACs such as the L TC2757 Figure
53. rator Produces Infinitely Fast Falling Edge Across 50Q Termination with Zero Settling Time to OV o EP osi Pesca RE o aes 1V DIV AN120 FH02 10ns DIV Figure H2 Mercury Wetted Reed Relay Opens in bns Settles Quickly to Zero 500MHz Ring Off Derives from Source Termination Impedance Mismatch V PARASITIC FIELD PARASITIC C PARASITIC R IMPERFECT 509 TRANSMISSION LINE PARASITIC L PARASITIC C MISMATCHED __ TERMINATIONS E AN120 FHO3 Figure H3 Parasitic Terms Limit Achievable Performance Transmission Line Required to Route Output Pulse Adds Termination Mismatch Errors and Line Related Infidelities interact in a haphazard and unpredictable way resulting in alien terms at the pulse output What is really needed is a relay specifically designed and constructed for inclusion into a wideband 50Q system A True 506 Wideband Mercury Wetted Reed Relay Inthe 1960s Tektronix manufactured the type 109 mercury wetted reed relay intended for use as a pulse generator In its preferred configuration energized charge lines are Note 1 Tangential to this discussion but nonetheless interesting is the corner rounding at the pulse top just before its rapid fall This may be due to teasing of the mercury causing its resistance to increase just before it fully opens John Willison of Stanford Research Systems suggests the mechanism may be charge displacement in the capacitor formed as the relay conta
54. rent DACs have different values of output capacitance CMOS DACs have the highest output capacitance typically 100pE and it varies with code A 5vyipiv B B 100uV DIV li AVERAGED lj 500ns DIV AN120 FC02 Figure D2 Optimized Compensation Capacitor Permits Nearly Critically Damped Response Faster Settling Time tggrri c 1 8ps to 0 000496 18 Bits Best settling results when the compensation capacitor Is selected to functionally compensate for all the above parasitics Figure D2 taken with an LTC2757 LT1468 DAC Amplifier combination shows results for an optimally selected in this case 20pF feedback capacitor Trace A is the DAC input pulse and trace B the amplifiers settle signal Theamplifieris seen to come cleanly out of slew and settle very quickly In Figure D3 the feedback capacitor is too large 2 pF settling is smooth although overdamped and a 300ns penalty results Figure D4 s feedback capacitor is too small 15pF causing a somewhat underdamped response with resultant excessive ring time excursions Settling time goes out to 2 8us Note that the above compensation values for 18 bit settling are not necessarily indicative of results for 16 or 20 bits Optimal compensation values must be establishedforany given desired resolution Typical values range from 15pF to 39pF Note 1 Spice aficionados take notice AN120 FD03 Figure D3 Overdamped Response Ensures Freedom from Ringing Even with Production
55. ressively chop the error into the noise but 7 milliseconds are required for complete recovery The error occurs because the amplifier sampled offset when its input was driven well outside its bandpass This caused the stabilizing amplifier to acquire erroneous offset information When this correction was applied the result was a huge output error AN120 FEO3 1ms DIV Figure E3 Surprise Actual Settling Requires 700x More This is admittedly a worst case It can only happen if the Time Than Figure E2 Indicates Slow Sweep Reveals DAC slewing interval coincides with the amplifier s internal Monstrous Tailing Error Note Horizontal Scale Change Due clock cycle but it can happen to Amplifiers Clocked Operation Stabilizing Loop s Iterative Corrections Progressively Reduce Error Before Finally Note 3 Readers are invited to speculate on the instrumentation Disappearing Into Noise requirements for obtaining Figure E3 s photo Note 4 The spirit of Appendix D s footnote 2 is similarly applicable in this instance APPENDIX F loading afull scale step into the DAC Figure F1 s processor based circuitry designed and constructed by LTC s Mark SETTLING TIME MEASUREMENT OF SERIALLY Thoren does this The start pulse trace A Figure F2 LOADED DACS initiates the measurement Traces B C and D are CS LD mE SCK and SDI respectively Trace E the resultant DAC Measuring serially loaded DACs settling time requires output is measured for
56. rhaps unduly pessimistic RMS error summing may be a defensible compromise but will keep you out of trouble Note 2 The potential problems with RMS error summing become clear when sitting in an airliner that is landing in a snowstorm APPENDIX E A VERY SPECIAL CASE MEASURING SETTLING TIME OF CHOPPER STABILIZED AMPLIFIERS The text box section page 2 lists the LTC1150 chop per stabilized amplifier The term special case appears in the comments column A special case it is To see why requires some understanding of how these ampli fiers work Figure E1 is a simplified block diagram of the LTC1150 CMOS chopper stabilized amplifier There are actually two amplifiers The fast amp processes input signals directly to the output This amplifier is relatively quick but has poor DC offset characteristics A second clocked amplifier is employed to periodically sample the offset of the fast channel and maintain its output hold capacitor at whatever value is required to correct the fast amplifiers offset errors The DC stabilizing amplifier is clocked to permit it to operate internally as an AC ampli fier eliminating its DC terms as an error source The clock OUTPUT OFFSET CONTROL oC STABILIZING INPUTS OFFSET HOLD CAPACITOR AMP AN120 FEO1 Figure E1 Highly Simplified Block Diagram of Monolithic Chopper Stabilized Amplifier Clocked Stabilizing Amplifier and Hold Capacitor Cause Settling Time Lag c
57. se Conditions 5 1k Resistor Mimics 10kQ Divider Output Impedance at A1 APPENDIX D PRACTICAL CONSIDERATIONS FOR DAC AMPLIFIER COMPENSATION Therearea number of practical considerations in compen sating the DAC amplifier pair to get fastest settling time Our study begins by revisiting text Figure 1 repeated here as Figure D1 Settling time components include delay slew and ring times Delay is due to propagation time through the DAC amplifier and is a very small term Slew time is set by the amplifiers maximum speed Ring time defines the region where the amplifier recovers from slewing and ceases movement within some defined error band Once a DAC amplifier pair have been chosen only ring time is DAC INPUT lt SETTLING TIME ALL BITS s G RING TIME d ALLOWABLE OUTPUT ERROR SLEW BAND TIME gt lt DELAY TIME DAC OUTPUT AN120 FDO1 Figure D1 DAC Amplifier Settling Time Components Include Delay Slew and Ring Times For Given Components Only Ring Time is Readily Adjustable AN120 18 Application Note 120 readily adjustable Because slew time is usually the domi nantlag itis tempting to selectthe fastest slewing amplifier available to obtain best settling Unfortunately fast slewing amplifiers usually have extended ring times negating their brute force speed advantage The penalty for raw speed is invariably prolonged ringing which can only
58. solution FROM FIGURE 13 s SAMPLE COMMAND Q1 PULSE DISCONNECT Q1 PULSE FROM SAMPLE COMMAND LINE 1k 5V 470pF 10pF 10k br B1 CIR RC C M1 Al 4 0 74HC123 Q SAMPLE INTERVAL ZERO PIN 8 LOGICAL 8 ZERO S1 OPEN 10k S1 100k 2 0 1yF FROM T1228 OUTPUT 0 1uF gy 9 BASELINE SAMPLE INTERVAL REFERENCE PIN 9 LOGICAL ZERO S2 CLOSED 5V 10k AUTO ZERO BIAS TO FIGURE 13 s SAMPLE COMMAND LINE 0 05uF e AUTO ZERO OFF 9102 9100 ro T4228 AUTO ZERO cc MP INPUT ON ET jl 1 4 74HC86 GROUND UNUSED INPUTS o o 1 4 LTC203 OBSERVE PIN CALL OUTS GROUND PINS 1 AND 16 5V SUPPLIES AN120 F102 Figure 12 Auto Zero Locks Sample Interval Zero Value to Non Sampled Region Baseline Synchronously Switched A1 Compares Sample Interval and Non Sampled Region Values and Applies Appropriate Offset Closing Correction Loop Around LT1228 M1 Precludes Settling Activity from Influencing Sample Interval Zero Value AN120 34 Application Note 120 for slight errors and should not require readjustment once set to equalize the sample interval zero value and the non sample region baseline The commented schematic provides information for the auto zero s interconnection to the settling time circuit Figure 13 shows auto zero related waveforms They include the time corrected input pulse trace A DAC output B sample delay C M1 input D M1 s sample interval zero pulse E G1 s Sampl
59. t Causes Shifted Output Baseline Trace B During Trace As Sample Interval A SV DIV B 10mV DIV i 250uV DIV WITH RESPECT TO A1 7 tus DIV AN120 F16 Figure 16 Trimmed Sample Interval Zero Has No Output Baseline Deviation Trace B During Sample Interval Trace A Sample Command Feedthrough is Just Visible at Trace B s Leading Edge A 5V DIV EEE se Skea B 10mV DIV 250uV DIV WITH RESPECT TO A1 BEER AN120 F17 Figure 17 Output Response Trace B To Sample Command Trace A Turn On Before Trimming Aberrations and Transition Purity Delay is 20ns Aberrations Peak 350pV Settle in 50ns A1 s Positive Input Grounded via 5kQ for This and Succeeding Figures an120f AN120 9 Application Note 120 settling in 50ns Figure 18 shows post trim response to sample command turn on Delay increases to Ons but aberrations peak only 50uV settling in 50ns Figure 19 shows output response trace B to sample command trace A turn off The 1000 1 transconductance drop ensures a Clean transition independent of the turn on optimized trims Circuit gain is adjusted with the indicated potentiometer A 5V DIV B 10mv DIV JMEN 250uV DIV WITH RESPECT TO A1 l pono CETT Figure 18 Post Trim Output Response Trace B To Sample Command Turn On Trace A Delay Increases to 70ns but Aberrations Peak Only 50pV Settling in 50ns A 5V DIV B 10mV DIV EREREENEEAENENN 250uV DIV WITH RESPECT
60. tured so if you have one take care of it Although analog and digital oscilloscopes are susceptible to overdrive many types can tolerate some degree of this abuse The early portion of this Appendix stressed that measurements involving oscilloscope overdrive must be approached with caution Nevertheless a simple test can indicate when the oscilloscope is being deleteriously affected by overdrive Note 1 Ergo the Real Thing Hopelessly bigoted residents of this locale mourn the passing of the analog scope era and frantically hoard every instrument they can find Note 2 Some discussion of input overdrive effects in analog oscilloscope circuitry is found in reference 13 Note 3 Additional information and detailed treatment of classical sampling oscilloscope operation appears in references 17 20 and 23 25 AN120 14 Application Note 120 INPUT ATTENUATOR ATTENUATOR BUFFER y TRIGGER TO HORIZONTAL CIRCUITRY SWEEP SECTION A ANALOG OSCILLOSCOPE VERTICAL DELAY LINE TO CRT CHANNEL VERTICAL VERTICAL PREAMP OUTPUT V INPUT ATTENUATOR ATTENUATOR BUFFER yt TRIGGER TIMING CIRCUITRY GENERATOR B SAMPLE DIGITAL COMMAND SAMPLING OSCILLOSCOPE MEMORY VERTICAL CHANNEL ais ger MICROPROCESSOR gt T0 CRT vv PULSE STRETCHER O O MEMORY SWITCH MEMORY DRIVER INPUT v r DELAY LINE O CLASSICAL TO CRT SAMPLING ps AC i OSCILLOSCOPE _ AMPLIFIER E VERTICAL
61. umming Scheme for DAC Settling Time Measurement Provides Misleading Results 18 Bit Measurement Causes gt 800x Oscilloscope Overdrive Displayed Information is Meaningless In theory this circuit allows settling to be observed to small amplitudes In practice it cannot be relied upon to produce useful measurements The oscilloscope con nection presents problems As probe capacitance rises AC loading of the resistor junction influences observed settling waveforms A 10pF probe alleviates this problem but its 10x attenuation sacrifices oscilloscope gain 1x probes are not suitable because of their excessive input capacitance An active 1x FET probe will work but a more Significant issue remains The clamp diodes at the settle node are intended to reduce swing during amplifier slewing preventing excessive oscil loscope overdrive Unfortunately oscilloscope overdrive recovery characteristics vary widely among differenttypes and are not usually specified The Schottky diodes 400mV drop means the oscilloscope may see an unacceptable overload bringing displayed results into question At 10 bit resolution 10mV at the DAC output resulting in omV at the oscilloscope the oscilloscope typically undergoes a 2x overdrive at 5 mV DIV and the desired omV baseline is just discernible At 12 bit or higher resolution the measurement becomes hopeless with this arrangement Increasing oscilloscope gain brings com mensurate increased vulnerabi
62. us 2 wait for falling edge Spi write 0x6F Set all DACs to 10V range spi write 0x00 spi write PM5 while input CONTROL delay us 2 wait for rising edge spi write 0x70 DACB Set DACB to 10 volts spi writeloxoo0 spi write 0x00 while input CONTROL delay us 2 wait for falling edge spi write 0x70 DACC Set DACC to 0 volts spi write 0x80 spi write 0x00 while input CONTROL delay us 2 wait for rising edge spi write 0x70 DACD Set DACD to 10 volts spi write OxFF spi write OxFF while 1 while input CONTROL delay us 80 wait for falling edge spi write 0x70 DACA Set DACA to 0 volts spi write OxFF spi write OxFF while input CONTROL delay us 80 wait for rising edge spi write 0x70 DACA Set DACA to 10 volts spi write 0x00 spi write 0x00 j void init setup adc ports NO ANALOGS setup adc ADC CLOCK DIV 2 setup spi SPI MASTER SPI L TO H SPI CLK DIV 4 SPI SS DISABLED CKP 0 Set up clock edges clock idles low data changes on CKE 1 falling edges valid on rising edges setup counters RTCC INTERNAL RTCC DIV 2 setup timer 1 T1 DISABLED setup timer 2 T2 DISABLED 0 1 setup eccpliCCcP OFE setup ccp2 CCP OFF set tris a 0500000000 set tris b 0b00000000 set tris c 0b10000100 Make sure control signal is input j Figure F3 Software Listing for PIC16C73
63. utput amplifier buthas an attenuator buffer and amplifiers ahead of the A D converter Because of this it is similarly susceptible to overdrive recovery problems The classical sampling oscilloscope is unique Its nature of operation makes it inherently immune to overload Figure B1C shows why The sampling occurs before any gain is taken in the system Unlike Figure B1B s digitally sampled scope the input is fully passive to the sampling point Additionally the output is fed back to the sampling bridge maintaining its operating point over a very wide range of inputs The dynamic swing available to maintain the bridge outputis large and easily accommodates a wide range of oscilloscope inputs Because of all this the ampli fiers in this instrument do not see overload even at 1000x overdrives and there is no recovery problem Additional immunity derives from the instrument s relatively slow sample rate even if the amplifiers were overloaded they would have plenty of time to recover between samples The designers of classical sampling scopes capitalized on the overdrive immunity by including variable DC offset generators to bias the feedback loop see Figure B1C lower right This permits the user to offset alarge input so small amplitude activity on top of the signal can be accurately observed This is ideal for among other things settling time measurements Unfortunately classical sampling oscilloscopes are no longer manufac
64. wave 6 Adjust Sample Interval Zero for no offset between the sample interval and the unsampled baseline 7 Adjust Sample Transition Purity and Aberration trims for minimum amplitude disturbances when the Sample gate opens with oscilloscope horizontal at 50ns per division and vertical sensitivity of 10mV per division 0 Reconnect precision 10k resistors and remove 5 1kQ2 unit from the settle node 9 Adjust Delay Compensation for 44ns delay from the pulse generator input to the time corrected output pulse 10 Turn off input pulses Disconnect the pulse generator and its 5002 termination Apply 5V DC to the pulse input 11 Connect Figure C3 s network to the settle node The added components shown furnish a 250uV DC gain calibration source when the input pulses are replaced by a 5V level Under the figure s conditions the DAC assumes a 10V output with the 5 1k resistor mimicking the 10kQ divider output impedance at A1 Figure 13 s Gain trim is adjusted fora 10mV DC deflection at the oscilloscope This completes the trimming procedure and the circuit is ready for use Note 1 The Sample Interval Zero trim is unnecessary if Appendix l s optional auto zero circuitry is used ADD THESE COMPONENTS 10V REFERENCE DISCONNECT i I Figure C3 Added Components Furnish 250V Gain Calibration Source with Input Pulses Replaced by 5V Level DAC Output Assumes 10V Reference Potential Under The

AN120 - 1ppm Settling Time Measurement for a Monolithic 18

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