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8575 N/B Maintenance

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1. 5 4 3 2 1 CLOSE TO CHT017 11 14318MHZ lt gt R565 1 MOD S 5 30 1 VI 7 0 1 9 Spread Range Selection R133 1 2 d R124 1 0603 0 m 50 SRO Spreading Range Input Frequency Modulation Rate R54 1 2 06030 R48 1 5 2 060 1 0 1 50 10 MHz to 20 MHz Fin 10 20 83 KHz R53 1 2 0603 R47 1 5 2 060 cm 1 1 2 50 10 MHz to 20 MHz Fin 10 20 83 KHz R78 4 060 R77 1 2 060 22PINA 22PINA E 9 i 2 Ex 201 PU 0 0 1 25 20 MHz to 35 MHz Fin 10 20 83 KHz R593 1 JQKINA 2 060 R592 1 ASTKINAZ 060 5 5 522 4552 0
2. J J 1 J V LAN C50 C62 C48 C45 C44 9 oiu 08030 J J ososo 09030 50 50V 50 50V 50 3V LAN R61 bd 06030 R609 o 06030 260 4 LX For cowvewrmwce 0607 595 b dm 10K PHY Address 00001 x 06050 R261 284501893001 E 1 2 15 18921 10 PQFP64_0 5MM us 0 RPS 274 1206 laste 0603 15 LAN MRXDO 8 35 expo LSS j 15 2 34 888888822 80 15 LAN MRXD2 88 Dus 88 Uo 15 LANCMRIADS nds fi x03 5 1 15 UN 3 2 mov 5 m a 15 LAN MRXER f 39 RXER usta 0603 15 LAN MRXC RXCLK gt gt
3. 5 4 3 2 1 15505 SHORT SMT4 savs E 1554 q 120Z 100M q 2012 C796 12VS R173 R165 1553 1 2 0 0 1202100 0603 003 1608 AVDDAD 0 01U NA 0514 501 0603 1 1 2 D 7 2 P to Codec t E ADP3301 TOPINA 4 j 1 GND 50 0603 C759 ADPSSOTAR SINA T 100 0 10 610 610 T 100 508 777 777 1206 0603 0603 1206 0603 AGND tov 50 50 50 50 tov R738 1 2 vis 0603 77 R704 1549 AC97_RST ACST RETE 1 MODEM SPK MODEM 5 19 vts 40K NA 0603 ACS7 SDOUT 194049 SDOUT ZH 23 1 2 040 sov 0603 NA BB 58 LINEANI D 50 15 ACS7 SDIN ACSLSDN 2 38 C260 1 2 010 sov MIC SYNC 11 RESET 2 C272 4 2 10V 0603
4. 04 TP501 6 HDH 63 gt 20 6 6 31 Gi Haoss 4 b 11 HOLK CPU aseto 31 9 b LAM m H_ADS 6 pias PN22 ET 11 HCLK AP ds Disa 21 ITP_CLKO TesTH AE 8 ADH Dias HDG Compo BNR H_BNR 6 50826 0 37 pen 15 _ 20 _ 20 2 HD 25 38 TS HEAD H FERRI Aue iius H BPMS PREQ ped 24 0898 DN2s HD 39 H IGNNER Eben H BPM4 PRDY AO Dp 2 26 lt 6821 HOH Dpit 25 c ANGE CORE 15 243 41 pE24 HT 15 INTR D1 2 HORT 625 HD AZ L H BMPTITE anz 2 56 1 2 0603 R748 HD 20 0842 DR24 43 15 UNT 1 ae 96 TESTHIB H STPCLKS 56 1 2 0603 8749 HORTS HCSTPCUKK vao SMM Wi TESTHS 561 0603 R750 HOFS HHS x TE
5. PD504 D D Board ALWAYS 7508 PD503 120Z 100M gt ADINP PD514 PF501 5 PD505 POWERIN of ot e o DVMAIN T m T ROAD SERM 518 L o gt 523 L 470K T 1000P T ms V V ook V PQ501 2N7002 LEARNING Step Connect Adaptor to D D BD J2 amp O P ALWAYS i 0509 P2 P27 Step2 ALWAYS gt 0506 Generate 5VA V rd p Micro Step3 H8 O P LEARNING for Charger Circuitry Controller VDDSS 0 9 vec PU1 our EDT 47 A 39 NEN Step4 For MOSFET 0502 G 0 D lt gt S PUL 29 aes 4 5 P2 d Step5 O P ADINP amp DVMAIN 01 Oe T 9 MAXAI73FEUT T V V R724 100K V E ALWAYS U506 H8_AVREF1 5VA 45V T LP2951 02BM 51250105 I E 5 e e 5 un En 1 2 6 E 2 0508 0516 L L R725 RESET SVTAP SENSE RLZ5 6B 0075 68 T 10 47 T 8621 10K 3 SHUTDN V V V HUS SW 45VA Sw502 pa tJ Pm R618 GND To H8 e 3 MN V SW 45VA 0515 From jij 7 0510 T DTC144WK Mother Bo
6. DDR WE RPI3 1 16 Lom ACRI er x 5 44x DDR 2 13 T DDR DDR 12 52 conte x DDR_CSO 6 11 7 DDR 50 DDR 651 10 51 13 7 DDR CSt 13 5254 DDR 2 5V_DDR PLACE CLOSE TO 2507 1 PLACE CLOSE TO 2508 DDR MAS MAS 7 DDR MAS DOR MAS 13 DDRVREF DDRVREF 7 DDR_MA12 DDR MA12 13 o J505 o J506 7 DDR MAB 13 7 DDR MAS DDR MA9 13 t 1 1 2 _____ 7 DDR MA1 DDR MAT MA1 13 3 4 d 3 4 7 4 PDR 13 Jd ND 5 L6 Mp4 C148 C588 __ 8 L6 MD4 7 DDR DDR BAO BAO 13 IL 106 C130 7 m5 0 10 1000P 7 8 MDS 7 DDR DDR RASH RASK 13 04U 1000P 4 9 10 4 0603 0603 4 9 10 4 7 poe DDR 0603 0603 5050 11 12 DOMO 50V 4 5050 11 12 DOMO redes DDR MA2 50V MD2 13 14 MD2 13 14 7 DDR MA10 DDR 10 13 5 15 16 GND 7 1 16 4 2 DORMAN DDR MAO T cb 17 18 7 1 18 7 7 DDR BA1 DDR BA1 13 19 MD12 MDb8 49 MD12 7 DDR MAT DDR MATT 13 t 22 4 4 21 22 e 5 X DDR MAT 1155 23 24 MDIS 23 24 513 7 BORMAS DDR MAG 13 0051 DOMi 095 5 DAMT 21 7 fen
7. SCALE 0 200 7 Jun O MATERIAL SEE NOTES TREATMENT REMARK PI P2 aL 05 RAWING NAME LT PF GDI X6A 14 1 103 8575 EDS DRAWN DESIGNED CHECKED APPROVED ATERIAL No AD 4162671172006 R00 4510 4 E 0 6 0 6 liz 3 10 3 CONTENTS OF CHANGE MM DD YY International Corp C D E SHEET NO 2 OF 2 Mode name MAIN ASSY 8575 File name 551 1033 85750 PDF created with FinePrint pdfFactory trial version http www fineprint com ITEM PART DESCRIPTION Q TY REMARK 3446711600011 COVER HINGE 8175 rx 441671130005 LCD ASSY ODI XGA 14 1 104 8575 OPTION 340671100015 KEYBOARD COVER ASSY B 8575 531099990128 KBD OPTION 86 US 8175 OPTION 3446 11600010 COVER DUMMY 8175 411671200007 PCB QUICK KEY 8170 340671700001 COVER ASSY 8575 442164900010 TOUCH PAD MODULE 350 YS FH Co 422665400002 FFC ASSY TOUCH PAD CASE KIT VENUS 340671600028 BRACKET ASSY T P INSULATOR 8175 411671200006 PWA PWA 8170 T P BD 345671600018 GASKET HEATSINK K B PLATE 8175 345671700010 GASKET KB PLATE 8575 345671700011 GASKET
8. Wr romewwwmamam 8575 ID3 15 Description 176 8575 N B Maintenance 9 Spare Parts List 7 8575 IDA 14 Part Number 8575 IDA 14 Description Location s 177 8575 N B Maintenance 9 Spare Parts List 8 8575 IDA 14 Part Number 8575 ID4 15 Description Location s 178 8575 N B Maintenance 9 Spare Parts List 9 8575 104 15 Part Number 451671700032 I 242671700001 242600000088 242669900009 441671730001 451671730001 413000020265 416267173003 526267173005 561567176003 561567170001 561567170003 416267173902 461671600018 221671650001 221671650008 221671650005 221671650006 221671650004 221671650007 222668820001 Dwmawcwpnswow e a OO e panasna BAG ANTI STATIC 170x270MM ORC 8575 104 15 Description 179 8575
9. 125V IL 175 176 c188 C180 010 040 0603 0603 0603 0603 0603 0603 16V 16V 16V 16 16V lt 16 4 GND 125V 9 Lots Ic cies ciso 010 010 010 0603 0603 0603 0603 0603 16V 16V 16 16V 16V GND 125 9 44 254 4 4 9 1 190 1000 1000P 1000P 0603 0603 0603 H 4 i C193 C153 0155 C151 1000 1000 1000P 1000P NA 0603 0603 0603 0603 GND i i GND 7 0 0150 0603 GND 125V C154 1 c192 1 172 0 0150 0 0150 6 0150 0603 0603 0603 5 GND THESE DECOUPLING CAPACITOR SHOULD BE PLACE WITHIN 150 Mils OF 1 25V THERMINATION R PACKs Mitac gt Tite 8575 DDR TERMINATION Size Document C Number 411671700010 Bheet 13 29 ate Wednesday January 16 2002 1 SIS961 1 3 Mitac gt 8575 SIS961 1 3 TS 185 IDEAVDD L 1202 100 4 4 2012 C265 266 C257 G 01U 610 100 peL ADIO 0603 0603 1206 18 28 29 PCI AD 0 31 lt _ gt d 50V
10. USBCLK SB DC Power Board e a From 0508 clock generator L520 3V 43V USB5VC5 120Z 100M L523 ui ec p gt 3 5 120Z 100M 9 P27 J7 PJ2 P2 Bn gt USBVDD e e 9 R10 y USBOC3 10K gt 2 gt R7 525 C744 C745 L USBOC3 5 39 SK DA lu T USBOCS USBVSS a 77 J8 e e 1 R8 1 V T 1000 47K USB_OC0_1 L522 7 1 50 USRPs 600Z 100M USB OC3 54 1 2 003 5 48 LAA R147 USBPS 4 Ys 2 22 U14 USBP0_P USBP0 e 32 R513 R514 4 5 USBP0_N USBP0 ISK Joe e 34 GND MuTIOL C86 C87 R148 100P 22P 2 45V Media I O R75 USBSVCCS GND USB 22 3 5 Controller USBPI P b USBP1 x vine VOLTI L504 5 120Z 100M USBPl USBPI 28 4 01 vouto H 515961 158 C122 9 C509 100P 22P 22 u T i R2 C504 L 33K T V USBOC3 77 R142 JA 22 R4 USBP3 P USBP3 1 14 47K USBP3_N USBP3 1508 P3 600Z 100M C83 C84 R143 USBP3 100 22 22 1 VA AA J 2 2s USBP3 4 e Y NT 2 USBPS P USBP5 1 R503 R502 USBPS N USBPS 15K 15K 3 10501 126 125 R163 gt GND 100P 22P 22 GND_USB 159 8575 N B Maintenance 8 10 PIO Port Test Error When a print command is issued printer prints nothing or garbage PIO Port Test Error 1 Check if PIO device is installed properly 1504 Board level 2 Check CMOS LPT port setting pro
11. SEL coevseLA ep csroe L SERERE CADE ra x CADIS 14 17 2829 POL EVSEL Po DE DEVSEL CPAR NE EE Rm zn 0 14172820 PCI FRAMER FRAME CEERR oo mE 1 14 17 2829 PCLIRDY IRDY CSERR ane 4 oe CPAR 1 4 14472820 TRDY CREQ 70 sen N RENE n 41 DELOK 14172829 STOP IER 48 14 17 2829 PCI PAR PAR CINT 0605 ES 172829 POI_PERR PERR E E VEN 14 17 28 29 PCI_SERR SERR CCLKRUN 8 18 52 1417 PCI REQUE 18 5 cu 1447 PCLGNTOR GNT R2 02 aS E enm AUS 7 9 14 17 21 28 29 PCIRST RST mou 4 2 5 y EL CADTS 7 15 CARD PMER RI OUTHPME vst pd doe R249 4 111 as VCCA 0603 20 eve E 9805 20 CARDSPK CARDSPK SPKR_OUT 1 EE 10 Ac 1 2 50 CREQ 17212829 CLKRUNE Mit CAUDIO Au 28 80 LU 0 CSTSCHG VCCA R134 CAD25 28 62 AUDIO 47k CSTSCHG 1521 SERIRQ N10 0603 28 Di ME2 2 En CCBEi CAD29 31 65 CAD3U 8793 1 CCIBE1 R2 02 66 4447 PCLINTBR BAA MFO
12. gt EATSINK ASSY P4 CPU 8575 ELDING ASSY 8515 EAKER ASSY L 8575 ASSY R 8575 ELDING AUDIO 8575 E ASSY TOUCH PAD 8575 ASSY MDM 56K UNIV F PACK WO KIT E ASSY MDC EMI 8515 Y CARD PCMCIA TETRA D A Y 306 2 5 9 5MM ID3 8575 PWA PWA 8575 MOTHER BD DVD ASSY QUANTA 1D3 8575 T ASSY OPTION LI ION 2000mAH 8515 103 USING ASSY 103 8575 COVER ASSY DIMM 103 8575 BRACKET 8515 T HEATSINK K B PLATE 81IT5 PLATE 8575 BY Co PO mi 2 2 a 5 2 2 gt 2 2 GEMS IEL 207 28 ay 2 2 29 PP gt 252 222 07 Pa 2 2 ir PLATE 1 8515 T LCD HINGE 8175 ET MIC 85T15 MICROPHONE ASSY 81 75 SPC SCREW M3L6 NIB K HD 10 8 NYLOK SPC SCREW M2L3 NIW K HD 73 SPC SCREW M2 6L4 N IW K HD 120 6 SPC SCREW M2L3 0 N IW NLK HD07 SPC SCREW 4 K HD NIB NL SCREW A 8110 STANDOFF 4 40093 54515 5 NIW SCREW M2L15 FLTC NIW NLK SPC SCREW M2 6L3 NIB K HD NYLOK SPC SCREW M2 6L6 K HD NIB NLK SPC SCREW M2 6L8 K HD NIW NLK 345671100002 THERMAL PAD MOD 8515 346671120002 INSULATOR REAR SCREW 103 8575 340611200020 ASSY 8110
13. TP 1 12 i TERT i TOUCH PAD 4 HIROSE STIMAS 1 LEFT1 6 ar 4602 CRL_UPT DF13 8P 1 25V 27 SCRL DOWNT 8 d TP 1 1 HIROSE CONN DF13V 8 0 25A DATA 2 4 291000410801 L20 1202 100 1608 GLK DF13 4P 1 25V 1 4 DATA 1311 1202 100 _ 1608 420 s J501 22 T DATA 1331 1202100 1608 3 TP GNpt T SET i 3038 1036 1037 2038 4039 2040 Jost 1042 77 DF13B 8P 1 25V 5 8 TP_GND 7 T 3 J 5 i 5 ouo 1 m E C222 C228 C221 5 RIGHT ife 010 i t quies BAVoS nr 0603 0503 0603 1 RIGHT 1 12 4 EE 05 SCRL UP 3 TP GND1 01 22 1 SCRL DOWN 12VISOMA e at S 22 i STS 042 A 4 A 3 KIS 22 ad 4 5 fst 1 4 86206 0800 777 SW 1 T T P veer TP_GND 1 9 C RIGHT Teng 20056 LEFT 11 TC010 PSs11CET B T 1 SHE 287040105012 T2VI50MA SW STS 042A 128 STS 042 A Di 2043 04 FPCIFFC 12P 1MM i 3 CONN ELCO6239 12 547 3 6 SWi CONN ELCO6239 12A t 1 404 4 uie H 4 5 SCRL 177 qe 41 LEFT 5010 Fish ROM NS 42VIS0MA _6 1 12 50 1 1122 8000 515 042 06 TCO10 PSs11CET B T 500 1 i SW_STS 042A MTG29 501 14 3 297040105012 MTGIID2 20056 17 i 1 3 x 5 1 ti ui 25 505 19 5 SCRL R132 506 20 DOWN j US
14. 7 14 VINA TAAHC14 VINA D 0603 TSSOP14 TSSOP14 TSSOP14 mis BATT POWERE SCROLL m GND GND 08050 1200 22 NUM 22 P boo zm 1 2 0605 ET T BATT LED 5VA 2T 0603 mu LED j scnou 22 LED DATA 1 5 3 8B B CAP 10K NR 5 96 0603 POWER LED hae Eden BRE PONER gt POWER 27 ACPLED 22 LED gt aor BATT R 15 ACPILED Ka 1 DTCIA4TKA 3 4 rt 22 RESET RESET ador 5 BATES 27 1528 Pb ERU GND vec 14 TAHETA jo RER BATT POWERE WZ E 96 777 FH LCD 14 330mA 15 800mA oO RAS us Leovee J3 Lenvee 1202 100M 2012 F503mircoSMDC110 1 L504 1 1 2 oo pack 5 5 cLosk To NDS 4 a 8 4 10 _ 1 paaie TXCLK 5 16 TXCLK acre ae c2 650 cs10 tt 1 0803 0808 T 03 1308 125 Eon 43 14 10U_NA 9 paourte o 4 TX2OUTO 1 a TX2OUTI 50V 10V 12067 DU Tx20uT2 T 1 a 1 TXOUTO ases 19 0 9 3 TUE A 2 POUT s Res 9 TXOUT2 TXOUT2 25 26 TXOUTI 9 Close to LCD Connector 9 pou TROUT 2 2 POT pour 9 i 25 0 brousta 1 10 07 5 2 PELA pons 1100702 1 36 a 8 LENAVDD_ lt Tenavo
15. Pmcxpumumasmacu wm BWiEPEESNNUERA ANTE 8575 1 5 15 Description Location s 181 8575 N B Maintenance 9 Spare Parts List 12 8575 105 15 Part Number 340671600019 340671600017 340671700002 340671600039 340671740001 451671710001 346671700021 531099990133 531020237350 340671700014 451671700032 242671700001 242600000157 441671740001 451671740001 413000020265 416267174003 526267174002 561567170001 416267174902 461671600012 227671600003 224670830002 221671250002 221671250001 Wxswmrmam LCD ASSY SAMSUNG XGA 15 1 ID5 8 LCD KIT SAMSUNG XGA 15 1 ID5 qp LCD LT 150X3 124 TFT 15 LVDS XGA is LT PF SAMSUNG XGA 15 1 ID5 8575 DERE Pouymawrsumemm ooo 8575 105 15 Description ____ 182 8575 N B Maintenance 9 Spare Parts List 13 8575 ID2Z ID3 IDA ID5 Common Spare Parts Part Number 441999900205 442671200004 541667170032 346671700016
16. 858883385 COLKRUN p R222 a 6 E 0603 22222222 i 1 avs 39985585 4 0603 cat PCI4106GU IL c25 270 10 1 GND2 GND4 0603 J BGA144_0 8MM E R223 10 0 635 H5 68P H3 Cl640 0603 GND HIROSE C217 E d an EE DTCHAAWK 307 0603 0505 NCCENO VCCA 1110900 3 3 3 3 3VA VDDP1 1 413 13 E e 4 H t t 5 Avcca 12 7 52211 AVCCC 10 aver Coo ceos cesa ka 2 5 010 010 0 10 SSoP16 0603 0603 0603 0603 Je 4 4 5 C676 C662 679 C684 C694 010 0 10 gt 4 7UINA 1206 1206 777 50 50v 50 16 50 dev 1 1 4 7 7 Close to 52211 MiTAC ile 8575 PCI1410 amp CARDBUS SOCKET ize Document Number 411671700010 P MCIA NTROLLER ARDB KET 0A Date Wednesday January 16 2002 Bheet 29 1 3V LAN
17. 7 R511 S 5 56 Controller T Ap 52 H8 F3437 58 4 L L UA 22 T Signal HI LOW 22 cna 77 LID Normal Suspend 77 Inverter Board 146 8575 N B Maintenance 8 4 External Monitor No Display There is no display or picture abnormal on CRT monitor but it is OK for LCD External Monitor No Display 1 Confirm monitor is good and check the cable are connected properly Check if UA J2 are cold solder Board level 2 Try another known good monitor Troubleshooting Re soldering Display OK One of the following parts on the mother board may be defective use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement Replace Parts Signals Motherboard CRT REFCLKO CRT DDDA CRT HSYNC CRT VSYNC CRT DDCK Connect the I O device amp cable to the M B one at a time to find out which part is causing the CRT RED problem CRT GREEN CRT BLUE 147 8575 N B Maintenance 8 4 External Monitor No Display There is no display or picture abnormal on CRT monitor but it is OK for LCD T3VS 3VS _ R2 J2 3VS Pis c
18. c c MEL MASTER VCC_CORE i 5 t R508 R529 R526 R527 J504 t H i 150 gt 51 51 51 pt 2 4 HBMP1 0603 0603 0603 H 4 311 214 H DBA H BPM4 PRDY 1 2 _ _ H_BMP1_ITP 513 4 6 MASTER RESETE H BPM5 PREG n H BPMS PREQ 5 5 ra H EPMA PRDY 217 D TDi J TESTHIS 1 18 i H BPM4 PRDY it ITP TMS i TESTHIT 1 HBPMSPREQ 1214 IIP_TRST R509 6 7 H BMP1 ITP CPURSTIF 1 16 TCK LA LOSE T 27 17115 16 PLACE CL TOSS 0603 HERE sp i ITP TDI AT ITE GL 21 19 20722 H_PWR 11 244 22 22 oer 5 i _ 24 i NO i 18 1 Z7MMIHSINA TESTAT 21 Ta 5 f SPEED TP TRST t paws wee 8 ESTE 520 0100 24 Edd toe GS Ene euet ic oe o sg 1 1 LL ESMO 1 X ELI 18 1206 R534 680 0603 tp M ne PLACE CLOSE TO CPU SOCKET 777 says Close to CPU socket One 220PF for each GTL REF Pin HC EIN A AE 5 gt Bes UNS es Se PLACE AT CPU END 12 1 2 2 gLGTLREF2 3 AE ee CPU THERMDA 393 0603 2 7 f 1 id 1U 220P 220P 2 8 0603 0805 0603 0603 i 47UH 51 51
19. mw mom e ur P17 A7 2 KB OUT Key matrix scan output 7 ili m x mic 65 8575 N B Maintenance Continue to previous espere Definitions RESET RESET OFF ross or e To ew un fe sso x s oof us rem mae e mom Jo o olen o Kent o wem fo e oles o mus fo o olen 9 Kent kymmen fe fo olen o ss e me e we _ mwmoenr w mss io Kop mmm mum vo e ee ms r we 8575 N B Maintenance Continue to previous Name H8 Pin During After ON STANDBY Function Definitions RESET RESET OFF Port 4 TTL input voltage input high min 2V input low max 0 8V P40 TMCIO 49 H8 PWR ON T L LH Keep System power on need pull down to define initial state during reset P41 TMO0 H8 THRM Keep H Thermal throttling control to Southbridge P42 TMRIO 51 SCI Keep SCI output and Fan Speed Tachometer FAN SPD SW Switch 1 H8 SCI Need invert to SCI sending to SB FAN oo 5 gt 3 Fan 5 _ tachometer P44 TMCO1 PA TMCOUHIRQI 1 ISA ISAIRQU 1 Keep Keyboard IRQI IRQI
20. taw 7243 AV PC22 PC23 PC25 i PC26 010 0805 0805 oy m 0805 25V 0805 25V 4 25V 80 20 Puto 25V 80 20 lle 1112 voca H 1 3802061 2 E e 4 2 PVDD1 2 H 4 dU 16 At MS 16 i t 3 AGND1 AGND4 12 PRIO 2 80 Mio Ae 105 1 0 2 5V_DDR 4009 AGND2 AGND3 R539 1 10 GND PC30 1 0010 eve Ae 29 GND 50 100K 1000P 10 0603 gt 0603 0603D 1 5 GND av wre 10K 0603 V ND 518 745 PWROK PWROK 3 RLS4148 9507 0517 Ng 1 DTC144TKA 2227 SW_ 5VA SW RLS4148 R631 10K 0603 y GND 2527 ADINP GND 1505 BEAD 1202 100M 6A PF502 08050 TRISFT 10A FUSE 2917 14 25 1 107 2 1 a PL504 219 4 BEAD 1202 100M 6A 4lo PR564 08050 5VAS 301K 9803D 5VA RVA 7P 2 5MM PRIT SUYIN 250005MR07G100ZU div BAT 1 0608D BAT GND 4 PR563 2 22 BATT lt I 2 PD512 4 08080 06080 19 PR12 1 1 22 BAT C lt 0603 0805 4 06030 06030 4 4 1 BAV99 V GND GND PD513 GND 22 BAT DC 9 GND 5 nt OVMAIN PR553 100K M PUS12 PUS13 0603 SI4835DY SI4835DY PR548 5 508 508 100 0603 4 lt ___ 2227 PR55 a 33K 0603 EE a 509 D s I DTC144
21. 22K a BAT V s BAT VOLT U509 o V PRII e e e 38 S 4 99K 5 9 3 BAT_T BAT_TEMP 42 E R671 C707 22 68P PCI9 PRS63 L 582 cL L e 3 Controller T 20K 100K T on T R655 H8 F3437 C710 e eq ee TRO IM 2 V 5 X503 16MHZ 140 8575 N B Maintenance 8 2 No Display There is no display on both LCD and monitor after power on although the LCD and monitor is known good No Display Monitor or LCD module Replace monitor or LCD Board level i Troubleshooting Make sure that CPU module DIMM memory are installed Propel a Refer to port 378H met ttes Yes error code description section to find out error code to port which part is causing the problem 378H Motherboard No 1 Try another known good CPU module DIMM module and BIOS 2 Remove all of I O device FDD HDD CD ROM from motherboard except LCD or monitor Check system clock and reset circuit 1 Replace faulty part Display Yes 2 Connect I O device to the OK M B one at a time to find out To be continued which part is causing the problem Clock and reset checking No 141 VCC CORE 8 2 No Display 3VS Q517 MMBT3904L 3VS R664 Q516 MMBT3904L 575 N B Maintenance System Clock Check 3VS lt 3VS
22. Crystal Input External Reference Input A parallel resonant 14 31818 crystal 20 ppm should be attached between this pin and XO However an external CMOS compatible clock can drive the XI FIN input Crystal Output A parallel resonance 14 31818MHz crystal 20 ppm should be attached between this pin and XI FIN However if an external CMOS clock is attached to XI FIN XO should be left open P OUT Pixel Clock Output This pin provides a pixel clock signal to the VGA controller which can be used as a reference frequency The output is selectable between 1X and 2X of the pixel clock frequency The output driver is driven from the VDDV supply pin 60 This output has a programmable tri state The capacitive loading on this pin should be kept to a minimum VREFI Reference Voltage Input 1 The VREFI pin inputs a reference voltage of VDDV 2 The signal is derived externally through a resistor divider and decoupling capacitor and will be used as a reference level for data sync and clock inputs 68 73 77 82 In D1 11 0 Data1 11 through Data1 0 Inputs These pins accept the 12 data inputs from a digital video port of a graphics controller The levels are 0 to VDDV is the threshold level 76 74 In XCLKI XCLKI External Clock Inputs These inputs form a differential clock signal input to the device for use with the H1 V1 and D1 11
23. Bus Grant 1 5V 3 3V M AAD 31 0 IO AGP Address Data Bus 1 5V 3 3V M 109 8575 N B Maintenance 5 2 SiS650 IGUI Host Memory Controller SiS MuTIOL Interface Name Pin Attr Signal Description AC BE 3 0 VO AGP Command Byte Enable 1 5V 3 3V M APAR Parity 1 5V 3 3V M ST 2 0 Status Bus 1 5V 3 3V M PIPE I AGP Pipeline Request 1 5V 3 3V M SBA 7 0 IO Side Band Address 1 5V 3 3V M RBF I Read Buffer Full 1 5V 3 3V M WBF I Write Buffer Full 1 5V 3 3V M AD STB 1 0 AD Bus Strobe 1 5V 3 3V M AD STB 1 0 f I O AD Bus Strobe Compliment 1 5V 3 3V M SB STB I Side Band Strobe 1 5V 3 3V M SB STB4 I Side Band Strobe Compliment 1 5V 3 3V M Stereo Glasses Interface Name Pin Attr Signal Description CSYNC Stereo Clock 3 3V M RSYNC Stereo Right 3 3V M LSYNC Stereo Left 3 3V M VB Interface Name Pin Attr Signal Description VBCLK I Channel B A Clock Input 1 8V 3 3V M VBCLK multiplexed with SBAO VBHCLK VB Programming Interface Clock 1 8V 3 3V M multiplexed with RBF VBCAD Uo VB Programming Interface Data 1 8V 3 3V M VBCAD multiplexed with AREQ VBCTL 1 0 VB Data Control 1 8V 3 3V M VBCTI 1 0 multiplexed with AAD 29 28 VGPIO 3 2 vO VB GPIO pins 3 3V M VGPIO 3 2 multiplexed with PIPE WBF VBHSYNC VO Ch
24. 202 20503 E E OPENSMTA OPENSMTA 40507 sot 20504 1 2 1 2 OPEN SMT4 OPEN SMTA OPEN SMTA 2 OPENSMTA T P ile SYSTEM POWER 26 Document pa Number 411671700004 Date Monday January 14 2002 1 20504 2 ALWAYS 20503 t t vs t EY t OAWAYS 20514 1 1 EC31QS04 TE12L t DYMAIN2 D VMAIN 502010 1 4 202 100 2012 HDR ATOPX2 H8 49 2050 PC1 PC6 15 X 520 me PRORA MK J 2 pests 753300 27 3300 010 EN odu bow 2012 OPEN SMT4 i 287 mes 4 SHORT SMTA Eca TaSo4 TE12L Em 2 PUSO2 062010 200 51078200 PF501 08 NZ 202 5 ao 1 1 1 2 4 1 2
25. BGCLK 31 4 H_ADSTB O ADSTBO AD_STB1 VBGCLK BOCLKE 4 HAW 3 31 C 7 1 A AD_sTBi vBGCLK 21 POCE mE AGPCLK AGP CLIC VBGCLK 0603 HA29 pM AA gt VBGCLKK 9 HA28 Mi AGPRCOMP _ HNCVREF At AGPRCOMP XE Bo AGPAVDDi AGPAVDD1 AGPAVSS1 35 Hated Mo Acpvss1 A8 AGPAVSST _ 9 HAH23 AGPAVDD2 0401 22 AGPVDD2 0603 22 AGPvss2 8 __ M 20 AGPVREF R62 HAH 301 HAS AGPVSSREF 2 MS Iu A HA17 p DSTBN 0 3 4 AGPRCOMP 3o Halet DSTBN3 5 AGPVREF DSTEN2 604 1 12 DSTBNO ad 60 OHM 1 C56 R57 11 DSTBP3 E 200 m HA10R DSTBP2 E Lou DSTBP1 3vs CORE DSTBPOR 1507 R544 HAHG AGPAVDDi HNCOMP HAS 8 ince 1 A 2 HAHA 1202 100 GND s888 888588888888d 8d nd8583888888888888888885555555555885885 8858 5555 com UD ZIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIITIIIIIIIIIIIIIIII Sou 03 R20 q Jg 518650 lt 507 10 540 77 85 JL503 ow AGPAVSS 1 110 1 06030 JP NET20 112 OHM 1 GND DBI 0 3 1511 Tum HD 0 63 4 AGPAVDD2 in 69 lt 1202 100 J 2012 J C33 C28 C563
26. 55 DDR MEAT Aue MD38 SMD46 S3AUXSW S3AUXSW 15 22 74XAVSS 3 068 55 DDR Dama MD39 SMD14 004 DDR SDCLK SDRAMCLK 11 355 54 515650 DDR MD T MO40 SMD13 R614 22 FWDSDCLKO ni 33 7177 DOR Mb4Z 84 MD41 SMD43 FWosDcLko AD11 R814 1 22 gt FWDSDCLKO 11 Ewpspcino 1 1 2 4 DDR Mas AES MD42 SMD42 NZ DOR MD43 SMD10 sorok uS 944174821 2829 PCIRST DDE Minas 88 MDA4 SMDAA 0953 15 23 BBE AES MD45 SMD12 15 AUXOK PDT 4 GND DDR 47 AE4 MD46 SMD41 vi SDAVDD R554 DDR Dams AEH MD47 SMD9 SDAVDD 5 DDR Dass DQMSISMD11 2 SDAVSS 06030 DDR MD48 99509858 SbAVss C654 50V PWROK Pt DDR MD49 488 04 DLLEN DDR MD50 MDSOSMDST 0 10 0603 DDR MD51 ACS 50 9 0 7 DDRAVDD ____ 1 0667 1 50 AUXOK WZ DDR 52 AG GND DDR MD53 AGI MDS2 SMD39 2__ DDRAVSS 0603 AELH MD53 SMD7 DDRAVSS DDR 055 0545 06 7 DDR ADA DDR 0056 2 AJ19 DDRVREFA DDR MESS REZ 0086 586 DDRVREFA DORVREFB SEL MDSB MD58 SMD1 DRAM SEL DRAM SEL L506 E L505 DDR MD60 ACA Heec ee ECLKAVDD 54 4 DCLKAVDD yii DDR MD61 1 DDR MD62 MD61 SMD3 1202 100 1202 100 DDR MD63 act 2 2012 2012 NB
27. After IPCISRT During Tolerant PCISRT S1 Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined D Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined High Z High Z High Z High Z High Z High Z High Z High Z High Z Driven Defined Driven Defined p Driven Defined Driven Defina pr High Z riven Defined Driven Defined Driven Defined High Z High Z S3 Off Off Off Off Off Off Off High Z High Z High Z Driven De Driven De Driven De Driven De Driven De Driven De Driven De Driven De High Z High Z z 5 5 d lt G 5 amp Eh 5 5 d lt 5 Eh 5 5 H e e V e 19 d d d d d d d d lt lt g lt lt lt lt 5 S 19 Eh ch 5 5 5 5 5 5 5 High Z High Z High Z 9 5 a e e ge High Z High Z 8575 N B Maintenance 1 7 Appendix 2 H8 Pins Definitions The shadowed block is the selected function Name H8 Pin During After STANDBY Function Definitions RESET RESE
28. PWR JACK POWER DIAGRAM OF THE PROJECT 8575 xs 1 LEVEL SHIFT SUSC PSON 4173FEUT DTC 144WK SIS PWRBTN H8 SIS cow H8 AVREFl bass F3437 FY SI SI E pp 2301DS 2301DS y 2 me 4400 1 _ 5 412V T 12Vs PWROK 4 A04400 1632 me 4 3V 3VS A SI S PWR ON T M AX 6 5 0 A04400 809 6 CPU AUXOK Z IIT circuit VMAIN B SI T 4 LTC 4835DY 3707 42 5V DDR e p DEP Cake ew Foe Ban tty ENIM LO TIRES SS WI c Arona te ate RM C LEARNING 2N7002 SYSE MIC 4VCC CORE 5248 255 ex LTC 1 709EG L VCC_RTC RTC BAT VCC_RTC VCC_RTC BATOK yore dmi circuit ENDAR gt Te 8575 POWER BLOCK DIAGRAM Document 411671700010 Date Wednesday January 16 2002 1 Bheet 3 of
29. Signals Associated Strobe REQ A4 0 16 3 ADSTBO A 35 17 ADSTB1 BINIT Input Output BINIT Bus Initialization may be observed and driven by all processor system bus agents and if used must connect the appropriate pins of all such agents If the BINIT driver is enabled during power on configuration BINIT is asserted to signal any bus condition that prevents reliable future operation If BINIT observation is enabled during power on configuration and BINIT is sampled asserted symmetric agents reset their bus LOCK activity and bus request arbitration state machines The bus agents do not reset their IOQ and transaction tracking state machines upon observation of BINIT activation Once the BINIT assertion has been observed the bus agents will re arbitrate for the system bus and attempt completion of their bus queue and IOQ entries If BINIT observation is disabled during power on configuration a central agent may handle an assertion of BINIT as appropriate to the error handling architecture of the system BNR Input Output BNR Block Next Request is used to assert a bus stall by any bus agent who is unable to accept new bus transactions During a bus stall the current bus owner cannot issue any new transactions 102 8575 N B Maintenance 5 1 Intel Pentium 4 Processor mPGA478 Socket Name Type Description Name Type Description 5 0 I
30. later Wednesday January 16 2002 25 Bheet of 29 1 5 VCC CORE jJ qp gt 100 1000 SN 7343 63 63V PL502 1202 100 2012 VMAN 1 5 core in is p 1 1 J J PC508 m PC510 EN 26515 518 1202 100 514 012 PE Deo De 220 220 220 220 220 220 22UINA 0503 0603 0603 0603 1812 1812 1812 1812 1812 1812 1812 25V 25V 25V 25V 25V 25V 25V SV 90 N SN 20 20 20 20 20 20 20 4 4 4 GND PR510 H PWRGD 1 7 H_PWRGD 2 AA REIT J 0603 PC516 100K 10 PD504 19 1000P wpecurs2 501 D PU502 U503 0603 r1 IRF7811A IRF7811A IRF7811A NA 525 526 50 508 5 508 08 0 022U 0 10 7 Dhi 2
31. 99 R159 i PLP9216S 4 470PINA 0603 e Ies 1526 2 TPA0202 TSSOP24 0102 0603 AGND 1 AGND 6002 100MINA 1527 AGND Re 4 1608 1 1608 6002700MNA 77 uie AGND W603 1552 CB06 734 im 100K 12020100 21 2 4 1 2 10 010 603 2 DEVICE DECT 1608 0603 nal HI Low 1 Te 220 ATOPINA 0603 50 0 DTC144TKA 8575 AUDIO CODEC amp AUDIO 0805 10K GENS 80 20 0603 SPK OFF ShutDown Normal E 1 Rev 777 uston ROME 444671700010 OA AGND Date Wednesday January 16 2002 20 2 5 4 3 2 1
32. Di 1 D4 SCLK 1394 NGS nos OSC25MHO i R247 0241 12 55 Dd Nos NC36 OSC25MHO 15 _ 4 USBPA N D3 41 17 06 D6 Bia 5 i PLACE UNDER 961 SOLDER SIDE WIE 28 USBPA i 12 66 05 Bis noas 10 22 06030 4 i 00 NC9 D19 x T 1 ge p GND Sel USBREFAVDD ree ues 0603 0603 BGA335 36 t i q 5 lt 10 i 0603 2 04U 1 1 4 0603D 0 SCLK 1394 31 1 C127 C128 C824 1 2 0404 cao cr d eam GND 1 1 10U NA 06030 1 51 1 1206 2 040 06030 lo eed 10 06030 C758 1 010 4 TK 8INA 1206 2 0 0 06030 06030 i 2 04U GND JP NET20 i 0603D A GND 1 762 9 R764 9 L539 GND 1 m IVDD AUX USBPVDD imm 4 9512 1202 100 3 6 1 d 2012 J VCC CORE T 1 2 Nb our 1 27 C828 LL ceso m f L 3 EN 4 T 100 O 01U NA 0 1U NA 27 i 2 0 0 1206 0603 1206 1 4 2 010 A AMEBSOTMEEV tov 50V lt tov 06030 50125 154 1 040 4 USBPVSS 1 06030 C756 lt i 001 n mu JP NET20 JP NET20 i GND 80 20 GND GND 3V Nm VIAM ee ed 9 3V 8182 4 ACS7 SDOUT R169 1 Default AC97_SDOUT 15 19 20 AURA R179 1 SB SPKR SB 1520 3 0603 d SB SPKR LPC addr mapping
33. PLATE 1 8515 343611600006 B 8115 gt r 340671100016 HEATSINK ASSY P4 8515 345611600016 LCD HINGE 8175 DO gt I 2 gt 340671100007 ELDING ASSY 8575 9 340671100 ASSY L 8575 21 1341671100 ELDING AUDIO 8575 22 14216171100 E ASSY MDC EMI 8575 23 1421671100 ASSY TOUCHPAD 8515 3 SPEA 20 1340671100008 SPEAKER ASSY R 8515 I SHIE 4 WIRE WIRE 2 THER 24 345611700 AL PAD MOS 8515 8 RE B 25 1412155600041 ASSY MDM 56K UNTV F PACK WO KIT lt 0 x gt 1 26 1344671600043 Y 8115 21 523461110009 HDD ASSY 306 2 5 9 5 8575 OPTION 28 1411671700010 PWA PWA 8575 MOTHER BD 29 523467160014 DVD ROM ASSY 8X SDR O81 QUANTA 8175 OPTION 30 441999900062 BATT ASSY OPTION LI 9 CELL 8575 OPTION 3 340671700002 HOUSING ASSY 8575 COVER ASSY DIMM 8175 SPC SCREW M3L6 K HD t0 8 NYLOK PC SCREW M2L3 K HD I NIB PC SCREW M2L3 0 N IW NLK HD PC SCREW M2 6L4 K HD 10 8 N IB NLK 0 PC SCREW M2L4 K HD t 1 1 TANDOFF 4 40DP3 5H515 5 00 C 20 EW M2LIS FLTCE NIW NLK PC SCREW M2 6L6 K HD NIB NL PC SCREW
34. osos 1208 os 1 50V 16V 50V ume gt pm 142829 PCLINTOR Em REQM 14 x i1 PEREGE 1428 PCI 14 41 PCLINTDE 57 14 18 u POLINTDE 1428 PCCREQO 1448 8 2K t 1206 1 R190 1 PLACE CLOSE TO CDROM CONNECTOR 1 2 CLKRUN 18 21 2829 mM LS 8 2K WIS716 1242 16 mils 0908 45 8 Se Fg Boa td Cpt Shia ina me a Cah 1 4 COMM CDROM LEFT CDROM EFT 20 RIGHT T d ME CDROM RIGHT 20 3VS 47K 10K J12 0603 soo on oxo 1m 2 304 RPS30 1 8 IDE RST 513 re 8008 SD5 1206 SDD7 5 6 5009 E 1 E HIE E 307 i SDDS 418091 S00 3 5924 hh ra 55672 501 1206 1 5003 1 15 16 HE 50013 502 3 6 5002 17 18 50014 503 4 5 SDDT 19 17 45 20 50015 5000 21 9 gt SDDREG 23 21 SDIOR SAO RP532 1 B 4 7 4 25 2 SDDACK PR SAT 3206 i SIORDY 1 5 SDAZ 1 8 M 2 i 5 TRIE T 21 22 SA2 nat i 217 saa SA4 i j SDAD A 2 SM SAS 1206 SOCSTE 55 Lb SA6 3 6 37 5VS CD BAB SAT 4 5 39 t 1 1 21 SAT LA tans se to IDE Connectoi 451i 4 SA12 RPS34 1 ATKA 2 a 1 13 21 SAIS 1 CABLE SEL 4145 Bd 21 genie 3 8 018 pG1102W 1 4 470 21
35. vss vss vss vss 555 vss vss vss 555 vss vss 555 vss 155 VS 48 vss vss 155 Vss vss vss vss 555 555 vss 555 555 vss vss 555 vss vss vss vss vss vss vss vss ss vss vss vss 555 VS VS VS VS VS vss vss 48 WMTATB NWD 14 Place these caps at CPU solder side NUS hogy Lea Le 1206 1206 1206 1206 1206 C511 C11 C555 1500_ 1500 E 10V 10V 10V 10v 10V 22U 22U 22U 22 73437 7343 1210 1210 1210 1210 10V 10V 4 4 1 4 1 VCC CORE 71 71 csao 71 2 cs4s es T oes T es T ewe J osos J osos osos ws 777 Place these caps at P EHI inde Ap quer CPU north side 00 CORE 4 Place these caps at i CPU south side 4VCC CORE 1 C541 C533 D Ales dle lee aise 100 T 100 10U 100 gt 100 1 c5 C553 C542 C539 C534 t i es iul c NICE TED TE f i 10V y 10V 10V y 10V 10V ii N PG 4
36. 1 7 27 SIS961 1 3 14 5 or or Quo 5 SIS961 3 3 16 s J IDE INETRFACE amp PULL UPs 17 oem Does 25 25 1410 amp CARDBUS SOCKET 18 LAN PHY ICS 1893 amp MDC 19 AUDIO CODEC amp ABDIQAME 20 POWER STATES IDSEL BUS MASTER amp BUTTON STATE n REQU GNTS MICROCONTROLLER H8 22 SIGNAT VOTAGE FULL ON STR STD MEC OFF REMARK 21 END 1 1 1394 uD72872 SUSB 2 HIGH LOW LOW LOW BD URD Hur 1 25 POWER CM8500 amp BAT CON 23 pee LL LL E 1 8V 2 5V POWER LTC3707 24 ae EI R PCIINT CHARGER TL594C 25 BATTERY 12V PCIINT CHIP CPU POWER LTC1709EG 7 26 RTE 5 PCT TATO CORE 1 75 X X INTC 1394 uPD72872 D D CONNECTOR amp MISC 27 x 7 INTD MINIPCI MINI PCI amp BLUETOOTH 28 1 0 x x T 2 IEEE1394 uPD72872 29 0 x 3VS 3 3 X X X 2 3V 3 3 X X sl 3VA 3 3V 0 5VS 5V X X X DRAW DESIGN CHECK ISSUED 35g B x 5VA 5V 0 0 12VS 12V X X X 12V 12V X X gt 8575 COVER SHEET amp SCREW HOLE C Number 411671700010 0A Date Wednesday January 16 2002 Sheet T of 29 8 575 8575N System Block Diagram MINIPCI Socket 1394 CONTROLLE
37. 10 SPKLOUT Y SUR YORE 528 RI DECT HP OPT m U16 Lais aka eF Wo MIS 600Z 100M J23 erac m 159 last page 47K R168 AOUT_L 100K 5V_AMP e 14 a DEVICE DECT R713 RI Q523 16 HP LINE R762 10K DTCIA44TKA J24 5 47K DECT_HP OPT DEVICE_DECT zr Amplifier LINE OUT 45V 5V AMP pe p 5 127 L529 Y P 2 7 18 LVDD RVDD R714 3 22 z 2 Y Y 2 C245 C284 C247 V 100 280 1 100p R194 L C791 R174 L C789 77 77 100P IK 100P L534 600Z 100M 5 Lup IN e L28 4 L536 SPDIFOUT 600Z 100M ED IE IN 120Z 100M rr S EDNEIN From last page 1 Drive C805 R73 R721 ICAGND AGND 8 22 10K 20K 9 IC 3VS SPD 0 1 Fo C806 R734 R722 Vis 22u 10K 10K L552 L530 2 T e e 120Z 100M 164 8575 N B Maintenance 8 12 LAN Test Error An error occurs when a LAN device is installed 1 Check if the driver is installed properly 2 Check if the notebook connect with the LAN properly Yes Correct it Check if BIOS setup 15 ok Yes Re test Correct it OK Board level Troubleshooting Replace Motherboard Check the following parts for cold solder or one of the following parts on the mother board may be defective use an oscilloscope to check the following signal or replace the parts one at a time and test after each repla
38. 35 8575 N B Maintenance The LPS input is considered inactive if it remains low for more than 2 6 us and is considered active otherwise When the TSBA1ABI detects that LPS is inactive it places the PHY LLC interface into a low power reset state in which the CTL and D outputs are held in the logic zero state and the LREQ input is ignored however the SYSCLK output remains active If the LPS input remains low for more than 26 us the PHY LLC interface is put into a low power disabled state in which the SYSCLK output is also held inactive The PHY LLC interface is also held in the disabled state during hardware reset The TSB41AB1 continues the necessary repeater functions required for normal network operation regardless of the state of the PHY LLC interface When the interface is in the reset or disabled state and LPS is again observed active the PHY initializes the interface and returns it to normal operation When the PHY LLC interface is in the low power disabled state the TSB41AB1 automatically enters a low power mode if the port is inactive disconnected disabled or suspended In this low power mode the TSB41AB1 disables its internal clock generators and also disables various voltage and current reference circuits depending on the state of the port some reference circuitry must remain active in order to detect new cable connections disconnections or incoming TPBIAS for example The lowest power consumption the ultralow power slee
39. 8 R835 C888 m 1 zt ig zn ex a gyn Log ap 1 66 3 5 AINE DAC 2K 0603 10 0603 7 0603 0603 1206 JL534 6 VBD O 11 61 DGND3 vswine 38 4_ lt Sw 2 5 FC VBD1 69 010 Ere 34 1 TXOUTO d 20 VBD2 2110 33 TXOUTON 10 VBD3 1 1069 7 2 sLVDD3 NZ NA R601 4 FC VBD4 2 5 pat TOUTT E DVDD v FC VBDS 75 011 Hig 015 10 1 6 xciKa LGND4 28 XUI 6 VBGCLK 5 DGND2 LDC2 TXOUT2 10 BO STIRS te a er eee esi ep FC VBD6 NE Dam wea Ree opek 10 T 0603 09 go 0118 TXCUK AD 1 2 __ J J FC 81 019 1 Eres LENT 5 8 D C652 C656 C660 i VBD11 82 pno Sis30 LV 10 3 48542 1 2 0 LPLL_VDD 9 100 010 0 10 063 0603 317552 1 60 T at 220 Chrontel CH7019 i Td s 25V FC VADO 8 2 TX20UTO 1202100 i r FC VAD1 0201 m TX20UTO TOOT 10 010 202 CLOSE TO CH7017 FC VAD2 8 021 0603 0603 1206 JL540 EIL FC VADO pal LDCS EM TX20UT1 10 SOV 25 BOY 25 FC VAD4 89 m nea 2 1 20 R02 1 A A p20 FC VADS 90 02141 DD 0603 91 025 pont TX20UT2 LOND1 8h xcu LDCS IRE TX20UT2 10 L510 ud 6 VAGCLKE 82 1066 TX20UT2 10 s LVDDO A i0
40. 2FH LPC ADO 5858 52 LPDO Te oNDi 7 aS LADO 82 FID LAD1 PDI TRKOR 48 2 LAD2 2 8 J 5 Pim 8575N T P BRD PDA DSKCHOR ners 11 CLK_LPC33 CLK PDSIMSENO 44 LU i 20K 7 914 170 2820 PCIRST URESET POGDRATEO 4 E LEDS 15 LPC_FRAME LFRAME PDTIMSEN1 15 LPC_DRO i LDROR 0 0 0 0 0 02 02 2242224 2 02 02 2434 44 0 2 02 1 PNFXRDY 38 DIT 17482829 CLKRUN E 15 CLKRUN GPIO36 SLOTWGATE 26 FPE P 27 E 15 18 SERIRQ RED 10 SERIRQ PEMWDATA SZ PBUSY PE 27 SMIH GPIO35 BUSY_WAIT MTR1 40 BUSY 27 RIT Sio ACKWDRIR 4 FESUN 27 Took 1 sio CLKIN 47 TIONI 27 0603 INIT DIR PERR Pt erremosene 51 TER LEER 27 ays gys vs sw503 21 AFD _DSTRB DENSEL 8 STE P AFD 27 ie ross STBA WRITER Sm 1727 4 3 2 X24 RDATAR 2 R152 2 R677 25 55 COM1DCD 10K 10K NA 10K 26 DCDIi 56 OMTDSR 0603 0603 0603 HDS402 Dem 57 COMIRXD 2 E xenro SW_HDS402 28 FEE COMIRTS COMITXD AE I EE 28 pni SOUTI XCNFO Lg e MS MTROR DTRI _BOUTI BADDR OMPR 4507 X 32 INDEX Ritt 82 SMR e COMIDCD if at eae XCNEL IRIX 4 GND IRRX1 COMTTXD 514 17 sao XAQ GPIO20 IRRX2 IRSLO FIRSEL 27 aes 5
41. GND 0 1 1 0603 2 7002 5 LL OVP 22 CHARGING 0603 196 SOT23 FET 50 4 PR544 PQ507 2 47K 2N7002 NDC7002N f 50128 rer L1 NA hs 3 DIVADJ 1 aN s n a vast 22 4 H PUS11 PC571 26573 _ PR545 PC569 8 0010 NA 150P 1M n rai e 0603 0603 0603 06038 1E GND 50V L1 1 10 UTAR CT Ed amp pil 1 13 OUTPUTCTRL 4 112 DIVADJ2 22 F REF FEEDBACK 1 2IN 11N 2 15 2 H J 15946 __ 574 5016 4 4 GND 010 NA PC568 06038 575 PR541 1000 PR540 PRG PR5 50V 0 01U 100K_ 7 0603B 10K 4 a 1M 1 50 10 0603B 109 X7R 06038 0603 0603 i 2 1 PR550 PR549 4 0603 0603 0603 PR542 4 je 4 4 4 4 Law 196 1 570 1 1 0 02 REF 1 Iu 4 2512 NZ PC572 PR543 GND 1 BATTGND 99 PR547 2 49K 50 vo 249K 0603 JO507 06038 s 0603 196 20 1 PR546 oPEN SMT2 lt V7 10506 OPEN SMT2 4 181 4 4 2 4 SHORT SMT3 VMAIN CHARGE 22 o 5VAS o PR561 4 7K 0603 PR556 681K PR559 4 0603 VADJ 2 P VADJ 1 P BAT TYPE NIMH CELL 0510 SOT23N Bocas 5 5 125 5 12 307 0 0 0 0 gt DEAD 22 Lo dp E 12 40V 0 1 0 0 gt LMV393M SSOP8 12 50V 1 0 0 0 4 12 60V 1 1 0 0 PR5S7 100K NEA 0603 GND SUV LI 9 68V GND Mitac gt Title 8575 CHARGER LT594C Bie Document audi C Number 411671700010 0A
42. Input TRDY Target Ready is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer TRDY must connect the appropriate pins of all system bus agents TRST Input TRST Test Reset resets the Test Access Port TAP logic TRST must be driven low during power on Reset This can be done with a 680 pull down resistor VCCA Input VCCA provides isolated power for the internal processor core PLLs Refer to the Intel Pentium 4 Processor in the 478 pin Package and Intel 850 Chipset Platform Design Guide for complete implementation details TCK Input TCK Test Clock provides the clock input for the processor Test Bus also knownas the Test Access Port 106 5 1 Intel Pentium 4 Processor mPGA478 Socket 8575 N B Maintenance Name Type Description Input provides isolated power for internal processor system bus PLLs Follow he guidelines for Vcca and refer to the Intel Pentium 4 Processor in the 478 pin Package and Intel amp 850 Chipset Platform Design Guide for complete implementation details VCCSENSE Output 15 an isolated low impedance connection to processor core power VCC It can be used to sense or measure power near the silicon with little noise VCCVID Input There is no imput voltage requirement for VCCVID for designs intended tosupport only
43. The ICS1893 Media Dependent Interface MDI can be configured to provide either half or full duplex operation at data rates of 10 MHz or 100 MHz The MDI configuration can be established manually with input pins or control register settings or automatically using the Auto Negotiation features When the ICS1893 Auto Negotiation sublayer is enabled it exchanges technology capability data with its remote link partner and automatically selects the highest performance operating mode they have in common Features Supports category 5 cables with attenuation in excess of 24 dB at 100 MHz across a temperature range from 5 to 85 C DSP based baseline wander correction to virtually eliminate killer packets across temperature range from 5 to 85 C Low power 0 35 micron CMOS typically 400 mW Single 3 3 V power supply 51 8575 N B Maintenance Single chip fully integrated PHY provides PCS PMA PMD and AUTONEG sublayers of IEEE standard 10Base T and 100Base TX IEEE 802 3 compliant Fully integrated DSP based PMD includes Adaptive equalization and baseline wander correction e Transmit wave shaping and stream cipher scrambler MLT 3 encoder and NRZ NRZI encoder Highly configurable design supports Node repeater and switch applications 10M or 100M half and full duplex modes Managed and unmanaged applications Parallel detection Auto negotiation with Next Page capabilitie
44. UM 4 LAE 21 IRSL1 67 27 17 2 SA2 XA2IGPIO22 IRSL3 PWUREG 98 7 8 17 SA3 XA3 GPIO23 SD 7 1722 8 XAA IGPIO24 XSTBO 9 XASIXSTB 1 XCNF2 XDOIGPIOO0IJOYABTN1 3 300 300 31 2 A SA4 17 10 110 1722 XAGIGPIO2S PRIQA XSTB24 XD1 GPIO01 JOYBBTN1 2 ES 44 5 EH SAS 17 Hin 1722 IRQ12 XATIGPIO27 PIROB XD2IGPIOO2OYAY izy 585 252 1102 2 6 ER 17 Lg XABIGPIOSO PIRQC xD3 GPIO03 JOYBY 1 10 35i ES Tbn EM SAT 17 22 FAN_SPDO t XAQ GPIO31 MTR1 PIROD xD4 GPIO04 JOYBx 88 585 EH Sp ER SAB 17 1722 IOR XA10 GPIO32 XIORD MDRX 5 9 E 556 Mo 0516 EAN SA9 17 1722 10W XA11 GPIO33 XIOWR MDTX XD6 GPIO06 JOYBBTNO 92 E E 06 18 Sa 10 17 17 XA12 GPIO10 JOYABTN1 RI2 XDTIGPIOO7IJOYABTNO SAM 17 17 SA13 XA13 GPIO11 JOYBBTN1 DTR2 _BOUT2 AB 4 17 5 14 XA14 GPIO12 JOYAYICTS2 XWR IXCNF1 E 19 voc He 3VS 17 SA15 XA15 GPIO13 JOYBY SOUT2 XRDHGPIOAWDOR 5 MEME MEMR 17 G 17 XAM6 GPIO14JOYBXIRTS2 XIOWRHXCS1HIMTRI DRATEO 7 MCCS 17 22 d ons 17 SAT XAITIGPIO15 JOYAXISINZ XIORD GPIOSTIIRSLIDR1 ROMCS eus 17 XA18 GPIO16 JOYBETNO DSR2 XCSOHDR1HKDRYIGPIO2S ROMCS 22 4 PUN 17 SAT XA19 DCD2 JOYABTNOIGPION7 pes sov 8292 10K 282574373004 0603DA 2829 0603 savs 284587393002 77 POFP100 0 5MM Te 8575 SUPER
45. 1 RM3 1 06030 SHORT SMT4 rh NM24C02N 0 508 0603 1 PLP3216S NA 1 1394 GND 777 CHOKE_PLP3216S_1 0603 8197 1 s a STATS Mitac 22 cb 1 TPA R198 1 0 0603 8575 IEEE 1394 uPD72872 Size lev Document C Number 411671700010 d later Bheet 29 Wednesday January 16 2002 1 8575 8575N DD BOARD ROA SYSTEM POWER 43V 5V 12V PL504 120200 2012 DVMAIN Iam T PLSOS 1202 100 M PCT 2012 2 _ 7 Pcsos 100 100 4000P 40U NA pRsi7 ww 995 1K 10 25V J 0603 20 PR518 1 100K pu2 0603 GND St416DY d 508 oND 4 pasoz 207002 4 50129 FET 5 Kp pesos 2 PWR ON Ks 2 7002 1 1 50128 1777 PL2 PRA 100 0015 E 0124 2512 PRS 4 pes A 1 32 4K pce 5 pus 0603 1000P NA PC10 0010 0603
46. 4 BG18 4 1000 to0u 59870 pesas 0603 4 734 S 7343 FBi8V PR530 1M GND 10 1 63 63V 50 1210 11K 0603 1 2 EC10QS04 NA SENSE3 4 10 0603 1 1000 PD506 INTVCC1 1 AA 25V PR570 easa SENSE3 i Cl pcs22 PRET 0603 0 PRS07 1000P NA 1 2 10 PUS10 0603 10K 0603 1 1 0603 2 7K 0603 SENSE3 RUNS E i 18 3 SENSE1 swi H Ti 2 VOSENSE1 1 28 1 4 FREQSET VIN poses NA Sov 4 FCB 5 eMe E 550 GND 0603 1 412 8 21 oU PR532 15K 0603 1 Walt INTVCC 20 0603 PC563220P 0603 10 2 PGND 49 50V 1 1 41 502 18 L pcssa PR528 15K 0603 1 T 12 THe BOOST2 1 o4U 4 10 PD507 GND 9 33 NA 50 11 PCS56 13 542 18 0603 12 PC549 70603 1 220P 14 SENSE2 TG2 4 lt 50 16V BAS32L 1000P 9005 SENSE2 RUN SS2 E 0605 10 LTC3707 gt 10 561 28 pend 1112 TG25 4 25510 PR529 GND 1000P 1 25V 0603 SUSC 1522 0 qq 10 BAS32L 0603 562 71 PL4 PR525 0 0220 SW2 5 iv 2 2542 1 j25V P 4 A A2 2 x x o 25V 10UH 10 D124C 2512 4 INTVCCI 1 4 PR526 PC558 dd 21 5K 1000PNA 0603 0603 I 26543 5 PUB 1 4 21 100 S4810DY 1206 508 e 16 8625 J Poseo Pcss2 pcs47 posea PD2 100U NA 100U _ 1000 5 7343 7343 SN 7343 Ecosu T 637 d O T 144 7 2852
47. Break Before Make Switching PC Card is a trademark of PCMCIA Personal Computer Memory Card International Association LinBiCMO is a trademark of Texas Instruments 30 8575 N B Maintenance 1 2 6 TSBA1ABI IEEE 1394a One Port Cable Transceiver Arbiter The TSBA1ABI provides the digital and analog transceiver functions needed to implement a one port node in a cable based IEEE 1394 network The cable port incorporates one differential line transceiver The transceiver includes circuitry to monitor the line conditions as needed for determining connection status for initialization and arbitration and for packet reception and transmission The TSBA1ABI is designed to interface with a link layer controller LLC such as the TSBI2LV21 TSB12LV22 TSB12LV23 TSBI2LV26 TSB12LV31 TSB12LV41 TSB12LV42 TSBI2LVOIA The TSBA1ABI requires only an external 24 576 MHz crystal as a reference An external clock may be provided instead of a crystal An internal oscillator drives an internal phase locked loop PLL which generates the required 393 216 MHz reference signal This reference signal is internally divided to provide the clock signals used to control transmission of the outbound encoded strobe and data information A 49 152 MHz clock signal is supplied to the associated LLC for synchronization of the two chips and is used for resynchronization of the received data The power down PD function when enabled by asserting the PD terminal hi
48. DBSY Data Bus Busy is asserted by the agent responsible for driving data on the processor system bus to indicate that the data bus is in use The data bus isreleased after DBSY is deasserted This signal must connect the appropriate pins on all processor system bus agents HIT HITM Input Output Input Output HIT Snoop Hit and HITM Hit Modified convey transaction snoop operation results Any system bus agent may assert both HIT and HITM together to indicate that it requires a snoop stall which can be continued by reasserting HIT and HITM together DEFER Input DEFER is asserted by an agent to indicate that a transaction cannot be guaranteed in order completion Assertion of DEFER is normally the responsibility of the addressed memory or Input Output agent This signal must connect the appropriate pins of all processor system bus agents DP 3 0 Input Output DP 3 0 Data parity provide parity protection for the D 63 0 signals They are driven by the agent responsible for driving D 63 0 and must connect the appropriate pins of all Pentium 4 processor in the 478 pin package system bus gents IERR Output IERR Internal Error is asserted by a processor as the result of an internal error Assertion of IERR is usually accompanied by a SHUTDOWN transaction on the processor system bus This transaction may optionally be converted to an external error signal e g NMI by
49. DDR CASE 12 ZAD7 SD DDR MESS MD22 SMD51 DDR WER 12 2 08 EI ESNE DDR MD23 5MD50 ZAD9 RSYNC DDR DOSZ DQM2 SMD52 ZAD10 tsync DDR IB 0052 5 2 2 011 DDR 025 cs j DDR CSOK 12 ZAD13 VCOMP DDR 026 X D14 VRSET DOE RON A3 HAEL DDR CS1 12 DOR 2 014 TERDA 13 MD27 SDQM6 DDR CS24 12 ZAD15 wewn E14 WBWN DDR 29 MD20 SMD48 csa Aolo p 00 0980 12 AREE DACAVDp1 12 DACAVDDI DDR MD30 ADi3 C12 DACAVSST DOR ENST ADL BBL 1 0 Tesi ER 3 DACAVSS1 DDR DOMS MO31 SDQM2 ZCMP VDDZCMP C13 2 DDR 0053 DOMS SMD 16 ZCMP_P ZCMP N DACAVDD2 C14 DACAVSSZ DOR ALU 0053 5834 ZCMP P DACAVSS2 10 MD32 SDAM5 4B2 CKEO 12 AEAT VSszCMP ESTE DOM HLO MD33 SDAM4 1 12 du DolkavDD 818 DOE OU MD34 SMD47 CKE2 12 1206 dug DCLKAVss 18 DCLKAVSS DB MD35 SMD45 Y amp 12 HXAVSS W2 170xavss ag DDR 036 610 gaa B14 ECLKAVDD 910 MD36 SDQMI 445 1 0 TP510 GU xx 999 ECLKAVDD RER EHe MDST SDQMO 5 12 O 509 596 PPP 20
50. Description Location s 504 U e Nn eo 52 z Q o gt 62 s J N Oo e DR e e z Q gt A NS ac gt o gt 62 gt gt gt w 6 ojo sls s s ge alale mig olo den gb EI 5 5 S olt Z ro 2 o gt 3 D o ae z J DM 62 DM d 2m 5 55 eol Jg o NDUCTOR 10UH CDRH127 SUMIDA SMT NDUCTOR 10UH CDRH127 SUMIDA SMT NDUCTOR 10UH CDRH127B SUMIDA SM DUCTOR 10UH D124C 20 TOKO DUCTOR 3 3uH 3A CSS054D SMT DUCTOR 33uH CDRH124 SMT NDUCTOR 4 7UH 10 2012 SMT JLATOR MDC 8170 JLATOR AL FOIL M B BOTTOM 857 JLATOR CD ROM M B 8575 JLATOR INVERTER 7170 JLATOR INVERTER PCB 8175 LATOR MINIPCI 8575 LATOR PCMCIA 8175 10 10 BLANK COMMON E gt z o z z o z ET 21212 misc x lt Eb ow N olo 5 5 0511 ce wee C ct PL2 PL4 PL3 PL3
51. ea em eerte enter row fo em 9 xan reme men 7 9 T Dmm wes o eem e Dee e fo pee ume man 67 8575 N B Maintenance Continue to previous Name H8 Pin During After ON STANDBY Function Definitions RESET RESET OFF Port 6 Schmitt trigger input voltage min 1 0V max 3 5V P60 KEYIN P61 KEYIN P62 KEYIN2 FTIA KEY IN2 P63 KEYIN x wm rf T E pes rmn m perm 0 p em p h pes __ 3 FTIB 29 KEYIN3 Key matrix input 3 need pull high P64 KEYIN4 FTIC KEY IN4 Kep Key matrix input 4 need pull high P65 KEYIN 5 FTID KEY INS Sao l Keep Key matrix input 5 need pull high P66 KEYIN6 IRQ6 KEY IN6 Key matrix input 6 need pull high P67 KEYIN Port 7 TTL input voltage input high min 2V input low max 0 8V P70 ANO P73 AN3 hrpac een eror P73 AN PIAN 2 1 a fe veces m Je erama fe TEMPI BAT TEMP2 e battery and 98 NiMH battery a o o o o Charge I_CTR BL ADJ 68
52. mina 454 MD7 SMD28 DORNAD 12 12 41 ZcLKO DDR DOS 022 DQMO SMD61 mE vosci REFCLKO 11 22 12 14 ZUREQ DDR 21 0050 580 DDR MAZ ut DDR MDS MD8 SMD27 AG DDR 14 ZDREQ ZDREQ DDR MD10 MD10SMDSS Maa ADi2 DDR MA4 14 ZSTBO ZSTBO rout CRT RED 10 DDR MD AE19 MD11 SMD23 Mas HAHI DDR MAS 14 ZSTBOR ZSTBO 818 CRT GREEN 10 CUR AE21 MD12 SMD26 15 Bout CRT BLUE 10 DDR MD13 20 MD13 SMD57 DDR MAT 14 ZSTBi ZSTB DDR 19_ MD14 SMD56 HEIS DOR 14 ZSTBI 251818 HsYNc 12 8546 1_ A A 2 33 CRT HSYNC 10 DDR 15 19 15 DDR MAS E13 8547 4 gt 33 EI USVNC dd DDR DOMI AF20 15 5 024 MAS 0 15 VSYNC DDR DOST 20 DOMT SMD25 MATO BANK SELECT 0 ZADO R548 100 DQS1 CSB1 11 DDR 12 ZAD1 VGPIO0 CRT DDCK 10 DEMOS AE18 Mp16 SMD22 MA12 DDR BA 12 Maa BANK SELECT ZAD2 VGPIO1 8566 100 CRT_DDDA 10 DDR 17 0165 22 Mata DDR MATI MATT ZAD E DDR MD18 ARIT MDISSMD20 Mata AF16 DDR 12 MA12 PAN DDR MD19 016 MD19SMD19 ZADS BEL gt POL 94417 DDR MD20 LI 14 DDR MD21 ARIE 20 5 54 SRAS DDR_RAS 12 AG BBE 27 ADIT MD21 SMD21 scas
53. 11 HCLK SIS650 CPUCLK 98 98 freer sey PEBB88888885325882r829 788588882522 2323222323 E 5 9050 0066 5655 8858 2 11 ios fX 8800 582 77722225222122255222200052512254400 9000 HT 5 5802 245 5 955551555451226 2 4 H_LOCK COE ET HLOCK B8 255 EEEE EEE EEEE R19 0 4 4 H_DEFER 28 DEFER 9 lt lt 5 lt 44 9554 8885 AREQRNBCAD C 1 gt VBCAD 9 9562 4 TRDY 426 HTRDY 88 46 gt 75 0 010 4 CPURST CPUEWRGD 220 CPURST AFRAMER 82 0603D 0603 4 CPUPWRGD ERE 919 CPUPWRGD jtina 61 1 lt 4 H_BPRI JH BERE 127 ATRDY 63 HVREF ADEVSEL 04 4 A4 4 H RSH 2 ASERR PHS RS2 ASTOR HL 2 sos cm RSt RSO 9563 628 C597 Place this m 0 VBHCLK 180 cap under ADS LES BHCLK R21 gt 9 650 solder HITM WBF VGPIO2 1 BEEN me WBFANGPIO2 Dg BCAD R110 1 A AA 2 VBCAD 9 DBSY 210 REQ 0 4 e 5 GND CREGRO 4 HREQ4 epee BGCLK 1 AA 2 22 VBGCLK HREQ3 Hix HREQ2 5 _5 _______ ____ HREQO AD STBOVAGCLK IS 5 STH ADS TBH AD_STBO VAGCLK ASOKE 4 H ADSTBIH Hae ADSTBI m
54. 1519 ACS7 SYNC SDATAOUT 2 Mii C264 1 010 50 063 AGND SYNC CDROM_RIGHT 1549 acor lt ACH 870 1 RBs 8 cor 22 sma 10 107 osos RIT 1 S Jconow RIGHT 17 QE CLOSE TO CODEC con 18 C269 1 2 10 10V R185 1 2 68K 5 CDROM LEFT JCDRONLLEFT 17 41 14 318MHZ_AUDIO XTUIN TRUE a MEET 1 2 10V 0603 186 1 2 68K 5 COMM MORD COR m 0603 T T 16 C267 1 2 0 1U NA 50v 0603 0603 1 12 ec peep VIDEO x d 1 C268 1 OU NA 50 0603 R192 VIDEOR 100K 100K 100K 0603 0603 0603 24 C263 1 osuma 50 093 tov 10 2 6242 PE C278 1 2 O1UNA 50 1v 1U 1 2 6243 32 35 AOUT L 7 10 10 i ias AQUI R 090 ANO CANET AND EE H 33 an uNEIOUTR 36 C 58 SPKR 1 0236 34 0262 1 10 10V 0603 LN 3 C225 1 10 10V 0603 x MONO OUT MONO OUT Mono OUT 19 R703 cm AGND 4 2 MEET 2 dur T 89 C224 4 2 010 50 0603 4 INTERNAL MICROPHONE 1 2 l 2 i sov OUT I 0 a cata 4 2 sov i 40K 0603 ow ALT LINE OUT R 4 ie 77 1 2 48 C250 1 1000P 50 0603 i t Hirose i 10 4 7 50V 0608 SIPDIF_OUT STMA 2 0513 0603 30 C281 1 1000P Sov 0603 4 DF13 2P
55. 22 06030 4 4 C757 4 cro 1 C86 06030 22 100P C767 4 10 40750 1 0603 gaos 06030 a 4 11 USBCLK SB USBCLK SB USBCLK48M IVDDO 1 8VS USBPO P B18 01 4 2 TEHRI H uvo IVDD2 USBPi P uvo IVDD3 xX Pe LR Ee SEU USBPI N r TODA ___08 2 ___ 16 R142 CLOSE TO 961 uv2 006 i 214 uv2 Z USBP3P_ pa 27 USBP3 1 USBP3_P USE 03 IVDD_AUXO Het tt av i 22 06030 P E18 Ins IVDD AUXI N Fig pe aum i wu USBPSN 27 USBP3 1 N USBPS N UV5 OVDD2 21u OVDD3 ps 2 950 27 USB 1 lt uap aci la oco OVDD4 OVDDS i USB 2 2 15K USBP2 P 4 OVDD6 i C84 USB 54 R107 1 15K USBP2 es ud 27 USB OC3 5 lt 554 OVDD7 AA 903 99 USB 5 OVDD AUXO sav USBVDD OVDD AUXI USBVDDO OVDD AUX2 i USBVDD1 OVDD_AUX3 i OVDD_AUX4 usBvsso USBVSS USBVSS1 PVDDO 3VS 1523 y M PVDD1 O Be A EE USBVDD REN vsso PVDD3 een DM IUE 1551 i R75 CLOSE TO 961 vss2 PVDD pow 4 4 2012 4 1 USBPL 1553 PVDD_AUX1 crag TL 27 USBP1 AR vss4 08 0803 22 06030 1555 PVDDZ 16 o 1 avs s 1206 i 1556 R757 R158 557 VDDZO 1 USBP1 858 VDDZ1 UsBvss 4 4 4 1
56. 8575 N B Maintenance Functional block diagram CPS LPS ISO CNA SYSCLK LREQ CTLO DO D1 D2 D3 D4 D5 D6 D7 PCO 2 CLKON RO R1 TPBIAS PD RESET gt Received Data Link Decoder Retimer Interface LO lt lt gt lt gt lt gt gt lt gt lt gt lt gt Arbitration gt and Control gt State Machine gt Logic gt gt gt lt Bias Voltage and eo Current Generator Transmit Data Encoder lt gt TPA lt gt TPA 9 lt gt TPB lt gt PLLS ud d 3 d 4 FILTERO and Cloc 4 FILTERI Generator 38 8575 N B Maintenance Features Fully supports provisions of IEEE 1394 1995 standard for high performance serial bus and IEEE 13942 2000 Fully interoperable with firewire and i LINKTM implementation of IEEE Std 1394 Fully compliant with openHCI requirements Provides one IEEE 13942 2000 fully compliant cable port at 100 200 400 megabits per second Mbits s Full IEEE 13942 2000 support includes connection debounce arbitrated short reset multispeed concatenation arbitration acceleration fly by concatenation port disa
57. 8575 N B Maintenance Continue to previous o teme Um mmo Definitions RESET RESET OFF mes mw mom o fo was p pomme Umwx eue po mew p D p per Umso mwee p p Port 9 TTL input voltage input high min 2V input low max 0 8V a wax rr o fo ee e ESRB fo fs mas www rr UE ONU DS RR mas ps penses re e asi me p mw p p p Imma pw me vam ve ve Do res Pull High Pull Low 5 3V Level shift 69 8575 N B Maintenance 1 8 Appendix 3 8575 Product Specifications CPU Intel Pentium 4 Processors Willamette Northwood with mFCPGA2 Package mPGA478 Socket Support up to Willamette P4 1 7GHz Throttling Northwood above 2 0 GHz Throttling FSB 400MHz PC 2100 615650 515961 L2 Cache 256KB System BIOS Flash EPROM Include System BIOS and VGA BIOS ACPI 1 0b DMI 2 3 1 compliant Memory OMB SDRAM on board Expandable to 1024MB Expandable with combination of optional 128MB 256MB 512MB memory Two 200 pin DDR SDRAM Memory Module PC 2100 1600 specifications 2 5x9 5
58. AP 1 0 Address Parity are driven by the request initiator along with ADS A 35 3 and the transaction type on the REQ 4 0 Z correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low This allows parity to be high when all the covered signals are high AP 1 0 should connect the appropriate pins of all Pentium 4 processor in the 478 pin package system bus agents The following table defines Request Signals subphase 1 subphase 2 A 35 24 APO AP1 A 23 3 APO REQ 4 0 1 APO ADS Input Output ADS Address Strobe is asserted to indicate the validity of the transaction address on the A 35 3 and REQ 4 0 pins All bus agents observe the ADS activation to begin parity checking protocol checking address decode internal snoop or deferred reply ID match operations associated with the new transaction BCLK 1 0 Input The differential pair BCLK Bus Clock determines the system bus frequency All processor system bus agents must receive these signals to drive their outputs and latch their inputs external timing parameters are specified with respect to the rising edge of BCLKO crossing V CROSS ADSTB 1 0 Input Output Address strobes are used to latch A 35 3 and REQ 4 0 on their rising and falling edges Strobes are associated with signals as shown below
59. PJTX s LAN MTXC R72 22 44 L ix E E MuTIOL LAN COL R69 2 49 U3 amp gt R32 Tm Media I O LAN_CRS R67 22 50 3 LAN_CT mm Controller ISC1893Y LF H80P 2 LAN MRXDV 1 800224 36 L 3 R31 R538 P LAN MRXER Sid D 5 7 2 515961 gt V 8 LAN 3 6 38 5 TXD i 71 TUAAAJ R35 R537 4 5 75 75 TDC 14 4 45 xps 6 TXD 4 Y YMO Bm RXC LAN MRXD0 1 g 2244 35 gt L R30 R27 T 1000P LAN MRXDI 2 mE MRXD2 3 6 33 e 77 5 GND 45 5 5 LAN MRXD3 n 4 32 1202 100 T 5 R260 0 OSC25MHI 3 V 2 R261 0 4 OSC25MHO L ces xi co GND 15502 2 T 27 osmuz 2 RAS 5 e 4 caos xa L C306 e R263 0 e T 10 25MHZ T 10 V V i V V 2 iv LAN GND 45 166 8575 N B Maintenance 8 13 PC Card Socket Failure An error occurs when a PC card device is installed PC Card Socket Failure 1 Check if the PC CARD device is installed properly 2 Confirm PC card driver 15 installed ok Board level Troubleshooting Check the following parts for cold solder or one of the following parts on the mother board may be defective use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement Yes Parts Signals oi U14 PCI AD 0 31 PCI SERRZ No
60. REQH GNT 30 PCI_GNT2 14 17 15 BT DETACH lt gt 1 DETACH NC5 ex Ao T 33 A PER 34 MPC PMER PMER 15 Hem 63 NS NS 29 35 29 RESERVEDS 38 IO GNDS t cRoUND2 piso i tap GND6 25 41 ADI SS 42 AD28 1202 100 vec GND 44 RESERVEDI 4 14 18 29 PCI AD 24 a ae 1 AD21 x1 Locko Locks AD 23 IDSEL 124 Ave 51 GROUNDS GROUNDIO T em an M6 13 Locke Locks 16 53 prol 4 m 0509 16 UsBP4 D gt BLUETOOTHINA ADIT H GROUND4 PAR E PAR PCLPAR 14 17 18 29 14589 2 4 BGA30 SKT1 22 ADI 58 ADIS 16 2 7 1 4553 WZ lt 7 14 18 29 PCI 2 BY AD 16 Br SND 14 17 18 29 PCI IRDY SL GROUND 82 cramer 17 18 2129 CLKRUN 7 65 TROE PCLTRDVA 14471859 PINE PCI SERRE 67 68 PCI STOP 17 18 1718 29 PCI_SERR 5 8 PCLSTOP 14 17 18 29 GROUNDS 3 3V 6 41 ooo 24 1 17 18 29 PCI PERR amp PoI PERRE TL PERR DEVSEL PCI DEVSEL PCI_DEVSEL 14 17 18 29 lar 14 18 29 1 Apis 134 GROUND12 Fat ADIE Tez HORNA 77 2004 013 2012 J510 zl Rona Api AE 1 pc IN ADIO 81 AD 10 GROUND13 25d 2 OU
61. SHORT SMT4 m FIR 7 R519 1 2 ma 1 420Z 100M GND 0 Ri V GINA IRED ANODE i E 1206 2 6802 4 2 FRL TRY 2 1 2 1 FD2 FDA FDI i J 8 128 0D7 6 128 007 6 128 007 6 FIDUCIAL MARK FIDUCIAL MARK FIDUCIALMARK FIDUCIAL MARK C531 C532 0 0603 GND 40U 0 47U i E oar TFDUGIOIE i 16 FIR TFDUGIO1E gt MiTAC 22 477 GND FIR 5 ED501 FD503 FD504 502 GND FIR FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK Te x DC POWER f X X We T Document ev See eels ILI BP deo te Ble ea Number 411671700004 Date Monday January 14 2002 3 of 3 5 z 3 z 1 Reference Material Intel Pentium 4 Processor 478 Socket 6515650 IGUI Host Memory Controller 515691 MuTIOL Media I O Controller SiS301LV Chrontel CH7019 TV LVDS Encoder PCII410GGU PCMCIA Controller uPD72872 IEEE1394 Controller 8575 Hardware Engineering Specification Intel INC SiS INC SiS INC SiS INC TI INC NEC INC Technology SERVICE MANUAL FOR 8575 Sponsoring Editor Jesse Jan Author Sissel Diao Assistant Editor Janne Liu Publisher MiTAC International Corp Address 1 R amp D Road 2 Hsinchu Science Based Industrial Hsinchu Taiwan R O C Tel 886 3 5779250 Fax 886 3 5781245 Fi
62. SRAS SDRAM Row Address Strobe 2 5V 3 3V M SCAS SDRAM Column Address Strobe 2 5V 3 3V M SWE SDRAM Write Enable 2 5V 3 3V M CS 5 0 SDRAM Chip Select CSB 5 0 2 5V 3 3V M CSB 5 0 multiplexed with DQS 5 0 DQM 7 0 SDRAM Input Output Data Mask 2 5V 3 3V M DQS 7 0 LO DDR Data Strobe 2 5V 3 3V M MD 63 0 Uo System Memory Data Bus 2 5V 3 3V M CKE 5 0 open drain SDRAM Clock Enable 2 5V 3 3V AUX S3AUXSW open drain Aux power switch for ACPI S3 state low active CKE6 2 5V 3 3V AUX DDRVREF A B I M DDR I O Reference Voltage SiS MuTIOL Interface Name Pin Attr Signal Description ZCLK I SiS MuTIOL Connect 3 3V M ZUREQ ZD Uo SiS MuTIOL Connect Control pins REQ 1 8V M ZSTB 1 0 VO SiS MuTIOL Connect Strobe 1 8V M ZSTB 1 0 LO Strobe Compliment 1 8V M ZAD 15 0 vo 1 8V M 1 8V M ZVREF I SiS MuTIOL Connect Reference Voltage M ZCMP_N I N MOS Compensation Input M ZCMP_P I P MOS Compensation Input M SiS MuTIOL Interface Continue Name Pin Attr Signal Description AGPCLK I AGP Clock 33 AFRAME vo AGP Frame 1 5V 3 3V M AIRDY Uo AGP Initiator Ready 1 5V 3 3V M ATRDY Uo AGP Target Ready 1 5V 3 3V M vO AGP Stop 1 5V 3 3V M ADEVSEL Uo AGP Device Select 1 5V 3 3V M ASERR I AGP System Error 1 5V 3 3V M AREQ I AGP Bus Request 1 5V 3 3V M AGNT
63. 0 2 CLK DDR 0 2 RPI6 RP20 10 8 eo R613 Pis R836 R837 150 From 014 515961 4 7K 4 7K J506 DDRVREFA SMBDATA 2 32 5 DDR gt n SMBCLK m gt gt R616 R658 150 4 33 DDRVREFB 47 P1 9508 35 VW _ gt 2 5 DDR R615 CS 2 3 150 Clock 44 AA gt DDRVREF R599 47K ICS952001 R662 gt u R95 DRAM SEL 33 tA 5 3VS 5 IK R632 7 CKE 23 E n 4 SDRAMCLK 22 U9 22 R98 R100 R102 EI FWDSDCLKO s Clock Buffer 8103 5 ICS93722 2 1 4 5 13 14 17 16 24 27 CLK_DDR 0 5 CLK DDR 0 5 3 5 CLK_DDR 3 5 614 22 150 8575 N B Maintenance 8 6 Keyboard K B Touch Pad T P Test Error Error message of keyboard or touch pad failure is shown or any key does not work Keyboard or Touch Pad Test Error Check 0509 713 J20 for cold solder lt 2 Re soldering Is K B or T P cable connected to notebook properly Board level Troubleshooting No 7 eri No One of the following parts or signals on the motherboard may be defective use an oscilloscope to check the signals or replace the parts one at a time and test after each replacement Parts Signals 0511 L33 5VA KBD_US JP Motherboard Ul L31 H8 SA2 U509 SW503 3VS IRQI Replace the faulty J13 RP48 45V IRQ12 Keyboard or J20 ROMCS IOR
64. 06030 lt 06030 80 20 060354 060305 0603054 0603D 06030 14 18 28 PCI AD O 31 en the a X ave 72 be Per 3 8 4 c2s9 b 275 71 0276 292 c293 l c294 295 c296 640 640 6410 040 640 640 50 50 50 50 50 50 50 50 0603D 060304 0603054 060304 06030 0603D 06030 4 4 4 4 4 4 4 V 98 _ TPBIN LE u 55 ND TPBiP 88 Te 101 TPA TPBIAS1 C875 1 0603 C876 4 1U NA 0603 96 TS L9 C297 1 2 1U NA 0603 C298 1 2 0603 TPBON 1 103 19 E SZ CLKRUN TRADE R804 R224 17182128 CLKRUN CLKRUN b 15 1394 PME crom 16 SERA 0603 14 17 28 PCI INTCH RAA2 GROM SCL SAk OUS 14 17 4 14 17 18 28 PCI FRAMER FRAME 4 14 17 18 28 PC _IRDY IRDY LVDDO 14 17 1828 PCI TRDY amp t TRDY LVDD1 ao 3 14 17 18 28 DEVSEL LVDD2 1417 18 28 PCI STOP LVDD3 1714828 PCI PERR LVDD4 3VS 14 1828 SERR LVDD5 44 17 18 28 PCI PAR PAR LVDD6 uPD72872 uPD72873 74 R225 T PCI VbDO R27 R227 NA PCI VDD1 ADANA m R811 P_DVDD2 PHYVDD y RIO amp RII connect an external resistor xo 56 2 229 Ed of 9 1K 0 5 to limit the LST s current eye la 3 P DvbDa
65. 1 mu O PHYVDD R813 RBIG INA 06030 06030 0603 Ro t R811 1 0603 R230 NA R230 6 R813 1 2 0603 PHYAVDD 7 9 4 17 8 21 28 PCIRST PRST PLAVDD7 exo nore 11 CLK 1394PCI PCLK P AVDDB R231 4 0 14 17 GNT fI 221 ONT P_AVDD9 14 1828 PCI AD22 R251 1 A2 IDSEL P_AVDD10 PHYAVDD 5 STE M NM PORTDIS 81 RESETB DGNDO M 83 cpg DGND1 610 59 DGND2 s DGND3 4 QE DGND4 5 DGND5 i DGND6 L ICL2 DGND7 DGND8 i DGND9 PC2 R232 1 10K 2 06030 CARDON 119 i CARD ON DGND10 3VS0 R283 130 A 2 118 EN xX PORTDIS RP529 E ICH2 AND PHYVDD O R284 1305 A2 AGND2 AGNDS CBES AGND4 i CBE2 AGNDS i 494 AGNDG lt CBEO AGND7 i RPSOA8C ano 1418 28 3 i UPD72872 SE PQFP120_0 4MM GND R195 TPB 0 5 8 35 8 CHOKE PLP3216S 1 4 1 32169 TPB J27 4 TPB LES Thad i R235 2 R236 270P 56 4 mCYYS 3 2 50 C302 1 10 06030 R238 1 0603D A 141 41 0603 0603 54K 56 M 1 z 1 A2 1 06030 R240 _ 1 A AA 2 0600 8196 1 AA A 2 14 spa 0 IEEE 1394 4P LINKTEK H 0 010 AVR20 4XXX0X 12 06030 R241 1 AQ 2 _ 06030 iL 2 3 as i AMAA 18506 4 4 i 4 8 56 142 GND R242 4
66. 14 IDE DE POOR 2 PODIS i opts IDE PDCSSE i 1 108RPX ae Poco IDE PDCSS R781 1 28 2 099 POCSI es a Ri RU We S 0608 0005 DERSTE poor pops PDDE PODS PODS PDDIT PODS PODIZ PDD2 PDDIS PIDI PODIE PDDG PDDIS PDDREQ R137 PIORDY i 4 2 7 PODACKE i 1 470 PORT 0603 PDCSSE i IDE 5 5 tsi Sok NAZ2PXDIST 15 DTCHAWKINA peo Uma B Er sca ise ee ee Eum Eee d 2 Ne 777 777 777 ET R730 10KINA 0603 PCI BUS y 7 019 pG1102W 1548 E 1429 PCI REQUE PGI GNTAF PCI ONTO rd 14 PCI GNT PCL POLGNTOR 1418 ECIOQSOANA 4482829 PCLPAR POLGNTM 1429 1428 mus 1 POLENTS TO ONDE 14 PENES moore ERE 8 T lt gt 7 25 5 HDD Si 1 1 4 E 14 182828 DEVSELH POl DEVSELE POLIRDY PCLIRDY 14182829 e is fa Er e PCI 5 31 PCI_SERR SHORT SMT3 to IDE Connector 18182829 PCLSTOP Pel STOPS a PCL SERRE POLSERRE 14162829 14182520 FRAMEE 41 7 PCI PERSE PO PERRA 14152 POLTRDY 14182829 4 4 x 19 4 8212829 PCRST 4 08 970
67. 2 6L3 NIB K HD NYLOK gt Co lt gt T SULATOR REAR SCREW 8575 43 370102610801 SPC SCREW M2 6L8 NIB K HD tz I I NIB 44 340671200020 FAN ASSY 8170 45 340611200013 SCREW ASSY CPU 8170 46 42167160005 MICROPHONE ASSY 8175 41 1345671700019 8575 M 48 1345671100009 BRACKET 8575 TOL erc RANGE M2 SI S PI Pe 6 02 SEE NOTES TREATMENT REMARK 0 6 0510 11 15 lo 2 05 0 110 5 15 UNIT MM SCALE 0 053 DRAWING NAME PF QDI XGA 14 1 04 8515 6 30 0 110 21 15 25 0 11 15 30 80 15 2510 210 3 0 4 DRAWN DESIGNED CHECKED APPROVED ATERIAL NO AD 416261113006 R00 aman 180 315 0 210 510 410 6 1 2 Inrfernational Corp CONTENTS OF CHANGE CHK APV MM DD YY 315 800 0 3 0 8 0 7141 1 1 5 D SHEET OF o w 0 0 2 80 180 15 0 3 25 45 0 0 813 25 0 S 0 4 B PDF created with FinePrint pdfFactory trial version http www fineprint com 31 8 TOL RANGE 0 6 6 30
68. 5 VDDQ 12 VSS 67 VCC CORE 4 2 C657 1 2 VDDQ 13 VSS 68 2 7 14 3 85 69 10 C685 010 VDDQ 15 VSs 70 C591 1 eU ces y j 2 0 x 7 16 VSS 71 C690 0 1 GND 18 8 VDDQ 17 VSS 72 C604 1 C921 1 e VSS 73 C686 4 VDDZ 0 VSS 74 C626 1 C922 1 2 019 1 VSS 75 VDDZ 2 VSS 76 cess 4 2 2639 10 2 57 9 VDDZ 3 VSS 77 GND 010 VDDZ 4 VSS 78 1 2 VDDZ 5 VSS 79 GND FOR VDDZ 6 VSS 80 FOR VIT GND VDDM C613 4 2 010 VDDZ 7 VSS 81 2028 o VSS 82 VDDZ9 5 VSS 83 x 002 10 2 e ool le VSS_84 515650 lt gt 540 77 85 Mitac Z 8575 515650 3 3 Be Document C Number 411671700010 jate Wednesday January 16 2002 Bheet 8 of 29 4VCC CORE 515650 3 3
69. L520 300Z 100M 36 e NN e e d C719 C718 T Olp 1000P 37 e e 117 1207 100 VDDREF 1 e 119 1202 100 VDDZ 11 e 120 1207 100 VDDPCI 13 19 e 123 AAA 1202 100 VDDA48 28 e 121 1202 100 VDDAGP 29 e 118 1207 100 VDDCPU 42 e 1146 m 1202100 VDDSD 48 C702 10P 7 e N o x502 C701 14318MHz 10P T 40 R644 33 HCLK CPU Ul 39 R648 33 HCLK CPU CPU PD VIT PWRGD R626 R645 R649 Pentium 4 2 4 7K 49 9 49 9 3VS 0 N 3 9 R641 2 ZCLKO gt cu 31 R661 22 AGP_CLK P7 R632 22 SDRAMCLK 47 gt U4 2 50 R630 33 REFCLKO e gt 44 R635 33 HCLK SIS650 gt Host Memory ds HCLK 6186504 3 gt Controller R636 R640 FWDSDCLKO SiS650 3VS 49 9 49 9 R875 R624 Tonext page 10K 4 7K 0520 5 gt CPU 5 y cS P14 Pis Pio 0508 3 1 e R633 33 REFCLK1 5 014 R625 33 REFCLK3 Clock gt oc 10 R646 22 MuTIOL Generator 5 USBCLK sh Media I O Control TX UC ntroller ICS952001 14 FS3 R668 33 SBPCI gt 0 SiS961 27 R670 2 CLK SIO 20 Pa gt 0511 15 FS4 R656 33 LPC33 8 Super I O PC87393 R83 R565 33 0 Po 4 FS2 14 318MHZ TV MOD XOUT Toui P siss0lLV Chrontel CH7019 17 R660 33 CARDPCI 5 gt PCMCI
70. Link reporting address parity errors data parity errors during the Special Cycle or any other system error where the effect can be catastrophic When reporting address parity errors it is an output PRST 5 3 3 Reset PCI reset Link PCLK 5 3 3 PCI Clock 33 MHz system Link bus clock Remark If the Link is pulled up it should be connected to 128 8575 N B Maintenance 6 System Block Diagram J509 MINI PCI Socket U6 PCMCIA Controller PCI 1410 U505 Power Switch PCMCIA CARDBUS Socket LCD PANEL TV S VIDEO CRT USB HDD CDROM Cover Switch RJ 45 Jack m U1 Pentium 4 CPU U2 Thermal Sensor Willamette Northwood ADM1032 Micro FCPGA 478 pin 0504 SiS301LV U4 CH7019 IGUI Host Memory Controller SiS650 200 pin DDR SO DIMM Socket 2 IEEE 1394 Controller uPD72872 PCI BUS Hyperzip Data Bus External Microphone Internal Microphone 014 AC Link 015 016 z UA Internal Speaker MuTIOL Media I O Audio Codec Amplifier SPDIF JACK Controller 05 515961 M D C LAN PHY ISA BUS IR Module
71. MIC INPS MIC 2 2 Y VV 1 C798 c L535 C264 220P T External lu 2 4 C271 R187 6 8K 20 in CDROM RIGHT gt Em C269 R185 J12 18 In SK CDROM_LEFT C270 R186 CDROM 19 th RRE 3 CONN e R193 R191 R192 R141 100K 100K 100K 0 77 77 C274 R173 0 0 23 C260 in L34 f 120Z 100M 24 L35 ___1202 100 L40 120Z 1100M 48 SPDIFOUT 1545 y w 1202 100M 1546 y _1202 100 36 AOUT R L547 1202 100 To next page 35 AOUT_L m AGND 163 8575 N B Maintenance 8 11 Audio Failure No sound from speaker after audio driver is installed AUDIO OUT DEVICE DECT DECT HP OPT C803 R731 R719 0 0 HP 228 10K 20K 1 0 No this condition 1 1 No device C804 R732 R720 22u 10K 10K VRLS 5V 3VS 3VS_SPD L39 o 600Z 100M J25 BIRD NEC 2 22 SPKROUT 1 21 RLINEIN R R96 SPKROUT 2 4 7K 20 RHP IN Y Y MUTE 143 6007 100 Internal 9 MUTE 11 Speaker VRI 600Z 100M CONN 910 EE 10K SPKLOUT rr 1 DTCIA4TKA T 5 _
72. Touch Pad L521 R146 Mie REO K1 0 7 KO 0 15 Try another known good Keyboard or Touch pad Fl 129 T CLK H8 T DATA 151 8575 N B Maintenance 8 6 Keyboard K B Touch Pad T P Test Error 0511 LPC Super I O 87393 Error message of keyboard touch pad failure is shown or any key does not work 5 L521 120Z 100M 709 C731 C708 RP48 H8 AVREFI J13 3VS 9 594 37 36 VCCL2 B AVCC 8737 AVREF 7T 100K SW503 19 KBD_US JP 4 ah 5 KI 0 7 _ 4 R744 10K P 22 VV KO 0 15 T5VA 3VS R245 R138 R125 U509 47K Ride 10K 10K 72 ROMCS 9 amp ncs 95 Fl 0 25 n Micro R690 45V oS N o 0 gt Controller 73 MCCS 14 15 H8 MCCS e 98 129 1207 100 SA2 CN a T CLK H8 T CLK E 133 1202 100 PEL IRQI 55 302i e p 131 1702 100 3 4 83 IOR 96 C222 4TP 82 IOW IOW_H8 82 Touch pad 152 8575 N B Maintenance 8 7 Hard Drive Test Error Either an error message is shown or the drive motor spins non stop while reading data from or writing data to hard disk Hard Driver Test Error 1 Check if BI
73. Translation Lookaside Buffers TLBs and ROMs 1149 1 Standard Test Access Port and Boundary Scan mechanism enables testing of the Pentium 4 processor and system connections through a standard interface Internal performance counters can be used for performance monitoring and event counting Includes a new Thermal Monitor feature that allows motherboards to be cost effectively designed to expected application power usages rather than theoretical maximums 1 2 2 System Frequency 1 2 2 1 System frequency synthesizer ICS952001 Programmable Timing Control Hub for P4 processor General Description The ICS952001 is a two chip clock solution for desktop designs using SIS 645 650 style chipsets When used with a zero delay buffer such as the ICS9179 06 for PC133 or the ICS93705 for DDR applications it provides all the necessary clocks signals for such a system 8575 N B Maintenance The ICS952001 is part of a whole new line of ICS clock generators and buffers called TCH Timing Control Hub ICS is the first to introduce a whole product line which offers full programmability and flexibility on a single clock device Employing the use of a serially programmable I2C interface this device can adjust the output clocks by configuring the frequency setting the output divider ratios selecting the ideal spread percentage the output skew the output strength and enabling disabling each individual output clock TCH also inco
74. USBCLK SB DC Power Board e a From 0508 clock generator 3V L524 T L523 3V USBOVCCS 120Z 100M 120Z 100M 9 J7 PJ2 0504 e USBVDD 3 BAWS6 e d R516 USBOCI 10K gt 2 gt R506 C506 Puy C744 C745 L USBOCO 1 5 33K D gt i AUSBOCH 5 J USBVSS e e J5 L C534 R518 i V T 1000P 47K USB 14 1509 P2 OC0 1 50 USERS 600Z 100M USB 54 0C3 5 48 TARAS R147 USBPO 4 Ys 2 22 014 USBPO0 P USBP0 32 R504 R505 4 USBP0_N USBPO 15K ISK 34 GND C86 C87 R148 MuTIOL 2 100P 22P 2 5V Media I O V R75 USBOVCCS GND_USB 22 3 5 Controller USBPI P USBP1 P2 vouri _ e 26 2 1516 USBP1_N USBP1 E 28 3 vivi U3 vou H SiS961 C122 C121 R158 100P 22P 22 E R3 C517 L 33K T V USBOCI 7T y R5 1 USBP3 P p USBP3 47K ES 14 USBP3 N USBP3 m Po siis e 16 600Z 100M USBP1 3 B e NWA 100P 22P 22 Riel USBPI 4 Y NS 2 22 USBPS P USBP5 e 1 R508 R509 4 5 5 USBPS N USBPS jokio GND C126 25 R163 i 100P 22P 22 GND_USB 158 8575 N B Maintenance 8 9 USB Test Error 2 An error occurs when a USB I O device is installed
75. amp BUTTON ze Document Number 411671700010 777 Dale Wednesday January 16 2002 Sheet 21 of 29 DEFAULT SHORT MICROCONTROLLER H8 x writ bbe phas 1 8 BDDACTP KO1 5VA CAP Expended mode with On Chip ROM disable 3 6 NUM KIZ BAV99 NA 4 B i SCROLL 5
76. cso 1 4 5 52 11 6 1 Z GND EAM C164 RP27 16 1 338 RPX8 1000P MAS 1 2 0603 14 3 13 4 1 5 GND 1 7 NE MDS RP33 16 1 338 RPXB GND 04 1 2 MDO 14 3 DOMO 13 4 0050 1 5 ri MDE RP32 16 1 338 0603 MD2 1 2 MD12 14 3 V 13 4 GND 1 Fi MD13 TAA 6 bast RAV C170 MDi0 16 YNN 1 378 1000P MD14 1 2 0603 015 14 3 MD11 13 4 MD16 1 5 MD17 11 6 GND Past we 8 MD25 RP 1 378 029 1 2 0053 14 3 DQM3 13 4 MD31 1 5 11 6 MD26 10 7 MD27 9 8 MD39 1 1 398 MD38 2 045 14 3 044 1 4 MD40 5 DQMS 11 6 10 7 9 8 1000P MD42 RP23 16 1 338 0603 Dass 1 2 i 049 1 5 GND MD48 ri MD53 1 7 MD52 MD54 RP22 16 1 338 RPXB C182 DOME 1 2 1000P DQS6 14 3 0603 055 13 4 051 1 5 MD50 BAAN ri 410 GND 8 RPZT 1 338 MD61 1 2 DOM 14 3 C186 Das7 13 4 1000P MD63 1 5 0603 MD62 11 6 p AA MDi8 RP30 1 1 378 GND MD21 IAM 2 022 14 3 13 4 19 1 5 MD23 11 6 024 10 7 MD28 9 8 12 1 1 398 ERA i MAT 14 3 MAS 13 1 5 MATT 6 1000P 10 7 0603 MAT 9 8 GND ci 010 1000P 0603 0603 e 16V GND
77. indicates to the bus arbiter that this device wants to become a bus master GNT 5 3 3 Bus master Grant Link indicates to this device that access to the bus has been granted IDSEL 22 5 3 3 Initialization Device Select Link is used as chip select for configuration read write transaction during the phase of device initialization If Cardbus mode CARD ON 1 this pin should be pulled up to DEVSEL 39 PCI Cardbus 5 3 3 Device Select when actively Link driven indicates that the driving device has decoded its address as the target of the current access STOP Uo 40 PCI Cardbus 5 3 3 PCI Stop when actively Link driven indicates that the target is requesting the current bus master to stop the transaction Name PIN NO IOL Volts V Function Block PAR 44 5 3 3 is even parity across Link ADO0 AD31 and CBEO CBE3 It is an input when ADO AD31 is an input it is an output when ADO AD31 is an output ADO0 AD31 VO 9 10 12 13 PCI Cardbus 5 33 PCI Multiplexed Address Link 15 18 23 24 and Data 26 29 32 33 47 50 52 53 55 56 58 59 62 63 65 68 CBEO CBE3 21 34 45 57 5 3 3 Command Byte Enables Link are multiplexed Bus Commands amp Byte enables FRAME vo 35 5 3 3 Frame is asserted by the Link initiator to indicate the cycle beginning and
78. this pin is used as PS2 mouse data signal PMCLK VOD PS2 Mouse Clock GPIO18 O OD When the internal keyboard and PS2 mouse controllers are 3 3V 5V AUX Jenabled this pin is used as the PS2 mouse clock signal MAC Interface Continue MAC Interface Name Pin Attr Signal Description TXEN Transmit Enable 3 3V AUX When set to a 1 and the transmit state machine is idle then the transmit state machine becomes active This bit will read back as a 1 whenever the transmit state machine is active After initial power up software must insure that the transmitter has completely reset before setting this bit MDIO VO Management Data I O 3 3V 5V AUX Bi direction signal used to transfer management information for the external physical unit Requires external pull up resistor RXDV I Receive Data Valid 3 3 5 AUX This indicates that the external physical unit is presenting recovered and decoded nibbles on the RXD 3 0 and that RXCLK is synchronous to the recovered data This signal will encompass the frame starting with the Start Of Frame delimiter and excluding the End Of Frame delimiter COL I Collision Detect 3 3 5 AUX This signal is asserted high asynchronous by the external physical unit upon detection of a collision on the medium It ll remain asserted as long as the collision condition persists CRS I Carrier Sense 3 3V 5V AUX This signal is asserted high asynchronously by t
79. 0 VO 3 3V 5V M PCI Address Data Bus In address phase 1 When the SiS961 is a PCI bus master AD 31 0 are output signals 2 When the SiS961 is a PCI target AD 31 0 are input signals In data phase 1 When the SiS961 is a target of a memory read write cycle AD 31 0 are floating 2 When the SiS961 is a target of a configuration or an I O cycle AD 31 0 are output signals in a read cycle and input signals in a write cycle PAR VO 3 3V 5V M Parity 515961 drives out Even Parity covering AD 31 0 and 3 0 It does not check the input parity signal FRAME 3 3V 5V M Frame is an output when the 515961 is a PCI bus master The 515961 drives FRAME to indicate the beginning and duration of an access When the SiS961 is a PCI slave device is an input signal IRDY 3 3V 5V M Initiator Ready IRDY is an output when the 515961 is a PCI bus master The assertion of IRDY indicates the current PCI bus master s ability to complete the current data phase of the transaction For a read cycle IRDY indicates that the PCI bus master is prepared to accept the read data on the following rising edge of the PCI clock For a write cycle IRDY indicates that the bus master has driven valid data on the PCI bus When the SiS961 is a PCI slave IRDY is an input pin TRDY 3 3V 5V M Target Ready TRDY 15 an output when the 5
80. 06030 0 1 0 1 0 100 00 166 67 71 43 83 33 GND C200 1 2 10 _ 06030 0 1 0 1 1 80 00 133 33 66 67 66 67 0 1 1 0 0 80 00 133 33 66 67 66 67 GND 0 1 1 0 1 95 00 95 00 63 33 63 33 2 5 DDR 25V DDR ER 0 1 1 1 0 95 00 126 67 63 33 63 33 L22 4 DAN CBVDD i002 CBVDDA m 0 1 1 1 1 66 67 66 67 50 00 50 00 3002 100 4 100 C101 L cos 2012 c112 c150 1000P 27 100 010 2 0603 1206 0603 0603 10 50 lt 50 50 8575 MAIN CLOCK amp CLOCK BUFFER ND Size lev Document C Number 411671700010 d later Wednesday January 16 2002 Bheet 11 of 29
81. 06030 AAA AUXOK E H INTR R16 L i weve coo 1 7 4 HINTR H NMI 20 NTR LAN 2 d RTC X2 1K 0603 A CM H IGNNE 48 NER 19 i 10 4 H FERR H FERRE FERR 9903 ST 5 er ieee R706 C782 4 H_STPCLK EE vig STPCLK R166 4 LAN MTXDO i GND 100K 220 4 SLP CPUSLP MIITXDO LAN 19 0603 H H i 20 11 REFCLK3 REFCLKS H RICE Ass gt LAN_MTXD1 19 GND APTCD1 C RU AAA Ag Bog gt LAN_MTXD2 19 B4 R178 1 LAN IL Cx HD pe ne MIITXD3 gt LAN_MTXD3 19 i ca 21 ADD LP ADI rano 0603 0603 21 LPC AD2 LAD2 LAN MERE 106 21 LPC_AD3 LADS MIIRXCLK MRXC 19 i aus 21 LPC_FRAME LPO pet LERAMER MIIRXDV MRXDV 19 lt 2 221 SERRO SERIRQ SRo MIIRXER 8 LAN MRXER__ lt T an MRXER 19 ND SE E 1 jeu geh hed u CPU 5 R850 1 0603 RIC Xi 92 08 LAN MRXDO P an 19 OSC32KkHO 25 AN MRXDI MRXD1 19 AN BATOK B8 LAN MRXD2 MRXD2 19 03 BATOK WAKE UP R851 _ 1 10 0603 7 28 PWROK PWROK PWROK 44 LAN MRXD3 lt MRXD3 19 1 E MPCIACT R252 1 19603 VCC_RTC RTCVDD TM LAN C
82. 1 16W 5 0603 SMT R231 R548 R566 R74 R789 R 1 0603 5 5 0603 SMT 5 0603 SMT PR557 PR563 PR508 PR518 D 8 ojo 15 5 21515 5 2 2 2 e 5 eo Oo o 1 0603 SMT 12 19 RES 10K 1 16W 196 0603 5 PR507 PR513 PR527 PR540 RES 10K 1 16W 596 0603 SMT R10 R516 RES 10K 1 16W 5 0603 SMT PR506 R125 R138 R149 R15 Part Number Description 271071106301 RES 10M 1 16W 5 0603 SMT R189 271071111101 RES 110 1 16W 1 0603 SMT R20 271071113101 RES 11K 1 16W 1 0603 SMT ________ 271071113101 RESLIK 1 16W 1 0603 SMT PR530 271071121211 RES 12 1K 1 16W 1 0603 SMT 271071127211 RES 12 7K 1 16W 1 0603 SMT PR508 271071137271 RES 13 7K 1 16W 196 0603 SMT PRI0 PR558 271071131101 RES 130 1 16W 1 0603 SMT R545 271071134701 RES 130K 1 16W 0 1 0603 5 PR560 271071147011 RES 147 1 16W 1 0603 SMT R549 271071151101 RES 150 1 16W 196 0603 SMT 271071151302 RES 150 1 16W 596 0603 SMT R503 R504 271071153101 5 15 1 16W 196 0603 5 PRI3 PRI4 271071153101 5 15 1 16W 196 0603 5 271071153301 RES I5K 1 16W 596 0603 SMT 271071153301 5 15 1 16W 596 0603 5 271071102102 RES IK 1 16W 196 0603 5 271071102302 RES 1K 1 16 5 0603 SMT PR517 271071102302 RES 1K 1 16
83. 193 T1 198 12 Reference Material 230 8575 N B Maintenance 1 Hardware Engineering Specification 1 1 Introduction The 8575 motherboard would support the Intel Pentium 4 processor with FCPGA packaged 478 Socket which will supports the different levels up to Willamette P4 1 7GHz Throttling Northwood above 2 0GHz Throttling This system is based on PCI architecture which have standard hardware peripheral interface The power management complies with Advanced Configuration and Power Interface ACPI 1 0 It also provides easy configuration through CMOS setup which is built in system BIOS software and can be pop up by pressing F2 at system start up or warm reset System also provides icon LEDs to display system status such as power indicator HDD CDROM NUM LOCK CAP LOCK SCROLL LOCK SUSPEND MODE and Battery charging status It also equipped 2 USB ports The memory subsystem supports OMB on board memory two JEDEC standard 200 pin small outline dual in line memory module SODIMM support PC2100 amp PC2700 515650 IGUI Host Memory Controller integrates a high performance host interface for Intel Pentium 4 processor a high performance 2D 3D Graphic Engine a high performance memory controller an AGP 4X interface and Sis MuTIOL Technology connecting w 515961 MuTIOL Media I O 8575 N B Maintenance The 515961 MuTIOL Media I O integra
84. 1U VIT 16 55 15 M C603 1 i 2100 C633 1 2 10 5 C634 1 2 VIT VSS 16 C644 4 2 10 2 010 ces 1 20 VIT 18 VSS 17 C665 1 2 10 C617 1 2 VIT_19 VSS_18 616 10 596 1 2 010 1 2 0 2 5 VTT 20 55 19 C590 110 2 109 61 2 E 5 VSS 20 57 Z VDDM 0 VSS 21 NV 7 GND GND VDDM 1 VSS_22 X GND GND VDDM 2 VSS 23 e VDDM 3 VSS_24 VDDM 4 vss 25 Hk FOR VIT VDDM 5 vss 26 VDDM 6 VSS 27 VDDM 7 VSS_28 VDDM_8 VSS 29 VDDM 9 VSS 30 VDDM 10 VSS 31 VDDM 11 vss 32 2 VDDM 12 vss 33 222 VDDM 13 vss 34 28 vss 35 29 2 5V_DDR VDDM_15 VSS 36 3VS VDDM_16 VSS 37 VDDM 17 vss 38 VDDM 18 vss 39 HA u VDDM 19 vss_40 2 1 2 1 1 w 4 2 10 VDDM 20 VSS 41 L ceso C674 cese ceo 1 VDDM 21 VSS 42 100 10 VDDM 22 VSS 43 e 1 VDDM 23 VSS 44 10v 10v 10V 10 u C682 1 2 VDDM 2M VSS 45 C671 1 2040 VOOM 26 1 2010 VDDM 27 vss 48 26 GND VDDM_28 vss_49 8 WZ VDDM 29 vss 50 VDDM 30 VSS 51 FOR VOCM VDDM 31 VSS 52 33 VDDM 32 VSS 58 FORVDDO 55 54 jH 0 VSS 55 VDDQ 1 VSS 56 VDDQ 2 VSS 57 3 VSS 58 VDDQ 4 VSS 59 VDDQ 5 VSS 60 VDDQ 6 VSS 61 VDDQ 7 VSS 62 VDDQ 155 63 3188 Wy 9 VSS 64 VDDQ 10 VSS 65 C649 1 VDDQ 1 VSS 66 avs 25 2
85. 2 0 0 2 05 0 2 0 2 2039 C2 TEM PART NO DES CRIPTION Q TY REMARK 34461 600 COVE R HINGE IDI 2 81 T5 44 611740 LC ASSY QDI XGA 14 1D5 8575 OPTION 34061 100 BOARD COVER ASSY S 85175 531 099990 OPTION 86 05 8115 OPTION 34467 600 ER DUMMY IDI 2 81 75 4 671200 PWA 8170 ESB BD 34061 110 ER ASSY SILVER 85T5 442164900 CH PAD MODULE TM41PD 350 CO YS ON BY Ce PO 422665400 ASSY TOUCH PAD CASE KIT VENUS 34061 600 CKET ASSY T P SULATOR 8115 4 611100 PWA 8515 T P BD 34561 600 HEATSINK K B_PLATE 8175 34561 100 8515 34561 100011 ET KB PLATE 1 8575 34367 600 TE KB 8175 340 611700 ASSY P4 8515 34561 600 LCD HINGE 8115 YI Co PO 340 671700 G ASSY 8515 9 1340 671700 ASSY 3L 8575 340 611100 ASSY R 8515 PO 341 611700 LDING AUDIO 8575 42 611100 ASSY MDC EMI 8575 42 611100 ASSY TOUCHPAD 85175 34561 100 AL 05 8515 412 55600 ASSY MDM 56K U V F PACK WO KIT 34461 600 Y CARD PCMCIA 8115 523461110 OS HDD AS
86. 2 A 5 MAIN e e e OUTPUTCTRL 11N e S V 5 5 i Q From H8 eT PWM PR543 RT FEEDBACK 6 19K 5VAS 14 REF TL594C e PR561 L 580 59 2IN 575 4 7K T 556 542 ol 2 49K pus 100K 568 L 540 10K Ou V zm 1000P 10K e e 5 BATT DEAD 575 00 566 1 e To H8 nd 181 PUSI4A V 5 C898 557 LMV393M 555 Pon PQ510 Olu 100K SCK431LCSK 5 e e V 139 8575 N B Maintenance 8 1 No Power Battery Discharge When the power button is pressed nothing happens no fan activity is heard and power indicator is not light up D D Board PUSI3 SI4835DY 8 BATTI 3 i e 5 i o VMAIN PU512 p PC579 PC578 1000P 0018 8 1 PR553 o 6 2 100K 5 1 a PR564 V 301K e e 5 H8_AVREF1 PR552 33K L521 1 504 ADEN 120Z 100M 508 1205 00M 2 7002 1 1 Y Y PRSSI L C708 C731 C728 PL505 226K 0 1 5 502 1207 100 ADINP gt V puer 23 12 e N p __ DTCI44WK 5 77 4 9 59 3637 V ADEN 47 w PC583 584 e 0 01 1000P 5VAS A D511 3 R672 BAV7OLTI 9
87. 22 SPKRQUT s00z 180M tss 11 HIROSE LE OUT 5 1 2 24 20 REIN nO Eus SPKRQUT 1608 1 2 2 R 2 1 2 5 VRI 007 10 143 Dr13 2P 1 25V R714 22 0603 AGN 7 2 1608 80071000 1537 4 i 11 10K 3 SPKLOUTe _ 1608 1 2 1 23 LINE OUT 2 1 2 1608_6007100 534 2 4 LOUT 15 SPKLOUT S00ZH00M t g 2 HIROSE 3 AOUT R n LLINE IN LOUT 1608 4 177 TIMA 2 174 SV _1 4 DECT HP OPT 1 TRA C793 18 1 2 5002100 145 DF13 2P 1 25 2 70603 AOUT L 2 1 1 1 11 10 17 SPDIFOUT 1 8 BYPASS 100P 1608 6002 100 128 ipm 220 4 0603 19 R BYPASS GNDO C280 1000 6 3V EW6 3 1603 0603 9 28 0805 10K J J ar tz i 1 s 2 1525 _ 80 20 0603 czas coss Very Close to TPAQ202 Pin 18 7 1536 SPOS TQ 7 1 2 1138 1 C286 10 40 44 9002 24 Ei A 4 2 1 2 600 FOXCONN AGND 0603 16 C245 1262 1608 6002 1 44 MUTE IN 2 0 10 1000 1608 80 20 3033 J032 MUTEIN Noo 7 0608 tev 77 AGNO AGND Noe 50 50 ewes 77 R721 CAGND 2 1530 1 1529 4 1 1 E 2 CL 0605 P ui AGND AGND 5VAMP gt 4 470 220 31 98 91 AAA 0805 0805 10K 32 27 CHOkE PLPaPtes 1 80 20 80 20 0603 La 2 10 33 98 63 28 PLP3216S CHOKE 165 1
88. 242670800113 340671600028 421015560001 272072153401 272075103702 272075103401 272075103401 272005103401 272005103401 272073223401 272072104702 272073104701 272075104701 272075104701 272072104402 272003104701 272075102701 272030102405 272075102403 272075102403 272075101701 ornosess _____ te 10 16V 80 2096 0603 SMT CAP lU 25V 80 20 0603 Y5V S 10 50V 80 2096 0603 SMT 10 50V 80 2096 0603 SMT 10 CR 16V 10 0603 X7R SM 10 CR 25V 80 20 0805 Y Part Number 272075101401 100 50V 10 0603 COG SMT C4 C7 272075101401 272075100701 Description CAP 100P 50V 10 0603 COG SMT CAP 10P 50 10 0603 NPO SM 272075100302 CAP 10P CR 50V 5 0603 5 272021106501 272021106501 272011106701 272012106701 272012106701 272022106701 272023106501 272073151301 272073151301 CAP 10U 10 20 1210 X7R SMT CAP 10U 10 20 1210 X7R SMT CAP 10U 10V 80 20 1206 Y5V S CAP 10U 16V 80 20 1206 Y5U CAP 10U 160 80 20 1206 50 CAP 10U 16V 80 20 1210 Y5V S CAP 10U 25V 20 1210 Y5U SMT CAP 150P CR 25V 5 0603 5 CAP 150P CR 25V 5 0603 5 272431157507 CAP 150U TPC 6 3V 20 H1 9 7343 272431157507 272431157508 272075150301 272071105701 272071105701 27200110
89. 3 D Db d gt USBVDD P1 CP3 age d on oar E circuit diagram Discharge P23 7 1 25V P29 Page 6 29 on M B board 23 circuit diagram 2 gt PHYVDD PF501 Through by part PF501 P29 1 544 501 gt PHYAVDD 501 PDS14 2 PL508 10502 PD505 PLS04 PU3 m 10506 gt 15501 PU502 PD506 PL505 PU4 10507 PUSO3 POWER IN gt gt ADINP DVMAIN gt DVMAINI s pe 13V oed 43V f 3 page 2 Pu PU6 P1 101 P1 P2 154 Pit JO2 PUSOI 155 PONE gt 45V pe gt 5 d qe 515 HDD Discharge U3 5 ALWAYS USBOVCCS 5VS_CD P3 P18 Ul 0505 D USBSVCC5 VCCA 152 P20 P18 153 0505 m J7 PU4 SV PUS PUG 25505 20 504 PL3 P2 L554 1506 PUSO7 10505 gt AVDDAD 12V 12V 12 VS 27 Q509 P22 P27 JO503 27 PL7 PU7 24 JO501 24 L512 Q8 10504 PJ1 J4 PU510 PUSO7 10502 P7 H8 AVREF 5VA 5VAS D VMAIN gt VMAIN s pee Bd P c 41 8VS To next page PUS 10503 Q511 5V P15 P15 117 014 3VA VCC PUS09 122 10504 E 42 5 V P 2 5 DDR Ge Torext rae PL501 PU505 PUSOI PUSOS PL502 PU506 PU502 PUI PUG P26 VCC CORE 8 1 No Power When the power button is pressed nothing happens no fan activity is heard and power indicator is not light up 2 gt 3 5 gt From last page
90. 3V M IDSAB 2 0 Secondary Channel Address 2 0 3 3V M CBLID A B I Primary Secondary Ultra 66 Cable ID 3 3V 5V M Legacy I O and Miscellaneous Signals Signal Name Pin Attr Signal Description SPK Speaker output 3 3V M The SPK is connected to the system speaker ENTEST I 515961 Test Mode Enable Pin 3 3V 5V M OSCI I S1S961 Test Mode Enable Pin 3 3V M Name Pin Attr Signal Description ACPILED OD ACPILED lt 5V AUX ACPILED can be used to control the blinking of an LED at the frequency of 1Hz to indicate the system is at power saving mode EXTSMI I External SMI GPIO3 Uo EXTSMI can be used to generate wakeup event sleep event or 3 3V 5V M SCI SMI event to the ACPI compatible power management unit 1 3 3V 5V AUX When the system is in power down mode an active low event on PME will cause the PSON to go low and hence turn on the power supply When the system is in suspend mode an active PMEZ event will cause the system wakeup and generate an SCI SMI PSON OD ATX Power ON OFF control lt 5 AUX is used to control the on off state of the ATX power supply When the ATX power supply is in the OFF state an activated power on event will force the power supply to ON state AUXOK I Auxiliary Power OK 3 3V AUX This signal is supplied from the AUX power source It is also used to reset the logic in AUX power well If there is no auxiliary pow
91. 4 A 4 GND GND GND GND GND GND 2 TRSFT I0A poste vers FUSE 2917 1202 00 J 4 1 UT pem N 00200 id a 4 090 0608 48518 30520 30519 RLZ24D PRI AK 4 0603 0805 0603 MLL34B PR2 0603 50V 0608 0603 EB E y clo p RU i i PRS08 Took 0603 p put GND1 kpe PQ501 RS 5 LEARNING LEARNING i n ste voc R dus 1 MAXATISFEUT T 010 2850 sv 2 4 50726 1202100 2012 aoe n 516 IL cs17 TOU NA 090 0603 0603 1206 0603 co ov 77 777 77 GND USB ns ue 47K vouto H 0603 2 4 44 VOUT1 8807269 50125 777 1 SBE Ie 9230105 ans ei TS OU 2012 AAA 12V 508 508 n BO 4 t 518 y 11 PR P MINISMDC110 NA 71 2 m js 3 CANSA i 0608 a lel 5 02100 25201 GND2 GND1 L519 GND3 GND2 1 L 2l GND3 777 TAONA 2012 PR510 SUYIN 3 4 DAGET A RO 1 m C520 C521 E P E TK R809 gt 4 PC509 PC503 0603 15K 0603 0603 090 090 SHORTSMTA 0608 0508 50V 50v 10K a 0603 D504 usaoct b USBOCO 1 GND USB SB PSON EUR X X Bawse PRS USBOVCC5 506 Cover Switch 33K
92. 5 0603 SMT 271071105301 RES IM 1 16W 5 0603 SMT 271071105301 RES IM 1 16W 5 0603 SMT 271071222302 RES 2 2K 1 16W 5 0603 SMT 271071249111 RES 2 49K 1 16W 196 0603 SMT PR546 271012278101 RES 2 7 1 8W 196 1206 SMT R14 271071272101 RES 2 7K 1 16W 1 0603 SMT PR9 Location s 578 731 732 733 734 109 116 21 508 553 528 532 720 722 R502 R503 R504 R505 R508 R107 R114 R269 R270 PR19 R556 R95 PR509 PR537 R1 R174 R194 PR509 PR521 PR6 PR7 R528 PR5 PR505 PR539 PR545 PR R552 R558 R672 R674 188 9 Spare Parts List 19 Part Number 271071272101 271071272301 271071200101 271072201101 271071204101 271071203701 271071203101 271071203302 271071215211 271071221302 271071226311 271071223302 271071249311 271071270301 271071202301 271071301011 271071301311 271071324211 271071330302 271071330302 271071333301 271071333301 271071390302 271072302301 271071475112 Description RES 2 7K 1 16W 1 0603 SMT RES 2 7K 1 16W 5 0603 SMT RES 20 1 16W 1 0603 SMT RES 200 1 10W 1 0603 SMT RES 200K 1 16W 1 0603 SMT RES 20K 1 16W 1 0603 SMT RES 20K 1 16W 1 0603 5 RES 20K 1 16W 5 0603 SMT RES 21 5K 1 16W 1 0603 SMT 1 16W 5 0603 5 RES 226K 1 16W 1 0603 SMT RES 22K 1 16W 5 0603 SMT RES 249K 1 16W 1 0603 SMT RES 27 1 16W 596 0603 SMT RES 2K 1 16 5 0603 SMT RES 301 1 16W 1 0603 SMT RES 301K 1 16W 1 0603 SMT
93. 5hr Options 128MB 256MB 512MB DDR SDRAM 9 cell Li ION Battery Pack AC Adapter w o Power Cord Notebook Carry Bag 72 8575 N B Maintenance 2 System View and Disassembly 2 1 System View 2 1 1 Front View Stereo Speaker Set Device Indicators Mini IEEE1394 Connector External Microphone Jack Line Out Phone Jack Volume Control Top Cover Latch 09050000909 2 1 2 Left side View Q Kensington Lock Ventilation Openings RJ 45 Connector O PC Card Slot Hard Disk Drive 73 8575 N B Maintenance 2 1 3 Right side View 9 Battery Pack CD ROM DVD ROM Drive 2 1 4 Rear View Power Connector S Video Output Connector USB Ports Parallel Port D D Fan RJ 11 Connector VGA Port Ventilation Openings 74 2 1 5 Top open View ooo0Q9goococe LCD Screen Microphone Keyboard Touch Pad Power Button Easy Start Buttons Battery Charge Indicator Battery Power Indicator AC Power Indicator 8575 N B Maintenance 75 8575 N B Maintenance 2 2 System Disassembly The section discusses at length each major component for disassembly reassembly and show corresponding illustrations Use the chart below to determine the disassembly sequence for removing components from the notebook NOTE Before you start to install replace these modules disconnect all peripheral devices and make sure the notebook is not turned on or connected to AC power 2 2
94. 6 20 5 2 2 6 200 5 2 1376408 1 1376409 1 GND GND 425V DDRO 2 5V_DDR PLACE CLOSE TO 2508 2 5V_DDR PLACE CLOSE TO 2507 1 1 1 4 4 1 4 J c133 ctas IL 144 c142 1 0139 n C132 C138 c13 10 100 100 040 0 10 gt 6 40 010 610 10 1U 10 100 10 10 10 1210 120 1210 06030 10V 10 lt 0603D 0603D 06030 06030 06039 06030 06030 dov 06030 06030 06030 1 1 1 1 8575 DDR SO DIMMs GND Size lev Document T C Number 411671700010 d later Bheet 12 29 Wednesday January 16 2002 E 12 MD 0 63 12 DQM O 7 12 0950 7 MD32 MD36 MD33 MD37 0054 MD34 MD35 cas 51 52 53 1 25V MD32 RP25 48 1 378 MD36 1 2 EE NE 1 4 C160 0054 5 1000P DOMA 11 6 0603 M34 1 7 MD35 ran 8 GND WE RP26 16 1 338 C163 CASH 1 2 1000P 14 3 0603
95. 777 T R511 swt EE 1 tli L524 5 0609 1 1 MPU 101 6DB R518 1 6 il E 2012 312 1206 0603 C501 5067 413 7 NA 4 1206 ae GND2 UsBOcO 1 so s aD HI 7 GND3 0 a ussoos s um eb use P BUSY TER 48145 45 5 PIPO LS LEARNING SUYIN 444 P LPDO 3 Tus 77 2551A 04GST A pi 40142 41 39 PPD 1 USBPO 1 2 GND USB TRTX 38 P_LPDS P_LPD2 3 USBPO t 4 1202100 SERA 36 38 37 PLPD4 3 1 77 USBPO 34 36 35 LPD5 PLEDI 3 0 1U NA ou ae 088 074 8 31 BPs 3 E 20030 603 Ex USBP1 28 28 27 I P_SLCT 4 509 3 27 ENPBLTI _ 1515 4 2 BEAD USBP1 25 4 iala 23 HS PER 06030 BEER Paro m P 2 BD 3 TV LUMA 20 20 19 19 EA 0805 3002 1008 15 17 PSN NT a BLADJ L513 4 BEAD 4 9 ripe T PELIS ATIS m ph E Beas 114 BHi eare BATT LED AC POWER i s sero 7 7 uspo 4 E d SATT LED 7 gt TS QU 8 7 G 1 4 e 2012 BLADJ ENPaLTI BATUR S 4 UNS Sans ijs Sue 1 fs 30410 mum 403 2 1 USBP5 12 11 15K 15K C505 ad 505 i 1 1 SBPS 3 0609 0609
96. 9 BEN x3 Pao 1206 y prot 1 90 1206 MA 20PX2 ST 1 872184000 777 Layout Note Gree RL RM 5VS S W W S 12 6 6 12 mils DISPLAY LCD LCD ID1 LCD 5 5 i DLE EHE HYUNDAI 0 1 0 a HANNSTAR 0 1 1 vs 354 Ld 6 F502 41 eo mircoSMDC110 NA 1 5VS 5VS Pats PACONOOGINA _ SSOPB 4 1 2 y 2 DDC2B 1 3 22K 22K Close to VGA Connector WW 5 0605 4 7 ent pen gt ORT RED RUNE unguem 1008 A CRT GREEN 1 2 _ 1608 2 7 CRT GREEN gt W S 16 12 12 12 16 mils 1 10 7 ont puue gt NE 2 usottdbz agom 1608 1 tin a Lk I VGA 38 4 B 055 34 16 i 6 gt 5 75355 1502 05 7 DODA CRIDDDA Fle 1 Js ES c 0502 2NT002 D 1 1 1 1 15 E L i 4 P 58 7 CRT HSYNC 5 Ig D 1 us 2N7002 2 ia ibs 5949 3VS F zw n EN VSYNC D 22 4 T 1206 7 1206 7206 1206 Es J 2N7002 Lil Iro ae A pock l SHORT SMTS Bac NR 7 CRI DOCK A 4 ke 2N7002 1 2 e EP SHORT STS 4 CRT 15 ei 0603 8575 LCONGA INTERFACE amp LEDs Document 411671700010 0 Number Date Wedne
97. 9 1 807 1 M 12 777 05 Be 515 042 TP 4 0603 1 1 GND TP GND 5 5VS i ITI TP GND i TP_ ND1 4 MTG19 MTG18 to 10220055 10220055 i 32 f MTGIID2 20056 ou E swe 0603 MEMR MEMR 17 22 1 SCRL_DOWN1 HN 50 _ pm RIGHTT t e 1 SCRL 16 5 VSS i RIGHT maru 8575 T P BRD E ES TC010 PSs11CET B T i T SW_STS 042A 4 TP STRAP OPTIO p RAP N i 1 SCRL DOWN SCRL TP 1197 tat E XCNF2 XCNF FUNCTIONALITY 24 Mon cose Ceri oe ee 12 50 0 0 NO BIOS TC010 PSs11CET B T i T SW_STS 042A 2 e 1 x 0 1 NORMAL MODE XRDY DISABLE i swio 0 1 0 LATCH MODE 12 19 XRDY ENABLE 3308 1 1 927 1 SCRL ex i 4 1 1 0 LATCH MODE GPIO 10 17 XRDY ENABLE sp 0 1 1 LATCH 12 19 XRDY DISABLE 5 NEONA iSHCET 1 1 LATCH MODE GPIO 10 17 XRDY DISABLE l1 cre 477 54 515 0424 GND1 640 010 040 TP 1 swit BASE ADDRESS SELECT sov sov sov sov Mg SCRL Schr O603DA 0603DA 06030 0603DA 1 jar 1 DOWN R303 INDEXREGISTER DATAREGISTER a om tes P Page 557 _ 0 3 777 LPD 0 7 MOUNTED 4H 15 AD O 3 D 8588 PIPDD Z 7 17 SMS em OPEN 2
98. BE 8042 IDE_SDA2 17 17 18 28 29 PCI_DEVSEL DEVSEL IDSAB H IDE SDAi 17 17 PCI PLOCK AL 11 CLK SBPCI 2 1 mer DE 306338 500588 47 7 9 17 18 21 28 29 PCIRST PCIRST IDECSBO 80 51 17 EM IDE DES uA ues redi gen ea IDA2 i 1 8VS n zou gt ______ 20 ze IDA IDAS i RP516 7 ZSTBO 25180 ZSTBO IDAS any i 7 ZSTBOR ZSTBOR IDA IDAB 26 1 2 25781 7 ZSTBi zsTB1 10 9 i 251808 3 2 7 25 1 251818 ZSTB1 1DA10 4 10 11 i 2A IDA12 i ZUREQ 7 zuREQ SuREQ N15 zuREQ IDA13 i GND 7 ZDREQ ZDREQ ZDREQ 10 14 15 Place near to 961 chip SUME VDDZCMP IDBO 17 SZzCMPN ____ ZCMP_N 1081 T 6 1082 SZCMP P R18 ZCMP P 1083 SVSszcMP pia e VSSZCMP 1084 1085 1086 SZIXAVDD ZIXAVDD 1087 SeXAVSS 09 Z1XAVSS 1088 1089 SZAXAVDD ZAXAVDD 10810 ___874 5 ____119 Iun ZAXAVSS 10811 10812 SZVREF R20 ZVREF a grygy 1DB13 SAVSSREF ZVSSREF B85883888588555555 IDB14 10815 UH IDE 5000 15 17 7 515961 BGA335 36 7 ZAD O 15 8 ion 18 8 E 3 5 3 5 SVDDZCMP 24 SZAXAVDD TES 1 SZ1XAVDD 2 1 1 1 4 R605 56 0603 1202 100 1202 100 1202 100 R109 c202 SZCMP N 4 4 2012 4 4 2012 4 4 2012 4 150 010 C592 C642 L C697 C212 C206 C
99. C705 1 2 _ 06030 DON EL s T 2072 0508 ZCLKo cni 1 06030 37 1 50V 50 GNDA t 1202 100 S ZCLK1 C718 4 10P NA __ 0603D 1505 019 15952001 0603 lt 7 SSOP48 CLK_SBPCI C724 1 1 06030 50 CLK_LPC33 2 10P NA _ 06030 AGP C721 4 2 10P NA _ 06030 2 CARDPCI C720 4 1 06030 3 SMBCLK R836 1 AJ 0603 t REFCLK3 C703 4 10PNA 06030 3Vs SMBDATA _ 8837 1 2 0603 14 318MHZ 14 318 2 AUDIO C92 1 10PNA 06030 4345 REFCLKO C704 1 2 10P NA 06030 1 1 0603 0603 REFCLK1 C706 1 2 10P NA 06030 1 1 2 VDDPCI C85 C109 2 USBCLK SB C722 1 06030 4 3 5 1210 1202 100 C98 C108 9 10V 50 C725 1 10P NA __ 0603D 1 1608 0 1U 146 GND 0603 0603 i002 VDDCPU 14 318MHZ TV C89 1 10PNA 06030 50 50V Layout note Place crystal within du 1 11102 Xo 500 mils of CLK Gen I cos gt CLK MINIPCI C813 4 2 10P NA _ 06030 i F ou 0603 0603 50 50 WZ u9 SMBCLK pem pure 16 R99 4 22 BF OUT BF OUT 4 2 10 06030 SMBDATA SDATA L2 R90 1 0 CLK DDRO Bi2 Bi7 Bite Bit4 BitS cpu 0 zek BFOUT 20 ROV 1 0 42 Sk DORN 54 53 FS2 51 FS0 MHz MHz
100. CBL 777 JP BEAD DFS 777 50125 777 1507 USBP3 1 2 2 UsBPS t 1 TZoZA0WNA T t 5 8 2012 F502 m 0501 4188 MINISMDC110 NA 3 2 3 1 2 413 002 100 GND1 ORE AGM2520U GND2 GND1 rer GND2 USBP3 NDS 2 USBP3 4 2 P_STB USB APX1 P 2012 SUYIN 2 PPD Ene doe 2551A 04G5T A a R503 10501 15K R502 2 0603 15 0603 po 0603 SHORT SMT4 PP LPD1 PE 7 GND USB GND USB 1206 R1 1 LPD3 0 0603 2 USBOC3 USBOC3 5 2 USBOC3 5 1284010 QSOP24A BAWSG S ag S 5 04 50 2 P LPD4 Peat bbe USBOCS i 2 PLLPDS a h 2 PLLPDS RB 17021500 2 2 J 2012 3 0603 C524 4 PIO GU NA GND 102 7536S 25G2T 640 102 1206 SUYIN dov P BUSY POPE 777 7 PLSLCT GND USB USBI4PX1 L521 STI T i USBP5 A 1 4 GND USB 2 120Z 100M NA s i 2012 Layout note PACI294010 Same legth QSOP24A GND 102 GND 102 USBPO i 622 3 USBPO 002 100 edd aur mS 2 52 elm ORE 25201 USBP5 11 2 MSBPS 120Z 100M NA GND J 2012 R513 Q R514 15K 15K C526 10 0603 lt 0603 ATPIN 0603 0603 10 4 Smil 77 USBP 77 GND USB ES ER EAD ML ME Smil USBP savs Smil 10 1 2 7 1 2 i 2 10 lt gt Rig S206 1 2
101. CORE EN 26 3 Geta 2 GNp NGCEVID VCCPVID 4 i Wess Em 2E 77 77 gt We 8575 PENTIUMA 2 2 ize Document 24 Number 411671700010 Dale Wednesday January 16 2002 5 oi 2 1 AHSYNC R36 1 22 VAHSYNC S VAHSYNC 9 502 FC VBD o 11 9 VBD11 VBD10 FC_VAD 0 11 9 VBDO VAI ven VADI 1300HM 100MHZ VADS 1300HM 100MHZ 505 AVSYNC 837 1 222 VAVSYNC S V VSYNC 9 1800HM 100MHZ 3 6 1800HM 100MHZ L14 1 CPUAVDD EE 1202 100 2012 1800HM 100MHZ 1 1800HM 100MHZ 6 22 VBHSYNC 0603 0603 1206 P7 BHSYNC R29 1 D VBHSYNC 9 q 507 10 1206 2P AINA AE 1500 1206 cruavss 4 JP_NET20 GND 3 5 115 GD gt PHYAVDD 1 2 t BVSYNC R24 1 A A 2 22 VBVSYNC 1202 100 4 292 J 00107 S 100 0603 0603 1206 4 50V 10V 1502 taa JP_NET20 lt gt GND UA di 8253384 BCLK R23 1 4 gt vec 9 VCC CORE gt r9eo owouocoo HES x
102. I O Controller Power and Ground Signals 8575 N B Maintenance General Purpose I O Signal Name Pin Attr Signal Description GPIO 6 0 Uo GPIO 3 3V 5V M Can be a general purpose input or output GPIO14 12 7 3 3 5 AUX Can be a general purpose input or output GPIO13 3 3V 5V AUX Can be a general purpose output GPIO 18 15 3 3V 5V AUX Can be a general purpose output GPIO 20 19 GPIO 3 3V 5V AUX a general purpose input or output Name Tolerance Power Plane Type Attribute VSS oV GROUND Di gital VSSZ GROUND Digital IVDD 1 8V MAIN Digital PVDDZ 1 8V MAIN Digital VDDZ 1 8V MAIN Digital VDDZCMP 1 8V MAIN Analog VSSZCMP OV GROUND Analog ZVSSREF OV GROUND Analog PVDD 3 3V MAIN Digital OVDD 3 3V MAIN Digital VTT 1 1V 2 65V MAIN Digital IVDD AUX 8 AUX Digital PVDD AUX 3 3 AUX Digital OVDD AUX 33V AUX Digital MITAVDD 3 3V AUX Analog 55 OV GROUND Analog USBVDD 3 3V AUX Analog USBVSS OV GROUND Analog RTCVDD 3 3V RTC Analog RTCVSS OV GROUND Analog ZIXAVDD 3 3V MAIN Analog ZIXAVSS OV GROUND Analog Z4XAVDD 3 3V MAIN Analog ZAXAVSS OV GROUND Analog IDEAVDD 1 8V MAIN Analog IDEAVSS GROUND Analog 118 8575 N B Maintenance 5 4 SiS301LV Chrontel CH7019 TV LVDS Encoder Pin Type Symbol Descrip
103. J 0603 TK 1 i 507 c 508 Pott lt 0603 Bsta 41 TOQU NA 1500 INTVCC2 12 Ar 1 1948 7343 100 PRO 1000P ONA PD1 63V 1210 PR10 41 2 4 cm 0603 s 100604 SENSE1 10 1 2 0603 1 28 1 2 PD2 27K 0603 11 10 sgnseT RUNS 27 asa SENSEI pow NSET 3 26 p 1000P NA 0603 1 SENSET wt 0603 VOSENSE1 25 PC16 _ 0 010 060 1 6 P recs Mal 1 PC17 33P NA 50 Bet 0603 1 1 ma 21 INIVCC2 Psat PRI3 15K 0603 1 M T 1 0 010 te PCIE 2205 0603 10 5580 GND pi 2 50V E E dr E ra EX P22 33 112 1 YOSENSE 542 16 sv 125 0603 220P 14 1 0603 16V GND PUSOT oats SENSE2 RUNISS2 P XU PC24 x 10002 2 412 E 908 5 PUS 10 25 5 26549 PC550 Sl4t6DY 1000 10 1000P P_ON 5 508 T 25V 0603 0805 25V 1 DHS 4 20 50 25V i PC26 id 4 orem PRIS 0603 0905 PRIG 10 1 EUN 1 p21 sd PL3 o 2512 4 1 18 7 PC28 53 6K 1000P NA 5 Pus 0603 0603 5 81 1 508 J J 05 4 PC29 pest PDA 1500 1500 n 100 Ectoasos FR AN 7343 1210 s 83V 6 10V prio 10K 1000P NA 0603 0603 1 251 1 SHORT SMT1 FBS EY ES 20505 2 OPEN SMTA E E
104. LCD LOWER 8175 346 69900004 SULATOR INVERTER 7170 310 102010407 310 102610603 PC SCREW M2 6L6 K HD NIB NLK 42 11600006 RE ASSY LCD UNIPAC 14 XGA 8115 2 421 11600010 IRE AeSTSINVERT STTS 310 102030301 B B R R SPC SCREW M2L4 K HD NIB NLK 5 W W 5 PC SCREW M2L3 K HD NIB 242 64800013 LABEL CAUTION INVERT BD PITCHING 310 102610401 SPC SCREW M2 6L4 K HD 10 8 NIB NLK 343 611600014 AL FOIL HST PANEL I15 X64 8175 42 11100002 WIRE ASSY ANTENNA 85 75 DATE 19 Jun O2 MATERIALL SEE NOTES TREATMENT REMARK 2 C B D Model name 8515 ASSY L1CD File name 8575 ASSY LCD PDF created with FinePrint pdfFactory trial version http www fineprint com NN a unit SCALE 0 050 DRAWING NAME LCD ASSY QDI XGA 14 103 85175 Es _ DRAWN DESIGNED CHECKED APPROVED MATERIAL NO AD 441611120033 nfernational Corp SHEET OF PART NO RIPTION REMARK 411503400201 SPWA STINGRAY INVERTER BD MSL 41300002031 7 L D 150PXII B TFT 15 LVDS XGA HANNSTAR 340671600017 SS PE EP 340671600019 eg me Verf 340671720009 Based LS S DSTI 342611600004 15 8175 342
105. MHz MHz 7 FWDSDCLKO FWDSDCLKO CLK INT PENA C104 1 2 10P NA 06030 4 12 91010 0 66 67 66 67 66 67 66 67 CBVDD 5 1 2 0 CEK DORTE GC 12 CLK DDROR C105 1 2 10P NA _ 0603D 4 VDD1 o o 1 100 00 100 00 66 67 66 67 as Ros ganap 0 CLK 12 CLK DDR1 4 2 1 06030 CBVDDA _________10 vDDA 2 0 0 0 1 0 100 00 200 00 66 67 66 67 CLK_DDRI C102 1 2 10P NA _ 06030 100 00 133 33 66 67 66 67 cues Ret 5 CLK DDR2 C135 40P NA 06030 GND1 HE 1 DDR3 amp 12 1112 4 GND2 o o 1 o 100 00 150 00 60 00 60 00 ws 2e Rigo g ng 9 CLK_DDR2 cis 1 2 10PNA __ 06030 4 1 0 1 100 00 125 00 62 50 62 50 2 CUS DORAR 12 CLK_DDR3 195 1 2 10 _ 06030 4 R626 1 2 47K FSO GND 18 26 R102 1 2 0 DDR5 i 0 1 0 100 00 160 00 66 67 66 67 REZA 1 AAAS ATK ud 59 cies 27 103 1 AA 2 0 CLK DDR5F 12 CLK_DDR3 C194 1 2 10P NA 06030 4 0 0 1 1 1 100 00 133 33 80 00 66 67 R669 1 47K FS3 1CS93722 CLK C197 1 2 10P NA 06030 4 R650 1 FS4 SSOP28A 100 00 200 00 66 67 66 67 CLK_DDR4 C198 1 2 10PINA __06030 4 0 1 0 0 1 100 00 166 67 62 50 62 50 CLK DDR5 C199 1 2
106. N B Maintenance 9 Spare Parts List 10 8575 ID5 14 Part Number 541667170001 343671600014 441999900062 442671700002 340671600026 221671640001 342671600007 342671600005 221669950008 221669950006 221671220002 431671710001 451671600031 340671600012 340671600029 340671600034 340671710001 344671600042 344671600046 323760000011 344671600043 523430061901 523467160014 227671600001 523411442518 beresomumuamnam Bassa bmmwovmmamam wmm SSS COVER ASSY LCD 14 ID1 2 8175 35 Exams bananas ooo 8575 ID5 14 Description Location s 180 8575 N B Maintenance 9 Spare Parts List 11 8575 ID5 14 Part Number 461671600002 227671600003 224670830002 221671650001 221671650008 221671650005 221671650006 221671650004 221671250003 221671650007 222668820001 332810000033 565180626001 561860000022 370101714501 370102610401 370102610801 421671600006 PACKING KIT N B 14 1 8175 ease pamorna osme Pe anc
107. O Conect Controll pins 18 ZSTB 1 0 Lo Megaband I O Connect Strobe 18 ZSTB 1 0 vo Strobe Compliment 1 8 ZAD 15 0 VO Address Data pins 18 ZVRE I M Megaband I O Connect I O reference voltage ZCMP N I M N MOS Compensation Input ZCMP P I M P MOS Compensation input PCIInterface Continue Name Pin Attr Signal Description FERR I Floating Point Error 1 1V 2 65V M CPU will assert this signal upon a floating point error occurring IGNNE OD Ignore Numeric Error 1 1V 2 65V M IGNNEZ is asserted to inform CPU to ignore a numeric error NMI OD Non Maskable Interrupt 1 1V 2 65V M A rising edge on NMI will trigger a non maskable interrupt to CPU INTR OD Interrupt Request 1 1V 2 65V M High level voltage of this signal conveys to CPU that there is outstanding interrupt s needed to be serviced APICD 1 0 VOD APIC Data 1 1V 2 65V M two signals are used to send and receive APIC data CPUSLP OD CPU Sleep CPUSTP 1 1V 2 65V M The CPUSLP can be used to force CPU enter the Sleep state CPU Clock STOP For Intel Mobile processor this signal can be used to stop the clock to the processor If the processor is in Quick Start state and the processor clock is stopped the processor will enter the Deep Sleep state For AMD processor this signal can be to reduce processor voltage during C3 S1 state STPCLK OD Stop Clock 1 1V 2 65V M STPCLK will be asserted to inhibi
108. P LPDO mU RESO 16 USB 1 LID 22 21 16 USB_OC3_5 LLIMIT 22 21 PLLPD2 1206 ME LEARNING 22 21 pee 21 FIRSEL ARA 04 TRRX 21 P LPS DP LPD6 1206 21 IRRX IRTX 21 PLLPDS 21 Io ck 21 DP SLCT RP504 21 PLSLCT D on 16 USBPO 1721 P_STB rA 16 USBPO 21 PAFD Ie ERR 21 PERR E bsp 16 USBP1 1721 ee d 16 USBP1 21 P ACK DP ACK 1206 9 ZU PRUSY 0603 R501 DP PE 9 TOUMA 16 USBP3 AC POWER 10 16 USBP3 BATT LED 10 5VA BATT G 10 5 5 BATT R 10 22 BLADJ ENABKL 922 NS PWR ON 2224 C504 10 15 24 PSON USBP5 16 UA USBP5 16 5 FM 22PX2 1 27 06 0110 441 SPEED cb CP504 505 5 22P 2 4 2 4 22P 4 1206 1200 1206 1206 4 1 2 0 5VS 5V0 t 2 3150 t i Lu 43V O t 1 Hz ALWAYS 1 2325 ADINP 1 1 He j DyMAIN1 QVMAIN 19 0 4 HDR OPX2 H8 4 4 1 2 56502 100 100 1210 1210 m 16 16 GND PHIPS D RA 44 X X CEN GND GND GND ADEN 22 23 MTG26 1D2 8 0D7 6 MTG27 1D2 8 0D7 6 Mitac gt 8575 DID CONN amp MISC Document 411671700010 OA Number later Bheet 27 o 28 Wednesday January 16 2002 E PCI AD21 PCI INTD REQ2 GNT2 MINI PCI amp BLUETOO
109. PCI 0 3 CARD PMEZ PCI REQO SERIRQ CARD_RI un 4 PCI FRAME 27 PCI IRDY VCCENO PCI TRDY VCCENI PCI DEVSELZ VPPENO Try another known good PC card device PCI STOP 1 Re test Change the faulty PCI INTC AA OK part then end PCIRST VPPA No PCI GNTO PCL PAR PCI PERR 167 8575 N B Maintenance 8 13 PC Card Socket Failure An error occurs when a PC card device is installed R249 10K 3VS o R785 0 VCCA o L coo 3VS R223 10K C27 CARD RI gt 020 DTC144WK CLK_CARDPCI gt gt From 0508 Clock Generator TE PCI AD 0 31 P15 R789 PCI AD20 100 014 gt PCI C BEA 0 3 MuTIOL PCI DEVSEL PCI FRAME PCI_IRDY gt 5 Media I O PCI_TRDY PCI 8 PCI PAR PCI PERR amp Controller PCI SERRA PCI REQ0 CARD SERIRQ 515961 PCIRST PCI GNTOR R793 gt PCI INTBA 0 SUSPEND AUX_VCC PCI VCC 0 3 CORE VCC 0 5 SKT_VCCO 1 D U513 PCMCIA Controller 1410 IDSEL 5VS 3VS 0 4 12VS VCCA 3 4 5 6 9 VCCENO 17 51 1 11 13 e e VCCENI 2 0505 10 18 52 VPPENO 15 TPS2211 C684 C662 C650 C661 VPPENI 14 0 1 0 1u e e 77 0 0 31 CAD9 R219 0 CADI2 R220 0 CCBE 0 3 CFRAME CIRDY CT
110. RES 32 4K 1 16W 1 0603 SMT 1 16W 5 0603 SMT 1 16W 5 0603 SMT RES 33K 1 16W 596 0603 SMT RES 33K 1 16W 596 0603 SMT RES 39 1 16W 596 0603 SMT RES 3K 1 10 5 0603 SMT RES 4 75K 1 16W 196 0603 SMT un S un amp un Location s PR531 R86 R87 R544 R PRI8 g PR12 PR519 R679 R719 R721 PR526 R117 R118 R119 R129 R130 PR551 R4 PR547 R509 R577 R727 R728 R835 R12 R62 PR564 R2 R3 R506 R7 PR16 PR552 R697 R532 R739 PR511 Z o an o e 1 N Part Number 271002472301 RES 4 7K 1 10W 5 0805 SMT PR516 271071472302 271071499111 271071471302 271071474301 271071474301 271071475011 271071473301 271071473301 271071487311 271071499811 271071518301 271071512101 271071562301 271071510301 271071511812 271071513301 271071536211 271071560101 271071560301 271071576311 271071604111 271071619111 271071681111 271071682301 8575 N B Maintenance Description RES 4 7K 1 16W 5 0603 SMT RES 4 99K 1 16W 1 0603 SMT RES 470 1 16W 5 0603 SMT RES 470K 1 16W 5 0603 SMT RES 470K 1 16W 5 0603 SMT RES 475 1 16W 1 0603 SMT RES 47K 1 16W 5 0603 SMT RES 47K 1 16W 5 0603 SMT RES 487K 1 16W 1 0603 SMT RES 49 9 1 16W 1 0603 SMT RES 5 1 1 16W 5 0603 SM RES 5 1K 1 16W 1 0603 SMT RES 5 6K 1 16W 5 0603 SMT RES 51 1 16W 596 0603 SMT RES 51 1 1 16W 1 0
111. S1 No M 135 8575 N B Maintenance Contents IVA Display E 141 8 3 VGA Controller Failure LCD No Display En ERE SOR EROR 145 8 4 External Monitor No 1 147 52 Memory Test EPPOL us eie e rer Ert Bei PU vetera ote a oe te b ee epis eas Ute 149 8 6 Keyboard K B Touch Pad Test Error 5 2 25 0 151 5 7 Hard Disk Drive Test Error pedo c dure t vea em ddp 153 5 5 CD ROM Driver Test Biron eoa Eon Ron PVP Cao CECI 155 8 9 USB Test TOC Ghavemeds 157 5 10 PIO Port Test EEEOE ioo o deo VELA CPU S Det E UA Per OPER TA T HU ANE 160 HER A dio TAME ern 162 SZ LAN Test 165 S PC Card Socket Failure loins hols poe chats slew odas Ni beue euge 167 8 14 IEEE Papas 169 9 Spare Parts List iieri Eu ta e Es Rav pase dee 171 10 System Exploded Views 2er REN VE M eee deters RE NEU
112. SAIS i 4 Ah osos 0 1206 SAB RET 4 i onor 21 SA9 1206 R44 GNI 5 6 21 SAS SA10 3 amp i GND y se 21 SAU SATI 0603 21 gain 5 FMIZSPXZRUA pod i sate qe 21 sate 4 i E EE X MD emt svs 21 SA18 41 1 21 Sato 51 186 SHORT SMT3 Mou AB 3208 sposa PE 4 1 IRQ1 4 10 Tie 2122 ROZ r 8575 IDE INTERFACE amp PULL UPs 2122 m r don Mes 2122 SHORT SITS MEMR T Tr TOW ky ize 21 MEMR low 2122 Document T UM 6 ESTE SSW 202 pocument 411671700010 0 5 2 Date Wednesday January 16 2002 Sheet 17 of 29 1410 vs AD20 4 4 R784 2 785 ona 50 ouod Em m VCCENO REQO GNTO R216 1 VOCENT 7 9 14 17 21 28 29 PCIRST VEPENO SIGNAL PCCARDPULLUP VOLT 0603 VPPENT avs BV CBLOCK CARD CARD VCC CDEVSEL CARD VCC veca CTRDY CARD VCC 0603 90 BV 4 CRST CARD 8555 us c203 CSERR CARD VCC 272010 co CPERR CARD VCC TEREFE a EET G13 IRDY n 5555 3235232 2 8922 LA CREQ CARD VCC 5555 5 552 CSTSCHG CARD VCC 142829 PCLAD O 31 2828 2 5885 Ghosh e
113. SDN 15 3 5 J a s pam 5 22 4 J A cm ni B RIT 1 15 20 GND SHIELDING 10 R46 R41 10 0 8 2 4 je l3 1 56 56 0603 179373 4 S W WIS 12 6 6 12 mils 0603 oau C209 i 1 TOPINA il ERA ETE QS GEM 0603 IDCSCREWHOLE __ __ as short as possible 4 1 10 PURX 4 4 4 R39 1 11 PJRX 30508 g i SHORT SMT3 RE z 1 14 pue 102800050 40509 4 1 R30 1 102800050 018 91 PIN 16 AUDIO CODEC ON MOTHER BD AUDIO CODEC ON DAUGHTER BOARD 2 1 1 5 lt gt CHOKE PLP3216S 1 T 1202100 can PLP3216S 1608 i p 1000P E 18088 H nid RJ11 5 5501 T m 14 gt 2 0 0603 1808A 2 SHORT SMT4 m SABE ow HIROSE DFI3 2P 1 25V S Hh 1000 OCTEKCONN 1808B PJS OXSXT 4 8575 LAN PHY 51 9 amp MDC Document Date Wednesday January 16 20025 19 29 1
114. The Integrated Audio Controller features a 6 channels of AC 97 v2 2 compliance audio to present 5 1 channel Dolby digital material or to generate stereo audio with simultaneous V 90 HSP modem operation Besides 4 separate SDATAIN pins are provided to support multiple audio Codecs one modem Codec maximally effectuating the realization of 5 1 channel Dolby digital material in theater quality sound Both traditional consumer digital audio channel as well as the AC 97 v2 2 compliant consumer digital audio slot are supported VRA mode is also associated with both the AC 97 audio link and the traditional consumer digital audio channel The integrated Fast Ethernet MAC features an IEEE 802 3 and IEEE 802 3x compliant MAC supporting full duplex 10 Base T 100 Base T Ethernet 1Mb s amp 10Mb s Home networking 5 wake up Frames Magic Packet and link status change wake up functions in G1 G2 states are supported Besides the integrated MAC provides a scheme to store the MAC address without the need of an external EEPROM The 25 MHz oscillating circuit is integrated so as only an external low cost 25 MHz crystal is needed for the clocking system 8575 N B Maintenance The integrated Universal Serial Bus Host Controllers features Dual Independent OHCI Compliant Host controllers with six USB ports delivering 2 x 12 Mb s bandwidth and rich connectivity Besides each port can be optionally configured as the wake up source Legacy USB devices as well as
115. When is deasserted the PCI bus transaction is in the final data phase GNT PCI bus grant GNT is driven by the PCI bus arbiter to grant the PCI1410 access to the PCI bus after the current data transaction has completed GNT may or may not follow a PCI bus request depending on the PCI bus parking algorithm IDSEL Initialization device select IDSEL selects the PCI1410 during configuration space accesses IDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus IRDY Lo PCI initiator ready IRDY indicates the PCI bus initiator s ability to complete the current data phase of the transaction A data phase is completed on a rising edge of PCLK where both IRDY and TRDY are asserted Until IRDY and TRDY are both sampled asserted wait states are inserted PERR T O PCI parity error indicator is driven by a PCI device to indicate that calculated parity does not match PAR when PERR is enabled through bit 6 of the command register REQ PCI bus request REQ is asserted by the PCI1410 to request access to the PCI bus as an initiator SERR PCI system error SERR is an output that is pulsed from the PCI1410 when enabled through bit 8 of the command register indicating a system error has occurred The PCI1410 need not be the target of the PCI cycle to assert this signal When SERR is enabled in the command register this signal also
116. Y 306 2 5 9 8515 OPTION 4 611700 PWA PWA 8575 MOTH ER BD 523461160 DV RO 5 8X SDR 081 QUANTA 8115 OPTION 44 999900 BAT SSY OPTION LI 9 CELL 8575 OPTION 340 611100 HO S G ASSY 8575 340 671600 COV ER ASSY DIMM 8175 69 310 03010 SPC SCREW 3L6 NIB K HD 10 8 NYLOK 310 02030301 SPC SC REW M2L 3 NIB NL 0 310 02610401 SPC SCREW 2 6L4 K 10 8 NIB NLK 29 310 02010309 5 SC REW M2L3 IW NLK HDO 310 02010401 SPC 56 REW M2L4 I NIB 3211 244010 DOFF 4 40DP3 5H5L5 5 NIW 311 02011502 EW 2LIS FLTCE N 310 02610603 SPC SC REW M2 6L 310 02610302 SPC SC to REW LOK 346 5 5 02 5 5 5 61170002 S LA TOR Ww gt Po 310 02610801 SPEE SCREW 2 6L 1 340 671200020 AS 51 81170 340 611200013 EW ASSY CPU 81 10 Sui 42161 600051 MIC ROPHONE ASSY 8175 34561 100019 645 MIC 8515 34561 100009 GAS BRACKET 8575 gt 7 Jun O2 MATERIA
117. available in two 16 pin small outline packages AC 97 interface on PCT303A and phone line interface on PCT303W The chip set eliminates the need for an AFE an isolation transformer relays opto isolators and 2 to 4 wire hybrid The PCT2303W chip set dramatically reduces the number of discrete components and cost required to achieve compliance with international regulatory requirements The PCT2303W complies with AC 97 Interface specification Rev 2 1 8575 N B Maintenance The chip set is fully programmable to meet worldwide telephone line interface requirements including those described by CTR21 NET4 JATE FCC and various country specific PTT specifications The programmable parameters of the PCT2303W chip set include AC termination DC termination ringer impedance and ringer threshold The PCT2303W chip set has been designed to meet stringent worldwide requirements for out of band energy billing tone immunity lightning surges and safety requirements Operating System Compatibility Windows 98 NT4 0 Win 2K Win XP Compatibility ITU T V 90 56000 54667 53333 52000 50667 49333 48000 46667 45333 42667 41333 40000 38667 37333 36000 34667 33333 32000 30667 29333 28000bps K56Flex 56000 54000 52000 50000 48000 46000 44000 42000 40000 38000 36000 32000bps ITU T V 34Annex 33600 31200 bps ITU T V 34 28800 bps ITU T V 32bis 14400 bps ITU T V 32 9600 4800 bps ITU T V
118. bytes INPACK Input acknowledge INPACK is asserted by the PC Card when it can respond to an I O read cycle at the current address DMA request INPACK can be used as the DMA request signal during DMA operations from a 16 bit PC Card that supports DMA If it is used as a strobe then the PC Card asserts this signal to indicate a request for a DMA operation WE Write enable WE is used to strobe memory write data into 16 bit memory PC Cards WE is also used for memory PC Cards that employ programmable memory technologies DMA terminal count is used as TC during DMA operations to a 16 bit PC Card that supports DMA The PCI1410 asserts WE to indicate TC for a DMA read operation IORD read IORD is asserted by the PCI1410 to enable 16 bit I O PC Card data output during host I O read cycles DMA write IORD is used as the DMA write strobe during DMA operations from a 16 bit PC Card that supports DMA The PCI1410 asserts IORD during DMA transfers from the PC Card to host memory IOWR write is driven low by the PCI1410 to strobe write data into 16 bit I O PC Cards during host I O write cycles read IOWR is used as the DMA write strobe during DMA operations from a 16 bit PC Card that supports DMA The PCI1410 asserts IOWR during transfers from host memory to the PC Card WP LOIS16 Write protect WP applies to 16 bit memory PC Cards WP reflects the status of t
119. current mode and are designed to work with external 112 line termination resistor networks in order to match the 110 cable impedance One network is provided at each end of a twisted pair cable Each network is composed of a pair of series connected 56 resistors The midpoint of the pair of resistors that is directly connected to the twisted pair A terminals is connected to its corresponding TPBIAS voltage terminal The midpoint of the pair of resistors that is directly connected to the twisted pair B terminals is coupled to ground through a parallel R C network with recommended values of 5k and 220pF The values of the external line termination resistors are designed to meet IEEE Std 1394 1995 when connected in parallel with the internal receiver circuits An external resistor connected between the RO and terminals sets the driver output current along with other internal operating currents This current setting resistor has a value of 6 34k 1 096 When the power supply of the TSBA1ABI is off while the twisted pair cables are connected the TSB41AB1 transmitter and receiver circuitry presents a high impedance to the cable and does not load the TPBIAS voltage at the other end of the cable Fail safe circuitry blocks any leakage path from the port back to the device power plane 33 8575 N B Maintenance The TESTM SE and SM terminals are used to set up various manufacturing test conditions For normal operation the TES
120. e e e C861 C235 C863 C239 C241 C252 e 1394PCI From U508 Clock Gen s PCI AD 0 31 Pis R231 PCI AD22 100 PCI C BEA 0 3 lt MuTIOL PCI DEVSEL PCI FRAME PCI_IRDY Media PCI_TRDY PCI 8 PCI PAR PCI lt Controller PCI SERRA PCI 19 1394 PME lt 515961 PCIRST PCI_GNT1 R224 PCI 9 lt U18 IEEE 1394 Controller uPD72872 IDSEL J27 3VS R86 R87 R236 2 7K 2 7K 0 SDATA SCLK U7 NM24C02N 2242 0 C93 L R225 IM 0 1u 7 1 2 2 4 2299 e C300 T 22 X6 T 2P di 24 576MHZ R198 0 4 R197 0 3 R196 0 2 TPB R195 0 1 R241 R243 R238 R240 56 56 56 56 2 15506 GNDI 2 51 59 C303 C304 C302 1 R239 0 011 0 01 270P T 5 1K 1394 GND 19205 7651 170 8575 N B Maintenance 9 Spare Parts List 1 8575 ID2 14 Part Number 343671600014 AL FOIL HST PANEL_15 XGA 8175 227671600001 END 14 1 8175 Po 8575 ID2 14 Part Number 340671600035 451671710001 346671700021 340671700014 451671700032 242671700001 242600000157 242669900009 441671710031 451671710052 413000020289 416267171901 41626717100
121. for a single PC Card of the discrete power MOSFETS a logic section current limiting and thermal protection for PC Card control are combined on a single integrated circuit using the Texas Instruments LinBiCMOS process The circuit allows the distribution of 3 3 V 5 V and or 12 V card power and is compatible with many PCMCIA controllers The current limiting feature eliminates the need for fuses which reduces component count and improves reliability Current limit reporting can help the user isolate a system fault to the PC Card The TPS2211A features a 3 3 V low voltage mode that allows for 3 3 V switching without the need for 5 V Bias power can be derived from either the 3 3 V or 5 V inputs This facilitates low power system designs such as sleep mode and pager mode where only 3 3 V is available End equipment for the TPS2211A includes notebook computers desktop computers personal digital assistants PDAs digital cameras and bar code scanners 29 8575 N B Maintenance Features Fully Integrated and V Switching for Single Slot PC Card Interface Low 70 m 5 Switch and 3 3 Switch Compatible With Industry Standard Controllers 3 3 V Low Voltage Mode Meets PC Card Standards 12 V Supply Can Be Disabled Except During 12 V Flash Programming Short Circuit and Thermal Protection Space Saving 16 Pin SSOP DB Compatible With 3 3 V 5 V and 12 V PC Cards
122. fourteen screws on the bottom of the notebook Figure 2 20 3 Remove nine screws fastening the base unit cover figure 2 21 Figure 2 20 Remove the bottom Figure 2 21 Remove the speaker assembly 89 8575 N B Maintenance 4 Lift up the base unit cover and disconnect the touch pad cord Figure 2 22 5 Remove the four screws fastening the base unit Figure 2 23 Figure 2 22 Remove the base unit cover Figure 2 23 Remove the metal shield 90 8575 N B Maintenance 6 Carefully put the notebook upside down 7 Remove four screws fastening the system board and disconnect the cables Figure 2 24 8 Lift up the system board and disconnect cable Now you can remove the system board Figure 2 25 Figure 2 24 Remove the screws and Figure 2 25 Remove the system board disconnect the cable Reassembly 1 Reconnect the cable to system board 2 Replace four screws fasten the system board 3 Reconnect one cable of system board fan and one cable of little battery to system board 4 Replace four screws fasten the base unit 5 6 7 8 Reconnect the touch pad cord Replace the base unit cover and secure with nine screws Carefully put the notebook upside down Then replace the bottom frame and secure with fourteen screws Replace the battery pack LED panel keyboard CPU HDD module CD DVD ROM drive and LCD assembly 91 8575 N B Maintenance 2 2 11 Touch pad Disassembly 1 Remo
123. is kept asserted during the burst cycle If Cardbus mode CARD_ON 1 this pin should be pulled up to TRDY Io 37 5 3 3 Target Ready indicates that Link the current data phase of the transaction is ready to be completed IRDY vo 36 5 3 3 Initiator Ready indicates Link that the current bus master is ready to complete the current data phase During a write its assertion indicates that the initiator is driving valid data onto the data bus During a read its assertion indicates that the initiator is ready to accept data from the currently addressed target PME PCI Cardbus 5 3 3 PME Output for power Link management enable CLKRUN Uo PCI Cardbus 5 3 3 PCICLK Running as input Link to determine the status of PCLK as output to request starting or speeding up clock INTA PCI Cardbus 5 3 3 Interrupt the PCI interrupt Link request A 127 8575 N B Maintenance 5 6 uPD72872 IEEE1394 Controller Name yo PIN NO IOL Volts V Function Block PERR Uo 41 PCI Cardbus 5 3 3 Parity Error is used for Link reporting data parity errors during all PCI transactions except a Special Cycle It is an output when ADO AD31 and PAR are both inputs It is an input when AD0 AD31 and PAR are both outputs SERR 42 PCI Cardbus 5 3 3 System Error is used
124. mm 27PINA 27PINA 1 0603 1 2 048 GPIOD T 1 T 1 d A R122 1 A TKINA AA 0603 Normal Normal PAL M PAL N Norma Title PAL NISC 8575 TVILVDS ENCODER 8193010 GPIOB R111 1 2 4IKNA YUV TV 5251 525P 750P 10801 id pze Document 411671700010 Number ais Wednesday January 16 2002 9 of 29 5 n 3 z 1 LCD amp CRT INTERFACE LED INDICATOR E ET BATT LED D16 D15 D13 D14 D15 NA D10 D8 D9 D11 D15 R586 CDROM HDD NUM CAP SCROLL R211 R212 R213 R96 For LCD 15 R723 U516A U516B U516C B J 4 1 ic 2 s 2 2 aum os C810 C808 C807 5 58 Nt 152427 PSON PTC 144TKAINA l Gede 0603 0603 0603 1
125. over current detection are also implemented The integrated IDE Master Slave controllers features Dual Independent IDE channels supporting PIO mode 0 1 2 3 4 and Ultra DMA 33 66 100 It provides two separate data paths for the dual IDE channels that sustain the high data transfer rate in the multitasking environment The MuTIOL Connect to PCI bridge supporting 6 PCI master is compliant to PCI 2 2 specification The 515961 also incorporates the legacy system I O like two 8237A compatible DMA controllers three 8254 compatible programmable 16 bit counters hardwired keyboard controller and PS2 mouse interface Real Time clock with 256B CMOS SRAM and two 8259A compatible Interrupt controllers Besides the I O APIC managing up to 24 interrupts with both Serial and FSB interrupt delivery modes is supported The integrated power management module incorporates the ACPI 1 0b compliance functions the APM 1 2 compliance functions and the PCI bus power management interface spec v1 1 Numerous power up events and power down events are also supported 21 general purposed I O pins are provided to give an easy to use logic for specific application In addition the SiS961 supports Intel Speed Step technology and Deeper Sleep power state for Intel Mobile processor For AMD processor the SiS961 use the CPUSTP signal to reduce processor voltage during C3 and S1 state 20 8575 N B Maintenance 1 2 4 CH7019 TV Encoder LVDS Transmitter General Description
126. system board to detach the keyboard Figure 2 5 A s D F G H J e eG Figure 2 4 Remove three screws Figure 2 5 Remove keyboard Reassembly 1 Reconnect the keyboard cable and fit the keyboard back into place with three screws 2 Replace the easy start buttons cover 79 8575 N B Maintenance 2 2 3 CPU Disassembly 1 Remove the easy start buttons cover and keyboard to access the CPU compartment See section 2 2 2 Disassembly 2 Remove seven screws fastening the heatsink cover and the rail Figure 2 6 3 Remove three screws fastening the heatsink Figure 2 7 20 o Emm Figure 2 6 Remove the cover and rail Figure 2 7 Remove the heatsink 80 8575 N B Maintenance 4 Disconnect the fan s power cord from the system board then lift up the heatsink Figure 2 8 5 Push the lever to the right Then lift up the lever to the vertical position Finally Remove the existing CPU Figure 2 9 Figure 2 8 Remove the fan s power cord Figure 2 9 Remove the CPU Reassembly 1 Carefully align the arrowhead corner of the CPU with the beveled corner of the socket then insert CPU pins into the holes Place the lever back to the horizontal position and push the lever to the left 2 Connect the fan s power cord to the system board fit the heatsink onto the top of the CPU and secur
127. system core logic The processor will keep TERRE asserted until the assertion of RESET BINIT or INIT This signals does not have on die termination DSTBN 3 0 Input Output Data strobe used to latch in D 63 0 Associated Strobe DSTBNO DSTBNI Z DSTBN2 DSTBN3 Signals D 15 0 DBIOZ D 31 16 Z DBU 0 47 32 DBR D 63 48 DBI3 DSTBP 3 0 Input Output Data strobe used to latch in D 63 0 Associated Strobe DSTBPO DSTBP1 DSTBP2 DSTBP3 Signals D 15 0 DBIO D 31 16 Z DBU D 47 32 12 D 63 48 DBI3 IGNNE Input IGNNE Ignore Numeric Error is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating point instructions If IGNNE is deasserted the processor generates an exception on a noncontrol floating point instruction if a previous floating point instruction caused an error IGNNE has no effect when the NE bit in control register 0 CRO is set IGNNE is an asynchronous signal However to ensure recognition of this signal following an Input Output write instruction it must be valid along with the TRDY assertion of the corresponding Input Output Write bus transaction FERR Output FERR Floating point Error is asserted when the processor detects an unmasked floating point error FERR is similar to the ERROR signal on the Intel 387 coprocessor and is incl
128. the Pentium 4 processor in the 478 pin package Refer to the Intel Pentium 4 Processor in the 478 pin Package and Intel amp 850 Chipset Platform Design Guide for more information VID 4 0 Output VID 4 0 Voltage ID pins can be used to support automatic selection of power supply voltages Vcc These pins are not signals but are either an open circuit or a short circuit to VSS on the processor The combination of opens and shorts defines the voltage required by the processor The VID pins are needed to cleanly support processor voltage specification variations The power supply must supply the voltage that is requested by these pins or disable itself Vssa Input Vssa is the isolated ground for internal PLLs VSSSENSE Output VssseNsE is an isolated low impedance connection to processor core Vss It can be used to sense or measure ground near the silicon with little noise TMS Input TMS Test Mode Select is a JTAG specification support signal used by debug tools TRDY Input TRDY Target Ready is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer TRDY must connect the appropriate pins of all system bus agents TRST Input TRST Test Reset resets the Test Access Port TAP logic TRST must be driven low during power on Reset This can be done with a 680 pull down resistor VCCA Input VCCA provides iso
129. us 1509 018 10K 4 P22 1 H8 RESET SIS_PWRBTN TE Vodi SiS301LV PCMCIA LPC MINI PCI IEEE 1394 SW502 pi vcc RESET Controller o VO devices Chrotel CH7019 Controller Super Socket Controller e 31 0515 9j SIS PWRBTN 0515 515961 4 DTCI44WK 97 RST P20 L 100K 2 um 015 MDC Audio Codec 144 8575 N B Maintenance 8 3 VGA Controller Failure LCD No Display There is no display or picture abnormal on LCD although power on self test is passed Controller Failure LCD No Display 1 Confirm LCD panel or monitor is good Check if and check the cable are connected U504 13 are cold properly 2 Try another known good monitor or LCD module Display OK No Remove all the I O device amp cable from Replace motherboard except LCD panel or extended Motherboard monitor Re soldering solder Board level Troubleshooting Yes Replace faulty One of the following parts on the mother board may be LCD or monitor defective use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement Parts Signals 43VS TX20UT 0 2 LCDVCC TX20UT 0 2 ENAVDD BLADJ PID 0 2 KH8 ENABKL TXCLK LID TXCLK TX2CLK TX2CLK TXOUT 0 2 TXOUT 0 2 Connect the I O device amp cable to the M B one at a time to find out which part is causing the proble
130. 0 data If differential clocks are not available the XCLK1 input should be connected to VREF1 The clock polarity can be selected by the 1 control bit 85 90 94 99 In D2 11 0 Data2 11 through Data2 0 Inputs These pins accept the 12 data inputs from a digital video port of a graphics controller The levels are 0 to DVDDV is the threshold level Pin Type Symbol Description 2 Analog LPLLCAP LVDS PLL Capacitor This pins allows coupling of any signal to the on chip loop filter capacitor 5 24 Out LL2C LLIC LVDS differential Clock2 amp Clock1 6 25 Out LL2C LL1C Negative LVDS differential Clock2 amp Clock1 8 11 14 17 LDC 7 4 Positive LVDS differential data 7 4 9 12 15 18 Out LDC 7 4 Negative LVDS differential data 7 4 21 27 30 33 Out LDC 3 0 Positive LVDS differential data 3 0 22 28 31 34 Out LDC 3 0 Negative LVDS differential data 3 0 38 Analog ISET Current Set Resistor Input This pin sets the DAC current A 140 ohm resistor should be connected between this pin and pin 39 using short and wide traces 40 42 44 46 Out DACB 3 0 DAC Output B Video Digital to Analog outputs 41 43 45 47 Out DACA 3 0 DAC Output A Video Digital to Analog outputs 120 Out VOUT V Sync Output This pin is the output of a voltage translating digital buffer and is driven from V5V 110 In VIN V Sync Input This pin is the input of a voltage translating digita
131. 000 The use of suspend resume is recommended for new designs 34 8575 N B Maintenance The port transmitter and receiver circuitry is disabled during power down when the PD input terminal is asserted high during reset when the RESET input terminal is asserted low when no active cable is connected to the port or when controlled by the internal arbitration logic The TPBIAS output is disabled during power down during reset or when the port is disabled as commanded by the LLC The cable not active CNA output terminal 64 terminal PAP package only is asserted high when there are no twisted pair cable ports receiving incoming bias that is they are either disconnected or suspended and can be used along with LPS to determine when to power down the TSB41AB1 The CNA output is not debounced When the PD terminal is asserted high the CNA detection circuitry is enabled regardless of the previous state of the ports and a pulldown is activated on the RESET terminal so as to force a reset of the TSB41AB1 internal logic The LPS link power status terminal works with the C LKON terminal to manage the power usage in the node The LPS signal from the LLC is used in conjunction with the LCtrl bit to indicate the active power status of the LLC The LPS signal is also used to reset disable and initialize the PHY LLC interface the state of the PHY LLC interface is controlled solely by the LPS input regardless of the state of the LCtrl bit
132. 010 aS io 0603 0603 e 50V o 10 AGCLK R42 1 222 _ VAGCLK R GIS AGCLK 1 2 22NA 9 VADE 9 1504 gt AGPAVSS2 ka r L M ILAC S 10 ENA HE VBCTLO JP NET20 0603 41198 VBCTLI youne 0 nie 7 lt 10 id VBCTL1 9 8575 SIS650 1 3 GND 7 GND Bie Document A GND C Number 411671700010 later Wednesday January 16 2002 Bheet 6 SIS650 2 3 12 DDR MD O 63 MDO 123 0 5 063 DDR 2 21 MDISMDSO DDR Alas MDZ SMD29 EE ARE MD3 SMD59 DOR MDS ADRS MD4 SMD31 MD5 SMD62 12 DDR 7
133. 0511 1509 Power Button Super I O Micro Print Port 87393 Controller U10 Touch Pad 8 3437 Flash ROM Keyboard 129 8575 N B Maintenance 7 Maintenance Diagnostics 7 1 Introduction Each time the computer is turned on the system bios runs a series of internal checks on the hardware This power on self test post allows the computer to detect problems as early as the power on stage Error messages of post can alert you to the problems of your computer If an error is detected during these tests you will see an error message displayed on the screen If the error occurs before the display is initialized then the screen cannot display the error message Error codes or system beeps are used to identify a post error that occurs when the screen is not available The value for the diagnostic port 378H is written at the beginning of the test Therefore if the test failed the user can determine where the problem occurred by reading the last value written to port 378H by the 378H port debug board plug at PIO PORT 130 8575 N B Maintenance 7 2 Error Codes Following is a list of error codes in sequent display on the PIO debug board Turn off FAST A20 for POST Signal power on reset Initialize the chipset Some type of lone reset 18h Dispatch to RAM test Check sum the ROM Reset PIC s Initialize video adapter s Initialize video 6845Regs Initialize color adapter 1Eh Init
134. 0603 LCD 102 LCD ID2 10 06030 SDAVDD 1 l 060 T savs ie 438 79 VDDZCMP 1 Z4XAVDD 1 ZIXAVDD 1002 1202 100M DDRVREFB t 1 1 1 1 1 1 7 C692012 1202 100 1202 100 1202 100 00107 100 ZCMP N R587 2 56 J J 2012 J J J 2012 J J J 2012 J 0603 0603 1206 C641 C637 C630 C67 C66 C63 C606 C607 C599 50 e 10 R615 0 01U 0 10 75 100 0 01U 0 10 100 0010 040 100 L510 150 ZCMP P R59 56 0603 0603 1206 0603 0603 1206 0603 0603 1206 SDAVSS 1 06030 e 50 10 4 50 10V 4 50 10V 1 1511 4512 4513 Title JP_NET20 C VSSZCMP E 1 1 zaxavss jee 2 zixavss fe I 8575 SIS650 2 3 nee ene ener NU Size Document gno GND GND GND C Number 411671700010 oA later Wednesday January 16 2002 Eheet 7 8 3V ces 11 2 1U C635 2 010 cesa 12 1 8V 3V GND GND FOR AUX3 3 amp g FOR PVDDM FOR OVDD amp AUX1 8 PVDD RE Vcc Col N AUX1 8 9 8 8888888 22222 Aus VIT 8 555222 88888 vss o 2 vss_1 22 vss2 24 VIT 4 vss 3 9 VIT vss_4 155 5 7 vss 6 VITIS VSS 7 9 VSS 8 10 vss 9 220 VCC CORE 1 8VS 155 10 _12 VSS M 4 2 100 VIT 13 vss_12 C629 1 vita 155 13 565 1 2 100 56051 210 6471 21 VIT 15 VSS 14 C585 1 2 0
135. 1 2 00 20 MHz to 35 MHz Fin 10 20 83 KHz AS 1 9 602 t 21 Ee GPIO3 SES FSO MODOUT PIOS vss sson 2 4 R833 P2010 NA 1 7 14 17 18 21 28 29 PCIRST R55 tann 50 and SRO HAVE IIS EIR PER INTERNAL R59 o DAC_VDD AES A 5 PULL UP 100K 1 AA as RP508 Ohm VBDE 1 6 NBDE CLOSE TO CHTOIT R40 2 i 75 3 5 L7 6 VBCTLI 8803 1 Sei 9509 1 e iv 2__ VCC green Led Y 754 1206 1202 100 19 LUMA 27 201 i 2 Vgl VDD 4 1 4 4 4 TV CRMA 27 IL c42 1202100 1 c52 cao C49 47518 gt 202 100 OU 10U 0603 0603 1206 12 15 o 50 SV 1 21539 25V d XV 4 GND L10 JP 20 TVPLL_GND J R540 1 503 1 vppv R543 0805 1 1 1 75 0 10 75 NCO e 2 1 4 1202 100 VREF1 0603 0603 0603 4 3 lt 25V 50V DAC VDD ied 50125 yDD 1 1 lt gt 0805 En Res 4 504 i 5 1 ___ 572 i cse 1202100 1 1 ddddg 4349144 140 7019 010 100 2012 25 2999992599259 PQFP128A 05 R549 0603 9698 E JL533 1202 100 0603 EXER 1 2012 10K CHT019 147 2 5 28929 56220212396 ge sero 498 6 VBVSYNC gt E 50888888889 R550 DXC_GND 1508 2 u lt lt tN BAWBHSYNC A A 2
136. 1 526267171002 461671600002 227671600003 224670830002 221669950001 221671650008 221671650005 221671650006 221671650004 221671250003 221671650007 222668820001 Description HOUSING ASSY LCD 14 ID 2 8175 HOUSING KIT ID2 8575 INSULATOR REAR SCREW 8575 KEYBOARD COVER ASSY S 8575 LABEL KIT N B 8575 LABEL AGENCY GLOBAL 8575 LABEL BAR CODE 125 65 COMMON LABEL BLANK 60 80MM 7170 LCD ASSY UNIPAC XGA 14 1 ID2 85 LCD ME KIT UNIPAC XGA 14 1 ID2 LCD UB141X01 TFT 14 1 XGA UNIPA LT PF OPTION XGA 14 1 ID2 8575 LT PF UNIPAC XGA 14 1 ID2 85753 LTXNX 8575 T4XX XXX XXXX L8D3B PACKING KIT N B 14 1 8175 PAD LCD KB ANIT STATIC 8175 PALLET 1250 1080 130 7521N PARTITION BOX 7170 PARTITION BOX TOP 8175 PARTITION BOX 8175 PARTITION FDD AK BOK BTM 8175 PARTITION BOX 8175 PARTITION PALLET 8170 PARTITION SIDE AK BOX 8175 PE BAG ANTI STATIC 170x270MM ORC Location s 171 8575 N B Maintenance 9 Spare Parts List 2 8575 ID2 14 8575 ID2 15 Part Number P N 526267171002 Description Location s 172 8575 N B Maintenance 9 Spare Parts List 3 8575 ID2 15 Part Number 340671700014 KEYBOARD COVER ASSY S 8575 35 416267171004 LT PF HANNSTAR XGA 15 1 102 857 Po 8575 ID2 15 Description Location s 461671600010 PACKING 15 8175 224670830002 PALLET 1250 1080 130 7521N 221671650001 PARTITION AK BOX 8
137. 1 25V AFLT2 zn AK zi 29 20mil 0603 AGND REFFLT CARDSPK R136 8 94 AHCTIG86DBV 470 0603 0603 54 ve sl AGND 50125 R698 50 4 C220 20k CHIP ALC200 54299 ALC201 C254 25 1000P NA 0603 Ea m ARE ve Se SPDIFOUT POFP48_0 5MM gt lt 109 0603 1031 0603 0603 1206 Cap pin31 0 1U x 0603 0603 m Cap pin32 0 10 _ 0 010 L sseorour 15 Cap pin33 x AGND AGND AGND AGND AGND AGND Cap p33 34 x 1000P Ris MIC VREF 0603 3VS_SPD 1545 4 sae 1 2 1 2 DTA144WK J 1 3 H R96 1532 1202 100 1202 100 47K R745 7 E d Hum dO 0905 TOKINA 1546 140 1608 i 1 MUTE AVDDAD 09058 External Micro Phone Jack B R728 B J28 420Z 100M 420Z 100M VREF E 7 wp us We b 1 H 1 2 1 2 5 2 2K MC 3 5 2 0603 mez a 2 2 TEIT 60027 1 77 77 77 06030 AGND AGND R739 5V 5V 15 SPK_OFF 27K 6 5 T DEVICE DECT 0803 J HCH 183 Ji IDJ B27 F6T 220P 5V 0603 SHORT SMT4 10 Caos R731 R719 7 C289 1000 6 3V EW6 3 11 21 2 3 2 4 1 2 AGND L535 i Qu 1 R713 220 1202100 40K TY GEN 0805 10K C792 2012 0603 600Z 100M 80 20 0603 un 10 Internal Speaker Connector 1608 AOUT R L Cap x2 SIZEO805 Amplifier DEVICE DECT Line Out Phone Jack AGND CAGND 53 4 0603 116 1608 J25 R710 22 0603 15 2
138. 1 Battery Pack 2 2 2 Keyboard Modular Components 2 2 3 CPU 2 2 4 HDD Module 2 2 5 CD ROM Drive 2 2 6 SO DIMM NOTEBOOK 2 2 7 LCD Assembly LCD Assembly Components 2 2 8 LCD Panel 2 2 9 Inverter Board 2 2 10 System Board Base Unit Components 2 2 11 Touch pad 2 2 12 Modem Card 76 8575 N B Maintenance 2 2 1 Battery Pack Disassembly 1 Carefully put the notebook upside down 2 Slide the release lever to the unlock 75 position 9 then sliding and holding the release lever outwards while pull the battery pack out of the compartment Figure 2 1 Figure 2 1 Remove the battery pack Reassembly 1 Push the battery pack into the compartment The battery pack should be correctly connected when you hear a clicking sound 2 Slide the release lever to the lock position 77 8575 N B Maintenance 2 2 2 Keyboard Disassembly 1 Open the top cover 2 Insert a small rod such as a straightened paper clip into the eject hole near the power connector of the notebook Figure 2 2 3 Push the rod firmly and slide the easy start buttons cover to the left 0 Then lift the easy start buttons cover up from the left side 0 Figure 2 3 Figure 2 2 Insert a rod easy to remove Figure 2 16 Remove easy start buttons cover 78 8575 N B Maintenance 3 Remove three screws fastening keyboard on the base unit cover Figure 2 4 4 Slightly lift up the keyboard and disconnect the cable from the
139. 101 5 Pin Descriptions of Major Components 8575 N B Maintenance 5 1 Intel Pentium 4 Processor mPGA478 Socket Name Type Description Name Type Description 35 3 Input Output A 35 3 Address define a 2 36 byte physical memory address space In sub phase 1 of the address phase these pins transmit the address of a transaction In sub phase 2 these pins transmit transaction type information These signals must connect the appropriate pins of all agents on the Pentium 4 processor in the 478 pin package system bus A 35 3 are protected by parity signals AP 1 0 A 35 3 are source synchronous signals and are latched into the receiving buffers by ADSTB 1 0 On the active to inactive transition of RESET the processor samples a subset of the A 35 3 pins to determine power on configuration A20M Input If A20M Address 20 Mask is asserted the processor masks physical address bit 20 A20 before looking up a line in any internal cache and before driving a read write transaction on the bus Asserting 20 emulates the 8086 processor s address wrap around at the 1 Mbyte boundary Assertion of A20M is only supported in real mode A20Mf is an asynchronous signal However to ensure recognition of this signal following an Input Output write instruction it must be valid along with the TRDY assertion of the corresponding Input Output Write bus transaction AP 1 0 Input Output
140. 11502 SCREW M2L15 FLT NIW NLK 340671700007 SHIELDING ASSY TOP 8575 SHIELDING AUDIO 8575 341671700001 370102610302 370102610603 370102610603 370102030301 370102030301 370102030301 370102030301 370102010309 370102010407 370102010407 370102010606 370103010405 370103010604 SPC SCREW M2 6L3 NIB K HD NYLOK SPC SCREW M2 6L6 K HD NIB NLK SPC SCREW M2 6L6 K HD NIB NLK SPC SCREW M2L3 K HD 1 NIB NLK SPC SCREW M2L3 K HD 1 NIB NLK SPC SCREW M2L3 K HD 1 NIB NLK SPC SCREW M2L3 K HD 1 NIB NLK SPC SCREW SPC SCREW SPC SCREW SPC SCREW SPC SCREW SPC SCREW M2L3 0 NIW NLK HD07 M2L4 K HD NIB NLK M2L4 K HD NIB NLK M2L6 K HD t0 2 NIB NL M3L4 NIW K HD T0 3 M3L6 NIB K HD t0 8 NYL RP502 190 8575 N B Maintenance 9 Spare Parts List 21 Part Number 288203401001 ITRANSAO3401 P MOSFET SOT 23 01 0509 0511 06 08 288200144003 TRANS DTCIA4TKA N MOSFET SOT 23 910 011 017 018 019 02 9 288203904010 TRANS MMBT3904L NPN Tr35NS TO236 015 0516 0517 Part Number 288204416001 288204416001 288204425002 Description TRANS Si4416DY N MOSFET 0280HM TRANS Si4416DY N MOSFET 0280HM TRANS SI4425DY PMOS 8 5A 30V 02 288204425002 TRANS SI4425DY PMOS 8 5A 30V 02 288204788001 TRANS SI4788CY P MOS 5A1 8 5 5V 288204810001 TRANS SI4810DY N MOS 01550HM SO 288204810001 TRANS SI4810DY N MOS 01550HM SO 288204835001 TRANS SI4835DY PMOS 6A 30V 035 288204925001 TRAN
141. 12 mo 7 DDR Dass 2 3 2 15 Dass 0055 13 113 114 4 113 14 4 7 DDR SDE i 14 MD43 13 16 BAT MA 15 116 X DDR 47 n 13 MD47 ds RPI2 108 RPXB ML 118 RASH BAD 117 118 JSDDFCMDAT DDR MDA 5 12 MD49 MD49 13 DDR MD32 1 16 MD32 1082 48 WEE 119 120 CASE WEF 119 120 CASE T DDR MD55 6 11 MD55 43 4 032 DDR 37 2 1 MD37 43 50 121 122 CSTE 2528 121 122 CSS 7 DDR MD48 L 10 MD48 13 7 DDR DQS4 DDR 0954 3 14 957 0054 13 212 Eze Eze 7 DDR MD54 FM 8 E MS 54 13 7 DDR DaMA 4 13 DOMA 13 es n 1 F DDR MD52 1 REY 16 RPX8 MD52 DDR MD36 5 1 MD36 MD32 127 128 MD36 MD32 127 128 MD36 7 DDR MDS2 MDS2 13 7 MD36 13 DDR DOM 2 15 DOMS DDR MD33 6 11 MD33 MD33 129 130 MD37 MD33 120 130 MD37 7 DDR DDR 2 1 DQM6 13 7 DDR MD33 ae at VD MD33 13 7 DDR DOSS 4 13 0056 MOS3 13 7 DDR MOM DDR MD35 8 9 MD35 5054 133 134 Dawa 1 5054 133 134 4 7 DDR DQse DDR MDSO a d 0096 13 7 DDRMD35 MD35 13 EL m 0054 m 7 DDR MDSI 8 11 051 Mosi 13 RPIB 108 Hat Bh ure Fe T DDR HOST DDR MD57 7 10 MD57 057 13 7 DDR MD44 DDR MD14 1 18 MD14 MD14 13 MD35 139 140 MD39 MD35 139 140 MD39 x DDR MD6T BEA MDOT MTS DDR 2 1 MES MD40 141 142 044 MD
142. 15961 is a PCI slave The assertion of TRDY indicates the target agent s ability to complete the current data phase of the transaction For a read cycle TRDY indicates that the target has driven valid data onto the PCI bus For a write cycle TRDY indicates that the target is prepared to accept data from the PCI bus When the S1S961 is a PCI master it is an input pin PCI Interface Name Pin Attr Signal Description DEVSEL vO Device Select 3 3V 5V M As a PCI target 515961 asserts DEVSEL by doing positive or subtractive decoding 515961 positively asserts DEVSEL when the DRAM address is being accessed by a PCI master PCI configuration registers or embedded controllers registers are being addressed or the BIOS memory space is being accessed The low 16K I O space and low 16M memory space are responded subtractively The DEVESEL is an input pin when S1S961 is acting as a PCI master It is asserted by the addressed agent to claim the current transaction PREQ 4 0 I PCI Bus Request 3 3V 5V M PCI Bus Master Request Signals PGNT 4 0 PCI Bus Grant 3 3V M PCI Bus Master Grant Signals PREQS I PCI Bus Request 5 Uo PCI Bus Master Request Signal 3 3V 5V M PGNTS5 PCI Bus Grant GPIO6 Uo PCI Bus Master Grant Signal 3 3V M INT A D I PCI interrupt A B C D 3 3V 5V M The PCI interrupts will be connected to the inputs of the internal Interrupt controller through the rerouting logic associated with each PCI int
143. 1671200010 341671200010 342671700001 342672400007 288003600001 295000010105 295000010116 295000010116 295000010029 345671700009 345671700010 345671700011 345671600016 345671700019 345671700004 340671700006 340671700016 344600000824 291000610032 331650047803 282574373004 282574186002 282074338402 282574164002 284501032001 HEATSINK ASSY N B 8575 HEATSINK ASSY P4 CPU 8575 IC CARD CON PART 68P IC11SA BD P IC SOCKET 32P PLCC TIN W O PEGS IC SOCKET BGA P GA478B SKT 74 73 D TRAN TSSOP 20P ea a Re IC 74AHCT1G86 SINGLE XOR SOT23 S U513 IC 74CBTD3384 10 BIT BUS SW TSOP 011 IC 74VHC164 SIPO REGISTER TSSOP U517 IC ADM1032 TEMPERATURE MTR SO8 U2 Description Location s Lasso EmEPROMNaaCoRNARSOR aussen fo 2593722001 ZERO croon Dnm Us Dern fesoa s sea eso fros 186 8575 N B Maintenance 9 Spare Parts List 17 Part Number 284500301004 284500650002 284500961003 286300594001 286100202001 286302211001 284572872001 2773000990012 273000990012 273000990031 273000990054 273000990115 273000990021 273000150106 346671200036 346671700001 346671700006 346669900004 346671600018 346671700007 346671600015 242600000145 242600000145 242662300009 242662300009
144. 1721 TROTZ 53 69 SW 35V DiVADIZ 728 4K 1721 IRQ12 BH 54 PasrmuRIt HIROT PBAIXDBA 69 5VA 2327 M MPU 101 80 NA Cmm Seg E the gt NA WHILE ASSEMBLY Kio 21 10 LED DATA mE PB7 XDB7 dib 7 44 I 21 EUM PSI RXDO Ko Koi 21 10 LED C HER ELK 18 psarscko 22 ADEN 2327 T 21 0 BATT DED CARD_RI 18 ie du ones P61 KEYIN1 FTOA PASIKEYIN11 22 itg KIZ 28 21 SUSC 35 H8 RESET 3 4 28 Pe2IKEYINZIFTIA PAAIKEYIN12 ES H8 SUSC 15 OW D 50 OTe 5 9 5 Kid 32 20 BAT SUSC 1524 7 0 OTs PORTO 23 DOMKEYINAKTIG PASKEYINTA 30 SUSB 2 1 9 10 T CK D EH 32 PATIKEYINIS 1 5158 ike _ 25 oo POWERBTN due DTC144TKA Fan Control 1 RES 2 RESET H8_RESET 10 0603 77 5VS R682 3 1 04 1206 8 JOW PWR ON ERE DIAL gg E EY sav memen A Mees COW 1721 Close to NDS352P J x 3 6 A R679 0603 HB F3437 PQFP100 0 5MM 1 2 kw pwns 01U R683 20K 50 RPA 1 OUUAI200 _ OW
145. 175 221671650008 PARTITION AK 8175 221671650005 PARTITION BATT AK 8175 221671650006 PARTITION FDD AK 8175 221671650004 PARTITION FDD AK 8175 221671250003 PARTITION PALLET 8170 221671650007 PARTITION SIDE AK BOX 8175 222668820001 BAG ANTI STATIC 170x270MM ORC 332810000033 PWR CORD 125V 7A 2P BLACK AMERIC 565180626001 S W CD 1 DVD WIN DVD INTERVIDEO 561860000022 SINGLE PAGE GN NOTE FOR BATTERY amp 370101714501 SPC SCREW M1 7L4 5 NIB K HEAD 370102610401 SPC SCREW M2 6L4 K HD t0 8 NIB N 370102610801 SPC SCREW M2 6L8 NIB K HD t 1 1 421671600004 WIRE ASSY LCD HANN 15 XGA 8175 P N 526267171001 173 8575 N B Maintenance 9 Spare Parts List 4 8575 ID3 14 Part Number 340671720010 COVER ASSY LCD 14 ID3 8575 p e 8575 ID3 14 Description 451671720001 HOUSING KIT ID3 8575 346671720002 INSULATOR REAR SCREW ID3 8575 451671720032 LABEL KIT N B 8575 ID3 242671720002 LABEL AGENCY GLOBAL ID3 8575 242600000088 LABEL BAR CODE 125 65 COMMON 242669900009 LABEL BLANK 60 80MM 7170 441671720031 ASSY UNIPAC XGA 14 1 ID3 85 451671720052 LCD ME KIT UNIPAC XGA 14 1 ID3 413000020289 LCD UB141X01 TFT 14 1 XGA UNIPA 416267172901 LT PF OPTION XGA 14 1 103 8575 416267172001 LT PF UNIPAC XGA 14 1 ID3 8575 526267172004 LTXNX 8575 T4XX XXX 3XX9 L9133 X 561567176003 MANUAL KIT EU 8575 N B 561567170001 MANUAL USERS EN 8575 N B 56156717000
146. 2 1 85 M BPRE is driven by the priority agent that wants to request the bus BPRI has higher priority than BREQO to access a bus BNR vO Block Next Request 1 2 1 85 M This signal can be driven asserted by any bus agent to block further requests being pipelined HLOCK I Host Lock 1 2 1 85 CPU asserts HLOCK to indicate the current bus cycle 15 locked HIT Uo Keeping a Non Modified Cache Line 1 2 1 85 M HITM Uo Hits a Modified Cache Line 1 2 1 85 M Modified indicates the snoop cycle hits a modified line in the L1 L2 cache of CPU DEFER Defer Transaction Completion 1 2 1 85 M defer response to host bus Name Pin Attr Signal Description RS 2 0 Response Status 1 2 1 85V RS 2 0 are driven by the response agent to indicate the transaction response type The following shows the response type RS 2 0 Response 000 Idle State 001 Retry 010 Defer 011 Reserved 100 Reserved 101 No data 110 Implicit Write back 111 Normal Data HTRDY Target Ready 1 2 1 85V M During write cycles response agent will drive TRDY to indicate it is ready to accept data DRDY Uo Data Ready 1 2 1 85V M DRDY f is driven by the bus owner whenever the data is valid on the bus DBSY Uo Data Bus Busy 1 2 1 85V M Whenever the data is not valid on the bus with DRDY is deserted DBSY deasserted to hold the bus HD 63 0 Data Bus Busy 1 2 1 85V M Whenever the data i
147. 20 q 2 R510 US 0603 GNDPCIO 7 GNDPCIT AGPCLKO 31 BEL gt AGP_CLK 6 EP AURA GND48 AGPCLKI 30 GC GNDAGP Linan 06030 __ ND R875 Lo 1 AAA 2 22 ZCLKO i GNDCPU ZCLKO 7 GNDSD 8646 1 0 2 22 ERI ZCLK1 14 avs 3vs 44 283 668 1 A 2 33 CLK SBPCI go DICERE FS3 PCICLK_FO CLK_SBPCI 14 sai PEN T xX ESAPCICLK F1 FS FSA R656 1 AYA 2 33 LPC33 CLKLPC33 21 USE WIRE JUMPING WHEN DEBUG PORT IS INSTALLED 1 VDDAGP Reso 1 CLK CARDPC cARDpCI 18 A202 00 4 21 RISS 1 33 CLK 1394PC 1394PCl 29 22 x 1608 610 _ 0603 epe 8756 1 An 33 CLK MNPCI 28 0603 md 33 PWRGD 8 4 E RES MAS c REFCLKO 7 MESUREF E82 R638 1 2 33 14 318MHZ AUDIO PET Q516 RBS 1 A2 475 1 38 FS2 REF2 R625 71 33 REFCLK3 5 WZ BMMBT3904L 0603 IREF R667 71 22 USBCLK SB me X 24 48MHZIMULTISEL 26 R6 1 22 CK SO CLK_SIO 21 z R83 1 33 14 818MHZ HCLK Reds 1 499 1 0603D 2 HCLK CP R649 1 49 9 1 0603D o 1520 35 86581 AAA 2 33 SMBCLK HCLK SIS650 R636 1 49 9 1 06030 SCLK SMBCLK 12 15 AAA 315 1 coo 36 SDATA 4 86621 22 33 SMBDATA SMBDATA 1215 515650 R640 1 499 1 06030 pis S es 300Z 100M Sus SDRAMCLK
148. 213 C207 L C700 06030 o603D 0010 040 S 100 O 01U 6 10 0 10 S 100 50 SZCMP 0603 0603 1206 0603 0603 0603 0603 1206 4 J 507 10 4 507 4 507 10V SZVREF R676 56 0603 21519 4520 4521 C SVSSZCMP 4 1 42 szaxavss 1 42 szixavss 4 Xl 2 1 4 pne JP NET20 V7 pne R116 c208 GND GND GND 150 0 10 0603D 50 4 1531 SZVSSREF lt gt JP NET20 GND Size Document Number 411671700010 later Bheet 14 of 29 Wednesday January 16 2002 1 SIS961 2 3 C291 112 Need very close to 961 15P 0603 RLS4148 U14B OSC25MHI 1 las OSC25MHI i x R189 4 NITE HOME pig AN OSC25MHO 32768KHZ 10M R705 Riz 2 LAN 16 osc2sMHo lt gt R244 TT CH 4 17 Smi MIITXCLK 8 AN lt MTXC 19 200
149. 22bis 2400 bps ITU T V 22 1200 bps ITU T V 21 300 bps ITU T V 23 1200 75 bps 43 ITU T V 17 ITU T V 29 ITU T V 27ter Bell 212A Bell 103 Modulation 56000bps V90 amp K56Flex 33600 bps V 34Annex 28800 V 34 14400 V 32bis 12000 V 32bis 9600 V 32bis 7200 bps V 32bis 9600 bps V 32 4800 bps V 32 14400 bps V 17 12000 bps V 17 9600 bps V 29 7200 bps V 29 4800 bps V 27ter 8575 N B Maintenance 14400 12000 9600 7200 bps 9600 7200 bps 4800 2400 bps 1200 bps 300 bps PCM TCM TCM TCM TCM TCM QAM TCM QAM QAM TCM TCM QAM QAM DPSK 44 8575 N B Maintenance 2400 bps V 27ter DPS 2400 bps V 22bis QAM 1200 75bps V 23 FSK 1200bps V 22 Bell 212A DPSK 300bps V 21 Bell 103 FSK Data Compression V 42bis MNP5 Error Correction V 42 LAPM MNP 2 4 DTE interface DTMF Tone Frequency Low Group Frequency Hz DTMF signal level 45 8575 N B Maintenance 1 2 8 1 High Group 10 2dBm 1 2 8 2 Low Group 12 2dBm Dialing Type Tone or pulse dialing Telephone Line interface RJ 11 Return Loss 300HZ 3400HZ gt 10db Flow Control XOFF XON or RTS CTS Receive Level 35 2dBm Transmit Level 7 15 dBm Specification and features subject to change without notice BIT CLK SYNC mE Isolation SDATA I
150. 29 30 MDi4 T 1 0 30 Ps CERT MD11 MD15 MD11 MD15 7 CKE2 33 34 33 34 7 DDR MD4 DDR MD4 RP20 1 19 16 __ __ MD4 MD4 13 7 CIK DORO 35 36 1 DDR3 3 36 3 7 DDR MD5 DDR MDS 2 15 MBS 05 13 DDROF 37 38 CLK 3 38 7 DDR DDR DOMO i E DOMO DOMO 13 39 40 i 39 40 1 7 DDR MDO DET E i MDO 13 z DDR 5 12 MDT 7 DDR MD1 DDR DQSO 11 DASD sas MD16 41 42 MD20 MD16 41 42 MD20 7 POR DDR MDS 7 10 MDS MDB 13 MD17 43 44 MD21 17 43 44 M21 7 DDR MD DEM a a MDT 13 11 CLK DDRO 45 46 4 4 46 4 7 DDR MD2 DDR MD2 1 16 REXS MD2 13 11 DDROR 0052 41 48 2 DASZ 4 48 DOMZ 7 DDR MD3 2 15 MD3 13 11 DDR1 MD18 49 50 MD18 49 50 MD22 3 14 d 51 DDR MD13 4 13 MD13 Mss M T MD1S 53 54 MD23 1 3 54 MD23 7 DDR 5 12 dix MD12 13 11 Mas MD24 MD28 7 DDR MD9 NDS MD9 13 11 CLK 0683 ss DDR DOST 7 10 0051 ee D 11525 59 60 1525 11525 59 60 14625 1 DOR DDR DOMT 8 DOMT DOM 13 DQS3 DOM 0053 DOMS 7 DOR MDIS DDR 1 5 7 16 18 MD18 13 11 CLK_DDR4 eas 64 S f DDR DDR MD23 2 15 MD23 MOIS PAPE 11526 65 66 MD26 6 66 7 DDR DQM2 203 1 Dame DQ
151. 3 MANUAL USERS EU 8575 N B 461671600018 PACKING KIT N B 5 IN 1 8175 221671650001 PARTITION AK BOX 8175 221671650008 PARTITION AK BOX TOP 8175 221671650005 PARTITION BATT AK BOX 8175 221671650006 PARTITION FDD AK BOR BTM 8175 221671650004 PARTITION FDD AK BOX 8175 221671650007 PARTITION SIDE AK BOX 8175 Location s 174 8575 N B Maintenance 9 Spare Parts List 5 8575 ID3 14 8575 ID3 15 Part Number Description Location s pu 344671720002 COVER DUMMY ID3 8575 7 4 344671720013 COVER HDD ID3 8575 344671720023 COVER HINGE ID3 8575 MEER NE 344670500042 DUMMY CARD PCMCIA 227671600005 END 5 IN 1 LOWER 8175 227671600004 END 5 IN 1 UPPER 8175 345671600018 GASKET HEATSINK K B_PLATE 8175 451671720071 HDD ME 103 8575 340671600019 HINGE L 15 8175 340671600017 HINGE R 15 8175 175 8575 N B Maintenance 9 Spare Parts List 6 8575 ID3 15 Part Number 340671720011 340671720007 340671720002 451671720001 346671720002 451671720032 242671720002 242600000088 242669900009 441671720034 451671720053 413000020265 416267172902 416267172003 526267172003 561567176003 561567170001 561567170003 461671600018 _ OOo
152. 301 CPU THERMDC 20 i SO TM 22 1 5 5 5 2012 S 5 lt 0603 62 b eny ren i i 103 7 avs Hvo GND THERM ERR 22 0503 7 Tu ye FERR i ADM1032 4 i mE mm M teen 508 VCC_CORE PLACE AT CPU END 2 Jta VCCA CPUPWRGD R535 i 20 7 1 2 2 M 2 CRU GTLREF 1 16 830 199 060 2 4 4 J CPURSTI R536 C546 PLL_VSSA i 100 10 220P 220P 0603 0805 0603 0603 1 amp 1 5 5572 im E 7343 C22 2 4 CPU SIGNAL TERMINATION RA 20 7 i 16 830 udi uu d om mie CP1812 7243 SHAPE GTL Reference CKT a NS i MiTAC zem PLL SUPPLY FILTER 8575 PENTIUMA 1 2 ize Document ae Number 411671700010 0 Date Wednesday January 16 2002 4 2 5 2 3 2 1 VCC CORE Vs SSBBBSSSEBSSBSESSBESOBESSOESSOSSESOSESSSSESOBSSSSESSSSSSOSESOSSSSOBSSOSESOSESSSSESSSSH 889998898889988998889988988899988998899889998998889998898889988998889888998899889998 VS vss vss Vss vss 555 vss 555 vss 155 VS 555 155 VS vss 155 VS VS vss ss vss vss vss 555 vss vss 26 2528 VS Ves 555 vss 4 vss vss 555 vss VS vss VS 155 vss vss VS vss vss vss
153. 331040050012 291000020202 331040050010 291000011030 291000020303 291000256823 331000004018 N 331870004017 331870004010 291000810205 1000810802 331840010005 331910002006 331840005013 Description CON FPC FFC 15P 2 8MM BD BD ST CON FPC FFC 20P 2 1 0MM H 4 6 ST CON FPC FFC 24P 1MM H8 2 ST ACES CON FPC FFC 8P 1MM R A 2CONTAC E CON HDR FM 10P 2 2 54MM R A H8 4 CON HDR FM 22 2 2MM ST C16805 CON HDR FM 25P 2 1 27X1 27MM D R CON HDR FM 5P 2 1 27MM ST H4 5 S CON HDR MA 10P 2 2 54MM R A H8 4 CON HDR MA 12P 1 1 25 ST SMT CON HDR MA 22P 2 2MM R A SMT ALL CON HDR MA 25P 2 1 27X1 27MM D R CON HDR MA 2P 1 1 25 R A SMT HIR CON HDR MA 50P 0 8MM R A H1 1 CON HDR MA 5P 2 1 27MM ST H17 85 CON HDR SHROUD MA 3P 1 25MM R A CON IC CARD PART 68P 0 635 H5 SM CON IEEE1394 MA 4P 8MM R A LINK CON MINI DIN 4P R A W GROND C108 CON MINI DIN 4P R A W GROUND C10 CON PHONE JACK 2P H 8 4 R A SMT CON PHONE JACK 8P H 12 59 R A RJ CON POF MINI JACK 10P W SPDIF 2F CON POWER JACK 2P 20VDC 5A DIP CON STEREO JACK 5P R A 28MF60 07 Location s J18 J3 J13 J501 J4 J7 J501 1 J6 19 2 508 12 J6 J503 11 J27 Jl Jl J9 J24 J2 J28 184 8575 N B Maintenance 9 Spare Parts List 15 Part Number 331000004029 291000410201 291000410301 291000410401 291000410801 313000150093 272625220401 331660020003 331
154. 40V JL514 IDEAVSS ES JP_NET20 GND PCI 4 ZSSENSAESHNLSOSLOOSXONLORENSOUXSNL IDEAVDD 17 PCI_REQ4 Pakeb sane 17 RE BB888888838335355555552222328852 IDEAVSS 028 lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt 17 28 PCI_REQ2 2 1729 1 REQUE 1 ICHRDYA IDE PIORDY 17 1718 PCLREQOR PREQO IDE PDDREQ 17 D z 17 PCI_GNT4 ena PGNTA CBLIDA TP517 42 PONENTS P I GNT2 PGNT3H 41 IDE _PDIOR 17 28 PCI_GNT2 PGNT2 WORAR IDE_PDIOR 17 1729 PCI_GNTI G3 port H2 Dre IDE PDIOW amp 17 PCI GNTOR H4 Yi IDE 17 18 PCI_GNTO PGNTO IDACKA amp 010 IDE_PDDACK 17 18 28 29 3 141 IDE PDA2 peve eere Wii IDE PDAO a CIBEt IDSAAO IDE_PDAO 17 ud 502 Eset IDE_PDCS3 17 7947 PCLINTA INTAR IDECSAO IDE_PDCSt 17 17 18 PCI_INTB INTB 17 2829 PCLINTCH INTC ICHRDYB i IDE SIORDY 17 17 28 PCI_INTD INTD IDREQB IDE SDDREQ 17 ROB 17 1828 29 PCI FRAMES FRAME CBLIDB TP516 17 182829 PI_IRDY IRDY 17 18 28 29 PCI_TRDY TRDY 114 DE SOC IDE_SDIOR 17 17 18 28 29 PCI_STOP STOP HME IDE_SDIOW 17 16 __IDE_SDDACK IDE_SDDACK 17 17 18 2829 SERRE 17 18 28 29 PCI PAR PAR 418
155. 4TPN 0608 o MAaPxart27 1 90 603 SPEED 45VAS GND2 BEAD T os py MITAC SPEED 0805c 50 VIT AO 0001 7 GND USB Tie Dc POWER Document Number 411671700004 OA Date Bheet 2 3 Monday January 14 2007 1 2 1 1 02 Place two fuses on same location only use one fuse 4 c12 33P TV OUT 5658 SV 1 1 5 5V N o 14 MINISMDC110 NA 1202100 1202 100M 2012 1 1608 Le R2 css 1 1 2 1 TV LUMA TU 100 NA 3 1 1 2 2 2 t TTV ERMA TVALUMA 2 0603 0603 1206 0603 A 10V 50V 77 7 1608 4 4 UsBOC3 GND USB 10801 10405 4 4 33P MINI DIN 4P cs C2 1002 100P 5 270P 270P i 754 RA 0603 0603 0603 50 10 10 1206 ut 10 10 0603 L505 _ H vino 5 H 2 DISCO 1 Nutt LE USBSVCCS RT9701
156. 5402 272003105701 272002105701 272002225701 272012225702 272012225702 CAP 150U TPC 6 3V 20 H1 9 7343 CAP 150U UE 6 3V 20 7343 SP C CAP 15P CR 50V 5 0603 NPO S CAP 1U CR 10V 80 2096 0603 75 CAP 1U CR 10V 80 2096 0603 Y5 CAP 1U CR 10V 1096 0805 XbR SM CAP 1U CR 25V 80 20 0805 CAP 1U 16 20 80 0805 5 CAP 2 2U CR 16V 80 20 0805 Y CAP 2 2U CR 16V 80 2096 1206 Y CAP 2 2U CR 16V 80 2096 1206 Y Location s C1 C122 C126 C37 C579 C78 C196 C227 C246 C41 C43 C7 C701 C702 PC31 C100 C132 C133 C10 C12 C14 C15 C16 C18 C 531 21 698 24 27 533 5 PC1 PC2 PC546 PC577 PC9 PC573 PC12 PC30 C17 C9 PC524 PC531 PC547 PC29 C291 C10 C3 C509 C8 C136 C137 C138 C139 C140 5 550 521 546 566 283 788 804 806 522 C714 183 8575 N B Maintenance 9 Spare Parts List 14 Part Number _______ 272075200302 272075222701 272075221302 272075221302 272431227504 272075220701 272075220301 272021226701 272075271401 272075271401 272075270302 272075330401 272001475701 272012475701 272075471401 272075471401 272075470701 272431476502 272075680302 313000020360 273000111002 273000111002 331000008038 331720015006 331720025005 Part Number 291000153006 291000144004 291000142404 1000150804 1040020004 1030044013 31040050013 91000011024 1040020005 291000011209 291000024409
157. 5V 0603 GNI 0603 50 ms GND J 10 GND PC529 5 5 PR502 1112 PUSOB 888 040 E VCC CORE PR509 2 __ 6 1 las DH1 1 cor 0603 ERE 2 ie RUNN SS 885 pool 88 50 1 2512 0603 34 core 1 i2 1 681K 470 podas 8 im t t L t 1 0603 50 100 dred BRE 1 250 PREO1 1 0603 0603 23 0 8x3 0 003 4 1 10 pi Pu2 p PU1 p 30 2512 4 4 PC504 PC503 506 PD503 1 2 5148100 SI4810DY SI4810DY 1 2 100 100 040 4 Vibo 18 00 SENSE1 3 508 G 508 508 PC7 1206 1206 0603 188355 4 19 SENSE1 527 PDS 7 8200 78200 lt 10 10V 4 d DE 20 Vins 1112 EC31QSO4 TE12L aV 4 VIDA 4 A 4 PH2 1_core 1000P 2 TG2 25V 6444 ERE NA 4 6 cor 0603 EAN Boo 0603 81 GND GND GND ES LS H s 80 6K ATOP 18 A gt 13 0603 0605 ATTENIN PR511 10 D GND VDIFFOUT 2 SENSE2 14 PR506 475 R513 Ep wy gs PR2 o 2 AA 22 2 9 Re was 5 85 5 vos 12 VCC_CORE 10K G 5 PQ502 m merda 51 1 0603 4 2N7002 4 d 0603 SSOP36A Ro 5 2 7002 2 1 PCS37 PR520 1 501 T d 6 v X 0 AA VCC SENSE 4 CPU CORE EN PC542 010 PR521 PR517 0603 PC533 0603 PR505 16V 100 dd 1M 0603 1 13 1206 0505 E ES 1000 0603 060 PRSY6 16v 11 52 PU506 PUS505 D PU504 25V
158. 6 VAGCLK XCLK2 LGND1 t 94 0266 LDC7 FC 95 029 J J J 1202 100 VAD8 96 6218 LVDDO C575 C576 C566 2012 VADO 97 058 ees TOK 610 100 98 029 TEA TX2CLKF TAAAK d 1206 4541 FC 99 02110 lt 50v 50V 25V 02411 LGNDO PRAD 6 FC lt H DGNDO LPLL GND H2 LPLLCAP 1513 s NZ 6 VAVSYNC 102 v2 LPLL VDD VDD ped 6 36 85 L 579 5 2 c571 1202 100 7 1519 1 00 2 100 0 10 100 2012 22 0603 1206 1 i aa 10 50V 25V As o 50 Jag agg 1 1202 100 1 cess ce40 8388338837 338888838833 Y SP NETZO 5VS 2012 100 010 0 10 LQFP C307 50v 7 lt 1538 1208 0608 0603 710 0603 LPLLGND 1 2 25V 4 4 9 20 PCLINTA 7 14 17 WV JP NET20 HPD 4 x D ND R74 10603 2 ENABKL 22 27 VADE mE ENAVDD 0603 0603 GPIO2 28 1 RI6 1 AA 2 O PCIRST 7 14 17 18 21 28 29 202 81051 2 GPIOC m 45 71 LE 1 4 pez R82 1 R84 1 GPIOD 1202 100 1 5 5 ROR ss 8 2012 Normal 4 1 VGA YUVTV SCART TV C614 R52 R51 0 10 100 GPIOA 0 0 1 1 4 TKINA R586 1 o 0603 1206 0603 0603 xs 50V 25V GPIOB 0 1 0 1 VBHCLK 1 1 R588 40KINA J pB 1 A A A2 10 o avs v R589 o GPIOA R115 40K NA 2 a 1 1 M
159. 603 SMT RES 51K 1 16W 5 0603 5 RES 53 6K 1 16W 1 0603 SMT RES 56 1 16W 1 0603 SMT RES 56 1 16W 596 0603 SMT RES 576K 1 16W 1 0603 SMT RES 6 04K 1 16W 1 0603 SMT RES 6 19K 1 16W 1 0603 SMT RES 6 81K 1 16W 1 0603 SMT RES 6 8K 1 16W 5 0603 SMT Location s PR14 PR4 PR561 R120 R144 R137 R156 R157 R200 R201 PR507 PR510 R505 R683 R7 R85 R4 R5 R518 R8 PR544 R134 R159 PR9 R533 R535 R636 R640 R645 17 R239 R131 R140 PR2 R512 R513 R514 R515 R R14 R521 R184 PR18 R41 R46 R605 R676 R238 R240 R241 R243 R587 PR556 R550 PR543 PR522 R185 R186 R187 189 8575 N B Maintenance 9 Spare Parts List 20 Part Number 271071604811 271071619811 271071620102 271071681101 271071750101 271071750302 271071822301 271071806211 271071820301 271071909101 271071976311 271611000301 271611000301 271571000301 271611100301 271571100301 271611103301 271611102301 271621102302 271611220301 271611330301 271571330301 271611472301 271621472303 271621471301 RES 75 1 16W 1 0603 SMT 75 1 16W 5 0603 SMT RES 82 1 16W 596 0603 SMT 0 8 16 1 16W 5 1606 5 RP 10 8 16P 1 16W 5 1606 SM Part Number 271621473301 RP 47K 8 10P 1 16W 5 1206 SMT RP513 RP517 Description Location s 271611750301 RP 75 4 1 16W 5 0612 SMT RP5 271611750301 RP 75 4 1 16W 5 0612 SMT RPT 3 711020
160. 647 x H8 R663 10K 5 72 DIAS 48 BLADJ 10 Sx ROB 3T Panya Micro 55 GAZ 1721 0603 DANZI2K T46 NA NA WHILE ASSEMBLY P21 A9 paricazo 92 S H KOTT SE Controller 203 ENABKL LESE KOT 64 1 23 11 17 21 927 ENABKL uh __ x93 KOTS 242 gp H8 DAN212KITH46INA 1 P25 A13 PBSIIRQARXD1 C iB enD Fn s Tg Kor 81 Pasata Peslrasiscxi s 8 _ MP Sak PORTO ____ Do P2TIAIS POOMIROZIESC2 J i SDT 82 1 P30 HDBO DO Ponraveiow 28 PU m 77 Cover Switch 55 S 83 p31 HDB1 01 23 D3 P32 HDB2 02 2 4 Eom Di 85 P33 HDB3 D3 aD D 55 P34 HDB4 D4 Poss 18 21 05 87 1 5 505 17 Bx P36 HDB6 D6 PSTIWAITISDA 18 A 4 D 25706757 MODED SECOND POWER SWITCH _ PAU TMCIO MD1 9 9 PAEEIM 2 1721 sop SOHFAN SWITCH WAKE UP CHARGING POWERBTN 85203 2402 SPD gg PAL IMPO LEARNING 3 6 DNADJI CHARGING 25 ti i ACES TROT 2 LEARNING 27 4 5 DVADJZ DAT 25 R643
161. 660020002 288110355001 288100032013 288100032013 288100054001 288100701002 288100099001 288100099001 288100056003 288100056003 288101004024 288101004024 288100112001 288100112003 288103104001 288103104001 288104148001 DIODE 188355 80V 100mA SOD 23 SM DIODE BAV99 70V 450MA SOT 23 DIODE BAW56 70V 215MA SOT 23 DIODE BAW56 70V 215MA SOT 23 Description 272601107501 EC 100U 6 3V 20 D6 3 40 85 C 312304705351 EC 47U 25V 2096 D10X10 5 105 C SY 312278206152 EC 820U 4V 20 10X10 5 FPCAP PC3 PC5 PC7 PC9 481672400002 F W ASSY KBD CTRL SCORPIO U509 481672400001 F W ASSY SYS VGA BIOS SCORPIO U10 340671200020 FAN ASSY 8170 273000610019 273000610019 273000150013 273000150013 FERRITE ARRAY 1300HM 100MHZ 3216 FERRITE ARRAY 1300HM 100MHZ 3216 FERRITE CHIP 1200HM 100MHZ 2012 FERRITE CHIP 1200HM 100MHZ 2012 273000130039 FERRITE CHIP 1300HM 100MHZ 1608 273000130039 FERRITE CHIP 1300HM 100MHZ 1608 273000150036 FERRITE CHIP 320HM 273000130038 422665400002 100 7 2012 5 FERRITE CHIP 6000HM 100MHZ 1608 ASSY TOUCH PAD CASE KIT VENU Location s C280 C289 PC31 PC32 PC33 FA501 FA501 L504 L512 L514 L516 L520 L L27 L504 L523 L554 PL5 PL L1 L4 L513 L515 L16 L17 L18 L19 L20 L21 L2 L34 L35 L40 L545 L546 L54 L28 L39 L43 L44 L45 L531 L1 185 8575 N B Maintenance 9 Spare Parts List 16 Part Number 34
162. 671600006 LIS 9119 345611600001 BBER 8175 345611600002 RUBBER PAD LCD LOWER 8175 346669900004 INSULATOR INVERTER 7170 310102010407 SPC SCREW M2LA4 K HD NIB NL K L6 K HD NIB NLK ASSY LCD HANN 15 8175 421611600010 WIRE ASSY INVERT 81 75 310102030301 SPC SCREW M2L3 K HD NIB NLK 24266480001 3 LABEL CAUTION INVERT BD PITCHING 340671720002 HOUSING ASSY LCD 9 108 637 421611100002 WIRE ASSY ANTENNA 8575 345671700006 5 BRACKET LCD 8575 92 3 0102610603 SPC SCREW M2 421671600004 1 PO c SCALE 0 200 DATE 9 Jun O2 MATERIAL SEE NOTES REMARK EE B 50501115021 0501105 asp SCALE 0 048 DRAWING LCD ASSY HANNSTAR 15 1 03 8575 800 0 110 2 15 25 0 1 15 9152 _ cans centes elo p gt DRAWN DESIGNED CHECKED APPROVED ERIAL NO 441611120035 1510 31 251 4510 4 0 8 3 25 nternational Corp CONTENTS OF CHANGE 0 3 0 8 0 7 1 1 10 8 5 4 5 SHEET NO PDF created with FinePrint pdfFactory trial version 75 File name LCD
163. 7 pcsss 10K 1000P NA 0603 0603 SENSE4 6 4 SENSE4 18503 1 2 4 4 4 SHORT SMT1 GND FB2 5V Mitac 22 8575 1 8V 2 5V PWR LTC3707 Size lev Document C 411671700010 d later Bheet 24 Wednesday January 16 2002 508 23 848350 PUSB PUSA Sl4925DY Si4925DY PD3 PL5 poe 595 2327 ADINP 2 5 i 5 3 16 1 4 BEAD 1202 100 33UH I 310504 08050 xi IND CDR127 1 DC2010 POS 14 PC567 PC15 57 18 576 0010 cT 1000 PDA 100 100 oou 0 PRI5 PD511 10 4 0603 25V 1210 25 25V rere 50 50 DC2010 NA 06088 2245 0603 10 PR560 0603 0603 130K lt 50 0 1 4 t 0603 1 5VAS 9 PR562 GND GND 2IN M GND GND PR16 PF501 33K 1o N 2 0603 J 14 1206 4 4 FUSE 1206 BAS32L PUS14A 4 506 MLL34B LMV393M PR10 d DTA144WK SSOP8 137 976K PRO SOT23AN_1 PCS81 71 0603 0603 487 Pas D
164. 8575 N B Maintenance 3 Definition amp Location of Connectors Switches 3 1 Mother Board 2 J18 J19 J20 J21 J23 24 25 J27 J28 MDC Connector Primary IDE Connector Touch pad Connector Internal Micro Phone Jack L Speaker Connector Line Out Phone Jack R Speaker Connector TEEE1394 Port External Microphone Jack VRI Volume Control 95 8575 N B Maintenance 3 Definition amp Location of Connectors Switches 3 1 Mother Board B J503 Fan Connector J505 200 pin expansion DDR SDRAM Socket J506 200 pin expansion DDR SDRAM Socket 508 CMOS Battery Connector 11509 Mini PCI Socket lt SW503 Country Selection for Keyboard J508 96 8575 N B Maintenance 3 Definition amp Location of Connectors Switches 3 2 DC Power Board A 1 TV Out Jack J2 J3 J4 J5 J6 77 Power Jack AC adapter Parallel Port Connector USB Port Connector USB Port Connector Inverter Board Connector USB Port Connector USB Port Connector D D Connector PJ2 MISC Connector SWI1 Cover Switch 97 8575 N B Maintenance 3 Definition amp Location of Connectors Switches 3 3 ESB Board A B J501 SWI SW2 SW3 Sw4 SWS SW6 Easy Start Button Connector Programmable Easy Start Button Switch Programmable Easy Start Button Switch Programmable Easy Start Button Switch Programmable Easy Start Button
165. A 141 142 MD44 TADDRINDST DDR MD62 1 OM 16 RPX8 MD62 T DDR DDR MD11 3 14 11 143 144 143 144 7 62 599 980 MD62 13 7 DDR 11 MD11 13 4 4 4 4 2 15 MDEO hoec X DDR 4 13 15 MOS 11541 145 146 1545 MDAT 14 146 1545 T DOR MD DDR 3 14 RU T DDR MDIS DDR MD16 5 1 MD16 DQS5 147 148 DOMS 0055 14 148 DOMS DDR 5057 4 13 DQS7 DDR MD20 6 11 MD20 149 150 149 150 7 DDR 2087 DDR MDE 0057 13 7 DDR MD20 MD20 13 4 7 DDR MD63 DDR MDGS 2 i M63 MD63 13 7 DDR DQS2 DDR 0052 7 i Dos DQS2 13 2 1451 MD46 MD42 MD46 7 DDR 59 DDR MDS6 1 059 13 7 DDR MDI7 2 ur MD17 13 163 154 MDAT MD43 153 154 MD47 T DDR DES DDR MDS 58 leid 15 158 1 Het 7 DDR MDS8 058 13 ELK DERE et fgg or 1 161 162 48 163 164 52 48 163 164 52 ah 049 165 166 MD53 MD49 16 166 MD53 4 167 168 4 4 16 168 4 DOSE 169 170 DOME 5056 169 170 DOME 050 171 172 MD54 050 171 172 054 173 114 4 173 114 4 MDS 115 116 055 551 175 176 055 56 177 178 M60 MD56 177 178 060 H t mr T 0057 183 184 DOMT 0957 183 184 DOMT 25V DDR DDRVREF e 185 186 4 18 186 4 058 187 188 MD6Z 1658 18 188 MD62 MD59 189 190 MD63 MD59 189 190 MD63 SMBDATA 193 194 SMBDATA 193 194 11 15 SMBDATA 11 5 SMBDATA 1146 SwECLK SERRA BR 1119 SMBCLE 388 31 0
166. A Controller P18 23 R756 33 CLK T5350 MINI PCI Socket 21 R755 33 CLK_1394PCI To UL8 P iEEEIS94 Controller 2 142 8575 N B Maintenance 8 2 No Display System Clock Check FWDSDCLKO 2 5 CLK INT E 9 From previous page 1 R91 0 CLK_DDRO 2 5_DDR 4 R89 0 CLK_DDR1 L22 300Z 100M e CBVDDA 10 DD 5 R88 0 CLK cil C101 13 R94 0 CLK DDR2 1000P es 14 R93 0 CLK_DDR2 2 5_DDR 124 V 600Z 100M CBVDD 31223 20 BF OUT e VDD 0 2 FBINT C112 C150 ourr T 10 0 1 01 04 i u u u 299 22 L C196 V V J506 17 R98 0 CLK DDR3 2 Bit7 Bit6 Bit4 Bit5 CPU SDRAM ZCLK AGP Clock FS4 FS3 FS2 FSI FS0 MHz MHz MHz MHz 16 R97 0 CLK8_DDR3 0 0 0 0 0 66 7 66 67 66 67 66 67 Buffer 0 0 0 0 1 100 00 100 00 66 67 66 67 0 0 0 1 0 100 00 200 00 66 67 66 67 24 R100 0 CLK DDR4 0 0 0 1 1 100 00 133 33 66 67 66 67 0 0 1 0 0 100 00 150 00 60 00 60 00 ICS93722 0 0 1 0 1 100 00 125 00 62 50 62 50 25 R101 0 CLK_DDR4 0 0 1 1 0 100 00 160 00 66 67 66 67 0 0 1 1 1 100 00 133 33 80 00 66 67 0 1 0 0 0 100 00 200 00 66 67 66 67 26 R102 0 CLK DDRS 0 1 0 0 1 100 00 166 67 62 50 62 50 0 1 0 1 0 100 00 166 67 7143 83 33 0 1 0 1 1 80 00 133 33 66 67 66 67 R102 0 D
167. A410 is compliant with the latest PCI Bus Power Management Specification and provides several low power modes which enable the host power system to further reduce power consumption The PC Card CardBus Controller and IEEE 1394 Host Controller Device Class Specifications required for Microsoft OnNow M power management are supported Furthermore an advanced complementary metal oxide semiconductor CMOS process achieves low system power consumption Unused PCIA410 inputs must be pulled to a valid logic level using 43 k resistor 26 8575 N B Maintenance Features Ability to wake from 03 03 old Fully compatible with the Intel 430TX Mobile Triton chipset 208 pin low profile PDV or 209 ball MICROSTAR BGA ball grid array package 3 3 V core logic with universal PCI interfaces compatible with 3 3 V and 5 V PCI signaling environments Mix and match 5 V 3 3 V 16 bit PC Cards and 3 3 V CardBus Cards Single PC Card or CardBus slot with hot insertion and removal Burst transfers to maximize data throughput on the PCI bus and the CardBus bus Parallel PCI interrupts parallel ISA IRQ and parallel PCI interrupts serial ISA IRQ with parallel PCI interrupts and serial ISA IRQ and PCI interrupts Serial EEPROM interface for loading subsystem ID and subsystem vendor ID Pipelined architecture allows greater than 130M bps sustained throughput from CardBus to PCI and from
168. AA2 1 6 ADSTB m Eas Dico 22 HDR HAAZ 4 6 HLADSTB O ADSTBAO D 63 xA RSVD PWRGOOD 48 H PROCHOT ICPUPWRGD 6 REQHS RESET ed CPURST 6 6 3 DSTBP 0 3 6 TEMEA THRMDA SLP ISLP 15 REQ H2 RS 2 DBHO Sea 64 THRMDC THRMTRIP REQ RS DSTBPHO 22 THRMTRIP CCS CIHRMTRIP 20 THRMTRIPE pte REQHO RS 0 DSTBP mls 5 RSP H_RSHO 2 6 DBI DSTBP 2 803 6 H 4 TRDY HCTROY 6 DSTANNO psreps 1423 2 25 05 DSTBN O 02 TMS A 32 DSTBNI 24 TRST DSTBN 2 WMT478 NWD_14 DSTBN 3 WMTATSINWD 14 6 3 WMTATBINWD 14 52 6 A rg m _ uut mii ee RP506 PRECISION FSB COMPENSATION RESISTORS 0 R14 1 2 _ i NN NN i 1 R521 o 1 2 _ 1 tee i 1 26 VID o 4 sVCC i HINTA PLACE THESE INSIDE SOCKET CAVITY DESIGN GUIDE PAGE 236 m at gs 3 DESCRIPTION NO extra pull up i M M M M M M REQUEST NEW PART NUMBER FOR 51 1 Ohm 1 resistors required Re 2 R612 0603 0603 5 0603 lt 0603 0603 0603 0603 0603 5 0603 1 i 1 _ PWR i i TDO CPU DEBUG PORT EE GIN
169. AI Reference Resistor Analog M VVBWN AI Voltage Reference Analog M ROUT AO Red Signal Output Analog M GOUT AO Green Signal Output Analog M BOUT AO Blue Signal Output Analog M Power and Ground Signals Name Tolerance Power Plane Type Attribute AIXAVDD 3 3V MAIN Analog 55 OV GROUND Analog A4XAVDD 3 3V MAIN Analog A4XAVSS OV GROUND Analog AGPVSSREF 0V GROUND Analog AUX1 8 1 8V AUX Digital AUX3 3 3 3V AUX Digital CIXAVDD 3 3V MAIN Analog C1XAVSS OV GROUND Analog Power and Ground Signals continue Name Tolerance Power Plane Type Attribute C4XAVDD 3 3V MAIN Analog C4XAVSS OV GROUND DACAVDDI 1 8 MAIN Analog DACAVDD2 1 8 MAIN Analog DACAVSSI 0 GROUND Analog DACAVSS2 0 GROUND Digital DCLKAVDD 3 3 MAIN Digital DCLKAVSS 0 GROUND Analog DDRAVDD 3 3V MAIN Analog DDRAVSS OV GROUND Analog ECLKAVDD 33 MAIN Analog ECLKAVSS 0 GROUND Analog IVDD 1 8V MAIN Digital OVDD 3 3V MAIN Digital PVDD 3 3V MAIN Digital PVDDM 3 3V AUX Digital PVDDP 1 8V MAIN Digital PVDDZ 1 8V MAIN Digital SDAVDD 3 3V MAIN Analog SDAVSS OV GROUND Analog VDDM 2 5 3 3V MAIN AUX Digital VDDQ 1 5 1 8 3 3V MAIN Digitalv VDDZ 1 8V MAIN Digital VDDMCMP 1 8 MAIN Analog VTT 1 2 1 85V MAIN Digital ZIXAVDD 3 3V MAIN Analog ZIXAVSS OV GROUND Analog Z4XAVDD 3 3V MAIN Analo
170. ASSY HANNSTAR 5 1D3 8575 MM DD YY MODEL 8575 AND 8575N Revision 0A Contexts 514 TP507 TP505 TP506 TOUCHPAD METAL8 TOUCHPAD_METAL8 TOUCHPAD TOUCHPAD 8 MS MTG9 v MTG10 11 0060 1 3 J o MTG13 k OD6 0 FIDUCIAL MARK FD2 FDA FIDUCIAL MARK _ FIDUCIAL MARK FIDUCIAL MARK 7 7 7 Title Page 7 7 j Bonosens Bonema 7 7 0 7 i WE WEE awn System Block Diagram 2 Eis eras Eero Siero ers Sibooaes bom ws Power Block Diagram 3 gt gt gt J j 4 1 2 4 P4 CPU 2 2 5 SIS650 1 3 6 515650 2 3 5 Mc pee T E SIS650 3 3 8 7 7 7 7 7 TVILVDS ENCODER SiS301LV 9 4 LCD VGA INTERFACE amp LEDs 10 Uu m MAIN CLOCK amp CLOCK BUFFER 11 HT s me DDR SODIMMs 12 D DDR TERMINATION 13
171. CARD VCC ADS 555555 lt 95955 Be 888888 2225 C CAD3O AD30 3 CAD30 B3 CAD29 pe Bass 54029 CAD28 PCII410 HAVE INTEGRATED ALL PULL UP RES ABOVE 5 C4 CAD27 AD27 885 CAD27 ____________ A026 E CAD26 ADOS AD25 CAD25 CAD24 C7 CAD23 A023 DB CAD27 A022 e a AD21 canai Ae aa AD20 C2 S AD19 CAD19 Law AD18 CAD18 a nm uu ADIT CADIT LER Se 018 cans Card Bus Socket 014 CAD14 EI3 F13 CADIS AD13 Abia CADI2 CAD VCCA AD S19 api AD10 cano 58 AD9 CADO C DE H S ADB CADB T Huan ADT La E ADe CADS ADS CADS AD4 M13 a a aeoo AD3 CAD3 ee Iama AD 32 J11 113 CADO 1 35 capo moo 55 PCI ES TAD 142829 PCI 4 142829 CIBE2 i 38 IET 142829 5 r 2705 142820 IL caw mE 5 20 m os comove A
172. CSERR reports address parity errors and other system errors that could lead to catastrophic results CSERR is driven by the card synchronous to CCLK but deasserted by a weak pullup and may take several CCLK periods The PCI1410 can report CSERR to the system by assertion of SERR on the PCI interface CSTOP T O CardBus stop CSTOP is driven by a CardBus target to request the initiator to stop the current CardBus transaction CSTOP is used for target disconnects and is commonly asserted by target devices that do not support burst data transfers CSTSCHG CardBus status change CSTSCHG alerts the system to a change in the card s status and is used as a wake up mechanism CTRDY Vo CardBus target ready CTRDY indicates the CardBus target s ability to complete the current data phase of the transaction A data phase is completed on a rising edge of CCLK when both CIRDY and CTRDY are asserted until this time wait states are inserted CVS1 CVS2 IO CardBus voltage sense 1 and CardBus voltage sense 2 CVS1 and CVS2 are used in conjunction with CCD1 and CCD2 to identify card insertion and interrogate cards to determine the operating voltage and card type 126 5 6 uPD72872 IEEE1394 Controller PCI Cardbus Interface Signals 52 pins 8575 N B Maintenance Name yo PIN NO IOL Volts V Function Block REQ PCI Cardbus 5 3 3 Bus master Request Link
173. D 0603 470K 5 1M 0603 7 10K 2 1 HB 5 50 0603 eei iS 13 0603 a 117 NDS352P 4 5 D10 1 5 15 wake up uP a 1 __ 8 WAKE UP ral R125 4 16MHZ R519 WAKE Y 33 0603 GND GND m C95 D 1 Signal HI Low Peay EXTSMI afim 212 External Pull Up Down ox EH mb 5 M STMA3 FAN FAN Off FAN On ROMCS __1 R146 2 0 0603 8 DF13 3P 1 25V Tit 1 SB THRM it 144 517 15 SB THRM a504 a 1721 mecs 1 890 20 0900 14 meum Rees ADEN ER RIS 16 R691 0 1 222 282 18 4 THRMTRIP 0603 19 BAT R129 1 22 THERM ERR 1 H8 MODET 41 POWERBTN gt ANC PO 4 SCL THRM EE 2 0 15 2 ges 12 R m BAT C 23 4 THERM ERR 41 5080 4 SDATHRM atlama D 20 23 em I3 7 Ee Ls 10K 33 245 285 382 58 5VA prcM4TKA J SIS_PWRBTN 4TK 8 1206 0803 cas R127 tore 219 24 WE 2 9 15 SIS PWRBTNE Rea 1000P 1 12 gt 3 1 06030 27 sw_ssval 20 amp _ SHORTSMT3 Jogi 515 515 PWRBTN KIT o SN74CBTD3384 R725 DTC144TKA 1 31 0603 QSOP24A Close to74CBTD3384DBQ Reset ok 41 1 0603 KT 777 OPEN SMT3 Switch om R718 515 Les Fan Control sw502 4TK 8 1206 s H
174. DRS 0 1 1 0 0 80 00 133 33 66 67 66 67 0 1 1 0 1 95 00 95 00 63 33 63 33 0 1 1 1 0 95 00 126 67 63 33 63 33 0 1 1 1 1 66 67 66 67 50 00 50 00 143 8575 N B Maintenance 8 2 No Display Dower Good amp Reset Circuit Check 5VS 5VS 9 0502 R518 MIC5248 R517 3VS U2 10 10K MAX809 en _ ud CPU CORE EN P5 PWROK 5 VCCPVID vcc RESET e L csi4 OUT 018 C223 P7 R145 513 4 _ 100K 77 ln 3V gt D513 VCC CORE RLS4148 PWROK 2 R512 301 51 CPU CORE EN 2 AUXOK CPURST mur IGUI CPUPWRGD PU510 DIS 10K T 220 RLS4148 Host Memory H_PWRGD PUS08 4 D14 V Controller n 1 54148 PCIRST 45VS H8 PWROK gg SiS650 R214 J19 gt gt 4 e IDE_RST 8575 D gt R215 Power pus Px 10K PWR_ON H8_PWRON 49 AUXOK Module 4 018 e DTCIA44TKA pe Primary EIDE ccm R679 Pis PCIRST RI 019 Connector 10 20K PWROK amp V U509 P17 J12 Your E Secondary EIDE Connector 5VA 43V 014 V 9 Controller REES MuTIOL Po Pis Pos R725 H8 F3437 10K Media I O PCIRST 0504 U6
175. Hardwre Trap Table DDR DOM ABA 0635 032 C35 C30 C562 C36 cat C561 DDR DOS7 2 OOM SO 040 ju 610 Defaut embedded m 4 50 10V lt 50 10 efault 30 50K Ohm 5 77 85 JL505 JL506 EnablsPLL Disable PLL 0 Yes ECLKAVSS 4122 DCLKAVSS 1 DRAM _ SDR DDR DDR Yes 1 1 TRAPO 550 Debug Mode DisabsEnable 7 0 Yes JP NET20 JP NET20 014 GND GND PANEL IDO 0 CSYNC Video Bridge Disaie Enatie 017 22 H amp PWROK RSYNC PANEL 101 1 2 5V_DDR 1815 LSYNC PANEL 102 0 C600 015 WBWN 1 305 R587 7 26 PWRGD 0603D 010 50 33 06030 06030 0603D RLS4148 u12 C593 DLLEN 8570 4 A A A2 4 7KINA 1 1 o 50 MAX amp Q9 SOT23N 112 VRSET DRAM SEL RED 1 AA 2 PWROK 3 TRAPO R571 1 ATKNA DDRVREFA 4 ZVREF 15 23 PWROK RESET Yon 0603D 010 50V RSYNC Rie 1 47K 2 ii 35 5 4 on DACAVDD1 T avs DDRAVDD 1 i R612 R553 610 DACAVDD2 4 1 150 150 4 0603 0603D 0603D 50 1202 100 4 4 aye 1 1 4 2012 4 C632 C563 6584 C580 00107 0 10 75 100 5 7 010 10 2 100 130 0603 0603 1206 GND GND 0603p 1206 50v lt 10 GND GND 50V of 10 1 JL507 JL509 DDRAVSS 1 GND DACAVSS2 1 1 JP_NET20 2 5V_DDR DACAVSS1 JP_NET20 L GND PIDO R828 1 A 2 0603 LCD 100 PID1 R829 A A 2 0603 LCD 101 T vs PID2 R830 1 A
176. Hz PC 2100 1600 SiS 650 515961 Host amp Memory amp AGP Controller integrates a high performance host interface for Intel Pentium 4 processor a high performance memory controller a AGP interface and SiS MuTIOL Technology connecting w 515961 MuTIOL Media IO 256KB Flash EPROM Inside Includes System BIOS VGA BIOS and plug amp Play capability ACPI OMB on board memory Two JEDEC standard 200 pin small outline dual in line memory module SODIMM Support PC2100 amp PC2700 8 16 32 64 UMA DDR Clock Buffer ICS 93722 Card Bus Controller TI PCI 4410 One type II slot Card Bus TSBA1ABI of 1394 PHY Power Amplifier TI TPA0202 IR Module for HP3600 Modem 56Kbps V 90 worldwide MDC Modem HY of LAN ICS1893Y 10 10 100 base T PHY 8575 N B Maintenance 1 2 1 CPU Intel Pentium 4 Processor The Intel Pentium 4 processor Intel s most advanced most powerful processor is based on the new Intel NetBurst micro architecture The Pentium 4 processor is designed to deliver performance across applications and usages where end users can truly appreciate and experience the performance These applications include Internet audio and streaming video image processing video content creation speech 3D CAD games multi media and multi tasking user environments The Intel Pentium 4 processor delivers this world class performance for consumer enthusiast and business professional desktop users as well as for entry level workstati
177. L L L2 L3 Part Number Description 242664800013 LABEL CAUTION INVERT BD PITCHING 242600000195 LABEL SOFTWARE INSYDE BIOS M 294011200001 LED GRN H1 5 0805 PG1102W SMT D18 D19 D20 D21 D22 D23 273000150033 PHASEOUT FERRITE CHIP 1200HM 100 110 111 112 113 114 115 124 Location s 187 8575 N B Maintenance 9 Spare Parts List 18 Part Number 411503400201 271046037103 271046057102 271045087101 271045107101 271045107101 271045157101 271586026101 271002000301 271002000301 271071000002 271071000002 271071152101 271071152302 271071100302 271071100302 271071101101 271071101301 271071104101 271071104302 271071104302 271071103101 271071103101 271071103302 271071103302 Description Location s PWA PWA STINGRAY INVERTER BD MSL RES 003 1 5W 1 2512 SMT PR501 PR503 RES 005 1 5W 1 2512 SMT PR502 PR504 RES 008 196 2512 SMT 16 RES 01 1W 1 2512 SMT PR4 PR506 RES 01 1W 1 2512 SMT PR525 RES 015 196 2512 SMT PR515 RES 02 2W 1 2512 SMT 0 1 10W 596 0805 SMT 0 1 10W 5 0805 SMT L513 0 1 16W 0603 SMT PR17 PR522 PR523 R1 R511 0 1 16W 0603 SMT C305 C723 L538 PR1 PR524 1 0603 5 R506 R579 A DP D w ojo RES 1 5K 1 16W 596 0603 5 R64 RESO 1 16 5 0603 5 PR3 RESO 1 16 5 0603 5 PR514 PR521 R100 R101 R14 RES 100 1 16W 1 0603 SMT RES 100
178. L SEE NOTES TREATMENT REMARK MM SCALE 0 053 DRAWING NAME LT PF QDI XGA 14 1 DS 6312 30 80 15 25 0 2 0 3 80 180 15 0 3 45 180 315 315 800 0 2 0 3 0 5 0 8 CONTENTS OF CHANGE CHK APV D MM DD YY 0 4 0 1 0 6 DESIGNED CHECKED APPROVED D ATERIAL NO E Model name MAIN ASSY 8515 File name MAIN ASSY 1D5 8515 PDF created with FinePrint pdfFactory trial version http www fineprint com AD 416267114006 ROO SHEET MITAC International Corp OF SCALE 0 200 CONTENTS OF CHANGE CHK MM DD YY 315 800 B PART NO DESCRIPTION 4 503400201 PWA PWA STINGRAY INVERTER BD MSL 413 00020304 LCD QDII4IXILHO3 TFT 14 1 LCDS XGA QUANTA MP 03 340 11600018 14 8175 340 600020 14 8175 340 120010 COVER ASSY LCD 14 03 8515 340 120003 HOUSING ASSTILCD T4 03 8515 342 600005 RACKET 14 8175 342 600007 RACKET 14 8175 Cw 345 600001 UBBER PADS LCD UPPERS 8175 345 671600002 UBBER PAD
179. N SDATA OUT Hybrid PCTZMXUON Chip Set PCT303W 8575 N B Maintenance 1 2 9 Keyboard System H8 3437S Universal Keyboard Controller CPU Memory 8 bit timer 2 channels PWM timer 2 channels PC bus interface one channel Host interface HIF Keyboard controller A D converter Two way general register configuration Eight 16 bit registers or sixteen 8 bit registers High speed operation Maximum clock rate 16Mhz at 5V Available in temperature range 0 C 70 C Include 60KB ROM and 2KB RAM 16 bit free running timer One 16 bit free running counter Two output compare lines Four input capture lines Each channel has one 8 bit up counter two time constant registers Resolution 1 250 Duty cycle can be set from 0 to 10096 Include single master mode and slave mode 8 bit host interface port Three hosts interrupt requests HIRQI 11 12 Regular and fast A20 gate output Controls a matrix scan keyboard by providing a keyboard scan function with wake up Interrupts and sense ports 10 bit resolution 8 channels single or scan mode selectable 47 9 9 8575 N B Maintenance D A converter 8 bit resolution 2 channels Interrupts Nine external interrupt lines IRQO to 7 26 on chip interrupt sources Power down modes Sleep mode Software standby mode Hardware standby mode A single chip microcomputer On chip flash m
180. N2 13 11 CLK_DDRS MD27 67 68 MD31 MD27 6 68 1 7 DDR MD22 BER 2 4 i mpeg MD22 13 69 70 4 4 69 70 4 gr 1 5 12 7 DDR MD21 MD21 13 22 x 72 7 DDR 19 DRESS 11 woe MD19 13 2 14 74 7 24 MD24 13 r e OOE 4 E t DDR MD29 r1 MD29 18 7 29 29 13 7 DDR MD30 BEEN 2 RO RPXS 050 13 22791 7 DDR_MD27 L8 7 4 X DDR 28 3 14 MD28 DDR MD25 4 13 MD25 x tex X 7 DDR 2083 DDR Dass DQS3 13 87 88 8 88 7 DDR MD31 DDR 5 11 MD31 MD31 13 CLK DDR2 90 1 CLK 6655 89 90 1 7 DDR DQM3 DDR 13 DDR2 _DDRS 7 DDR MD26 DDR MD26 8 9 M26 MD26 13 93 94 1 i 93 94 i 7 DDR MD39 DDR MD39 RETI 1 16 REXB MD39 13 Z oea 95 7 8 DDR M38 2 15 MDSS MD38 13 rr 98 9 X DDR MD45 3 14 MD4S Me ds MATZ 99 100 MAT WAT 99 100 7 DDR MD DDR 4 13 Ld MD44 13 a 0 Mae o X DDR MD40 5 12 MD4O 104 104 4 7 DoR DOMS d a u zz 13 MAT 105 106 MAG MAT 10 106 MAG 7 DDR MD46 DDR 046 MD46 MD46 13 MAS 107 108 10 108 MA4 7 DOR O DDR MD42 8 9 MD42 aa 109 110 MA2 109 110 MA2 7 DDR_MD41 DDR 041 RPO 1 16 MD41 13 LL MM Oo m 12 mo at m
181. OL TUE Need very close to 961 BT WAKEUP R265 1 0603 EN BT R266 1 SZ RTGVSS LAN CRS CRE HG i o DETACH R267 0603 cb E n 688 11 12 SMBDATA SMBDATA RITT L AAA LAN DELK OLAN 19 er 142 SMBCLK SMBCLK Eee MIMDC 33 0603 i GPIO11 4 4 R181 1 _AC97 SDIN AC97 SDIN A2 E RIP ods 19 06030 1 LUNN 20 AC97_SDIN SDINO us 19 MDC SDIN usa AC SDINT sk 6240 a gata 00 801 AC97 SDOUT MIIAVDD MAVES Oe 161920 AC97_SDOUT C27 SPOUT W2 spour ilavss BS MIAVES ______ 4 SYNC AC97_RST 0 22 2 2 2 1920 ACOIRST SYNC 1 22 0603 BITCLK AC i 1920 AC97 SYNC lt 45 1 Need no close to 961 chip 1920 AC87_BITOLK AC BIT en T 2 imr ae 0603 i Catt R701 11 REFCLK1 REEL 3 osci GPIO1 CD RST CD_RST 17 0603 ME 06030 SB SPKR ENTEST VES HEURE E 6503 16 20 SB SPKR lt SPK GPlo2 H sB THRM 22 ave i 5 22 56 PWRBTN SIS PWRBTN PWRBTN GPIo3 8 lt __ 22 132 55 PME 2 Spt cae i Od ut Hwi LCD 103 _____ Close to 961 chip LCD 103 MIAVDD L e e TIE S t
182. OS setup is OK 2 Try another working drive and cable Re boot OK One of the following parts or signals on the motherboard may be defective use an oscilloscope to check the signals or replace Board level Troubleshooting the parts one at a time and test after each replacement Replace the faulty parts Parts Signals 014 5VS 112 5VS_HDD R215 PCIRST IDE_PDD 0 15 Motherboar 018 SENIORE R214 IDE PDA 0 2 JS6 IDE PDCS3 JS7 IDE_PDCS1 R202 IDE_PDIOR RP42 IDE PDIOW RP45 IDE_PDDACK R781 IDE_PDDREQ IDE 14 153 8575 N B Maintenance 8 7 Hard Drive Test Error Either an error message is shown or the drive motor spins non stop while reading data from or writing data to hard disk 5VS 5VS 154 5VS_HDD 19 R214 o 10K e 155 41 42 B C261 C275 C258 10K 273 01 RI 018 DTCI44TKA V V V PCIRST wal Q19 IDE_RST i DTC144TKA 5VS o R200 Dis rs PGI102W V 5VS O p R144 4 7K IDE PIORDY R202 10 PIORDY 2 7 8 D U14 RP42 PR45 d 10 8 t IDE PDD 0 15 PDDI0 15 2 18 gt MuTIOL PDA 0 2 IDE_PDCS3 RP528 33 4 PDA 0 2 PDCS3 33353638 Q 5 Media I O 5 IDE PDCS14 R781 33 PDCS1 37 Controller 8 IDE PDIOR R212 10 PDIOR 25 SiS961 IDE_PDIOW R213 2 PDIOW IDE_PDDACK R211 2 PDDACK 29 IDE_PDD
183. OUTZ PMEZ Ring indicate out and power management event output Terminal provides an output for ring indicate or PMEZ signals SPKROUT Speaker output SPKROUT is the output to the host system that can carry SPKR or CAUDIO through the PCI1410 from the PC Card interface SPKROUT is driven as the exclusive OR combination of card SPKRZ CAUDIO inputs SUSPEND I Suspend SUSPEND protects the internal registers from clearing when the GRST or PRST signal is asserted 123 8575 N B Maintenance 5 5 PCII410GGU PCMCIA Controller 16 Bit PC Card Interface Control Slots and B Name Vo Description Name Description BVDI STSCHG RI I Battery voltage detect 1 BVD1 is generated by 16 bit memory PC Cards that include batteries BVD1 is used with BVD2 as an indication of the condition of the batteries on a memory PC Card Both BVD1 and BVD2 are high when the battery is good When BVD2 is low BVD1 is high the battery is weak and should be replaced When BVD1 is low the battery is no longer serviceable and the data in the memory PC Card is lost Status change STSCHG is used to alert the system to a change in the READY write protect or battery voltage dead condition of a 16 bit I O PC Card Ring indicate RI is used by 16 bit modem cards to indicate a ring detection OE Output enable OE is driven low by the PCI1410 to enable 16 bit memory PC Card data outpu
184. P6 Li4 CPUAVDD P6 Lis PHYAVDD P6 L507 mee AGPAVDDI P6 1511 AGPAVDD2 P6 R62 P AGPVREF P7 113 mae SDAVDD 1516 E DDRAVDD L505 mee DCLKAVDD P7 L506 ECLKAVDD P7 L515 gt ZIXAVDD P7 112 ZAXAVDD L519 L510 L509 1 508 1512 L513 Q503 F503 L504 L520 8575 N B Maintenance P9 DVDD po VDDV po TVPLL_VCC po TVPLL VDD po LVDD0 1 po LVDD2 P7 LVDD3 P9 DAV_VDD P9 LPLL_VDD P10 LCDVCC VDDA Main Voltage Map L23 VDDA4S8 zi VDDZ 11 118 VDDCPU 11 121 VDDAGP VDDPCI 11 117 VDDREF 11 116 VDDSD 14 lt gt SZIXAVDD 14 126 SZ4XA VDD P19 L8 3 LAN Q529 20 3VS SPD P24 ie 2 5 From last page P24 ae 158 5 From last page P7 R613 DDRVREFA P7 R616 we DDRVREFB Pil 122 gt CBVDDA Pil 124 gt CBVDD P12 R95 DDRVREF R557 s ZVREF P7 L518 VDDZCMP 7 1514 DACAVDDI 2 1524 SVDDZCMP 138 IDEAVDD R109 gt SZVREF 137 8575 N B Maintenance 8 1 No Power When the power button is pressed nothing happens no fan activity is heard and power indicator is not light up
185. PCI to CardBus Interface to parallel single slot PC Card power interface switches like the TI TPS2211 Up to five general purpose I Os Programmable output select for CLKRUN Five PCI memory windows and two I O windows available to the 16 bit PC Card socket Two I O windows and two memory windows available to the CardBus socket 27 8575 N B Maintenance Exchangeable Card Architecture ExCA compatible registers are mapped in memory and I O space Intel 82365SL DF and 82365SL register compatible Distributed DMA DDMA and PC PCI DMA 16 Bit DMA on the PC Card socket Ring indicate SUSPEND PCI CLKRUN and CardBus CLKRUN Socket activity LED pins PCI bus lock LOCK Advanced submicron low power CMOS technology Internal ring oscillator OHCI link function designed to IEEE 1394 Open Host Controller Interface OHCI Specification Implements PCI burst transfers and deep FIFOs to tolerate large host latency Supports physical write posting of up to 3 outstanding transactions OHCI link function is IEEE 1394 1995 compliant and compatible with Proposal 1394a Supports serial bus data rates of 100 200 and 400Mbits second Provides bus hold buffers on the PHY Link I F for low cost single capacitor isolation 28 8575 N B Maintenance 1 2 5 1 Single Slot PC Card Power Interface Switch TPS2211A The TPS2211A PC Card power interface switch provides an integrated power management solution
186. PP SLIN DSPH WA SLIN 17 5 Ax P LPD3 PP LPD3 LPD3 5 Pa 5 RI 9 1827 0 0502 PACI28401Q GND 102 RP3 13 0 4 P LPD4 8 1 PP LPD4 CSP ow LPD4 6 Da P LPDS E PP_LPDS LPDS 2 5 P LPD6 PP LPD6 PSP ie LPD6 8 na P LPD7 5 4 PP LPD7 CSP 4 LPD7 9 Av Een T 10 P BUSY 7 2 PP_BUSY PSP wd io BUSY 2 na P PE amp _ CSP 4 oo PE 12 na P SLCT PP SLCT PSP SLCT T 5 3 RP4 et 2 0 4 23 TEN GND 102 GND 102 10 90uuo o E1e d 161 8575 N B Maintenance 8 11 Audio Failure No sound from speaker after audio driver is installed Audio Failure 1 Check if speaker cables are connected properly 2 Make sure all the drivers are installed properly Board level Troubleshooting Check the following parts for cold solder or one of the following parts on the motherboard may be defective use an oscilloscope to check the following signal or replace parts one at a time and test after each replacement 1 If no sound cause 2 If no sound cause 3 If no sound cause Yes of line out check of MIC check of CD ROM check Correct it the following the following the following parts amp signals parts amp signals parts amp signals Parts Signals Parts Signals Parts Signals I Try another known good speaker 014 AOUT R U14 5VS U14 CDROM_LEFT CD ROM U15 AOUT L U15 AVDDAD U15 CDROM
187. R NEC uPD72872 RJ45 5 3 3 m o m m 5 IC CARD TPS2211 Power Switch Socket SSOP 16 5 8 83 PCI 1410 PCMCIA CONTROLLER uBGA 144 Control PCI BUS AD O 31 Control LAN PHY 10 100 M ICS1893 MII Ultra DMA 33 66 100 Ultra DMA 33 66 100 LPC PC87393 IR Module TFDU6101E PRINTER PORT 2 S9 3013 Super TQFP 100PIN HUB 0 11 Pentium 4 Willamette Northwood C P U Micro FCPGA 478 pin 0 0 63 31 Control Pannel w SiS301LV _ CH7019 LVDS 128 pin LOFP Sis 650 CRT ISA BUS Flash ROM 512KB PLCC 32 702 Balls BGA HyperZip AD 1032 Thermal Recorder 200 Pin DDR SO DIMM Socket 2 DDR SDRAM PC2100 Memory Bus 266MHz WINIG OS Data Bus 266MHz 512MB sec 3 FOUR USB USB Cover Switch id AC Link Realtek ALC201 TPA 0202 Audio Codec Amplifier PQFP 48 5 M D C 30 pin H8 3437 Keyboard Controller PQFP 100 FAN1 For CPU FAN2 For D D External Microphone Internal Microphone Internal Speaker SPDIF JACK Clock Generator RJ 11 1CS952001 JACK Keyboard Touch PAD MiTAC 22 Te 8575 SYSTEM BLOCK DIAGRAM Document Number 41671700010 ie Wednesday January 16 2002 Ene 2
188. R8 0603 15501 IRF7811A IRF7811A IRF7811A NA 0605 d NE 4 2 i 4 1 2 4 6 508 508 508 10 VSS_SENSE 4 DH2 core 4 4 4 4 SHORT SMT1 PRI s s s PR503 0 GND PC538 4 4 0603 040 4 0603 1 50 core 2 1 a 2 1 25UH 083 PR504 Wu qd 1 Di D PU4 D PUG 1 5148100 Si4810DY 54810 PCS PC9 sos 508 508 205 758200 228200 DL2 core all all zx PD6 2512 av E 1 4 EC31QS04 TE12L s s 8 ERE ERE 444 LLL 44 x GND 4 GND Mitac gt Tite 8575 CPU PWR LTC1709EG 7 Size lev Document C Number 411671700010 d later Wednesday January 16 2002 Bheet 26 of 29 E A 5 ALWAYS 0509 5VA 9511 5VA 5VAS F504 0506 H8 AVREF1 Ea 1 N 2 21 Sense 5V 3216FF 1 ERR 5 x 3 4 e SHUTDN GND 1 ren o LP2951 028M D508 D516 ceos 31230109 1206 R621 6230103 0603 R618 508 FS 100 1 RLZ5 6B 025 68 MUL34B 800323 1206 A K 0603 16 GND RLS4148 GND GND GND GND 0510 2228 SW 5 K Break E DTCMAWK ay a GND V GND 21
189. RDY CDEVSEL CSTOP CPAR CPERR CBLOCK CVS1 2 CSERR CREQ CINT CAUDIO CSTSCHG CCD1 2 R2 D2 R2 114 R2 18 CGNT CCLK R218 0 Pis Joxoogs sng preg 168 8575 N B Maintenance 8 14 IEEE 1394 Failure An error occurs when a IEEE 1394 device is installed IEEE1394 Fail 1 Check if the 1394 device is installed properly 2 Confirm 1394 driver is installed ok Check the following parts for cold solder or one of the following parts on the mother board may be defective use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement Board level Troubleshooting Correct it Parts Signals 014 PCI AD 0 31 PCI SERR 1508 PCI 0 3 1394 PME U18 CLK 1394PCI PCI REQIZ U7 REQ SDATA J27 PCI FRAME SCLK L543 PCI IRDY 1 544 TEA Check if BIOS setup 15 ok Rost PCI TRDY TPA R224 PCI DEVSEL R198 PCI STOP TPB R197 PCI MR Replace Motherboard Re test Correct it R195 PCIRST PHYVDD R225 PCI GNTI PHYAVDD X6 PCI PAR PCI PERR 169 8575 N B Maintenance 8 14 IEEE 1394 Failure An error occurs when a IEEE 1394 device is installed 3VS PHYVDD 1543 e e C857 C231 C859 C233 4 74 0 3 5 PHYAVDD V 1544
190. REQ R205 82 PDDREQ 21 IDE_IRQ14 R210 82 IRQ14 31 154 8575 N B Maintenance 8 8 CD ROM Drive Test Error An error message is shown when reading data from CD ROM drive CD ROM Driver Test Error Board level Troubleshooting 1 Try another known good compact disk 2 Check install for correctly One of the following parts or signals on the motherboard may be defective use an oscilloscope to check the signals or replace the parts one at a time and test after each replacement Parts Signals Replace the faulty parts Check the CD ROM driver for proper Replace installation Motherboard 014 5VS J12 5VS_CD R215 PCIRST Q19 IDE SIORDY 018 IDE SDD 0 15 R214 IDE SDA 0 2 JS6 IDE SDCS3 JS7 IDE SDCSI R204 IDE SDIOR Z RP41 IDE_SDIOW RP44 SDDACK RP43 IDE_SDDREQ IDE_IRQI5 155 8575 N B Maintenance 8 8 CD ROM Drive Test Error An error message is shown when reading data from CD ROM drive 5VS 5VS 156 5VS_CD 2 R214 9 10K 157 e 38 42 R215 T C648 C74 C643 Pi 17 RI 018 DTCIA4TKA V V V PCIRST wal Q19 IDE_RST 5 DTCIA4TKA 5VS R743 DIS 4 PGI102W 5VS p R73 Pu 47K o IDE SIORDY R204 10 SIORDY 27 3 RP41 PR44 014 1098 d IDE SDD 0 15 SDD 0 15 TH gt m Mu
191. RIGHT 2 Exchange another known good Replace U16 3 5 121 MICI J12 CDROM_COMM charger board Motherboard VRI 128 n L529 3VS_ SPD C272 R185 L28 SPK OFF L531 R186 L530 SPDIFOUT L532 Q528 Q529 Correct it 124 162 8575 N B Maintenance 8 11 Audio Failure No sound from speaker after audio driver is installed AUDIO IN L553 1202 100 43VS 19 C88 108 5VS AVDDAD L554 18505 1207 100 WY e 2538 L C120 D D 01 77 77 R154 22 AC97_SDIN 8 _ Pis AC97 SDOUT 5 97 SYNC R764 2 10 U14 AC97 RST AC97 BITCLK R699 2 6 MuTIOL 4 Media I O SPK_OFF Controller To next page pe 2 515961 R150 24576Muz EL SB SPKR AVDDAD e 3 R703 cm C246 10K ln 1 BOUT RU 4 R697 cm 470K Olu 4 E 12 06 ae m lt 0513 R698 20K PCI1410GU 7T DVDD1 2 AVDDI 2 Pao 15 Audio Codec ALC201 LINE IN L LINE IN R PC L532 21 6002 100 J AVDDAD Internal R728 R727 2 7K MIC_VREF 2 2K e 2 MIC e 47P L C788 R739 T dn x 2 7K 128 3 con 1531 6002 100 MIC_3 4 21
192. RPSOA 8C LAN ND 3 P av 15 LAN MTXDO 45 TP RXN 4 RAN 15 LAN MTXDI 2 18 LANCMTXD2 4 d 15 LAN MTXD3 1x03 Po Hio 12 1k 0 2 1 06030 42 06030 1 0603 06030 2 22 06030 43 IXER 3 LAN CT 06030 Th TXCLK 15 LAN 15 LAN 23 06038 6 CoL 10 2 1 CRS TOTCSR 18 Resen nopee H F Lock FAL x 4 52 REF our ANSEL 28 x PS ppxset 4 20 m ouma 1 6030 6030 Res SOV s 06050 eranyeoraatt 8333333833333 899299999999 LX LA x 4 12201 T Q 06030 060309 06030 TXC7X5 gt C65 274012500401 27 06030 55 LAN LaN ND LA rj Lc 313 414 ITE ow 8 16 9 02 GNDi av 817 GNDS 1 R121 0603 20 MONO OUT EN 8PX1 1 016MM 3 n TAKA MODEM SPK pk 20 1 CONN PJS AST 8 5 6 T CLOSE TO TET zr 8 a 1 ICS1839 9 10 4 C210 S i Jos ios Jos mj 5 0603 5 i 9 0603 1 19 CLOSETO MDC some me 4 708 59 3 E 2 m cer sync 1520 Layout Note pd CHOKE PLP32168 1 Ld 15 820 n EIE CSI EE MDC
193. S SI4925DY P MOSFET SO 8 288209410001 TRANS SI9410DY N MOSFET 040HM S 288205003004 TRANS SUD50N03 11 N MOS TO252 273001050039 TRANSFORMER 10 100 BASE LF H80P 271911103906 VR 10K 2096 0 05W RN 101GAC1OKPGJ 1671700002 WIRE ASSY ANTENNA 8575 1668300005 WIRE ASSY BIOS BATTERY HOPE 1668300005 WIRE ASSY BIOS BATTERY HOPE 421671600010 WIRE ASSY INVERT 8175 1671700004 WIRE ASSY MDC EMI 8575 WIRE ASSY TOUCHPAD 8575 XTAL 14 318M 50PPM 32PF 7 5 4P S 274011431422 XTAL 14 318MHZ 16PF 20PPM 8 4 25 274011600408 XTAL 16MHZ 16PF 50PPM 8 4 5 2P 274012457405 XTAL 24 576M 30PPM 16PF 7 5 4P S 274012457406 XTAL 24 576MHZ 16PF 50PPM 8 4 5 274012500401 XTAL 25MHZ 30PPM 18PF 4P SMT B 421671700001 274011431408 Location s PU2 PU5 PU507 PU509 PU502 PU512 PU513 PU504 PU505 PU3 PU6 PU7 PU8 PU Q503 PU1 PU2 PU4 PU5 PU501 PY U3 4508 4508 502 501 X503 X6 1 4 191 8575 N B Maintenance 9 Spare Parts List 22 Part Number Description Location s 274013276103 XTAL 32 768KHZ 20PPM 12 5PF CM20 mE DESCRIPTION COVER HINGE 1D3 8575 LCD ASSY QDI XGA 14 1 103 8515 COVER ASSY KB 1D3 8575 BD OPTION 86 05 8175 COVER DUMMY 103 8575 PWA PWA 8170 ESB BD COVER ASSY 103 8575 TOUCH PAD MODULE TM41PD 350 ASSY TOUCH PAD CASE KIT VENUS RACKET ASSY T P INSULATOR 8175 PWA 8515 T P BD LATE 81 15
194. S hd com Jus 1 MBID AUXOK 48 MB 100 ORNA i Acer TAE 10 ACPILED lt ACPILED Ve ipi PT MEC dai 4 eros 0 01U 0 10 100 28 BT WAKEUP m m GPIO13 R40 1 A A 2 0603 gt 5 _ 20 LCD 103 0909 0809 ae 28 MPCIACT R255 0603 GPlo14 Plog lt 22 A m 158 u17 5VA hi 1 9 77 close to 961 28 EN BT Rest 0603 6 15 GPIO9 so 22 06 JP NET20 t NCO GNDO 4 VIN H 28 BT DETACH R258 0805 GPlO16 B 10 GND 4 NC GPOM 281 0288 10 28 MPCI PD GPIO17 GP1011 0805 TP 9895 22U I L 6 12 CPU STP amp 11 80 20 SOT25 GND T BGA335_36 760 GND E 305 1 GND 3VA a Bois EDEN me leas R685 R862 9 TOKINA 1 RTC 0603 0603 aid ED Need no close to 961 chip MB IDO MB 101 MMBT3906L lt E i R686 R863 E 3 5V 4 D16 RLS4148 RP36 128 d i EE Aa 51K R175 3 SERIRQ i 0603 R162 4 1 4 tawv 4 BATOK 4 LPC ADZ 4 0603 cass 2 _ L i 10 20 J 4 4 1206 GND GND 4 0603 1210 C279 i 4 10V R180 1U 0010 FS 100 R729 4 7K 06030 4 0603 003 1206 i 1 LPC DROR 4 i Ri
195. SERVICE MANUAL FOR 8575 BY Sissel Diao TESTING TECHNOLOGY DEPARTMENT TSSC Jun 2002 ADAC gt 8575 N B Maintenance Contents 1 Hardware Engineering Specification cccsscsccsscssscccccccccsscccssccccccsccsscsccsssccecsscsoccess 4 INE Introduction a 4 1 2 System Hardware Parts ren 7 1 3 Other Functions oa oo e enata Dra cisco balan ode tet tuni ind Pane Chega tad 53 L4 Peripheral Components 58 1 5 cu e Ue e DOM Rt uei 61 1 6 Appendix 1 515961 GPIO Definitions 63 L7 Appendix 2 H8 Pins Definitions rere Tubo ri Vete des bep 64 1 8 Appendix 3 8575 Product Specifications sss Ime me eee enne 70 2 System View and Disassembly v eoo caua e edo eee vea eee epe UU eau ui 73 rdum ira me RME E RC rr 73 2 2 System Disassembly 2 oet S abo NEM ME REL LM E 76 3 Definition amp Location of Connectors Switches 94 ST Mother Board E IPTE T vetet exa as Nav E et gu P ds a 94 3 2 DC Power Board T 97 3 3 ESB Board er CER 98 5 4 Touchpad oe eR RN erre Eo AED at
196. STHIO Ans ESH resreino 351 0603 RIS ATT Dus Eo vp TESTHO MASTER RESETE H IGNNER 56 1 0603 R752 HOFTE VIDS R 2 4025 5 2 AT BR 0 H_BRHO 6 UEM ed Hore VE 2 6 MR HB Df48 BPRU HINIR 56 1 0603 R754 HDi HD A9 VIDT R GTLREF2 3 Ain BRIE H_BPRI 6 Hoia Duis 0024 HDMS R Griners GTLREEZ 3 Mn H5 H_DBSY 12 0450 2 25 Moo GTLREF2 21 21 DBSY 11 Dis PUST GTLREF1 59 CPU GTLREF A22 DEFER CDEFERM 6 0852 HD 53 VCC CORE AF2 GTLREFO LCORE gt p NU hme ied pies XE 4023 HORS Wo HDHSS AC24 TESTHW 25 6 A p d 5 VCCPVID AEE 26 0856 PLL NCCA ____ 020 yeca TesTHis ACZO __ ____ 0603 HOES 25 HD ST 21 TESTHIZ ART IERR pAC3 16A 2 0603 _ ue HE 26 VCC SENSE 2 28 D 58 2 VCCIOPLL TESTHI7 A822 TESTE 29 HINIT IH INIT amp 15 0859 0459 VSSA VSSA TESTHIG JESTHIG H HOPS Y21 HD 60 SENSE lt E26 1 o 6 HOW s Uy MN TP amp AA22 E21
197. Switch Programmable Easy Start Button Switch Programmable Easy Start Button Power Switch 98 8575 N B Maintenance 3 Definition amp Location of Connectors Switches 3 4 Touch pad A B J501 4 SW2 4 SW3 4 SWA Touch pad Board to Touch pad Connector 1502 Touch pad Board to Main Board Connector Scroll Up Button Switch Left Button Switch Right Button Switch Scroll Down Button Switch JP1 MDC Jump Wire Connector MDC LAN Transfer Board to M B Connector 99 8575 N B Maintenance 4 Definition amp Location of Major Components 4 1 Mother Board C qf Je 18 Intel Pentium 4 Processor mPGA478 Socket LF H80P LAN Buffer SiS650 IGUI Host Memory Controller ISC1893Y LAN Controller PCI1410GGU PCMCIA Controller 1CS93722 Clock Buffer Flash ROM SN74CBTD3384 Level Shift 515961 MuTIOL Media I O Controller ALC201 Audio CODEC TPA0202 Audio Amplifier uPD72872 IEEE 1394 Controller PU10 CM8500 1 25V Generator 100 8575 N B Maintenance 4 Definition amp Location of Major Components 4 1 Mother Board B 504 SiS301LV Chrontel CH7019 505 TPS2211 PC Card Slot Power Switch 508 ICS952001 Clock Generator 509 H8 F3437 Micro Controller 511 PC87393 Super I O PU508 LTC1709EG 7 CPU Power Generator PU510 LTC3707 1 8V 2 5V Generator PU511 TL594C PWM D
198. T GND2 24 GROUND AD 9 PCM SYNC RESET 2 Ape ADIB 88 POL PCI 14 18 29 4 CLK B4 87 saviz H 5 RxD 88 ADS 891 ADIS run 6 RTS 88 ADE 32 m 20 amp p Ap15V89 3 L 5 0 RESERVED WIPA 0 35 x GNDO E 99 anit RESERVED WiPA 1 HX 15 WAKEUP UP GND3 1 9 101 102 4 85 12 4 2 GROUNDS GROUND14 40 BE TxD ANTENNA H 242 5105 AC SDATA IN AC OUT 106 4 NS X107 AC Bir AC CODEC 198 gt 15 BT DETACH DETACH ncs 15 x RJA 3P NA R803 c2 HIROSE gt 109 AC 1 1 AC RESET 110 315 NC6 8 10 AUDIO RESERVED 12 0603 2534 98 Nco BLUETOOTH ANTENNA AUDIO GNDO GROUND15 114 4 vcc GND5 gt t svs AUDIO SYS AUDIO IN FS GND6 15509 51L svs _ SYS AUDIO IN GND Hie gt CI MPCIACT 15 e vcc GND7 2003 9 19 AUDIO GND1 AUDIO GND2 120 GND8 2 121 RESERVEDS 2108 vecsva 3 3VAUX 1 24 8050209 ay BLUETOOTHINA gar 18511 ND 50020 GND1 SUYIN SHORT SMT4 9502 124 0 8 6 SHORTSMIE SPEED 4 827 101 0038 C846 NZ 5 7 PIN24 124 AUX POWER BT GND BT GND GND 1 507 l
199. T OFF puso quee MODEL m H8 Hardware Hardware Standby input pull high input pull high CE s E TET Daa gt ow N gt om P fp IE Perse oom wr wseroor fo fo Jo Port A COMOS input level input high min 3 5V input low max 1 0V 21 H8 SUSC System resume from S4 soft off through RTC A H8 SUSC o to S4 soft off H8 SUSB Invert from SUSA to wake up H8 when system resumed by MDC modem and internal LAN Inform system power management status Crystal input 64 8575 N B Maintenance PCI reset gate Name H8 Pin During After ON STANDBY Function Definitions RESET RESET OFF Port B TTL input voltage input high min 2V input low max 0 8V 91 H8 SB PWRBTN Keep H Power button trigger VIA8231 on off Duplicate Power BTN 53V H8 WAKE WAKE KeepH H Wake up SB at ACPI mode 5 3V i eus Jo p D norem ai pedo pet enm em 58 7 fo Lithium ion battery charging CV mode voltage ERN ERR RR Port 1 TTL input voltage input high min 2V input low max 0 8V mus o Gu fa mom oe _ p e o em rommeememi ZEE xen ermm Des ps pee f fo M De n pen romes
200. TERFACE terminating resistors should be place close to South Bridge PM S PS MTG23 IDE_SDD1 1 SDD1 44 IDE_SDDACK IDE_SDDACK R170 1 22 0603 SDDACK 1 IDE SDD2 2 12 8002 JDE TDE SDIORF 176 1 0803 ie oat IDE 000 15 m IDE Sp 5 ig sb we lt R202 1 1 2 __PIORDY ed IDE SDIOWI 10220038 77 IDE PDDO 4 48 IDE SDDS t it 5005 IDE SIORDY _ R204 1 10 2 0603 SIORDY RP43 IDE PDD1 2 18 PDDT IDE SDDG 7 10 5006 14 IDE lt A 334 IDE PODZ 2 DE SDDT 10 388 IDE 1 RPSQASC 14 IDE IDE PDDS 4 4g PDDS n 1 IDE SDAT SDAT 5 12 00 lt IDE R205 1 14 IDE SDAZ 2 1 SDAZ Te eee 6 ke TRNA IDE SDDREQ 182 sporea 14 IDE 80534 IDE SDCSR Rm 135 Cz Esci IDE PDDE 1 020 ipe lt 44 IDE SDCST baa 14 lt R201 450 2 18014 IDE 5008 1 E RoS 1 3002 4 5508 14 IDE lt AR TDE SDD10 En 30010 T 502 5 30012 PODACKE IDE PDIORA R212 1 0808 IE 08 1 REA DE S0013 5 1 30018 TDE POIOWH R23 1 22 2 0603 IDE 2 45 PDD IDE_SDD14 I 40 50014 14 IDE_PDIOW DE PODI 2 12 0010 56675 i 3 RPs28 DE PODZ PODIZ IDE PDAO 354 DAO IDE PODIS i
201. TH o 1 BLUETOOTH MODULE AD O 31 14 18 29 PCI AD 31 3509 U519 33 RING 2 gt A IN GND1 uet 4 ge pA 2 OUT GND2 MNA Tx H xX gt PCM SYNC RESET E3 x L pir 3 2 4 PCM CLK 84 DTC144TKAINAS o rep 105 5 Bi x 0536 iE LED1_GRNP LED2 12 6 RTS 88 10 5 MPCI PD tun zm LED1_GRNN LEDZ YELN 44x gil 6 X 47 CHSGND RESERVE ities Pt R801 4 9 19 INTA 20 MINIPCI INTD 8800 1 A A 2 0603 PCLINTDA 14 17 gt 14 17 29 PCIINTC Ox 21 RESERVEDO RESERVEDS HEX 15 BT WAKEUP WAKE UP GND3 GRoUNDO 3 3VAUXIO x TxD ANTENNA 11 CLK MINIPCI 25 26 PCIRST 7 9 14 17 18 21 29 GNp4 4 22 GROUND1 28 34 NC4 14 17 PCI REQ24
202. TIOL IDE_SDA 0 2 IDE_SDCS3 RP43 33 4 SDA 0 2 SDCS3 31 33 34 36 1 Media I O IDE_SDCS1 R208 33 SDCS14 35 8 Controller 8 IDE SDIOR amp R176 10 SDIOR 24 515961 IDE_SDIOW R203 22 SDIOW amp 25 IDE SDDACK R170 22 SDDACK 28 IDE_SDDREQ R207 82 SDDREQ 2 IDE_IRQIS 8777 82 IRQIS 29 156 8575 N B Maintenance 8 9 USB Test Error An error occurs when a USB I O device is installed Check the following parts for cold solder or one of the following USB Test Error Check if the USB device is installed properly Including charge board parts on the mother board may be defective use an oscilloscope Yes to check the following signal or replace the parts one at a time pom Correct it and test after each replacement Board level Troubleshooting No Parts Signals M D D D 3V USBOC3 5 Replace another known good charge USBCLK SB USBP5 board or good USB device USBOCO 1 USBP5 5 USB5VCC5 SBPO USBP3 SBOVCCS5 USBP3 SBP1 5 1 Replace Motherboard Re test OK Correct it No 157 8575 N B Maintenance 8 9 USB Test Error 1 An error occurs when a USB I O device is installed
203. TM terminal should be connected to Vpp through a Ik resistor SE should be tied to ground through a 1k resistor and SM should be connected directly to ground Four package terminals are used as inputs to set the default value for four configuration status bits in the self ID packet and are tied high through a 1k resistor or hardwired low as a function of the equipment design The PCO C2 terminals are used to indicate the default power class status for the node the need for power from the cable or the ability to supply power to the cable See Table 9 for power class encoding The C LKON terminal is used as an input to indicate that the node is a contender for either isochronous resource manager IRM or for bus manager BM The TSBA1ABI supports suspend resume as defined in the IEEE 13942 2000 specification The suspend mechanism allows pairs of directly connected ports to be placed into a low power state suspended state while maintaining a port to port connection between bus segments While in the suspended state a port is unable to transmit or receive data transaction packets However a port in the suspended state is capable of detecting connection status changes and detecting incoming TPBIAS When the port of the TSB41AB1 is suspended all circuits except the band gap reference generator and bias detection circuit is powered down resulting in significant power savings For additional details of suspend resume operation see IEEE 13942 2
204. The CH7019 is a Display Controller device which accepts two digital graphics input data streams One data stream outputs through an LVDS transmitter to an LCD panel while the other data stream is encoded for NTSC or PALTV and outputs through a 10 bit high speed DAC The TV encoder device encodes a graphics signal up to 1024x768 resolution and outputs the video signals according to NTSC or PAL standards The LVDS transmitter operates at pixel speeds up to 165MHz per link supporting 1600x1200 panels at 60Hz refresh rate The device can also accept one graphics data stream over two 12 bit wide variable voltage ports which support nine different data formats including RGB and YCrCb RGB must be used for LVDS output A maximum of 330M pixels per second can be output through dual LVDS links The TV Out processor will perform non interlaced to interlaced conversion with scaling flicker filtering and encoding into any of the NTSC or PAL video standards The scaler and flicker filter are adaptive and programmable for superior text display Eight graphics resolutions are supported up to 1024 by 768 with full vertical and horizontal under scan capability in all modes A high accuracy low jitter phase locked loop is integrated to create outstanding video quality Support is provided for MacrovisionTM In addition to TV encoder modes bypass modes are included which allow the TV DAC s to be used as a second DAC 21 8575 N B Maintenance The LVDS tran
205. Two Arithmetic Logic Units ALUSs on the Pentium 4 processor are clocked at twice the core processor frequency This allows basic integer instructions such as Add Subtract Logical AND Logical OR etc to execute in half a clock cycle For example the Rapid Execution Engine on a 1 50 GHz Pentium 4 processor runs at 3 GHz 256KB Level 2 Advanced Transfer Cache The Level 2 Advanced Transfer Cache ATC is 256KB in size and delivers a much higher data throughput channel between the Level 2 cache and the processor core The Advanced Transfer Cache consists of a 256 bit 32 byte interface that transfers data on each core clock As a result the Pentium 4 processor 1 50 GHz can deliver a data transfer rate of 48 GB s This compares to a transfer rate of 16 GB s on the Pentium III processor at 1 GHz Features of the ATC include Non Blocking full speed on die Level 2 cache 8 way set associativity 256 bit data bus to the level 2 cache Data clocked into and out of the cache every clock cycle 8575 N B Maintenance Advanced Dynamic Execution The Advanced Dynamic Execution engine is a very deep out of order speculative execution engine that keeps the execution units executing instructions The Pentium 4 processor can also view 126 instructions in flight and handle up to 48 loads and 24 stores in the pipeline It also includes an enhanced branch prediction algorithm that has the net effect of reducing the number of branch mis prediction
206. USBREF 27 USBP1 vss9 0022 432 NA i e opti 15510 VDDZ3 m vssti 0024 9 6121 9422 5912 VDDZ5 1 22 100 i 0603 0603 vonzo SHOULD BE 433 18 5 10 3314 5815 VTTO Leto voc cone OSC12MHI i VSS16 vim VSS17 ot GND SD 2 MH 2 15519 15520 LREQ i vss21 10 AUX kiai CLOSE TO 961 vss22 NCH 332 NG12 LINKON C816 0603 27 USBP5 Law USBF 3524 13 GPIO22 EEDI SAUNA 2 50 p20 22 EET 22 06030 14 20 __ 62021 EESK i VSS26 NC15 ips R163 VSS27 NC16 AUX 4 2 0603 27 EST USBPS N 8528 Notz USBVDD C20 GPIO24 EECS i vsszo NC19 22 06030 yeast Nota E20 2023 EEDO C124 L538 C125 C126 ease Nee USBVSS 20P NA in y 22 100 i USBREF 0603 0603 0603 van 22 Big OSCI2MHI 5 120Z 100M NA 5 10 i 23 015 USBPVSS 1608 SZ T VSSZ5 NC24 USBPVDD usBVss GND i vase 25 A17 OSCI2MHO zi Nen SBREFAVDD Big USBVSS 5529 NC28 per cran e NCO 211 CT 0 s R246 CLOSE TO 961 i NC2 Nc32 28 USBP4 USBP4 P Nc33 HRA 22 06030 140 D12 NC4 Pato gh ete Rhy
207. VA 2 1 0 2 Expended mode with On Chip ROM enable a J R611 1 A 2 0603 CDACTP BAVOOINA ok C522 1 Single Chip mode TU NA 0603 RP509 1206 D503 SCROLL 1 8 5VA H8 AVREF1 5VA 40 gt SCROU NUM 1 E 10 N M 2 1 D Close to H8 3437F 2 Close to H8 3437F 17 HDDACTP 4 5 3 BAV99 NA 24 CDACTP R610 4 2 0603 4 17 CDACTP D504 040 010 188 AT 1 Quick Switch Button Stuff RP589 R1359 EASY START BTN ni owa o 20908 p LED Stuff RP590 R1360 oe BAVOQINA HDDACTP KO 1 SCROLL PVC CORE 3 4 NUM BAV99 NA Ha PWRSW 5 6 CAP 2 TT From Batin 41 51 7 B CDACTP 3 Come From Battery 5 10 1 2 bsos t eat vor 0603 _ Fire 059 12 4 i 1 2 0603 BATT A SPEED 4 5100 0000 101 1 512 C736 crar 777 HORISHRMA SPX2 77 _ 224 1206 0603 0603 GND_H8 JP BEAD DFS 50V 50V 06038_DFS 0509 Signal HI Low 8898 988828 GND ut 929 555222 Normal Suspend 1 ROT 79 38 TU 2 RO prani He LuMm 27 3 1 40 1 6 4 PTAIANA 6 KO 4 43 012 R642 KOS 3 44 CHARGE CTR R
208. WK SOT23AN 1 pases 2N7002 SOT23 FET GND 25 BATTI 579 26578 0 010 50 lt 10 06030 GND MiTAC 22 Title 8575 1 25V PWR CM8500 amp BAT CONN Size lev Document 411671700010 d later Bheet 28 of 29 Wednesday January 16 2002 18V P 183 2050 1 4050 P OPEN SMTA PL7 Vince 1 D VMAIN M 4 1202 100 4 J 25V_P 2 5V_DDR 2012 12 _ 11 71 Pcs28 1 546 1 100 2 10 boh m 10U 25V 25V 0603 0503 1210 OPEN SMTA 4 50 10 25V To I do 2 3950 EL 1 PUSO7 HAG GND S14416DY y OPENSMT4 508 GND 4 TG18 4 prd PR537 0603 1 2 5V Ls 254 7 sm8 1 18V 2 1 es 4 CS 1 27002 10UH 4 4 50723 D124C 4 PSON 10 1527 Posas FERE 2227 PWR ON Hs 2 7002 Q538 ONA 010 1000P NA 50123 548 DTC144TKA 0603 9909 EM 0603 0 0220 002 45 0
209. a D ae ee ee ee E eed 99 3 5 Da ghter KT 99 8575 N B Maintenance Contents 4 Definition amp Location of Major Component 100 AL Mother BO ar ev rer 100 5 Pin Description of Major Component cccccccscccccccsccccccccssccscccssssccccscsscsccesesssscessees 102 5 1 Intel Pentium 4 Processor mPGAZ478 2 5 102 5 2 515050 IGUI Host Memory Controller sss III II Ie ehe he he ere 108 5 3 515691 Mu TIOL Media UO Conktroller 1 redet rta ddr oe ba ta deoa 113 5 4 SiS301LV Chrontel CH7019 TV LVDS Encoder me he eren 119 5 5 PCIAI0GGU PCMCIA Controller eerte e x oa ka deer 122 5 6 uPD72872 IEEET394 Controller RF ania CR eeu 127 6 System Block Dia Gram que dose eva deed 129 7 Mamtenance Dine wis cce 130 mL 130 ye nude e 131 Maintenance Diagnostics abl a xU REOR e EH OR EON Sa VP HN TO oa eras 133 8 Beni di ptr 134
210. above keyboard From left to right that indicates LAN CD ROM HARD DISK DRIVE NUM LOCK CAPS LOCK and SCROLL LOCK 55 8575 N B Maintenance 1 3 6 Battery Status Battery Warning System also provides Battery capacity monitoring and gives user a warning so that users have chance to save his data before battery dead Also this function protects system from mal function while battery capacity is low Battery Warning Capacity below 10 Battery Capacity LED flashes per second system beeps per 2 seconds System will suspend to HDD after 2 Minutes to protect users data Battery Low State After Battery Warning State and battery capacity is below 4 system will generate beep for twice per second Battery Dead State When the battery voltage level reaches 7 4 volts system will shut down automatically in order to extend the battery packs life 1 3 7 Fan power on off management FAN is controlled by H8 embedded controller using AD2201 to sense CPU temperature and PWM control fan speed Fan speed is depended on CPU temperature Higher CPU temperature faster Fan Speed 56 8575 N B Maintenance 1 3 8 CMOS Battery CR20323V 220mAh lithium battery When AC in or system main battery inside CMOS battery will consume no power or main battery not exists CMOS battery life at less 220mAh 5 8uA 4 years Battery was put in battery holder can be replaced 1 3 9 I O Port One Power Supply Jack One Ext
211. age 1 1V to 3 3V 55 Power TVPLL VDD TV PLL Supply Voltage 3 3V 54 Power TVPLL VCC TV PLL Supply Voltage 3 3V 51 Power TVPLL GND TV PLL Ground 37 Power DAC VDD DAC Supply Voltage 3 3V 39 48 Power DAC GND DAC Ground 7 13 19 20 26 32 Power LVDD LVDS Supply Voltage 3 3V 4 10 16 23 29 35 Power LGND LVDS Ground 1 Power LPLL VDD LVDS PLL Supply Voltage 3 3V 3 Power LPLL GND LVDS PLL Ground 121 8575 N B Maintenance 5 5 PCII410GGU PCMCIA Controller PCI Interface Control Name Description DEVSEL T O PCI device select The PCI1410 asserts DEVSEL to claim a PCI cycle as the target device As a PCI initiator on the bus the PCI1410 monitors DEVSEL until a target responds If no target responds before timeout occurs then the PCI1410 terminates the cycle with an initiator abort Power Supply Name vo Description GND Device ground terminals Power supply terminal for core logic 3 3V VCCCB Clamp voltage for PC Card interface Matches card signaling environment 5 3 3 V VCCI Clamp voltage for interrupt subsystem interface and miscellaneous I O 5 V or 3 3 V VCCP Clamp voltage for PCI signaling 5 V or 3 3 V PC Card Power Switch FRAME T O PCI cycle frame is driven by the initiator of a bus cycle FRAME is asserted to indicate that a bus transaction is beginning and data transfers continue while this signal is asserted
212. al After PRST is deasserted the PCI1410 is in a default state When the SUSPEND mode is enabled the device is protected from the PRST and the internal registers are preserved outputs are placed a high impedance state but the contents of the registers are preserved STOP T O PCI cycle stop signal STOP is driven by a PCI target to request the initiator to stop the current PCI bus transaction STOP is used for target disconnects and is commonly asserted by target devices that do not support burst data transfers TRDY T O PCI target ready TRDY indicates the primary bus target s ability to complete the current data phase of the transaction A data phase is completed on a rising edge of PCLK when both IRDY and TRDY are asserted Until both IRDY and TRDY are asserted wait states are inserted 122 Multifun 8575 N B Maintenance 5 5 PCII410GGU PCMCIA Controller ction and Miscellaneous Pins Name Uo PCI Address and Data Description MFUNCO vo Description IO Multifunction terminal 0 MFUNCO can be configured as parallel PCI interrupt INTA GPOO socket activity LED output ZV switching outputs CardBus audio PWM GPE or a parallel IRQ MFUNCI IO Multifunction terminal 1 MFUNCI can be configured as GPOI AD 31 0 I O PCI address data bus These signals make up the multiplexed PCI address and data bus on the primary interfac
213. annel B H Sync 1 8 3 3 M VBHSYNC multiplexed with AAD30 VBVSYNC Uo Channel B V Sync 1 8 3 3 M VBVSYNC multiplexed with AAD31 VBDE vo Channel B Data Valid 1 8V 3 3V M VBDE multiplexed with AAD27 VBGCLK Uo Channel B Clock Output 1 8V 3 3V M This clock is used to trigger dual edge data transfer Perfect duty cycle is required VBGCLK multiplexed with AD STBI VBD 11 0 Channel B Data 1 8 3 3 M VBD 11 0 multiplexed with AAD VAHSYNC Uo Channel A H Sync 1 8V 3 3V M VAHSYNC multiplexed with AAD18 VAVSYNC Uo Channel A V Sync 1 8V 3 3V M VAVSYNC multiplexed with AAD17 VADE Uo Channel A Data Valid 1 8V 3 3V M VADE multiplexed with AAD16 VAGCLK Uo Channel A Clock Output 1 8V 3 3V M This clock is used to trigger dual edge data transfer Perfect duty cycle is required VAGCLK multiplexed with AD STBO VAGCLK vO Channel A Differential Clock Output To support 1 8V 3 3V M Chrontel VAGCLK multiplexed with AD STBOZ VAD 11 0 Channel A Data 1 8V 3 3V M VAD 11 0 multiplexed with AAD 110 8575 N B Maintenance 5 2 515650 IGUI Host Memory Controller Interface Name Pin Attr Signal Description VOSCI I 14 318 Reference Clock Input 3 3V M HSYNC Horizontal Sync 3 3V M VSYNC Vertical Sync 3 3V M INTA Internal Interrupt Pin 3 3V M VGPIO 1 0 IO Internal VGA GPIO pins 3 3V M VCOMP Al Compensation Pin Analog M VRSET
214. ard V Y 138 8575 N B Maintenance 8 1 No Power Battery Charge When the power button is pressed nothing happens no fan activity is heard and power indicator is not light up D D Board PU9B PU9A SI4835DY SI4925DY SI4925DY PD3 PLS PL6 10804 1202 100 UE 2 ADINP gt e YY 1 YY e Js LL To next page 5VAS 1 2 DS L 4 567 5 62 PRIS PD511 T 00 T 100p PR560 100K PR7 100K RLZ20C EC31QS04 130K 20K e 1006 125V 4 LI OVP V MMBT2222A e 2 PUSI4A 33k PD L PCS8I PR558 LMV393M PL501 BAS32L 2N 2N7002 LI OVP S e 4 5 e V PRO PRIO V 487K 13 7k 976K CHARGING 506 VADJ 2 P VADI 1 TYPE NIMH CELL DAD DAADR From Hs DTC144WK TA 2 k A gt 2 m 12 40V 9 1 0 0 From H8 T PQ2B PQ2A From H8 5 PR544 12308 1 NDC7002N NDC7002N M 47K D 12 60V 1 1 0 PQ507 27002 V 5 8 11 L PC573 PR545 PC569 CLC2 150P IM 12 Pos 16 2IN vcc 2IN CHARGE I CTR
215. art and firmly insert the OS DIMM into the socket at 20 degree angle Then push down until the retaining clips lock the SO DIMM into cover 2 Replace the SO DIMM cover 3 Replace seven screws to fasten the SO DIMM socket cover 84 8575 N B Maintenance 2 2 7 LCD Disassembly 1 Open the top cover Remove easy start buttons cover keyboard and heatsink See section 2 2 2 and 2 2 3 Disassembly 2 Remove the two hinge covers and remove two screws fastening the easy start button board Figure 2 15 3 Disconnect the LCD cables from the system board and remove four screws of the hinges Now you can separate the LCD assembly from the base unit Figure 2 16 o ee e e Figure 2 15 Remove LCD hinge cover Figure 2 16 Remove cables and screws and button board to separate LCD Reassembly 1 Attach the LCD assembly to the base unit and secure with four screws on the hinges 2 Reconnect the LCD cable connectors to the system board 3 Fit the easy start button board and secure with tow screws 4 Replace two hinge cover the heatsink keyboard and easy start buttons cover 85 8575 N B Maintenance 2 2 8 LCD Panel Disassembly 1 Remove the LCD assembly See section 2 2 7 Disassembly 2 Remove the four rubber pads and two screws on the lower part of the panel figure 2 17 3 Insert a flat screwdriver to the lower part of the frame a
216. ble suspend resume Register bits give software control of contender bit power class bits link active control bit and IEEE 1394a 2000 Features IEEE 1394a 2000 compliant common mode noise filter on incoming TPBIAS Extended resume signaling for compatibility with legacy DV devices and terminal and register compatibility with TSB41LV01 allow direct isochronous transmit to legacy DV devices with any link layer even when root Power Down features to conserve energy in battery powered applications include automatic device power down during suspend device power down terminal link interface disable via LPS and inactive ports powered down Failsafe circuitry senses sudden loss of power to the device and disables the port to ensure that the device does not load TPBIAS of the connected device and blocks any leakage path from the port back to the device power plane Software device Reset SWR Industry leading low power consumption Ultralow power sleep mode 39 8575 N B Maintenance Cable power presence monitoring Cable ports monitor line conditions for active connection to remote node Data interface to link layer controller through 2 4 8 parallel lines at 49 152 2 Interface to link layer controller supports low cost TI bus holder isolation and optional J electrical isolation Interoperable with link layer controllers using 3 3 V Single 3 3 V supply operation Low
217. ceived on the TPA cable pair and the encoded strobe information is received on the TPB cable pair The received data strobe information is decoded to recover the receive clock signal and the serial data bits The serial data bits are split into two four or eight bit parallel streams depending upon the indicated receive speed resynchronized to the local 49 152 MHz system clock and sent to the associated LLC Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration The outputs of these comparators are used by the internal logic to determine the arbitration status The TPA channel monitors the incoming cable common mode voltage The value of this common mode voltage is used during arbitration to set the speed of the next packet transmission In addition the TPB channel monitors the incoming cable common mode voltage on the TPB pair for the presence of the remotely supplied twisted pair bias voltage 32 8575 N B Maintenance The TSB41AB1 provides 1 86 V nominal bias voltage at the TPBIAS terminal for port termination This bias voltage when seen through a cable by a remote receiver indicates the presence of an active connection This bias voltage source must be stabilized by an external filter capacitor of TPBIAS is typically Vp 0 2 V when the port is not connected to another node The line drivers in the TSB41ABI operate in a high impedance
218. cement Signals 3 LAN DATAIO LAN DCLK LAN MTXDJ 0 3 LAN MTXE LAN MTXC LAN COL LAN CRS LAN MRXDV LAN MRXER LAN MRXC LAN MRXDJ 0 3 OSC25MHI OSC25MHO 165 8575 N B Maintenance 8 12 LAN Test Error An error occurs when a LAN device is installed 43V 13V LAN LS 120Z 100M 3V_LAN 3V MIIAVDD 7 8 15 16 25 54 63 e Y Y VDD 0 6 is R609 0 4 1207 100 c232 L 230 C754 _ 108 LAN i m e YY ss 1522 101 H MUSS e e t Dos m ik C44 c45 c62 c59 C64 kel POAC 18 R49 22K LK RESETN e e e 33 LAN_DATAIO HET V Toga C54 Gat R177 33 LAN_DCLK 31 0 V r e NE C41 R166 33 LAN_MTXD0 45 gt 10P V R41 R46 R167 33 LAN MTXDI 46 56 56 9 R172 33 LAN MTXD2 47 y 14 RXIN L6 a e R178 33 LAN_MTXD3 20M H PIR 5 DUNT 3 014 15 PJRX Pio LAN MTXE 43 U5 13 REIN e 3 gt ayy
219. cost 24 576MHz crystal provides transmit receive data at 100 200 400Mbits s and link layer controller clock at 49 152MHz Low cost high performance 48 64 pin TQFP PHP PAP thermally enhanced packages increase thermal performance by up to 210 Meets Intel mobile power guideline 2000 1 2 7 AC 97 Audio System Advance Logic Inc ALC201 515961 is an AC 97 2 1 compliant controller that communicates with companion Codecs 515 a digital serial link called the AC link The ALC201 is an AC97 2 2 compatible stereo audio codec designed for PC multimedia systems The ALC201 provides the way for PC98 and PC99 compliant desktop portable and entertainment PCs where high quality audio is required The ALC201 AC 97 CODEC provides a complete high quality audio solution 40 8575 N B Maintenance Features 9 Single chip audio CODEC with high S N ratio gt 90 dB 18 bit ADC and DAC resolution Compliant with AC 97 2 2 specification Meet performance requirements for audio on PC2001 systems 18 bit stereo full duplex CODEC with independent and variable sampling rate 4 analog line level stereo input with 5 bit volume control LINE IN CD VIDEO AUX 2 analog line level mono input PC BEEP PHONE IN Mono output with 5 bit volume control Stereo output with 5 bit volume control 2 MIC inputs Software selectable Power management 3D Stereo Enhancement Headphone output with 50mW 20ohm driving capabili
220. d in the system ITP_CLK 1 0 no connects in the system These are not processor signals 104 8575 N B Maintenance 5 1 Intel Pentium 4 Processor mPGA478 Socket Name Type Description LINT 1 0 Input LINT 1 0 Local APIC Interrupt must connect the appropriate pins of all APIC Bus agents When the APIC is disabled the LINTO signal becomes INTR a maskable interrupt request signal and LINT1 becomes NMI a nonmaskable interrupt INTR and NMI are backward compatible with the signals of those names on the Pentium processor Both signals are asynchronous Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as or LINT 1 0 Because the APIC is enabled by default after Reset operation of these pins as LINT 1 0 is the default configuration Name Type Description LOCK Input Output LOCK indicates to the system that a transaction must occur atomically This signal must connect the appropriate pins of all processor system bus agents For a locked sequence of transactions LOCK is asserted from the beginning of the first transaction to the end of the last transaction When the priority agent asserts BPRI to arbitrate for ownership of the processor system bus it will wait until it observes LOCK deasserted This enables symmetric agents to retain ownership of the processor system bus throughout the bus l
221. d to DRAM CPU off Twister K Partial off Suspend PCMCIA Suspend Audio off SDRAM self refresh Suspend to HDD devices are stopped clock and power down System status is saved in HDD All system status will be restored when powered on again 1 5 2 Other Power Management Functions HDD amp Video access System has the ability to monitor video and hard disk activity User can enable monitoring function for video and or hard disk individually When there is no video and or hard disk activity system will enter next PMU state depending on the application When the VGA activity monitoring is enabled the performance of the system will have some impact 62 8575 N B Maintenance 1 6 Appendix 1 515961 GPIO Definitions SB SiS961 GPIO Signal MUX Name Function Loo a 20 SMBDATA Mitac Definition IDO CD SB_THRM IEXTSMI ICLKRUN LCD IDO LCD IDI LCD ID2 WAKEUP Z IN SPK OFF CPU_STP IMPCIACT DPRSLPVR PWRONZ2 HILOA LO HE CD RST SMBCLK SMBDATA Buffer Type O o E E E lt o Power Plane AU 3 gt c gt gt gt z gt c gt gt gt gt gt
222. d to accept posted writes to improve bus utilization Function 1 of PCI4410 is compatible with IEEE1394A and the latest 1394 open host controller interface OHCI specifications The chip provides the IEEE1394 link function and is compatible with data rates of 100 200 and 400Mbits per second Deep FIFOs are provided to buffer 1394 data and accommodate large host bus latencies The PCIA410 provides physical write posting and a highly tuned physical data path for SBP 2 performance Multiple cache line burst transfers advanced internal arbitration and bus holding buffers on the interface are other features that make the 4410 the best in class 1394 Open HCI solution 25 8575 N B Maintenance The 4410 provides an internally buffered zoomed video ZV path This reduces the design effort of PC board manufacturers to add a ZV compatible solution and ensures compliance with the CardBus loading specifications Various implementation specific functions and general purpose inputs and outputs are provided through eight multifunction terminals These terminals present a system with options in PC PCI DMA PCI LOCK and parallel interrupts PC Card activity indicator LEDs and other platform specific signals ACPI compliant general purpose events may be programmed and controlled through the multifunction terminals and an ACPI compliant programming interface is included for the general purpose inputs and outputs The PCI
223. d uses VREF2 2 as the threshold voltage VREF2 divide by 2 function is generated on chip 121 HPD Hot Plug Detect Internal Pull down This input pin determines whether a CRT monitor is connected to the VGA connector When terminated the monitor is required to apply a voltage greater than 2 4 volts Changes on the status of this pin will be relayed to the graphics controller via the HPINT pin pulling low 122 Out HPINT Hot Plug Interrupt Output This pin provides an open drain output which pulls low when a termination change has been detected on the HPD input 108 In SPC Serial Port Clock Input This pin functions as the clock input of the serial port and uses VREF2 2 as the threshold voltage VREF2 divide by 2 function is generated on chip 36 VSWING LVDS Voltage Swing Control This pin sets the swing level of the LVDS outputs A 2 4K Ohm resistor should be connected between this pin and LGND pin 35 using short and wide traces 106 In AS Address Select Internal Pull up This pin determines the device address of the serial port 58 RESET Reset Input Internal Pull up When this pin is low the device is held in the power on reset condition When this pin is high reset is controlled through the serial port 119 5 4 SiS301LV Chrontel CH7019 TV LVDS Encoder 8575 N B Maintenance Pin Type Symbol Description
224. ddition to integrated GUI SiS650 also can support external AGP slot with AGP 1X 2X AX capability and Fast Write Transactions A high bandwidth and mature SiS MuTIOL technology is incorporated to connect SiS650 and 515961 MuTIOL Media I O together 515 MuTIOL technology 15 developed into three layers the Multi threaded I O Link Layer delivering 1 2GB bandwidth to connect embedded DMA Master devices and external PCI masters to interface to Multi threaded I O Link layer the Multi threaded I O Link Encoder Decoder in 515961 to transfer data w 533 MB s bandwidth from to Multi threaded I O Link layer to from SiS650 and the Multi threaded I O Link Encoder Decoder in 515650 to transfer data w 533 MB s from to Multi threaded I O Link layer to from SiS961 8575 N B Maintenance An Unified Memory Controller supporting PC133 or DDR266 DRAM is incorporated delivering a high performance data transfer to from memory subsystem from to the Host processor the integrated graphic engine or external AGP master or the I O bus masters The memory controller also supports the Suspend to RAM function by retaining the CKE pins asserted in ACPI S3 state in which only AUX source deliver power The 515650 adopts the Shared Memory Architecture eliminating the need and thus the cost of the frame buffer memory by organizing the frame buffer in the system memory The frame buffer size can be allocated from 8MB to 64MB The Integrated GUI features a high performance 3D acc
225. disable enable R555 1 40K NA USB 2 RP518 013 sip EE AAA GPIO24 EECS i cs vecl amp AC97 PCICLK PLL enable disable R608 2 USB 0658 GPIO21 EESK 2155 E MITA EE A d EC Fane lige QE 3 USB 2 GPIO22 EEDI 24 See ENGET ge 55 C129 USB OC24 SB debug mode enable disable i 4 5 USB 4 GPi3EEDO 40 UNA e tes 4 DR CAE weary set NZ 0603 Title USB_OC5 Trap mode PCI AD ROM i cp 10K 4 1206 NM93CAGINA 8575 SIS961 3 3 508 Size lev Document C Number 411671700010 ais Wednesday January 16 2002 16 of 2 1 2 3 4 5 5 IDE 0000 15 uf 14 IDE 90000 15 IDE IN
226. e 1 2 1 2 _ 4 1 BAT R86 1 2 10K BALOK R66 1 10K MPU 101 80 0803 vee So 0003 0515 BAT DATA R653 4 2 10K 0603 IMP811 R724 0603 GND 501143 GND Es 507 0603 05 G 1 FANO 5VS 511 1 8 Ruso 35 oko TONA 2 180 MLL34B d 7 4 0510 GND 6 5 Signal HI Low A 3 2 lt gt 15 2 100K 1 0603 DANZI2KITMG 5 474 77 PERC FAN FAN On TT 4 DF13 3P 1 25H q J H8 RESET 5 os marli 2 GND 8680 4 3 R6 R502 b 5VASO 4 V P sv 1 8 1 21 FAN Stet M cra 33 lt 3 58 50125 GND 45V E 1 SCWEAN SPD 0608 1000P 1 R652 06030 10K 144 0603 GND R634 777 SCHJFAN SWITCH 10K GND 0603 SUSB Q514 3 0519 ERES 7 15 S3AUXSW SOAUXSWE 1 Suse AP FAN1 SPD Lo FANO SPD 9512 ao aa DTC144TKA DTC144TKA Poe use FAN SPD Te 8575 MICROCONTROLLER H8 ize Document 411671700010 0A Number Wednesday January 16 2002 Z7 2 1 25V CM8500 CONNECTOR amp BATTERY PL8 1 25Vo 3 3UH 0603
227. e During the address phase of a primary bus PCI cycle AD31 ADO contain a 32 bit address or other destination information During the data phase AD31 ADO contain data socket activity LED output ZV switching outputs CardBus audio PWM GPEZ or a parallel IRQ Serial data SDA When VPPDO and VPPDI are high after a PCI reset the MFUNC 1 terminal provides the SDA signaling for the serial bus interface The two pin serial interface loads the subsystem identification and other register defaults from an EEPROM after a PCI reset MFUNC2 IO Multifunction terminal 2 MFUNC2 can be configured as PC PCI DMA C BE 3 0 I O PCI bus commands and byte enables These signals are multiplexed on the same PCI terminals During the address phase of a primary bus PCI cycle C BE 3 C BE 0 define the bus command During the data phase this 4 bit bus is used as byte enables The byte enables determine which byte paths of the full 32 bit data bus carry meaningful data C BE 0 applies to byte 0 AD7 ADO C BE 1 applies to byte 1 AD15 AD8 C BE2 applies to byte 2 AD23 AD 16 and C BE 3 applies to byte 3 AD31 AD24 CardBus audio PWM GPE or a parallel IRQ MFUNC3 IO Multifunction terminal 3 MFUNC3 can be configured as a parallel IRQ or the serialized interrupt signal IRQSER MFUNC4 IO Multifunction terminal 4 MFUNC4 can be configured as PCI LOCK GPI3 GPO3 socket activity LED output ZV s
228. e 2 CAD23 CADS and CC BE 3 applies to byte 3 CAD31 CAD24 CINT CardBus interrupt CINT is asserted low by a CardBus PC Card to request interrupt servicing from the host CIRDY T O CardBus initiator ready CIRDY indicates the CardBus initiator s ability to complete the current data phase of the transaction A data phase is completed on a rising edge of CCLK when both CIRDY and CTRDY are asserted Until CIRDY and CTRDY are both sampled asserted wait states are inserted CPAR IO CardBus parity In all CardBus read and write cycles the PCI1410 calculates even parity across the CAD and buses As an initiator during CardBus cycles the PCI1410 outputs CPAR with a one CCLK delay As a target during CardBus cycles the calculated parity is compared to the initiator s parity indicator a compare error results in a parity error assertion 125 8575 N B Maintenance 5 5 PCII410GGU PCMCIA Controller CardBua PC Card Interface Control Slots A and B Continued Name Description CPERR IO CardBus parity error CPERR reports parity errors during CardBus transactions except during special cycles It is driven low by a target two clocks following that data when a parity error is detected CREQ CardBus request CREQ indicates to the arbiter that the CardBus PC Card desires use of the CardBus bus as an initiator CSERR CardBus system error
229. e with four screws 3 Replace the keyboard Then replace easy start buttons cover 81 8575 N B Maintenance 2 2 4 HDD Module Disassembly 1 Carefully put the notebook upside down 2 Remove one screw and slide the HDD module out of the compartment Figure 2 10 3 Remove six screws to separate the hard disk drive from the metal shield Figure 2 11 Figure 2 10 Remove HDD module Figure 2 11 Disassemble the hard disk Reassembly 1 To install the hard disk drive place it in the bracket and secure with six screws 2 Slide the HDD module into the compartment and secure with one screw 82 8575 N B Maintenance 2 2 5 CD ROM Drive Disassembly 1 Carefully put the notebook upside down 2 Remove one screw fastening the CD DVD ROM drive Then hold the CD DVD ROM drive and slide it outwards carefully Figure 2 12 Figure 2 12 Remove one screw to loose the CD DVD ROM drive Reassembly 1 Push the CD DVD ROM drive into the compartment 2 Secure the CD DVD ROM drive with one screw 83 8575 N B Maintenance 2 2 6 SO DIMM Disassembly 1 Carefully put the notebook upside down 2 Remove seven screws to access the SO DIMM socket Figure 2 13 3 Full the retaining clips outwards 0 and remove the SO DIMM Figure 2 14 Figure 2 13 Remove the SO DIMM cover Figure 2 14 Remove the SO DIMM Reassembly 1 To install the SO DIMM match the SO DIMM s notched part with the socket s projected p
230. ease refer to the A 32 Software Developer s Manual Volume 3 System Programming Guide RESET Input Asserting the RESET signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents For a power on Reset RESET must stay active for at least one millisecond after VCC and BCLK have reached their proper specifications On observing active all system bus agents will deassert their outputs within two clocks RESET must not be kept asserted for more than 10 ms while PWRGOOD is asserted A number of bus signals are sampled at the active to inactive transition of RESET for power on configuration This signal does not have on die termination and must be terminated on the system board RS 2 0 Input RS 2 0 Response Status are driven by the response agent the agent responsible for completion of the current transaction and must connect the appropriate pins of all processor system bus agents PROCHOT Output PROCHOT will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature This indicates that the processor Thermal Control Circuit has been activated if enabled RSP Input RSP Response Parity is driven by the response agent the agent responsible for completion of the current transaction during assertion of RS 2 0 the signal
231. ed to the P6 micro architecture used on today s Pentium III processors One of the key pipelines the branch prediction recovery pipeline is implemented in 20 stages in the NetBurst micro architecture compared to 10 stages in the P6 micro architecture This technology significantly increases the performance frequency and scalability of the processor 400 MHZ System Bus The Pentium4 processor supports Intel s highest performance desktop system bus by delivering 3 2 GB of data per second into and out of the processor This is accomplished through a physical signaling scheme of quad pumping the data transfers over a 100 MHz clocked system bus and a buffering scheme allowing for sustained 400 MHz data transfers This compares to 1 06 GB s delivered on the Pentium III processor s 133 MHz system bus 8575 N B Maintenance Level 1 Execution Trace Cache In addition to the 8KB data cache the Pentium 4 processor includes an Execution Trace Cache that stores up to 12K decoded micro ops in the order of program execution This increases performance by removing the decoder from the main execution loop and makes more efficient usage of the cache storage space since instructions that are branched around are not stored The result is a means to deliver a high volume of instructions to the processor s execution units and a reduction in the overall time required to recover from branches that have been mis predicted Rapid Execution Engine
232. elerator with 2 Pixel 4 Texture and a 128 bit 2D accelerator with pipeline BITBLT engine It also features a Video Accelerator and advanced hardware acceleration logic to deliver high quality DVD playback A Dual 12 bit DDR digital video link interfaced to SiS 301B Video Bridge packaged in 100 pin PQFP is incorporated to expand the 515650 functionality to support the secondary display in addition to the default primary CRT display The SiS301B Video Bridge integrates an NTSL PAL video encoder with Macro Vision Ver 7 1 L1 option for TV display a TMDS transmitter with Bi linear scaling capability for TFT LCD panel support and an analog RGB port to support a secondary CRT The primary CRT display and the extended secondary display TV TFT LCD Panel 2 nd CRT features the Dual View Capability in the sense that both can generate the display in independent resolutions color depths and frame rates 8575 N B Maintenance Two separate buses Host t GUI in the width of 64 bit and GUI t Memory Controller in the width of 128 bit are devised to ensure concurrency of Host t GUI streaming and GUI t MC streaming In PC133 or DDR266 memory subsystem the 128 bit GUI t MC bus will attain the AGP4X or AGP 8X equivalent texture transfer rate respectively The Memory Controller mainly comprises the Memory Arbiter the M data M Command Queues and the Memory Interface The Memory Arbiter arbitrates a plenty of memory access requests from the GUI or AGP con
233. emory Maximum 64kbyte address space Support three PS 2 port for external keyboard mouse and internal track pad Support SMI SCI trigger input Cover switch Battery charging control Smart Battery monitoring Control D D system on off Fan control and LED indicator serial interface 100pin TQFP 48 8575 N B Maintenance 1 2 10 System Flash Memory BIOS 2 M bit Flash memory Flashed by 5V only User can upgrade the system BIOS in the future just running flash program 1 2 11 Memory System 64MB 128MB 256MB 512MB x64 200 Pin DDR SDRAM SODIMMs JEDEC standard 200 pin dual in line memory module SODIMM Utilizes 200 Mb s and 266 Mb s DDR SDRAM components 64MB 8 Meg x 64 H 128MB 16 Meg x 64 H and HD 256MB 32 Meg x 64 HD 512MB 64 Meg x 64 HD VDD VDDQ 2 5V 0 2V VDDSPD 2 2V to 5 5V 2 5V I O SSTL_2 compatible Commands entered on each positive CK edge DQS edge aligned with data for READs center aligned with data for WRITEs Internal pipelined double data rate DDR architecture two data accesses per clock cycle Bi directional data strobe DQS transmitted received with data 1 e source synchronous data capture Differential clock inputs CK and be multiple clocks CK1 CK1 etc Four internal device banks for concurrent operation 49 8575 N B Maintenance Selectable burst lengths 2 4 o
234. emperature has reached a level beyond which permanent silicon damage may occur Measurement of the temperature is accomplished through an internal thermal sensor which is configured to trip at approximately 135 C Upon assertion of THERMTRIP the processor will shut off its internal clocks thus halting program execution in an attempt to reduce the processor junction temperature To protect the processor its core voltage VCC must be removed following the assertion of THERMTRIP Once activated THERMTRIP remains latched until is asserted While the assertion of the RESET signal will de assert THERMTRIP if the processor s junction temperature remains at or above the trip level THERMTRIP will again be asserted after RESET is de asserted TMS Input TMS Test Mode Select is a JTAG specification support signal used by debug tools STPCLK Input STPCLK Stop Clock when asserted causes the processor to enter a low power Stop Grant state The processor issues a Stop Grant Acknowledge transaction and stops providing internal clock signals to all processor core units except the system bus and APIC units The processor continues to snoop bus transactions and service interrupts while in Stop Grant state When STPCLK is deasserted the processor restarts its internal clock to all units and resumes execution The assertion of STPCLK has no effect on the bus clock STPCLK is an asynchronous input TRDY
235. er source on the system this pin should be tied together with PWROK PWRBTN I Power Button 3 3V 5V AUX This signal is from the power button switch and will be monitored by the ACPI compatible power management unit to switch the system between working and sleeping states RING I Ring Indication GPIO8 vO An active RING pulse and lasting for more than 4ms will cause 3 3V 5V AUX wakeup event for system to wake from 51 55 BCLK_STP Stop CPU clock GPIO12 Uo Output to the external clock generator for it to turn off the CPU 3 3V 5V AUX clock during C3 Sx DPRSLPVR Deeper Sleep GPIO13 DPRSLP can be used to lower the Intel processor voltage 3 3V 5V AUX during C3 SI state 115 8575 N B Maintenance 5 3 515961 MuTIOL Media I O Controller LPC Interface Name Pin Attr Signal Description LAD 3 0 IO LPC Address Data Bus 3 3V 5V M LPC controller drives these four pins to transmit LPC command address and data to LPC device LDRQ I LPC DMA Request 0 3 3V 5V M This pin is used by LPC device to request DMA cycle LDRQI I LPC DMA Request 1 GPIOI1 Lo This pin is used by LPC device to request DMA cycle 3 3V 5V M LFRAME LPC Frame 3 3V M This pin is used to notify LPC device that a start or a abort LPC cycle will occur SIRQ Uo 3 3V 5V M 3 3V 5V M TRC Interface Name Pin Attr Signal Description BATOK I Battery Powe
236. ernal CRT Connector For CRT Display Supports two USB port for all USB devices One MODEM RJ 11 phone jack for PSTN line One RJ 45 for LAN Headphone Out Jack Microphone Input Jack Line in Jack One Card Bus Sockets for one type II card extension 1 3 10 Battery current limit and learning Implanted H W current limit and battery learning circuit to enhance protection of battery 57 8575 N B Maintenance 1 4 Peripheral Components 1 4 1 LCD Panel LCD 14 1 Hyundai HT14X12 100A 1 4 2 Ext Floppy Disk Drive Mitsumi D353GU External USB 3 5 1 44MB 1 2 MB 720KB FDD Option 1 4 3 HDD Hitachi 30GB Height 9 5 mm 2 5 1 4 4 24X CD ROM Drive TEAC 58 8575 N B Maintenance 1 4 5 SW AR CD RW KEM Height 12 7 mm IDE I F 1 4 6 Keyboard Windows 98 Keyboard 1 color multi languages support JP US and Europe Keyboard with Volume UP and Volume Down word 1 4 7 Track Pad Synaptics Accurate positioning Low fatigue pointing action Low profile No moving part high reliability Low power consumption Environmentally sealed Compact size Software configurable Low weight 9 Operating temperature 0 to 60 degree C 59 8575 N B Maintenance 1 4 7 Track Pad Synaptics Operating humidity 5 95 relative humidity non condensing Storage temperature 40 to 65 degree C ESD 15KV applied to fron
237. errupt PCIRST PCI Bus Reset 3 3V M PCIRST will be asserted during the period when PWROK is low and will be kept on asserting until about 24ms after PWROK goes high SERR I System Error 3 3V 5V M When sampled active low a non maskable interrupt NMI can be generated to CPU if enabled STOP 3 3V 5V M Stop STOP indicates that the bus master must start terminating its current PCI bus cycle at the next clock edge and release control of the PCI bus STOP is used for disconnection retry and target abortion sequences on the PCI bus 114 8575 N B Maintenance 5 3 515961 MuTIOL Media I O Controller Power Management Interface IED Interface Name Pin Attr Signal Description IDA 15 0 VO Primary Channel Data Bus 3 3V 5V M IDB 15 0 VO Secondary Channel Data Bus 3 3V 5V M IDECSA 1 0 O Primary Channel CS 1 0 3 3V M IDECSB 1 0 O Secondary Channel CS 1 0 3 3V M HOR A B Primary Secondary Channel IOR Signals 3 3V M TIOW A B Primary Secondary Channel IOW Signals 3 3V M ICHRDY A B I Primary Secondary Channel ICHRDY Signals 3 3V 5V M IDREQ A B I Primary Secondary Channel DMA Request Signals 3 3V 5V IDACK A B O Primary Secondary Channel DMACK Signals 3 3V M IIRQ A B I Primary Secondary Channel Interrupt Signals 3 3V 5V M IDSAA 2 0 Primary Channel Address 2 0 3
238. et responds If no target responds before timeout occurs then the PCI1410 terminates the cycle with an initiator abort Name Description CAD 31 0 CardBus address and data These signals make up the multiplexed CardBus address and data bus on the CardBus interface During the address phase of a CardBus cycle CAD31 CADO contain a 32 bit address During the data phase of a CardBus cycle CAD31 CADO contain data CAD31 is the most significant bit CFRAME T O CardBus cycle frame is driven by the initiator of a CardBus bus cycle is asserted to indicate that a bus transaction 15 beginning data transfers continue while this signal is asserted When is deasserted the CardBus bus transaction is in the final data phase CGNT CardBus bus grant CGNT is driven by the PCI1410 to grant a CardBus PC Card access to the CardBus bus after the current data transaction has been completed CC BEZ2 3 0 IO CardBus bus commands and byte enables CC BE 3 CC BE 0 are multiplexed on the same CardBus terminals During the address phase of a CardBus cycle CC BEZ3 CC BE7O define the bus command During the data phase this 4 bit bus is used as byte enables The byte enables determine which byte paths of the full 32 bit data bus carry meaningful data applies to byte 0 CAD7 CADO applies to byte 1 CADIS CADS CC BE 2 applies to byt
239. ether Panel fitting scaler up scale to 1600 x 1200 VDS low jitter PLL accepts spread spectrum input LVDS 18 bit and 24 bit output 2D dither engine for 18 bit panels Panel protection and power down sequencing Programmable power management Hot Plug detection Support for second CRT DAC bypass mode Four 10 bit video DAC outputs Fully programmable through serial port Complete Windows and DOS driver support Variable voltage interface to graphics device Offered in a 128 pin LQFP package 24 8575 N B Maintenance 1 2 5 PC Card and OHCI Interface Controller TI PCI4410 The PCI4410 is a dual function PCI device compliant with PCI Local Bus Specification 2 2 Function 0 provides the independent PC Card socket controller compliant with the 997 PC Card Standard The PCI4410 provides features that make it the best choice for bridging between the PCI bus and PC Cards and supports either 16 bit or CardBus PC Cards in the socket powered at 5 V or 3 3 V as required card signals are internally buffered to allow hot insertion and removal without external buffering The PCI4410 is register compatible with the Intel 82365SLF 82365SL ExCA controllers The PCI4410 internal data path logic allows the host to access 8 16 and 32 bit cards using full 32 bit PCI cycles for maximum performance Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting The PCI4410 can be programme
240. g Z4XAVSS OV GROUND Analog 111 8575 N B Maintenance 5 2 SiS650 IGUI Host Memory Controller Test Mode Hardware Trap Power Management Name Pin Attr Signal Description DLLEN Uo Hardware Trap pin refer to section 5 3 3V 5V M DRAM SEL I Hardware Trap pin refer to section 5 3 3V 5V AUX TRAP 1 0 I Hardware Trap pins refer to section 5 3 3V 5V M ENTEST I Test Mode enable pin 3 3V 5V M TESTMOD I Test Mode select pin E 2 0 3 3V 5V M Nand Tree Test 100 AUXOK I Auxiliary Power OK 3 3V AUXI This signal is supplied from the power source of resume well It is also used to reset the logic in resume power well If there is no auxiliary power source on the system this pin should be tied together with PWROK PCIRST I PCI Bus Reset 3 3V AUXI PCIRST is supplied from SiS MuTIOL Media IO SiS961 PWROK I Main Power OK 3 3V AUXI A high level input to this signal indicates the power being supplied to the system is in stable operating state During the period of PWROK being low CPURST and PCIRST will all be asserted until after PVROK goes high for 24 ms 112 8575 N B Maintenance 5 3 515961 MuTIOL Media I O Controller Host Bus Interface MuTIOL Connect Interface Name Pin Attr Signal Description ZCLK I Megaband I O Connect Clock 3 3V M ZUREQ Uo Megaband I O Conect Controll pins 18 ZDREQ Megaband I
241. gh stops operation of the PLL The TSBA1ABI supports an optional isolation barrier between itself and its LLC When the ISO input terminal is tied high the LLC interface outputs behave normally When the ISO terminal is tied low internal differentiating logic is enabled and the outputs are driven such that they can be coupled through a capacitive or transformer galvanic isolation barrier as described in Annex J of IEEE Std 1394 1995 and in IEEE 1394a 2000 section 5 9 4 hereinafter referred to as Annex J type isolation To operate with TI bus holder isolation the ISO terminal on the PHY must be high 31 8575 N B Maintenance Data bits to be transmitted through the cable port are received from the LLC on two four or eight parallel paths depending the requested transmission speed and are latched internally in the TSB41AB1 in synchronization with the 49 152 MHz system clock These bits are combined serially encoded and transmitted at 98 304 196 608 or 393 216Mbits s referred to as S100 S200 and S400 speeds respectively as the outbound data strobe information stream During transmission the encoded data information is transmitted differentially on the TPB cable pair and the encoded strobe information is transmitted differentially on the cable pair During packet reception the TPA and TPB transmitters of the receiving cable port are disabled and the receivers for that port are enabled The encoded data information is re
242. gital input signal from a PC Card to the system speaker The PCI1410 supports the binary audio mode and outputs a binary signal from the card to SPKROUT CBLOCK T O CardBus lock CBLOCK is used to gain exclusive access to a target CCLKRUN IO CardBus clock run CCLKRUN is used by a CardBus Card to request an increase in the CCLK frequency and by the PCI1410 to indicate that the CCLK frequency is going to be decreased CCD1 CCD2 CardBus detect 1 and CardBus detect 2 CCD1 and CCD2 are used in conjunction with CVS1 and CVS2 to identify card insertion and interrogate cards to determine the operating voltage and card type CRST CardBus reset CRST brings CardBus PC Card specific registers sequencers and signals to a known state When CRST is asserted all CardBus PC Card signals are placed in a high impedance state and the PCI1410 drives these signals to a valid logic level Assertion can be asynchronous to CCLK but deassertion must be synchronous to CCLK CE1 CE2 Card enable 1 and card enable 2 CE1 and CE2 enable even and odd numbered address bytes CE1 enables even numbered address bytes and CE2 enables odd numbered address bytes CardBus PC Card Address and Data Slots A and B CDEVSEL T O CardBus device select The PCI1410 asserts CDEVSEL to claim a CardBus cycle as the target device As a CardBus initiator on the bus the PCI1410 monitors CDEVSEL until a targ
243. gs 015 7 i R715 47K 06030 3 E MMBT3904L 1 LPC AD1 0522 0603 i SZ Ae S3AUXSW 144 GND GND GND r i AMINA 4 a 0603 PLACE CLOSE TO 961 GND GND GND GND 5 JL545 k 29 1394 PME 22 12 1 GND JP_NET10 R619 J508 R717 JL546 4 7K bi R627 10K 06030 1 R693 1 0603 10K 0603 18 lt gt 2 2 0603 JP NET10 1 R620 1 0 PME pir 102427 06030 DFS H8 SUSC 4 1547 3 lt 1 2 DF13 2P 1 25H 3 9524 PSON 28 MPCLPMER VW 9513 SUSC 144 1 JP bd a 8575 515961 2 3 Be Document C Number 411671700010 jaie Wednesday January 16 2002 15 of 2 i R147 CLOSE TO 961 TEN S S 9 6 3 3 22 06030 R148 27 USBPO USBPO N 1 2 10 i 2 wu
244. h Audio Codec 3 3V 5V AUX AC SDOUT AC 97 Serial Data Output 3 3V M Serial data output to Codecs AC SYNC AC 97 Synchronization 3 3V M This is a 48KHz signal which is used to synchronize the Codecs USB Interface Name Pin Attr Signal Description USBCLK48M USB 48 MHz clock input 3 3V 5V M This signal provides the fundamental clock for the USB Controller OC 0 5 Lo USB Port 0 5 Overcurrent Detection 3 3V 5V AUX OC 0 5 are used to detect the overcurrent condition of USB Ports 0 5 UV 2 0 vO USB Port 2 0 Differential UV 2 0 3 3V AUX These differential pairs are used to transmit Data Address Command signals for ports 0 2 USB controller 1 UV 5 3 Lo USB Port 5 3 Differential UV 5 3 3 3V AUX These differential pairs are used to transmit Data Address Command signals for ports 3 5 USB controller 2 116 8575 N B Maintenance 5 3 515961 MuTIOL Media I O Controller Keyboard Control Interface Name Pin Attr Signal Description VOD Keyboard Dada 15 O OD When the internal keyboard controller is enabled this pin is 3 3 5 AUX used as the keyboard data signal KBCLK VOD Keyboard Clock GPIO16 O OD When the internal keyboard controller is enabled this pin is 3 3V 5V AUX used as the keyboard clock signal PMDAT VOD PS2 Mouse Data GPIO17 O OD When the internal keyboard and PS2 mouse controllers are 3 3V 5V AUX enabled
245. he physical unit upon detection of a non idle medium RXCLK I Receive Clock 3 3V 5V AUX continuous clock that is recovered from the incoming data During 100Mb s operation RXCLK is 25MHz and during 10Mb s this is 2 5MHz TXCLK I Transmit Clock 3 3V 5V AUX continuous clock that is sourced by the physical unit During 100Mb s operation RXCLK is 25MHz and during 10Mb s this is 2 5MHz Name Pin Attr Signal Description RXER I RX Packet Error 3 3 5 AUX This event is signaled after the last received descriptor in a failed packet reception that has been updated with valid status MIICLK25M PHY 25MHz Clock Input 3 3V 5V AUX This pin provides the 25MHz clock signal input to the built in oscillator MDC Management Data Clock 3 3V AUX Clock signal with a maximum rate of 2 5MHz used to transfer management data for the external physical unit on the MIIMDIO pin TXDJ 0 3 I Receive Data 3 3 5 AUX This is a group of 4 data signals aligned on nibble boundaries which are driven synchronous to the RXCLK by the external physical unit TXEN Transmit Data 3 3V AUX This is a group of 4 data signals which are driven synchronous to the TXCLK for transmission to the external physical unit RXD 0 3 I Receive Data 3 3 5 AUX This is a group of 4 data signals aligned on nibble boundaries which are driven synchronous to the RXCLK by the external physical unit 117 5 3 515961 MuTIOL Media
246. he write protect switch on 16 bit memory PC Cards For 16 bit I O cards WP is used for the 16 bit port IOIS167 function T O is 16 bits IOIS167 applies to 16 bit I O PC Cards IOIS16 is asserted by the 16 bit PC Card when the address on the bus corresponds to an address to which the 16 bit PC Card responds and the I O port that is addressed is capable of 16 bit accesses DMA request WP can be used as the DMA request signal during DMA operations to a 16 bit PC Card that supports DMA If used then the PC Card asserts WP to indicate a request for a DMA operation VS1 VS2 T O Voltage sense 1 and voltage sense 2 VS1 and VS2 when used in conjunction with each other determine the operating voltage of the PC Card 124 8575 N B Maintenance 5 5 PCII410GGU PCMCIA Controller CardBus PC Card Interface System Slots A and B Name Vo Description CardBua PC Card Interface Control Slots A and B CCLK CardBus clock CCLK provides synchronous timing for all transactions on the CardBus interface All signals except CRST CCLKRUN CINT CSTSCHG CAUDIO CCD2 CCD1 CVS2 and 51 are sampled on the rising edge of CCLK and all timing parameters are defined with the rising edge of this signal CCLK operates at the PCI bus clock frequency but it can be stopped in the low state or slowed down for power savings Name Description CAUDIO I CardBus audio CAUDIO is a di
247. ialize monochrome adapter Test 8237A page registers Code POST Routine Description 10h 11h 12h 13h 14h 15h 16h 17h 19h 1Bh 1Ch Dh 1 Test keyboard Test keyboard controller 28h Protected mode entered safely Signon messages displayed Code POST Routine Description 20h 21h 22h 23h 24h 25h 26h 27h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 131 8575 N B Maintenance 7 2 Error Codes Following is a list of error codes in sequent display on the PIO debug board Jump into bootstrap code Update NUMLOCK status Special init of COMM and LPT ports 132 8575 N B Maintenance 7 3 Maintenance Diagnostics 7 3 1 Diagnostic Tools LED 8 CONNECTOR 1 A 4 P N 411904800001 Description PVA PWA 378Port Debug BD Note Order it from MIC TSSC 7 3 2 Circuit PIO 3 Connector PINI STROBE lt PIN 13 SLCT PIN10 ACKZ lt gt PIN 16 INTZ BUSY lt gt PIN 17 SELINE LED MMS _ PINI2 lt gt PIN 14 AUTOFD PIN 9 2 PD 7 0j 133 8575 N B Maintenance 8 Trouble Shooting D D D D D D D 8 1 No Power 8 2 No Display 8 3 Controller Failure LCD No Display 8 4 External Monitor No Display 8 5 Memory Test Error 8 6 Keyboard K B Touch Pad T P Test Error 8 7 Hard Driver Test Error 8 8 CD ROM Driver Test Error 8 9 PIO Port Test Error 8 10 USB Port Te
248. l buffer Input threshold can be programmed by serial port to equal to VREF2 2 or to DVDD 2 The amplitude will be 0 to VDDV is the threshold level for these inputs 119 Out HOUT H Sync Output This pin is the output of a voltage translating digital buffer and is driven from V5V 109 In HIN H Sync Input This pin is the input of a voltage translating digital buffer Input threshold can be programmed by serial port to equal to VREF2 2 or to DVDD 2 49 Out C HSYNC Composite Horizontal Sync Provides composite sync in TV modes and horizontal sync in bypass RGB mode This pin is driven by the DVDD supply 50 Out BCO VSYNC Buffered Clock Outputs Vertical Sync This output pin provides buffered crystal oscillator clock output or VSYNC output in bypass RGB mode This pin is driven by the DVDD supply 93 9 In XCLK XCLK2 External Clock Inputs These inputs form a differential clock signal input to the device for use with the H2 V2 and D2 11 0 data If differential clocks are not available the XCLK2 input should be connected to VREFI The clock polarity can be selected by the MCP2 control bit 120 5 4 SiS301LV Chrontel CH7019 TV LVDS Encoder 8575 N B Maintenance Pin 4 Type Symbol Description 118 Power V5V 5V supply for H VOUT 5V 64 83 84 103 Power DVDD Digital Supply Voltage 3 3V 67 75 92 100 Power DGND Digital Ground 60 Power VDDV Supply Volt
249. lated power for the internal processor core PLLs Refer to the Intel Pentium 4 Processor in the 478 pin Package and Intel 850 Chipset Platform Design Guide for complete implementation details 107 8575 N B Maintenance 5 2 515650 IGUI Host Memory Controller Host BUS Interface Continue Host BUS Interface Name Pin Attr Signal Description CPUCLK I Host differential clock input CPUCLK 071 CPURST Host Bus Reset 1 2 1 85 M is used to keep all the bus agents in the same initial state before valid cycles issued CPUPWRGD o CPUPWRGD is used to inform CPU that main power is stable ADS Address Strobe 1 2 1 85 M Address Strobe is driven by CPU or 515650 to indicate the start of a CPU bus cycle HADSTB 1 0 Source synchronous address strobe used to latch 1 2 1 85 HREQ 4 0 amp HA 31 3 at both falling and rising edge HREQ 4 0 amp HA 16 3 are latched by HASTBO HA 31 17 are latched by 1 HREQ 4 0 Request Command 1 2 1 85 M HREQ 4 0 are used to define each transaction type during the clock when ADS is asserted and the clock after ADS is asserted HA 31 3 Host Address Bus 1 2 1 85 M BREQO Symmetric Agent Bus Request 1 2 1 85 BREQO is driven by the symmetric agent to request for the bus BPRI Priority Agent Bus Request 1
250. m 145 8575 N B Maintenance 8 3 VGA Controller Failure LCD No Display There is no display or picture abnormal on LCD although power on self test is passed J3 Pio 10 101594409 GOT 0503 3VS NDS9410 F503 L504 5 3 mircoSMDC110 1202 100 f LCDVCC zwar 1 CY Y p lt 6 C506 12VS G 510 L c509 C2 43VS l R505 T 1000P 1000P ibi 470K IK 4 e 77 77 77 32 34 36 Q2 C506 24 TXCLK 8 RI 0 1 oe J i 710504 25 TXCLK 10 5 TX2CLK 7 ENAVDD 127 s 6 TX2CLK 9 SiS301LV 33 3027 TXOUT 0 2 202625 Chrontel m LcD m2 ENT 128 m TROUT AF 29827 Py HYUNDAI 0 1 0 17 14 11 TX20UT 0 2 13 14 19 HANNSTAR 0 1 1 CH7019 UA CMO 1 0 0 18 15 12 TX20UT 0 2 15 1621 IGUI PIDO R828 0 e LCD 10 31 82 LCD 11 Host Memory bi REM 0 e 83 LCD ID2 Controller pm REX 0 e 35 RP40 SiS650 R74 10K 4 100 al e o DC Power Board 1514 23 9 ys 45V NN e 3 4 J7 PJ2 P2 P2 R642 Y 1512 7 P 10K 5VS O P22 U509 45 BLADJ 8 BLADJ 1513 4 5 17 H8 ENABKL ENABKL ENPBLTI 1515
251. mm height 10 15 20 30GB Support Ultra DMA 66 100 Reseller Exchangeable Ext FDD Support External FDD w z USB I F 3 5 Format for 720KB 1 2MB 1 44MB Display 14 1 15 XGA TFT display Resolution 1024 x 768 14 17 15 SXGA TFT display Resolution 1280 x 1024 P ROM Drive 12 7mm Height 24X CD ROM Drive 8X DVD ROM Drive 8X4x24 CD RW or above 8X8X4X24 Combo or above 70 8575 N B Maintenance Continue to previous Video Controller Integrated in SiS650 Support Multi Monitor Ultra AGP REAL 256 2D 3D Graphic Keyboard 19mm pitch 3 0mm stroke Windows Logo Key x 1 Application Key x 1 5x Easy Start Buttons functions defined by user Glide pad with 2x buttons and 1x scroll button PCMCIA Type II or Type I x1 CardBus Support Audio System Sound Blaster Pro compatible Built in mono microphone Support AC97 2 1 2X Speakers 1Watt each I O Port Bi directional Parallel Port EPP ECP x 1 Standard USB1 1 port x 2 RJ 11 port x 1 RJ 45 port x 1 IR port x1 complies with IrDA 1 1 DC input x 1 VGA monitor port x1 Audio out x 1 SPIDF x 1 71 8575 N B Maintenance Continue to previous Port Hardware Volume Control 1394 Port x 1 S Video Out Port x 1 NTSC PAL Communication Built in 56Kbps V 90 MDC modem Built in 10 100 based T LAN Power Supply 9 cell Li ion 2000mAH 3 7V User swappable Battery Life 1 5 hrs Support Power off charge 3hr 80 in 1 6Hrs Support Power on charge 4hr 5
252. n REFCLK0 CRT IN Pu 014 515961 ONE e From U508 Clock Gen E R558 FA501 1000P T 22K 120 100 7 R566 100 CRT DDDA S D D e 12 M G Q505 P7 R546 gt 33 CRT HSYNC slelo ANRA SZ P 13 G Q502 tri R547 2N7002 33 CRT VSYNC 5 4 2 74 R548 LG 5 257002 100 CRT_DDCK 8 D 5 iF 0506 04 27002 gt 5 S CRT RED L503 1202 100 1 VY 8 CRT GREEN L502 1202 100 2 8 IGUI YY e 5 5 2 Host Memory CRT BLUE L501 1702 100 3 Controller halal e nd ical al iex 6 7 8 10 C600 VVBWN 0 1 RP502 CP501 CP502 SiS650 C593 41 8VS 75 4 22 4 22 4 JLI VCOMP H 1514 e e e e c wal Tsoi 1207 100 e 9 6 eo DACAVDD1 2 eo e 77 C583 C584 L C56l 01 Ip T DACAYSS1 2 JL509 e e R545 V 130 VRSET 148 8575 N B Maintenance 8 5 Memory Test Error Extend SDRAM is failure or system hangs up Memory Test Error 1 If your system installed with expansion SO DIMM module then check them for proper installation One of the following components or signals on the motherboard may be defective Use an oscilloscope to check the signals or replace the parts one at A time and test after each replacement 2 Make sure that your SO DIMM sockets are OK Board level Troubleshooting 3 Then try another kn
253. n Out DD1 DD2 DDC Serial Data Serial data for DDC to 5V 111 VREF2 Reference Voltage 2 Used to generate the threshold level for SDD SDC SPD and SPC port This pin should be tied externally to the maximum voltage seen by the ports 1 5V to 3 3V 115 117 In Out DCLDC2 DDC Serial Clock Clock for DDC 0V to 5V 63 104 In DE1 DE2 Data Enable These pins accept a data enable signal which is high when active video data is input to the device and remains low during all other times The levels are 0 to VDDV VREFI is the threshold level One of these inputs is used by the LVDS links The TV Out function uses H and V sync signals and values in the SAV register as reference to active video 123 126 56 57 In Out GPIO 5 0 General Purpose Input Output 5 0 These pins provide general purpose I O and are controlled via the serial port 3 3V 127 Out ENAVDD Panel Power Enable Enable panel VDD 3 3V 128 Out ENABLK Back Light Enable Enable Back Light of LCD Panel 3 3V 62 105 Out FLD STL1 FLD STL2 TV Field Flat Panel Stall Signal These outputs can be programmed to be either a TV Field output from the TV encoder or a Stall output from the flat panel Up scaler These outputs are tri stated upon power up 107 In Out SPD Serial Port Data Input Output This pin functions as the bi directional data pin of the serial port an
254. nal and output control Feedback pins for input to output synchronization Spread Spectrum tolerant inputs 3 3V tolerant CLK INT input Switching Characteristics PEAK PEAK jitter 66MHz 120ps PEAK PEAK jitter gt 100 2 lt 75ps CYCLE CYCLE jitter 66MHz 120ps CYCLE CYCLE jitter gt 100 2 65ps OUTPUT OUTPUT skew 100ps Output Rise and Fall Time 650ps 950ps DUTY CYCLE 49 5 50 5 8575 N B Maintenance 1 2 3 Core Logic SiS650 SiS961 1 2 3 1 SiS650 IGUI Host Memory Controller 515650 IGUI Host Memory Controller integrates a high performance host interface for Intel Pentium 4 processor a high performance 2D 3D Graphic Engine a high performance memory controller an AGP 4X interface and SiS MuTIOL Technology connecting w SiS961 MuTIOL Media IO 515650 Host Interface features the AGTL amp AGTL compliant bus driver technology with integrated on die termination to support Intel Pentium 4 processors 513650 provides 12 level In Order Queue to support maximum outstanding transactions up to 12 It integrated a high performance 2D 3D Graphic Engine Video Accelerator and Advanced Hardware Acceleration MPEGI MPEGII Video Decoder for the Intel Pentium 4 series based PC systems It also integrates a high performance 2 1 GB s DDR266 Memory controller to sustain the bandwidth demand from the integrated GUI or external AGP master host processor as well as the multi masters In a
255. nction in power management 1 3 4 Reset Switch There is a reset switch at bottom side of notebook It will reset embedded controller H8 and turn off system totally When system hands up and Power button has no function this switch is the only way to turn off system without remove power source 54 8575 N B Maintenance 1 3 5 LED Indicators System has eight status LED indicators to display system activity which include three at front side and five above keyboard 1 Three LED indicators at front side From left to right that indicates AC Power Battery Power and Battery Status AC Power This LED lights green when AC is powering the notebook and flash on 1 second off 1 second when Suspend to DRAM is active using AC power The LED is off when the notebook is off or powered by batteries Battery Power This LED lights green when the notebook is being powered by Battery and flash on 1 second off 1 second when Suspend to DRAM is active using Battery power The LED is off when the notebook is off or powered by batteries or when Suspend to Disk Battery Status During normal operation this LED stays off as long as the battery is charged When the battery charge drops to 10 of capacity the LED lights red flashes per 1 second and beeps per 2 second When AC is connected this indicator glows green if the battery pack 15 fully charged or orange amber if the battery is being charged 2 Five LED indicators
256. nd gently pry the frame out Repeat the process until the frame is completely separated from the housing 4 Remove the two screws on two sides and two screws on the lower part of the LCD panel and disconnect the cable from the inverter board figure 2 18 m c 0 N Figure 2 17 Remove LCD frame Figure 2 18 Remove LCD panel 86 8575 N B Maintenance Reassembly 1 Fit the LCD panel back into place and secure with four screws and reconnect the cable to the inverter board 2 Fit the LCD frame back into the housing and replace the four screws and four rubber pads 3 Replace the LCD assembly See section 2 2 7 Reassembly 87 8575 N B Maintenance 2 2 9 Inverter Board Disassembly 1 Remove the LCD assembly and detach the LCD panel see instructions in previous two sections 2 To remove the inverter board on the bottom side of the LCD assembly disconnect the cable and remove one screw figure 2 19 Figure 2 19 Remove the inverter board Reassembly 1 Fit the inverter board back into place and secure with one screw 2 Reconnect the cable 3 Replace the LCD frame See section 2 2 8 Reassembly 4 Replace the LCD assembly See section 2 2 7 Reassembly 88 8575 N B Maintenance 2 2 10 System Board Disassembly 1 Remove the battery pack keyboard CPU HDD module CD DVD ROM drive and LCD assembly See section 2 2 1 to 2 2 5 and 2 2 7 Disassembly 2 Remove
257. nput Output BPM 5 0 Breakpoint Monitor are breakpoint and performance monitor signals They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance BPM 5 0 should connect the appropriate pins of all Pentium 4 processor in the 478 pin package system bus agents BPM4 provides PRDY Probe Ready functionality for the TAP port PRDY is a processor output used by debug tools to determine processor debug readiness 5 provides PREQ Probe Request functionality for the port PREQ is used by debug tools to request debug operation of the processor Please refer to the Intel Pentium 4 Processor in the 478 pin Package and Intel amp 850 Chipset Platform Design Guide for more detailed information These signals do not have on die termination Refer to the Intel Pentium 4 Processor in the 478 pin Package and Intel 850 Chipset Platform Design Guide for termination requirements BPRI Input BPRI Bus Priority Request is used to arbitrate for ownership of the processor system bus It must connect the appropriate pins of all processor system bus agents Observing BPRI active as asserted by the priority agent causes all other agents to stop issuing new requests unless such requests are part of an ongoing locked operation The priority agent keeps BPRI asserted until all of its requests are completed then releases the bus by dea
258. nterrupt request IREQ is asserted by a 16 bit I O PC Card to indicate to the host that a device on the 16 bit I O PC Card requires service by the host software IREQ is high deasserted when no interrupt is requested REG Attribute memory select REG remains high for all common memory accesses When is asserted access is limited to attribute memory OE or WE active and to the I O space IORD IOWR active Attribute memory is a separately accessed section of card memory and is generally used to record card capacity and other configuration and attribute information DMA acknowledge REG is used as a DMA acknowledge DACK during operations to a 16 bit PC Card that supports DMA The PCI1410 asserts REG to indicate a DMA operation REG is used in conjunction with the DMA read IOWR DMA write strobes to transfer data CD1 CD2 Card detect 1 and Card detect 2 CD1 and CD2 are internally connected to ground on the PC Card When a PC Card is inserted into a socket 1 and CD2 are pulled low RESET PC Card reset RESET forces a hard reset to a 16 bit PC Card WAIT Bus cycle wait WAIT is driven by a 16 bit PC Card to extend the completion of the memory or I O cycle in progress CE1 CE2 Card enable 1 and card enable 2 and CE2 enable even and odd numbered address bytes CE1 enables even numbered address bytes and CE2 enables odd numbered address
259. ocked operation and ensure the atomicity of lock PWRGOOD Input PWRGOOD Power Good is a processor input The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state PWRGOOD can be driven inactive at any time but clocks and power must again be stable before a subsequent rising edge of PWRGOOD The PWRGOOD signal must be supplied to the processor it is used to protect internal circuits against voltage sequencing issues It should be driven high throughout boundary scan operation MCERR Input Output MCERR Machine Check Error is asserted to indicate an unrecoverable error without a bus protocol violation It may be driven by all processor system bus agents assertion conditions are configurable at a system level Assertion options are defined by the following options Enabled or disabled Asserted if configured for internal errors along with IERR Asserted if configured by the request initiator of a bus transaction after it observes an error Asserted by any bus agent when it observes an error in a bus transaction For more details regarding machine check architecture pl
260. on users Highlights of the Pentium 4 Processor Available at speeds ranging from 1 50 to 2 GHz Featuring the new Intel NetBurst micro architecture Supported by the SiS650 chipset Fully compatible with existing Intel Architecture based software Internet Streaming SIMD Extensions 2 Intel MMX media enhancement technology Memory cache ability up to 4 GB of addressable memory space and system memory scalability up to 64GB of physical memory Support for uni processor designs Based upon Intel s 0 18 micron manufacturing process 8575 N B Maintenance Intel Pentium 4 Processor Product Feature Highlights The Intel NetBurst micro architecture delivers a number of new and innovative features including Hyper Pipelined Technology 400 MHz System Bus Execution Trace Cache and Rapid Execution Engine as well as a number of enhanced features Advanced Transfer Cache Advanced Dynamic Execution Enhanced Floating point and Multi media Unit and Streaming SIMD Extensions 2 Many of these new innovations and advances were made possible with improvements in processor technology process technology and circuit design that could not previously be implemented in high volume manufacturable solutions The features and resulting benefits of the new micro architecture are defined below Hyper Pipelined Technology The hyper pipelined technology of the NetBurst micro architecture doubles the pipeline depth compar
261. own good SO DIMM Parts Signals modules R90 2 5V_DDR R91 DDRVREF Yes CKE 0 3 SDRAM module R93 DDR MDJ 0 63 RPI3 RP15 DDR BA 0 1 RP16 RP20 DDR_CS 0 3 R632 DDR 12 R614 DDR_DQS 0 7 If your system host bus clock running at R658 DDR RAS 266MHZ then make sure that SO DIMM R662 DDR_CAS module meet require of PC 266 Motherboard R98 DDR_WE R100 SDRAMCLK R102 FWDSDCLK R97 SMBDATA R101 R103 SMBCLK CLK_DDR 0 5 CLK DDR 0 5 4 Replace the faulty SDRAM module 149 8575 N B Maintenance 8 5 Memory Test Error Extend SDRAM is failure or system hangs up gt U4 IGUI Host Memory Controller SiS650 3VS 1516 1 25 o 1207 100 DDRAVDD e e C623 L C624 C632 J505 Olp T 2 5V DDR A SMBDATA DDRAVSS JL507 m SMBCLK Pio V 470 gt _ 0 3 CREO 42 5V DDR DDR 0 7 DQM 0 7 e gt DDRREF DDR_MD 0 63 MD 0 63 o e gt DDR BA 0 1 DDR CS 0 3 BA 0 1 CS 0 3 CS z e gt DDR MA 0 12 DDR DQS 0 7 MA 0 12 DQS 0 7 o e DDR DDR CASS DDR_WE RAS CASH WE E R90 R9 R94 RPS RPI2 10 8 3VS R91 R88 R93 2 20 DDR 058 o 0 CLK DDR
262. p mode is attained when the port is either disconnected or disabled with the port interrupt enable bit cleared The TSB41AB1 exits the low power mode when the LPS input is asserted high or when port event occurs which requires that the TSB41AB1 become active in order to respond to the event or to notify the LLC of the event for example incoming bias is detected on a suspended port a disconnection is detected on a suspended port a new connection is detected on a nondisabled port etc The SYSCLK output becomes active and the PHY LLC interface is initialized and becomes operative within 7 3 ms after LPS is asserted high when the 5 41 1 is in the low power mode 36 8575 N B Maintenance The PHY uses the C LKON terminal to notify the LLC to power up and become active When activated the C LKON signal is a square wave of approximately 163 ns period The PHY activates the C LKON output when the LLC is inactive and a wake up event occurs The LLC is considered inactive when either the LPS input is inactive as described above or the LCtrl bit is cleared to 0 A wake up event occurs when a link on PHY packet addressed to this node is received or when a PHY interrupt occurs The PHY deasserts the C LKON output when the LLC becomes active both LPS active and the LCtrl bit set to 1 The PHY also deasserts the C LKON output when a bus reset occurs unless a PHY interrupt condition exists which would otherwise cause C LKON to be active 37
263. perly Troubleshooti p id iu c One of the following parts or signals on the motherboard may be defective use an oscilloscope to check the signals or replace the parts one at a time and test after each replacement Correct it Parts Signals Try another known good Replace the Replace PIO device faulty parts Motherboard No Re Test OK No 160 8 10 PIO Port Test Error When a print command is issued printer prints nothing or garbage Mother Board 0511 LPC Super I O 87393 VDDJ 0 3 P 0 3 P LPD 4 7 SLCT P STB AFD P ERR INIT P SLIN P BUSY RP501 0 4 J7 DP LPD 0 3 DP LPD 4 7 DP SLCT DP STB DP AFD DP ERR DP INIT DP SLIN DP ACK DP BUSY mo 43VS CP503 22P 4 CP504 22P 4 CP505 22P 4 CP506 22P 4 L C504 22P 77 8575 N B Maintenance 35 33 31 36 34 32 5VS P 0501 0501 PACI28401Q DUN PJ2 P 0 4 P 8 PP STB DP STB 1 A P_AFD 7 2 PP_AFD AFD 14 M P_LPDO 5 P_LPDO LPDO 2 Av P ERR 4 PP ERR A ERR 15 5 P LPDI RP2 8 1 PP LPDI LPDi 3 3 os aud P_INIT 7 2 INIT INIT i 2 na P LPD2 3 PP LPD2 A LPD2 4 My P_SLIN
264. processor chipset and clock synthesizer All agents must operate at the same frequency The Pentium 4 processor in the 478 pin package operates currently at a 400 MHz system bus frequency 100 MHz BCLK 1 0 frequency 0 Analog 1 0 must be terminated on the system board using precision resistors Refer to the Intel Pentium 4 Processor in the 478 pin Package and Intel amp 850 Chipset Platform Design Guide for details on implementation DBI 3 0 Input Output DBI 3 0 are source synchronous and indicate the polarity of the D 63 0 signals The DBI 3 0 signals are activated when the data on the data bus is inverted The bus agent will invert the data bus signals if more than half the bits within the covered group would change level in the next cycle DBI 3 0 Assignment To Data Bus Bus Signal Data Bus Signals DBI3 D 63 48 2 D 47 32 DBI1 D 31 16 DBIO D 15 0 DBR Output DBR is used only in processor systems where no debug port is implemented on the system board DBR is used by a debug port interposer so that an in target probe can drive system reset If a debug port is implemented in the system DBR is a no connect in the system DBR is not a processor signal 103 8575 N B Maintenance 5 1 Intel Pentium 4 Processor mPGA478 Socket Name Type Description Name Type Description DBSY Input Output
265. pulses indicating that an address parity error has occurred on a CardBus interface Name vo Description VCCD0 Logic controls to the TPS2211 PC Card power interface switch to control VCCD1 AVCC VPPDO O Logic controls to the TPS2211 PC Card power interface switch to control VPPD1 AVPP PCI System Name Description GRST I Global reset When the global reset is asserted the GRST signal causes the PCI1410 to place all output buffers in a high impedance state and reset all internal registers When GRST is asserted the device is completely in its default state For systems that require wake up from D3 GRST will normally be asserted only during initial boot PRST should be used following initial boot so that PME context is retained when transitioning from D3 to DO For systems that do not require wake up from D3 GRST should be tied to PRST When the SUSPEND mode is enabled the device is protected from the GRST and the internal registers are preserved All outputs are placed in a high impedance state but the contents of the registers are preserved PCLK I PCI bus clock PCLK provides timing for all transactions on the PCI bus All PCI signals are sampled at the rising edge of PCLK PRST I PCI reset When the PCI bus reset is asserted PRST causes the PCI1410 to place all output buffers in a high impedance state and reset internal registers When PRST is asserted the device is completely nonfunction
266. r 8 Auto precharge option KBC and PS2 mouse can be individually disabled Auto Refresh and Self Refresh Modes 15 6us MT4VDDT864H MT8VDDT1664HD 7 8125us MT4VDDT1664H MT8VDDT3264HD MT8VDDT6464HD maximum average periodic refresh interval Serial Presence Detect SPD with EEPROM Serial Presence Detect SPD with EEPROM Fast data transfer rates PC2100 or PC1600 Selectable READ CAS latency for maximum compatibility Gold plated edge contacts 1 2 12 PHY 3 3 V 10Base T 100Base TX Integrated The ICS1893 is a low power physical layer device PHY General Description The ICS1893 is a low power physical layer device PHY that supports the ISO IEC 10Base T and 100Base TXCarrier Sense Multiple Access Collision Detection CSMA CD Ethernet standards The ICS1893 architecture is based on the ICS1892 The ICS1893 supports managed or unmanaged node repeater and switch applications 50 8575 N B Maintenance The ICS1893 incorporates digital signal processing DSP in its Physical Medium Dependent PMD sublayer As a result it can transmit and receive data on unshielded twisted pair UTP category 5 cables with attenuation in excess of 24 dB at 100 MHz With this ICS patented technology the ICS1893 can virtually eliminate errors from killer packets The ICS1893 provides a Serial Management Interface for exchanging command and status information with a Station Management STA entity
267. r OK 3 3V RTC When the internal RTC is enabled this signal is used to indicate that the power of RTC well is stable It is also used to reset the logic in RTC well If the internal RTC is disabled this pin should be tied low OSC32KHI I RTC 32 768 KHz Input 3 3V RTC When internal RTC is enabled this pin provides the 32 768 KHz clock signal from external crystal or oscillator OSC32KHO RTC 32 768 KHz Output lt 3 3V RTC When internal RTC is enabled this pin should be connected with the other end of the 32 768 KHz crystal or left unconnected if an external oscillator is used PWROK I Main Power OK 3 3V RTC A high level input to this signal indicates the power being supplied to the system is in stable operating state During the period of PWROK being low PCIRST will all be asserted until after PVROK goes high for 12 ms AC 97 Interface Name Pin Attr Signal Description AC BIT CLK AC 97 Bit Clock 3 3V 5V M This signal 15 12 288MHz serial data clock which is generated by primary Codec AC_RESET 9 AC 97 Reset 3 3V AUX Hardware reset signal for external Codecs AC_SDINO I AC 97 Serial Data Input 3 3V 5V AUX Serial data input from primary Codec AC SDINI I AC 97 Serial Data Input 3 3V 5V AUX Serial data input from secondary Codec When Modem Codec is used this pin dedicate to Modem Serial data input AC SDIN 3 2 AC 97 Serial Data Input GPIO 10 9 vo Serial data input from third and fort
268. rporates ICS s Watchdog Timer technology and a reset feature to provide a safe setting under unstable system conditions M N control can configure output frequency with resolution up to 0 1 MHz increment Recommended Application 515645 650 style chipsets Output features 2 Pairs of differential CPUCLKs 3 3V 1 SDRAM 3 3V 8 PCI 3 3V 2 3 3V 2 ZCLKs 3 3V 1 48MHz 3 3V fixed 1 24 48MHz 3 3V selectable by 3 REF 3 3V 14 318MHz 8575 N B Maintenance Features Benefits Programmable spread percentage for EMI control Watchdog timer technology to reset system if system malfunctions Programmable watch dog safe frequency Support I C Index read write and block read write operations For PC133 SDRAM system use the ICS9179 06 as the memory buffer For DDR SDRAM system use the ICS93705 as the memory buffer Uses external 14 318MHz crystal Key Specifications PCI PCI output skew lt 500ps CPU SDRAM output skew lt Ins AGP AGP output skew 150ps Programmable output frequency divider ratios output rise fall time output skew 8575 N B Maintenance 1 2 2 2 DDR buffer frequency synthesizer ICS93722 Low Cost DDR Phase Lock Loop Zero Delay Buffer Recommended Application 515645 650 style chipsets Product description features Low skew low jitter PLL clock driver for functio
269. rst Edition Jun 2002 E mail Willy Chen mic com tw Web http www mitac com http www mitacservice com
270. s MAC Repeater Interface can be configured as 10M or 100M Media Independent Interface 100M Symbol Interface bypasses the PCS 10M 7 wire Serial Interface Small Footprint 64 pin Thin Quad Flat Pack TQFP 52 8575 N B Maintenance 1 3 Other Functions 1 3 1 Hot Key Functions Combination Fn Fl Reserve Fn F2 Reserve Fn F3 Volume Downa _____ Rotate display mode in LCD only CRT only and simultaneously display switching Brightness down Decreases the LCD brightness F Fn F10 Break Fn F12 Suspend to DRAM HDD Force the computer into either Suspend to HDD or Suspend to DRAM mode depending on BIOS Setup 1 3 2 Power on off suspend resume button APM mode At APM mode Power button is on off system power 8575 N B Maintenance APM mode At ACPI mode Windows power management control panel set power button behavior You could set standby power off or hibernate must enable hibernate function in power Management to power button function Continue pushing power button over 4 seconds will force system off at ACPI mode 1 3 3 Cover Switch System automatically provides power saving by monitoring Cover Switch It will save battery power and prolong the usage time when user closes the notebook cover At ACPI mode there are four functions to be chosen at windows power management control panel l None 2 Standby 3 Off 4 Hibernate must enable hibernate fu
271. s by about 33 over the P6 generation processor s branch prediction capability It does this by implementing a 4KB branch target buffer that stores more detail on the history of past branches as well as by implementing a more advanced branch prediction algorithm Enhanced Floating Point and Multimedia Unit The Pentium 4 processor expands the floating point registers to a full 128 bit and adds an additional register for data movement which improves performance on both floating point and multimedia applications Internet Streaming SIMD Extensions 2 SSE2 With the introduction of SSE2 the NetBurst micro architecture now extends the SIMD capabilities that technology and SSE technology delivered by adding 144 new instructions These instructions include 128 bit SIMD integer arithmetic and 128 bit SIMD double precision floating point operations These new instructions reduce the overall number of instructions required to execute a particular program task and as a result can contribute to an overall performance increase They accelerate a broad range of applications including video speech and image photo processing encryption financial engineering and scientific applications 8575 N B Maintenance Features Used for Test and Performance Thermal Monitoring Built in Self Test BIST provides single stuck at fault coverage of the micro code and large logic arrays as well as testing of the instruction cache data cache
272. s for which RSP provides parity protection It must connect to the appropriate pins of all processor system bus agents A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low While RS 2 0 000 RSP is also high since this indicates it is not being driven by any agent guaranteeing correct parity 105 8575 N B Maintenance 5 1 Intel Pentium 4 Processor mPGA478 Socket Name Type Description REQ 4 0 Input Output REQ 4 0 Request Command must connect the appropriate pins of all processor system bus agents They are asserted by the current bus owner to define the currently active transaction type These signals are source synchronous to ADSTBO Refer to the 1 0 signal description for a details on parity checking of these signals Name Type Description TDI Input TDI Test Data In transfers serial test data into the processor TDI provides the serial input needed for JTAG specification support SKTOCC Output SKTOCC Socket Occupied will be pulled to ground by the processor System board designers may use this pin to determine if the processor is present TDO Output TDO Test Data Out transfers serial test data out of the processor TDO provides the serial output needed for JTAG specification support TESTHI 12 8 5 0 Input TESTHI 12 8 and TESTHI 5 0 m
273. s not valid on the bus with DRDY is deserted deasserted to hold the bus DBI 3 0 Dynamic Bus Inversion An active DBI will invert 1 2 1 85V M it s corresponding data group signals DBIO is referenced by HD 15 0 is referenced by HD 31 16 DBI2 is referenced by HD 47 32 DBI3 is referenced by HD 63 48 HDSTBP 3 0 Source synchronous data strobe used to latch data at falling edge 1 2 1 85V M HD 15 0 DBIOZ latched by HDSTBPO HD 31 16 are latched HDSTBP1 HD 47 32 12 are latched by HDSTBP2 HD 63 48 DBI3 are latched HDSTBP3 HDSTBN 3 0 Source synchronous data strobe used to latch data at falling edge 1 2 1 85V M HD 15 0 are latched by HDSTBNO HD 31 16 are latched by HDSTBN1 HD 47 32 DBI2 are latched by HDSTBN2 HD 63 48 DBI3 are latched by HDSTBN3 HNCOMP I GTL N MOS Compensation Input M 108 8575 N B Maintenance 5 2 SiS650 IGUI Host Memory Controller Host BUS Interface Continue Name Pin Attr Signal Description HPCOMP I GTL P MOS Compensation Input M HVREFT 4 0 I AGTL reference voltage HNCOMPVREF M DRAM Controller Name Pin Attr Signal Description SDCLK I SDRAM Clock Input 3 3V M SDRCLKI I SDRAM Read Clock Input 2 5V 3 3V M FWDSDCLKO O SDRAM Forward Clock Output 2 5V 3 3V M MA 14 0 System Memory Address Bus 2 5V 3 3V M
274. sday January 16 2002 Sheet 10 of 29 1 L17 i2 VDDREF 120Z 100M 1608 070 0603 50 123 LAW 2 VDDA48 x U508 120280M 71 cus VDDREF 1 1608 010 voor 010 0603 VDDPCT woe ey My aS ty Page S avs 0603 lt 50 i 507 8651 VDDA48 28 L19 10K VDDAGP 29 VDDA8 i 1 002 0603 VDDCPU 42 CLOSE VDDSD 48 40 R644 4 HCLK CPU TO R622 499 NA VDDSD CPUCLKT 0 HCLK CPU 4 AGER OM CPUCLKC 0 H2 R648 1 2 33 HCLK CPUR 4 0525 Law 1 06030 1608 TA 15 CPU_STP CPU CPU STOPA CPUCLKT 1 4 nm 33 HCLK 515650 6 Deos CPUCLKC 1 Ant HOLK 5188504 6 5628 4 AAA 2 33NA R511 0603 35 QNDREF spram 47 R632 _ 1 22 SDRAMCLK gt SDRAMCLK 7 R6
275. smitter includes a panel fitting up scaler and a programmable dither function for support of 18 bit panels Data is encoded into commonly used formats including those detailed in the OpenLDI and the SPWG specifications Serialized data outputs on three to eight differential channels Hi DE i XCLK2 XCLK2 DES VREF1 Te Enhancernent Scaling Een Conversion LVDS PLL b Eneocke 5arnialtza Figure 1 Functional Block Diagram BCO VSYNC DAC 3 0 LDC 2 LOC 2 0 LLI GLL 1C ENAVDD EMABEL LO C 6 4 LDC 6 4 XUAN XO 22 8575 N B Maintenance 1 2 4 1 TV Out to TV conversion supporting up to 1024 x 768 MacrovisionTM 7 X copy protection support Two variable voltage digital input ports Simultaneous LVDS and TV output TrueScaleTM rendering engine supports under scan in all TV output resolutions Enhanced text sharpness and adaptive flicker removal with up to 7 lines of filtering Support for all NTSC and PAL TV formats Outputs CVBS S Video and RGB Support for SCART connector TV Monitor connection detect Output video switch for easy wiring to connectors 23 8575 N B Maintenance 1 2 4 2 LVDS Out Single Dual LVDS transmitter Dual LVDS supports pixel rate up to 330Mpixels sec when both 12 bit input ports are ganged tog
276. sserting BPRI BRO Input Output BRO drives the BREQO signal in the system and is used by the processor to request the bus During power on configuration this pin is sampled to determine the agent ID 0 This signal does not have on die termination and must be terminated D 63 0 Input Output D 63 0 Data are the data signals These signals provide a 64 bit data path between the processor system bus agents and must connect the appropriate pins on all such agents The data driver asserts DRDY to indicate a valid data transfer D 63 0 are quad pumped signals and will thus be driven four times in a common clock period D 63 0 are latched off the falling edge of both DSTBP 3 0 and DSTBN 3 0 Each group of 16 data signals correspond to a pair of one DSTBP and one DSTBN The following table shows the grouping of data signals to data strobes and DBI Quad Pumped Signal Groups DSTBN DSTBP Uu D 15 0 0 0 D 31 16 1 1 D 47 32 2 2 0 63 48 3 3 Data Group Furthermore the DBI pins determine the polarity of the data signals Each group of 16 data signals corresponds to one DBI signal When the DBI signal is active the corresponding data group is inverted and therefore sampled active high BSEL 1 0 Output The BCLK 1 0 frequency select signals BSEL 1 0 are used to select the processor input clock frequency The required frequency is determined by the
277. st Error 8 11 Audio Failure 8 12 LAN Test Error 8 13 PC Card Socket Failure 8 14 IEEE 1394 Failure 134 8575 N B Maintenance 8 1 No Power When the power button is pressed nothing happens no fan activity is heard and power indicator is not light up Is the notebook connected to power either AC adaptor or battery Try another known good battery or AC adapter or battery Board level Troubleshooting Is the M B and charger Replace the BD connected faulty AC properly Replace adaptor or Motherboard Battery Try another known good charger BD Replace the faulty Charger BD Where from power source problem first use AC to power it Check following parts and signals Parts J2 PF501 PL508 PL501 JS501 PUS502 PD502 PD514 PD505 Check following parts and signals Parts J14 PF502 PL504 PL505 PR564 PUS13 PD506 PD504 PUS12 PR551 509 508 RP553 PR552 Signals ADINP ALWAYS DVMAIN VDDS5S Signals BATT VMAIN ADEN BAT_V BAT_T 135 8 1 No Power 8575 N B Maintenance When the power button is pressed nothing happens no fan activity is heard and power indicator is not light up P15 L32 mee MITAVDD PB BATT A Main Voltage Map PD3 PL5 PQ1 PL6 PU9 gt 1 8V NOTE Charge be U523 Eis DP 1 2
278. t 7 cp cp 3V _BT St 2514 18512 P 4 2 3VS 1 2 USBP4 o SHORT SMT4 3 BT WAKEUP M 1 4 4 5 7 7 5 BT DETACH C849 C850 C851 C852 GND BT 7 EN BT 220 010 0 10 1210 0603 0603 0603 10 50 50 50 1 DF13 8P 1 25HINA 4 15 lt gt NS v cb 3 5 5 1 5VSO VIN our gt 2 ENG BN eve 4 OPEN SMT4 4 1 1 4 C226 Tp E TS C229 0603 0603 0603 0603 0729 80 20 2 50V 50V 50 0603 MITA GND cb cb 8575 MINIPCI amp BLUETOOTH Size lev Document C 411671700010 d ate Wednesday January 16 2002 Eheet 28 of 29 1 4 PHYVDD PHYAVDD UPD72872 U rye 1 2 LNN e BEAD t 7 7 BEAD T t T AD22 0603D 4 4 4 06030 4 4 4 4 C857 C201 C859 C283 C861 C235 C239 C241 C252 INTCH i 470 640 640 010 470 040 040 010 640 i 0805 50V 50V 50 0805 sov 50 50 50 50 REQI GNT1 80 20 06030
279. t during host memory read cycles DMA terminal count OE is used as terminal count TC during DMA operations to a 16 bit PC Card that supports DMA The PCI1410 asserts OE to indicate TC fora DMA write operation BVD2 SPKR Battery voltage detect 2 BVD2 is generated by 16 bit memory PC Cards that include batteries BVD2 is used with as an indication of the condition of the batteries on a memory PC Card Both BVD1 and BVD2 are high when the battery is good When BVD2 is low and BVD1 is high the battery is weak and should be replaced When BVD1 is low the battery is no longer serviceable and the data in the memory PC Card is lost Speaker SPKR is an optional binary audio signal available only when the card and socket have been configured for the 16 bit I O interface The audio signals from cards A and B are combined by the PCI1410 and are output on SPKROUT DMA request BVD2 can be used as the DMA request signal during DMA operations to a 16 bit PC Card that supports DMA The PC Card asserts BVD2 to indicate a request for a DMA operation READY REQ Ready The ready function is provided by READY when the 16 bit PC Card and the host socket are configured for the memory only interface READY is driven low by the 16 bit memory PC Cards to indicate that the memory card circuits are busy processing a previous write command READY is driven high when the 16 bit memory PC Card is ready to accept a new data transfer command I
280. t or throttle CPU activities upon a pre defined power management event occurs INIT OD Initialization 1 1V 2 65V M INIT is used to re start the CPU without flushing its internal caches and registers In Pentium III platform it is active high This signal requires an external pull up resistor tied to 3 3V APICCK I APIC Clock 2 5V M This signal is used to determine when valid data is being sent over the APCI bus A20M OD Address 20 Mask 1 1 2 65 When 2 is asserted the CPU A20 signal will be forced to 0 Name Pin Attr Signal Description PCICLK I PCI Clock 3 3V 5V M The PCICLK input provides the fundamental timing and the internal operating frequency for the 515961 It runs at the same frequency and skew of the PCI local bus C BE 3 0 IO PCI Bus Command and Byte Enables 3 3V 5V M PCI Bus Command and Byte Enables define the PCI command during the address phase of a PCI cycle and the PCI byte enables during the data phases C BE 3 0 are outputs when the 515961 15 a PCI bus master and inputs when it is a PCI slave PLOCK Uo PCI Lock 3 3V 5V M When PLOCK is sampled asserted at the beginning of a PCI cycle SiS961 considers itself being locked and remains in the locked state until PLOCK is sampled and negated at the following PCI cycle 113 8575 N B Maintenance 5 3 515961 MuTIOL Media I O Controller PCI Interface Continue Name Pin Attr Signal Description AD 31
281. t surface SEE ESD Testing specification PN 520 000270 01 Power supply voltage 5 0Voltage 1096 Power supply current 4 0mA max operating 1 4 8 Fan HY45J05 001 1 4 9 Memory e e e DDR RAM ATP 128M 256M DDR RAM Apacer 128M 256M DDR RAM Unidorsa 128M 256M 1 4 10 Modem MDC Askey 60 8575 N B Maintenance 1 5 Power Management The 8575 system has built in several power saving modes to prolong the battery usage for mobile purpose User can enable and configure different degrees of power management modes via ROM CMOS setup booting by pressing F2 key Following are the descriptions of the power management modes supported 1 5 1 System Management Mode Full on mode In this mode each device is running with the maximal speed CPU clock is up to its maximum Doze Mode In this mode CPU will be toggling between on amp stop grant mode either The technology is clock throttling This can save battery power without loosing much computing capability The CPU power consumption and temperature is lower in this mode Standby mode For more power saving it turns of the peripheral components In this mode the following is the status of each device CPU Stop grant LCD backlight off HDD spin down 61 8575 N B Maintenance Suspend to DRAM The most chipset of the system is entering power down mode for more power saving In this mode the following is the status of each device Suspen
282. tes the Audio Controller with AC 97 Interface the Ethernet the Dual Universal Serial Bus Host Controllers the IDE Master Slave controllers and the MuTIOL Connect to PCI bridge The PCI to LPC bridge I O Advanced Programmable Interrupt Controller legacy system I O I O Advanced Programmable Interrupt Controller and legacy power management functionalities are also integrated The SiS961 also incorporates an universal interface supporting the asynchronous inputs outputs of the X86 compatible microprocessors like PIII K7 and P4 The CH7019 is a Display Controller device which accepts two digital graphics input data streams One data stream outputs through an LVDS transmitter to an LCD panel while the other data stream is encoded for NTSC or PALTV and outputs through a 10 bit high speed DAC The TV encoder device encodes a graphics signal up to 1024 x 768 resolution and outputs the video signals according to NTSC or PAL standards The LVDS transmitter operates at pixel speeds up to 165MHz per link supporting 1600 x 1200 panels at 60Hz refresh rate The TI 4410 is a dual function PCI device compliant with PCI Local Bus Specification 2 2 Function 0 provides the independent PC Card socket controller compliant with the 1997 Card Standard The 4410 provides features that make it the best choice for bridging between the PCI bus and PC Cards and supports either 16 bit or CardBus PC Cards in the socket powered at 5 V or 3 3 V as req
283. tion 66 101 In Out HLH2 Horizontal Sync Input Output When the SYO control bit is low these pins accept a horizontal sync inputs for use with the input data The amplitude will be 0 to VDDV VREFI is the threshold level for these inputs These pins must be used as inputs in RGB Bypass mode When the SYO control bit is high the TV encoder will output a horizontal sync pulse 64 pixels wide to one of these pins The output is driven from the DVDD supply This output is valid only when TV Out is in operation Pin Type Symbol Description 112 In Out SDD Low Voltage DDC Serial Data Low voltage serial data for DDC It uses VREF2 2 as the threshold voltage VREF2 divide by 2 function is generated on chip 113 In Out SDC Low Voltage DDC Serial Clock Low voltage serial clock for DDC It uses VREF2 2 as the threshold voltage VREF2 divide by 2 function is generated on chip 65 102 In Out 1 2 Vertical Sync Input Output When the SYO control bit is low these pins accept a vertical sync inputs for use with the input data The amplitude will be 0 to VDDV VREFI signal is the threshold level These pins must be used as inputs in RGB Bypass mode When the SYO control bit is high the TV encoder will output a vertical sync pulse one line wide to one of these pins The output is driven from the DVDD supply This output is valid only when TV Out is in operation 114 116 I
284. troller Host Controller and I O bus masters based on a default optimized priority list with the capability of dynamically prioritizing the I O bus master requests in a bid to offering privileged service to 1 the isochronous downstream transfer to guarantee the min latency amp timely delivery or 2 the PCI master upstream transfer to curb the latency within the maximum tolerant period of 10us Prior to the memory access requests pushed into the M data queue any command compliant to the paging mechanism is generated and pushed into the M CMD queue The M data M CMD Queues further orders and forwards these queuing requests to the Memory Interface in an effort to utilizing the memory bandwidth to its utmost by scheduling the command requests in the background when the data requests streamlines in the foreground 8575 N B Maintenance 1 2 3 2 515961 MuTIOL Media I O overview The SiS961 MuTIOL Media I O integrates the Audio Controller with AC 97 Interface the Ethernet MAC the Dual Universal Serial Bus Host Controllers the IDE Master Slave controllers and the MuTIOL Connect to PCI bridge The PCI to LPC bridge I O Advanced Programmable Interrupt Controller legacy system I O I O Advanced Programmable Interrupt Controller and legacy power management functionalities are also integrated The 515961 also incorporates an universal interface supporting the asynchronous inputs outputs of the X86 compatible microprocessors like PIII K7 and P4
285. ty ALC201 Line output with 50mW 20ohm driving capability ALC201A Headphone jack detect function to mute LINE output Multiple CODEC extension MC 97 chained in allowed for multi channel application External Amplifier power down capability Support S PDIF out is fully compliant with AC 97 specification rev2 2 41 8575 N B Maintenance DC offset cancellation Power support Digital 3 3V Analog 5V Standard 48 Pin LQFP Package 1 2 8 MDC PCTel Modem Daughter Card PCT2303W The PCT2303W chipset is designed to meet the demand of this emerging worldwide AMR MDC market The combination of PC TEL s well proven PCT2303W chipset and the HSP56TM MR software modem driver allows systems manufactures to implement modem functions in PCs at a lower bill of materials BOM while maintaining higher system performance PC TEL has streamlined the traditional modem into the Host Signal Processing HSP solution Operating with the Pentium class processors HSP becomes part of the host computer s system software It requires less power to operate and less physical space than standard modem solutions PC TEL s HSP modem is an easily integrated cost effective communications solution that is flexible enough to carry you into the future The PCT2303W chip set is an integrated direct access arrangement and Codec that provides a programmable line interface to meet international telephone line requirements The PCT2303W chip set is
286. uded for compatibility with systems using MSDOS type floating point error reporting INIT Input INIT Initialization when asserted resets integer registers inside the processor without affecting its internal caches or floating point registers The processor then begins execution at the power on Reset vector configured during power on configuration The processor continues to handle snoop requests during INIT assertion INIT is an asynchronous signal and must connect the appropriate pins of all processor system bus agents If INIT is sampled active on the active to inactive transition of RESET then the processor executes its Built in Self Test BIST ITPCLKOUT 1 0 Output The ITPCLKOUT 1 0 pins do not provide any output for the Pentium 4 processor in the 478 pin package GTLREF Input GTLREF determines the signal reference level for AGTL input pins GTLREF should be set at 2 3 Vcc GTLREF is used by the AGTL receivers to determine if a signal is a logical 0 or logical 1 Refer to the ntel amp Pentium 4 Processor in the 478 pin Package and Intel amp 850 Chipset Platform Design Guide for more information ITP CLK 1 0 Input CLK 1 0 are copies of BCLK that are used only in processor systems where no debug port is implemented on the system board CLK 1 0 are used as BCLK 1 0 references for a debug port implemented on an interposer If a debug port is implemente
287. uired Function 1 of 4410 is compatible with IEEE1394A and the latest 1394 open host controller interface OHCI specifications The chip provides the IEEE1394 link function and is compatible with data rates of 100 200 and 400Mbits per second Deep FIFOs are provided to buffer 1394 data and accommodate large host bus latencies 8575 N B Maintenance The 14410 provides physical write posting and a highly tuned physical data path for SBP 2 performance Multiple cache line burst transfers advanced internal arbitration and bus holding buffers on the PHY Link interface are other features that make the PCI4410 the best in class 1394 Open HCI solution To provide for the increasing number of multimedia applications the AC97 CODEC ALC201 is integrated onto the motherboard A full set of software drivers and utilities are available to allow advanced operating systems such as Windows Me and Windows 2000 to take full advantage of the hardware capabilities such as bus mastering IDE Windows 95 ready Plug amp Play Advanced Power Management APM and Advance configuration and power interface ACPI Following chapters will have more detail description for each individual sub systems and functions 8575 N B Maintenance 1 2 System Hardware Parts Intel Pentium 4 processor Willamette Northwood with mFCPGA2 Package mPGA 478 Socket Support up to Willamette P4 1 7GHz Throttling Northwood above 2 0 GHz Throttling FSB 400M
288. ust be connected to a VCC power source through a resistor for proper processor operation SLP Input SLP Sleep when asserted in Stop Grant state causes the processor to enter the Sleep state During Sleep state the processor stops providing internal clock signals to all units leaving only the Phase Locked Loop PLL still operating Processors in this state will not recognize snoops or interrupts The processor will recognize only assertion of the RESET signal deassertion of SLP and removal of the BCLK input while in Sleep state If SLP is deasserted the processor exits Sleep state and returns to Stop Grant state restarting its internal clock signals to the bus and processor core units If the BCLK input is stopped while in the Sleep state the processor will exit the Sleep state and transition to the Deep Sleep state THERMDA Other Thermal Diode Anode THERMDC Other Thermal Diode Cathode SMI Input SMI System Management Interrupt is asserted asynchronously by system logic On accepting a System Management Interrupt the processor saves the current state and enter System Management Mode SMM An SMI Acknowledge transaction is issued and the processor begins program execution from the SMM handler If SME is asserted during the deassertion of RESET the processor will tristate its outputs THERMTRIP Output Assertion of THERMTRIP Thermal Trip indicates the processor junction t
289. ve the base unit cover See steps 1 6 in section 2 2 10 Disassembly 2 Remove the eight screws to lift up the touch pad holder and touch pad panel Figure 2 26 Figure 2 26 Remove the touch pad Reassembly 1 Replace the touch pad holder and touch pad panel and secure with eight screws 2 Assemble the base unit cover See section 2 2 10 Reassembly 92 8575 N B Maintenance 2 2 12 Modem Card Disassembly 1 Remove the battery pack keyboard CPU HDD module CD DVD ROM drive and LCD assembly See section 2 2 1 to 2 2 5 and 2 2 7 Disassembly 2 Disassemble the notebook to access the system board See section 2 2 10 Disassembly 3 Remove the two screws fastening the modem card and then disconnect the cable from system board Figure 2 27 Figure 2 27 Remove the Modem card Reassembly 1 Reconnect the cable to the modem card and secure the modem card with two screws 2 Assemble the notebook See section 2 2 10 Reassembly 93 8575 N B Maintenance 3 Definition amp Location of Connectors Switches 3 1 Mother Board A 1 1 J5 J8 J9 J11 J12 J13 Modem Connector RJ11 72 LCD Connector JA MDC Jump Wire Connector 76 J7 External VGA Connector D D Connector Easy Start Buttons Connector MISC Connector Fan Connector LAN Connector RJ45 PC Card Socket Secondary IDE Connector Internal Keyboard Connector Battery Connector 94
290. witching outputs CardBus request GPI2 GPO2 socket activity LED output ZV switching outputs PAR PCI bus parity In all PCI bus read and write cycles the PCI1410 calculates even parity across the AD31 ADO and C BE 3 C BE 0 buses As an initiator during PCI cycles the PCI1410 outputs this parity indicator with a one PCLK delay As a target during PCI cycles the calculated parity is compared to the initiator s parity indicator A compare error results in the assertion of a parity error PERR audio PWM GPE or a parallel IRQ Serial clock SCL When VPPDO and VPPDI are high after a PCI reset the MFUNCA terminal provides the SCL signaling for the serial bus interface The two pin serial interface loads the subsystem identification and 16 Bit PC Card Address and Data Slots and B other register defaults from an EEPROM after a PCI reset MFUNCS5 vo Description IO Multifunction terminal 5 MFUNCS can be configured as DMA grant GPO4 socket activity LED output ZV switching outputs CardBus audio PWM or a parallel IRQ ADDR 25 0 PC Card address 16 bit PC Card address lines ADDR25 is the most significant bit MFUNC6 IO Multifunction terminal 6 MFUNC6 can be configured as a PCI CLKRUN or a parallel IRQ 15 0 PC Card data 16 bit PC Card data lines 15 is the most significant bit RI

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