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digital key telephone system service manual

1. _ C uman as 0 KA ii e 7 roo e serna 238 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM ELFR9001501 INDUCTOR RADIAL C C 90UH 90 uH M R TP ROHS 421 422 450 451 C500 5 ECCH0000225 CAP CERAMIC CHIP 47 pE 50V J NPO TC 1608 R TP 3 01 ECES0000120 4 7 STD 5 5 2 R TP 0000108 1 uF 16V K STD 3216 TP ECTH0000113 2 2 uF 16V M STD 3216 TP C437 C458 C460 C466 0000113 CAP TANTAL CHIP 2 2 UP 16V 3216 P 3 0000117 4 7 uF 10V 970 3216 0000121 10 uF 10V K STD 3216 TP 0000126 10 uF 6 3V M STD 3216 TP EDBVO000601 THAILAND SMD 600V 0 5A R TP ED4016 EDNY0001802 7 84 3 91710 50 23 3 9 V 35 W R TP PB FREE FDNY0001804 BZX84C6V8LT1G SOT 23 6 8V 0 35W R TP FDSY0002901 KDS193 SOT 23 85V 0 3A R TP FDSY0003001 KDS226 RTK THAILAND 50 23 85 0 1 EDSY0004501 RS26 D0 214MA SMB 400 V 1 5 A R TP FAST SWITCHING 3 3 3 0002801 G6K 2F Y TR DC4 5V 4 5 V V A ohm 2 EQBNO003001 KST13 MTF S0T 23 0 35W R TP DARL INGTON EQBNO003501 BC846BL T1G S0T 23 0 TP EQBP0001402 KST63 MTF S0T 23 0 35W R TP 01801 BC856BL T16 SOT 23 0 3M R TP FRHY0000342 12K ohm 1 16W F 1608 R TP 0000367 100K ohm 1 16W F 1608 R TP ERHY0000401 0 ohm 1 16W J 1608 R TP 8 8351 358 9391 398 ERHY0000466 10K
2. X ELK YI 2 0071 Sarin 421 0 ee ee E TY 4 ill ii 165 R d ml E s RUE gt PERE CABS VIM 41 VINI a T YING lt UIN e DIN IUTE DIN 106 bp A i Bed P DOUT SE 26 COUT i kk d 509 Dar ja i il 1 ET WIN SUME X PP PESET y PP PP 9049 u FR mon si T Qo LEID g 504 2 A A LL a 4 E T Es poo rT it ND E n He PM MENU LIPP Bi T m me Hann mnm LDO0P RINGI LOOP PING 1 TET Figure 3 3 3 Digital part Analog signal part CO analog signal part of CHB308 and CSB316 consist of DC loop circuit and loop amp ring detection circuit Codec interface circuit The port 1 is used for circuit description as an example 2501 ze BEN 111 011 2012 D 111 a DIT 8 88 Rl E T 45 ipLDK 60 SERVICE MANUAL DIGITAL KEV TELEPHONE SVSTEM 3 Figure 3 3 4 SLT interface circuit The line protection circuitrv consists of
3. Gl Figure 3 3 9 The hook sensing circiut DKT Digital Terminal part The digital line interface circuit is composed of the GSL12 block of ACT a matching transformer capacitors resistors and a posistor It provides a connection with two wires to one digital terminal Capacitors and diodes are used for protecting line interface circuit against ESD or lightning surge provides 30V power to the digital terminal through the transformer and posistor is used to protect the over current due to line short The DKT TX interface line of the GSL12 block of ACT2 on the MBU are output terminals and used to transmit a digitized voice and data to the digital terminals via the transformer And the DKT RX lines of the GSL12 block of ACT2 are input terminals and are used to receive a digitized voice and data from the digital terminals Figure3 3 10 Digital line interface circuit for CHB308 48 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 3 3 4 Meaning of Connectors The CHB308 has three 3 connectors for installation of CMUSOPR or CMU12 16PR and connection with MBU or EMBU STAQ 10 5 11 STA12 STA13 STA14 5 15 16 MM CMUSOPR To DKT or SLT CHB308 To CO line Figure 3 3 11 CHB308 Layout Pin assignments of CN1 CN2 and for CHB308 1 10 12 21 B5 B11 Reserved PFT CTL PFT control signal Feeding B1 MPX RX1 PCM bus RX
4. 2 202 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 3 020 040 EUSY0050701 IC LOW SPECTRUM SPREAD CLOCK CYIFS781BSXC SOIC 8 PIN R TP lam pes EUSYOO49201 1C UNDERVOLTAGE SENSING MC340640 5R2G S0 8 8 PIN R TP CD 023 124 EUSYOO03101 IC REAL TIME CLOCK 042724211000200 DIP 18PIN ST EUSYO 149001 1 SECURE MEMORY 885 153 1050 2 7 5016 8 PIN R TP EUSYO270801 16 3 3 Single Power Phy KSZ8721SL SSOP 48 PIN R TP Pb Free EUSYOO49101 1C 3A LDO REGULATOR FAN1587AM33X T0 263 3 PIN R TP PB FREE U IC QUAD BUS BUFFER WITH 3 STATE EUSYO 111801 MC74VHC1250T TSSOP 14 PIN R TP CONTROL INPUTS i I U71 U82 U123 I EUSY0049801 IC LOW VTG OCTAL BUS TRANSCEIVER TC74LCX245FT TSS0P 20 PIN R TP 3 U113 U116 U118 EUSY0037302 1 0 AMP NJM4556M SOIC 8PIN R TP U114 U117 EUSYO036702 1 COMPARATOR LM2903MX S01C 8 PIN R TP PB FREE 0119 EUSYO130003 1C DC DC CONVERTER NCP1117ST18T3G SOT 223 3 PIN EPM3128ATC100 10 TQFP 100 PIN PLD 192 MHZ CLOCK 229 120 121 EUSPO 18 701 IC PBX 250MHZ IC DC TO DC CONVERTER CONTROL 3 0122 EUSY0078 101 MC34063AD SO 8 8 PIN R TP CIRCUITS 25MHZ 49 5 50 20 pF 50 0005801 X TAL 25 MHz ohm SMD 11 4 4 67 3 4 EXSY0001201 OSCILLATOR 32 768 MHz KMS 870R 32 768 7 25 PPM 15 pF SMD 7 025 0s1 7 CD 2
5. 82 3 949 C Irc UE SSCP HOW Men PU LU 82 3 9 4 Meaning of Connectors Switches and LEDS pp 87 9 10PSU POWER SUPPLY SL tea ueni ta 89 SUN IBIOGK uuu 89 10 2 Operaton ia orae eode wat a g 90 SECTION 4 TROUBLESHOOTING i a Qua Ceca A VIE MM c 92 EMB U ta ipse dium a an MO RE M RE HDI IM a 123 139 151 2255 o 161 SIL 167 173 4 O IE EEA 176 AI 179 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM BOC NA ane 199 A M 200 5 PART EIS T a a 202 IE na 202 52 ESU E E 211 218 0 10 22 MET 221 P MS 227 mc 231 238 245 9 249 SAIS TR NEM 249 ATA DUE 250 SNAP d ENT 252 au Mirta te dde pad ue enden E tar cl ata pato IUD NA ua rere 253 ipLDK 60 SERVICE MANUAL DIGITAL KEY TEL
6. a 12 2 9 General DescripllODn iss u u L ha Ua d le ette ri de de E ea cd 12 2 9 2 5ystem Generic Ro sa ael caf 12 2 Operalitg Memory E TI 12 2 3 4 Customer Database 12 ila RESOURCES T 12 ASGALL PROCESSING Z a 14 241 Internal uy u i E 14 24 2 Outside Call TY DOS cc 14 ZA 9 COBDIGEFOPCIDIG aea ie i 15 SECTION 3 CIRCUIT DESCRIPTION a a da 3 1 MAINBOARD UNIT WITH C O ie u 16 iii L ee een eee eee 16 3 1 2 Block Diagram amp Circuit DESEHIDUON 17 3 1 3 Meaning of Connectors Switches and LEDS pp 33 9 2 EMBU EXPANSION MAIN BOARD UN 39 2 BEIM UE UT mm 39 e272 BIOGK DAO UTER 39 3 2 9 CIFCUIL ed ba g an 40 3 2 4 Meaning of Connectors and LEDS nanna 40 3 9 GHBDOUGAND CSB a a G d ui 43 aa ssib 43 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 9 9 2 2107 4126 a _ ice nd Lene 43 9 9 9 C jek A Da aa 44 3 94 Meaning or CONNECIONS u uuu D I 49 3 4 SLIB8 SINGLE
7. ua E tt S a ta u Ll SLT VOUT Figure 3 3 1 Block diagram of CHB308 43 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM L P ETE SLT SLT VOUTI SLT WIR SLT WOUTI SLT VIN3 SLT VOUT3 SLT WIN SLT VOTTA SLT WINS SLT WOUTS SLT WIN OPTION 68 SLT WOUT SLT WAT SLT Wot ELT VINE SLI Port 1 8 SLT VOTE sur gr ernie ELT H DK SLT VIN l i SLT VOTT 10 112 114 115 Bim E BIO rq sa e a A SLT ELT E315 Figure 3 3 2 Block diagram of CSB316 3 3 3 Circuit description Digital signal part Digital signal part of CHB308 and CSB316 boards consist of SICOFI U1 U2 U3 for A D conversion voice signal and Address decoding parts Relay control parts loop amp ring read buffer SICOFI U1 U2 U3 is IC which convert voice into digital PCM data and reverse function But the function of PCM data switching exist in ACT2 IC on IC 06 is used for address decoding 07 is used for control of SICOFI IC 08 and 04 are used for loop relay control and SMS switch control for IC 09 is used for CO Loop amp ring signal detection IC 010 and U5 are used for SLT ring relay IC U11 is used for SLT off hook signal detection 44 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM uz JD dns HELE m PG
8. r Y Y NO 22 neu acrz Figure 3 5 16 Clock driver and buffer circuit H LAN interface circuit The S3C4530A has an Ethernet controller which operates at 10 Mbits per second in half duplex or full duplex mode The Ethernet controllers MAC layer supports media independent interface MII that supplies the transmit and receive clocks of 2 5MHz at the 10 Mbit s speed In half duplex mode CPU supports IEEE802 3 carrier sense multiple access with collision detection CSMA CD protocol and in full duplex mode it supports IEEE 802 3 MAC control layer including pause operation for flow control 10 100BaseTX FX Physical Layer Transceiver with Auto cross over U8 58721 generates 2 5V power with an internal regulator and provides control signal to GREEN LED of MJ1 to indicate Ethernet link state Line interface circuit incorporates noise filtering L1 L2 and line protection circuit D25 D28 and T1 to prevent 08 from being damaged from high voltage surge and electrical fast transient and burst e FB i KOSEPBS Y wo pa eie LL n EM RX i d t RX T RD R44 lt 1555 75 LINK 479 jr Figure 3 5 17 Ethernet line interface circuit The filters L1 and L2 suppress electronic magnetic interference and diodes D25 D28 protects Ethernet PHY U8 KSZ8721SL from high voltage surge electri
9. Diaeram of Diagram of ipLDK 60 MOD 2MCLK MPX RX MPX TX FRAMES THC der 3538 SESE RR ERR RRR a Figure 3 7 1 Block Diagram of MODU MODU consists of MODEM chip 12457 line side direct access arrangement DAA chip Si3018 CODEC DC DC power generation circuit and so on MODEM chip U1 is a complete embedded modem chipset with integrated direct access arrangement DAA that provides a programmable line interface to meet global telephone line requirements It includes a DSP data pump a modem controller on chip RAM and ROM an analog front end AFE a DAA and an analog output Line side DAA chip U2 connects directly with the telephone local loop TIP and RING Data interface with CPU can be configured as either a serial UART interface with flow control or as a parallel 8 bit interface The UART port1 of CPU is used for serial interface with MODU Modulated analog signal from PSTN through CO interface circuit is converted to PCM data by CODEC before it is switched to MODU The CODEC U3 on the MODU extracts PCM modem data from a time slot of PCM highway with a specific frame sync signal FRAMSYNC and converts it to analog signal This expanded modulated analog signal is sent to MODEM chip through line side DAA chip U2 and telephone line 76 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM circuit for de modulation The signal flow from MODU to PSTN works with the polar
10. 1 25Hz square 55Vrms 65Vrms ire H2 zn EN ibe E gt RING Figure 3 1 26 Ring generation circuit 31 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM LAN Circuit The S3C4530A has an Ethernet controller which operates at 10 Mbits per second in half duplex or full duplex mode The Ethernet controllers MAC layer supports media independent interface that supplies the transmit and receive clocks of 2 5MHz at the 10 Mbit s speed The is used to LAN circuit through connector MJ3 on the In half duplex mode CPU supports IEEE802 3 carrier sense multiple access with collision detection CSMA CD protocol and in full duplex mode it supports IEEE 802 3 MAC control layer including pause operation for flow control LAN circuit is composed of 10 100BaseTX FX Physical Layer Transceiver with Auto cross over 030 KSZ8721SL Ethernet interface circuit power regulator that provides PHY with 2 5V power and EEPROM in which some information such as MAC address is stored Data transformer T1 protects the secondary circuits from high voltage surge It is possible to check the state of LANU visually by LEDs on RJ45 modular jack MJ1 LED LD1 Green Data Transfer Status toggle ON link OFF no link LD2 Orange Link Status and Activity ON link and activity at 100MBps OFF link and activity at 10MBps MODULAR JACK MJ3 CONNECTOR PIN NUMBER
11. 1850mm EUROPEAN SWPY0005401 POWER CORD ASSY APPROVED 2 WIRE ASSY 90000101 3600 mm 4 11 16 4101500000 2 emma T T E sto 6 nia ae 2 7 C ae errr ref evince re mom ava wa EFIE ee Bee y 1 1 si EE esee meer LT THAILAND 3mm 10mm SBA1 FZY M3x10 GMDV9000801 SCREW MACHINE FLAT TS an Flat L MIBA9001102 TEMPLATE MOUNTING MOUNTING IPLOK 60 BKSU STG WA Mount ing Template ipLOK 60 GMFY0001801 3 MM 6 MM SB41 FZY B KB1023 M3 X 6 1 GMFY0OO01801 SCREW MACHINE PAN SZ P GTFB0002001 3 MM 10 MM SB41 FZV B 4 TB X10 SZ GTFBO002001 SCREW TAP TITE PAN re ST CAD THRE OPER gt enjan eos T MT T 217 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 5 3 CHB308 MLAC9006306 LABEL BARCODE IPLOK 60 BKSU BRA WA IPLDK 60 BKSU BRA WA NORTEL MASTER BOX SPEC 79045001 LABEL LABEL SAGV9250202 CHB308 PCB ASSV OPTION IPLDK 60 CHB308 BRA OPTION 1 4 U100 U102 SHPVO000101 PHOTOCOUPLER TLP521 2GR 8PIN 2PORT GR DIP sTMYO000301 TRANSFORMER MATCHING 6170NA0001D 5 PIN DIP 4H 1H T 2 1 T11 18 STMY0003801 TRANSFORMER MATCHING STMYOO03801 5 PIN DIP 121 2
12. Pin8 of U121 25Hz YES NO Check of 2Mhz Clock Download PLD Image and or Replace U121 98 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 1 9 Clock generation circuit FRAMEOUT pin 104 of 08 244ns 122ns CLK8M 8MHz INV 2MHz pin 22 32 of U9 11 MPX TX RX 2Mbps U9 U10 U11 One channel of MPX bus 3 9us IDT SICOFI FS pin 31 of 49 11 Frame Syne ST BUS 15 i ST BUS CH 16 31 f V V M M l 2 3 BKSU and 7SLT MBU VMIU AAFU MODU lt lt MPX RX 5 V L M T 2 U CD and 7511 MBU VMIU AAFU MODU 308HYB 316SLB 8SLB on BKSU MHT D m A NHT NHT MPX1 TX RX Aro J 1 ro CO lt Clock generation and MPX PCM highwav gt 99 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM CLK32M Check the frequency measured at pin 120 of U8 ACT2 NO Check and Replace X3 R 1 R 2 around U40 FB8 For SICOFI U9 U10 U11 2M HZ DT on MBU amp Option Board Check the frequency measured at FB11 pin 43 of U8 gt Check the FB11 U8 amp Connection Status 2MHZ_VMIU For DSP U1 on VMIU AAFU Check the frequency measured at FB9 pin 41 of U8 Check the frequency measure
13. 5 00 5 5 107 Acqs B High 5 04 the circuit around U8 Check the negative IX signal measured at pin 161 of U8 on MBU Check the circuit around U8 Check the Mixed TX RX signal measured at C347 9 at Pin 41 B15 of NO gt Check the circuit around C347 C365 on MBU YES 5 00 5 5 31 Acqs a T egos lt gt une 15 11 50 195 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 2 Line feeding voltage 30V check Start Check the voltage level of VO Check the voltage level of the signal measured at one lead of PT8 Sheet 7 7 PSU Check components are damaged or not Note 1 PT8 T11 C189 D22 and D23 196 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 9 1 14 SLT interface circuit For the SLT interface circuit on 5108 add on board please refer to the descriptions of CSB316 extension board T Check SLU8 add on Off hook or SLT Check decoder U22 and buffer U37 Replace 022 037 or 010 lt Check 030 and output buffer U32 Yes Give ring to any SLT Yes Off hook SLT Is dial tone heard Check 030 and input bu
14. RJ45 modular jack MJ1 e gt MJi LED LED1 Green OFF No Link ON Link Toggle Data Transfer LED2 Orange OFF Link and activitv at 1OMbps ON Link and activity at 100Mbps Table 3 5 9 MJ1 LED Indications 71 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM C Modular jack pin assignment LAN PORT MJ1 Conector Pin Number SIGNALNAME FUNCTION 4 5 7 8 RESERVED Transmit Data mensmtDab RI _ Table 3 5 10 Pin assignment of MJ1 RX Tip RX Ring TXTi 5 2 ra Table 3 5 11 Pin assignment of MJ3 1111 RJ11 PORT Connector PINNumber NO SIGNAL NAME Table 3 5 12 Pin assignment of MJ2 72 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 3 6 VMIU AAFU Voice Mail Interface Unit Auto Attendant Function Unit 3 6 1 General The VMIU Provides the announcements for the system s UCD feature as well as the system voice prompt and personal user greetings System voice prompts UCD and user greeting will be stored in Flash memory Voice data are compressed or decompressed by the processing of DSP during recording and playing There are four 4 recording playing channels Note that each channel can operate as either recording or playing mode at a time The DSP TMS320VC5402PGE provides 32Kbps at an 8KHz sampling rate when activated without gap coding This board can be installed VMIU AAFU slot on MBU 3 6 2 VM
15. 1 14 External MOH Analog music sonal sheet 5 7 10 l Connect external music source to And then check the signal measured at 487 or 64 of U11 v circuit of T4 pin 64 of 011 Check amp Replace the around 1 15 External sheet5 t0 Analog signal l Program external PAGE mode and then check the signal measured at pin 62 of 011 Check 2MCLK FRAMESYNC ao lt gt and the around circuit of 011 U8 amp Audio Source v Check the signal measured at PJ2 BLUE or FB14 Check the around 105 circuit of T5 FB14 FB15 amp External Amplifier Speaker ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 1 16 RGU check NOU CZ oHZ RSET ck cang BGN 2200 PEGE ET B tu P853 9 1 gt C811 808p RET T 2972 4 o PEE PBT3 DK 2 R875 i mn 058 alee 4 Ty B S45BL RETT Rete gt RING y Note RGU operates just in SLT ringing state it doesn t work during SLT idle state Ringing state 25Hz square wave idle state no output Ring Generation
16. 94 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 1 5 Reset and Watch dog circuit TEE heet 2 1 Reset OK NO By Power ON Check amp Replace U23 YES NO Reset OK Check amp Replace U23 R236 SW3 Reset Switc R237 R239 R240 C57 C58 C59 YES NO wes Check R231 R233 U86 U85 and U1 Pulse enable YES Check watch dog pulse at pin 199 of U1 and Pin 12 of U85 Pin 15 of U85 4 Replace 085 Low 2 R234 R235 R238 C56 YES End 95 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 1 6 Real Time Clock RTC circuit HTC circuit Check the power of 18 of U24 is 3 0V When System Power OFF SW2 5 VB source R232 C55 YES NO Check CS U121 OE and Check control signals Address Data and Replace U24 RTC YES End 96 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 1 7 1st PLD Circuit 1st PLD 0120 PCLK Pin 87 of U120 50Mhz ME Check 045 18 81646 FB57 YES NO Goto Check of System Reset Trigger at Pin90 of 0120 Compare Pin90 with 49 CS FLASHO NO Download PLD Image and or Same shape P Replace U120 YES 9 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 1 8 2nd PLD Circuit 15 PLD 0121 Check 045 18 1646 FB57 NO Check of System Reset Circuit NO YES
17. SCHMITT EUSY0093 01 INVERTER MC ALCX14DTR3 TSSOP 14 PIN PB FREE 22 23 UAB EUSVO050701 IC LON SPECTRUM SPREAD CLOCK LOW EMI SPECTRUM SPREAD CLOCK CYIFSTBIBSXC S0IC8 PIN S01C 8 PIN U47 U112 99999999999 IN ASSEMBLE M ASSEMBLE qu ____ EA m EN P s 3 HN 245 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM EUSY0085301 1 VOLTAGE CMOS BUFFER MC74LCX541DTR2G TSSOP 20 PIN 3 STATE Cs CA TA 3 ws 1 3 0 sirare oe my _____ INP Free 246 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 131 136 144 ECCHO000272 CERAMIC CHIP 247 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM R304 R345 R419 420 ERHYOOO0450 RES CHIP jsemew mum E ma is 28 SI RUNE L AW eese ume ase 222200002 ABAZO007307 BAG ASSY IPLOK 60 VOIB STG ZZ ipLDK 60 Bag Ass v VOIB GMFVOOO1801 3MM 6MM 5841 227 B KB1023 M3X6 GMFYOO01801 SCREW MACHINE MBADOO02408 BAevIYLF VINVL BAevIYLF 77 UNDERAY X DX A MMCY9001001 MOUNTING SCREW IPLOK 60 VOIB STG SV Mount ing Screw M3x19 5 248 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 5 9 VOIU pesos AO ooe ase erin KA ra STOMA MBEF9105801 AR DPU2 STG ZZ a E MLAC9006303 LABEL BARCODE LVP 2890 USA MS WA LVP2890 BOX BARCODE LABE
18. 172 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 7 VMIU AAFU 7 VMIU AAFU 7 1 Power status Check the 5 Check the Connector CNI pin A1 Check the component of the 3 3 3 3V Generation part 1 U8 No 2 Yes Check the component of Check the 1 8 1 8V Generation part 2 U Note 1 07 08 173 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 7 2 Clock Check 10MHz Check amp Replace X1 Check R9 R10 174 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 7 3 Play Record status Yes play the prerecorded messag Ex Time stamp Timing Check U9 Pin 11 8 U9 Pin 3 Check the Clock amp Power 175 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 8 VOIB 8 1 3 3V check Check the voltage level of the signal measured at pin 2 of U12 sa Yes 8 2 1 8V check Check the voltage level of the signal measured at oin 9 of U114 8 VOIB 1 check pin 3 of 038 2 Check the components 012 1 5V check 1 of 0114 2 Check the components U114 R459 R457 C220 1 6 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 8 3 1 2V check Check the voltage level of the signal measured at 1 5V check pin 1 of 055 pin 5 of U55 Yes 2 Check the components U55 R424 R423 8 4 Clock check R199 10Mhz Check amp replace X1 U2
19. Check the CO fusible Resistor R401 R406 Change the Resistor R401 R406 Check the Transformer wire impedance T1 T3 Change the transformer 130 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM Check the loop current circuit Q16 Change the transistor Check the loop current sensing signal LOOP_RING Check the circuit around 0100 8431 8451 452 Check voice signal VIN amp VOUT at 2 around U2 Yes Check Signal Check U1 U42 48 pin of U8 are damaged or not the components are damaged ornot 131 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 2 CO Ring detection check 1S Port PORT 1 Check the incoming ring path Check the components 1 are damaged or not Can you see ring signal at pini 1 of U100 No Yes Replace the U100 Check the loop current sensing signal LOOP RING Check the circuit around U100 Yes NO Check route of ring sensing signal LOOP RING Check the circuit around U120 to port of U120 pin 29 pin 9 of U120 CO LOOP RING DET NO Yes Note 1 C401 R401 R402 RLA R411 2011 2012 BD1 011 012 R421 R422 R431 132 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 2 9 Digital Terminal Interface 15 port sheet 6 7 1 AMI signaling check Digital Line Signal Check the positive TX signal measured at
20. Polarity Reversal OutD COIT CMU Outi CO2R DET2 Polaritv Reversal Out2 2 CMU _ DET2 gt 16KHz _ DET3 Polaritv Reversal Out3 DET3 Out3 CO3T Figure 3 8 2 Block diagram of CMU12PR 78 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 3 8 4 Circuit description A Polarity Reversal part PR DETECTI lt FI RI HE a E rtu ii i PSI a Polarity Reversal OUT 1 E oou Figure 3 8 3 PR detection circuit This section describes 1st port related 1st CO as an example Tip and Ring signal of CO pass through high impedance resister R1 R2 R11 R12 And then come to U1 for comparison between Tip polarity and Ring polarity So if polarity is changed POL signal refer to above picture will be changed different value low become high high become low And then the CPU on MBU indicates changed polarity B Call Metering 50 Hz detection part CM 1 DETECT ERA ur 3 7 u T Figure 3 8 4 Call Metering 50Hz detection circuit This section describes 1st port related 1st CO as an example Tip and Ring signal of CO pass through high impedance resister R1 R2 R11 R12 And then come to U1 for comparison between Tip polarity and Ring polarity So if polarity is changed sig
21. SAGA9056201 PCB ASSY OPTION AUTO IPLDK 60 SLIB8 STG OPTION 1 1 U6 EUSVOOSOBOT IC LON VTG 3 0 8 LINE DECODER LOW VTG 3 T0 8 LINE DECODER TC74LCX138FT TSSOP 16 PIN TSSOP 16 PIN IN OCTAL D TYPE FLIP FLOP 3 STATE U U10 EUSY0062001 OUTPUT TC74ACTS 4FT TSSOP 20 PIN uut U11 EUSVODBS301 IC LON VOLTAGE CMOS BUFFER LOW VOLTAGE CMOS OCTAL BUFFER MC74LCX541DTR2G TSSOP 20 PIN 3 STATE TSS0P 20 PIN 3 STATE Ls poora eme warm eem re 7011 16 2021 26 99999999999 NOT ASSEMBLE KDS226 RTK THAILAND SOT 23 85V 0 1A R TP Ls wm z RS2G 00 214AA SMB 400V 1 5A FAST SWITCHING 228 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM n C28 1 288 0404 407 99999999999 NOT ASSEMBLE NOT ASSEMBLE 229 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM n R271 278 ERHY0000952 RES CHIP 1K 1 10W IPLDK 60 SLIB8 STG ZZ ipLDK 60 Bag GMFYOOO 1801 6MM 5841 FZY B KB1023 M3 X 230 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM GTFB0001801 3MM 8MM SB41 FZY B 4 TB X 8 SZ GTFBOO01801 SCREW TITE PAN B P DJ MBADO002408 BAG VINYL PE 77 UNDERAY X DX A DJ MMCV9001101 MOUNTING SCREW IPLOK 60 CHB308 STG SV Mounting Screw M3x28 3 MEER MSAZ9033602 SHEET AR SLIB8 STG WB ARIA SOHO 8SLB Sheet MBAA9001803 BAG AIR CAP AR SLIB8 STG ZZ AR MBU STG ZZ 0 06t X 270 X 35
22. SIGNAL NAME FUNCTION RJ45 4 5 7 8 Reserved Rx 32 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 3 1 3 Meaning of Connectors Switches and LEDs There are various kinds of connectors switches modular jacks and LEDs in the MBU The below figure MBU Configuration shows the configuration of MBU and the location of connectors switches modular jacks and LEDs CN13 DPU2 CN3 LANU CN9 10 CMUSOPR CN2 CHB308 CSB316 SLIB8 CN1 To EKSU H CN4 MODU ia rr m ma sm 111 111 CN5 VMIU AAFU f L N Tx SW2 should be turned o ___ CN7 PSU connection ON position before the svstem installation to protect svstem data in the case of power failure 6 102 103 104 HB H BH SW3 System reset button Figure 3 1 27 MBU Layout A Functions of connectors modular iacks and switches SWTCHCONNECTOR FUNCTIONS REMARK ExemaMOHComedon Sain or Sofware Usas atau TON Lithium Battery ON OFF Switch for Memory and RTC Back Up Defaut OFF sm Table 3 1 4 Functions of connectors switches and modular jacks 33 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM Functions of modular jacks MJ1 MJ4 MJ1 CO C
23. 8221 8231 8291 221 021 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 3 SLT Ring path check Connect a SLT to a SLT port and hook off Line feeding check Call to tke Check the Ring path Ring sound heard R221 R231 RL11 R201 211 1 PT11 and 010 U5 06 Y NO es 158 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 4 SLT Voice path check Check voice signal VIN amp VOUT at 279 part around U2 and U3 Check the circuit around U111 U113 U115 U117 U2 amp U3 Check the circuit around 111 118 MHz FRAMESYNC _ _ normal 02 03 Connectidn 1539 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 4 4 Rx or Tx Fail check the B13 of 2Mhz ok Check the signal source from MBU Check the U1 U2 U3 amp R21 No Check the signal source from MBU Check theU1 U2 U3 amp R22 pin 22 32 of U1 U2 Ue 2Mhz ok Yes check the B14 of Framesync ok Yes Framesync ok check ramesyn U1 U2 U Yes Line feeding check Check the related SICOFI U1 U2 and 03 No 160 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 5 5188 5 5188 5 1 SLT interface circuit 1st port 1 SLT Line feeding voltage 36V check Check the voltage level of VF at L1 to power check Routine Check t
24. E L E 1 8 E RASD SDCSH 5 FASS SDDS3 8 Pt m M Jal Re 378 He CA 0048 FAS E C AS3 cm J OWE FLASH 8 rl gt m 58 WMEU DISP C5 89 24 ECS _EWAITS EWAIT pon PSE L2 PESO emi PESEE B ie 1701 FE Sg S M L PLES S pas m 7 ROSA m t SE peer Figure 3 1 2 System memory assignment oystem manager of CPU provides the four DRAM SDRAM the four External banks the six ROM SRAM Flash banks and etc Each bank is set by corresponding registers and the below table shows system memory assignments for IPLDK 60 system Chip selection Width _SDCSO 16bits SDRAM _ECSO Flash CS _ECS1 VMIU_DSP CS _ECS3 Table 3 1 2 Chip selection signals 18 ipLDK 60 SERVICE MANUAL DIGITAL KEV TELEPHONE SVSTEM The S3C4530A has an Ethernet controller which operates at 10 Mbits per second in half duplex or full duplex mode The Ethernet controllers MAC layer supports media independent interface that supplies the transmit and receive clocks of 2 5MHz at the 10 Mbit s speed The MII is used to for 1 basic port of Ethernet on MBU MJ3 The CPU has two UART blocks that provides two independent asynchronous serial SIO ports UARTO is used to monitor system operation and UART1 is used to communicate with MODEM chipset on the
25. J 1608 R TP ohm 1 16W J 1608 R TP R22 R24 R27 30 R32 ERHY0000466 RES CHIP 10K ohm 1 16W J 1608 R TP ERHY0000434 RES CHIP 330 ohm 1 16W J 1608 R TP 0000466 RES CHIP 10K ohm 1 16W J 1608 R TP 3 104 105 8143 189 190 ERHY0000466 10K ohm 1 16W J 1608 R TP FRHY0000466 10K ohm 1 16W J 1608 R TP R148 149 R152 R158 159 ERHY0000434 RES CHIP RHY0000434 RES CHIP R53 54 R56 R63 R66 R69 ERHY0000466 RES CHIP 244 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM R575 622 R787 789 ERHYO000466 RES CHIP m EXE CNS FNSY9017201 CON SOCKET SOCKET CON SOCKET JE610 A254 650V 50 PIN STRAIGHT 2 54 m A254 JE610 A254 650V 50 PIN STRAIGHT 2 54 m l 50 PIN STRAIGHT 2 54 mm 0810 1X1T 36 F 10P IN 1JACK ANGLE 10 100BASE TX EXTENDED te ESDY0000101 DIP BSM 101A 24V 0 3A 1POLE RAD ED9009 X0001 S 101A 24V 0 3A 1POLE RAD ED9009 X0001 S HERO WSBBO9 FIRMWARE SYSTEM 0x45D2 GS88F 2 a IPLDK 60 PRHB8 RUS 5 8 VOIB oor AO 2 s owe suma __ uw eeen e aser aso _ jiu sear ES a JrmemenmassmmmE U 8599 10 22 KGFS60800 PCBO TSP1 48 PIN PCBO TSOP1 48 PIN s lt LOW VOLTAGE CMOS
26. SV SV Power SLT HOOK RING RLY9 2 9 SLT HOOK16 SLT Hook sense B9 RING RLY16 Ring relay control 2 MHz Clock B10 CN7 Table 3 5 7 Pin assignment of CN7 B LED indications The 10 LEDs mounted in the E1HB8 provide diagnostic information for states of the board KC Rr mt ee mm _ Live AS Awmemr _ Numi Board syne Emer md _ Libres Chants Alameda _ Nomalperatonindeaton Bm _ Linum _ mera _ Lupus imuse muse We Table 3 5 8 LED indications Note a In normal operation of slave clock LED 8 is blinking and LED 9 is turned ON b normal operation of master clock LED 8 is blinking and LED 7 is turned ON If the line has no signal LED 2 4 5 and 7 are turned ON d o If at least one of LED 2 3 4 and 5 is turned ON it says the E1 line has faults physically SO it needs to contact PXs engineer to check E1 line Reference clock extracted from E1 bit streams is selected and LD9 red LED turns on only when E1 line is activated and there isn t any error f 1010 blue LED turns on whenever any internal terminal DKT or SLT is in activated state It is possible to check the state of Ethernet port visually by LEDs
27. These time slots are paired that is there is a transmitting and a receiving time slot for each channel The transmitting time slot is connected to a receiving time slot and a receiving time slot is connected to a transmitting time slot to form a full duplex communication link ipLDK 60 has basic KSU and expansion KSU supports wall mounting and rack mounting It allows any mix of station boards with CO ports The system back plane communications channel is distributed to the expansion KSU as a logical extension of the basic KSU using a 50 pin connector with flat cable System control is performed by a 32 bit microprocessor and governed by software stored in Flash Memory on MBU This Stored Program Control provides a very flexible system in terms of features and functions 2 1 2 Instrument Types ipLDK 60 Digital Key Telephone System is a digital switching instrument providing digital communications all the way to desktop A Digital Instruments The proprietary Digital Key Telephone is a digital voice communication instrument It means that the voice data transmitted from and received to these instruments is in digital form The transmission medium for these instruments is a single pair of copper wires Therefore the full duplex digital voice information the full duplex digital signaling information e g lamp status etc and the 30Vdc power for the instrument are carried through the single pair of wires The 30 is then regulated
28. Tip and Ring signal of CO pass through high impedance resister R1 R2 R11 R12 DETT signal refer to above picture will be changed low value Default value of Call Metering 12kHz or 16kHz is high It means that OFF state of Call Metering 12kHz or 16kHz is high And then the CPU on MBU indicates the Call Metering 12kHz or 16kHz signal 80 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 3 9 Voice over Internet Protocol Interface Module VOIB 3 9 1 General The VOIB provides an Ethernet interface to connect the system to a network that supports Internet Protocol IP and is installed on basic KSU The board transmits and receives voice and data in an IP format to and from the system This board supports Voice over IP VoIP and Fax over IP FoIP The purpose of the board is to take advantage of the applications offered utilizing IP protocol while retaining the reliability of traditional telephone PBX and it requires a unique address known as an IP or TCP IP address This address must be compliant with Internet Assigned Number Authority standards for IP addressing to insure its individuality Until the IP address is entered in programming the VOIB is inactive The board allows VolP and works with both the Internet and Intranet The board adheres to the standards set forth in H 323 Revision 3 To insure Quality of Service QoS it is recommended that this application use a LAN or WAN This board design reduce
29. to buffer 16bits data bus These buffers separate CPU and SDRAM memory with other peripheral devices such as FALC 56 ASIC ACT2 DSP and flash memory and they are controlled by enable signal IO BUS that is generated by AND gate U17 from various chip selection signals Octal buffer 013 converts 3 3V signals to 5V signals D ACT2 and its peripheral circuits The ACT 2 is a custom Mixed Signal ASIC device used to construct a small to medium size digital key telephone system It is designed to support most functions of the digital key telephone system by enhance existing ASIC device ACT 1 The ACT 2 device provides three major functions of GSXD DBID GSL12 as follows And also the ACT 2 has chip DSP and memory to support DTMF CPT and CID detection and generation B switching max switching capacity 12 highways 576 ports PCM gain modification any desired gain value Support channel based dedicated A PCM and mixed PCM No restrictions between PCM conversion Support expansion system highways to increase system switching capacity Support Rx highway based line delay adjustment Internal Tone generation max 64 tones PCM conference 192 summation locations Internal FSK generation max 64 ports DBID block has 36 port interface circuit MPX mode operation Two GSL12 blocks to support 24 ports digital terminal interface circuit Internal 100MHz 16 bit fixed point Zaram DSP and Program Data Memory
30. voltage ow 6 meme PCM bus TX 43 5 5VPowr 88 _ Write Enable Ground A2 Am A2 B9 BOE OutEnable 528 3 3V Power Option Chip Select r3 7 2 MHz Clock for Option 13 20 Framesvnc for Option Data out from 49 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM CNNT Pin Number Pinname Descipon _ A1 POL DETI Polarity Reversal Detection 1 CMU DETI CMU Detection 1 POL DET2 Polarity Reversal Detection 2 CMU DET2 CMU Detection 2 POL DET3 Polarity Reversal Detection 3 CMU DET3 CMU Detection 3 5V 5V power GND Ground CMU_BOARD1 2 CMU Detection 1 amp 2 SMS_IN1 CID Signal path 1 SMS_IN2 CID Signal path 2 SMS_IN3 CID Signal path 3 OPEN Reserved 12 16SET 12 16 select CO1R CO 1 Ring 1 1 CN3 CMU50PR CMU12PR CMUSOPRY 28 CMU12PR CO2T CO 2 Tip CO3R CO 3 Ring _____6 ____ COST CO 3 Tip Table 3 3 1 Pin assignment of CN1 CN2 and for CHB308 The CSB316 has five 5 connectors for installation of CMUSOPR SLU8 and connection with MBU or EMBU CO4 COS coe SLT17 SLT18 SLT19 SLT20 SLT21 SLT22 SLT23 SLT24 SLT9 SLT10 51711 SLT12 SLT13 SLT14 SLT15 SLT16 SLUS CMUSOPR mL To SLT CSB316 To CO line Figure 3 3 12 CSB316 Layout 50 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM Pin assi
31. 9 System Highway and MPX PCM Highway circuits Sheet 4 11 Highway circuit Check waveform of Reference triggering signal is FRAME FRAMEOUT System highway TX RX 150 as for measuring waveforms of system highway i Check TX ISC 8 RX_ISC signal it ri 2 signals Is it right shape On the MBU Yes J MEL TA mm Check the waveform of amp H TXD 8 1 sub frame HDLC D 6B HDLC start ag 01111110 TX 150 gt of CPU U12 Extracted and H TXD Pin 20 De fragmented H RXD Pin 18 H CLK Pin 25 Is it right shape Check the waveform of HDLC start flag 011111 10 PCM highway MPX0 1 No Check signals at counterpart ku AL Devices FALC56 or DSP 190 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 9 1 10 ACT 2 CPU interface circuit Sheet 4 7 CPU interface Check CPU control signals for ACT 2 Chip selection 2 CE RD enable BOE enable _BWBEO1 No Is it right shape Check U19 and U20 Check RC delay R549 and C214 Yes ACT _ BWBEOL _ _EWAIT Check CPU wait signal _EWAIT Check _DTACK signal from ACT 2 1 1 2 Is itright shape and U6 and U20 4 D _ _EWAIT NOTE CPU interface EWAIT External wait signal for CPU access cycle _ Data signal f
32. CHIP LG R1013 R1016 R1537 _ LE 81500 1501 81685 99999999999 ASSEMBLE NOT ASSEMBLE 81502 1503 1503 ERHYOO00430 CHIP 920 VIN M um 1507 R1510 ibas ERHYOO04101 RES CHIP 49 9 1 10W RI508 1500 1509 ERHYOO00343 CHIP IN FI BE eau o R1534 R1552 ERHY0000420 RES CHIP 68 1 10W R1548 R1579 R1591 ERHY0000401 SOP 0000000000 CHIP 1 16W R1558 1554 R1665 0000458 RES CHIP 4 7K 1 16 m ENS 1593 R1647 0000410 RES CHIP 22 1 16 209 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM n R1669 1681 R1699 ERHY0000420 RES CHIP 68 1 10W msemwemws iO ares zt me 121 222200002 20007420 BAG ASSY 00000000000 ASSY IPLDK 60 BKSU STG ZZ ipLDK 60 BKSU Bag Ass y 60 BKSU STG 2 IPLDK 60 BKSU STG ZZ ipLDK 60 BKSU Bag Ass y 60 BKSU Bag Ass y IPLOK 60 EKSU STG ipLDK 60 Rubber Foot Bag ABAZ0005002 BAG ASSY SS y ES MBADOO02406 BAGVIMLOE VINYL 22 27 STATION H S XOXA 00000000000 STATION H S X DX A V1625A HOSW F 1850 EUROPEAN SWPYOO05401 POWER ASSY APPROVED VDE SW40000101 M EASY ASSY 000 101 3600 mm 4 LINE 16 001015 3600 000 101 3600 mm 4 LINE 16 001015 4 LINE 16 01101
33. CN Check the PSU amp Part shortage or Damaged IC Check the voltage level measured at pin 5 of CN7 chen the PSU or Damaged Part YES END 123 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 2 2 3 3V amp 1 8 Power Status p sheet 1 2 7 the voltage level measured at of C142 U38 v level 3 3V YED 1 8 the around circuit ot 038 8 Check 5V Power source Check the status of 1 8V VDD pin 23 49 75 107 158 204 of U8 Check the voltage level measured at pin 2 4 of 050 amp Check 45V Power source v END 2 3 Clock 32 768MHz 32 68MHz For ACT2 Operation Pin 3 of X3 Check amp Replace X3 26 no_ 32 768MHz Check amp Replace U40 sheet 2 7 124 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 2 4 General Purpose Relay circuit sheet 7 7 Relay ON Check the output signal measured at pin 12 of 052 Check the around circuit of 052 YES lt Check the relay contact measured at pin 4 5 of the around circuit of RL8 2 5 Relav circuit sheet 7 7 lt operation Between 5118 During power ON OFF NO Replace rela
34. Check the components are damaged or not Yes Perform Line feeding check Check hook sensing circuit Note 1 U110 R291 R281 C251 R501 R503 146 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM NO Ringing state Check the components pi gt SLT HOOK U110 pint are damaged or not Check a hook sensing Circuit during ringing Ringing state Check the components ni 25 SLT 0110 1 0110 8281 251 2 8221 8231 8291 221 021 147 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 3 SLT Ring path check Connect a SLT to a SLT port and hook off Line feeding check Call to tke Check the Ring path Ring sound heard R221 R231 RL11 R201 211 1 PT11 and 010 U5 06 Y NO es 148 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 4 SLT Voice path check Check voice signal VIN amp VOUT at 279 part around U2 and U3 Check the circuit around U111 U113 U115 U117 U2 amp U3 Check the circuit around 111 118 MHz FRAMESYNC _ _ normal 02 03 Connectidn 149 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 3 5 Rx or Tx Fail check the B13 of 2Mhz ok N z Check the signal source from MBU No Check the U1 U2 U3 amp R21 gt No Check the signal source from MBU Check the
35. E Ls mee omo O KDS226 RTK THAILAND S0T 23 85V 0 1A R TP RS2G D0 214AA SMB 400 V 1 5 A R TP FAST 05 0004501 DIODE SWITCHING SWITCHING EDBY0000601 THAILAND SMD 600V 0 5A R TP n 225 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM n C28 1 288 R20 1 208 99999999999 NOT ASSEMBLE NOT ASSEMBLE 226 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM n R535 ERHY00006 3 RES CHIP 33K 1 10 Ds ws 60 CSB316 STG ZZ ipLDK 60 Bag 70007306 BAG ASSV Ass y CSB316 GMFY0001801 3 MM 6 MM SB41 FZY B KB1023 X GMFYOOO1801 SCREW MACHINE PAN 6 SZ P 001801 3 MM 8 MM SB41 FZY B TB X 8 SZ GTFB0001801 SCREW TITE PAN B IPLDK 60 CHB308 STG SV ipLDK 60 Mount ing MMCY9001101 MOUNTING SCREW M3x28 3 PLDK 60 BKSU BRA WA NORTEL MASTER BOX SPEC MLAZ9045001 LABEL 2 esowswe wmuaem won _ ka 5 5 SLIB8 SAGY9251401 SLIB8 PCB ASSV OPTION IPLOK 60 SLIB8 STG OPTION 1 1 ELFR9001501 l INDUCTOR RADIAL C C 9009 90 uH M R TP ROHS 7061 EDTYOOO7201 DIODE TVS 1 00 20 140 43V 1500W TVS DIODE ENHY0001707 CONNECTOR HEADER HIF3H 50DA 2 5405 50P IN 2 54mm STRAIGHT ENJM9012301 CONN JACK PLUG MODULAR 623PCB4 G8 4 PIN 8 JACK RJT1 227 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM
36. H MVIP bus for world market telecommunication systems The FALC 56 implements all of the standard framing structures for or PCM 30 CEPT 2 048 Mbit s carriers The internal HDLC or CAS controller supports all signaling procedures including signaling frame synchronization synthesis and signaling alarm detection in all framing formats The time slot assignment from the PCM line to the system highway and vice versa is performed without any changes of numbering TSO TSO 1531 TS31 e Monolithic single channel T1 E1 J1 Framer Line Interface Unit and Signaling Controller for Long Haul amp Short Haul applications e Crystal less wander and jitter attenuation compensation to TR62411 Frame alignment synthesis for all standard E1 T1 J1 formats e Includes HDLC LAPD signaling controllers e Real software switchable E1 T1 J1 device by integrated switchable termination resistance 75 120 e Enables hitless switching of parallel transmit lines e Supports programmable system data rates 2048 4096 8192 and 16384kbit s Dual voltage 1 8 V 3 3 V or single voltage 3 3 V power supply 62 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 124 2 1n AA CU DO PSA XL fe 2 ALI YOON 12 XLZ ka HOLE lt Gin Su 2 34 TT Bs qur FALC 56 LS E ORELE ie 04SM RD dH MP PX SCLER IA CLE BM 8 1S2M TEC ay F
37. ICG FIXED POINT DSP TMS320VC5402PGE 100 TQFP 144 PIN 25MHZ HC 49 SM 50 0005801 X TAL 25 MHz PPM 20pF 50ohm SMD 11 4 4 67 3 4 as HERR X5 EXSY0001401 OSCILLATOR 10 MHz KMS 8 3C 10MHZ 50 PPM 15 pF SMO 7 0 5 0 1 7 BMS 873R 8 192MHZ 30PPM pF SMD 7 0 5 0 1 7 3 3V EXSY0019101 OSCILLATOR 8 192 MHz OPER 91000601 TRANSFORMER MATCHING MATCHING 5J1102 16 PINSMD IPA 16 5 IP KIS T1144NL 16 PIN SMO DUAL Y aa nan Am ZCYS51R5 2PAT 01 SMD 0 5A COMMON MODE CHOKE aia SFY0000101 BEAD 5 0000101 4 06 3 052 543 4 06 3 05 2 54 ES er eres C C sim KDS226 RTK THAILAND SOT 23 85V 0 1A R TP Ls e jesmen neweanem wemsrnewsmw CD CD c DO 232 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM C3 053 C137 C167 _ 00259 CAP CERAMIC CHIP 233 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM C175 177 ECCH0000368 CAP CERAMIC CHIP Es ms ewer reson rie 234 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM R100 101 ERHYOO00441 RES CHIP 235 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM R535 ERHY0000975 RES CHIP CE i L FE sess mamanman U maca s saam KDS226 RTK THAILAND SO
38. LINE INTERFACE BOARD 8PORT pp 53 CME IMP D Tr 53 SR 2 BOCK DIAG a i T ERE o3 9 4 9 _ ____ 53 254 4 CONMECIONS 54 3 5 E1HB8 E1R2 DIGITAL TRUNK amp 8 HYBRID 55 92921 General NUT 55 qoi m MM 55 3 9 9 GI editiDeSCIIDIOI Z u uu kaa 56 3 5 4 Connectors Modular jacks and LEDS pp 69 73 73 9 02 VMIJAAFU Block ESG 73 73 r 74 2 0 eec 75 DUAIMODEN UNIT h ra 76 S Ta i GENET Alia is A ie it umu et u ee ee 76 91 2 Block Diagram DescriDEHOR ocius a a ace t 76 CMUSOPR CIMT PR ia ii a ___ _____ 77 3 8 1 CMUSOPR Call Metering 50Hz and Polarity Reversal Detection 77 3 8 2 CMU12PR Call Metering 12KHz and Polarity Reversal Detection Unit 77 weld 78 IFC IE GSS CPO Cm 79 3 9 VOICE OVER INTERNET PROTOCOL INTERFACE 81 S 9 l i e 81 3 9 2 DIOCK MA
39. Line short status Check the voltage level of the signal measured at lead of 21 28 Check the components are damaged or not END Note TOT Od 116 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 1 20 SLT interface circuit 1 port eet 6 770 1 Line feeding voltage 36V check sheet 6 11 Check the Mes level Go to power check Routine Check the voltage level Check the components at PETITA are damaged 1 021 8541 R551 R561 031 R601 R611 R631 1 R501 R511 11 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 2 Hook sensing check sheet 7 10 Connect a SLT toa SLT Port 1 and hook off Check the voltage level of VRD amp VLD NO 1 VRD 16 3V amp VLD 21 6V a Perform Line feeding check Yes Check a hook sensing circuit Note 1 0110 0104 R581 R621 R591 C551 R951 R954 118 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM NO Ringing state Check the components amp 030 028 damaged not Check hook sensing Circuit during ringing Ringing state _ Check components PA amp 030 28 damaged not 1 0110 R581 8621 C551 R591 Roe C524 D21 2091 3 SLT Ring path check Connect a SLT to a SLT port and hook off Line feeding check Call
40. MANUAL DIGITAL KEY TELEPHONE SYSTEM 1 2 3 3V amp 1 8 Power Status OV sheet 3 4 10 lt Check the voltage level measured at pin of C142 near 038 Y level 3 3V Check the around circuit of U38 or C142 and 5 status VES Check the 41 8V power pin gt 23 49 75 107 158 204 of 08 and 0119 and C302 C303 Check the voltage level measured at pin 2 4 of U119 C END k 1 3 Clock Check 10MHz 50MHz 32 768MHz 10MHz 32 768MHz For CPU operation 10MHz and 2 32 768MHz puc Check amp Replace X4 and R218 10MHz sheet 1 10 YES NO Check amp Replace U20 and YES 77 of U1 5OMHz For SDRAM PLD operation sheet 1 3 10 YES Pin 1 of U40 32 768MHz Check amp Replace and R771 R772 TCO FB8 NO Check amp Replace components 32 76WESz sheet 4 10 around U40 and FB8 044 Pin3 components 32 768MHz around U44 TEG END 93 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 1 4 Battery back up circuit for SRAM amp RTC Battery backup circuit U1 is below 3 0V When System power Turn ON the SW2 YEG SW2 OFF Check amp Replace D4 R232 SW2 ON oltage at Pin 11 of U1 is below 2 4V Mhen System power SW2 OFF Check amp Replace battery BAT1 SW2 ON
41. MINIATURE FTR C1GA005 G 5 V 1 A V A 179 ohm C1 7 09 020 C271 ECCH0000369 CAP CERAMIC CHIP 0 1uF 50 00146 CAP TANTAL CHIP 100uF 16V ECCH0000356 CERAMIC CHIP 10nF 50V 0000136 CAP TANTAL CHIP 33uF 10V 0000102 CAP AL ELEC SMD 2 2uF 50 C141 143 0221 228 EGTHOOOO113 CAP TANTAL CHIP 2 2UF 16 0000117 CAP TANTAL CHIP 4 TuF 10 CAP CERAMIC CHIP CAP CERAMIC CHIP CAP TANTAL CHIP 16V 100 pF 50V J NPO TC 1608 R TP 25V 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 219 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 501 506 ECCHO008201 CAP CERAMIC CHIP 220 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM R505 R507 R509 ERHY0000405 RES CHIP 2 em emer pee reme IPLOK 60 CHB308 STG ZZ D 60 CHB308 Bag 20007310 BAG ASSY SS EL ess IPLDK 60 SLUB STG ZZ 5 4 CSB316 RO ces 221 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM EUSY0050801 IC LOW VTG 3 T0 8 LINE DECODER TC74LCX138FT TSSOP 16 PIN R TP IG OGTAL D TYPE FLIP FLOP 3 STATE 9 U 8 U10 U21 EUSY0062001 TC74ACT574FT TSSOP 20 PIN R TP EEC P TUMSUMS U17 U115 U117 EUSVOD37302 18 NJM4556M 501C 8P IN NJMASS6M SOIC SPIN R TP OP AMP DC TO DC CONVERTER CO
42. Power Specification The DSP and Flash memory chips require 3 3V 5 but 5V 5 is need for other chips 3 6 4 Circuit description A DSP and its peripheral circuits The DSP CODEC TMS320VC5402PGE is a versatile multi functional Analog Front End IC featuring the combination of Sigma Delta CODECs DSP Analog muxes and amplifiers with programmable gain having various peripheral interfaces on a single chip All DSP U1 in VMIU AAFU works with main clock 10MHz from oscillator X1 and has host port interface block that is composed of data bus HDO HD7 HCNTL1 2 HBIL HR W HDS1 2 HCS HAS HRDY and HINT signals for command amp event communication with host CPU on the MBU B Decoding circuit The CPU of MBU in IPLDK 60 system generates various chip selection signals with VMIU DSP CS signal FLASH CS and data 2MHz clock and the information of Flash for operation of VMIU Below table shows descriptions of chip selection signals used in VMIU Level buffering is needed because flash memory works with 3 3V and 1 8V power so that buffer 03 OR gate IC 05 and AND gate IC 09 are used to generate signals for controlling flash memory and other signals Chip selection Bus Width _ DSP CS Read write DSPs on VMIU FLASH CS Read write voice data from to flash memory Table 3 6 1 Decoding signals C LEVEL Buffering circuit The DSP Flash memory and some buffers require 3 3 5 so that power regulator U8 prov
43. R681 and C581 withSICOFI SLT VIN1 and SLT VOUT1 nodes are connected to the analog interface ofSICOFI821054 010 IDT U10 provides many functions which are A D conversion of voice signal impedance matching analog amplification attenuation trans hybrid balancing PCM highway interface and etc For more information aboutSICOFI refer to the datasheet ofSICOFI821054 manufactured bvSICOFI illa qe Gili T11 RIRI S fm ma edi FP SL TAIN 297 1u t2 RADI ty aA x L L 0281 F A EF CHI y SLT Figure 3 1 19 SICOFI interface circuit The key devices of the hook sensing part are U30 octal buffer line driver and U110 LM2903 comparator The off hook sense circuit comprises a comparator and octal buffer line driver for detecting the loop current And the 28 ipLDK 60 SERVICE MANUAL DIGITAL KEV TELEPHONE SVSTEM CPU on MBU reads this hook status information through input ports of U30 Off hook sensing process of SLT circuit can be explained as two cases that is when SLT rings or not If the called party doing off hook at the time of no ringing the voltage applied to R621 input pin 3 of comparator goes down to below VLD 21 6VDC and then the SLT signal becomes low If the called party answers the phone at the moment of ringing ring current is getting charged to RC circuit R531 and C521 When the charged voltage of C521 discharges if the voltage is h
44. These internal DBID block in the ACT2 provides the mux demux of the PCM signals to and from the appropriate ISC highway as a time slot assigner 26 ipLDK 60 SERVICE MANUAL DIGITAL KEV TELEPHONE SVSTEM S A 5110 ep FRAMES THC 121 1 hr 38 291 9 pE TX 23 8 SICOFI pal PEB2466H 8 TEB wE pin DIN 3215 7 pour 502 HS 5 E INT 12 He eoo NT 34 779 VIN3 m lt PP RESET 4 ENI vin 8 OH a 503 1 4 S638 SI4 1 EV eii Figure 3 1 15 CO line and PCM highway interface of SICOFI The CPU can read and write the internal registers of SICOFI by control signals that are DIN DOUT and DCLK generated from SICOFI control buffer 029 Loop relays are driven by relay drivers 052 CPU writes control data active high to latch buffers U91 the latched data is routed to input pin of relay driver U52 and then each driving circuit is activated RLY1 3 are enable signals for relays in CO interface circuits and is for power failure transfer PFT relay and RLY CONTACT 182 are for free relay contacts Figure 3 1 16 Loop and PFT relays driver J SLT interface circuit The circuit of each SLT Port is composed of SLT line interface and protection 36V power feeding IDT interface part and hook sensing parts as sho
45. U1 U2 U3 amp R22 Yes eck pin 22 32 of U1 U2 U8 2Mhz ok Yes check the B14 of Framesync ok Yes check 31 of U1 U2 U Framesync ok Yes Line feeding check Check the related SICOFI 01 02 and 03 150 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 4 CSB316 4 CSB316 4 1 CO Dial tone check CO Off hook Yes NO Check the CO line connection Correct the connection amp RLA No Yes Check the CO fusible Resistor or Poly switch Change the Fusible Resistor R101 R106 PT101 PT106 or Poly switch Yes Check the Transformer wire impedance fri Change the transformer 151 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM Check the 011 Q16 Change the transistor Check the U100 U102 Check the components are damaged or not Check the U101 U103 U104 NO Yes Check the components are damaged or not ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 4 2 CO Ring detection check PORT 1 Check the incoming ring path Check the components 1 are damaged or not Can you see ring signal at pin t1 of U100 No 0100 PORT 2 Check the incoming ring path Check the components 2 are damaged Can vou see ring signal at pin 3 of 0100 No Replace the 0100 Note 1 C101 R111 RLA 2011 2012 011 012 8121 8122
46. U100 No Yes Check amp Replace the U100 sensing signal LOOP RING Check the circuit Check the ju current around U100 R431 R451 R452 SLOOP_RING1 Low Check route of ring sensing signal y LOOP RINGH Check the circuit to of U31 pin 2 031 Pin 13 of 028 LOOP RING DET 1 C401 R401 R402 RLA R411 2011 2012 801 011 012 R421 R422 R431 114 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 1 19 Digital Terminal Interface 1st port sheet 8 10 1 AMI signaling check Digital Line Signal Check the positive TX signal measured at pin 180 of U8 5 00 5 5 107 Acqs B High 5 04 sheet 4 11 the circuit around U8 R 28 Check the negative IX signal measured at pinff1 9 of U8 Check the circuit around U8 R 29 Check the Mixed TX RX signal measured at C339 amp C357 Check the circuit around 839 0357 Terminal amp Wiring Status Tek 5 00MS s 31 Acqs UN Digital terminal Tni a senate 15 11 50 115 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 2 DKT interface Line feeding voltage 30V check Check the voltage level of at pin 2 of CN7 Go to power check Routine amp Check
47. UR 32F Figure 3 5 7 ACT 2 control signals The ACT 2 generates several frame sync signals and data clocks to interface various PCM device as shown in the below table MPX FS PCM frame sync for DSP H CLK 512KHz HDLC clock for HDLC channel B of CPU PCM data clock for DSP CLK8M PCM data clock for FALC E1 transceiver FRAME PCM frame sync for FALC E1 transceiver EXP FRAME Frame sync from master ACT 2 on MBU Table 3 5 4 Clock and Frame signals P485 FRAME ga gt FS tImweried Early Frame FRAME QUT FRAME QUT CLK QUITO a DP HLCLKINon inverted BI EHZ CLK OJTI HESS CLK AMi Inverted 2MHz CLE QUT CLESM CLK SM FRAMECILIT gt gt FRAME Normal Frame tna ExT CLE32M FRAME AC EXP FRAME Figure 3 5 8 System clock generation circuit 61 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM E DC DC circuit This circuit converts 5V power to 3 3V and 1 8V powers that are provided to CPU 2 DSP and so on Power regulator U4 generates 1 8V and 07 provides 3 3V ACT 2 and DSP requires 1 8V core voltage 1 215870 3 Cle EE 1 2 77 E Figure 3 5 9 3 3V 1 8V generation circuit F E1 interfacing circuit The FALC 56 Version 2 2 framer and line interface component is designed to fulfill all required interfacing between analog E1 T1 J1 lines and the digital PCM system highway H 100 H 110 or
48. Unit circuit PARA Rees pee gt RING 0158 et lek 054 gt 2 25 2 i gt RING 828 71158 056 a 2 658 2250 894 891 RING IE 200 1 24 25Hz square wave 25Hz Oscillation circuit 106 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 1 25Hz generation circuit 25Hz generation 4 Check the pin 8 of 0121 YES 4 Check the amplitude measured at L2 NO Check the 053 056 884 891 amp Replace abnormal part 10 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 2 Ring signal generation circuit ON OFF Control Signal Check the control signal measured at pin 3 of U75 1 when giving a ring to SLT Waveform depends on Ring cadence NO gt Check the pin 1 of U75 On Ring on time 5V Pin 12 of U93 and circuit around Q8 Off Ring off time 0V YES L _ k 4 Check the control signal measured at collector of 050 or Pin 13 of 063 NO p Check the circuit around U63 Q51 Q50 R8 6 R8 3 YES 108 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM sheet 9 10 Ring signal D 4 Check the waveform measured at pin 4 of T30 NO Check the circuit around Q52 D136 R881 and 180 YES lt Check the waveform measured at secondary circuit Cathode of D137 Ring A
49. connection 6 When connecting the external battery check the polarity of batteries 7 When assembling KSU check the connection of protection parts and earth ground 1 3 System Features Flexible architecture Simplifving system structure Powerful application LAN RS 232C Stable amp Enhanced voice features Simple installation amp efficient system management Iw Remote admin amp software upgrade through LAN connection Remote admin amp software upgrade through PSTN modem 6 Value Added features Distinctive voice mail Quality ADPCM 32 Kbps Basic CID CO amp SLT Function 8 Poly internal MOH 13 Music sources ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 1 4 System Specifications 1 4 1 General specifications ep ARMSTDMicoreG2bt SOME Switching Device Custom Mixed Signal ASIC Device Memory Backup Duration ww PSU AC Voltage Input 100 230 10 Volt AC 47 63Hz AC Input Fuse 2A 250Volt AC External Relay Music Source input ExemaPsgnpPot Frequency Deviation DTMF Dialing Frequency Deviation Dimension 339mm W x 288mm H x 85mm D LOO l xPM Weight ee ooo VODU VOIB LAN Interface 10 100 Base T Ethernet IEEE 802 3 10 100 Mbps Auto Negotiation Half Duplex Full Duplex Auto Negotiation ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE
50. control DIP switch read LED control and MPX bus control 20 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM HF miu REND pde stem 43 EEI TOS A 0 27 a B r3 d i 4 1 ri p T 1 T rr 12 t LL HE L EPH31234TE188 1H id DOR itl e 21 DLP SULT H i NE CS k 7 ds maran s PEE Tua Figure 3 1 6 PDL2 Circuit x The 2Kbits EEPROM U25 stores system Serial information and Software function key for using and is controlled by general I O signals from CPU PSCLK and PSDATA F Level buffer The CPU and system memory such as SDRAM flash memory and SRAM work with 3 3V power supply and other peripheral devices operate with 5V power Bi directional data buffer U33 and U91 U93 converts 3 3V data bus from CPU to 5V data bus and vice versa Buffers U34 U35 convert 3 3V address bus to 5 bus and various control signals G RIC The MBU incorporates a Real Time Clock RTC72421B U24 which maintains the date and time for the system Information from the RTC is useful for the date and time display at keyset call record and alarm record etc The RAM Battery Back up cir
51. line interface circuit Data transformer T1 protects the secondary circuits from high voltage surge Hm 0 Table 3 9 3 VOIP Specifications F Power circuit There are five power sources that is 3 3V 1 8V 1 8V A 2 5V and 1 2V in the VOIB The CPU its peripheral circuit DSP and memory devices and some logic chips require 3 3V power 3 3V that is generated 012 The DSP needs dual power supply of 1 8V for core and 3 3 for its peripheral blocks and power 86 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM regulator U114 provides DSP with 1 8V 2 5V power for Physical Layer Tranceiver KSZ8721 is supplied by itself In addition 1 2 for FPGA is generated by 055 zr Deui C188 1Bu Tu 2231 224 Figure 3 9 8 Power circuit 3 9 4 Meaning of Connectors Switches and LEDs There are various kinds of connectors switches and LEDs in the VOIB Figure 3 9 9 VOIB Lavout shows the configuration of VOIB and the location of connectors switches and LEDs VOIU SW 1 System reset button The Default of the pole1 3 84 SW2 is off 1234 09 LD10 LD11 101 1 2 LD3 1 4 LD5 LD6 LD7 LD8 B H H H H B B B B B B LAN port Figure 3 9 9 VOIB Layout 87 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM Switch Connector Functions Remark _ SW1 VOIB Reset Switch for CPU S32510A SW2 Pole1 Boot mode selection others reserved De
52. measured at pin of 0120 when giving a ring to SLT Waveform depends on Ring cadence NO Check 0120 and circuit On Ring on time 5V 8 pin 77 of 0120 Off Ring off time VES lt Check the control signal measured at collector of 050 Or Pinf13 of U63 NO p Check the circuit around U63 Q50 Q51 R8 6 R8 3 YES 128 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 4 Ring signal 2 Check the waveform measured at pin 4 of T30 YES 4 the circuit around 052 0136 R881 and 180 Check the waveform measured at secondary circuit Cathode of D137 Ring Anode of D138 Ring the Darlington circuit TTTT m NO D137 0138 953 056 lum NN YES lt ms Check the signal Ring deeem ene B measured at L2 4 20 04 M20 0ms Chi 7 70 8V 27 jul 2006 10 08 18 NO Check RC filtering circuit C820 L2 and etc YES 4 Freq 24 990 Hz I C1 RMS 79 1V Ring signal 25Hz 50Vrms 129 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 2 8 CO interface circuit sheet 3 7 1 CO Dial tone check 1 st Port oeizure the CO line line connection Correct the connection 8 Check RLA Good No Connection Yes
53. one bridge diode BD1 between the Tip with Ring input and Fusible resistor 101 R102 for high power current and arrestor for limitation high voltage The one relav circuit provide suppression of transients and input to the Ring Detection circuit The Ring signal passes through C101 R111 and C501 And then finally Ring signal arrive at U100 1 for detection When the Ring comes in CHB308 or CSB316 RL4 2 is open If you want to connect CO RL4 2 will be short to RING line So DC loop is connected through Q12 U100 1 is used for DC loop and Incoming Ring detection The resistor R141 and Q12 are used for DC loop current limit according to DC voltage 3421 IN 171 3 H VINI C171 Li 2172 SEE RIEZ 150 gille 172 L _ 1 Figure3 3 5 CODEC interface circuit Transformer T1 transfers two wire voice signals to one way voice signal Moreover the function of Transformer is the isolation of the system digital side from CO line analog side The incoming voice signal pass through OP AMP which is amplified signal and prevented hauling with R172 C151 The outgoing voice signal pass through C172 and R162 to transformer Impedance matching is incorporated on the secondary winding of the audio transformer through appropriate RC networks with SICOFI U1 CO VIN1and CO VOUT 1 nodes are connected to the analog interface of SICOFI 01 SICOFI U1 provides many functions which are A D conversion of voi
54. optional MODEM unit MODU that supports 33Kbps transmission rate Both support full MODEM control signals In addition the CPU provides several external ports that are used to access EEPROM on the MBU to read some functional signals and to output control signals such as reset signal Local oscillator X4 on MBU generates 10MHz clock and provides it to CPU through Spread Spectrum clock generator U20 PLL block of CPU multiplies it by 5 to generate 50MHz clock SDCLK for system operation CLOCK INPUTCTOMHz 2218 tt SY 33 mA UTE Ci LL 8 Tu gt Figure 3 1 3 CPU Clock generation B Reset circuit The Reset circuit generates reset pulses to CPU RESET flash memorv RESET SRAM 3 3V real time clock 5V DET and peripheral boards PP RST These reset signals are generated when system is ON or reset switch SW2 is pressed by watch dog reset of CPU Power ON reset operates when 5 falls down to 4 65 in voltage detection IC U23 The output of voltage detection IC and WDOG reset signal are connected to PLD U120 WDOG reset signal is generated when CPU can t clear the counter 085 by WATCH periodically due to certain abnormal operation 5V DET and 3 3V DET signals are generated in case of pressing reset switch SW3 system power ON and power instability to prevent SRAM and RTC data from being written with garbag
55. pin 180 of U8 5 00 5 5 107 Acqs B High 5 04 sheet 2 7 Check the circuit around U8 Check the negative IX signal measured at pinff1 9 of U8 Check the circuit around U8 Check the Mixed TX RX signal measured at C339 Check the circuit around C339 C357 Check DKT Terminal amp Wiring Status 31 Acqs UN Tek 5 00MS s Digital terminal Tni a senate 15 11 50 133 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 2 Interface Line feeding voltage 30V check Check the voltage level of at pin 2 of CN7 Go to power check Routine Check Line short status Check the voltage level of the signal measured at one lead of PT21 Check the components are damaged or not END Note TOT Od 134 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 2 10 SLT interface circuit 15 port sheet 4 5 7 1 Line feeding voltage 36V check Check the a level of Go to power check Routine Check the voltage level between Ring and TIP at 1 11 Check the components are damaged or not END Note 1 021 R541 R551 R561 031 R601 R611 R631 RL11 R501 R511 135 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 2 Hook sensing check sheet 4 5 7 C
56. reverse function But 53 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM the function of PCM data switching exist in ACT2 IC on IC 06 is used for address decoding 07 is used for control of SICOFI IC U10 and U5 are used for ring relay IC U11 is used for off hook signal detection B Analog signal part Analog signal part of SLIB8 consists of ring detection circuit and Codec interface circuit Circuit is the same of CHB308 and CSB316 SLT analog signal part 3 4 4 Meaning of Connectors The CHB308 has three 3 connectors for installation of CMUSOPR or CMU12 16PR and connection with MBU or 00111 SLT9 51710 51711 51712 50113 5114 51115 51116 SLIB8 kus To SLT Figure 3 4 2 SLIB8 Layout Pin assiqnments of CN1 CN2 and CN3 for CSB316 Pin Number Pin name Description Number Pin Name Description 1 1 eg B4 PFT_CTL PFT Relay Control voltage a SV 5VPowr 86 MPX RX __ PCM bus RX pow ome PCM bus TX aber FEI A23 iss sad 16 A7 A8 Option Chip Select A13 A20 2000 0007 2 MHz Clock A22 o4 ipLDK 60 SERVICE MANUAL DIGITAL KEV TELEPHONE SVSTEM 3 5 E1HB8 E1R2 digital trunk 4 8 Hybrid Board 3 5 1 General The E1HB8 E1R2 Digital trunk 4 8 Hybrid Board is a option board to interface IPLDK 60 system to digital trunk E1 line which transmits receives the information of 30 subscriber lines bv multiplexing it to digital str
57. the connection RL4 Check the CO fusible Resistor or Poly switch Change the Fusible Resistor R101 R106 PT101 PT106 or Poly switch Yes Check the Transformer wire impedance T1 T3 Change the transformer 139 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM Check the Q11 Q16 Change the transistor Check the U100 U102 Check the components are damaged or not Check the U101 U103 U104 Yes Check the components are damaged or not 140 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 3 2 CO Ring detection check PORT 1 Check the incoming ring path Check the components 1 are damaged or not Can you see ring signal at pin t1 of U100 No 0100 PORT 2 Check the incoming ring path Check the components 2 are damaged Can vou see ring signal at pin 3 of 0100 No Replace the 0100 Note 1 C101 R111 RLA 2011 2012 011 012 8121 8122 2 C102 8113 85 BD2 2013 2014 013 014 R123 R124 141 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM PORT 3 Check the incoming ring path Check the components 1 are damaged or not Can you see ring signal at pin l of U102 No Yes Replace the U102 Note C103 R115 2015 2016 Q15 Q16 R125 R126 142 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 3
58. the four CO line interface circuits Each port is identical The CO line Tip and Ring connect to the modular jack MJ1 on the MBU Basic line protection circuitry consists of 3 pole arrestor AR1 between TIP and Ring This device provides protection for the loop detect current sink circuitry 2591 17006 eV U 2111 3 BV 2011 foggy amie 3 gt m a T FI gt Figure 3 1 12 CO Line Interface and protection circuit The loop seizure pulse dial relav is under the control of the output data of the Loop relav control buffer U91 These control data are sent to relay driver 052 to activate deactivate the Loop Pulse dial relay RL1 for the port 1 When closed the relay contacts complete the circuit to the remainder of the CO interface circuit The Loop detect current sink circuit diode bridge BD1 maintains proper voltage polarity Voltage limit is provided by the TVS D11 that protects the current sink circuit of transistors Q11 amp Q12 resistors and capacitor Base drive for Q11 is derived from the CO loop to the series RC circuit of RA41 and C421 and is limited by current sensing circuits Q12 R421 and 422 as much as less than 60mA loop current Loop current and ring is detected by the same circuit that is composed of the resistor and opto isolator R431 and U100 The output of the opto isolator is connected to the input pin 2 LOOP RING1 of 031 and the dat
59. to the SLT No Check the Ring path Ring sound heard R521 RL11 R501 R511 and U93 U88 U28 for Ring relay control Ring Generation Circuit 119 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 4 SLT Voice path check Check voice signal VIN amp VOUT at 279 part around U9 Check the circuit around U111 010 Check U10 U1 1 2MCLK FRAMESYNC 8 ACT2 U8 U51 U86 MPXB_TX MPX_RX R776 777 R710 711 at 010 011 normal 120 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 1 21 2 5V Voltage generation check Check the voltage level of the signal measured at Check the components Pin 13 47 of 030 U30 lt gt YES 1 22 MII Clock 25Mhz generation Check Check the MII Tx Rx Clock Pinf10 15 of U30 Check the components U30 FB30 FB31 R1643 R1644 lt gt YES 121 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 1 23 Component check Check the LED of MJ3 after LAN connecting 1 YELLOW always amp 130 2 GREEN finally blinking after end of MBU initialization 122 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 2 EMBU 2 EMBU 2 1 Power check from PSU VO 30V 45V 5V VO 30V Check the voltage level measured at pin 2 of CN Check the PSU amp Part shortage or Damaged IC Check the voltage level measured at pin 3 4 of
60. various connectors for optional CO amp extension boards and function boards as well as basic CO amp Extension interface circuits A CPU amp System Memory The CPU S3C4530A is 32bit RISC controller It is manufactured using ARM7TDMI core designed by advanced RISC machine Ltd so it has integrated micro processor and peripheral circuits which can be used for various applications It is especially good for communication and networking system consists of system manager block 2 SCC controllers 2 UART channels 2 channel 2 32bit timers 18 general input output port interrupt controller DRAM SRAM controller ROM controller and flash memory controller It has 8Kbyte cache Ethernet controller too S3C4530A operates at 50MHz clock speed internally Flash memory U2 amp U3 operates at 70 access time CPU manipulates programmable register so that it can read and write data There is a code in flash memory so CPU can control system administration and call processing with the 17 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM code Following table shows the memory size SRAM 2Mbit 1Mbyte SDRAM 128Mbit 16Mbyte Table 3 1 1 Memory size Data which are stored in SRAM 06 U7 can be preserved without loss even though system is power off by the battery for memory backup SRAM backup circuit part consists of long time lithium battery voltage detector and switch SW2 for connection with backup battery SDCS
61. which is not feasible for less cost system VOIB will require two wait state for program memory Flash memory and data memory 3C2510A has a lot of programmable internal I O registers which gives great flexible features however requires attention for software to program internal registers correctly _____ pevicesize AccessTime Size Flash memory 2M x 16bits 4M Bytes SDRAM 4M x 32bits 16M Bytes NAND flash memory 32M x 8bits 32M Bytes Table 3 9 1 Memory size 82 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM Memory controller consists of Ext Bank controller and SDRAM controller Ext Bank controller supports ROM SRAM and Flash memory SDRAM controller support SDRAM Each bank is set by corresponding registers and the below table shows system memory assignments for VOIB Reserved ACT II U7 Table 3 9 2 Chip selection signal Address and data bus are buffered by 166 driver 74LVC16244 U5 and U6 and 16bits bi directional driver 74LVC16245 U8 to increase fan out capacity UARTO is for RS232C serial communication to trace the state of CPU operation in development stage and supports 9600bps to 110520bps A HDLC controller is implemented in FPGA with VHDL coding to communicate between main CPU on and local micro controller through HDLC port of Programmable ports are used for flash memory control board detect watch dog DSP reset interrupt source and so on The two
62. 0 2 rere ie a rra fs ee one een ABEZ9066302 BOX ASSY IPLOK 60 SLU8 STG ZZ 5 6 E1HB8 SAGY9250801 E1HB8 PCB E1HBB POB ASSV OPTION OPTION IPLOK 60 E1HBB STG OPTION 1 0 60 E1HB8 STG OPTION 1 0 FQD EXSTOO00501 32 68MHz 32 68MHZ 30PPM 15pF RAD 20 13 06 5 1 S ESDY0000103 SNDPP DIP KSD42H 24V 0 3M APOLE RAD 24V 0 3A ija C ENHYOOO 1 707 CONNEGTOR HEADER HEADER HIFSH SODA 2 540SA 50PIN 2 54nm STRAIGHT 50DA 2 5405 50P IN 2 54mm STRAIGHT a 087 26 26 e 118 08 30 30 eee ENJMOO02 101 CONN JACK PLUG MODULAR MODULAR 2 2 406549 4 8PIN JACK 1 1 RJ 45 ASSY WITH LED 4 8PIN 1JACK 1 1 RJ 45 ASSY WITH LED ocr E rc memmessenaio 3 e mama finan sg 231 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM EUSY0035202 IC LOGIC MC 4HC405 1ADR2G SOIC 16 PIN PB FREE aun aie Ls fm seme Ls m n icons IC D TYPE FLIP FLOP 3 STATE 32 037 EUSY0062001 OUTPUT TC74ACTS 4FT TSSOP 20 PIN EUSYO120501 IC BOOT SECTOR FLASH MEMORY S29ALO32D90TF 1030 TSOP 48 PIN BK Uu EUCA9002801 IC ASIC ACT 2 0 2 MQFP 240 PIN ETC a ju FUSY0052001 IGFIXED POINTOSP DSP
63. 03 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 3 ZD11 16 7021 26 EDNY0001802 DIODE ZENER BZX84C3V9LT1G S0T 23 3 9 V 35 W R TP PB FREE KDS226 RTK THAILAND SOT 23 85V 0 1A A TP KDS226 RTK THAILAND SOT 23 85V 0 1A R TP RS2G D0 2 14AA SMB 400 V 1 5 A R TP FAST SWITCHING EDBY0000601 THAILAND SMD 600V 0 5A R TP 204 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM n 0204 205 000257 CAP CERAMIC CHIP 6 8nF 5OV 205 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM n C692 C801 C804 C806 ECCH0000369 CAP CERAMIC CHIP 0 50V 206 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM n R168 R196 R215 R283 99999999999 NOT ASSEMBLE NOT ASSEMBLE 207 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM n R494 R496 R641 647 ERHYOO00466 RES CHIP 10K 1 16W Ls res oe _ Ds me RB06 R851 856 R851 856 ERHYOO00458 CHIP 4 7K KW 2 0 0 R981 R1006 n 0000466 RES CHIP 1 16W RB31 AB33 AB35 R833 R835 ERHYO000496 SOP 0000000000 CHIP 330K KW LL F E 208 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM n R881 ERHYOOO 1605 RES CHIP 100 1 2W ln ERHYO000437 RESCH CHIP OT q ENML 1011 81014 0000466 RES CHIP 1 16 1015 3 1012 81504 1505 R1504 1505 ERHYOO00445 SOP
64. 12PR CN1 From BKSU CN7 PSU connection uim gt i tie A 2 l F 1 a gt f i 5 0 gi we U V MN E A po LN a Dna eS EMBU FIGURE 3 2 2 EMBU NOTE When AC Power was failed the last SLT port on EMBU will be connected to automatically Even though the EKSU power is turned off while both svstems BKSU and EKSU are working properly the BKSU will restart automatically 40 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM The EMBU is installed in the KSU and provides various kinds of connectors and RJ11 modular jacks for the connection of peripheral boards and miscellaneous functions refer to Figure 3 2 3 and Table D i A L LI LI H L I f E 4 To CO line To DKT or SLT FIGURE 3 2 3 EMBU CONNECTION PORTS CONNECTOR MODULAR JACK SWITCH FUNCTIONS LSWTCHCONMECTOR FUNCTONS REMARK LED INDICATIONS RED NNN LD1 Blue Periodic Toggle ON 300msec OFF 300msec 41 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 3 2 3 1 Modular Jack MJ1 MJ3 Pin Assignment EMBU MJ1 CO EMBU MJ1 1 2 3 CONNECTOR PIN SIGNAL NAME NOTE When installing the or SLT on Hybrid Ports MJ2 1 2 3 4 5 6 7 8 keep the above pin assignment Otherwise the DKT or SLT will not operate normally T
65. 2 C102 8113 85 BD2 2013 2014 013 014 R123 R124 153 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM PORT 3 Check the incoming ring path Check the components 1 are damaged or not Can you see ring signal at pin l of U102 No Yes Replace the U102 Note C103 R115 2015 2016 Q15 Q16 R125 R126 154 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 4 3 SLT interface circuit 1st port 1 SLT Line feeding voltage 36V check Check the voltage level of VF at L1 to power check Routine Check the voltage level between Ring and at PT1 PT11 Check the components are damaged or not Note 1 021 C241 R251 8261 031 8301 8311 8331 RL11 R201 R21 1 155 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 2 Hook sensing check Connect a SLT to a SLT Port 1 and hook off Dial tone heard Yes NO Check the voltage level of VLD at R501 Check the components are damaged or not Yes Perform feeding check Check a hook sensing circuit Note 1 U110 R291 R281 C251 R501 R503 196 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM NO Ringing state Check the components LT HOOK U110 pin are damaged or not Check a hook sensing Circuit during ringing Ringing state Check the components ni 25 SLT 0110 1 0110 8281 251 2
66. 2 No Yes Check amp replace X2 U46 R246 32 68Mhz Yes No Check amp replace X5 U23 R342 and R343 20Mhz Yes No 1 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 8 5 ACT II check lt 120 of U7 32 768 2 Check clock i 4 of U7 3 3V N 1225 of U7 1 8 Check power 5 of U48 FRAME Check MBU FRAME Check U48 R294 119 of U7 FRAME E Y 37 of U7 FRAME Replace U7 41 of U7 2MHz Replace U7 42 of U7 512KHz Replace U7 Check CPU Check CPU _WE01 OE is OK Check CPU ADDRESS DATA OK Check CPU gt lt MPX channel is OK X RX Highway are Replace U7 UBI End Check MBU Highway ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SVSTEM 9 ETHB PRHBS 9 E1HB PRHBS Sheet means page number of circuit diagram 9 1 E1THBS PRHBS E1R2 8 8 Hybrid interface Board 9 1 1 Power check from MBU VO 30V 5V 5V Sheet 5 7 VO 30V lt Check the voltage level measured at pin 26 or B1 of CN5 Check the PSU Check the voltage level measured at pin 27 B2 of CN5 NO Check the PSU Check the voltage level measured at pin 3 OT CN5 A Check the PSU 179 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 9 1 2 3 3V Power Status 3 9V lt Sheet 4 7 Check the voltaoe level me
67. 3 Digital Terminal Interface 1st port 1 AMI signaling check Check the components are damaged or not Check the signal measured at 2 of each of T21 Check the MBU if they have no damage No AMI signal valid Nu Yes 5 00 5 5 31 Acqs UE aswa e 40mV TE E areca ape soy 15 11 50 1 21 T28 143 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 2 Interface Line feeding voltage 30V check Check the voltage level of the signal measured Check the connection at pin Al B1 of between CHB308 and MBU Check the voltage level of the signal measured at one lead of Check the components each of PT21 are damaged or not Note 1 PT21 PT28 T21 T28 C541 C548 C551 C558 C561 C568 144 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 3 4 SLT interface circuit 1st port 1 SLT Line feeding voltage 36V check Check the voltage level of VF at L1 to power check Routine Check the voltage level between Ring and at PT1 PT11 Check the components are damaged or not Note 1 021 C241 R251 8261 031 8301 8311 8331 RL11 R201 R211 145 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 2 Hook sensing check Connecta SLT to a SLT Port 1 and hook off Yes Dial tone heard NO Check the voltage level of VLD at R501
68. 5 as fer cere mar rc T me mem wes msn y 1 60001801 SCREW MACHINE PAN QMFYOOO1801 3 MM 6 MI SBA1 FZY 1023 X 6 i ho TU 210 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM MI rn BG HL esses Fi Fal 1 87980002001 SCREW TITE PAN B GTFBOO02001 3MM 10MM 5841 27 TB X10 SZ P 1 009000301 SCREW MACHINE FLAT GMDY9000301 THAILAND 3mm 10mm 5841 27 M3x 10 eres II 7 pesemsw oeomw SOO Go KO iron omo TG WAI SOM cora Cow 7 ri oes dT _ s ipana Per 5 2 EKSU i FT OOOO Co e KO O O Hsin Loner Oy 121 LT 211 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 0002601 CONNECTOR HEADER JE118 A8G 10 10PIN 2 54mm STRAIGHT GOLD GTFB0002001 3 10 MM SB41 FZV B 4 TB X10 SZ 22 GTFBO002001 SCREW TAP TITE PAN cer ena o fe faw ese OOOO O EPM3128ATC100 10 TQFP 100 PIN PLD 192 MHZ CLOCK 250MHZ IC DC TO DG CONVERTER CO
69. 68 5 0004001 TRANSFORMER MATCHING SIMVOOO4001 6 PIN DIP 2 2 21 28900 1501 C C 90UH 90 uH M R TP ROHS EDTY0007201 1 5KE43A D0 201AD 43 V 1500 W R TP 0100 SEAY0000301 T83 A350X 350 V RAD SETY0000501 TR250 120T R1 8 0 5 0 125 PTC ohm RAD ENSY9017201 1 610 254 050 50 PIN STRAIGHT 2 54 mm 2 ene 2 MJ gt 0001507 CONNECTOR HEADER JE117 A25G 06 6 PIN 2 54 mm STRAIGHT ENHYOO01606 CONNECTOR HEADER JE118 A8G 20 20PIN 2 54mm STRAIGHT AR 623G3 S2 GY30 2 JACK PCB d 1 ENJMO000101 CONN JACK PLUG MODULAR MOUNT UL AU50 Ez jw ENJM9012301 AR 67368 S4 BK30 4 PIN 8 JACK RJ11 EUSYOO 16901 PEB2466 H QFP 64P IN BK SICOFI 4 IC TR ARRAY KI065003AF SOIC 16P IN R TP IC D TYPE FLIP FLOP 3 STATE m U 8 U10 EUSY0062001 TC74ACT574FT TSSOP 20 PIN R TP 218 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM Level Descr ipt ion Specification 021 28 041 48 051 EDSYOO03001 DIODE SWITCHING 5226 THAILAND SOT 23 85V 0 1A R TP 2528 00 214 400 V 1 5 05 0004501 DIODE SWI TCHING SWITCHING 01 3 011 18 0000601 DIODE BRIDGE EDBY0000601 THAILAND SMD 600V 0 5A R TP 1o 420 8 DIODE LED CHIP HT 170NB Blue THERMISTOR PSR21083B 2 PTC RAD 09705 RELAY DC G6K 2F Y TR DC4 5V 4 5 V A V A ohm 2 RELAY
70. 7401 IC Free C MC74VHC125DT TSSOP 14PIN QUAD BUS BUFFER WITH 3 STATE 9 3 3 3 3 3 243 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 3 R170 172 R175 R178 186 SFBH0001202 FILTER BEAD CHIP HB 1M1608 800JT 80 ohm 1608 FB8 FB14 16 FB70 71 SFBHO001301 FILTER BEAD CHIP 1060362218220 ohm 1608 R85 R361 R560 R786 SFBHO001301 FILTER BEAD CHIP L10603G221R 220 ohm 1608 025 26 R33 USBLC6 48C6 507 23 61 5 V 300 W R TP LOW CAPACITANCE TVS 559 EDTY0008001 DIODE TVS DIODE ARRAY Ls m emas et C1 C5 C11 C15 C19 20 ECCHO000272 0 1 uF 25V 2 V5V HD 1608 R TP ECCH0000272 0 1 uF 25V Z Y5V HD 1608 R TP ECCH0000272 0 1 uF 25V Z Y5V HD 1608 R TP C98 0101 102 C110 112 00272 CERAMIC CHIP 0 1 uF 25V Z Y5V HD 1608 R TP ECCH0000272 0 1 uF 25V Z Y5V HD 1608 R TP 000272 0 1 uF 25V Z Y5V HD 1608 R TP C146 147 0149 C154 155 00272 0 1 uF 25V Z Y5V HD 1608 R TP 3 ECCH0000272 0 1 uF 25V Z Y5V HD 1608 R TP EDSY0003001 KDS226 RTK THAILAND S0T 23 85V 0 1A R TP FRHY0000401 0 ohm 1 16W J 1608 R TP FRHY0000401 0 ohm 1 16W J 1608 R TP ERHVO000423 RES CHIP 82 ohm 1 16W J 1608 R TP 0000423 RES CHIP 3 3 82 ohm 1 16W J 1608 R TP 330 ohm 1 16W J 1608 R TP R455 R459 R471 ERHY0000401 RES CHIP 0 ohm 1 16W J 1608 R TP R161 R294 297 R413 R483 R566 571 330 ohm 1 16W
71. 8 The data transmission ACK signal DTACK generated from ACT2 is routed to the wait signal of CPU after NAND logical computation 22 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM TX BKSU MP 5 T DXX 21 B Figure 3 1 8 highwax time slots assignment The oscillator on MBU generates 32 768 2 clock and provides it to ACT2 through Spread Spectrum clock generator U40 for EMI reduction ACT2 generates various clocks 2MHz and 8KHz needed for system operation from system reference clock CLK32M An internal 32MHz of X3 or an FRAMEOUT to EMBU is provided to PLL block of ACT2 CLOCK INPUTGS2 T68MHz 33 Y c a 2 772 48 FSTBIBIB _ 305 VDC OUT XIN VDD 1y l lu GND e a TE FsouT 8 32 TES Hz Cans B Bu 3 3K 33 gt CLE SEM Figure 3 1 9 ACT2 Clock generation 23 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 2MHz VMU 2MHz X ProgrammableClockOutforVMIU akm 32MHz 27 00 EXPFRAME Frame Sync for Expansion KSU EMBU Frame Sync for DSP U1 on the VMIU AAFU Frame Sync for CODEC U3 on the MODU _____ FS 8KHz Frame Sync for SICOFI and IDT on the MBU EMBU CHB3OS CSB316 Table 3 1 3 Clock and Frame signals
72. ACT 2 in E1HB operates in slave mode and one in MBU operates in mater mode so EXP FRAME signal is from master ACT 2 on the MBU to synchronize two devices Glue logic that is composed of U6 019 U20 implements control signals to interface CPU with ACT 2 ACT 2 requires read write signal R W to go to low before chip selection signal CE is activated and the data transmission ACK signal DTACK generated from ACT 2 is routed to the wait signal of CPU after below logical computation FS frame for bus 100 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15116 17 18 19 20 21 22 23 24 25 26 27 28 29 30 311 _ _ 15 Voice channels B channels 15 Voice channels B channels Multiplexing PCM bus0 32 time slots per frame TSO FAS NFAS TS16 MFAS ABCD CAS signaling TS1 TS15 TS17 TS31 B channels 30 Voice channels B channels Multiplexing PCM bust 32 time slots per frame TS0 TS29 B channels for DSP that decodes encodes MFC R2 tones Figure 3 5 6 MPX PCM highway time slots assignment 60 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 3 54 lu y 470 10028 5 DTACK e ei 4428 2 ACT2 3 S meer 4 HRDY gt AUT2 o From FI BOE gt _BWBEA1 TC74LCx32F 2 052 Fron TENUIS ed WBEBD BIS RSI 12 MWBEOM _WBE1 gt 33 TCTAL
73. ANUAL DIGITAL KEY TELEPHONE SYSTEM Reference triggering signal is FRAME FRAMEOUT as for measuring CLKOUT and FRAMEOUT signals CLKOUT H CLK HDLC clock CLK2M 2 048MHz PCM clock CLK8M 8 192MHz PCM clock e FRAMEOUT 5 125 5 PCM frame CLK 32M Sheet 4 7 Check the frequency measured at pin120 of US3A ACT2 NO licia SELL RON Check PLL circuit PE EMI YES m CLK8M PCM data clock for FALC 56 4 Check the frequency measured at 55 NO Check FB10 and R557 Replace damaged part YES CLK2MHz PCM data clock for DSP Check the frequency measured at R565 Check the FB11and R565 Replace damaged part 250M5 5 170 Acqs itm ca da ly Freq 1 2 0483MH2 NEXT PAGE 22 Nov 2006 13 25 31 188 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM H_CLK HDLC clock for CPU HDLC port Sheet 4 7 Check the frequency measured at R1029 Check the FB19 and U5 FRAME gt PCM Frame for 56 Check the frequency ALI at FB9 Check the around circuit of 034 YES MPX FS Frame for DSP Sheet 4 7 Check the frequency measured at R485 NO Check the R485 and U34 BKHz frame DSP chip U35 Sheet 6 7 YES End 189 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 9 1
74. CN2 CN3 CN4 and CN5 for CSB316 Including 5108 52 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 3 4 5188 Single Line Interface Board 8Port 3 4 1 General The SLIB8 8 Single Line Interface 85115 Board provides an analog interface function of the system The PCB of this board is exactly the same as it of CSB316 So if there is any problem of SLIB8 please refer to the CSB316 part This board can be inserted in connector CN2 on the MBU or EMBU 3 4 2 Block Diagram Block Diagram of ipI AK dh A 41 L5 DR BE DOUT 3 i MEXE EX gt E mmo T E SLT WOUTL RING m OTT SLT VIN tim _ CS SLT WO 1 SLT VINI DD SLT TOTT3 SLT INA SLT W UT4 SLTRLY CTL O 74 OPTION SLT HO SLT VOTTS SLT RLY CTL 1H SLT H E DET ka mate MLC BM E 9 ta 8 ELT WINS SLT VOTT SLT WIN SLT HOQEl Ir vor ELT VINE ELT VIN SLI W UT SLT SLT HOOK 196 mio 114 116 VLD RING m MTM s n Figure 3 4 1 Block diagram of SLIB8 3 4 3 Circuit description A Digital signal part Digital signal part of SLBI8 boards consist of SICOFI 02 U3 for A D conversion voice signal and Address decoding parts Relay control parts SICOFI U2 U3 is IC which convert voice into digital PCM data and
75. EPHONE SYSTEM SECTION 1 General Description This manual is intended to provide a full understanding of the architecture operation and circuits employed in LG NORTEL s Digital Key Telephone system ipLDK 60 is intended for use as an aid in training installation and maintenance personnel Also in conjunction with circuit schematics this document is intended for use in support of component level repair by authorized LG NORTEL repair facilities The ipLDK 60 is a fully digital switching system which is intended for small or medium sized business office The ipLDK 60 system incorporates state of the art digital technology for command processing and voice switching utilizing a Pulse Code Modulation Time Division Multiplexing PCM TDM distributed switching matrix The system supports A law voice encoding rule based on the requirements of local regulations The ipLDK 60 system achieves a high level flexibility by 1 employing three kinds of option boards and 2 providing expansion system The KSU of ipLDK 60 is a wall mounted cabinet that houses the MBU Main Board Unit and several connectors for the CO line Digital KTU SLT Voice mail LAN interface boards and other useful boards Confidential and Proprietary This document contains confidential and proprietary information of LG NORTEL It s use is subject to the conditions it should be used only for the intended purposes as stated in this document that it should not be copied or rep
76. ERMINAL DKT CONNECTOR PIN NUMBER SIGNAL NAME N A 42 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 3 3 CHB308 and CSB316 3CO amp 8Hybrid Board 3CO amp 16Single Line Interface Board 3 3 1 General The CHB308 and 8 Hybrid 8 DKTs 8 8SLTs Board provides an analog interface between the outside CO or PABX lines and the system The CSB316 3CO and 16 Single Line Interface Board also provides an analog interface between the outside CO or PABX lines and the system Each CO PABX line interface circuit provides the A D and D A conversions for audio and signaling to and from the ISC bus of system and the CO PABX line These boards can be inserted in connector CN2 on the MBU or EMBU 3 3 2 Block Diagram VINL LOOF RLY eo voumn I MUTE RLY WINI RING RLY eo VOTI CO WIN VOTTA SLT VIN SLT VOUTI SOT WIMI SLT VOUT SLT WIN3 ELT TDUT3 ELT VIH4 SLT VOUTE SLT WINS SLT vours SLT WINK vorr SEICOE SLT ELT VOUTT ELT WINE SLT VOUTE LOOF N a 5385 RLY SLT ELY ACTS O pmr pi M ee SLT RLY CTL FOL CMU DET OPTION 08 LIE LEO y f SME CTL SLT 7110 12 SLT TOTT 114116 14 SsO III
77. Ethernet controllers support both the media independent interface MII and the buffered DMA interface BDI The MAC layer consists of a receiver and a transmitter blocks a flow control block a content addressable for storing network addresses a number of commands status and error counter registers The MII supplies the transmission and reception clocks of 25MHz for 100M bps operation 2 5 MHz for the 10Mbps speed or 1MHz for the 1M bps for Home PNA The MII conforms to the ISO IEC 802 3 standards The first Ethernet controller is used to interface LAN amp WAN B Reset Circuit The Reset circuit generates reset pulse to CPU RESET by initiated JTAG emulator peripheral reset signal from CPU on the MBU watch dog signal reset switch and power on reset Power ON reset occurs at voltage detection IC U4 at the moment when 3 3V power falls down to 2 7V The main CPU of MBU can reset VOIB by PP reset signal PPRESET 3 34 201 52 10 4 277 na 19 U D Figure 3 9 2 Reset circuit 83 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM C Clock generation Local oscillator X1 generates 10MHz clock and provides it to CPU through Spread Spectrum clock generator U22 PLL block of micro controller multiplies it to generate 133MHz clock for internal CPU clock and external bus clock OUT GND E133 ie gt gt CLE 10H 3 cer ee F
78. FRAME QUTO SZ s gt VMIU_FS FRAME _OUT 1 DUE FFAME QUT 10125 Ss2MH7 VMIL CLE_OUTIE PO Hon CLE_OUT MH IDT 192 194 EXP FRAME EXT32M CLE32M FRAME IN ILL Figure 3 1 10 Svstem clock generation circuit Digital terminal interface port is composed of two transmit signals IXP and TXN and a receive signal _0 23 _0 23 and TXN 0 23 pins of the GSL12 block of ACT2 are used for transmit digital line signal to digital terminals and the RX 0 23 pins are used for receive digital line signal from digital terminals Resistors 64 769 to generate bias voltage for DASL block should have 1 accuracy in terms of the resistance NT BIAS 1 515VDC PT BIAS 1 785VDC Voltage level is very important T 180 Rice 30 15 8 C357 B lu VICO ES ua mi om IE C358 8 1u bs 2731 308 C348 2 2 TTE a 300 _ gt gt DET ego 358 8 1 TXN 2 1 jen til gt E C368 6 14 2 173 FIS 08 ce pad TXN 3 BT3IE 42388 gt 0 4 Figure 3 1 11 interface circuit and bias voltage 24 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM Loop start CO interface circuit The MBU provides basic CO interface circuits that are composed of three line interface circuits two relay controllers and a 4 channel PCM CODEC The following figures show circuit diagram of 1 port of
79. ICE MANUAL DIGITAL KEY TELEPHONE SYSTEM N DC DC circuit This circuit converts 5V power to 3 3V power that is used by main CPU and its peripheral devices such as SDRAM Flash memory ACT2 and so on Power regulator 038 generates Fixed 3 3VDC power 5 43 31 EUM C148 C141 8 lu Figure 3 1 25 3 3V generation circuit O RS232C serial port The line transceiver section consists of RS 232C line transceiver IC U12 capacitors resistor and protection bead The line transceiver IC receives a TTL level data from the UARTO of CPU and converts it to a RS 232C format And also it receives a RS 232C format signals from external equipment and converts it to a TTL level RGU Ring Generator Unit The Ring Generation circuit provides the ring voltage to SLT interface circuits to ringing SLT It generates 25Hz Square wave ring signal whose voltage is 75Vrms and can support simultaneous ringing for 8 SLTs The ring source or 25Hz square wave signal is generated by FRAMESYNC OPTION counters U64 amp U65 and other peripheral parts The small voltage of sine wave signal is amplified by DC DC step up circuit which is implemented by PWM switching 063 11494 and its peripheral parts power transformer T30 Power transistors 052 and so on RGUC25HZ ____ FLI d INI gz im we E Rose gt RING RGU ye ki gt 1 gt
80. IU of MPX bus are used to for PCM channels Voice B channels are transmitted received to from system highway for switching by time slot assignment function of DBID System highway TX ISC1 and RX ISC1 carries 48 B channels with FRAME signals Clock Generation DSP FRAME 2 Clock amp Sync H CLK HIGHWAV MTX Interface Interface MRX RX HIGHWAY D Channel H RXD Interface Interface N H TXD CPU Interface Data Address bus Control signals Figure 3 9 6 act 2 block diagram 85 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM Rx HDLC H RXD Controller Data Tx HDLC CPU Address H TXD Interface Control Signals Clock amp Sync H CLK Control Logic Internal Memory Figure 3 9 7 FPGA block diagram A FPGA U54 provides 1 channel HDLC High level Data Link Control for data communication between main CPU MBU and local micro controller on VOIB HDLC interface port H CLK H TXD and H RXD is used for communication and its transmission rate is 512Kbps E Ethernet interface circuit The MII supplies the transmission and reception clocks of 25MHz for 100M bps operation 2 5 MHz for the 10Mbps speed or 1MHz for the 1M bps for Home PNA The MII conforms to the ISO IEC 802 3 standards The first Ethernet controller is used to interface LAN amp WAN Ethernet interface circuit consists of 10 100BaseTX FX MII Physical Layer Transceiver with Auto cross over U52 KSZ8721
81. IU AAFU Block Diagram Figure 3 6 1 Block Diagram of VMIU AAFU 3 6 3 Functional description The DSP TMS320VC5402PGE chip is a digital speech signal processing subsystem that implements speech compression and voice prompt telephone line signal processing and flash memory management The DSP message storage utilizes a proprietary high quality speech compression algorithm to reduce the data rate of the speech signal The compression algorithm is high rate without gap coding and 32kbps at 8KHz sampling rate 73 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM A Digital Voice activated recording VOX Digital Voice Activity detection is implemented in the DSP and can be activated only in record mode According to the host command recording of the speech signal may either start upon a positive result of voice activity detection or immediately after issuing a recording command B Message play back The DSP supports random access for playback of any recorded message During playback the DSP monitors the telephone line C Call proaress tone CPT Detection The DSP monitors the line for incoming telephone line signals and detects the presence of call progress tones in a predefined frequency region The DSP supports call progress tone detection by utilizing a filter detector with a bandwidth of 300 640 Hz Indication of the presence of call progress tones is transferred to the main CPU it be used for terminating recording D
82. In the application for E1HB8 the features of GSXD block and two DBIDII blocks are selected to implement PCM 59 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM switching and interfacing with peripheral PCM devices such as FALC 56 chip DSP and etc The ACT 2 switches PCM channels between main switching device on the MBU and peripheral PCM devices in the E1HB8 and provides physical channel to carry HDLC packets between main CPU on the MBU and local processor of E1HB8 for high level data communications It also provides two PCM buses called MPX bus MPXO and MPX1 that are used to transmit receive PCM data to from E1 transceiver FALC 56 and DSP with frame sync 8KHz and data clock 2 048MHz signals These PCM buses are composed of 32 time slots and 30 time slots out of them are used for PCM switching as shown in the Figure 3 1 8 MPX PCM highway Time slot 0 and 16 of MPXO is reserved for framing and CAS signaling implemented in FALC 56 chip and the reset 30 time slots are assigned to PCM voice switching The former 30 time slots of MPX1 are used for DSP that can generate and decode 30 channels of MFC R2 signals at the same time The ACT 2 also generates various frame sync and data clocks to support all kind of PCM highway interfaces MPXO PCM highway interface for FALC 56 is implemented by 8KHz frame sync FRAME and 8MHz data clock CLK8M and MPX1 PCM highway for DSP is by 8KHz frame sync MPX FS and 2 048MHz data clock CLK2M The
83. KEY TELEPHONE SYSTEM 0 12 CMU12PR KA INA IET cas wem sare am 2 sess Wesen meen onem TE KDS226 RTK THAILAND SOT 23 85V 0 1A R TP ERHYOO00960 RES CHIP 2 4K 1 10N bp eejo pexeamsim O wes wem waar Ta pese mem mma C wuemwussm 0 0 252 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 5 13 CMUSOPR abs 1 i seron O KDS226 RTK THA ILAND SOT 23 85V 0 1A 3 R97 99 ERHY0001008 RES CHIP 240K 1 10W Gree mess 2 2 Ps mee cone cee sns ceo muwr emessm usse nuk owe US fens inca ose 0 253
84. L 5 10 VMIU wl ar OE 2 ET 249 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 619 20 622 28 031 0000271 CAP CERAMIC CHIP 0 142 R55 R56 57 58 ABEZ9066202 BOX ASSY IPLDK 60 AAFU STG ZZ 2 mo eo _ Lx enero oeaan _ 2 se wem users o IS NER Ho oo os 9 11 AAFU __ so RE SEATON e E oo sona RR HA __ u era os _ m LW aoeeriapam OOO O Ls qe jis on Yana o e WE ew aE Co C co c 250 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM EXSYOOO1401 OSCILLATOR 10 MHz KMS 8 3C 10MHZ 50 PPM 15 pF SMD 7 0 5 0 1 7 FN oie cieca 18 21 ECTHO000124 TANTAL CHIP F C R TTE 20 022 UNO 28 031 0000271 CAP CERAMIC CHIP 3 10930 JI 30 ECCHO000231 CERAMIC CHIP CAP CERAMIC CHIP 4 7778 Ww 77777777 0000425 RES CHIP 100 ewo wsow eT wear ae _ O de Fh usaman _ i CD CD Cale 251 ipLDK 60 SERVICE MANUAL DIGITAL
85. MPXB RX RXI Normal PCM pulse Check U8 and SICOFI IDT 09 010 011 the abnormal components gt For checking check with Framesync signal JA 3 92115 4 045 Frec 2 07337M LOW 27 resolutic CO3 1 6 V 25 Jan 201 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 1 11 Internal MOH circuit Check the signal measured at C488 U50 sheet 5 10 Check the around circuit of U50 And the signal of MOH SCLK YES SDATA MOH RST from U1 Replace abnormal component sheet 1 5 10 v END 100kS s 1721 Acqs M9 M 103 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 1 12 General Purpose Relay circuit sheet 10 10 C Relay ON b the output signal sheet 7 10 measured at pin 12 of 052 Output OV ue Check the around circuit of 052 YES E Check the relay contact measured at pinzt4 5 of circuit of RL8 1 13 PFT Relay circuit sheet 7 10 10 lt operation Between and 517 During power ON OFF NO Check amp Replace U52 pinst4 13 amp Check the Initializing condition TES END 104 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM
86. NTROL U152 EUSYOO 8101 MC34063AD 50 8 8 PIN R TP CIRCUITS 53 EUSYOO49701 IC OCTAL BUS IC OCTAL BUS BUFFER NON INVERTING INVERTING TC 4ACT5A41FT TSS0P 20 PIN TC74ACTS41FT TSSOP 20 PIN R TP mW 23 02128 28 EDSY0003001 DIOE SWTOHNG SWITCHING KDS226 RTK THA ILAND SOT 23 85V 0 1A R TP RS2G D0 214AA SMB 400 V 1 5 A R TP FAST 05 0004501 DIODE SWITCHING SWITCHING 8 801 3 8011 18 EDBY0000601 DIODE BRIDGE EEC 222 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM n 0251 258 0000358 CAP CERAMIC CHIP 15nF 5OV 223 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM n R152 R154 R156 0000985 RES CHIP 3OK 1 10W 224 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 3 R761 R763 R765 99999999999 NOT ASSEMBLE NOT ASSEMBLE ENHYO001606 CONNECTOR HEADER 118 087 26 26 PIN 2 54 ENHY0005301 CONNECTOR HEADER mm STRAIGHT TIN 2ROW 2BODY JE118 D8T 30 30 PIN 2 54 0005302 CONNECTOR HEADER mm STRAIGHT TIN 2ROW 2BODY ENJMO000101 CONN JACK PLUG MODULAR AR 82363 S2 6 30 2 PIN 3 JACK PCB MOUNT UL AU50 aa ENJM9012301 CONN JACK PLUG MODULAR AR 623G8 S4 BK30 4 PIN 8 11 Ls tie A DC TO DC CONVERTER CONTROL U118 EUSYOO 8101 eae MC34063AD 50 8 8 PIN R TP Li 2 SICY0001301 CHOKE COIL COIL STCY0001301 0 1 mH RAD 0 1 mH RAD Es sa mes sere
87. NTROL 0122 05 0078101 ES MC34063AD 50 8 8 PIN R TP IC LOW VTG QUAD 2 INPUT AND GATE TC74LCXOBFT TSSOP 14 PIN R TP KDS226 RTK THAILAND S0T 23 85V 0 1A R TP U120 EUSPO 187 01 IC PBX 212 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 051 58 0142 050003001 DIODE SWITCHING K0S226 RTK THAILAND SOT 23 85V 0 1A R TP RS2G 00 214AA SMB 400 V 1 5 A R TP FAST SWITCHING FOBY0000601 THAILAND SMD 600V 0 5A R TP wr eese jrmessmmr 213 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM C641 00121 CAP TANTAL CHIP 214 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM R446 8501 507 99999999999 ASSEMBLE 215 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM R631 R833 8835 ERHY0000496 RES CHIP 216 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM messe wz HL ona Pe 2 BAG ASSY IPLOK 60 EKSU STG C T 60 Rubber Foot Bag ABAZ0005002 BAG ASSY SS ABEA0000101 BOX ASSVJBASIC ASSY BASIC zz ZZ C39365 A9925 B503 A9925 B503 IPLOK 60 EKSU STG GR Champ Cable ACDV9001601 CHAMP CABLE ASSY joa BTBA0000101 CABLE BTBA0000101 SH 190 MBADOO02406 VINVL PE ZZ IZZKPSIAMONH SXDKA 000000000 STATION H S X DX A V1625A CORE HO5VV F
88. NUAL DIGITAL KEY TELEPHONE SYSTEM XNOTE VOIU DET is read by micro controller on VOIB through to detect whether is installed or not Corresponding pin on VOIU side is tied to ground 0 AddressOtoHBIL B8 Addressi to HR W B9 CN3 Ground Read output enable Table 3 9 8 CN3 Pin assignment 3 10 PSU Power Supply Unit 3 10 1 Block Diagram Figure 3 10 1 Block diagram of PSU 89 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 3 10 2 Operation description This unit is Switching Mode Power Supply using PWM method And is formed of 2 switching parts that is separated and controlled Voltage Mode Control A 30V generation circuit This switching power circuit generates 30VDC for digital terminal and single line telephone respectively VO power varies from 22V to 30V depending on AC Power supply When AC power is failed VO is provided from system back up batteries and is ranged from 22V to 24V In normal situation VO is provided from PSU and is steady 30V This circuit produces stable DC power for digital terminal and single line telephone regardless of AC power variation It is composed of PWM controller U1 power transformer T1 rectification circuit RC and feedback circuit 30V Output AC DC PART 1 Input Filter It lays restraint on noise to come into the input line and out to the switching part 2 Input Rectifier amp Smoothing Transfer AC input to DC vol
89. RAME B 5 BER xD b MPx TXB 3 Wet BHD vy l AL ABS _ _ J n nr pac ww ED PASI SL ide F cua 22 2 m FALLGGD4 R 5 INT 2256 lt v INT s oor FALC PST Lib ETE i 1BUT 0 Auf B tal 77 M ay put 2 yogy ese ay i l INTERNAL Pu C124 135 E119 0111 032 10 Tb tu Au Tg 10 Pu WEL 3 34 M 3 2V oaral ion NES uar Power Figure 3 5 10 FALC 56 and its peripheral circuit a Master clock A reference clock of better than 32 ppm accuracy in the range of 1 02 to 20 MHz must be provided to master clock signal The FALC56 internally derives all necessary clocks from this master Roos x4 FE1E 2323 N OT SS PEB MCLK t fly NC E 28 132HHz 32 PPM Figure 3 5 11 Master clock generation The communication between the CPU ARM7 and the FALC 56 is done using set of directly accessible registers The interface is configured as Intel type de multiplexed data access with a data bus width of 8bits b PCM system interface The PCM interface with the system highway is implemented by 8KHz signal PEB FRAME and 8MHz data clock CLK8M from swit
90. SYSTEM 1 4 2 Environment Specification ITEM DEGREES DEGREES Optimum Operation Temperature 20 26 68 78 Storage Temperature 10 70 32 158 Relative Humidity 0 80 non condensed 1 4 3 System Capacity DESCRIPTION CAPACITY BOARD TOTAL Time Slots 128 CO Line Ports 3 MBU 3 EMBU 3 CHB308 Max 36 W _ Max Direct Station SLT 055 8 MBU 8 EMBU 8 CHB308 Max 48 Attendant Positions 5 Svstem Intercom Links Non Blocking Paging 1 zone All Call Internal 5 zones 100 station 24 digits each 15 50 admin programming 32 digits Internal MOH 13 Musie Sources meu 1 _____ 1 2 ExemdPamgpot 1 2 External Relay Contact 2MBU2EMBU 4 Circuit 1 MBU 1 EMBU 1 CHB308 4 1 CSB316 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 1 5 System Configuration 1 5 1 System Configuration The following Figure 1 2 1 System connection diagram shows the ipLDK 60 system configuration for all kinds of board in this system that includes the existing boards for the ipLDK 60 system and the developed new boards Expansion KSU EKSU Expansion Key System Unit EMBU Expansion Main Board Unit 3CO 8Hybrid ports Ar Voice Mail Interface Unit 4 chs PSU Power Supplv Unit 9OW Auto Attendant Function Unit 4 chs 33 Kbps Modem 1 Port 3 CO a
91. T 23 85V 0 1A R TP Ls os sam nox nm esmsvmsmsmww RS2G 00 214AA SMB 400V 1 5A FAST SWITCHING 236 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM C331 C333 C335 C337 00272 CAP CERAMIC CHIP 237 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 8613 8615 8617 8619 99999999999 NOT ASSEMBLE E ncs sunan masanguna PRORERTE imam rn ro KO ING CT ose ones meses E E LVP 2890 USA MS WA FOR NORTEL LVP2890 BOX MLAC9006303 LABEL BARCODE BARCODE ABAZ0007305 BAG ASSY ASSY IPLDK 60 E1HB8 STG 77 1010 60 Bag Ass y E1HB8 GMFVOOO1801 3MM 6MM SB41 FZY B KB1023 M3X6 GMFYOO01801 SCREW MACHINE SZ P ho 222 MBADOOO24OB lr es 2 NSAZ00800 SHEET IPLDK 60 ETHB8 STG WB IpLOK 60 PC Sheet GTFB0001801 3 MM 8 MM SBAT FZY B TB X 8 NEN i 5 7 PRHB8 IT ee CC 2 60001801 SCREW MACHINE PAN GMFY0001801 3 MM 6 WM SB41 FZY B KB1023 X 6 SZ P mrs wama rene eris Seti NSAZ0033004 SET IPLDK 60 E1HB8 STG WB ipLDK 60 PC Sheet E1HB8 GTFB0001801 THAILAND 3 8 MM SBAT FZY B TB M3 X 8 GTFB0001801 SCREW TITE PAN B SZ P E az Fence ancien _____ Ferrero sar
92. TELEPHONE SYSTEM 3 2 EMBU Expansion Main Board Unit 3 2 1 General The EMBU is the Expansion Main Board Unit of ipLDK 60 It provides basic CO Station and extension interface circuits physical connection with various boards and also miscellaneous functions The EMBU is composed of a main processor and its peripheral circuits the three CO interface circuits 8 hybrid circuits that are selected to DKT or SLT ports by pin assignment 8 digital line interface circuits and 8 single line interface circuits a Ring Generator circuit a system battery backup circuit Basically the EMBU provides the capacity of 3 08 that is the three CO interface circuits and the eight extension terminal interface circuits that are composed of 8 DKT ports and 8 Hybrid ports The system features can be added by installing function boards at connectors that are prepared on the EMBU 3 2 2 Block Diagram Block Diagram of ipLDK 60 EMBU Option CSB316 SLIBS Figure 3 2 1 Blockdiagram of EMBU 39 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 3 2 3 Circuit description There are five kinds of option boards such as CHB308 CSB316 SLIB8 and CMU50 12PR This board doesn t have ports for RS 232C and connectors for VMIU E1HB8 and MODU So all features of the EMBU are exactly the same as the MBU except the features of RS 232C Voice Mail Interface E1HB8 Please refer to the MBU part CN2 CHB308 CSB316 SLIB8 CN9 10 CMUS50PR CMU
93. TP LOW VTG HEX INVERTER CYIFS781BSXC S01C 8 PIN R TP LOW EMI SPECTRUM SPREAD PORE U21 EUSY0050701 IC CLOCK FUSY0052001 15222222 5820 5402 0 100 144 PIN BK FIXED POINT DSP lie 7 TC74ACT574FT TSSOP 20 PIN R TP D TYPE FLIP FLOP 037 EUSY0062001 3 STATE OUTPUT 3 256 25 26 FUSY0074001 TCTANHC24SFT TSSOP 20 PIN R TP BUS TRANSCEIVER MC74LCX541DTR2G TSSOP 20 PIN R TP LOW VOLTAGE CMOS U27 29 U31 U36 EUSY0085301 IC OCTAL BUFFER S3 STATE cafe FUSY0099401 S3C4530A1 QE80 QFP 208 PIN BK MICROCONTROLLER EUSYO120401 MTABLCAM32B2P 7 TS0P 86 PIN BK SYNCHRONOUS DRAM S29AL032D90TF1030 TSOP 48 PIN BK BOOT SECTOR FLASH NCP1117ST18T3G SOT 223 3 PIN R TP DC DC CONVERTER KSZ8721SL SSOP 48 PIN R TP 3 3V Single Power Phy Pb ww FUSY0282601 PEF2256HV2 2 PIN R TP E X5 EXSY0001401 OSCILLATOR KMS 873C 10MHZ 10 MHz 50 PPM 15 pF SMD 7 0 5 0 1 7 BMS 873R 8 192MHZ 8 192 MHz 30 PPM 25MHZ HC 49 SM 25 MHz 50 PPM 20 pF 50 SETY0000701 THERMISTOR PSR21083B 2 PTC RAD ED9705 T FB5 6 SFBHO000301 FILTER BEAD CHIP HH 1M2012 121 120ohm_ 2012 R TP SFBYO000101 FILTER BEAD SFBY0000101 4 06 3 05 2 54 ED3863 S SMT 242 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM Bs qi STMVO019001 TRANSFORMER MATCHING DG2001DV T1 E3 S0T23 6 6 PIN R TP SPDT ANALOG SWITCH Pb U10 EUSY007
94. VICE MANUAL DIGITAL KEY TELEPHONE SYSTEM NO Ringing state Check the components SLT HOOK U110 pini are damaged or not Check a hook sensing Circuit during ringing Ringing state Check the components SLT_HOOK U110 pin are damaged or not 1 U110 R281 251 2 R221 R231 R291 221 021 169 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 3 SLT Ring path check Connect a SLT to a SLT port and hook off Line feeding check Call to tke Check the Ring path Ring sound heard R221 R231 RL11 R201 211 1 PT11 and U5 Y NO es 1 0 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 4 SLT Voice path check Check voice signal VIN amp VOUT at 279 part around U2 and U3 Check the circuit around U111 U113 U115 U117 U2 amp U3 Check the circuit around 111 118 MHz FRAMESYNC _ _ normal 02 03 CN2 Connectidn 171 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 6 2 Rx or Tx Fail check the A10 of CN2 2Mhz ok N z Check the signal source from MBU Ne Check the U2 U3 the signal source from MBU Check the 02 03 heck pin 22 32 of U2 U 2Mhz ok Yes check the A11 of CN2 Framesync ok Yes check pin 81 of 02 03 Framesync ok Yes Line feeding check Check the related SICOFI U2 and U3
95. Vdc around Check the component D1 C8 C9 C29 YES 30V OUT 200 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM DC 30V PART INPUT NO U11 Check amp Change YES U4 1 CHECK NO RECTANGAL WAVE FORM 04 Check Change YES NO R22 Vout CHECK Check the D8 U4 1 2 Vout 5Vdc around YES DC 5V OUTPUT YES Check the D7 U3 DC 5V OUTPUT DC 5V OUTPUT 201 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM SECTION 5 part list 5 1 BKSU 121 woo S e a 72 e u AT C G ac isi 090 sina Lower es mee Lr jw emm meme memo _ ENJMO000101 CONN JACK PLUG MODULAR MODULAR AR 623G3 S2 GY30 2 PIN 3 JACK PCB MOUNT AR 62363 52 6Y30 2 PIN 3 JACK PCB MOUNT UL AUSO 2 wt 0810 1 1 36 10 PIN ANGLE ENJMO008803 CONN JACK PLUG MODULAR TEMP BELMAG WITH LEDS GTFB0002001 SCREW TAP TITE PAN B GTFB0002001 3MM 10MM 5841 227 X10 SZ MCJZ0029301 COVER IPLDK 20 MBU AUS BK LDK 20 50pin Connector Cover IC IMX8BIT LOW POWER AND LOW VOLTAGE ES U1 EUSYO224001 mM BS62LV800 1E IP70 TSOP2 44 PIN R TP L3 o Ds jw esee seme 722002020000 T ju
96. a is then available to the main CPU for further processing The current sink circuit permits the audio transformer to operate in a non saturated state with DC blocking from series capacitor C431 25 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM LOOP PING 421256431 33u T 2 2u 50y Figure 3 1 13 Loop current sink circuit Also port is comprised of the 4 channel PCM CODEC 09 SICOFI interface part and T1 matching transformer U101 amplifier and other passive devices The main functions of this part are the isolation of the system side from CO line side and the gain conversion of voice signal The digital filters in the SICOFI provide necessary transmit and receive filtering for voice telephone circuits to interface with time division multiplexed systems An integrated programmable DSP realizes AC impedance matching trans hybrid balance frequency response correction and gain adjustment functions TA Ta _LOOP_RING1 SMS1_IN lt 441 FB ERIT ENT 472 gq lt co vauri Figure 3 1 14 interface circuit at secondarv part The 4 Channel PCM CODEC 09 provides A D conversion of signals from the Analog CO VIN1 line to MPX RX PCM highway and D A conversion of PCM signals to the Analog CO VOUT1 line from MPXB TX PCM highway Digitized voice and data are available from the corresponding PCM time slots of MPXB bus MPXB TX and MPXB RX that are provided by DBID block
97. al instrument are placed on a back plane highway transmit B channel and sent to the MBU where gain modification and or conference summations take place The output is placed on a back plane highway receive B channel for the receiving port All voice channels are fully 64Kbps digital time slots 2 2 2 Signaling Channels The D channels are 16Kbps channels designed to carry channel specific signaling information and low speed user data 11 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 2 3 Administration 2 3 1 General Description ipLDK 60 Hybrid Key Telephone System utilizes stored program control technology It means that system time slot switching hardware control and all feature implementations are controlled by software code residing on memory in the system There are 3 types of memories used by the system System Generic memory Scratched memory and Customer Database memory All 3 types of memories are contained on the Main Board Unit MBU 2 3 2 System Generic Memory The first type of memory is called System Generic memory and is stored on Flash memories on MBU This memory is used by the Main Processor and dictated how the system operates controls all feature implementations monitors all functions etc The System Generic memory cannot be changed however upgraded software can be downloaded to add new features to the system or change feature operation 2 3 3 Operating Memory The second type of memory is a system o
98. and other control signals The PP RESET signal is from main board where main CPU generates this signal for software reset or hardware reset is made by power detection circuit The JTAG RST signal is generated by CPU emulator during software development In addition there are other reset signals provided by WATCH DOG Power on reset and board reset switch The 3V DET signal is generated in case of pressing reset switch SW3 system power ON and power instability Power ON reset operates when 45V falls down to 44 65V in voltage detection IC U2 to prevent uncertain operation The output of voltage detection IC 3V DET and WDOG counter U3 pulse signal are connected to OR gate U 1 1 to make board reset signal RESET eventually WDOG reset signal is generated when CPU can t clear the counter U3 58 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM by WATCH DOG periodically due to certain abnormal operation KESE LIC Dur ing mode i 334 G Po UFF Hormal operation E lt MATCH DOG 74 060 P21 18DF gt gt RESET TALEX PP RESET tFron Figure 3 5 5 Reset circuit C Read amp Write Buffer There are several read write buffers on the E1HB8 to buffer address data and control signals and to convert 3 3V signals to 5 signals Octal buffers U27 U29 are to drive address bus and read write control signals and bi directional buffers U25 U26
99. asured at pin of C4 NO Check the around circuit of U YES ENO 9 1 3 1 8V Power Status 1 8 lt Check the voltaoe level measured at pin of C16 Check the circuit around U4 Sheet 4 7 NOTE U4 NCP1117ST18 1 8V regulator U7 EZ1587CM 3 3 3 3V regulator 180 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 9 1 4 Clock Check 10MHz Sheet 1 7 10MHz At FB14 10MHz 012 C1 Freq 1 50 000MHz NOTE U12 S3C4530A ARM7 CPU U14 FS781 clock driver 181 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 9 1 5 Reset circuit Sheet 2 7 Reset OK m Replace U2 and By power on Check U1 U5 amp U6 yes Reset OK SW3 no Check U2 R4 R7 C1 yes Check watch dog pulse Watch_dog Pulse enable at pin 205 of U12 CPU Gheck R14 R22 Uf At least everv 2ms Check Pin 12 of 03 Ho Check U3 and parts 03 yes Pin 15 of U3 Low U2 MC34064 Power detect IC U1 74LCX32 OR gate U3 74HC4060 binary counter U5 74LCX08 AND gate U6 74LCX04 Inverter 182 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 9 1 6 PLL Phase Locked Loop circuit 1 PLL circuit check Sheet 5 7 Reference oock Check the frequency measured at pin 3 of U9 MEL NO 2 048 2 YES NO Check M th
100. ation by this serial port it is necessary to use GDK TRC tool that converts 5V signals to 12V signals and vice versa In addition the CPU provides several external I O ports that are used to read some functional signals like DIP switch information board issues and name a few and to output control signals such as reset signal LED indications and etc CPU Pon NOUT CPU Pon NOUT PO FALC Interrupt PS Interrupt request P1 DSPinterruptdecoding PO Boardinfobit2 1 P2 P10 P17 LED indications O P3 Boardinfobito Pl8 P4 RESERVED X Ps FALC reset P21 WATCH DOG i DSP reset P22 P25 DIP switch info 0 3 Table 3 5 3 CPU port signals Local oscillator X2 on E1HB8 generates 10MHz clock and provides it to CPU through Spread Spectrum clock generator 014 PLL block of CPU multiplies it EXTCLK by 5 to generate 50MHz clock MCLKO for system operation RIS ts 3 7214 op TID Edi 3 C70 276 H C53 LED 2 9 1 g gtu GND FES ETO is x e a EO A E R65 B A Figure 3 5 4 CPU Clock generation B Reset circuit The Reset circuit generates reset pulse RESET to CPU and flash memory from various control signals such as peripheral reset PP RESET of MBU JTAG RST of CPU emulator
101. cal fast transient burst and other electrical disturbances 66 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM DSP and its peripheral circuits The DSP U35 TMS320VC5402 can perform 30 channels of MFC R2 generation and decoding at the same time DSP decodes MFC R2 signal from E1 line through FALC56 and ACT 2 to inform CPU of one type out of 15 MFC R2 tone types by HPI host interface For MFC R2 signaling time slots 1 15 and 16 31 carry R2 signals that are used to forward or backward information R2 signals received from E1 line are input to MPXO RX port of ACT 2 and switched to MPX1 TX port to make DSP decode tone types of received signals DSP inform host CPU of decoded information by EVENT format defined between CPU and 5 On the contrary R2 signals generated by DSP with host COMMAND is input to MPX1 RX port and switched to MPXO TX port through ACT 2 Eventually MFC R2 information is transmitted to other side through FALC56 The HPI Host Port Interface is an 8 bits parallel port to interface a host processor with DSP chip The host can read write internal RAM fully through a dedicated internal bus DSP has an internal PLL circuit that generates internal master clock 100MHz from external clock 10MHz CLK 10M and an external clock must be 1 8 voltage signal t3 3V 275 6143 B tu 0 11 1OMHz CLE gt lt 150 should be 1 8 2429 8 Figure 3 5 18 DSP master clock circuit G
102. ce signal impedance matching analog amplification attenuation trans hybrid balancing PCM highway interface and etc For more information about SICOFI refer to the datasheet of PEB2466 manufactured by Infineon SLT Analog signal part SLT analog signal part of CHB308 and CSB316 are composed of SLT line interface and protection circuit 36 power feeding circuit current limiting circuit SICOFI interface circuit and hook sensing circuit The port 1 is used for circuit description as an example 46 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM Ti BLTI PM m BD11 Bt a Gk ULTI T Ts PT 11 T Il u ome se Figure 3 3 6 The SLT line interface and protection The line protection circuitry consists of one bridge diode BD1 between the Tip with Ring input and Relay RL 11 2 for providing the ring signal and making the DC loop As the figure shown below 36V power feeding part are connected to SLT line interface and protection part So 36V power is supplied to SLT through resistors and transistors Q21 and Q31 the SLT line interface and protection circuit The resistors R656 R701 and R671 transistors Q41 and Q101 capacitor C728 and zener diode ZD10 makes the loop current be limited Figure 3 3 7 36V power feeding and current limiting circuit The SICOFI interface circuit is comprised T11 matching transformer U111 1 amplifier and othe
103. ceive the page Stations that are not busy when the page was activated will be placed in the off hook mode and will monitor the receive B channel assigned to that station External pages are set up in the same way however communication to an external page zone can be 2 way meaning a talkback speaker can be used for the external zone and the speaker can transmit voice back to the page initiator 2 4 2 Outside Call Types A CO Calls CO calls connect a station in the system to a central office port telephone line on the system It provides access to the Public Switched Telephone Network PSTN When an outside line is requested by a station the CO line interface is terminated providing CO dial tone from the local central office A transmitting and receiving B channel pairs are used on the system ISC highway to route the PCM digitized audio between the station and the CO line circuit When the station dials DTMF digits the dialed digit data is communicated to the MBU which in turn injects PCM data of the dialed digit DTMF tones onto the transmitting B channel through digital summation techniques The CODEC associated with the CO Line decodes the PCM data into the analog wave form which is placed on the CO circuit and sent to the local central office to establish the call connection After the call is established the system monitors the CO line for open loop disconnecting supervision If the tip and ring loop is open during the programmed loop supe
104. cess to system terminal programming and diagnostic routines The UART is directly connected to I O port of the MBU microprocessor With UART terminal programming and system SMDR printout can accomplished simultaneously The system customer database programming routines are directed by the system generic software allowing only one communication port to access customer database programming at a time 1 RS 232C Communication ipLDK 60 system provides a port of serial communication standard RS 232C that is implemented by the first UART of CPU It provides asynchronous serial communications up to 19200 baud rates A log on procedure is used to enter the system terminal programming mode and ASCII characters and control codes used to modify the customer database The 9 pin RS 232C port is configured as Data Communication Equipment DCE Data is transmitted on pin 2 and received on pin 3 Hardware flow control is supported with a Clear To Send function on pin 7 The system will halt transmission of data when this signal is asserted by the connected equipment 2 Modem Communication The optionally equipped modem unit functions on the second UART of main CPU 53 4530 Interface connectors the MBU allow the Modem unit to be installed as an option on the MBU The modem will answer incoming line ringing to the specified CO line with modem carrier tone Modem communications will support up to 33k baud rates E Digital Voice Announcemen
105. ch device ACT 2 PCM frame sync signal PEB FRAME is generated by D Flip flop to meet required timing for FALC 56 PEF 2256 63 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM Receive clock RCLK Pin 75 with frequency 2 048MHz is extracted from the incoming data pulses to synchronize the system with E1 network In case of Loss Of Signal LOS the output is derived from the clock that is provided on MCLK This extracted clock is routed to PLL device U11 after being divided by 4 to make 512KHz reference clock for PLL circuit roy 10 15 2 utz 4 219 9 ma TETA ER EF BFRAME 52 140 E BFALC RST gt Figure 3 5 12 FALC 56 PCM Frame sync signal c Line interfacing circuit The FALC 56 PEF 2256 has been optimized to realize generic Long Haul and Short Haul solutions The signal at the ternary interface is received at both ends of a transformer A termination resistor is used to achieve line impedance matching The operating modes 75 or 120 are selectable by switching an internal termination resistor of 300 O in parallel This selection does not require the change of transformers The E1HB8 supports only the line termination of 120 O R99 so the additional impedance match device such as BALUN is needed for connection with operating modes 75 The serial resistors R95 98 in transmitter side are recommended with 1 2 transformer to satisfy all related CCITT and ITU T require
106. controller of CPU Following table shows the memory size SDRAM 128Mbits 16Mbytes Table 3 5 1 Memory size System manager of CPU provides the four DRAM SDRAM banks the four External I O banks the six ROM SRAM Flash banks and etc Each bank is set by corresponding registers and the below table shows system memory assignments for LDK 20 system Reserved Reseved J Reserved Others o Reserved Table 3 5 2 Chip selection signals 56 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM spesa PS EO 3 1 RASU 50058 1 a RASI 8068 pase _ 50052 __ 50653 SDRAS 5 0 SDCAS Sepre ku 33 CAST SDCAS SDCKE lt 55 2_ CAS3 FALC cs HEC _ECSO E 8168 8670 k AIT T FLASH RESO lt EE RESA F R 54 R SS EL POSIZEO E lt 1 BOSTE 1 enne DE 980 74 pr NBEO 580 115 NBEO DOMO WBE U _ 2 lt 187 _ 2_ 2 WBE lt 180 WBE 3 DOM3 leave reg EXTMACE Figure 3 5 2 System memory interface The S3C4530A has an Ethernet controller which operates at 10 Mbits per second in half duplex or full duplex mode The Ethernet controllers MAC layer supports media independent interface MII that supplies the transmit and receive clocks of 2 5MHz at the 10 Mbit s speed The MII is used to implemen
107. cuitry output also connected to this kind of device so that clock operation is maintained during a local power failure 21 ipLDK 60 SERVICE MANUAL DIGITAL KEV TELEPHONE SVSTEM Figure 3 1 7 Real Time clock circuit H 2 and its peripheral circuits The ACT2 U8 is a custom switching device that has a DBID block and two GSL12 blocks so that it can cover all functions for SOHO system And it provides three PCM highways TX RX ISCO 2 to interface system back plane interface device kind of time slot assigner on the peripheral boards and several ports for general purpose I O ACT2 supports PCM switching gain control tone generation and conferencing together with a tone gain generation function The one DBID block makes a PCM highway called MPX bus that is composed of 32 PCM time slots and used to interface all PCM CODECs on the MBU CO boards and some function boards as shown in the Figure 3 1 8 Reference clock 2MHz and 8KHz frame sync signal to mask time slot assigned to specific PCM CODEC are provided by ACT2 so that PCM CODEC transmits and receives its voice data to from specific time slot of MPXB PCM highway GSL12 block that is composed of internal DBID and DASL logic block compatible to TP3406 provides 32 digital terminal interface circuits The eight ports DKT1 DK18 are assigned to 8 basic digital terminal circuits on the MBU and the rest signals DKT9 DKT32 are routed to digital terminal interface part of EMBU CHB30
108. d Blue LED 109 on the E1HB8 turns on when line is activated and PLL circuit operates in synchronous mode Ri LLG 3 RED 89 utt CD TAHCAE 46 x 3lTOMM IN CCOMPI OJT E 1 vip COMPIT QUT CIA PHASE PLILE r 14 bid TA 1 33 8 10 ja AN 28 x 2 Feed back 512kHZ Figure 3 5 14 PLL circuit BRCLK clock signal 2 048MHz from FALC 56 PEF 2256 is divided to 512KHz by D type Flip Flop U9 and routed to PLL IC U11 for phase comparison with internal feedback clock from counter U16 PLL IC U11 produces comparator output signal that is routed to VCXO through loop filter that is composed of R59 R57 C56 and C57 The 2 5V DC DC circuit that consists of U39 and divide resistors generates 2 5 VC bias voltage from 5V power E MENO r sk V 1 3 Elis E784 15K ___ E 299288 1821 4 i 3 5 15 2 5 VC power circuit VCXO OU1 32 768MHz clock oscillated by VCXO X3 is routed to switching device ACT 2 through spread spectrum clock driver U21 and buffer U38 65 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM VCXO OUT 32 768MHz C31 57 fm 3 3K QUT gt D Low ROLES P545 33 TON ee S us 220 gt gt R36
109. d at FB10 pin 42 of U8 NO gt Check the FB10 and U8 100 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM TIT C EXP FRAME D For EKSU Voice Communication Check the frequency measured at Pin 4 of 073 y 8 9208 4 Check the around circuit of U8 R 2 Long Frame SICOFI U9 IDT U10 U11 MBU Check the frequency measured at R726 pin 40 of U8 Check the R 26 and U8 U36 R324 R325 Check the frequency measured at R 24 R725 pin 37 38 of U8 101 Check the R724 R725 and U8 amp Connection Status ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 1 10 System Highway and MPX PCM Highway circuits For EKSU For EKSU Highway circuit TX RX ISCO 3 Connection is OK Check the EXP TX RX ISCO is YES Check the CLK32M and EXP FRAME are O il sheet 4 10 _ 15 UB is self connected for Voice Gain control during conversation Check the normal PCM pulse in NO MMS_TX RX_ISCO 8 08 pin 69 72 90 93 and R 19 R 22 Check the Normal PCM gt pulse swing of timeslot in each highway and pin 6 89 of 08 R723 R938 R939 NO Check the U8 R 2 and circuits NO gt around them Replace the abnormal components Check MPX PCM Highway _ 1 8
110. e C Divide cout U2A FALC 56 Check the circuit around U9 Check the waveform of oin 11 of U13 buffer v Check the frequency measured at pin 9 of 09 x 2 15 25 31 Run 100MS s Sample 1 sam Freq i 512 80 2 Ww D 512KH ivi i 5 32V oe Check divider U9 v Check the frequency measured at pin 3 of U11 Check the frequency of oin 10 of U16 counter mu 100 5 5 sample VA 2 5 the circuit around M YES C Next Page B Check the circuit around U16 183 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 1 PLL circuit check continued Sheet 5 7 C Phase Comparator Output Check the shape measured at pin 2 of U11 Check the circuit around U11 v VES MEE javox 2 the voltage measured at pin of Cb 1 Check U10 and NO loop filter RC circuit R59 R57 C56 amp C57 205 2822 2 if voltage level at pin lof U10 i
111. e LD3 Blue Timer Flashes every 100msec LD4 Blue LCD Active Updating Flashes every 300msec Table 3 1 6 LED indications C PIN descriptions of various connectors 1 Expansion KSU connection Expansion KSU should be connected to CN1 by using 50 pin flat cable CNNT Pin Number Pinname Description EA 0 EA 12 ED 0 ED 15 CN1 7 7 _ ERCS3 A Enable and RCS Chip Select for Expansion _WE01 Write Enable for Expansion KSU A2 B2 EXP TXISCO EXP RXISCO TXISCO and RXISCO for Expansion MBU Data out from Sicofi IDT on EKSU and Interrupt not used from Expansion ACT2 EXP DET Expansion Detection Table 3 1 7 Pin assignment of CN1 A23 B23 DOUT EXP INT ASIC2 35 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 2 CO and Station boards installation aad 1 1 30V Power B6 _ MPX Bus for Option 2 2 MPX Bus for Option A4 A9 A10 A11 ___89 ___ __ Out Enable for option da GND Ground B10 _PP_RESET for option 83 85 811 823 B12 OPTION CS b Option Chip Select 5 6 7 8 AA 1 AA 4 Address B13 2MCLK OPTION a Rag OG don 13 20 000 00 Data 0000 OPTION g Framesync for Option Data out from DKT Interfaces for NE andi Sicofi IDT Option CHB308 Table 3 1 8 Pin assignment of CN2 Inversed 2MHz clock signal from sw
112. e data As shown in the below figure power supplies VBP and VB are supplied by dip switch SW2 and battery BAT1 3 6V for protecting of system memory and RTC date time data during local power failure VBP is the power supplied to SRAM and VB to RTC Figure 3 1 4 Reset and backup battery circuit 19 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM C PLD1 The PLD1 U120 is used to control MBU board which are reset signal control address decoding for chip selection signal generation support latch buffer functions for ring relay SLT hook sense Co loop relay control Co loop ring sense and general relay control ti fi L m uni A Bis in um PM Rn Hr n LH sg ____ 3 jir tt E Wi 3 mm 5 IIT EsF mm Fr BUFFER MEE BINE BYE i B JE T B Hk i IIT 3 TAE A El DFTIDU d n Lm 6 RR er 8 E i HE B Rena Ha 2 NAE a LL TIT II s TE 51 10 MI BH ER P Ez E l Tan Figure 3 1 5 PDL1 Circuit D PLD2 The PLD2 U121 is used to control MBU board which are address decoding to generate chip selection signals codec devices
113. eam PCM 32 Slots E1HB8 is designed based on CCITT G 703 704 823 physically can support pulse dialing MFC R2 register signaling which is based on ITU T Q 440 480 An extension board SLU8 Single Line interface Unit 8 ports is basically installed to connectors on the E1HB8 to provides 8 hybrid ports that mean supporting DKT Digital Key Telephone or SLT Single Line Telephone connection 90 its maximum capacity is 30 trunk ports and 8 internal telecom ports E1HB8 is composed of main CPU Memory circuit Ethernet circuit HDLC interface circuit line interface circuit PLL Phase Locked Loop PCM switching circuit and DSP circuit for MFC R2 coder as shown in the following block diagram 3 5 2 Block Diagram 4MB Connector from to MBU CN5 2 gt LAN circuit Reserved Reserved HDLC Comm With MBU CN2 DKT interface 8 Clock 32MHz Reserved a05 2 5375 225 8 Line interface circuit RJA5 MJ3 z ji gar mar Highwav 31003 Wo _FALC_CS sumali CLK 32MHz to MBU HCS WES SLT interface 8 Figure 3 5 1 Block diagram of E1HB8 E1HB8 consists of CPU Central Processing Unit and its peripheral circuits Ethernet interface 10Mbps and RS232C se
114. eserved B Ch 64Kbps TX HIGHWAY Ki LL UA Fir UEM RX HIGHWAY UE HDLC Idle tri state HDLC D 6B D Ch Idle tri state B Ch Idle 55h or D5h vertical IC Trigger JC Display JC Cursors JC Measure JC Math JC Masks save J Recall JO scope JC Help i Tik 1 7 gt lt ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 9 1 8 Clock generation amp PCM bus ACT 2 Sheet 4 11 244ns FRAMEOUT D FRAME for FALC56 8MHz SCEKR X of FALC 56 2MHz DSP PCM clock 488ns 512KHz HOLC clock One time slot of MPX bus 3 9us 2 048Mbps Data rate MPX FS frame for MPX PCM bus 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 17 18 19 20 21 22 23 24 25 26 27 28 29 30 E MPX IXO 15 Voice channels B channels 15 Voice channels B channels MPX RXO Multiplexing 32 time slots per frame TSO FAS NFAS 516 MFAS ABCD CAS signaling TS1 TS15 TS17 TS31 B channels H ING A a ST SER EE SSE TS 1 TS 15 ig TS 17 TS 31 OD A 30 Voice channels B channels MPX 1 1 Multiplexing PCM busti 32 time slots per frame TS0 TS29 B channels for DSP that decodes encodes MFC R2 tones Clock generation and MPX PCM highway 187 ipLDK 60 SERVICE M
115. fault all OFF CN1 JTAG Joint Test Action Group for debug RS232C Trace Tool Connection VOIU Board Connection maa CN4 VOIU Board Connection W MBU Connection Network RJ 45 Cable Connection Table 3 9 4 Various switches and connectors functions hemak LD1 Channel1 Seize indication LED ON Busy OFF Z 102 _________ Channel2 Seize indication LED ON Busy OFF Idle o o LD3 Channel3 Seize indication LED ON OFF LD4 ________ _ Channel Seize indication LED ON Busy OFF Idle o o 105 channel5SeizeindicationLED ON Busy OFF Idle o LD6 Seize indication LED ON Busy OFF Idle o o Channel7 Seize indication LED ON Busy OFF Idle Channel8 Seize indication LED ON Busy OFF Idle 1097 VOIU DSP operation status LED ON Normal OFF Fail 1010 VOIB DSP operation status LED Normal OFF Fail ____ psPHINTinterruptLED ON Active OFF Idle x U L MJ1 LD1 yellow Speed Status LED ON 100Mbps operation OFF 10Mbps MJ1 LD2 green orange Link Status LED ON Link Toggle Data transfer Table 3 9 5 LED indications Connector Pin Number SIGNALNAME FUNCTION ___ _ Table 3 9 6 MJ1 Pin assignment HD 0 HD 5 Ground 9 HD 6 JDatabustoHPI8 JNC A10 DatabustoHPI8 BIO INC 0 CNA Table 3 9 7 CN4 Pin assignment 88 ipLDK 60 SERVICE MA
116. ffer U36 damaged part Yes END 19 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 9 1 15 LAN interface circuit 1 2 5V check LAN PHY U8 has internal switching regulator that generates 2 5Vdc voltage Check the voltage at Pin 38 VDDRCV of U8 2 Component check 9 Check U8 and replace it line filter L1 L2 protection diodes D25 D28 and transformer T1 Replace damaged parts NO TXCLK MII RXCLK CI Freq 1 25 0004MH2 Idle state 25MHz Link state 2 5MHz 10Mbps Check the LED of MJ1 after connecting LAN cable 1 YELLOW gt turns off in link state 10Mbps 2 GREEN blinking to indicate the flow of traffic 198 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 10 CMU12 50PR 10 CMU12 50PR 10 1 Polarity Reversal detection 1 st Port Check the Voltage level CO1T to CO1R Check the Line connection Cor 3 Lower than 45V Yes Check The pin 32 3 of U toggle the level by Polarity EC NO Check the signal Check the 1 Check the components 1 Change the U7 Note 1 82 R11 R12 U1 R51 R41 R42 1 2 199 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 11 PSU 11 PSU AC DC PART Plug wire Contact Check AC CONTACT CHECK Change F1 250V T2A C29 VOLGATE CHECK Vdd 30
117. gitized voice and data to the digital terminals via the transformer And the RX 0 RX 15 pins of the GSL 12 block of ACT2 are input terminals and are used to receive a digitized voice and data from the digital terminals Figure 3 1 21 DKT interface circuit 29 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM L Music On Hold MOH circuit IPLDK 60 provides two MOH sources that are internal MOH and external MOH It will operate control signals from CPU MOH SCLK MOH SDATA R492 R493 control the speed of operation Music play U50 Internal MOH is generated by Music 050 and is routed to input port VINA of SICOFI 09 for A D conversion INT MOHC 1s Music sources Figure 3 1 22 Internal MOH circuit External signal from audio jack PJ1 is routed toSICOFI 011 for A D conversion and then digitized data is transmitted to a time slot of PCM highway Audio transformer T4 protects the secondary circuits from high voltage surge EXT MOH Figure 3 1 23 External MOH circuit M External Paging circuit External paging signal is generated by SICOFI U11 that extracts paging data from the specific time slot and converts it to analog signal Audio transformer T5 protects the secondary circuits from high voltage surge and page signal EXT PAGING is connected to external audio instrument through modular jack PJ2 14 2431 EXT PAGE Figure 3 1 24 External Paging circuit 30 ipLDK 60 SERV
118. gnments of CN1 CN2 and CN3 for CSB316 A1 A10 A12 A 21 5 11 Reserved PFT CTL PFT control signal 1 VD Pereng B6 MPX_RX1 PCM bus RX voltage 2 5 5 MPXB TX1 PCM bus TX sv Power We Write Enable A2 A4 A23 A2 B9 BOE Out Enable 5 GND Ground B3 B23 3 Power Option Chip Select A5 A6 A7 A8 1 4 2 MHz Clock for Option A13 A20 DD 0 DD 7 Framesync for Option Data out from POL DET 1 Polarity Reversal Detection 1 CMU DETI CMU Detection 1 POL DET2 Polarity Reversal Detection 2 CMU DET2 CMU Detection 2 POL Polarity Reversal Detection 3 CN3 CMU DET3 CMU Detection 3 CMUSOPR tow power CMU12PR GND Ground CMU BOARD1 2 CMU Detection 1 amp 2 SMS IN1 CID Signal path 1 SMS IN2 CID Signal path 2 SMS IN3 CID Signal path 3 OPEN Reserved 12 16SET 12 16 select F CO3T CO 3 Table 3 3 2 Pin assignment of 1 CN2 and CN3 CHB308 51 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM Pin assignments of CN4 and CN5 for SLU8 Connection A178 5196 5116 SLT9 SLT16 Ring B1 B8 6179 T SLT16 5119 51116 Tip 10 SLU COEDC DET A11 B11 VD B10 B12 A2 A9 SLT HOOK9 SLT Hook9 B2 B9 RING RLYO9 Ring 9 SLT HOOK16 Hook16 RING RLY16 Ring Relay16 CN5 A15 8SLU DET SLU8 Detection B15 GND Ground Table 3 3 3 Pin assignment of CN1
119. he voltage level between Ring and at PT1 PT11 Check the components are damaged or not Note 1 021 C241 R251 8261 Q31 8301 8311 8331 RL11 R201 R211 161 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 2 Hook sensing check Connecta SLT toa SLT Port 1 and hook off Yes Dial tone heard NO Check the voltage level of VLD at R501 Check the components are damaged or not Yes Perform Line feeding check Check hook sensing circuit Note 1 0110 R291 R281 C251 R501 R503 162 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM NO Ringing state Check the components SEL HOOK U110 pin 1 2 Check hook sensing Circuit during ringing Ringing state Check the components are damaged or not 1 U110 R281 C251 2 R221 R231 R291 C221 021 163 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 3 SLT Ring path check Connect a SLT to a SLT port and hook off Line feeding check Call to tke Check the Ring path Ring sound heard R221 R231 RL11 R201 211 1 PT11 and 010 U5 06 Y NO es 164 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 4 SLT Voice path check Check voice signal VIN amp VOUT at 279 part around U2 and U3 Check the circuit around U111 U113 U115 U117 U2 amp 03 Check the ci
120. hrough 8bits 84 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM HPI The DSP requires SRAM U51 256K X 16bits 8ns for data memory Oscillator X5 generates 20MHz clock and provides it to DSP through Spread Spectrum clock generator U23 PLL block of DSP multiplies it to generate 100MHz internal core clock 592 CLK20M_DSP1 180 R343 E Wa CLK20M DSPO 9 01 Figure 3 9 5 DSP Clock generation 2 and FPGA circuit The ACT 2 is a custom Mixed Signal ASIC device used to construct a small to medium size digital kev telephone svstem It is designed to support most functions of the digital key telephone system by enhance existing ASIC device 1 The ACT 2 provides three major functions of GSXD DBID and GSL12 And also the ACT 2 has on chip DSP and memory to support DTMF CPT and CID detection and generation The DBID Digital Back plane Interface Device part of the ACT 2 provides high speed synchronous data channels for inter card and control communications The device also provides the mechanism for transmit and receive highway time slot assignment for the system B and D channels The micro controller on VOIB controls the ACT 2 on this peripheral board directly by initializing internal registers through CPU interface block MPX bus of the ACT 2 are TXBO and RXBO labeled with MTX and MRX transmits receives 32 channels of PCM data to from buffered serial port BSP of DSP Eight channels 4 for VOIB and 4 for VO
121. ides it and bi direction buffer U3 converts 5V data bus to 3 3V bus and vice versa 74 ipLDK 60 SERVICE MANUAL DIGITAL KEV TELEPHONE SVSTEM Us Dia TCT4LCY245ET Figure 3 6 2 Level buffering circuit D Flash memory NAND Flash memory U2 256MX1ea stores voice data compressed with 32Kbps by DSP and provides about 136 minutes of recording time 3 6 5 Connector VMIU AAFU has a connector for interfacing with MBU Pin assignments of connector CN1 is the same with other side of MBU except that A5 and A16 pin is tied to ground for VMIU board detection Figure 3 6 3 VMIU AAFU Layout Connector Pin CNNT Description Description CNNT Pname Description _ Number l VD 1 VD 8 RDY BUSY Ready Busy B14 A 10 Address FLASH WP Flash Memory Write Protect B15 VMIU DET VMIU Detection c zi p Master Switch B16 AAFU DET AAFU Detection FLASH CLE Flash Memory Command Latch Enable FLASH_ALE Flash Memory Address Latch Enable Table 3 6 2 Pin assignment of CN1 75 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 3 7 MODU Modem Unit 3 7 1 General The MODU MODEM Unit provides serial communication for remote maintenance and PC Admin It supports V 34 V 32bis V 32 V 22bis V 22 V 23 and V 21 Data Mode Therefore it operates in full duplex asynchronous modes at line rates up to 33kbps 3 7 2 Block Diagram amp Description
122. igher than 3 9V ZD31 plus forward voltage of diode in 030 octal buffer 030 gets turned on Likewise the voltage applied to R621 input pin 3 of comparator goes down to below VLD and then the SLT signal becomes low The values of VLD and VRD should be set properly in consideration of ring trip loop length and etc Here IPLDK 60 VLD 21 6VDC VRD 16 3VDC The ring signal passes resistor R521 and is sent to the SLT line through the 11 2 ring loop relay The Ring Loop relay is controlled by the output signal RING from U93 and relay driver 053 ULN2003AD COM VO E 118 1 Hf RING gt Nu lt B lu gt gt SLT HOOK FT RoT 9 1K 591 Ter LN Figure 3 1 20 Off hook sensing circuit K Digital terminal interface circuit The digital terminal or Digital Key Telephone interface circuit is composed of the GSL12 block of ACT2 a matching transformer capacitors resistors and a poly switch It provides a connection with two wires to one digital terminal Capacitors and diodes are used for protecting line interface circuit against ESD or lightning surge It provides 30V power to the digital terminal through the transformer and the poly switch is used to protect the over current due to line shortage The _0 TXP 15 _0 15 pins of the GSL12 block of ACT2 on the MBU are output terminals and used to transmit a di
123. igure 3 9 3 CPU Clock generation D DSP circuit The AC48204 voice processor supports low bit rate voice fax and data communication for up to four independent PCM channels For voice transmission the system receives digitized voice originating from an external PCM codec and compresses it to one of the supported standards Fax and data transmissions are automatically detected and demodulated by the integrated NetFax Engine The 48204 transfers the resultant bit stream for every channel in packets to the Host processor through the integral Host Port Interface 48204 performs receive and transmit operations simultaneously receives compressed and packetized PCM speech from a remote VOIP unit through the Host Port Interface It decompresses the PCM speech and transmits it through the PCM voice interface It also re modulates and transmits fax data signals to the fax machine or data modem in analog form The fax data relay process is transparent for the transmitting and receiving fax machines or data modems 482 F RN MSTRB Figure 3 9 4 AC48204 Block diagram Voice interface is implemented by buffered serial port BSP of DSP that consists of PCM In BDR PCM Out BDX 2MHz clock BCLK and 125us Frame BFS signals The BSP is connected to MPX PCM bus MPX MTX 2M CLK and F SYNC of ACT II U7 Micro controller of VOIB controls DSP operations and transmits receives compressed data to from DSP t
124. ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM DIGITAL KEY TELEPHONE SYSTEM SERVICE MANUAL MODEL ipLDK 60 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM Table of Contents SECTION 1 GENERAL DESGHRIPTIONL Te boXSTEMCONNEGTIONJDIAGRAM ciao ce Sanct hos dete dance Used es tu ia coste bou ds 2 122 SPECIAL ATTENTION OF NOTICE ___________ tatha 3 FEATURES odia uo 3 SYSTEM SPECIFICATIONS ie gt 4 1A l General TM TETTE LEE 4 1 42 Efivironment SDS CICA ON 5 ER 5 TS OVS TEN CONFIGURATION a 6 Configura liO 2 oo mm 6 1 5 2 System a 7 SECTION 2 SYSTEM OPERATION THEORY J Zl VOTE NAR CFI EC TURE tt pasay m ata hi 9 2 1 1 General Descrip Ho yu u ____ _ ___ B fu 9 SS 9 2 Il 9 Capacity ESaUOS cC pc 10 PE 11 ZZ Il DIAN S An IIS CUI me 11 2 2 2 ONAIING 5 __ ____ _ __ __ ise 11 ZO ADMINISTRATION i
125. itching IC 2 PCM CODEC on the CO and Station board needs frame sync 2MHZ clock and bus signals for interfacing voice B channel bus called MPXB with ACT2 b Chip selection signal to access CO and Station boards like CHB308 CSB316 and SLIB8 active LOW c Multiplexed Bus MPXB is voice B channel bus that is for interfacing voice CODEC chipset with main switching IC MPXB consists of 32 PCM timeslots and its transmission rate is 2Mbps MPXB RX is PCM signal from various voice chipsets on the peripheral boards to AC12 d MPXB TX is PCM TX signal from AC T2 to various voice chipsets on the peripheral boards e 45V buffered write enable byteO signal that is asserted LOW for CPU to write data to 8bit peripheral devices f 45V buffered output that is read enable signal that is driven to LOW when CPU reads data from peripheral devices g FRAMESYNC OPTION is 125us frame sync signal to mask 16 PCM time slot out of 32 time slots of MPXB bus h When any and Station board is installed OPTION DET1 2 is driven to LOW for CPU to detect CO and Station board installation 36 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 3 MODU installation Pin Name Description PPRESET MODU Framesvnc for MODU 30V Power 2 MHz Clock for MODU i GND Ground TX PCM bus TX B9 MPXRX PCMbusRX _____ o ee Tab
126. le 3 1 9 Pin assignment of 4 a 8KHz frame signal to mask slot assigned to MODU channel b Inversed 2MHz clock signal from main switching IC 2 on the 4 VMIU AAFU installation B6 VMIU DSP CS DSP Chip Select VD 1 VD 8 CN5 A 11 RDY _ iN Ready Busy B14 A 10 Address FLASH WP Flash Memory Write Protect VMIU DET VMIU Detection FLASH CE Flash Memory Enable Master Switch AAFU DET AAFU Detection FLASH CLE Flash Memory Command _ Latch Enable B13 FLASH ALE Flash Memorv Address Latch Enable Table 3 1 10 Pin assignment of CN5 a Inverted 2MHz signal from ACT2 b 8Khz Long frame signal from ACT2 37 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 5 RS232C connection There is a serial port in MBU for diagnosis It is connected to the 1 UART port of CPU The serial port supports all hardware flow control signals such as RTS CTS DTR and DSR Pin Number Pin name Description PinNumber Pin name Description 1 CD Reseved 6 Datta Ready 2 RD data Request to Send Transmitted 8 1 CTS Clear To Send Data Terminal Ready __ 9 Reserved Signal Ground le E Table 3 1 11 Pin assignment of UART 8 6 PSU installation 6 7 GND Ground Table 3 1 12 Pin assignment of CN7 38 ipLDK 60 SERVICE MANUAL DIGITAL KEY
127. llow unlimited 3 party conference at the same time Gain modification is performed by the switching block A look up table stored in ACT2 permits PCM words to be adjusted for the circuits receive volume level The gain word volume level is used as the Gain ROM index with the PCM word as the address The output from the Look Up Table is the gain modified PCM signal which is placed on the appropriate receive B channel 15 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM SECTION 3 Circuit Description 3 1 Main Board Unit with CO 3 1 1 General The MBU is the Main Board Unit of IPLDK 60 It provides basic CO Station and extension interface circuits physical connection with various boards and also miscellaneous functions The MBU is composed of a main processor and its peripheral circuits the three CO interface circuits a Digital Keyset Unit DKT interface circuit 7 hybrid circuits that are selected to DKT or SLT ports by Modular Jack pin assignments a Ring Generator circuit a system battery backup circuit two general purpose relay contact an internal MOH an external MOH an external PAGE an alarm sense and the master clock generation circuit as well as system s PCM voice processing circuit that has custom switching device ACT2 for PCM tone generation and PCM Gain control And it also has various connectors to install CO extension and function boards switches modular jacks and etc Basically the MBU provides the capacit
128. lue logic that is composed of U18 and 020 generates DSP chip selection signal for DSP U35 DSP requires read write signal R W to to low before chip selection signal DSP CS The HPI interface port is composed of chip selection DSP CS read write enable signal BWBEO 8bits data bus HDO HD7 HPI control register decoding signals HCNTLO and HCNTL1 and low high byte strobe signal HBIL 3 3 3 m WOM lui 90 ES 2 NS C C22 ES 33 UALR HES gt 22 S gt HCNTLO R467 22 AACS 6 gt 1 AA 0 2 gt gt anYr HEIL 3 3V Me HRDY Figure 3 5 19 DSP HPI interface circuit 67 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM J Internal telecom ports The E1HB8 board provides 8 hybrid ports that can be used to connect SLT through modular jack MJ2 8 interface circuits are placed the E1HB8 and SLT interface board SLUS that has 8 SLT interface circuits is basically installed on connectors CN6 and CN7 of E1HB8 The main CPU on the MBU controls all functions needed to support 8 hybrid ports and the decoder IC U22 is used to select one of 4 I O buffers gt SLT RLY 32 BOARD INFO S5 SLT HOOK DET Figure 3 5 20 5108 decoding circuit The CPU downloads DSP coefficients to PCM CODECs in the SLU8 board and read registers from them with data latch buffer U37 Blue LED LD10 on Pin 14 of
129. ments The analog transmitter T3 transforms the unipolar bit stream to ternary alternate bipolar return to zero signals of the appropriate programmable shape The unipolar data is provided by the digital transmitter 3 34 F El ALL 15 ER CELIE 52265 l ERI 8 e M Aii NE 1 TX4 04 DE RL 2 lt IX Figure 3 5 13 FALC 56 line interface Diodes DA D7 and poly switches PT9 and PT10 are to protect FALC amp 56 PEF 2256 from high voltage surge electrical fast transient burst and AC power induction G Phase Locked Loop circuit The PLL circuit has a role in generating system master clock 32 768MHz for PCM system in free run mode synchronous mode The master clocks CLK32M and MCLK32M are provided to switching devices ACT 2 on the MBU and E1HB8 and they generate various system clock signals 64 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM In free run mode where line is not activated VCXO Voltage Controlled Crystal Oscillator X3 generates 32 68MHz VCO OUT VC signal fixed to 2 5V with 1 accuracy On the other hand VCXO is controlled by comparator output that is generated by exclusive OR computation with internal feedback clock Q6 of U16 and extracted reference signal SIGNAL IN of U11 from E1 bit streams in synchronous mode Analog switch U1 selects VC control signal to 2 5 VC or COMP OUT by CPU clock selection signal CLK SEL an
130. mp Hybrid 8DKTs amp 8SLTs Port CMUBOPR 50Hz 12 16kHz Call Metering Unit 12PR amp Polarity Reversal Detection 3 chs E1HB EIR2 and 8 Hybrid Basic KSU BKSU Basic Key System Unit Terminals MBU Main Board Unit IDKT 7Hybrid ports Digital KTU LDP 6012D amp LDP 6030D LIP 6212D amp LIP 6230D LDP DSS LDP DPB PSU Power Supply Unit 90W SLTs FAX Modem RS 232C LAN External Page amp External MOH Figure 1 2 1 System Configuration ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 1 5 2 System Components BASIC KSU ITEM OPTION BOARD DESCRIPTION Service Unit Power Main Board MIET Extension Boards SLIB8 E1HB8 and VOIB Other Boards Boards VMIU AAFU MODU CMU50PR CMU12PR can be installed COLineand 3COLinesand8HybridinteaceBoard Extension Call Metering 50Hz and Polarity Reversal Detection Unit Boards 3 channels CMU12PR Call Metering 12KHz or 16KHz and Polarity Reversal Detection Unit 3 channels CSB316 3 CO Lines and 16 SLT Interface Board 3 channels Call Metering 12KHz or 16KHz and Polarity Reversal Detection Unit 3 channels 8 SLT Interface Board NE N 7 7 Other Boards VoiceMailnterface Unit 4chanels _ af L Annimali MODU MODEM unit 33Kbps 1 MODEMUnIEB8Kbp
131. mponents FB16 FB21 Check the signal measured at ROUT of U12 NO Check the components around 012 and CPU U1 Replace damaged part Note 1 A standard serial interfacing for PC requires negative logic i e logic 1 is 3V to 12V and logic 0 is 8V to 12V 111 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 1 18 CO interface circuit sheet 5 10 1 CO Dial tone check 1 st Port CO line is connected oeizure the CO line YES Dial tone NO Check the CO line connection Correct the connection amp RLA Good NO Connection YES Check the CO fusible Resistor R401 R406 Change the Resistor R401 R406 Yes Check the Transformer wire impedance T1 T3 Change the transformer ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM Check the loop current circuit Q16 Change the TR Check the loop current Check the circuit amp Ring detection signal _LOOP_RING around U100 R431 R451 R452 Check R955 U51 U86 R777 U8 are damaged Yes Check signal VIN amp VOWT at 2 9 part around U9 Check 471 472 451 462 471 R481 U101 R804 are damaged or not 113 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 2 CO Ring detection 15 Port PORT 1 Check the incoming ring path Check the components 1 are damaged or not Can you see ring signal at 1 of
132. n NAND flash memory The length of recorded announcements is monitored and recording is stopped if the maximum announcement length for the message being recorded is exceeded 2 4 Call Processing 2 4 1 Internal Call Types A Intercom Intercom calls begin with a station going off hook The station or station board receives the off hook data and communicates to the MBU In response the MBU places digitized intercom dial tone on a B channel The station or station board in turn switches this B channel to the requesting station which converts the digital signal to analog audio and the station hears the dial tone When you dial digits or press button on the phone the same communication exchange from station or station board to MBU and back take place It informs the MBU of the request such as dialing an intercom number The MBU then checks the scratch pad memory for status of the dialed phone and a connection is established by assigning transmitting and receiving B channel pair for both stations Or a call progress tone is sent to the initiating phone such as busy tone B Paging Paging is a programmable feature either enabled or disabled in customer database programming When a station places a page request the MBU must check scratch pad memory at first to determine if the page zone is busy Then the customer database programming must be checked to determine if the station is allowed to initiate a page and to determine which stations are to re
133. nal refer to above picture will be changed different value low become high high become low Default value of Call Metering 50Hz is high It means that OFF state of Call Metering 50Hz is high And then the CPU on MBU indicates the Call Metering 50Hz signal 79 ipLDK 60 SERVICE MANUAL DIGITAL KEV TELEPHONE SVSTEM C Call Metering 12kHz or 16kHz detection part Ina 1 C XEBIDA XT AI DD YOD CMU lt 3 579546 2 SYSTEM SELECT gt ml CHI DE RG SMS IMI gt CHI ENABLEN gt 158 PS5 CH1 AMP IM CH2_AMP_OUT 2 AK pen CH1_AMP_IN CH2_AMP_IN os _ IN ESMS CON gt 6049565 RET Tur 1OGK ET2 504955 100E 271 1GE SMS gt EW c7 zu 198P wios _ Les ATAL H 8 1 2 xTALN SYSTEM SELECT HS 12 16SET 7 _ wi cHU DET3 A cut oP H 5 SMS IN325 4 Yr EAE gt AMP OUT ENABLEM w 1 J FEM cH1 AMP IN AHMP OUT gt R54 CH1_AMP_IN CH _AMP_IN HE 2 4K vss CH2 U1TOE 4 Ora B 12 GO4AGES _ gt dL g Ba si Figure 3 8 5 Metering 12KHz or 16kHz detection circuit 5 TOBE a This section describes 1st port related 1st CO as an example
134. ng regulator U5 and this switching regulator generates battery charging voltage 27 3V with current limitation of 100mA And this voltage can be changed by adjusting the variable resistor VR1 When the AC input power fails the pin 1 of 06 goes low and it turns the FET Q3 on for supplying the system power from external battery If battery voltage goes lower than 21 5V the 1 of U1 goes high and it turns the Q3 off and this situation protects the battery from over discharging The battery discharging voltage can be adjusted by using variable resistor VR2 Fuse F2 250V 5A protects the system from outside short circuit Figure 3 10 3 Backup batterv circuit 91 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 1 MBU SECTION 4 TROUBLESHOOTING 1 MBU 1 1 Power check from PSU VO 30V 5V 5V VO 30V Check the voltage level measured at pin 2 of CN Check the PSU amp Parts shortage or Damaged IC Check the voltage level measured at pin 3 4 of CN Check the PSU amp Parts shortage or Damaged IC Check the voltage level measured at pin 5 of CN7 Check the PSU or Damaged IC YES Note Check the resistance MBU without connecting PSU 5 8 GND 1Kohm or more normally 1 END 3 3 8 GND 200ohm or more normally 210ohm 1 8V GND 300ohm or more normally 380ohm 92 ipLDK 60 SERVICE
135. node of D138 Ring Check the Darlington circuit 0137 0138 053 058 E Check the signal Ring measured L2 Check RC filtering circuit C820 L2 and etc 4 cy Freg 24 990 Hz 791v END 09 24 41 Ring signal 25Hz 50Vrms 109 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 1 17 Serial RS 232C Port check 1 Transmitting side System TX PC RX sheet 9 10 Check the signal measured at Input pins T IN of U12 YES ASCII character code Check input and output signals of buffer 1 035 and RS232C converter U12 Check the RS232C signal measured at IxOUT of U12 Check the components U12 C802 C805 amp 1 Buffer IC U35 converts 43 3V signal from CPU to 5 0 signal 2 A standard serial interfacing for PC requires negative logic i e logic 1 is 3V to 12V and logic 0 is 8V to 12V 110 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM sheet 9 10 2 side PC Svstem Check the RS232C signal measured at Input pins R IN of U12 12 YES ASCII character code Check serial cable from PC and baud rates Replace co
136. o synchronize slave 2 the E1HB8 with master AC T 2 in the c System back plane bus called Inter Svstem Connection ISC is composed of several highway signals TX ISCZ and 15 reference clock CLK8M and synchronization signal EXP FRAME and each highway signal incorporates HDLC channel and 48 B channels for voice switching TX ISC2 stands for TX highway signal 2 RX 15 2 for RX highway 2 and so on d MA and MD address and data bus from to main CPU in the MBU to control 8 SLT interface board 5108 M M OE and PP CS control signals for MBU CPU to read write buffers to control SLU8 DOUT Data out from PCM CODEC in the SLU8 MBU CPU reads or write the data with DIN DOUT DCLK and _CS DIN DCLK and GS signals are made from output latch buffer U37 g M MPX RX TX PCM highway from to MBU ACT 2 that carries multi channels of voice data for PCM CODEC h PCM highway called MPX bus operates with frame signal M FRAME and data clock M CLK2M i is digital terminal interfacing signals from MBU 2 for 8 hybrid ports PIN Pinname Description PIN PinName Description A1 A8 SLT interface Ring B1 B8 SLT interface Tip AQ Open A9 Be Opens CODEC detection ii 30V power 30V power Table 3 5 6 Pin assignment of CN6 70 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM Lew Pinmame Descipion _ A1
137. ohm 1 16W J 1608 R TP 0000474 30K ohm 1 16W J 1608 R TP 239 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM R261 268 R301 308 0000663 RES CHIP EEC Es mess a nome serm ws 34063 0 50 8 8 PIN R TP DC TO DC CONVERTER CONTROL 3 dE IC CIRCUITS 220 uF 50V M SMS STD 10 12 5 5mm JE610 A2 54 626 26 PIN STRAIGHT 2 54 mm JE610 A254 G30P 30 PIN STRAIGHT 2 54 mm i sess JIE e 240 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM CONNECTOR HOUSING TO 2 ENNY0001503 BOARD GIL G 4P S3T2 E5 4PIN 2 5mm STRAIGHT ED8782 P0004 VCXO FQD 2 EXST0000501 TCXO 198 205 ECCHO000343 CAP CERAMIC CHIP Ca CI CT L a omen 32 768MHZ 32 768 2 30PPM 15pF RAD 20 7 13 06 5 1 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 241 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM Lie ew 7 CANTE US TRE ms i 956 SAE BM RIPE Lu usw 3k RER ATO ewm eee TC74LCXOBFT TSSOP 14 PIN R TP LOW VTG QUAD 2 AND U5 U17 U20 EUSY0049301 TC74LCX32FT TSSOP 14 PIN R TP LOW VTG QUAD 2 INPUT OR ee MC74ACT138DTR2 TSSOP 16 PIN R TP 3 TO 8 LINE yl CT FUSY0050001 TCTALOXIAFT TSSOP 14 PIN R
138. onnect a SLT toa SLT Port 1 and hook off Dial tone heard Yes NO Check the voltage level of VRD amp VLD NO 1 VRD 16 3V amp VLD 21 6V a Perform Line feeding check Yes Check a hook sensing circuit Note R 2097298 136 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM sheet 4 5 7 NO Ringing state Check the components SLT HOOK Low are damaged or not Check a hook sensing Circuit during ringing Ringing state Check the components HOOK Low 2 1 0110 R581 8621 C551 R591 2 0104 R521 8531 C521 021 2031 3 Ring path check Connect a SLT toa SLT port and hook off Line feeding check Call to the SLT Check the Ring R521 RL11 R501 R511 and 014 Ring sound heard Yes 13 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 4 SLT Voice path check Check voice signal VIN amp VOUT at 279 part around U2 Yes Check the circuit around U111 U3 Check the circuit around T11 MHz FRAMESYNC MPXB T MPX RX normal 4 No Check U111 amp ACT2 U8 U21 U42 R207 R260 Yes 138 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 3 CHB308 3 CHB308 3 1 CO Dial tone check CO Off hook Yes NO Check the CO line connection Correct
139. onnector PiNNumber no SignalName MJ2 1 DKT Only ee TI 3 RN An MJ2 2 3 4 5 6 7 8 Hybrid SLT N A 1 Ta NOTE When installing or SLT on Hybrid Ports MJ2 2 3 4 5 6 7 8 keep the above pin assignment Otherwise the DKT or SLT will not operate normally LAN 4 5 7 457 8 RESERVED NE A e sss 6 Re ReeveDsa 34 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM SWI Functions The default is all ON The MBU also has a four position DIP switch SW1 The function of each switch position is as follows Default setting All ON position SWITCH FUNCTION OFF ON DEFAULT Command Event Trace Software Testing Simplified Message Desk Control SMDI Voice SMDI ON SMDI OFF Table 3 1 5 SW1 functions Before programming the system switch 1 4 should be placed in the ON position and power cycled off and on to initialize the system database to default Once the database has been initialized switch 1 4 should be placed in the off position and put SW2 for the lithium battery on so as to protect the database B LED indications The 5 LEDs mounted in the MBU provide diagnostic information for states of the board The below table shows the meaning of various states of LEDs LED MEANING LD1 Blue Periodic Toggle ON 300msec OFF 300msec LD2 Blue In Use or Idle Status ON One or more Port s in use OFF idl
140. opposite way Regulator U4 generates 3 3V power for MODEM chip MODU has a connector for interfacing with MBU Pin assignments of connector are the same with other side of MBU Figure 3 7 2 MODU Layout 3 8 CMUSOPR CMU12PR Call Metering 50Hz and Polarity Reversal Detection Unit Call Metering 12 16kHz and Polarity Reversal Detection Unit 3 8 1 CMUSOPR Call Metering 50Hz and Polarity Reversal Detection Unit The Call Metering 50Hz and Polarity Reversal Detection Unit CMUSOPR provides 3 Call Metering Detection circuits for 50Hz and provides 3 channels of Polarity Reversal Detection for Call Metering or signaling It can be installed on MBU EMBU CHB308 and CSB316 3 8 2 CMU12PR Call Metering 12KHz and Polarity Reversal Detection Unit The Call Metering 12KHz or 16KHz and Polarity Reversal Detection Unit CMU12PR provides 3 Call Metering Detection circuits for 12KHz or 16KHz and provides 3 channels of Polarity Reversal Detection for Call Metering or signaling It can be installed on MBU EMBU CHB308 and CSB316 77 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 3 8 3 Block diagram COIR POL E DETI Polarity Reversal Out1 COIT CMU DETL Gonz Outi CO2R POL mE DET2 Polarity Reversal Out2 CO2ZT CMU DET2 Gonz Out2 POL _ DETS Polarity Reversa 1 Out3 CO3T MU _ DETS3 Out3 Figure 3 8 1 Block diagram of CMU50PR COIR POL
141. perating memory This type of memory is a SDRAM Synchronous Dynamic Random Access Memory and is used for system operating The memory is lost when system power failure is occurred and it is always initialized on system power up 2 3 4 Customer Database Memory The third type of memory is called Customer Database memory This memory is stored in RAM Random Access Memory and is used to store the data and status of programmable features e g line ring assignment Customer database memory is maintained during power failure by an onboard lithium battery It is the customer database memory that must be initialized upon the first installing the system so that a known default database can be used to start building a customized customer database 2 3 5 System Resources System resources are functions made available for users on the system to support features and optional functions on the system A Tone Generation The system generates tones which are available on the system back plane B channels These tones are stored digitally in ACT2 For instance when a station is received intercom dial tone it is commanded to monitor the B voice channel where system intercom dial tone resides This procedure is the same for all tones including ringing tones busy recorder and ring back tones Tones 1 Receivers The system provides the ability to monitor and identify Dual Tone Multiple Frequency tones generated e
142. r passive devices The main functions of this circuit are the isolation of the system side from SLT line side and the gain conversion of voice signal The audio transformer T11 operates in a non saturated condition with DC blocking capacitor C261 Impedance matching is incorporated on the secondary winding of the audio transformer through appropriate RC networks with SICOFI VIN1 and VOUT1 nodes is connected to the analog interface of SICOFI U2 SICOFI U2 provides many functions which are A D conversion of voice signal impedance matching analog amplification attenuation trans hybrid balancing PCM highway interface and etc For more information about SICOFI refer to the datasheet of PEB2466 manufactured by Infineon 47 ipLDK 60 SERVICE MANUAL DIGITAL KEV TELEPHONE SVSTEM ____ Me ee 1 T11 Fab IM 3 gy 4 Gl gt i lu ic 2331 7051 sn 4 8V gal A r EX ti Figure 3 3 8 The SICOFI interface circuit The key devices of the hook sensing circuit are U3 LM2903 comparator and VLD If the called party hooking off after comparing VLD SLT_HOOK1 signal becomes low So the system detects the hook off status SLT signal is active low _ U118 1 L B lu ut l gt fiL T HIoE _ P i
143. rcuit around 111 118 MHz FRAMESYNC MPXB T MPX RX normal U2 U3 Connectidn 165 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 5 2 Rx or Tx Fail check the B13 of 2Mhz ok N z Check the signal source from MBU No Check the U1 U2 U3 amp R21 gt No Check the signal source from MBU Check the U1 U2 U3 amp R22 Yes eck pin 22 32 of U1 U2 U8 2Mhz ok Yes check the B14 of Framesync ok Yes check 31 of U1 U U3 Framesync ok Yes Line feeding check Check the related SICOFI U1 U2 and U3 No 166 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 6 5108 6 5108 6 1 SLT interface circuit 1st port 1 SLT Line feeding voltage 36V check Check the voltage level of Go to power check Routine Check the voltage level between Ring and TIP at 1 11 Check the components are damaged or not Note 1 021 C241 R251 8261 031 8301 8311 8331 RL11 R201 R21 1 16 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 2 Hook sensing check Connecta SLT toa SLT Port 1 and hook off Yes Dial tone heard NO Check the voltage level of VLD at R501 Check the components are damaged or not Yes Perform Line feeding check Check hook sensing Circuit Note 1 U110 R291 R281 C251 R501 R503 168 ipLDK 60 SER
144. rial port PCM switching and signaling control ASIC ACT2 trunk 55 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM interface circuit FAL C56 chip DSP TMS320VC5402 circuit voltage regulator reset circuit and various connectors for extension board 5108 and other functions An extension board SLU8 is composed of PCM CODEC 8 interface circuits 8 SLT interface circuits and 36V feeding voltage generation circuit 3 5 3 Circuit Description A CPU amp System Memory The CPU S3C4530A is 16bit 32bit RISC controller It is manufactured using ARM7TDMI designed by advanced RISC machine Ltd so it has integrated micro processor and peripheral circuits which can be used for various applications It is especially good for communication and networking system It consists of system manager block 2 SCC controllers 2 UART channels 2 channel GDMA 2 32bit timers 18 different input output part interrupt controller DRAM SRAM controller ROM controller and flash memory controller It has 8Kbyte cache SRAM Ethernet controller too S3C453A operates at 50MHz clock speed internally Flash memory U33 operates at 70 access time CPU manipulates programmable register so that it can read and write data There is a code in flash memory so CPU can control system administration and call processing with the code CPU can communicate with the main board that has main processor by HDLC protocol Communication is accomplished by HDLC
145. rminals There is only line interface circuit in the ETHB8 and AMI signals DKT9 DKT16 come from 55112 block of ACT 2 the MBU The below circuit shows the first port of DKT interface circuits in the E1HB8 and the rest ports are same to it 68 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM DKT9_R lt DKT9 T lt lt Figure 3 5 21 Digital line interface circuit 3 5 4 Connectors Modular jacks and LEDs There are various kinds of connectors switches modular jacks and LEDs in the E1HB8 The below figure shows the layout of E1HB8 and the location of connectors switches modular jacks and LEDs 1 LD1 102 103 104 105 106 107 108 LDS B B B B B B B B C The Default is all ON 9 S To DKT or SLT SW3 Svstem reset button Figure 3 5 23 the layout of SLU8 69 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM Pin assignments of CN5 CN6 and CN7 Pin Pinname Description Pin PinName Description A4 GND Ground B4 OPEN A6 MAQ Address2 M MPX RX MPXPCMbusRX M WEO A9 OPEN J CNS PP chip selection MD 3 MD 7 A21 OPEN 81 5 IDKTdatasignal A24 RING __ Ring 25Hz 75Vrms B24 OPEN A25 GND Ground B25 X Table 3 5 5 Pin assignment of CN5 MCLK32M 32 768 2 master clock for master 2 b EXP FRAME is used t
146. roduced in any manner in whole or in part without the express written consent of LG NORTEL ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 1 1 System Connection Diagram ipLDK 60 system can be connected to several externals and internal line for call processing as following Figure1 1 1 oystem connection diagram undi E1R2 LCO l a ipunx mu ee m PC Admin IP Phone 28 VoIP an Internet 3 2 EN LAN 10M Ethernet SSE Hub d VMIU AAFU x Internal 8 Voice ipLDK 60 MODU SSS Internal CET MODEM SMDR Printer SLT Battery m Battery 24V 10AH 1 cilii MOH ext O Music Source U Alarm Sensor e Relav contact Loud Alarm Detection External pager 055 Figure 1 1 1 System Connection ipLDK 60 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 1 2 Special attention of notice 1 Make sure that the power is off and start disassembling the system and board 2 When dealing with PCB check the discharge of human body and deal it with the edge of PCB 3 When changing electric parts IC Capacitor or Etc and connecting the ring signal be sure not to touch the lead wire 4 When assembling KSU check the screw 5 When assembling KSU check the cable
147. rom ACT 2 to inform CPU that ACT 2 is ready for data transfer BWBEO1 Write enable signal for 16bits data access 191 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 9 1 11 E1 interface circuit 1 Operation frequency check Tr Start Check the frequency of the signal measured at Change the X4 pin 3 of X4 NO 8 192MHz valid Yes Check the frequency of Check U24 and its peripheral circuit the signal measured at Replace damaged part around X4 pin 73 of 024 FB16 R373 NO 8 192MHz valid Yes A Pone 16 04 31 2 timing check Start Check the waveform of Check BFRAME signal at U34 U13 FRAME at Pin 6 of 024 Replace U15 or U18 if damaged NO Is it right shape Yes N END NN PEB FRAME Trigger Sample Edge a A Edge SCLKR 8192 MHz 192 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 3 TX amp RX Fail Sheet 5 7 Start Check transmitter ternarv signals XL1 and XL2 Check line resistors R95 R98 No Protection diodes D6 D7 transformer T3 amp filter T2 and poly switches PT10 Replace damaged part Waveforms are same to right waveform Yes DC bias around 1 Check receiver ternary signals and RL2 Check termination resistor R99 No Protection diodes D4 D5 transformer T3 amp filter T2 and pol
148. rvision time the system disconnects the call 14 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 2 4 3 Conferencing Conferencing is accomplished on the ipLDK 60 system by using switching block of a special custom integrated circuit called the ACT2 This device uses a technique that involves the real time digital summation of two ports conferee s PCM data That is the digitized voice is added together in a digital format and then placed on the appropriate B channel For a 3 party conference ports A B amp C port A will require that ports B amp C be summed and placed on the receive time slot for port A Port B will require that ports A and C be summed and placed on the receive time slot for port B Port C will require that ports A and B be summed and placed on the receive time slot for port C This provides a feature of 3 party conference on the system Since the system is designed to provide up to 3 parties in a conference the switching block on the ACT2 was incorporated to provide this function The digital summation process can store its output into this function The digital summation process can store its output into this conference memory of switching block The memory is large enough to support many digitally stored summations The summed conference memories can then be used as one or both inputs for additional summations and its output stored in memory again or placed on a B channel Conference memory is large enough to a
149. s Ne na 3 channels Call Metering 12KHz or 16KHz and Polarity Reversal Detection Unit 3 channels ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM EXPANSION KSU ITEM OPTION BOARD DESCRIPTION x KU Key Service Unit 0000 Power Supplv Unit Main Board EMBU Expansion Main Board Unit 3 CO and 8 CO and Extension CO Line and DK T SLT interface Boards Boards CHB308 CSB316 SLIB8 Other Boards CMU12PR CMU50PR be installed BEEN 3 CO Lines and 8 Hybrid Interface Board CMUSOPR Call Metering 50Hz and Polaritv Reversal Detection Unit 3 channels CMU12PR Call Metering 12KHz or 16KHz and Polaritv Reversal Detection Unit 3 channels CSB346 3 CO Lines and 16 SLT Interface Board CMUSOPR Call Metering 50 Hz and Polaritv Reversal Detection Unit 3 channels CMU12PR Call Metering 12KHz or 16KHz and Polaritv Reversal Detection Unit 3 channels SLU8 8 SLT Interface Unit Installed on CSB316 as a default SLIB8 KOSTA 8 SLT Interface Board Other Boards CMUSOPR Call Metering 50Hz and Polarity Reversal Detection Unit CO Line and Extension CHB308 Boards 3 channels CMU12PR Call Metering 12KHz or 16KHz and Polarity Reversal Detection Unit 3 channels ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM Section 2 System Operation Theory 2 1 System Architecture 2 1 1 General Description ipLDK 60 i
150. s A EXP ISC Highways EXP Inter Svstem Communication EXP ISC Highways are buses on the back plane that distribute digitized voice and signaling data and carry out board level communication throughout the system connector s These highways are provided in transmitting receiving pairs and there are a total of 3 highway pairs in ACT2 Communication on each highway is at 8 192Mbits per second in a time division multiplexed format Time division multiplexing creates channels or time slots that carries digitized voice signaling data and High Level Data Link Control HDLC protocol information Voice B channels carry digitized voice signals Signaling D channels are employed for channel specific signaling implementation B Channel Allocation The Main Board Unit MBU determines which time slot on which ISC highway will be used to transmit and receive B and D channels information for all stations and circuits The DBID 65112 block in ACT2 the B and D data onto the system highway at the appropriate time slot Any port can be assigned to transmit on any transmit B channel and receive on any receive B channel The D channels can also be flexibly assigned and controlled independently of the B channels The HDLC inter board communication channel on each highway is also controlled by the main processor on the MBU and placed on the highway by the DBID on peripheral board C Voice Channels PCM signals received from the digit
151. s F ovac YES Check 32 768MHz Pin 6 of U21 32 68MHz Check the circuit around U21 no and replace damaged part Yes Check U38 and CLK_SEL signal Replace damaged part END 184 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM When is activated Check the red LED LD9 is ON Check CLK SEL signal from CPU CLK_SEL 0 External clock 1 Internal clock 1 YES NOTE CLK_SEL is clock selection signal from CPU and selects clock source to internal clock or extracted clock When line is activated and no errors are detected extracted clock 18 selected by control signal of CPU When internal clock is selected reference DC voltage 2 5V makes VCXO X8 operate in nominal state 2 Functional check Sheet 5 7 Sheet 5 7 Lo the voltage level measured at Pin 6 of 010 NO b the circuit around 039 C NOTE U39 MIC5205 3 0 3 0V regulator with 1 accuracy 2 5 VC is generated with divide resistors R784 and R785 185 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 9 1 7 System Highway structure Sheet 4 11 244ns FRAMEOUT 122ns 244ns 8MHz System highway clock oe 1 2 3 4 5 6 7 258 1 8 sub frames 1HDLC 1D 48B HDLC 512Kbps or 1024Kbps when D channel is used as HDLC 8bits x 8 sub frame x 1 125 512Kbps D Ch r
152. s a Hybrid Digital Key Telephone System designed to provide digital voice transmission It uses a digital switching architecture A Main Processor CPU on the MBU directly controls Option boards and expansion KSU The custom main switching device ACT2 ASIC incorporate a DBID block and two GSL12 blocks for the basic voice connection of network and extension and features voice switching conference and voice gain tone control Basically a PCM highway called MPX bus that is provided by ACT2 and is composed of 32 PCM time slots interfaces general voice PCM CODEOCs Essentially the DBID block is a Multiplexer Demultiplexer providing the ISO layer 1 transport mechanism for the B and D channels through the system The Main Processor directs the ACT2 to control switching on each board CODECs are used to convert analog voice signals into Pulse Code Modulated PCM digital signals and to decode digital signals back into analog signals All routing of voice signals through the system are accomplished in the PCM digital form Control Signals and digitized voice signals for each channel are routed throughout the system on the back plane in a Time Division multiplexed format TDM TDM is a method of utilizing the bandwidth of a transmission line to its fullest capability by transmitting many channels of information over the same link There is a unique time interval for the transmission of each channel Each channel is sometimes referred to as a time slot
153. s echo jitter and latency by utilizing the H 323 Rev 3 fast protocol The QoS is equal to or better than Toll Quality achieved by automatic online adjustments to customize each call The VOIB provides basic four VOIP channels and has a option board VOIU that provides additional four VOIP channels 81 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 3 9 2 Block Diagram Block Diagram of ipLDK 60 VOIB Clock 32 68MHz Address Transcodec Function MRX AC48204 PEN TXISC1 RXISC1 FRAME 1 120 15 512KHz HTXD HRXD Clock SRAM 20MHz 256Kword HDLC L Option VOIU DOHOMZZOO 48204 I AVTOCUT q 1 a EZ1587 SE m 100 15 m ou TPse2000 8 548 SRAM 256Kword Figure 3 9 1 Block diagram of VOIB 3 9 3 Circuit Description A CPU and Memory 3C2510A 16 32 bit RISC micro controller is a cost effective high performance micro controller solution for Ethernet based systems for example SOHO router internet gateway WLAN AP etc A variety of communication features are embedded into S3C2510A required in many communication areas including two Ethernet MACs three TSAs supporting IOM2 two high speed UARTs a console UART and USB A security feature is also supported by DES 3DES accelerator Fast devices with 7Ons access time are required for 2 wait system
154. stem Analog voice communication is sent over the single pair of wires from the single line interface boards to the station CODEC on the SLT interface circuits is used to convert digital voice signals to analog voice signals before being sent to the analog instrument and to converts analog voice from the phone to digital PCM signals before routing them through the system 2 1 3 Capacity Limitations A CO Ports It allows max 12 central office lines to be connected to the system B Station Ports The maximum number of station Digital KTUs or SLTs installed on the system is 48 Max 32DKTs 475175 10 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 2 2 Switching 2 2 1 Back plane Architecture ipLDK 60 system has PCM highway called MPX bus to interface voice CODECs on the MBU and Option boards to main switching device ACT2 For extension boards and expansion KSU on which additional PCM highway is needed system back plane architecture called ISC highway provides interfacing custom blocks such as DBID and GSL12 in ACT2 on the MBU The ACT2 has the DBID block and the two GSL 12 blocks that provide a MPX bus and 15 pairs of ISC highways A MPX bus is composed of 36 PCM time slots that are assigned to basic voice CODECs on the MBU and voice CODECs on the CO ports Expansion MBU also has custom back plane interface blocks such and GSL12 to transmit and receive and D channels information for stations and circuit
155. t The system optionally provides digitized voice announcements for system and station features When the Voice Mail Interface Unit is installed on MBU features supported to the VMIU are provided with pre recorded system voice announcements customized hunt group announcements and customized user voice announcements The VMIU provides 4 channels of access to voice announcements All kinds of voice messages are stored digitally on NAND flash memory and related information for voice are stored on RAM that is retained during power failure with a lithium battery on MBU When commanded by the MBU the appropriate digitized voice announcement is converted from compressed digital format to a PCM digital signal and placed on a receive channel The requesting station or system port is then commanded to monitor that channel System software control terminates the voice announcement and frees up the channel on the VMIU when the announcement is completed When storing a customized voice announcement the 13 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM requesting station is assigned a transmit B channel and the VMIU is assigned a corresponding receive B channel The VMIU connects one of its 4 ports to the receive channel and starts monitoring for sound If no sound is detected the recording is stopped and the connection is broken down If sound is detected the digitized PCM voice is converted into compressed digitized audio and stored o
156. t Ethernet connection with PC through modular jack MJ1 for S W development and board maintenance doa PISC ay Ha 38 IE EE 0 MII MDIO COL COL 10M 89 lt MII COL TX_CLK_TXCLK_ 108 lt MIL TXOLK m EE 43 2149 33 41 330 TX TXEN 10M ag SS MIL TXEN TX_ER_PCOMP 10M MIL TXER CEPS CRS 10M 28 lt MII CRS CLK RXCLK 10M RR AEN MII RXCLK RADO 10M 15 lt MII RXD1 RADE lt MII RXD2 RAD 2 MIT_RADS DV LINK 36 MII RXEDWV MIT_RXER ETHERNET 1BBASE T Figure 3 5 3 interface 57 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM The S3C4530A includes one time slot assignor TSA which provides flexible data path control between the two HDLCs and external interfaces The TSA and HDLC channel A not used at E1HB8 The HDLC channel B is used for HDLC communication between main board MBU and peripheral board like E1HB8 and is routed to PCM switching device ASIC ACT2 that has a role in carrying PCM voice data or control signals like HDLC The CPU has two UART blocks that provides two independent asynchronous serial l O SIO ports UARTO is used to monitor system operation by RS232C serial port and UART is reserved UARTO supports 19200bps speed but doesn t provide MODEM control signals such as DTR DSR RTS and CTS To monitor board oper
157. tage rectified 3 PWM Control amp Switching It has skill that occurs to the steady rated voltage from feedback signal according to changing the load and input condition by PWM Also If current is over limit point it controls output by detecting from is pin 4 Transformer Transfer firstly part voltage to secondary part 5 Auxiliary Power Supply Supply with VCC for driving the PWM controller 6 Output Rectifier amp Smoothing Transfer square wave supplied from transformer to DC voltage rectified 5 5V Output DC DC PART 1 PWM Control It has skill that occurs to the steady rated voltage from feedback signal according to changing the load and input condition by PWM Also if current is over limit point it controls output by detecting from is pin 2 Drive Circuit Single pulse supplied from PWM IC provides switching FET with each crossed pulses 3 Switching It drives switching FET by each crossed pulse It is made of Synchronized Buck Converter 4 Inductor Transformer As switching energy driven by inductor is transferred to 5V output part Also as this inductor consisted of transformer it is transferred to 5V output part 5 Output Rectifier amp Smoothing 90 ipLDK 60 SERVICE MANUAL DIGITAL KEV TELEPHONE SVSTEM Transfer square wave supplied from transformer to DC voltage rectified Figure 3 10 2 5V 5V generation circuit D Backup battery circuit The battery charging power is generated by switchi
158. to provide lamp voltage and stepped down to 5 for logic circuits within the digital ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM terminal Digital information is sent to between MBU and Keyset which employs a Ping Pong technique which is used to send voice and signaling information for that instrument One B channel carries digital voice information while the channel carries signaling information for that instrument to and from digital terminal interface boards The GSL12 block of ACT2 on the MBU assembles and disassembles the 28 0 information packets and controls the digital signal for transmission Digitized voice is converted to analog voice in the instrument by the Codec device coder decoder and analog voice is converted to digitized voice by the same Codec for transmission back to digital terminal interface boards Signaling information sent on the D channel from the digital instrument to digital terminal interface boards is processed by the micro processor on MBU The micro processor processes requests and sends system status and commands by digital terminal signaling logic in the 55112 block to the phone Digitized voice information sent on the B channel is routed to ACT2 on the MBU for switching and gain control The MBU switches the information to a receive B channel and informs the receiving terminal on the system such as another station B Analog Instruments Analog instruments can be used in ipLDK 60 sy
159. will turn on whenever any terminal the E1HB8 is in activated state Output latch buffer U32 that is accessed by chip selection signal SLT RLY CTL2 is to control ring relays and input data buffer U36 that is controlled SLT HOOK is used for main CPU to sense SLT hook state The main CPU on the MBU can detect whether SLU8 board is installed or not and get board information from input data buffer U31 that is accessed by BOARD INFO a SLT Analog terminal part The 5108 board is commonly used in E1HB8 CSB316 Please refer to them in CSB316 section for detail circuit descriptions of SLT interface circuits b DKT Digital Terminal part The digital line interface circuit is composed of the GSL12 block of ACT 2 a matching transformer capacitors resistors and a posistor It provides a connection with two wires to one digital terminal Capacitors C197 and C213 and diodes D22 and D23 are used for protecting line interface circuit against ESD or lightning surge It provides 30 power to the digital terminal through the transformer T11 and the posistor PT8 is used to protect the over current due to line short The DKT TX interface line of the GSL12 block of ACT 2 on the MBU are output terminals and used to transmit a digitized voice and data to the digital terminals via the transformer And the DKT RX lines of the GSL12 block of ACT 2 are input terminals and are used to receive a digitized voice and data from the digital te
160. wn below Seven SLTs can be connected to the MBU through modular jack MJ2 Each SLT interface circuit is identical and this section describes first SLT interface circuit as an example The line protection circuitry consists of one bridge diode BD11 between the Tip and Ring input RL11 2 Relay for providing the ring signal and occupying the DC loop 2f ipLDK 60 SERVICE MANUAL DIGITAL KEV TELEPHONE SVSTEM PTI SLTI E 20 1724 12 2 I TEM PT11 Figure 3 1 17 SLT line interface and protection circuit As the figure shown below 36V power feeding part are connected to SLT line interface and protection part So 36V power is supplied to SLT through resistors and transistors Q21 and Q31 the SLT line interface and protection circuit The resistors R656 R701 and R671 transistors Q41 and Q101 capacitor C728 and zener diode ZD10 makes the loop current be limited Figure 3 1 18 36V power feeding circuit and current limiting circuit The Sicofi interface part is comprised of T11 matching transformer U111 amplifier and other passive devices The main functions of this part are the isolation of the system side from SLT line side and the gain conversion of voice signal The audio transformer T11 operates in a non saturated condition with DC blocking capacitor C561 Impedance matching is incorporated on the secondary winding of the audio transformer through appropriate RC networks R661
161. xternally It supports system features and functions such as Single Line Telephone DTMF dialing and DISA calls Calls 12 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM requiring DTMF monitoring are connected via a system B channel to one of 15 DTMF receiver channels in ACT2 And the CPU on the MBU identifies which digit is generated from Single Line Telephone SLT 2 DTMF Tone Generation With call processing tones the system generates DTMF tones from digitally stored tones in ACT2 as a Look up table DTMF tones in digital PCM form are injected onto the receive highway at the proper time slots by a digital summation technique and digital gain modified by the Tone Generation block in ACT2 device on the MBU board More about the digital summation and gain process are discussed in section 2 4 3 Conferencing C Real Time Clock The system maintains its own real time with a real time clock circuit The day date and time are stored in the Device retained in the system by the on board lithium battery on the MBU The clock is used for many system features such as LCD time amp date display SMDR time amp date printout the wake up call feature etc D System Information input output I O The system can communicate detailed call records customer database changes and diagnostic routines through multi purpose hardware ports on the system MBU A channel Universal Asynchronous Receive Transmit UART device is used to provide ac
162. y RL TES END 125 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 2 RGU check sheet 7 7 NOU CZoHZ 7 5 8880 2200 HI 858 AAA gt SI er ee REP 2714 gt 056 al m gt 4 Tu wa 3 RING Note RGU operates just in SLT ringing state it doesn t work during SLT idle state Ringing state 25Hz square wave idle state no output Ring Generation Unit circuit 884 005 PAMESYNC OPTION A w N ms 1 800Hz 25H7 EM UASB lt d 5 a 12 7 E miror J gt i 4 IA g i pase 7 BC856BL RING 4 NC401 TBDR2 T4HC4040 25Hz square wave 25 2 Oscillation circuit 126 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 1 25Hz generation circuit 25Hz generation Check the waveform measured at pin 3 of U65 Check the U64 U65 from U8 amp Replace damaged part Check the amplitude measured at pin 3 of U65 Check the Q53 056 R884 R891 amp Replace damaged 127 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 2 Ring signal generation circuit ON OFF Control Signal Check the control signal
163. y of 3 08 that is three CO interface circuits and eight extension terminal interface circuits that are composed of 1 DKT port and 7 Hybrid ports The capacity of IPLDK 60 system can be extended to maximum 12 48 that means the twelve CO interface ports and the forty eight extension ports by adding EKSU CHB308 and CSB316 board The system features can be added by installing function boards at connectors that are prepared on the MBU 16 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 3 1 2 Block Diagram amp Circuit Description SLT HOOK POL OPTION CS MODEM VAKIU_DSP_IRG ASIC_FSK Basic J Exp Expansion KSU Connection EKSU S pin Figure 3 1 1 Block Diagram of MBU The main processor on the MBU is to communicate with terminals such as DKTs or SLTs and to execute call processing application As shown in the above block diagram MBU consists of CPU Central Processing Unit ARM7 and its peripheral circuits PCM and signaling control ASIC ACT2 voltage regulator 1 RS 232C port reset circuit RTC Real Time Clock memory back up circuit 1 internal MOH 1 external MOH 1 external paging port 2 general relay ports interface Option MODU ALARM sense Fal IDT_DATA l WATCH DOG S35 33VReguator oyy Expanam CS ASIC CS Option 316SLB alarm detection circuit battery backup circuit ring generation circuit and
164. y switches PT9 Replace damaged part Waveforms are same to right waveform Yes Check FALC56 U24 and its circuits Replace damaged part 193 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 9 1 12 DSP Digital Signal Processor circuit Sheet 6 7 Start Check DSP master clock CLK 10M Check oscillator X5 FB15 1 8V 10MHz and divide resistors R417 R429 Replace damaged parts Yes Check the waveform at Check U18 and HPI part Pin 27 of DSP XF HDO HD7 HCNTLO 1 HBIL _DSP CS BWBEO Is it right shape Jep 1 245 Yes 21 C1 Freg 2449kHz Low resolution TO 125us i 2 42 Poi o i o 3 2 i 20 05 CHi x 1 56 w 22 Nov 2006 15 38 46 NOTE DSP U35 TMS320VC5402 We can check whether or not DSP operates normally by measuring the waveform at Pin 27 XF of DSP DSP toggles XF signal whenever it starts to process each channel among 30 channels 2 signals are switched from MPX 0 to MPX busithrough 2 e MPX bus0 PCM bus for E1 transceiver FAL C56 e MPX bus1 PCM bus for DSP MFC R2 Encoder decoder 194 ipLDK 60 SERVICE MANUAL DIGITAL KEY TELEPHONE SYSTEM 9 1 13 Digital Terminal Interface 1st port 1 AMI signaling check MBU Sheet 5 11 Digital Line Signal Check the positive TX signal measured at pin 162 of U8 on MBU

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