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AD820

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1. 8 Figure 5 2 Data Memory Space nun nh nh nhan nu snas snas na snas nn 9 Figure 5 3 Status and Control Register Address 1111 10 Figure 5 4 Watch Dog Reset nnn nnn nnn 11 Figure 5 5 Timer Register Address 0 23 11 Figure 5 5 Timer Block Diales ss 12 Figure 5 7 Port 0 Data Register Address 0X00 2 4 12 Figure 5 8 Port 1 Data Register Address 0x01 2 22 2 22 12 Figure 5 9 Block Diagram 2 25 rua aeu in P Sonya MEUS RAUS Cana PADRE E CURE 13 Figure 5 10 Port 0 Pull Up Register Address 0 08 2 2 2 13 Figure 5 11 Port 1 Pull Up Register Address 0 09 22 13 Figure 5 12 Port Isink Register for One 14 Figure 5 13 The Cext Register Address 0 22 4 0 4 14 Figure 5 14 Clock Oscillator On chip Circuit 14 Figure 5 15 Global Interrupt Enable Register Address 0x20
2. 15 Figure 5 16 Interrupt Controller Logic Block Diagram 15 Figure 5 17 Port 0 Interrupt Enable Register Address O0x04 16 Figure 5 18 Port 1 Interrupt Enable Register Address O0x05 16 Figure 5 19 GPIO Interrupt Logic Block Diagram eese nennen 17 Figure 5 20 USB Device Address Register Address 0 12 18 Figure 5 21 USB End Point 0 RX Register Address 0 14 2 2 1 1 18 Figure 5 22 USB Engine Response to SETUP and OUT transactions on End Point O 19 Figure 5 23 USB End Point 0 TX Configuration Register Address 0x10 19 Figure 5 24 USB End Point 1 TX Configuration Register Address Ox1 1 20 Figure 5 25 USB Status and Control Register Address 0 13 20 TIMING RR EO TETTE KS 24 Figure 8 2 USB Data Signal 24 TABLE OF TABLES T
3. 1073 1 10 102 103 104 105 Frequency Hz vs FREQUENCY 160 120 80 40 PSRR dB 1 10 10 10 104 109 106 Frequency Hz OUTPUT NOISE vs FREQUENCY 104 103 102 Noise nV VHz 10 1 10 102 103 104 105 Frequency Hz TYPICAL PERFORMANCE CURVES CONT 25 Vs 15V unless otherwise noted lq mA Vour V QUIESCENT CURRENT vs POWER SUPPLY 10 8 6 4 2 0 6 9 12 15 18 Power Supply V INPUT RANGE vs POWER SUPPLY 16 12 8 4 0 6 9 12 15 18 Power Supply V OUTPUT SWING vs LOAD 15 10 5 0 0 500 1000 1500 2000 Load Input Bias Current pA Vour V Settling Time us 12 11 10 15 10 10 INPUT BIAS CURRENT vs POWER SUPPLY 9 12 15 18 Power Supply V OUTPUT SWING vs POWER SUPPLY 9 12 15 18 Power Supply V SETTLING TIME vs FILTER CAPACITOR 10 20 99 Filter Capacitor pF BURR BROWN PGA202 203 TYPICAL PERFORMANCE CURVES
4. 6 Edits to TYPICAL PEBREORMANGE CHARACTERISTICS iuda ibn HE A 8 16 C00873 0 5 02 D PRINTED IN U S A AV Nationat Semiconductor November 1999 ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 8 Bit Compatible A D Converters General Description The ADCO801 ADCO802 ADCO803 ADCO804 ADCO805 are CMOS 8 bit successive approximation A D converters that use differential potentiometric ladder similar to the 2568 products These converters are designed to allow operation with the NSC800 and INS8080A derivative control bus with TRI STATE output latches directly driving the data bus These A Ds appear like memory loca tions or ports to the microprocessor and no interfacing logic is needed Differential analog voltage inputs allow increasing the common mode rejection and offsetting the analog zero input voltage value addition the voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of resolution Features m Compatible with 8080 uP derivatives no interfacing logic needed access time 135 ns Fasy interface to all microprocessors or operates stand alone Connection Diagram m Differential analog voltage inputs B Logic inputs and outputs meet both MOS and TTL voltage level specifications m Works with 2 5V LM336 voltage reference On chip clock generator OV to 5V ana
5. cia 10 90 2 1 E 16 202 USB 17 AAPP 17 00 0 Wake ens 17 59 058 ENGINE indie 17 5 9 1 USB Enumeration PIOGBSS id 92 FONTO e c 18 592 1 RECEIVE qc 18 5 9 2 2 O Transrail issii a colinas SE Lou m n 20 5 931 e NNI ei 5 94 USB Status and Control m 20 5 10 Instruction Set Summary aia 21 6 0 ABSOLUTE 1 RATINGS acta 22 L0 DC CHARACTERS LOS E REA encia 22 8 0 SWITGHINOGBABAGIEBRISTIOS Ria 23 SU ORDERING INFORMATION nica osea 24 10 0 PACKAGE DIAGRAMS EAM NENNT 25 CY7C63000 CY7C63001 CY7C63100 CY7C63101 Ext PRELIMINARY CY7C63200 CY7C63201 Ml ci LL 65200 0 7065201 TABLE OF FIGURES Figure 5 1 Program Memory Space lt
6. 0 V 15 V T 25 C Ven 0 V Voy 0 V unless otherwise noted AD820A 820 Parameter Conditions Min Typ Max Min Typ Max Unit DC PERFORMANCE Initial Offset 0 4 0 3 Max Offset over Temperature 0 5 0 5 Offset Drift 2 2 Input Bias Current Vem 0V 2 2 Vem 10 40 40 at Tuax 0 5 0 5 Input Offset Current 2 2 0 5 0 5 Vo 10 V to 10 V 100 Tmn to Tax 10 Tmn to Tmax Tmn to Tmax NOISE HARMONIC PERFORMANCE Input Voltage Noise 0 1 Hz to 10 Hz UV p p_ f 10 Hz nV VHz f 100 Hz nV NHz f 1 kHz nV VHz f 10 kHz nV VHz Input Current Noise 0 1 Hz to 10 Hz fA f 1 kHz fA NHz Harmonic Distortion f 10 kHz dB DYNAMIC PERFORMANCE Unity Gain Frequency MHz Full Power Response Vo p p 20 V kHz Slew Rate Settling Time to 0 1 Vo 0Vtotl0V to 0 01 INPUT CHARACTERISTICS Common Mode Voltage Range Tmn to Tmax CMRR 15 V to 12 V Tmn to Tax Input Impedance Differential Common Mode OUTPUT CHARACTERISTICS Output Saturation Voltage Ismx 20 Tmn to Tmax ISourck 20 HA Tmn to Tmax Vor Vzg Ismx 2 mA Tmn to Tmax Vcc Von 2 mA Tmn to Tmax Vor Vxzg Ismx 15 mA Tmn to Tmax 15 mA Tun to Operating Output Current Turn to Short Circuit Cur
7. DS005671 40 Effect of Unadjusted Offset Error vs 2 Voltage OFFSET ERROR LSBs LE 0 1 1 0 5 2 0 005671 43 Linearity Error at Low 2 Voltages LINEARITY ERROR 15857 1 0 0 0801 2 VOLTAGE DS005671 46 www national com S0800Q0V vr0o800Q0V 0800Q0V c0800QV 0800 QV ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 TRI STATE Test Circuits and Waveforms tim 210 pF RD O DATA CS OUTPUT CL 10k VOH DATA di OUTPUTS DS005671 48 DS005671 47 1 220 ns ton tou C 210 pF Vcc Vcc RD 10k O DATA CS OUTPUT DATA C OUTPUTS T 0L pr DS005671 50 DS005671 49 t 20 ns Timing Diag rams All timing is measured from the 50 voltage points START CONVERSION tW WR L BUSY DATA IS VALID IN ACTUAL INTERNAL OUTPUT LATCHES STATUS OF THE CONVERTER NOT BUSY 1 TO 8 x 1 fCLK INTERNAL Te LAST DATA WAS READ INTR LAST DATA WAS NOT READ INT ASSERTED lt gt am af DS005671 51 www national com 6 Timing Diag lames timing is measured from the 50 voltage points Continued Output Enable and Reset with INTR INTR RESET INTR N CS 181 RD DATA TRI STATES OUTPUTS GSP GaP
8. 4 50 4 15 5 00 5 25 5 50 Vee SUPPLY VOLTAGE DS005671 38 VS Clock Capacitor kHz 1000 100 ee E25 viri N NAM 100 1000 CLOCK CAPACITOR pF DS005671 41 Output Current vs Temperature OUTPUT CURRENT mA 5 O 50 25 0 25 50 Vec 5Voc N DATA OUTPUT NIT BUFFERS HNH ISOURCE St TS _ sink Vout 04 a 75 100 125 TA AMBIENT TEMPERATURE C DS00567 1 44 Delay From Falling Edge of RD to Output Data Valid vs Load Capacitance DELAY ns T 400 300 200 UUN s m EA ES ER E m A 1 _ Lege qoe LOAD CAPACITANCE pF 0 005671 39 Full Scale Error vs Conversion Time LINEARITY ERROR 1585 LLL LLL ALLLLLLLLLLA 6 4 51 Tc CONVERSION TIME us DS005671 42 Power Supply Current vs Temperature Note 9 Icc POWER SUPPLY CURRENT 24 100 125 50 25 0 25 50 75 AMBIENT TEMPERATURE C DS005671 45 CLK IN Schmitt Trip Levels vs Supply Voltage CLK IN THRESHOLD VOLTAGE V 4 50 415 500 525 550 Vec SUPPLY VOLTAGE
9. m fm ma m m _ x 2 qme p T qme je SND _ 21 PRELIMINARY a t SESZ Cypress CY7C63000 CY7C63001 CY7C63100 CY7C63101 CY7C63200 CY7C63201 6 0 Absolute Maximum Ratings Giorage TORIBOI 65 C to 150 C Ambient Temperature with Power 09C to 70 C supply voltage on Voc Telalive AR NE 0 5 to 7 0V DO PULVON m 0 5V to 0 5 DC voltage applied to outputs in High Z 1 esses nennen nnns 0 5V to 0 5 Max Mo 12 oomen 60 mA Max output current into non Port PIS MET _ _ _ _ __ _ wol IW cerit m 300 mW eae 2 6 T DO M RITE EET E gt 200 mA 7 0 DC Characteristics 6 MHz Operating Temperature 0 to 70 C General Operating Voltage Maximum applied voltage Vec Operating Supply Current Supply Current Suspend Mode Supply Current Start up Mode Programming Voltage disabled Resonator Start up Interval Internal timer 1 interrupt period Internal timer 2 interrupt period WatchDog timer period 7 168 8 192 Power On Reset POR Voltage VCC reset slew USB Interface
10. G 25 150 LES pS AAG 200 009 i o 012 B 045 __ m 15 d b T NES E f Eo e i 419 SEATI 330 Ex 5 PLANE gt wv Y U O Cypress Semiconductor Corporation 1997 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product Nor does it convey or imply any license under patent or other rights Cypress Semiconductor does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress Semiconductor products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges ANALOG DEVICES single Supply Rail to Rail Low Power FET Input Amp AD820 FEATURES True Single Supply Operation Output Swings Rail to Rail Input Voltage Range Extends Below Ground Single Supply Capability from 5 V to 36 V Dual Supply Capability from 2 5 V to 18 V Excellent Load Drive Capacitive Load Drive Up to 350 pF Minimum Output Current of 15 mA Excellent AC Performance for Low Power 800 pA Max Quiescent Current Unity Gain Bandwidth 1 8 MHz Slew Rate
11. A 1 A ANALOG INPUT 0800567 1 83 Error Plot 1 158 3 4 LSB 1 2 158 ERROR 1 2 LSB 3 4 LSB 1 LSB A 1 A 1 ANALOG INPUT Viy DS00567 1 84 FIGURE 2 Clarifying the Error Specs of an A D Converter 14 LSB 17 www national com 508090V 08090V 2808090V 208090V 108090V ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Functional Description Continued Transfer Function DIGITAL OUTPUT CODE A 1 A A 1 ANALOG INPUT Viy DS005671 85 Error Plot 1 LSB 1 158 A 1 A ANALOG INPUT Viy DS005671 86 FIGURE 3 Clarifying the Error Specs of an A D Converter 1 LSB 2 0 FUNCTIONAL DESCRIPTION The ADCO801 series contains a circuit equivalent of the 2568 network Analog switches are sequenced by succes sive approximation logic to match the analog difference input voltage Vin Vin to a corresponding tap on the R network The most significant bit is tested first and after 8 comparisons 64 clock cycles a digital 8 bit binary code 1111 1111 full scale is transferred to an output latch and then an interrupt is asserted INTR makes a high to low transition A conversion in process can be interrupted by issuing a second start command The device may be oper ated in the free running mode by connecting INTR to the WR input with CS 0 To ensure start up under all possible conditions an external WR pulse is required duri
12. Test a single bit in status word by looking for 1 to be rotated into the CARRY an INT 15 1 If CARRY is set then load contents of A Dat port ADDRinC register If CARRY is not set increment C register to point to next A D then test next bit in status word Read data from interrupting A D and invert the data Store the data Store A Didentifier A D port ADDR Test next bit in status word Re establish all registers as they were before the interrupt Return to original program 39 DS005671 A6 www national com 508090VW 08090V 2808090V 208090V 108090V ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Physical Dimensions inches millimeters unless otherwise noted 0 495 0 512 12 598 13 005 0 394 0 419 10 008 10 643 30 TYP LEAD NO 1 Bl LAN V YY Y Y Wu Ww OM LL 0 010 0 254 0 291 0 299 7 391 7 595 0 010 0 029 0 093 0 104 0 254 0 737 7 2 362 2 642 0 004 0 012 8 0 004 0 012 ALL LEADS 0 102 0 305 0 SEATING d 1 PLANE qn 0 229 0 330 40406 1270 Dn 27 0 356 0 508 TYP ALL LEADS TYP ALL LEADS TYP 0 008 0 203 M20B REV SO Package M Order Number ADCO802LCWM or ADCO804LCWM NS Package Number M20B 1 013 1 040 0 092 x 0
13. gt m qm aD DS005671 52 Note Read strobe must occur 8 clock periods 8 6 after assertion of interrupt to guarantee reset of INTR Typical Applications 6800 Interface Ratiometeric with Full Scale Adjust 5 DS005671 53 Note before using caps at or Vngrp 2 see section 2 3 2 Input Bypass Capacitors e a lt lt Wa a L OPTIONAL FS ADJUST DS005671 54 www national com 508090VW 08090V 2808090V 208090V 108090V ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Typical Applications Continued Absolute with a 2 500V Reference For low power see also LM385 2 5 Zero Shift and Span Adjust 2V lt Vin lt 5V SETS ZERO CODE VOLTAGE 1k 2 2 7 ZERO ADJ www national com 5 0 005671 55 5 e SETS VOLTAGE SPAN SEE SECTION 2 4 1 2k DS005671 57 Absolute with a 5V Reference Vcc VREF 5 JJ 100 2k r I L OPTIONAL FS ADJUST DS005671 56 Span Adjust OV lt Vy lt Vec 5 2k LM336 DS005671 58 Typical Applications Continued Directly Converting a Low Level Signal Vcc 5 O VIN OV lt Vin lt 512 mV 2 24k 3 9k 15 Vpc
14. 100 Vos 10 ADJ 10 Vnpr 2 256 mV 1 mV Resolution with pP Controlled Range 8 BIT DAC 2 500 V i MICRO DACTM 0830 DATA BUS 2 128 mV 1 LSB 1 mV VpAcSViNS VpAc 256 mV 0 VpAc lt 2 5V 3 9k LM336 DS005671 59 5 T A Interfaced Comparator Vcc 5 05005671 60 Vin gt Vin Output FF ugx For Vin lt Vin Output 00HeEx 2k 9 1k 2 500 Vpc 1k SPAN LM336 ADJ DS005671 61 www national com 508090VW 08090V 2808090V 208090V 108090V ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Typical Applications Continued Digitizing a Current Flow 0 1 lLOAD 2A FULL SCALE 5 100 240 10 uF 100 D ZERO ADJ 120 Self Clocking Multiple A Ds Use a large value to reduce loading at CLK R output www national com IF MORE THAN 5 ADDITIONAL 05 USE A CMOS BUFFER NOT 721 DS005671 63 10 2k 9 1k LM336 1k FS ADJ DS005671 62 External Clocking 5V x L L 2v mm 1 gt 4 44 15 0 1 A D CLK CLK IN DS005671 64 100 2 lt lt 1 460 kHz Typical Applications Continued Self Clocking in Free Running Mode uP Interface for Free Running A D 7 STAGE BINARY CTR A D CLKR CD4024BC SYS RESET al al START READY TO uP Mi 1
15. OUTPUT FILTERING The summing nodes of the output amplifier have also been made available to allow for output filtering By placing matched capacitors in parallel with the existing internal capacitors as shown in Figure 5 you can lower the fre quency response of the output amplifier This will reduce the noise of the amplifier at the cost of a slower response The nominal frequency responses for some selected values of capacitor are shown in Table III FIGURE 5 Output Filtering CUTOFF FREQUENCY C AND C 1MHz None 100kHz 47 10kHz 525pF TABLE III Output Frequency vs Filter Capacitors INPUT CHARACTERISTICS Because the PGA202 203 have FET inputs the bias currents drawn through input source resistors have a negligible effect on DC accuracy The picoamp currents produce no more than microvolts through megohm sources The inputs are also internally diode clamped to the supplies Thus input filtering and input series protection are easily achievable A return path for the input bias currents must always be provided to prevent the charging of any stray capacitance Otherwise the amplifier could wander and saturate A IMQ to resistor from the input to common will return floating sources such as thermocouples and AC coupled inputs see Applications Section Figures 8 and 9 DYNAMIC PERFORMANCE The PGA202 and the PGA203 are fast settling FET input programmable gain instrumentation amplifiers Careful a
16. 0 229 0 381 lt DIA NOM etta 11 016 8256 yq 0 045 0 015 1 143 0 381 0 050 1 270 0 130 0 005 3 302 0 127 0 125 0 140 t 3 175 3 556 THU 0 508 TYP MIN 0 018 0 003 0 457 0 076 i 5 100 0 010 100 0 010 T e 2 540 0 254 294 0 060 1 524 REV F Molded Dual In Line Package NS Package Number LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor National Semiconductor Corporation Europe Americas Fax 49 0 180 530 85 86 Tel 1 800 272 9959 Email europe support nsc com Fax 1 800 737 7018 Deutsch Tel 49 0 69 9508 6208 Email support nsc com English Tel 44 0 870 24 0 2171 www national com Frangais Tel 33 0 1 41 91 8790 2 A critical component is any component of a life Support device or system whose failure to perform can be reasonably expected to cause the fail
17. BURR BROWN PGA202 203 2 CONFIGURATION ABSOLUTE MAXIMUM RATINGS Top View Supply Voltage d IE T cene 18V Digital Common Internal Power Dissipation Analog and Digital Operating Temperature Range G Package Vour P Package Lead Temperature soldering 10s Output Short Circuit Duration Filter B Junction Temperature Vout Sense Vos Adjust V N V iN PACKAGE INFORMATION PACKAGE DRAWING MODEL PACKAGE NUMBER PGA202KP 14 Pin Plastic DIP PGA202AG 14 Pin Ceramic DIP PGA202BG 14 Pin Ceramic DIP PGA203KP 14 Pin Plastic DIP PGA203AG 14 Pin Ceramic DIP PGA203BG 14 Pin Ceramic DIP NOTE 1 For detailed drawing and dimension table please see end of data sheet or Appendix D of Burr Brown IC Data Book ORDERING INFORMATION TEMPERATURE OFFSET VOLTAGE MODEL PACKAGE RANGE MAX mV PGA202KP 1 10 100 1000 Plastic DIP 09 to 70 2 24 G PGA202AG 1 10 100 1000 Ceramic DIP 25 C to 85 C 2 24 G PGA202BG 1 10 100 1000 Ceramic DIP 25 C to 85 C 1 12 G PGA203KP Plastic DIP 09 to 70 C 2 24 G PGA203AG Ceramic DIP 25 C to 85 C 2 24 G PGA203BG Ceramic DIP 25 C to 85 C 1 12 G The information provided herein is believed to be reliable however BURR BROWN assumes no responsibility for inaccuracies or omissions BURR BROWN assumes no responsibility for the us
18. Debido a que la tecnolog a USB es relativamente nueva a nivel mundial no se ha podido encontrar ning n experto en la materia dentro del pa s eso tambi n incluye libros es por ello que para encontrar la documentaci n necesaria sobre el tema se hizo una b squeda por Internet para encontrar libros referentes al tema en otros pa ses Por otro lado con respecto al uso de la resina la empresa Fibrocentro la cual es la encargada de distribuir resina en el pa s tambi n presta servicio de asesor a para sus clientes en cuanto al manejo de la resina y a la elaboraci n de los moldes a utilizar La medici n de los par metros necesarios para este proyecto tales como tiempo de reacci n ancho de banda voltajes m nimos y m ximos etc fueron de gran importancia para evaluar si los componentes que se desean adquirir cumplen con los requerimientos necesarios para poder desarrollar el proyecto de una forma satisfactoria Con respecto a la elaboraci n de las pistas de circuitos de montaje de superficie fueron hechas a mano debido a la carencia de un programa que pudiera hacerlas de una forma satisfactoria ya que se tuvo que combinar tanto integrados de montaje superficial como de tipo DIP 4 2 Obtenci n y an lisis de informaci n Debido a la carencia de informaci n sobre el tema de USB en el pa s como se mencion anteriormente se hizo uso del Internet para poder obtener informaci n necesaria para desarrollar el sistema Sitios de
19. Pull P1 7 Pull P1 6 Pull P1 5 Pull P1 4 Pull P1 3 Pull Pi 2 Pull P1 1 Pull P1 0 Figure 5 11 Port 1 Pull Up Register Address 0x09 Writing a 0 to the Data Register will drive the output LOW Instead of providing a fixed output drive the USB Controller allows the user to select an output sink current level for each pin The sink current of each output is controlled by a dedicated Port Isink Register The lower 4 bits of this register contain a code selecting one of sixteen sink current levels The upper 4 bits of the register are ignored The format of the Port Isink Register is shown in Figure 5 12 CY7C63000 CY7C63001 CY7C63100 CY7C63101 gt PRELIMINARY CY7C63200 CY7C63201 Figure 5 12 Port Isink Register for One GPIO Line Port 0 is a low current port suitable for connecting photo transistors Port 1 is a high current port capable of LED drive See section 7 0 for current ranges 0000 is the lowest drive strength 1111 is the highest The write only sink current control registers for Port 0 outputs are assigned from address 0x30 to 0x37 with the control bits for POO starting at 0x30 Port 1 sink current control registers continue from address 0x38 to Ox3B sink current control registers are cleared during a reset resulting in the minimum drive setting 5 6 Instant on Feature Suspend Mode The USB Controller can be placed in a low power state by setting the Suspend bit bit 3 of the Status an
20. 0033 RTI 0034 02 00 FDB 0200 Starting address data storage 0036 00 00 TEMP2 FDB 0000 0038 CE 02 00 ENDP LDX 0200 Reinitialize 003B DF 34 5 0050 DE 36 LDX TEMP2 005 59 RTS Return from subroutine To user s program DS005671 A1 Note 22 In order for the microprocessor to service subroutines and interrupts the stack pointer must be dimensioned in the user s program ANALOG Y INPUTS 150 pF DS005671 25 FIGURE 16 0801 6820 PIA Interface www national com 30 Functional Description continued SAMPLE PROGRAM FOR Figure 16 ADC0801 MC6820 PIA INTERFACE 0010 CE 00 38 DATAIN LDX 0013 FF FF F8 STX 0016 B6 80 06 LDAA 0019 CLRA 001A B7 80 07 STAA 001D B7 80 06 STAA 0020 CLI 0021 C6 34 LDAB 0023 86 3D LDAA 0025 F7 80 07 CONVRT STAB 0028 B7 80 07 STAA 002B 0026 DE 40 LDX 002 8C 02 OF CPX 0031 27 OF BEQ 0033 08 INX 0034 DF 40 STX 0036 20 ED BRA 0038 DE 40 INTRPT LDX 003A B6 80 06 LDAA 003D A7 00 STAA 003F 3B RTI 0040 02 00 FDB 0042 CE 02 00 ENDP LDX 0045 DF 40 STX 0047 59 RTS PIAORB EQU PIACRB EQU The following schematic and sample subroutine DATA IN may be used to interface up to 8 ADCO801 s directly to the MC6800 CPU This scheme can easily be extended to allow the interface of more converters In this configuration the converters are arbitrarily located at HEX address 5000 in the MC6800 m
21. 05005671 21 FIGURE 13 1 58048 Interface SAMPLE PROGRAM FOR Figure 13 INS8048 INTERFACE 04 10 JMP 10 Program starts at addr 10 ORG 04 50 Interrupt jump vector ORG 10 Main program 99 FE ANL Pl s Chip select 81 MOVX Read inthe lst data toreset the intr 8901 START ORL Pl 1 Set port pinhigh B8 20 MOV RO 20H Data address B9 FF MOV OFFH Dummy address BA 10 MOV R2 10H Counter for 16 bytes 23 AGAIN MOV A Set ACC for intr loop 99 FE ANL Pl ZOFEH Send CS bit 0 of Pl 91 MOVX R1 Send WR out 05 EN I Enable interrupt 96 21 LOOP JNZ LOOP Wait forinterrupt EA 1B DJNZ R2 AGAIN If 16 bytes are read 00 NOP to user s program 00 NOP ORG 50H 81 INDATA MOVX Input data CS still low AO MOV QRO Store inmemory 18 INC RO Increment storage counter 89 01 ORL Pl 1 Reset CS signal 2 7 CLR A Clear ACC to get out of 93 RETR the interrupt loop DS005671 A0 4 2 Interfacing the Z 80 The Z 80 control bus is slightly different from that of the 0 O 8080 General RD and WR strobes are provided and sepa rate memory request MREQ and I O request IORQ sig nals used which have to be combined with the general ized strobes to provide the equivalent 8080 signals An WR advantage of operating the A D in space with the 2 80 is 05005671 23 that the CPU will automatically
22. 2 input voltage should then be adjusted until the digital output code is just changing from 1111 1110 to 1111 1111 This value of Vagp 2 should then be used for all the tests The digital output LED display can be decoded by dividing the 8 bits into 2 hex characters the 4 most significant MS and the 4 least significant LS Table 1 shows the fractional binary equivalent of these two 4 bit groups By adding the voltages obtained from the VMS and VLS columns in Table 1 the nominal value of the digital display when 2 2 560V can be determined For example for an output LED display of 1011 0110 or B6 in hex the voltage values from the table 3 520 0 120 or 3 640 These voltage values represent the center values of a perfect A D converter The effects of quantization error have to be ac counted for in the interpretation of the test results www national com 508090VW 08090V 2808090VW 208090V 108090V ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Functional Description Continued www national com 3k D GND 8 NSL5027 8 FIGURE 9 Basic A D Tester DS005671 18 24 For a higher speed test system or to obtain plotted data a digital to analog converter is needed for the test set up An accurate 10 bit DAC can serve as the precision voltage source for the A D Errors of the A D under test can be expressed as either analog voltages or differences in 2 digital words A basic A D tester that use
23. 25 Vs 15 unless otherwise noted QUIESCENT CURRENT vs TEMPERATURE INPUT BIAS CURRENT vs TEMPERATURE 10 103 8 5 AA cr ra LB 102 E D B O 2 9 10 2 o c 2 0 1 50 25 0 25 50 75 100 50 25 0 25 50 75 100 Temperature Temperature CURRENT LIMIT vs TEMPERATURE SLEW RATE vs TEMPERATURE 25 25 20 20 gt g 15 1 10 10 50 25 0 25 50 75 100 50 25 0 25 50 75 100 Temperature OUTPUT SWING vs TEMPERATURE LARGE SIGNAL RESPONSE 14 ERE MEE 12 gt TT gt 10 AAA PS gt LO 8 6 50 25 0 25 50 75 100 1us Div Temperature BURR BROWN PGA202 203 6 TYPICAL PERFORMANCE CURVES CONT 25 Voc 15 unless otherwise noted SMALL SIGNAL RESPONSE 2 4 5mV Div 1us Div DISCUSSION OF PERFORMANCE A simplified diagram of the PGA202 203 15 shown on the first page The design consists of a digitally controlled differential transconductance front end stage using precision FET buffers and the classical transimpedance output stage Gain switching 18 accomplished with a novel current steer ing technique that allows for fast settling when changing gains T
24. 8 Pontes Ww 3 10 _ Grystal Ceramic resonatorinor external cocking o n Grystal Ceramicresonatorot CEXT Connects to external R C timing circuit for optional suspend 11 wakeup VPP 7 Programming voltage supply tie to ground during normal 10 operation M 4 Ms 5 7 7 CY7C63000 CY7C63001 CY7C63100 CY7C63101 gt PRELIMINARY CY7C63200 CY7C63201 4 0 Pin Description _ ______________ VDD 1 pin Connects to the USB power source or to a nominal 5V power supply Actual Vcc range can vary between 4 0V and 5 25V 1 pin Connects to ground 1 pin Used in programming the on chip EPROM This pin should be tied to ground during normal operations XTALIN 1 pin Input from an external ceramic resonator crystal or clock XTALOUT 1 pin Return path for the ceramic resonator or crystal 0 7 16 pins P0 0 PO 7 are the 8 I O lines in Port 0 P1 0 P1 7 are the 8 lines in Port 1 Please note 1 0 1 7 that 1 0 1 1 supported in the CY7C6320x and 1 0 1 3 supported in the CY7C6300x I O pins are pulled up internally by 16 resistors However the sink current of each pin can be programmed to one of sixteen levels Besides functioning as general purpose lines each pin be programmed as an interrupt input The interrupt i
25. E Vg PREVENTS RD DURING A D DS005671 65 DATA UPDATE Te After power up momentary grounding of the WR input is needed to REGET 72x 1 y RESET guarantee operation ER Operating with Automotive Ratiometric Transducers Ratiometric with VpRep 2 Forced 5 5 0 0 0805 DS005671 68 DS005671 67 V 0 18 15 of lt lt 85 of Vcc uP Compatible Differential Input Comparator with Pre Set Vos with or without Hysteresis 5 OUTPUT 1 5k 1 2 LM358A LM336 OR Vos 1 2 CD4016 A eee i DS005671 69 See Figure 5 to select R value DB7 1 for Vin gt Vin VReF 2 Omit circuitry within the dotted area if hysteresis is not needed 11 www national com 508090VW 08090V 2808090V 208090V 108090V ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Typical Applications Continued Handling 10V Analog Inputs Low Cost uP Interfaced Temperature to Digital Converter 5 O DS005671 70 DS005671 71 Beckman Instruments 694 3 R10K resistor array Interfaced Temperature to Digital Converter 5 3k LM335 2 98V O 25 C 4 adi 10 mV K 10 uF 2 5V 11k 2 5V TA MIN 1k LM336 ADJ Ta MAX 100 21 820 DS005671 72 Circuit values shown are for 0 C lt T lt
26. However the program space of the CY7C63000 CY7C63100 and CY7C63200 is 2K bytes For applications requiring more program space the CY7C63001 CY7C63101 and CY7C63201 each offer 4K bytes of EPROM The program memory space is divided into two functional groups Interrupt Vectors and program code The interrupt vectors occupy the first 16 bytes of the program space Each vector is 2 bytes long After a reset the Program Counter points to location zero of the program space Figure 5 1 shows the organization of the Program memory Space 5 1 2 Security Fuse Bit The Cypress USB microcontroller includes a security fuse bit When the security fuse is programmed the EPROM program memory outputs OxFF to the EPROM programmer thus protecting the user s code a t SESZ Cypress after reset CY7C63000 CY7C63001 CY7C63100 CY7C63101 PRELIMINARY CY7C63200 CY7C63201 Address 0x000C Interrupt Vector GPIO 0 0010 program Memory Ox07FF 2 ROM CY7C63000 CY7C63100 CY7C63200 OxOFFF 4K ROM CY7C63001 CY7C63101 CY7C63201 Figure 5 1 Program Memory Space CY7C63000 CY7C63001 pu CY7C63100 CY7C63101 Em PRELIMINARY CY7C63200 CY7C63201 5 1 3 Data Memory Organization The USB Controller includes 128 bytes of data RAM The upper 16 bytes of the data memory are used as USB FIFOs for End Point 0 and End Point 1 Each end point is associated with an 8 byte FIFO The USB controller includes two pointers into data RAM t
27. Input voltages less than are a completely different story The amplifier can safely withstand input voltages 20 V below the minus supply voltage as long as the total voltage from the positive supply to the input terminal is less than 36 V In addition the input stage typically maintains picoamp level input currents across that input voltage range The AD820 is designed for 13 nV VHz wideband input voltage noise and maintains low noise performance to low frequencies refer to TPC 11 This noise performance along with the AD820 s low input current and current noise means that the AD820 contributes negligible noise for applications with source resistances greater than 10 and signal bandwidths greater than 1 kHz This is illustrated in Figure 15 100k WHENEVER JOHNSON NOISE IS GREATER THAN AMPLIFIER NOISE AMPLIFIER NOISE CAN BE CONSIDERED NEGLIGIBLE FOR APPLICATION as x INPUT VOLTAGE NOISE yu Vnus 1 LL AMPLIFIER GENERATED NOISE 0 1 10 100k 10M 100M 10G SOURCE IMPEDANCE Figure 15 Total Noise vs Source Impedance Output Characteristics AD820 s unique bipolar rail to rail output stage swings within 5 mV of the minus supply and 10 mV of the positive supply with no external resistive load The AD820 s approximate output saturation resistance is 40 2 sourcing and 20 Q sinking This can be used to estimate output saturation voltage when driving heavier current loads For instance wh
28. L Port Isink Register Figure 5 9 Block Diagram of an Line Table 5 2 Output Control Truth Table Data Register Port Pull up Register Output at I O Pin Sink Current 0 NEUEM Sink Current 0 To configure a GPIO pin as an input 1 should be written to the Port Data Register bit associated with that pin to disable the pull down function of the Isink DAC see Figure 5 9 When the Port Data Register is read the bit value will be a 1 if the voltage on the pin is greater than the Schmitt trigger threshold and 0 if below the threshold In applications where an internal pull up is required the 16K Q pull up resistor can be engaged by writing a 0 to the appropriate bit in the Port Pull Up Register Both Port 0 and 1 Pull up registers are write only see Figures 5 10 5 11 Port O Pull up is located at I O address 0x08 and Port 1 Pull up is mapped to address 0x09 The contents of the Port Pull up registers are cleared during reset allowing the outputs to be controlled by the state of the Data Registers The Port pull up registers also selects the polarity of transition that generates a GPIO interrupt A 0 selects a HIGH to LOW transition while 1 selects a LOW to HIGH transition 7 6 5 4 3 23 j 1 0 Pull PO 7 Pull PO 6 Pull PO 5 Pull PO 4 Pull Pull 2 Pull PO 1 Pull 0 Figure 5 10 Port 0 Pull Up Register Address 0x08 551 5 1 2 1
29. Molded DIP y S INS CHES 7 0070 115 5 3 ES e 5 065 oue 385 20 Lead 300 Mil Molded SOIC 29 3 D DIMENSIONS CHES MIN TEM EAD CUPLANARITY 0 004 SEA G PLANE 513 92 0S0 JL 03 AN a T 9019 12 5 26 CY7C63000 CY7C63001 CY7C63100 CY7C63101 Trs ___ ____ 22 6320 0 7063201 Package Diagrams continued 24 Lead 300 Mil Molded SOIC y 0 393 DIMENSIONS 1 CHES 0 991 f 420 2 39 EAD CUPLANARITY 0 004 v SEATI PLANE 99 0 092 O y me 1 zc PM 50 0 013 003 0 015 013 24 Lead 300 Mil Windowed CerDIP W14 MIL STD 1835 D 9 Config A LENS NN P dm NEUEN A N DAR 1 1 n f DIMENSIONS IN INCHES E 095 005 MIN MIN d MAX LAG z BASF P ANE 643 gt 2 ET JR ES LOL C 7J 200 1280 219 VUDU H _ v 55 3 TUN
30. Windowed CerDIP CY7C63200 PC 18 Pin 300 Mil PDIP CY7C63201 PC B _ 18 Pin 300 Mil PDIP CY7C63201 WC 18 Pin 300 Mil Windowed CerDIP Document 38 00557 D N w gt 2K 2K 4K 4K 4K 2K 4K 4K 2K 4K K 24 CY7C63000 CY7C63001 CY7C63100 CY7C63101 PRELIMINARY CY7C63200 CY7C63201 cypress Package Diagrams 20 Lead 300 Mil Windowed CerDIP W6 MIL STD 1835 D 8 Config A T OTMAIS Pr p lt 1 EIN RS LIINS gt UN 5 MA N N Y NN __ N HA TE mnl VA N gt 4 31 N p E EE OO o Yd WE RAR BASE PLA TES EE E gt a Le Re _ 5 UM Em UIO ict El b 1 Ly ff Y As H gt E TS or E 109 EU 1 012 ll san 45 e E E ZU _ ore ANS T 29 SFA ANF A Ss SEA 7 PLA n PRN 2 E D 0325 25 CY7C63000 CY7C63001 __ 7 63100 7 63101 es PRELIMINARY CY7C63200 CY7C63201 e EEE E Package Diagrams continued 20 Lead 300 Mil
31. duced from 20 mV 5 span to 10 mV and 1 LSB at the 2 input becomes 5 mV As can be seen this reduces the allowed initial tolerance of the reference voltage and requires correspondingly less absolute change with tem perature variations Note that spans smaller than 2 5V place even tighter requirements on the initial accuracy and stability of the reference source In general the magnitude of the reference voltage will re quire an initial adjustment Errors due to an improper value of reference voltage appear as full scale errors in the A D transfer function voltage regulators may be used for references if the ambient temperature changes are not ex cessive The LM336B 2 5V IC reference diode from Na tional Semiconductor has a temperature stability of 1 8 mV typ 6 mV max over 0 C lt T lt 70 C Other temperature range parts are also available www national com 508090V 08090V 2808090V 208090V 108090V ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Functional Description Continued SV F MAX 3 5V Vin Vin MIN 0 5V 4 3 2 SPAN 3V 1 0 DS005671 87 a Analog Input Signal Example SPAN 2 1 5 DS005671 88 0 5 1 5 ZERO SHIFT SPAN ADJ ADJ 1 2 LM358 Add if 2 1 with LM358 to draw mA to ground b Accommodating an Analog Input from 0 5V Digital Out 00 Ex to 3 5V FIGURE 7 Adapting the A D Analog Input Volta
32. if we apply an analog input equal to the center value 14 LSB we guarantee that the A D will produce the correct digital code The maximum range of the position of the code transition is indicated by the horizontal arrow and it is guar anteed to be no more than 12 LSB The error curve of Figure 3 shows a worst case error plot for the ADCO802 Here we guarantee that if we apply an analog input equal to the LSB analog voltage center value the A D will produce the correct digital code Transfer Function DIGITAL OUTPUT CODE A 1 A ANALOG INPUT Viy DS005671 81 Next to each transfer function is shown the corresponding error plot Many people may be more familiar with error plots than transfer functions The analog input voltage to the A D is provided by either a linear ramp or by the discrete output steps of a high resolution DAC Notice that the error is continuously displayed and includes the quantization uncer tainty of the A D For example the error at point 1 of Figure 1 is LSB because the digital code appeared 12 LSB advance of the center value of the tread The error plots always have a constant negative slope and the abrupt up side steps are always 1 LSB in magnitude Error Plot 1 LSB 1 2 LSB ERROR ce 1 2 LSB 1 LSB A 1 A ANALOG INPUT Viy DS005671 82 FIGURE 1 Clarifying the Error Specs of an A D Converter Accuracy 0 LSB A Perfect A D Transfer Function DIGITAL OUTPUT CODE
33. pin 4 The output will then remain in the low state until a trigger pulse is again applied When the reset function is not in use it is recommended that it be connected to to avoid any possibility of false trig gering Figure 3 is a nomograph for easy determination of C val ues for various time delays NOTE In monostable operation the trigger should be driven high before the end of timing cycle C CAPACITANCE uF 105100 us1 ms 10ms100 ms 1 105 1005 tq 7 TIME DELAY DS007851 7 FIGURE 3 Time Delay ASTABLE OPERATION If the circuit is connected as shown in Figure 4 pins 2 and 6 connected it will trigger itself and free run as a multivibrator The external capacitor charges through R4 Rg and dis charges through Thus the duty cycle may be precisely set by the ratio of these two resistors DS007851 8 FIGURE 4 Astable In this mode of operation the capacitor charges and dis charges between 1 3 Vec 2 8 Vec As in the triggered mode the charge and discharge times and therefore the fre quency are independent of the supply voltage www national com 9991 1171 LM555 Applications Information continued Figure 5 shows the waveforms generated in this mode of operation H Sc Hor 05007851 9 5 Top Trace Output 5V Div TIME 20us DIV Bottom Trace Capacitor Voltage 1V Div RA 3 9kQ Rg 3kQ 0 01uF FIG
34. que los dispositivos HID tienen la caracter stica Plug 4 Play que es un gran beneficio El programa entonces se encargar a principalmente de estas tareas 3 Reconocer aquellos dispositivos USB HID que al ser conectados se identifiquen como dispositivo maestro 4 Iniciar la comunicaci n con las puntas de osciloscopio requiriendo la transmisi n de los datos 5 Obtener los datos procesarlos y graficarlos en la interfase seg n los par metros dados por el usuario por medio de los controles 6 Terminar o pausar la comunicaci n con las puntas de osciloscopio Algunas funciones adicionales ser an 1 Almacenar en disco la se al captada 2 Mostrar toda la se al desde el inicio de la captura hasta el final La siguiente figura 3 2 3 pertenece a la interfaz implementada para el osciloscopio 13 cl Lectura datos X Trigger 0 0000000000 Disconnect dezplazamiento la derecha Desconectar osciloscopio dezplasamiento la izquierda Dezplasamiento de la sa al dezplasamiento hacia abajo dezplasamiento hacia arriba voltaje FIGURA 3 2 3 Ventana del osciloscopio Debido a que pueden conectarse al mismo tiempo m s de una punta la cantidad de puntas que el programa pueda soportar ser determinada por la capacidad de la computadora y no por la interfaz Los gr ficos utilizados en la interfaz no tiene un impacto importante en el consumo de recursos de la aplicaci n ni
35. superficie e Implementar el programa de tal forma que sea amistoso para usuario Construir un embalaje que proteja los circuitos Capitulo 3 3 1 Marco te rico Siendo que la teor a de microcontroladores la de los convertidores anal gico digital la de volt metros amper metros y osciloscopios es ya bien conocida se obviar n y se la dar prioridad a la teor a correspondiente al puerto USB El puerto USB nace debido a la necesidad de conectar nuevos dispositivos a una computadora sin necesidad de introducir una tarjeta controladora y que fuera de r pido acceso a diferencia de los otros puertos del PC USB Universal Serial Bus es una interfase plug amp play entre el PC y algunos dispositivos como el teclado el Mouse el esc ner las impresoras los m dems las tarjetas de sonido las c maras etc Una caracter stica importante es que permite a los dispositivos trabajar a velocidades que van de los 1 5 Mbps para USB1 a los 12 Mbps para USB 2 trabaja solamente con cuatro l neas dos de las cuales son para la transmisi n y recepci n de los datos y las dos restantes son utilizadas para proporcionar energ a a los dispositivos que no tengan un alto consumo y que as lo requieran proporcionando una tensi n de 5v siempre que el dispositivo no se encuentre a una distancia mayor de 5 metros El funcionamiento del puerto USB consiste en el paso de testigos que es similar a otros buses como los de las redes locales
36. that is in Same positionas 1 Done then output new SAR code Open SW1 close SW2 then proceed with program Preamp iS now zeroed Normal Read A D Subroutine Read A D data Invert data IS B Reg 0 If not stay inauto zero subroutine DS005671 A5 FIGURE 21 Software for Auto Zeroed Differential A D 5 3 Multiple A D Converters in a Z 80 Interrupt Driven e The stack pointer must be dimensioned in the main pro Mode Continued The following notes apply It is assumed that the CPU automatically performs RST 7 instruction when a valid interrupt is acknowledged CPU is in interrupt mode 1 Hence the subroutine starting address of X0038 The address bus from the Z 80 and the data bus to the Z 80 are assumed to be inverted by bus drivers gram as the RST 7 instruction automatically pushes the PC onto the stack and the subroutine uses an additional 6 stack addresses e The peripherals of concern are mapped into I O space with the following port assignments A D data and identifying words will be stored in sequen tial memory locations starting at the arbitrarily chosen address X 00 37 www national com s0800Q0V vros00QV 0800Q0V c0800QV 0800 QV ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Functional Description Continued HEX PORT ADDRESS PERIPHERAL 04 A D 4 HEX PORT ADDRESS PERIPHERAL 05 A D 5 00 MM74C374 8 bit flip flop 06 A D 6 01 A D 1 07 A D 7 02 A D 2 This port address also ser
37. 2 Uses Chebyshev implementation for steeper roll off unity gain 2nd order low pass filter Adding a separate filter for each channel increases system response time if an analog multiplexer is used DS005671 75 Output Buffers with A D Data Enabled Increasing Bus Drive and or Reducing Time on Bus TO uP DATA BUS TRI STATE BUFFERS DS00567 1 76 A D output data is updated 1 CLK period prior to assertion of INTR 15 TO uP DATA BUS TRI STATES BUFFERS DS005671 77 Allows output data to set up at falling edge of CS www national com 508090VW 08090V 2808090V 208090V 108090V ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Typical Applications Continued Sampling an AC Input Signal fin MAX FILTER SKIRT 60 80 dB f 60 LOW PASS MULTI POLE FILTER she SAMPLE AND HOLD LF398 aa DS005671 78 Note 11 Oversample whenever possible keep fs gt 2f 60 to eliminate input frequency folding aliasing and to allow for the skirt response of the filter Note 12 Consider the amplitude errors which are introduced within the passband of the filter 7096 Power Savings by Clock Gating 540 kHz ss 1 4 74032 TO A D Complete shutdown takes 30 seconds 1 2 74074 D CLK 1 3 74004 DS005671 79 Power Savings by A D and Shutdown uP CONTROL BUS Use ADC0801 02 03 or 05 for
38. 25 kHz Sine Input Unity Gain Figure 7 Small Signal Response Unity Gain Follower 6000 15 Follower Vs 15 V 10 111 Figure 5 Vs 5 V 0 V Unity Gain Follower Figure 8 Vs 5 V 0 V Unity Gain Follower Response to 0 V to 4 V Step Response to 0 V to 5 V Step 10 REV D FERE Figure 9 Unity Gain Follower Figure 12 Vs 5 V 0 V Unity Gain Follower Response to 40 mV Step Centered 40 mV above Ground Figure 10 Gain of Two Inverter Figure 13 Vs 5 V 0 V Gain of Two Inverter Response to 20 mV Step Centered 20 mV below Ground SERRE Figure 11 Vs 5 0 V Gain of Two Inverter Response to 2 5 V Step Centered 1 25 V below Ground REV D 11 10820 APPLICATION NOTES Input Characteristics In the AD820 n channel JFET are used to provide a low offset low noise high impedance input stage Minimum input common mode voltage extends from 0 2 V below to 1 V less than Vs Driving the input voltage closer to the positive rail will cause a loss of amplifier bandwidth as can be seen by comparing the large signal responses shown in Figures 5 and 8 and increased common mode voltage error as illustrated in TPC 11 AD820 does not exhibit phase reversal for input voltages up to and including Vs Figure 14a shows the response of an AD820 voltage follower t
39. 8 bit bi directional port located at an arbitrarily chosen port address EO The TRI STATE output capability of the A D eliminates the need for a peripheral interface device however address decoding is still required to generate the appropriate CS for the con verter 27 It is important to note that in systems where the A D verter is 1 of 8 or less mapped devices no address decoding circuitry is necessary Each of the 8 address bits to 7 can be directly used as CS inputs one for each device 4 1 2 INS8048 Interface The INS8048 interface technique with the ADCO801 series see Figure 13 is simpler than the 8080A CPU interface There are 24 lines and three test input lines in the 8048 With these extra lines available one of the I O lines bit 0 of port 1 is used as the chip select signal to the A D thus eliminating the use of an external address decoder Bus control signals RD WR and INT of the 8048 are tied directly to the A D The 16 converted data words are stored at on chip RAM locations from 20 to 2F Hex The RD and WR signals are generated by reading from and writing into a dummy address respectively A sample interface program is shown below www national com 508090VW 08090VW 208090V 208090V 108090V ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Functional Description Continued INS8048 0 0801 bh e Jan iw rm 20 E 6 INPUT ANALOG
40. Connections OFFSET ADJUSTMENT Figure 2 shows the offset adjustment circuits for the PGA202 203 The input offset and the output offset are both sepa rately adjustable Notice that because the PGA202 203 change between four different input stages to change gain the input offset voltage will change slightly with gain For systems using computer autozeroing techniques neither offset nor drift is a major concern but it should be noted that since the input offset does change with gain these systems should perform an autozero cycle after each gain change for opti mum performance In the output offset adjustment circuit the choice of the buffering op amp is very important The op amp needs to have low output impedance and a wide bandwidth to main tain full accuracy over the entire frequency range of the PGA202 203 For these reasons we recommend OPA602 as an excellent choice for this application FIGURE 2 Offset Adjustment Circuits BURR BROWN PGA202 203 GAIN SELECTION Gain selection is accomplished by the application of a 2 bit digital word to the gain select inputs Table I shows the gains for the different possible values of the digital input word The logic inputs are referred to their own separate digital common pin which can be connected to any voltage be tween the minus supply and 8V below the positive supply The gains are all internally trimmed to an initial accuracy of better than 0 196 so no external
41. Static Output High Static Output Low General Purpose Pull up resistance Port 0 sink current 0 lowest current Port 0 sink current F highest current Port 1 sink current F highest current Port 1 sink current 0 lowest current Sink current max min Differential nonlinearity Input leakage current Sink current Notes 1 Per Table 7 6 of revision 1 0 of USB specification for Cload of 100 350pF 2 Power on Reset will occur until the voltage on increases above Vrst 3 Rx external idle resistor 7 5 2 to Vcc 22 Oscillator off D gt min Vec 5 0V Vec 5 0V ceramic resonator NOTE 2 6 linear ramp 0 to Vrst 15k 5 Q to Gnd 4 NOTE 4 Vout 2 0 V DC Port 0 only 141 Vout 2 0 V DC Port 0 only 141 Vout 2 0 V DC Port 1 only 141 Vout 2 0 V DC Port 1 only 4 Vout 2 0 V DC Port 0 or 1 17 19 Port 0 or Port 1 Pl CEXT only CEXT only CY7C63000 CY7C63001 pu CY7C63100 CY7C63101 o _ PRELIMINARY CY7C63200 CY7C63201 7 0 DC Characteristics continued Fosc 6 MHz Operating Temperature 0 to 70 C ink Parameter Max Units Conditions le Current sink response time 0 8 us Full scale transition General Purpose l O continued Tracking Ratio Port1 to Porto Vout 2 0 191 Port 1 max sink current Summed over all Port 1 bits Port 1 amp CEXT sink mode dissipation Per pin Input Threshold Voltage All ports and Cext l Input Hys
42. como volt metro y de igual forma para medir corriente Para poder realizar este proyecto se decidi utilizar primordialmente convertidor anal gico digital y uno de los microcontroladores de la CYPRESS que incorpora puerto USB as como amplificadores de instrumentaci n e integrados que proporcionan tensi nes negativas Abstract The following project consists of implementing an oscilloscope an ammeter and a voltmeter by means of port USB of the computer As it is known the oscilloscope is one of the used instruments more in electronics but their prices are very high and are for that reason that is desired to implement an oscilloscope with the help of the computer using port USB this with the purpose of lowering the price of the cost of an oscilloscope so that it is more accessible even to such technician students graduated and engineering in electronics electrical and any area in which an oscilloscope can be used lt is possible to mention that the technology of the computation has advanced to huge steps lowering the price of the costs of the faster and accessible computers being is for that reason that it is desired to still more take advantage of the capacities the computer by means of this project In addition to the oscilloscope it is desired that the product also has the capacity to measure current and tension to extend its capacities still more The system will consist of an apparatus of interchangeable ends that is c
43. en anillo con paso de testigos y la funci n del controlador ser la de distribuir los testigos por el bus y el dispositivo que tenga la direcci n igual a la portada por el testigo deber responder enviando los datos al controlador el cual tambi n se encarga de distribuir la energ a a los dispositivos Utiliza una topolog a de estrella la cual le permite un funcionamiento simult neo de 127 dispositivos a la vez lo que implica la necesidad de dispositivos de tipo hub anfitri n que centralicen las conexiones y controlan todo el tr fico del bus Este tipo de topolog a permite a diferentes dispositivos conectarse un nico bus l gico sin que los dispositivos que se encuentren m s debajo de la pir mide sufran retardo Como se puede observar en la figura 4 1 el sistema USB consta de tres componentes el controlador el hu y los perif ricos Root HUE Figura 3 1 1 Estructura de capas del bus USB El controlador se encuentra dentro de la computadora y es el encargado de llevar a cabo la comunicaci n entre los dispositivos y la PC tambi n se encarga de estar verificando cuando se dio una conexi n como una desconexi n adem s de que verifica que tipo de dispositivo y se encarga de asignarle una direcci n l gica que utilizar cada vez que desee comunicarse con el dispositivo o viceversa Tambi n se encarga de comunicarle al usuario si se encontr alg n error en la transmisi n o recepci n de la informaci n y se enca
44. en su desempe o ya que todos los elementos ser n simples fachadas para recibir los par metros del usuario El nico elemento que consume recursos continuamente es la representaci n gr fica de la onda en una pantalla virtual ya que los datos ser n procesados constantemente durante la captura de la se al 14 3 3 Descripci n de los principales principios F sicos de software y o electr nicos relacionados con la soluci n del problema Para este proyecto una de los par metros m s importantes que se tom en cuanta es el ancho de banda de los componentes a utilizar ya que esto pod a presentar una limitante para el osciloscopio pues dependiendo del ancho de banda al que trabajen los componentes electr nicos correctamente as ser el ancho de banda a la que podr trabajar el osciloscopio por ejemplo el ancho de banda de los amplificadores a utilizar est entre 1 y los 15 MHz el microcontrolador es de 10 MHz aproximadamente la velocidad m xima del ADC es de 1MHz y el amplificador de instrumentaci n trabaja con una frecuencia de 440 MHz as que el dispositivo tendr la m xima velocidad del componente mas lento Tambi n hay que tomar en cuenta la resoluci n a la que se desea utilizar el ADC para nuestro caso tomaremos una resoluci n de 8 bits Los datos de corriente de entrada y de salida as como sus respectivos voltajes fueron tomados en cuenta para todos los circuitos integrados para que haya un correcto acople en
45. esta pueda representar estos datos en el monitor No todos los integrados es posible encontrarlos para que sean de montaje de superficie 7 2 Recomendaciones l Para ampliar el ancho de banda bajo el cual trabaja el dispositivo de adquisici n de tatos por USB no hay que usar el PGA202 si no que se implementa su misma funci n con amplificadores operacionales multiplexores anal gicos Cambiar el ADCO804 por un convertidor de mayor velocidad oe pueden utilizar integrados equivalentes a los que se utilizaron en este proyecto para reducir el costo por materiales Para que las pistas en un circuito impreso queden de mayor calidad el circuito debe de tener la mayor cantidad de cobre posible oe puede utilizar el microcontrolador de la microchip el 16c745 con lo que se reducir a el costo de fabricaci n y de materiales del dispositivo maestro 33 Bibliograf a Libros y catalogos 1 Natinal Semiconductor National Analog and Interface Products Databook 2002 Edition 2 Robert Coughlin Amplificadores Operacionales y Circuitos Integrados Lineales Quinta edici n Prentice Hall 3 Cypress CY7C63001 Datasheet Internet http es wikipedia org wiki Microcontrolador http www monografias com trabajos13 fire fire shtml http www freebyte com programming delphi http www soft gems net HID php http www oscilloscope lib com 34 APENDICE Glosario e USB universal serial bus bus serial univers
46. fem and using a 640 kHz A D clock fc would allow a peak value of the common mode voltage Vp which is given by vo LAVemax 4 5 Or 5 x 10 3 640x 103 6 28 60 4 5 which gives The allowed range of analog input voltages usually places more severe restrictions on input common mode noise lev els An analog input voltage with a reduced span and a relatively large zero offset can be handled easily by making use of the differential input see section 2 4 Reference Voltage 2 3 Analog Inputs 2 3 1 Input Current Normal Mode Due to the internal switching action displacement currents will flow at the analog inputs This is due to on chip stray capacitance to ground as shown in Figure 5 www national com 20 e lt 60 ns TIME Rs CHARGE y m V CSTRAY I DS005671 14 of SW 1 and SW 2 5 CSTRAY 5 x 12 pF 60 ns FIGURE 5 Analog Input Impedance The voltage on this capacitance is switched and will result in currents entering the V n input and leaving Vin input which will depend on the analog differential input volt age levels These current transients occur at the leading edge of the internal clocks They rapidly decay and do not cause errors as the on chip comparator is strobed at the end of the clock period Fault M
47. industrial temperature range while the plastic package covers the commercial range Covered by U S PATENT 4 883 422 International Airport Industrial Park Tel 520 746 111 Twx 910 952 1111 Mailing Address PO Box 11400 Cable BBRCORP 01989 Burr Brown Corporation Tucson AZ 85734 Telex 066 6491 PDS 1006C APPLICATIONS DATA ACQUISITION SYSTEMS AUTO RANGING CIRCUITS DYNAMIC RANGE EXPANSION REMOTE INSTRUMENTATION TEST EQUIPMENT Vos Adjust Filter B Sense Vour VREF Logic Circuits 30kQ 5 3pF Filter A Ag A Digital Common Street Address 6730 S Tucson Blvd Tucson AZ 85706 520 889 1510 Immediate Product Info 800 548 6132 Printed in U S A August 1993 SPECIFICATIONS ELECTRICAL At 25 C Voc 15 unless otherwise noted PGA202 203AG PGA202 203BG PGA202 203KP PARAMETER CONDITION YP TYP MAX UNITS GAIN Error 2 Nonlinearity Gain vs Temperature RATED OUTPUT Voltage lt 5mA Over Specified Temperature See Typical Perf Curve Current lt 10V ANALOG INPUTS Common Mode Range Absolute Max Voltage 9 No Damage Impedance Differential Common Mode OFFSET VOLTAGE RTI Initial Offset at 25 C 4 ones AE 7 e vs Temperature Offset
48. input current is a precise linear function of the differential input voltage 2 3 3 Input Source Resistance Large values of source resistance where an input bypass capacitor is not used will not cause errors as the input currents settle out prior to the comparison time If a low pass filter is required in the system use a low valued series resistor 1 for a passive RC section or add an op amp active low pass filter For low source resistance applica tions 1 a 0 1 bypass capacitor at the inputs will prevent noise pickup due to series lead inductance of a long Functional Description continued wire A 1000 series resistor can be used to isolate this capacitor both the R and C are placed outside the feed back loop from the output of an op amp if used 2 3 4 Noise The leads to the analog inputs pins 6 and 7 should be kept as short as possible to minimize input noise coupling Both noise and undesired digital clock coupling to these inputs can cause system errors The source resistance for these inputs should in general be kept below 5 Larger values of source resistance can cause undesired system noise pickup Input bypass capacitors placed from the analog inputs to ground will eliminate system noise pickup but can create analog scale errors as these capacitors will average the transient input switching currents of the A D see section 2 3 1 This scale error depends on both a large
49. insert one wait state the RD FIGURE 14 Mapping the A D as an Device and WR strobes are extended one clock period to allow for Use with the 7 80 CPU more time for the devices to respond Logic to map the A D in space is shown in Figure 14 Additional advantages exist as software routines are available and use can be made of the output data transfer which exists on the upper 8 address lines A8 to www national com 28 Functional Description continued A15 during I O input instructions For example MUX chan nel selection for the A D can be accomplished with this operating mode 4 3 Interfacing 6800 Microprocessor Derivatives 6502 etc The control bus for the 6800 microprocessor derivatives does not use the RD and WR strobe signals Instead it employs a single R W line and additional timing if needed can be derived fom the 2 clock All devices are memory mapped in the 6800 system and a special signal VMA indicates that the current address is valid Figure 15 shows an interface schematic where the A D is memory mapped in the 6800 system For simplicity the CS decoding is shown using gt DM8092 Note that in many 6800 systems an already decoded 4 5 line is brought out to the common bus at pin 21 This can be tied directly to the CS pin of the A D provided that no other devices are addressed at HX ADDR or 5XXX The following subroutine performs essentially the same func a
50. mode Output voltage swing extends to within 10 mV of each rail providing the maximum output dynamic range Offset voltage of 800 uV max offset voltage drift of 1 uV C typical input bias currents below 25 and low input voltage noise provide dc precision with source impedances up to a Gigaohm 1 8 MHz unity gain bandwidth 93 dB THD at 10 kHz and 3 V us slew rate are provided for a low supply current of 800 AD820 drives up to 350 pF of direct capacitive load and provides a minimum output current of 15 mA This allows the amplifier to handle a wide range of load conditions This combi nation of ac and dc performance plus the outstanding load drive capability results in an exceptionally versatile amplifier for the single supply user The AD820 is available in two performance grades The and B grades are rated over the industrial temperature range of 40 C to 85 The AD820 is offered in two varieties of 8 lead package plastic DIP and surface mount SOIC Figure 2 Gain of 2 Amplifier Vs 5 0 Vin 2 5V Sine Centered at 1 25 Volts One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 Analog Devices Inc 2002 AD820 SPEC 0 Vs 0 5 V OT 25 Ven 0 V 0 2 V unless otherwise noted Parameter DC PERFORMANCE Initial Offset Max Offset over Temperature Offset Drift Input Bias Cur
51. on reset POR Improved output drivers to reduce Operating voltage from 4 0V to 5 25VDC Operating temperature from 0 to 70 degree Celsius Available in space saving and low cost 18 pin PDIP 20 pin PDIP 20 pin SOIC and 24 pin SOIC packages Windowed packages also available to support program development 18 20 and 24 pin Windowed CerDIP Industry standard programmer support 2 0 Functional Overview The CY7C63xxx is a family of 8 bit RISC One Time Programmable OTP microcontrollers with a built in 1 5 Mbps USB serial interface engine The microcontroller features 35 instructions which are optimized for USB applications There is 128 bytes of onboard RAM available incorporated into each microcontroller The Cypress USB Controller accepts a 6 MHz ceramic resonator or a 6 MHz crystal as its clock source This clock is doubled within the chip to provide a 12 MHz clock for the microprocessor The microcontroller features two ports of up to sixteen general purpose I Os GPIOs Each GPIO pin can be used to generate an interrupt to the microcontroller Additionally all pins in Port 1 are equipped with programmable drivers strong enough to drive LEDs The GPIO ports feature low EMI emissions as a result of controlled rise and fall times and unique output driver circuits in the microcontroller The Cypress microcontrolles have a range of GPIOs to fit various applications the CY7C630xx has twelve GPIO the CY7C631xx has sixteen GPIO and the CY7C632x
52. solamente trabaja con valores positivos de voltaje es por ello que se utiliza el AD820 cuyo 24 valor ya menciono antes y que tiene la habilidad de trabajar con solo una fuente de voltaje esto permite que pueda ser utilizado para colocar la se al proveniente del PGA202 sobre un nivel de CD que permita que la tenga solamente valores positivos El valor de las resistencia y los capacitares seria de aproximadamente de 2 DL m M AMA 100kQ R7 1 5kQ eu IN 100KQ LIN 50 SE AL DE ENTRADA R5 1 lt 7 GND amp DS204N gt 4 R2 1 ALA ENTRADA R1 4 ANALOGICA DEL 10k0 DISPOSITIVO R3 MAESTRO 1 5 0 VIN Cr gr 20k0 4254 sm FR dy 10uF 4 19 7GND 22 0 MAAXLAA 100 1673 OUT Yee Y TIERRA LNSKIF GND PROPORCIONADAS POR EL PUERTO USB Figura 5 1 4 1 Circuito para la punta removible de osciloscopio El valor total para el circuito de la punta removible de osciloscopio ser a de 23 26 y si a este le sumamos el embalaje que costar a 5 y el conector para el cable coaxial 1 45 el valor total seria de 18 61 Tabla 5 1 4 4 Costo de los materiales de la punta removible de osciloscopio adquirir mas de 100 LM555 0 4794 AD820 CNN Genere Cables Resistencias e a o Placa TOTAL 24 61 25 Figura 5 1 4 2 Embalaje par
53. the Wake up Interrupt Enable bit bit 7 of the Global Interrupt Enable Register This interrupt can be used to perform periodic checks on attached peripherals when the USB Controller is placed in the low power suspend mode See the Instant On Feature section for more details 5 9 USB Engine The USB engine includes the Serial Interface Engine SIE and the low speed USB transceivers The SIE block performs most of the USB interface functions with only minimal support from the microcontroller core Two end points are supported End Point 0 is used to receive and transmit control including setup packets while End Point 1 is only used to transmit data packets The USB SIE processes USB bus activity at the transaction level independently It does all the NRZI encoding decoding and bit stuffing unstuffing It also determines token type checks address and endpoint values generates and checks CRC values and controls the flow of data bytes between the bus and the End Point FIFOs CY7C63000 CY7C63001 CY7C63100 CY7C63101 gt PRELIMINARY CY7C63200 CY7C63201 The firmware handles higher level and function specific tasks During control transfers the firmware must interpret device requests and respond correctly It also must coordinate Suspend Resume verify and select DATA toggle values and perform function specific tasks The USB engine and the firmware communicate though the End Point FIFOs USB End Point interrupts and the USB regis
54. to 5 the span would be as shown in Figure 7 With 0 5 applied to the Vin pin to absorb the offset the reference voltage can be made equal to 1 2 of the span or 1 5 The A D now will encode the signal from 0 5V to 3 5 V with the 0 5V input corresponding to zero and the 3 5 input corresponding to full scale The full 8 bits of resolution are therefore applied over this reduced analog input voltage range 2 4 2 Reference Accuracy Requirements The converter can be operated in a ratiometric mode or an absolute mode In ratiometric converter applications the magnitude of the reference voltage is a factor in both the output of the source transducer and the output of the A D converter and therefore cancels out in the final digital output code The ADCO0805 is specified particularly for use in ratio metric applications with no adjustments required In absolute conversion applications both the initial value and the tem perature stability of the reference voltage are important fac tors in the accuracy of the A D converter For Vagp 2 volt ages of 2 4 nominal value initial errors of 10 mVpc will cause conversion errors of 1 LSB due to the gain of 2 of the Vnres 2 input In reduced span applications the initial value and the stability of the 2 input voltage become even more important For example if the span is reduced to 2 5V the analog input LSB voltage value is correspondingly re
55. 0 CY7C63101 CY7C63200 CY7C63201 Universal Serial Bus Microcontroller 3901 North First Street SanJose 95134 408 943 2600 Cypress Semiconductor Corporation October 1996 Revised June 26 1997 CY7C63000 CY7C63001 CY7C63100 CY7C63101 Exc __ PRELIMINARY CY7C63200 CY7C63201 MM cid IN A TABLE OF CONTENTS o 4 20 FUNG HONAL OVERVIEW error Ni 4 PIN DEFINITIONS a E e EEE 6 40 PIN DESCRIPTION seus n aii ii S 7 5 0 FUNCTIONAL DESCRIPTION tasas act 7 5 1 Memory Organizati t orante 7 5 1 1 Program Memory Organiza on aaa aa aiaa 9 1 2 idas 7 9 1 3 Data Memory m 52 TEE m 9 LEON 10 5 31 BOWer ON Reset POR 5 9 2 Walch Dog Reset WIDA escitas 11 535 USB BUS e M 11 54 5 11 5 5 General Purpose DO 12 5 6 Instant on Feature Suspend Mode 14 5 7 XTALIN XTALOUT cda 14 5 6 IMENU 15
56. 02 03 04LCJ 05 mA ADCO0804LCN LCWM mA Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions Note 2 All voltages are measured with respect to Gnd unless otherwise specified The separate A Gnd point should always be wired to the D Gnd Note 3 A zener diode exists internally from Vcc to Gnd and has a typical breakdown voltage of 7 Vpc Note 4 For Vin gt Vin the digital output code will be 0000 0000 Two on chip diodes are tied to each analog input see block diagram which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the Vcc supply Be careful during testing at low Vcc levels 4 5V as high level analog inputs 5V can cause this input diode to conduct especially at elevated temperatures and cause errors for analog inputs near full scale The spec allows 50 mV forward bias of either diode This means that as long as the analog Vy does not exceed the supply voltage by more than 50 mV the output code will be correct To achieve an absolute 0 to 5 input voltage range will therefore require a minimum supply voltage of 4 950 over temperature variations initial tolerance and loading Note 5 Accuracy is guaranteed at 640 kHz At higher clock frequencies accuracy can degrade For lower cloc
57. 030 2 337 X 0 762 0 032 0 005 MAX DP 0 813 0 127 RAD NO 1 IDENT 0 260 0 005 6 604 0 127 PIN NO 1 uc o 1 EN OPTION 1 y MIN 0 300 0 320 OPTION 2 7 620 8 128 0 065 1 524 TYP 95 5 0 009 0 015 0 229 0 381 0 325 0 015 31 016 8 255 0 130 0 005 4 4X 3 302 0 127 0 145 0 200 3 683 5 080 90 0 004 0 020 0 100 0 010 1 0 125 0 140 0 508 _0 060 0 005 2 540 0 254 0 018 0 003 3175 3556 MIN 0 040 1 524 0 127 0 457 0 076 N20A REV G Molded Dual In Line Package N Order Number ADCO801LCN ADCO802LCN ADCOS803LCN ADCO804LCN ADCO805LCN NS Package Number N20A www national com 40 Notes LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 5 V eiqneduio 118 8 608000V t08000V 0800Q0V 20800Q0V L0800QV 1 Life support devices or systems are devices or 2 critical component is any component of a life systems which a are intended for surgical implant support device or system whose failure to perform into the body or b support or sustain life and can be reasonably expected to cause the failure of whose failure to perform when properly used in the life support device or
58. 102 0 254 A Yo y E SEATING 0 004 A PLANE 0 008 0 010 Pipe e 0050 0 356 0 050 0 014 0 020 0 01 1254 CS 1279 7400 356 0 508 TYP ALL LEADS 203 P REV Small Outline Package M NS Package Number M08A 0 118 0 004 310 1 8 0 189 180 004 0 193 0 004 on 1 4 8 4 9 0 1 0 0256 0 65 To 0 0256 LAND PATTERN RECOMMENDATION 0 65 0 005 0 13 0 045 0 005 PLANE MAX l R 0 13 TYP 0 010 0 25 0 01 mm 004 TH las 0 021 0 005 0 E 101 0 53 0 12 09 69 2 0 051 0 054 0 0575 SEATING PLANE 0 06 0 15 0 86 0 953 0 00 0 0510 0 007 0 002 0 18 0 05 b MUAOBA REV B 8 Lead 0 118 Wide Molded Mini Small Outline Package NS Package Number 11 www national com LM555 Timer 0 092 2 337 mr 7 PIN NO 1 im 3 0 373 0 400 9 474 10 16 0 090 Physical Dimensions inches millimeters unless otherwise noted Continued 0 032 0 005 0 813 5 0 127 0 250 0 005 RAD 6 35 0 127 PIN NO 1 OPTION 1 0 280 0 040 7 112 MN 0 030 1 016 me OPTION 2 0 300 0 320 0 762 0 145 0 200 s 0 991 3 683 5 080 7 62 8 128 20 t T 95 5 2 0 125 1 651 0 009 0 015 _ 3178 1 55
59. 128 C calibrate each sensor to allow easy replacement then A D can be calibrated with a pre set input voltage www national com 12 Typical Applications Continued Handling 5V Analog Inputs Vcc 5 Vpc Beckman Instruments 694 3 10 resistor array uP Interfaced Comparator with Hysteresis DS005671 35 DS00567 1 33 Read Only Interface RD A DATA IS STARTS NEW OUTPUT CONVERSION DS005671 34 Protecting the Input Diodes are 1N914 13 05005671 9 www national com S0800Q0V vr0o800Q0V 0800Q0V c0800QV 0800 QV ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Typical Applications Continued Analog Self Test for a System 8 SYSTEM CHANNEL DC TEST POINTS CD4051 C CHANNEL SELECT ee FROM OUTPUT PORT OF uP DS005671 36 A Low Cost 3 Decade Logarithmic Converter i 10 mV gt VA gt 10V gt T y rud 10 VMAX per rdi 710 DS005671 37 LM389 transistors B D LM324A quad www national com 14 Typical Applications Continued 3 Decade Logarithmic A D Converter C LM324A 1 2 LM394 VIN g radi 100 C10 mv 10v gt 100 1M 1 336 ZERO ADJ DS005671 73 Noise Filtering the Analog Input Multiplexing Differential Inputs CHANNEL DIFFERENTIAL MU X 604052 CHANNEL SELECT m FROM OUTPUT DS005671 74 20
60. 2 Int En P1 1 Int En P1 0 Int En Figure 5 18 Port 1 Interrupt Enable Register Address 0x05 A block diagram of the GPIO interrupt logic is shown in Figure 5 19 The bit setting in the Port Pull up Register selects the interrupt polarity If the selected signal polarity is detected on the pin a HIGH signal is generated If the Port Interrupt Enable bit for this pin is HIGH and no other port pins are requesting interrupts then the 12 input OR gate will issue a LOW to HIGH signal to clock the GPIO interrupt flip flop The output of the flip flop is further qualified by the Global GPIO Interrupt Enable bit before it is processed by the Interrupt Priority Encoder Both the GPIO interrupt flip flop and the Global GPIO Enable bit are cleared during GPIO interrupt acknowledge by on chip hardware CY7C63000 CY7C63001 CY7C63100 CY7C63101 gt PRELIMINARY CY7C63200 CY7C63201 Port Pull Up GPIO Interrupt Register 12 Input Flip Flop OR Gate 1 Enable Port Interrupt 0 Disable Enable Register Interrupt Acknowledge 9 Q Interrupt IRQ Global Priority 1 Enable GPIO Interrupt Encoder Interrupt 0 Disable Enable Vector Figure 5 19 GPIO Interrupt Logic Block Diagram Please note that if one port pin triggered an interrupt no other port pins can cause a GPIO interrupt until that port pin has returned to its inactive non trigger state or its corresponding port interrupt enable bit is cleared The USB Controller does not a
61. 8 Open Loop Gain vs Temperature TPC 11 Input Voltage Noise vs Frequency UL LLL LEM 50 a fl PUNCTUM AMAA E HH ICH 2 ana 110 INPUT VOLTAGE pV THD dB 16 12 8 4 0 4 8 12 6 100 10k 100k OUTPUT VOLTAGE V Hz TPC 9 Input Error Voltage vs Output Voltage TPC 12 Total Harmonic Distortion vs Frequency for Resistive Loads REV D 7 OPEN LOOP GAIN dB OUTPUT IMPEDANCE XN PHASE MARGIN DEGREES COMMON MODE REJECTION dB RL 2k0 C 100pF A Yi 10k 10 10k 100k 1M 10M Hz EANO Hz TPC 13 Open Loop Gain and Phase Margin TPC 16 Common Mode Rejection vs Frequency vs Frequency Z HHH a m ef HAHN A CECO il fg H ae CA COMMON MODE ERROR VOLTAGE mV 100 AR 10k 100k 1M 10M FREQUENCY Hz Commode T FROM me RAILS V TPC 14 Output Impedance vs Frequency TPC 17 Absolute Common Mode Error vs Common Mode Voltage from Supply Rails Vs Vem 1000 E NE M VE 2262 E OUTPUT SWING FROM 0 TO Volts ma zm HT 10 OUTPUT SAT
62. A L Test of bytes entered 0107 FE OF CPI OFH If 16 JMP to 0109 1301 JZ CONT user program 010C D3 EO OUT EO H Start A D 010 Enable interrupt 010 00 LOOP NOP Loop until end of 0110 50 01 JMP LOOP conversion 0113 CONT User program to process data e e e e e e e e 0300 DB EO LD DATA IN EOH Load data into accumulator 0302 77 MOVM A Store data 0303 23 INXH Increment storage pointer 0304 C30301 JMP RETURN DS005671 99 Note 18 The stack pointer must be dimensioned because a RST 7 instruction pushes the PC onto the stack Note 19 All address used were arbitrarily chosen The standard control bus signals of the 8080 CS RD and WR can be directly wired to the digital control inputs of the A D and the bus timing requirements are met to allow both starting the converter and outputting the data onto the data bus bus driver should be used for larger microprocessor systems where the data bus leaves the PC board and or must drive capacitive loads larger than 100 pF 4 1 1 Sample 8080A CPU Interfacing Circuitry and Program The following sample program and associated hardware shown in Figure 12 may be used to input data from the converter to the INS8080A CPU chip set comprised of the INS8080A microprocessor the INS8228 system controller and the INS8224 clock generator For simplicity the A D is controlled as an l O device specifically an
63. C0803 ADC0804 ADC0805 AC Electrical Characteristics continued The following specifications apply for 5 and unless otherwise T Symbol Units Cour TRI STATE Output pF CONTROL INPUTS Note CLK IN Pin 4 is the input of a Schmitt trigger circuit and is therefore specified separately Logical 1 Input Voltage Vce 5 29 2 0 15 Voc Except Pin 4 CLK IN Logical 0 Input Voltage 4 75 Voc Voc Except Pin 4 CLK IN ln 1 Logical 1 Input Current Vin 5 Voc 0 005 1 l n 0 Logical 0 Input Current Vin 0 Voc 1 0 005 CLOCK IN AND CLOCK R V CLK IN Pin 4 Positive Going 2 7 3 1 3 5 V CLK IN Pin 4 Negative 1 5 1 8 2 1 Vpc 0 Logical 0 CLK Output 10 360 pA 0 4 Vpc Vaur Logical 1 CLK R Output lo 360 2 4 Voc Voltage 4 75 Voc DATA OUTPUTS AND INTR Vout 0 Logical O Output Voltage Data Outputs lour 1 6 mA 4 75 Voc Voc INTR Output lour 1 0 mA 4 75 Voc Vog Vour 1 Logical 1 Output Voltage lo 360 4 75 Vour 1 Logical 1 Output Voltage lo 10 4 75 EE Voc lout TRI STATE Disabled Output Vour 0 Voc Leakage All Data Buffers Vour 5 Vpc POWER SUPPLY loc Supply Current Includes 640 kHz Ladder Current 2 25 and CS 5 ADC0801
64. C63000 CY7C63001 CY7C63100 CY7C63101 gt PRELIMINARY CY7C63200 CY7C63201 5 3 2 Watch Dog Reset WDR The Watch Dog Timer Reset WDR occurs when the Most Significant Bit of the 4 bit Watch Dog Timer Register transitions from LOW to HIGH Writing any value to the write only Watch Dog Restart Register at Ox21 will clear the timer The Watch Dog timer is clocked by a 1 024 ms clock from the free running timer If 8 clocks occur between writes to the timer a WDR occurs Bit 6 of the Status and Control Register will be set to record the event A Watch Dog Timer Reset lasts for 8 192 ms after which the microcontroller begins execution at ROM address 0x00 The USB transmitter is disabled by a Watch Dog Reset because the USB Device Address Register is cleared Otherwise the USB Controller would respond to all address O transactions The transmitter remains disabled until the WDR bit in the Status and Control Register is reset to 0 by firmware lt 8 192 ms 4 8 192 ms gt _ j No write to WDT Execution begins at register so WDR Reset Vector 0X00 last write to Watchdog Timer Register goes high Figure 5 4 Watch Dog Reset WDR 5 3 3 USB Bus Reset The USB Controller recognizes a USB Reset when a Single Ended Zero SEO condition persists for longer than 8 micro seconds SEO is defined as the condition in which both the D line and the D line LOW Bit 5 of the Status and Control Register wi
65. CING MULTIPLE A D s IN AN MC6800 SYSTEM ADDRESS HEX CODE MNEMONICS COMMENTS 0010 DF 44 DATAIN STX TEMP Save Contents of X 0012 CE 00 2A LDX 002 Upon IRQ LOW CPU 0015 FF FF F8 STX FFF8 Jumps to 002A 0018 B7 50 00 STAA 5000 StartsallA D s 0018 OE CLI 001C WAI Wait interrupt 001D 50 00 LDX 5000 0020 40 STX INDEX1 Reset both INDEX 0022 CE 02 00 LDX 0200 land2to starting 0025 DF 42 STX INDEX2 addresses 0027 DE 44 LDX TEMP 0029 59 RTS Return from subroutine 002A DE 40 INTRPT LDX INDEX1 INDEX1 X 002C A6 00 LDAA X Read data in fromA Dat X 002E 08 INX Increment X by one 002F DF 40 STX INDEX1 X INDEX1 0031 DE 42 LDX INDEX2 INDEX2 X DS005671 A3 SAMPLE PROGRAM FOR Figure 17 INTERFACING MULTIPLE A D s IN AN MC6800 SYSTEM ADDRESS HEX CODE MNEMONI 0055 7 00 5 0055 8C 02 07 CPX 0058 27 05 BEQ 003A 08 INX 003B DF 42 STX 003D 20 EB BRA 003F 3B RETURN RTI 0040 50 00 INDEX1 FDB 0042 02 00 INDEX2 FDB 0044 00 00 TEMP FDB CS COMMENTS X Store data at X 0207 Have all A D s been read RETURN Yes branch to RETURN No increment X by one INDEX2 X INDEX2 INTRPT Branch to 002A 5000 Starting address for A D 0200 Starting address data storage 0000 DS005671 A4 Note 25 In order for the microprocessor to service subroutines and interrupts the stack pointer must be dimensioned in the user s program For amplification of DC input sig
66. Indefinite 8 Lead SOIC Package 160 C W Differential Input Voltage 30 V Storage Temperature Range N 65 to 125 C Storage Temperature Range R 65 C to 150 C Operating Temperature Range nD520 D 40 to 85 C Lead Temperature Range Soldering 60 SEC E SX 2609 ORDERING GUIDE Temperature Package Package Model Range Description Options AD820AN 40 C to 85 8 Lead Plastic Mini DIP N 8 AD820BN 40 C to 85 C 8 Lead Plastic Mini DIP N 8 AD820AR 409 to 85 C 8 Lead SOIC R 8 AD820BR 40 C to 85 C 8 Lead SOIC R 8 Not for new design obsolete April 2002 CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the AD820 features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality REV D WARNING ESD SENSITIVE DEVICE AD820 Typical Performance Characteristics 0 2 0 1 0 01 02 03 04 0 5 OFFSET VOLTAGE mV NUMBER OF UNITS 0 4 0 3 1 Typical Distribution of Offset Voltage 248 Units Vs 5V EH Vs 15V IN BIN 0 10 8 6 4 2 OFFSET VOLTAGE DRIF
67. Instituto Tecnol gico de Costa Rica Escuela de Ingenier a en Electr nica Escuela de Ingenier a Electr nica Sistema de adquisici n de datos v a USB con aplicaciones en medici n y control I nforme Final de proyecto de graduaci n para optar por el grado de Licenciatura en Ingenier a en Electr nica Bismarck lvarez Baltodano Cartago septiembre de 2006 INSTITUTO TECNOLOGICO DE COSTA RICA ESCUELA DE INGENIERIA ELECTRONICA PROYECTO DE GRADUACI N TRIBUNAL EVALUADOR Proyecto de Graduaci n defendido ante el presente Tribunal Evaluador como requisito para optar por el t tulo de Ingeniero en Electr nica con el grado acad mico de Licenciatura del Instituto Tecnol gico de Costa Rica Miembros del Tribunal P Tak Jimenez Robles nleriano Salguero Profesor asesor Profesor lector Los miembros de este Tribunal dan fe de que el presente trabajo de graduaci n ha sido aprobado y cumple con las normas establecidas por la Escuela de Ingenier a Electr nica Cartago 20 09 06 Declaro que el presente Proyecto de Graduaci n ha sido realizado enteramente por mi persona utilizando y aplicando literatura referente al tema e introduciendo conocimientos propios En los casos que he utilizado bibliograf a he procedido a indicar las fuentes mediante la respectivas citas bibliografi tas En consecuencia asumo la responsabilidad total por el trabajo de graduaci n realizado y por el contenido d
68. Ok Cancel Figura 5 1 5 2 Ventana del boton de Opciones Ahora se puede escoger ya sea el osciloscopio el voltimetro o el amperimetro para escoger el osciloscopio vasta con oprimir el bot n de Mostrar Osciloscopio y con eso aparecer la ventana del osciloscopio donde se observar n las ondas capturadas por la computadora S Oscilloscope 1 Hex Jaggies Manual Waitfornex Menu Test Performance Figura 5 1 5 3 Ventana para el osciloscopio Start read from file 28 De igual forma para utilizar el volt metro amper metro se puede oprimir los botones Mostrar Volt metro o Mostrar Amper metro respectivamente con lo que aparecer n las ventanas que se muestran en las figuras 5 1 5 4 y 5 1 5 6 la ventana de volt metro dar valores cada 0 5 voltios hasta los 128 voltios y el amperimetro dar valores cada 0 010 amperios hasta los 2 5 amperios FVoltimetro Figura 5 1 5 4 Ventana para el Volt metro FAmperimetro m Figura 5 1 5 5 Ventana para el Amperimetro 29 Cap tulo 6 An lisis de Resultados Los resultados obtenidos con el dispositivo fueron muy satisfactorios ya que se calibraron con ayuda de instrumentos de medici n de los laboratorios de electr nica y las mediciones realizadas con los dispositivos dieron valores id nticos a los valores obtenidos con los instrumentos de medici n de la escuela de electr ni
69. R F F remains low for 8 of the external clock periods as the internal clocks run at Ys of the frequency of the external clock If the data output is continuously enabled CS and RD both held low the INTR output will still signal the end of conversion by a high to low transition because the SET input can control the Q output of the INTR F F even though the RESET input is constantly at a 1 level in this operating mode This INTR output will therefore stay low for the duration of the SET signal which is 8 periods of the external clock frequency assuming the A D is not started during this interval When operating in the free running or continuous conversion mode INTR pin tied to WR and CS wired low see also section 2 8 the START F F is SET by the high to low tran sition of the INTR signal This resets the SHIFT REGISTER which causes the input to the D type latch LATCH 1 to go low As the latch enable input is still present the Q output will go high which then allows the INTR F F to be RESET This reduces the width of the resulting INTR output pulse to only a few propagation delays approximately 300 ns When data is to be read the combination of both CS and RD being low will cause the INTR F F to be reset and the TRI STATE output latches will be enabled to provide the 8 bit digital outputs 2 1 Digital Control Inputs The digital control inputs CS RD and WR meet standard T L logic voltage levels These signa
70. T TPC 2 Typical Distribution of Offset Voltage Drift 120 Units NUMBER OF UNITS 4 INPUT BIAS CURRENT pA 5 6 7 8 9 10 TPC 3 Typical Distribution of Input Bias Current 213 Units INPUT BIAS CURRENT pA 2 1 0 1 2 COMMON MODE VOLTAGE V TPC 4 Input Bias Current vs Common Mode Voltage Vs 5 0 V and 5 V pA 5 e INPUT BIAS CURRENT o 12 16 TPC 5 Input Bias Current vs Common Mode Voltage 15 V INPUT BIAS CURRENT TEMPERATURE C TPC 6 Input Bias Current vs Temperature Vs 5 Vey 0 REV D 10M gt om E e S 3 u 100k 7 O 10k 100 10k 100k 0 60 120 180 240 300 PM RESISTANCE 0 OUTPUT VOLTAGE FROM VOLTAGE RAILS mV TPC 7 Open Loop Gain vs Load Resistance TPC 10 Input Error Voltage with Output Voltage within 300 mV of Either Supply Rail for Various Resistive Loads 5 1 0 1 k _____ ___ _ 07 ____ ALLA H 3 gt M 7 100 A D tH EB a 5 hd EG E lt z pj 100k 10 ________ _ _ gt gt it a maan z III _ m 60 40 2 80 100 120 140 100 10k TEMPERATURE qa EHEGUENOT TPC
71. UP Note 15 Note 15 HEX BINARY F 1 1 1 15 256 0 300 1 1 0 0 280 D 1 1 1 13 256 0 260 1 1 0 0 240 1 0 1 11 256 0 220 1 0 0 0 200 9 1 0 1 9 256 0 180 8 1 0 0 0 160 7 0 1 1 0 140 6 0 1 0 0 120 5 0 1 1 0 100 4 0 1 0 0 080 3 0 0 1 0 060 2 0 0 0 0 040 1 0 0 1 0 020 0 0 0 0 0 Note 15 Display Output VMS Group VLS Group 25 www national com 508090VW 08090V 2808090V 208090V 108090V ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Functional Description Continued ANALOGO INPUTS MM NT 14 DM8131 BUS T2 COMPARATOR B2 1 Note 16 Pin numbers for the DP8228 system controller others INS8080A Note 17 Pin 23 of the INS8228 must be tied to 12 through a 1 resistor to generate the RST 7 instruction when an interrupt is acknowledged as required by the accompanying sample program FIGURE 12 ADC0801_INS8080A CPU Interface www national com 26 170 WR 27 170 RD 25 uF 080 13 DB1 16 DB2 11 DB3 9 DB4 5 DB5 18 086 20 087 7 AD15 36 AD14 39 AD13 38 AD12 37 AD11 40 AD10 1 DS005671 20 Functional Description continued SAMPLE PROGRAM FOR Figure 12 ADC0801 1NS8080A CPU INTERFACE 0038 C35 0003 RST7 JMP LD DATA e 0100 21 00 02 START LXI H 0200H HL pair will point to data storage locations 0103 51 0004 RETURN LXI SP 0400H Initialize stack pointer Note 1 0106 7D MOV
72. URATION VOLTAGE mV miii mii mui 0 0 1 0 2 0 3 0 4 0 5 0 0 001 0 01 100 SETTLING TIME ps T CURRENT mA TPC 15 Output Swing and Error vs Settling Time TPC 18 Output Saturation Voltage vs Load Current 8 REV D OUTPUT SATURATION VOLTAGE mV 1 60 40 20 0 20 40 60 80 TEMPERATURE TPC 19 Output Saturation Voltage vs Temperature SHORT CIRCUIT CURRENT LIMIT mA 0 60 40 20 0 20 40 60 80 TEMPERATURE TPC 20 Short Circuit Current Limit vs Temperature QUIESCENT CURRENT pA 24 28 30 TOTAL V TPC 21 Quiescent Current vs Supply Voltage vs Temperature REV D 100 120 140 100 120 140 36 HA LOL SUS ME LUI NU 10 100 10 100 10 SFREOUEN ON Hz POWER SUPPLY REJECTION dB M E E i y TPC 22 Power Supply Rejection vs Frequency 20 LETT 1M OUTPUT VOLTAGE V m 00k 10M FREQUENCY Hz TPC 23 Large Signal Frequency Response 10820 Figure 3 Unity Gain Follower Figure 6 Large Signal Response Unity Gain Follower 15 V 10 tilo Figure 4 20 V
73. URE 5 Astable Waveforms The charge time output high is given by t 0 693 Ra Rg And the discharge time output low by 0 693 Rg C Thus the total period is T t t 0 693 Ra 2Rg The frequency of oscillation is A 1 44 IT Rad 2RgC Figure 6 may be used for quick determination of these RC values The duty cycle is CAPACITANCE uF 0 01 0 001 1 10 100 10k 100k f FREE RUNNING FREQUENCY Hz DS007851 10 FIGURE 6 Free Running Frequency FREQUENCY DIVIDER The monostable circuit of Figure 1 can be used as a fre quency divider by adjusting the length of the timing cycle Figure 7 shows the waveforms generated in a divide by three circuit www national com DS007851 11 Voc 5V Top Trace Input 4V Div TIME 20us DIV Middle Trace Output 2V Div Ra Bottom Trace Capacitor 2V Div C 0 01uF FIGURE 7 Frequency Divider PULSE WIDTH MODULATOR When the timer is connected in the monostable mode and triggered with a continuous pulse train the output pulse width can be modulated by a signal applied to pin 5 Figure 8 shows the circuit and in Figure 9 are some waveform examples DS007851 12 FIGURE 8 Pulse Width Modulator DS007851 13 Voc 5V Top Trace Modulation 1V Div TIME 0 2 ms DIV Bottom Trace Output Voltage 2V Div Ra C 0 01uF FIGURE 9 Pulse Width Modulator Applicatio
74. USB bus O 9 The host generates control reads to the USB Controller to request the Configuration and Report descriptors 10 The USB Controller retrieves the descriptors from its program space and returns the data to the host over the USB 11 Enumeration is complete after the host has received all the descriptors 5 9 2 End Point 0 USB devices are required to have an end point number 0 that is used to initialize and manipulate the device End Point 0 provides access to the device s configuration information and allows generic USB status and control accesses End Point 0 can receive and transmit data Both receive and transmit data share the same 8 byte End Point 0 FIFO located at data memory space 0x70 to 0x77 Received data may overwrite the data previously in the FIFO 5 9 2 1 End Point 0 Receive After receiving a packet and placing the data into the End Point 0 FIFO the USB Controller updates the USB End Point 0 RX register to record the receive status and then generates an USB End Point 0 interrupt The format of the End Point 0 RX Register is shown in Figure 5 21 7 3 D w w w 08 Aw RW AW Figure 5 21 USB End Point 0 RX Register Address 0x14 This is a read write register located at address Ox14 Any write to this register will clear all bits except bit 3 which remains unchanged bits are cleared during reset Bit O is set to 1 when a SETUP token for En
75. a bit in Port B is set to make Vy more positive and the output more negative This continues for 8 approximations and the differential output eventually con verges to within 5 mV of zero The actual program is given in Figure 21 All addresses used are compatible with the BLC 80 10 microcomputer system In particular Port A and the ADC0801 are at port address E4 Port B is at port address E5 Port C is at port address E6 control word port is at port address 7 Program Counter automatically goes to ADDR 3C3D upon acknowledgement of an interrupt from the ADCO0801 5 3 Multiple A D Converters in a Z 80 Interrupt Driven Mode In data acquisition systems where more than one A D con verter or other peripheral device will be interrupting pro gram execution of a microprocessor there is obviously a 35 need for the CPU to determine which device requires servic ing Figure 22 and the accompanying software is a method of determining which of 7 ADCO0801 converters has com pleted a conversion INTR asserted and is requesting an interrupt This circuit allows starting the A D converters in any sequence but will input and store valid data from the converters with a priority sequence of A D 1 being read first A D 2 second etc through A D 7 which would have the lowest priority for data being read Only the converters whose INT is asserted will be read The key to decoding circuitry is the DM74L S373 8 bit D type flip flop Wh
76. a la punta removible de osciloscopio 5 1 5 Programa que maneja los dispositivos Como ya se hab a mencionado el dispositivo trabaja con un programa hecho en DELPHI utilizando la biblioteca gratuita para dispositivos HID y el archivo DLL para osciloscopio este archivo DLL es el encargado de hacer que la honda se vea tal cual es en el monitor de la computadora con lo cual se ahorro mucho tiempo de programaci n En la figura siguiente se muestra la pantalla principal del programa 26 Sistema de adquisici n de datos USB Opciones Mostrar V altimetro Mostrar amp mperimetro Salir Figura 5 1 5 1 Imagen de la ventana principal del programa En esta ventana se muestra en una pantalla negra si el dispositivo USB esta conectado en el bot n Tomar Datos se debe de oprimir antes de intentar ver los datos ya sea en el osciloscopio el o en el amperimetro que con este botos se le indica a la computadora que debe de tomar todos los datos provenientes del puerto USB en uso Una vez oprimido el bot n de Tomar Datos se puede oprimir el bot n de Opciones en el cual vienen la opci n de cambiar la velocidad de lectura del dispositivo USB se puede cambiar la escala del osciloscopio o tambi n se pueden guardar en un archivo de texto todos los datos obtenidos 21 Opciones Tiempo ms 150 Escala C 10 1005 t 10005 Salida Guardar datos en archivo
77. able 5 1 110 Register SUMMARY B aX eS 9 Table 5 2 Output Control Truth 13 Table 5 3 Interrupt Vector 4 422 41 17 411 nennen 16 Table 5 4 Instruction Set 21 CY7C63000 CY7C63001 pu CY7C63100 CY7C63101 o _ PRELIMINARY CY7C63200 CY7C63201 1 0 Features Low cost solution for low speed USB peripherals such as mouse joystick and gamepad USB Specification Compliance Conforms to USB 1 5 Mbps Specification Version 1 0 Conforms to USB HID Specification Version 1 0 Supports 1 device address and 2 endpoints 8 bit RISC microcontroller Harvard architecture 6 MHz external ceramic resonator or clock crystal 12 MHz internal operation USB optimized instruction set Internal memory 128 bytes of RAM 2K bytes of EPROM CY7C63000 CY7C63100 CY7C63200 bytes of EPROM CY7C63001 CY7C63101 CY7C63201 I O ports Integrated USB transceivers Up to 16 Schmitt trigger pins with internal pull up Up to 8 pins with LED drive capability Special purpose I O mode supports optimization of photo transistor and LED in mouse application Maskable Interrupts on all pins 8 bit free running timer Watchdog timer WDT Internal power
78. ableOuts is set to 1 and Stall and StatusOuts are O A maximum of 8 bytes are written into the End Point 0 FIFO If there are less the 8 bytes of data the CRC is written into the FIFO Due to register space limitations the Receive Data Invalid bit is located in the USB End Point 0 TX Configuration Register Refer to the End Point 0 Transmit section for details This bit is set by the SIE if an error is detected in a received DATA packet The table below summarizes the USB Engine response to SETUP and OUT transactions on End Point O In the Data Packet column Error represents a packet with a CRC PID or bit stuffing error or a packet with more than 8 bytes of data Valid is a packet without an Error Status is a packet that is a valid control read Status stage while N Status is not a correct Status stage see section 5 9 4 The Stall bit is described is section 5 9 2 2 The StatusOuts and EnableOuts bits are described in section 5 9 4 Control Bit Settings Received Packets USB Engine Response NE TUE e pan NM MP Type Packet Update Update 7 E NER NEA MEL MN RM _ 5707 7 ww m IA CANNE _ ___ Nm Ww Ne Ns MK NE NE AME ME ME ME NEM MM NEN MUN NN MEM MM ME 51 2 O ME MAME A AM MESS EA LE LAIA AR NEM NM ME 4 E A EE E Figure 5 22 USB Engine Respo
79. al puerto de comunicaciones serial de alta velocidad que utiliza solamente dos hilos para entablar comunicaci n entre un dispositivo y la computadora e Testigos tokens el controlador USB utiliza los testigos que son c digos que contienen las direcciones de los dispositivos conectados al puerto ramas tiempo utilizado entre la comunicaci n a trav s de transacciones Transacciones informaci n compuesta por testigos tokens Datos validaci n Handshake e Validaci n Bandera que se utiliza para indicar el resultado de la Transacci n e de transferencia de datos de grandes cantidades e s crono de transferencia de datos de gran ancho de banda utilizado para audio telefon a y video e USB 1 0 Protocolo USB cuya velocidad m xima de transmisi n es de 1 5 Mbps human interface device dispositivo de interfaz humana es un protocolo de comunicaci n USB utilizado para ciertos dispositivos e DII Dynamic Link Library Biblioteca de v nculos din micos es un archivo que contiene funciones que se pueden llamar desde aplicaciones otras DII Los desarrolladores utilizan las DIl para poder reciclar el c digo y aislar las diferentes tareas Las DII no pueden ejecutarse directamente es necesario llamarlas desde un c digo externo 35 fax id 3401 CY7C63000 CY7C63001 E CY7C63100 CY7C63101 Y PRELIMINARY _ CY7C63200 CY7C63201 CY7C63000 CY7C63001 CY7C6310
80. am All CPU registers then recover the original data they had before servicing DATA IN 5 2 Auto Zeroed Differential Transducer Amplifier and A D Converter The differential inputs of the ADCO0801 series eliminate the need to perform a differential to single ended conversion for a differential transducer Thus one op amp can be elimi nated since the differential to single ended conversion is provided by the differential input of the ADCO801 series In general a transducer preamp is required to take advantage of the full A D converter input dynamic range www national com 508090VW 08090V 2808090V 208090V 108090V ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Functional Description Continued R W 34 6 DATA BUS 00 33 31 D1 32 29 D2 31 K D3 30 H 04 29 32 D5 28 30 06 27 L 07 26 J ANALOG Y INPUTS O A2 11 U A1 10 V A0 9 40 4 5 8 123 91 OR 3 2 IR 4 10 WXY GND m 41 42 43 5 ANALOG Y INPUTS O 1 o o lt 1 2 8092 4 12 22 34 A13 23 N A14 24 M 5 15 25 33 DS005671 26 Note 23 Numbers in parentheses refer to MC6800 CPU pin out Note 24 Numbers of letters in brackets refer to standard M6800 system common bus code FIGURE 17 Interfacing Multiple A Ds in an MC6800 System www national com 32 Functional Description continued SAMPLE PROGRAM FOR Figure 17 INTERFA
81. ara conectar las puntas removibles de los 6 pines se usaran 5 donde dos ser n para la alimentaci n de energ a de la punta removible uno donde pasaran los datos anal gicos hacia la entrada del ADC y por ultimo dos cables se encargaran de manejar las puntas conectadas En la figura 5 1 1 2 se muestra el embalaje que tendr a el dispositivo maestro creado por comodidad con resina Tomando en cuenta que el embalaje tendr a un valor de 1 el dispositivo maestro tendr a un valor de 9 7 21 Mini puerto USB a la computadora Figura 5 1 1 2 Dise o de embalaje para el dispositivo maestro 5 1 2 An lisis para el circuito del dispositivo punta removible de volt metro El dise o de la punta removible de volt metro constar simplemente de un divisor de tensi n cuyo m ximo valor a la entrada del dispositivo esta dada por 128 voltios y cuya menor entrada deber de ser de 0 voltios Este divisor de voltaje se construy con una resistencia de 3 ko una de 5 ko y una de 120 ko permitiendo una tensi n de 5 voltios para la entrada del ADC y si sacamos la relaci n de 128 256 nos dar el valor en el que se incrementara el volt metro por cada cambio en los valores del ADC el cual es de 0 5 voltios el circuito se muestra en la figura 5 1 2 1 Las resistencias y la placa para el montaje del circuito tiene el valor de 0 1 el cual seria el costo total de los materiales para la contracci n del circuito el costo total de cables conector y
82. as successful 5 9 3 End Point 1 End Point 1 is capable of transmit only The data to be transmitted is stored in the 8 byte End Point 1 FIFO located at data memory space 0x78 to Ox7F 5 9 8 1 End Point 1 Transmit Transmission is controlled by the USB End Point 1 TX Register located at address 0x11 see Figure 5 24 This is a read write register All bits are cleared during reset ta a a o RW W R W R W RA RW RW Hw m m 1 0 NE m qe Point 1 Count 3 Count 2 Count 1 Count 0 Respond to IN Enable packets Figure 5 24 USB End Point 1 TX Configuration Register Address 0x11 Bits 0 to 3 indicate the numbers of data bytes to be transmitted during an IN packet valid values 0 to 8 inclusive Bit 4 must be set before End Point 1 can be used If this bit is cleared the USB Controller will ignore all traffic to End Point 1 Setting the Stall bit bit 5 will stall IN and OUT packets until this bit is cleared Bit 6 Data 1 0 must be set to either 0 or 1 depending on the data packet s toggle state 0 for DATAO 1 for DATA1 After the transmit data has been loaded into the FIFO bit 6 should be set according to the data toggle state and bit 7 set to 1 This enables the USB Controller to respond to an IN packet Bit 7 is cleared and an End Point 1 interrupt is generated by the SIE once the host acknowledges the data transmission 5 9 4 USB Status and Control USB status and con
83. being executed when an interrupt occurs the first instruction of the Interrupt Service Routine will execute a min of 16 clocks 1410 5 max of 20 clocks 5410 5 after the interrupt is issued The interrupt latches are sampled at the rising edge of the last clock cycle in the current instruction 5 8 2 GPIO Interrupt The General Purpose 1 0 interrupts are generated by signal transitions at the Port 0 and Port 1 I O pins GPIO interrupts are edge sensitive with programmable interrupt polarities Setting a bit HIGH in the Port Pull up Register see Figure 5 10 and 5 11 selects a LOW to HIGH interrupt trigger for the corresponding port pin Setting a bit LOW activates a HIGH to LOW interrupt trigger Each GPIO interrupt is maskable on a per pin basis by a dedicated bit in the Port Interrupt Enable Register Writing a 1 enables the interrupt Figure 5 17 and Figure 5 18 illustrate the format of the Port Interrupt Enable Registers for Port 0 and Port 1 located at I O address 0x04 and 0x05 respectively These write only registers are cleared during reset thus disabling all GPIO interrupts 7 po 5 4 83 2 1 9 PO 7 Int En PO 6 Int En P0 5 Int En 4 Int En P0 3 Int En P0 2 Int En P0 1 Int En P0 0 Int En Figure 5 17 Port 0 Interrupt Enable Register Address 0x04 P1 7 Int En P1 6 Int En P1 5 Int En P1 4 Int En P1 3 Int En P1
84. blema 15 Capitulo 4 Procedimiento 16 4 1 Reconocimiento y definici n del problema 16 4 2 Obtenci n y an lisis de informaci n 16 4 3 Evaluaci n de las alternativas y s ntesis de una soluci n 17 4 4 Implementaci n de la 18 45 Reevaluaci n y redise o 19 Cap tulo 5 Descripci n detallada de la soluci n explicaci n de dise o 20 5 1 An lisis de soluci n y selecci n final 20 5 1 1 An lisis para el circuito del dispositivo maestro 20 5 1 2 An lisis para el circuito del dispositivo de punta removible sia iii 22 5 1 3 An lisis para el circuito del dispositivo de punta removible d ambperimelrO REO dept bindet EE UE Se 23 5 1 4 An lisis para el circuito del dispositivo de punta removible dao _ _ _ 24 5 1 5 Programa que maneja los dispositivos 26 Capitulo 6 An lisis de 30 Tecnica 33 5 33 7 2 RECOMENAACI ONES uvae Vis
85. ca A continuaci n se mostrar n varias im genes de fotos tomadas entre los instrumentos de medici n del laboratorio de electr nica y los dispositivos de medici n implementados para este proyecto FVoltimetro VOLTCRAFT ON OFF FUNCTION SET RESET DOWN E mM 1252 te FREQ Figura 6 1 Imagen que muestra la medici n de tensi n bajo iguales condiciones entre el programa y un mult metro Como se puede observar en las dos im genes presentadas en la figura 6 1 utilizando un circuito de prueba para hacer las mediciones de tensi n ambas mediciones son id nticas 30 FAmperimetro m E VOLTCRAFT M 3850 ON OFF FUNCTION SET RESET DCR AC uen Figura 6 2 Imagen que muestra las mediciones de corriente a iguales condiciones entre el programa y un multimetro Como se puede observar nuevamente bajo las mismas condiciones de medicion esto es utilizando un circuito de prueba para hacer las mediciones el dispositivo de punta removible de amperimetro esta dando exactamente la misma medicion que el multimetro digital GNA Figura 6 3 Imagen que muestra una medici n hecha con el osciloscopio del laboratorio de la escuela de electr nica 31 4 Oscilloscope Trigger 20 674560000 for Beam Jaggies Manual Menu Test Performance Figura 6 4 Imagen que m
86. d Control register Almost all logic blocks in the device are turned off except the USB receiver the GPIO interrupt logic and the Cext interrupt logic The clock oscillator as well as the free running and watch dog timers are shut down The suspend mode will be terminated when one of the three following conditions occur 1 USB activity 2 A GPIO interrupt 3 Cext interrupt The clock oscillator GPIO and timers restart immediately on exiting suspend mode The USB engine and microcontroller return to a fully functional state at most 256 us later microcontroller will execute the instruction following the write that placed the device into suspend mode before servicing any interrupt requests Both the GPIO interrupt and the Cext interrupt allow the USB Controller to wake up periodically and poll potentiometers optics and other system components while maintaining a very low average power consumption To use Cext to generate an Instant on interrupt the pin is connected to ground with an external capacitor and connected to VCC with an external resistor A 0 is written to the Cext register located at I O address 0x22 to discharge the capacitor A 1 is then written to disable the open drain output driver A Schmitt trigger input circuit monitors the input and generates a wake up interrupt when the input voltage rises above the input threshold By changing the values of the external resistor and capacitor the user can fine tune
87. d Point 0 is received Once set to a 1 this bit remains high until it is cleared by an I O write or a reset While the data following a SETUP is being received by the USB engine this bit will not be cleared by an I O write User firmware writes to the USB FIFOs are disabled when bit 0 is set This prevents SETUP data from being overwritten CY7C63000 CY7C63001 pu CY7C63100 CY7C63101 o _ PRELIMINARY CY7C63200 CY7C63201 Bits 1 and 2 are updated whenever a valid token is received on End Point O Bit 1 is set to 1 if an OUT token is received and cleared to 0 if any other token is received Bit 2 is set to 1 if an IN token is received and cleared to 0 if any other token i s received Bit 3 shows the Data Toggle status of DATA packets received on End Point 0 This bit is updated for DATA following SETUP tokens and for DATA following OUT tokens if Stall bit 5 of 0x10 is not set and either EnableOuts or StatusOuts bits 3 and 4 of 0x13 are set Bits 4 to 7 are the count of the number of bytes received in a DATA packet The two CRC bytes are included in the count so the count value is two greater than the number of data bytes received The count is always updated and the data is always stored in the FIFO for DATA packets following a SETUP token The count for DATA following an OUT token is updated if Stall bit 5 of 0x10 is 0 and either EnableOuts or StatusOuts bits 3 and 4 of 0x13 are 1 The DATA following an OUT will be written into the FIFO if En
88. d devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage 18V Power Dissipation Note 3 LM555CM LM555CN 1180 mW LM555CMM 613 mW Operating Temperature Ranges LM555C 0 C to 70 C Storage Temperature Range 65 C to 150 C Electrical Characteristics notes 1 2 Ta 25 5V to 15V unless othewise specified Parameter Conditions Supply Voltage Supply Current 5V RL 99 Voc 15V vo Low State Note 4 Timing Error Monostable Initial Accuracy Drift with Temperature Ra 1k to 100 0 1uF Note 5 Accuracy over Temperature Drift with Supply Timing Error Astable Initial Accuracy Drift with Temperature Ra 1k to 100k0 C 0 1uF Note 5 Accuracy over Temperature Drift with Supply Threshold Voltage Trigger Voltage Trigger Current Reset Voltage Reset Current Threshold Current Control Voltage Level Pin 7 Leakage Output High Pin 7 Sat Note 7 Output Low Output Low Veo 15V 15mA Voc 4 5V 4 5mA Soldering Information Dual In Line Package Soldering 10 Seconds 260 C Small Outline Packages SOIC and MSOP Vapor Phase 60 Seconds 215 Infrared 15 Seconds 220 C See AN 450 Surface Mounting Methods and Their Effect on Product Reliability for other methods of soldering surface mount devices Limits LM555C Typ We Units
89. e 1 The external capacitor is initially held discharged by a transistor inside the timer Upon application of a nega tive trigger pulse of less than 1 3 Vec to pin 2 the flip flop is set which both releases the short circuit across the capacitor and drives the output high 5V 15V TRIGGER NORMALLY ON LOAD P OUTPUT NORMALLY R OFF LOAD L DS007851 5 FIGURE 1 Monostable The voltage across the capacitor then increases exponen tially for a period of t 1 1 R4 C at the end of which time the voltage equals 2 3 Voc The comparator then resets the flip flop which in turn discharges the capacitor and drives the output to its low state Figure 2 shows the waveforms gener ated in this mode of operation Since the charge and the threshold level of the comparator are both directly propor tional to supply voltage the timing internal is independent of supply DS007851 6 Voc 5V Top Trace Input 5V Div TIME 0 1 ms DIV Middle Trace Output 5V Div Ra 9 1kQ Bottom Trace Capacitor Voltage 2V Div C 0 01uF FIGURE 2 Monostable Waveforms During the timing cycle when the output is high the further application of a trigger pulse will not effect the circuit so long as the trigger input is returned high at least 10us before the end of the timing interval However the circuit can be reset during this time by the application of a negative pulse to the reset terminal
90. e contribution of resistors R2 and R3 thus minimizing the inherent out put voltage noise of the filter 5 s BI N 5725457 Figure 20 Single Supply Half and Full Wave Rectifier 4 5 V Low Dropout Low Power Reference rail to rail performance of the AD820 can be used to provide low dropout performance for low power reference circuits powered with a single low voltage supply Figure 21 shows a 4 5 V reference using the AD820 and the AD680 a low power 2 5 V bandgap reference R2 and R3 set up the required gain of 1 8 to develop the 4 5 V output R1 and C2 form a low pass RC filter to reduce the noise contribution of the AD680 100k0 5 FILM C3 10 F 25V REF COMMON Figure 21 Single Supply 4 5 V Low Dropout Reference With a 1 mA load this reference maintains the 4 5 V output with a supply voltage down to 4 7 V The amplitude of the recovery transient for a mA to 10 mA step change in load current is under 20 mV and settles out in a few microseconds Output voltage noise is less than 10 uV rms in a 25 kHz noise bandwidth 14 2 0 022 Vs 01 R1 R2 R3 D 243kO 243 243k0 7 C1 9 0 022uF AD820 O 2 _ Vout 4K 0 01 9 5 Vs 10 FREQUENCY Hz Figure 22 10 Hz Sallen Key Low Pass Filter REV D 10820 OUTLINE DIMENSIONS Mini DIP Package N 8 Dimensions shown in inches and mil
91. e of this information and all use of such information shall be entirely at the user s own risk Prices and specifications are subject to change without notice No patent rights or licenses to any of the circuits described herein are implied or granted to any third party BURR BROWN does not authorize or warrant any BURR BROWN product for use in life support devices and or systems BURR BROWN 3 PGA202 203 TYPICAL PERFORMANCE CURVES 25 Vs 15 unless otherwise noted GAIN vs FREQUENCY Gain dB 10 40 10 10 10 Frequency Hz CMRR vs FREQUENCY 160 120 80 40 CMRR dB 1 10 10 103 104 109 106 Frequency Hz INPUT NOISE vs FREQUENCY 104 103 Noise nV VHz 102 1 10 102 103 104 109 Frequency Hz BURR BROWN PGA202 203 GAIN ERROR vs FREQUENCY G 1000 10 1 Gain Error 1072
92. el programa tomara los datos y los mostrara en el monitor donde el programa a utilizar dependera de la punta intercambiable en uso AL PUERTO USB DE LA PC ENTRADA DEL ADC CONECTORES CONVERTIDOR MICROCONTROLADOR CON ANALOGICO DIGITAL PUEERTO USB FIGURA 3 2 2 Dispositivo maestro El programa para el osciloscopio volt metro y amper metro USB se hizo en lenguaje de alto nivel como ya mencion anteriormente se utilizo DELPHI 7 ya que este ambiente integrado de desarrollo IDE cuenta con grandes facilidades para la creaci n de interfaces gr ficas en Windows adem s de que el lenguaje Object Pascal que Delphi permite la comunicaci n multitarea y de bajo nivel con el sistema operativo de 32 bits y los puertos USB en todas sus versiones lo que es indispensable para recolectar la se al del dispositivo de la manera m s precisa Adem s el c digo binario generado por Delphi es muy ptimo y puede ejecutarse en pr cticamente cualquier versi n de Windows desde la 95 sin necesidad de instalar ninguna biblioteca ni controladores adicionales Unos pocos IDE como por ejemplo Visual ofrecen una velocidad de ejecuci n y comunicaci n como la que posee Delphi pero estos IDE no cuentan con facilidades de dise o como las de Delphi as que tomar a mucho m s tiempo desarrollar la interfaz del osciloscopio que tiene una gran cantidad 12 de controles Po
93. el correspondiente informe final San Jos 22 de septiembre de 2006 Bismart a FL Bismarck lvarez Baltodano Ced 8 065 629 Dedicatoria mi se or Jesus mi Dios Por la fortaleza y la luz que me diste en los momentos mas dif ciles A mi Madre Por que siempre fuiste un ejemplo de fortaleza bondad y amor y por que siempre me diste tu apoyo incondicional gracias porque se que de donde est s seguir s velando por mi Te amo A mis Hermanos Por su apoyo confianza en mi y por llenar de aligria mi vida A todos aquellos que de una manera u otra me tendieron su mano para que este proyecto fuera una realidad gracias han sido una gran bendici n iii Agradecimiento Agradezco primeramente a mi Dios mi se or Jes s porque siempre me ha dado la fortaleza necesaria para salir adelante y por llenarme de bendiciones en todo momento gracias De manera muy especial agradezco a mi madre su apoyo su amor su empe o y su fortaleza han sido un gran ejemplo para mi vida eres lo mas valioso que Dios me pudo haber regalado y te agradezco todo el gran esfuerzo que hiciste por mi Te amo gracias por todo lo que me diste A mis hermanos que siempre han estado con migo en los momentos dif ciles los buenos y por su gran apoyo A los profesores que de alguna manera estuvieron involucrados con este proyecto que me tendieron la mano cuando m s lo necesit mis amigos que a o tras a o me llenan de alegr a y que si
94. embalaje seria de 1 con lo que la pieza tendr a el valor de 1 1 R7 R8 AAA 1200 3 2 3 Figura 5 1 2 1 Circuito para la punta removible de volt metro Y cuyo embalaje se muestra en la figura 5 1 2 2 22 Figura 5 1 2 2 Embalaje para la punta removible de voltimetro Tabla 5 1 2 2 Costo de los materiales de la punta removible de volt metro Componentes Valor 2 0 Resistencias Placa para montaje 4 Conector 06 ____ Conector 0 TOTAL 5 1 3 An lisis para el circuito del dispositivo punta removible de amper metro Como se puede observar en la figura 5 1 3 1 correspondiente al circuito del volt metro que en la entrada de este se encuentra una resistencia de 1 ohm esta se encargara de hacer pasar la corriente a medir que ser de O a 2 5 voltios este valor de voltaje entrara en el amplificador operacional AD820 que la duplicara y de ah entrar al convertidor anal gico del dispositivo maestro El valor del AD820 es de 1 y las resistencias junto con la placa para el montaje tienen un valor de 0 1 el costo del embalaje seria exactamente igual que el del volt metro que es de 1 con lo que el valor total de materiales para la punta removible de amper metro es de 2 1 23 USO A LA ENTRADA ANALOGICA DEL DISPOSITIO MAESTRO TIERRA USB Figura 5 1 3 1 Circuito para la punta removible de amper metro El embalaje de este circuito es exac
95. emory space save components the clock signal is derived from just one RC pair on the first converter This output drives the other A Ds All the converters are started simultaneously with a STORE instruction at HEX address 5000 Note that any other HEX address of the form 5XXX will be decoded by the circuit pulling all the CS inputs low This can easily be avoided by using a more definitive address decoding scheme All the interrupts are ORed together to insure that all A Ds have completed their conversion before the microprocessor is interrupted The subroutine DATA IN may be called from anywhere in the user s program Once called this routine initializes the 0038 Upon IRQ low CPU FFF8 jumps to 0038 PIAORB Clear possible IRQ flags PIACRB Set Port Basinput 4934 3 Starts 0801 PIACRB Wait for interrupt 020 Is final data stored ENDP CONVRT PIAORB Read data in X Storeit 0200 Starting address for data storage 0200 Reinitialize TEMPI Return from subroutine 8006 user s program 8007 DS005671 A2 CPU starts all the converters simultaneously and waits for the interrupt signal Upon receiving the interrupt it reads the converters from HEX addresses 5000 through 5007 and stores the data successively at arbitrarily chosen HEX addresses 0200 to 0207 before returning to the user s pro gr
96. en sourcing 5 mA the saturation voltage to the positive supply rail will be 200 mV when sinking 5 mA the saturation voltage to the minus rail will be 100 mV The amplifier s open loop gain characteristic will change as a function of resistive load as shown in TPCs 7 through 10 For load resistances over 20 the AD820 s input error voltage is virtually unchanged until the output voltage is driven to 180 mV of either supply If the AD820 s output 15 driven hard against the output satura tion voltage it will recover within 2 us of the input returning to the amplifier s linear operating region REV D 10820 Direct capacitive load will interact with the amplifier s effective output impedance to form an additional pole in the amplifier s feedback loop which can cause excessive peaking on the pulse response or loss of stability Worst case is when the amplifier is used as a unity gain follower Figure 16 shows the AD820 s pulse response as a unity gain follower driving 350 pF This amount of overshoot indicates approximately 20 degrees of phase margin the system is stable but 15 nearing the edge Configurations with less loop gain and as a result less loop bandwidth will be much less sensi tive to capacitance load effects Figure 17 15 a plot of load that will result in a 20 degree phase margin versus noise gain for the AD820 Noise gain is the inverse of the feedback attenu ation factor provided by the feedback
97. en the Z 80 acknowledges the interrupt the program is vectored to a data input Z 80 subroutine This subroutine will read a peripheral status word from the DM74LS373 which contains the logic state of the INTR outputs of all the converters Each converter which initiates an interrupt will place a logic 0 in a unique bit position in the status word and the subroutine will determine the identity of the converter and execute a data read An identifier word which indicates which A D the data came from is stored in the next sequential memory location above the location of the data so the program can keep track of the identity of the data entered www national com 508090VW 08090V 2808090V 208090V 108090V ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Functional Description Continued OPEN SW1 CLOSE SW2 PREAMP 15 ZEROED AND PROPER INPUT CONVERSIONS CAN BE DONE www national com START ZEROING SUBROUTINE CLOSE SW1 OPEN SW2 INITIALIZE SAR BIT POINTER REG B X 80 INITIALIZE SAR CODE IN REG C REGC X 7F OUTPUT FIRST SAR CODE PORT X 80 START A D AND READ DATA QR REG B WITH REG C TO CLEAR BIT IN PORT B WHEN REAPPLIED SHIFT 1 IN REG B RIGHT TO POINT TO NEXT BIT YES IS REG B ZERO NO EXCLUSIVE OR REG B WITH REG C TO SET NEXT BIT IN PORT B OUTPUT NEW SAR CODE TO PORT B FIGURE 20 Flow Chart for Auto Zero Routine DS005671 28 36 Functional Descript
98. ero Error and Non Linearity Part Full 2 2 500 Voc 2 Connection 5 Adjustments No Adjustments Adjusted ADCO802 7 LSB ADCO803 1 LSB www national com 2 Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Distributors for availability and specifications Supply Voltage Note 3 Voltage Logic Control Inputs At Other Input and Outputs Lead Temp Soldering 10 seconds Dual In Line Package plastic Dual In Line Package ceramic Surface Mount Package Vapor Phase 60 seconds 0 3V Electrical Characteristics Notes 1 2 Infrared 15 seconds Storage Temperature Range Package Dissipation at Ta 25 C ESD Susceptibility Note 10 Sales Office Operating Ratings notes 1 0 3V to 18V Temperature Range to 0 3 08041 ADC0801 02 03 05LCN 260 C 08041 300 ADC0802 04LCWM Range of Vcc 215 C 220 65 C to 150 2 875 mW 800V 40 C lt T lt 85 C 40 CS lt T lt 85 C 0 C lt T lt 70 C 0 lt lt 70 4 5 to 6 3 The following specifications apply for Vcc25 Voc lt lt and fe 640 kHz unless otherwise specified With Full Scale 14 LSB See Section 2 5 2 Parameter ADC0801 Total Adjusted Error Note 8 ADC0802 T
99. este dando ordenes por medio de interrupciones este convertidor anal gico est conectado con sus 8 bits al puerto O del microcontrolador cy c63001 que es con este puerto que el microcontrolador estar tomando los datos del convertidor anal gico digital para que luego con ayuda del microcontrolador que incorpora el puerto USB se puedan convertir los datos de tal forma que estos puedan ser enviados a la computador por medio del puerto USB Como se puede observar en el ADC se encuentra una resistencia de 10 seguido de un capacitor de 150 nF con esta configuraci n se obtienen los pulsos de reloj necesarios para que el ADC pueda hacer sus conversiones y tambi n determina la velocidad de las conversiones del ADC el capacitor de 10 uF es utilizado como filtro de ruido el voltaje de referencia del ADC es de 2 5 V este se obtiene con la ayuda de un divisor de voltaje formado por dos resistencia de 330 ohms la resistencia de 7 5 Ko que se encuentra entre la patilla R y tierra del microcontrolador CY7C63001 se utiliza para decirle a la computadora que el dispositivo que se esta utilizando tiene puerto USB 1 las patillas correspondientes a R y R est n conectadas al puerto USB mini B a este puerto tambi n fueron conectados los cables de 5v y tierra para que fueran proporcionados el puerto USB de la computadora con lo que el circuito queda totalmente alimentado con el puerto USB Este dispositivo tiene un conector hembra de 6 pines que ser til p
100. fios electr nicos no siempre cumplen cabalidad los objetivos y las metas de funcionamiento planteados para esa etapa en espec fico as como tambi n el circuito varia el embalaje de los circuitos tambi n var a segun las especificaciones geom tricas del circuito 4 5 Reevaluaci n y redise o Debido a que la tecnolog a actual en microcontroladores y en miniaturizaci n de componentes electr nicos avanzando a pasos agigantados es recomendable estar verificando las nuevas tecnolog as para de esta forma estar ofreciendo un producto de mejor calidad y m s econ mico adem s de implementar nuevas puntas intercambiables que permitan medir otras variables f sicas que permitan expandir el mercado meta del producto 19 Capitulo 5 Descripci n detallada de la soluci n Explicaci n del 1 5 1 An lisis de soluciones y selecci n final Para poder llevar acabo de forma satisfactoria el adecuado funcionamiento del sistema hay que hacer un an lisis de las soluciones planteadas y un estudio de las caracter sticas de los materiales a utilizar para as tener la certeza de que son los mas adecuados es por ello que acontinuaci n se har una descripci n de cada una de las etapas de los circuitos implementados 5 1 1 An lisis para el circuito del dispositivo maestro Los componentes escogidos para desarrollar este circuito fueron el microcontrolador de la Cypress el 7 63001 que ya contiene el puerto USB y como se mencion
101. gain adjustment is required However if necessary the gains can be increased by the use of an external attenuator around the output stage as shown in Figure 3 Recommended resistor values for certain selected output gains are given in Table II FIGURE 3 Gain Increase with Buffered Attenuator COMMON MODE INPUT RANGE Unlike the classical three op amp type of circuit the input common mode range of the PGA202 203 does not depend on the differential input and the gain In the standard three op amp circuit the input common mode signal must be kept below the maximum output voltage of the input amplifier minus 1 2 the final output voltage If for example these amplifiers can swing 12 then to get 12V at the output you must restrict the input common mode voltage to only 6V The circuitry of the PGA202 203 15 such that the common mode input range applies to either input pin regardless of the output voltage BURR BROWN PGA202 203 OUTPUT SENSE An output sense has been provided to allow greater accuracy in connecting the load By attaching this feedback point to the load at the load site IR drops due to the load currents are eliminated since they are inside the feedback loop Proper connection is shown in Figure 1 When more current is required a power booster can be placed in the feedback loop as shown in Figure 4 Buffer errors are minimized by the loop gain of the output amplifier FIGURE 4 Current Boosting the Output
102. ges to Match an Arbitrary Input Signal Range 2 5 Errors and Reference Voltage Adjustments 2 5 1 Zero Error The zero of the A D does not require adjustment If the minimum analog input voltage value is not ground a zero offset can be done The converter can be made to output 0000 0000 digital code for this minimum input voltage by biasing the A D Vin input at this value see Applications section This utilizes the differential mode op eration of the A D The zero error of the A D converter relates to the location of the first riser of the transfer function and can be measured by grounding the Vin input and applying a small magnitude positive voltage to the V input Zero error is the differ ence between the actual DC input voltage that is necessary to just cause an output digital code transition from 0000 0000 to 0000 0001 and the ideal 12 LSB value 2 LSB 9 8 mV for 2 2 500 2 5 2 Full Scale The full scale adjustment can be made by applying a differ ential input voltage that is 172 LSB less than the desired analog full scale voltage range and then adjusting the mag nitude of the 2 input pin 9 or the Vec supply if pin 9 is not used for a digital output code that is just changing from 1111 1110 to 1111 1111 2 5 3 Adjusting for an Arbitrary Analog Input Voltage Range If the analog zero voltage of the A D is shifted away from ground for example to accommodate an anal
103. hardware details are pro vided separately for each type of microprocessor 4 1 Interfacing 8080 Microprocessor Derivatives 8048 8085 This converter has been designed to directly interface with derivatives of the 8080 microprocessor The A D can be mapped into memory space using standard memory ad dress decoding for CS and the MEMR and MEMW strobes or it can be controlled as an device by using the R and W strobes and decoding the address bits AO gt or address bits A8 A15 as they will contain the same 8 bit address information to obtain the CS input Using the I O space provides 256 additional addresses and may allow a simpler 8 bit address decoder but the data can only be input to the accumulator To make use of the additional memory reference instructions the A D should be mapped into memory space An example of an A D in I O space is shown in Figure 12 Functional Description continued DAC1000 10 BIT 8 BIT A D UNDER TEST VANALOG OUTPUT ANALOG INPUT VOLTAGE 100X ANALOG ERROR VOLTAGE DS005671 89 FIGURE 10 A D Tester with Analog Error Output DIGITAL INPUT FIGURE 11 Basic Digital A D Tester DAC1000 10 BIT DAC A D UNDER TEST DIGITAL OUTPUT DS005671 90 TABLE 1 DECODING THE DIGITAL OUTPUT LEDs OUTPUT VOLTAGE FRACTIONAL BINARY VALUE FOR CENTER VALUES WITH 2 2 560 LS GROUP VMS VLS GROUP GRO
104. he Program Stack Pointer PSP and the Data Stack Pointer DSP The value of PSP after reset is 0x00 The PSP is incremented by 2 whenever a CALL instruction is executed and it is decremented by 2 whenever a instruction is used The DSP is pre decremented by 1 whenever a PUSH instruction is executed and it is incremented by 1 after a POP instruction is used The default value of the DSP after reset is 0x00 which would cause the first PUSH to write into USB FIFO space for End Point 1 Therefore the DSP should be mapped to a location such as 0x70 before initiating any data stack operations Refer to the Reset section for more information about DSP re mapping after reset Figure 5 2 illustrates the Data Memory Space after reset Address 10 0x02 0x04 Y DSP 0x70 USB FIFO Endpoint 0 Ox77 0x78 USB FIFO Endpoint 1 Ox7F Figure 5 2 Data Memory Space 5 2 Register Summary I O registers are accessed via the I O Read and I O Write IOWR IOWX instructions Table 5 1 Register Summary Regsterhame WO Address ReadWite Port 1 Pull up 0x09 CY7C63000 CY7C63001 pu CY7C63100 CY7C63101 o _ PRELIMINARY CY7C63200 CY7C63201 Table 5 1 Register Summary continued Register Name VO Address Read Write Global Interrupt Enable Global Interrupt Enable Watch Dog Timer Watch Dog Timer clear Cext Clear Exter
105. he result is a high performance programmable instrumentation amplifier with excellent speed and gain accuracy The input stage uses a new circuit topology that includes FET buffers to give extremely low input bias currents The differential input voltage is converted into a differential output current with the transconductance gain selected by steering the input stage bias current between four identical input stages differing only in the value of the gain setting resistor Each input stage is individually laser trimmed for input offset offset drift and gain The output stage is a differential transimpedance amplifier Unlike the classical difference amplifier output stage the common mode rejection is not limited by the resistor match ing However the output resistors are laser trimmed to help minimize the output offset and drift BASIC CONNECTIONS Figure 1 shows the proper connections for power supply and signal The power supplies should be decoupled with 1uF tantalum capacitors placed as close to the amplifier as possible for maximum performance To avoid gain and CMR errors introduced by the external components you should connect the grounds as indicated Any resistance in the sense line pin 11 or line pin 4 will lead to a gain error so these lines should be kept as short as possible To also maintain stability avoid capacitance from the output to the input or the offset adjust pins FIGURE 1 Basic Circuit
106. ic signal wires and leads should be grouped and kept as far away as possible from the analog signal leads Exposed leads to the analog inputs can cause undesired digital noise and hum pickup therefore shielded leads may be necessary in many applications A single point analog ground that is separate from the logic ground points should be used The power supply bypass capacitor and the self clocking capacitor if used should both be returned to digital ground Any 2 bypass ca pacitors analog input filter capacitors or input signal shield ing should be returned to the analog ground point A test for proper grounding is to measure the zero error of the A D converter Zero errors in excess of 4 LSB can usually be traced to improper board layout and wiring see section 2 5 1 for measuring the zero error 3 0 TESTING THE A D CONVERTER There are many degrees of complexity associated with test ing an A D converter One of the simplest tests is to apply a known analog input voltage to the converter and use LEDs to display the resulting digital output code as shown in Figure 9 For ease of testing the 2 9 should be supplied with 2 560 Vpc and Vec supply voltage of 5 12 Vpc should be used This provides an LSB value of 20 mV If a full scale adjustment is to be made an analog input voltage of 5 090 5 120 17 gt LSB should be applied to the Vin pin with the Vin pin grounded The value of the
107. inter s como amazon com jameco com o digikey com han sido fuentes importantes de informaci n y de adquisici n de componentes necesarios para este proyecto Con respecto a los impresos para circuitos de soldadura de superficie existe informaci n de c mo llevar a cabo este tipo de impresos en Internet adem s como se mencion anteriormente y con la ayuda de la Escuela de electr nica del Instituto Tecnol gico que cuenta con un laboratorio de circuitos impresos y que llevaron acabo la fabricaci n del impreso Como anteriormente se mencion la empresa Fibrocentro fue la encargada de dar la asesor a necesaria para poder hacer un embalaje con resina que permiti que el sistema a implementar sea a n m s econ mico 16 Con respecto a la circuiter a necesaria para el sistema ya la gran mayor a de los integrados han sido utilizados en uno o varios de los laboratorios cursados durante la carrera tales como los amplificadores operacionales y el convertidos anal gico digital cuyo manejo viene claramente explicado en los libros de texto utilizados en la carrera la nica diferencia fue para el caso los amplificadores operacionales que se deb a tomar en cuenta el ancho de banda y el voltaje de polarizaci n ya que el circuito debe de ser de baja potencia para poder ser alimentado con la energ a proveniente del puerto USB la cual es de 5 voltios y 500 mA a esto hay que agregarle que el montaje de estos componente debe de ser de
108. ion continued Note 29 All numerical values are hexadecimal representations 5000 3002 5004 3006 007 5009 3DOB 3DOD SDOE 5010 5015 3015 5016 5017 3D1A 3D1B 3010 5020 021 3023 5024 026 5029 3D2A 3D2D 3D2E 3D2F 3D30 3D33 3D34 3D37 3D38 3D39 3D3B 3D3D 3C3D 3CSF 5041 5042 5045 5045 5048 3 90 D3E7 2601 7C D3E6 0680 D3E5 SLAASD 03 4 00 C3163D 7A C600 CA2D3D 78 600 lF FEOO CA373D 47 C3333D 79 BO C3203D A9 C30D3D 47 7C EEOS D3E6 DBE4 EEFF 57 78 EGFF C21A3D C33D3D 90 Out Control Port MVIHOI MOV A H OUT C MVI B 80 MOV C A OUT B LXI SP 3DAA OUT A IE NOP JMP Loop MOV A D ADI 00 JZ Set C MOV A B ORI 00 RAR CPI 00 JZ Done MOV B A JMP New C MOV ORA B MOV C A JMP Shift B XRA C JMP Return MOV B A MOV XRI 03 OUT C Program for processing proper data values INA XRI FF MOV D A MOV A B ANI FF JNZ Auto Zero JMP Normal Program PPI Auto Zero Subroutine Close SW1 open SW2 Initialize SAR bit pointer Initialize SAR code Return s Port SAR code Start Dimension stack pointer Start A D Loop Loop until INT asserted Auto Zero Test A D output data for zero Shift B Clear carry Shift l inBright one place IS Bzero If yes last approximation has been made Set setbitinCthatisinsame positionas 1 New Clear bit
109. ispositivo maestro 32 Cap tulo 1 1 1 Problema existente e implementaci n de su soluci n Los aparatos de medici n en electr nica siempre se han caracterizado por ser sumamente costosos por lo que las empresas medianas y grandes y las universidades son las que pueden adquirir estos productos no sin antes haber hecho una fuerte inversi n para comprarlos con lo que estos aparatos quedan fuera del alcance de cualquier persona que desee tener su propio laboratorio de electr nica o incluso de empresas que necesiten adquirirlos pero que no tengan el capital para este fin Actualmente en el mercado los mult metros pueden costar desde los 12000 colones hasta los 50000 colones en el pa s dependiendo de las funciones que desempefie y de su calidad Los osciloscopios pueden tener costos que van desde los 300 hasta los 1500 dependiendo de su calidad y rango de trabajo esto en EE UU Es por los costos que surge la necesidad de disefiar un aparato de medici n de bajo costo y de alta calidad que pueda ser accesible y que satisfaga las necesidades de aquellos que ocupen aparatos electr nicos de medici n 1 2 Soluci n seleccionada El sistema que se desea implementar es un dispositivo USB de bajo costo que permita medir corriente tensiones y hacer las funciones de osciloscopio por tanto se decidi hacer un dispositivo de puntas intercambiables estas pu
110. izaci n de amplificadores de instrumentaci n e inversores de tensi n Para la protecci n del circuito en caso de picos de corriente en la red el ctrica no se utiliz m s que la protecci n que ya incluye la fuente de poder de la computadora Para la parte de programa se utiliz DELPHI que es un lenguaje de alto nivel del cual se encuentra mucha documentaci n y cuya base es PASCAL que fue el lenguaje con el que aprend a programar y que me permiti la r pida comprensi n de DELPHI Por ltimo en lo que respecta al embalaje del producto debido a las dimensiones del dispositivo maestro se decidi que lo m s econ mico seria utilizar resina para hacer el embalaje de igual forma para las puntas removibles de amper metro y pero no as para la punta de osciloscopio que por sus dimensiones ya no resulta viable utilizar resina por lo que se implement su dise o para que sea hecho en pl stico inyectado Capitulo 2 2 1 Meta Meta y objetivos Construir un producto de medici n de variables f sicas de bajo costo de muy buena calidad que sea de f cil manejo para el usuario que est acostumbrado a utilizar esta clase de equipo 2 2 Objetivos general Desarrollar un sistema econ mico que por medio del puerto USB de una PC permita medir datos de variables f sicas como tensi n y corriente y adem s implementar un osciloscopio 2 3 Objetivos espec ficos a Objetivos de circuiteria Desarrollar un di
111. k frequencies the duty cycle limits can be extended so long as the minimum clock high time interval or minimum clock low time interval is no less than 275 ns Note 6 With an asynchronous start pulse up to 8 clock periods may be required before the internal clock phases are proper to start the conversion process The start request is internally latched see Figure 4 and section 2 0 www national com 4 AC Electrical Characteristics Continued Note 7 The CS input is assumed to bracket the WR strobe input and therefore timing is dependent on the WR pulse width An arbitrarily wide pulse width will hold the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse see timing diagrams Note 8 None of these A Ds requires a zero adjust see section 2 5 1 To obtain zero code at other analog input voltages see section 2 5 and Figure 7 Note 9 The Vrer 2 pin is the center point of a two resistor divider connected from Vcc to ground In all versions of the ADCO801 ADCO802 ADC0803 and ADCO805 and the ADCO804LCJ4 each resistor is typically 16 In all versions of the ADCO804 except the 08041 each resistor is typically 2 2 Note 10 Human body model 100 pF discharged through a 1 5 resistor Typical Performance Characteristics Logic Input Threshold Voltage vs Supply Voltage LOGIC INPUT THRESHOLD VOLTAGE V 1 8 pasestasiase MIR
112. k up to 200mA or drive TTL circuits Schematic Diagram O ee A Sep THRESHOLD WD CONTROL 9 2 3 Vcc VOLTAGE 1 GND O DISCHARGE O 014 2000 National Semiconductor Corporation 05007851 February 2000 999017 Features Direct replacement for SE555 NE555 Timing from microseconds through hours Operates in both astable and monostable modes Adjustable duty cycle Output can source or sink 200 mA Output and supply TTL compatible Temperature stability better than 0 005 Normally on and normally off output Available in 8 pin MSOP package Applications Precision timing Pulse generation Sequential timing Time delay generation Pulse width modulation Pulse position modulation Linear ramp generator R6 028 3 O OUTPUT 2 08 TRIGGER 4 T MEER REL EMBED DS007851 1 www national com LM555 Connection Diagram Dual In Line Small Outline and Molded Mini Small Outline Packages GND TRIGGER DISCHARGE OUTPUT THRESHOLD RESET CONTROL VOLTAGE DS007851 3 Top View Ordering Information Part Number Package Marking Media Transport NSC Drawing 8 Pin SOIC LM555CM LM555CM m LM555CMX LM555CM 2 5 Units Tape and Reel 8 MSOP 5550 PES ape and Ree MUAOSA LM555CMMX 3 5k Units Tape and Reel 8 Pin MDIP LM555CN LM555CN NOSE www national com 2 Absolute Maximum Ratings Note 2 If Military Aerospace specifie
113. levels that drive the auto zero resistors be constant Also for symmetry a logic swing of OV to 5V is convenient To achieve this a CMOS buffer is used for the logic output signals of Port B and this CMOS package is powered with a stable 5V source Buffer amplifier A1 is necessary so that it can source or sink the D A output current 47k 100k 200k FROM OUTPUT 390k PORT B BUFFER 793k 1 56 M 3 16M DS005671 91 FIGURE 18 Gain of 100 Differential Transducer Preamp www national com 34 Functional Description continued INVERTING ADDRESS BUFFERS 8080A ADDRESS BUS PORT A BUFFERS INS8202 07 8080A 1 58255 DATA BUS MM74C00 PORTC BUFFERS 74 00 8080A CONTROL SIGNALS DM8131 OUTPUT VOUT PREAMP VOUT Of OUTPUTS VREF 2 DS005671 92 FIGURE 19 Microprocessor Interface Circuitry for Differential Preamp A flow chart for the zeroing subroutine is shown in Figure 20 It must be noted that the ADCO801 series will output an all zero code when it converts a negative input Vin gt Vin Also a logic inversion exists as all of the ports are buffered with inverting gates Basically if the data read is zero the differential output voltage is negative so a bit in Port B is cleared to pull Vx more negative which will make the output more positive for the next conversion If the data read is not zero the output voltage is positive so
114. limeters 0 39 9 91 MAX A 0 25 0 31 6 35 7 87 0 30 7 62 REF 0 035 0 01 0 165 0 01 0951025 4 19 0 25 0 011 0 003 0 125 8 18 eee 0 28 0 08 15 0018 0 003 JL D 0 0 46 0 08 064 PLANE SOIC Package R 8 Dimensions shown in millimeters inches 5 02 0 1968 80 0 80 0 1574 4 00 6 20 0 2440 0 1497 3 80 5 80 0 2284 y E PIN 1 AU e 0 050 0 50 0 0196 asc 5 25 0 0099 lt 45 COPLANARITY 1 75 0 0688 0 25 0 0098 0 10 0 0040 114 SEATING 2 51 0 0201 0 25 0 0298 amp 1 27 0 0500 PLANE 0 33 0 0130 0 19 0 0275 0 41 0 0160 CONTROLLING DIMENSIONS ARE IN MILLIMETERS INCH DIMENSIONS IN PARENTHESES ARE ROUNDED OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO STANDARDS MS 012 AA REV D 15 10820 Revision History Location Page Data Sheet changed from REV C to REV D Changeto SOIC Package R 8 Drawing Pared P RE dasi bend RE Ede acie d 15 Eds to PERATUKES sisas atari ER det RE W s Bw MEO Bep eam ewe che eee E eben d 1 Edits to PRODUC TF DESCRIPTION ab 0o dieto de ds arde a ao ace ct dia 1 Delete SPECIFICATIONS Tor ADS20A 9NV ESI CHEE SBE KORE SEES card oo sd 5 Eds ORDERING GUIDE
115. ll be set to record this event If the USB reset happens while the device is suspended such as after a the suspend condition will be cleared and the clock oscillator will be restarted However the microcontroller is not released until the USB reset is removed 5 4 On chip Timer The USB Controller is equipped with an 8 bit free running timer driven by a clock one sixth the crystal frequency Bits 0 through 7 of the counter are readable from the read only Timer Register located at I O address 0x23 The Timer Register is cleared during a Power On Reset Figure 5 5 illustrates the format of this register and Figure 5 6 is its block diagram With a 6 MHz crystal the timer resolution is 1 us The timer generates two interrupts the 128 us interrupt and the 1 024 ms interrupt Figure 5 5 Timer Register Address 0x23 11 CY7C63000 CY7C63001 pu CY7C63100 CY7C63101 ES _ PRELIMINARY CY7C63200 CY7C63201 1 024 ms interrupt 128 us interrupt m ALL Figure 5 6 Timer Block Diagram To Timer Register 5 5 General Purpose Ports Interface with peripherals is conducted via 12 GPIO signals These 12 signals are divided into two ports Port O and Port 1 Port 0 contains eight lines 0 0 0 7 and Port 1 contains up to eigth lines P1 0 P1 7 depending on the package Both ports can be accessed by the IORD IOWR and IOWX instructions The Port 0 data register is located at address 0x00 while the Port 1 data register i
116. ller contains a separate latch for each interrupt except the Wake up interrupt When an interrupt is generated itis latched as a pending interrupt It will stay as a pending interrupt until it is serviced or a reset occurs The Wake up interrupt is not latched and is pending whenever the Cext pin is high A pending interrupt will only generate an interrupt request if it is enabled in the Global Interrupt Enable Register The highest priority interrupt request will be serviced following the execution of the current instruction When servicing an interrupt the hardware will first disable all interrupts by clearing the Global Interrupt Enable Register Next the interrupt latch of the current interrupt is cleared This is followed by a CALL instruction to the ROM address associated with the interrupt being serviced i e the Interrupt Vector The instruction in the interrupt table is typically a JMP instruction to the address of the Interrupt Service Routine ISR The user can re enable interrupts in the interrupt service routine by writing to the appropriate bits in the Global Interrupt Enable Register Interrupts can be nested to a level limited only by the available stack space 128 us CLR NN logic 1 1D Q 9 Enable 1 128 us IRQ 1 ms CLR 12805 CLK Interrupt End PO IRQ ES End P1 CLR Global Enable 7 0 End P1 IRQ nable D oon pL CLR CLR 0 Enable 6 B GPIO Interrupt GPIO Ack
117. log input voltage range with single 5V supply No zero adjust required 0 3 standard width 20 pin DIP package 20 pin molded chip carrier or small outline package Operates ratiometrically or with 5 2 5 or analog span adjusted voltage reference Key Specifications m Resolution 8 bits B Total error 14 LSB 15 LSB and 1 LSB Conversion time 100 us ADCO80X Dual In Line and Small Outline SO Packages 1 2 5 4 5 6 7 8 9 OR CLKR DBO LSB DB7 MSB DS005671 30 See Ordering Information Ordering Information TEMP RANGE 14 Bit Adjusted ERROR 112 Bit Unadjusted 2 Bit Adjusted 1Bit Unadjusted PACKAGE OUTLINE Z 80 is a registered trademark of Zilog Corp 2001 National Semiconductor Corporation DS005671 0 70 0 70 ADCO804LCWM M20B Small Outline 40 C TO 85 ADCO0801LCN ADCOS802LCN ADCO0804LCN ADCO805LCN ADCO804LCJ N20A Molded DIP www national com 5 V eiqneduio 118 8 SO80DdV Pos0ddv e0800dv z0800dv L0800avV ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Typical Applications TRANSDUCER 8 BIT RESOLUTION OVER ANY DESIRED ANALOG INPUT VOLTAGE RANGE SEE SECTION 2 4 1 ANY uPROCESSOR SPAN ADJ SEE SECTION 2 4 1 DS005671 1 NSC800 8080 280 8048 05005671 31 Error Specification Includes Full Scale Z
118. lowest power consumption Note Logic inputs can be driven to Vcc with A D supply at zero volts Buffer prevents data bus from overdriving output of A D when in shutdown mode Functional Description 1 0 UNDERSTANDING A D ERROR SPECS A perfect A D transfer characteristic staircase waveform is shown in Figure 1 The horizontal scale is analog input voltage and the particular points labeled are in steps of 1 LSB 19 53 mV with 2 5V tied to the 2 pin The digital output codes that correspond to these inputs are shown as www national com 16 Vcc 5 Voc CMOS BUFFER BUS TO DATA DS005671 80 D 1 D and 0 1 For the perfect A D not only will center value A 1 A 1 analog inputs produce the correct output digital codes but also each riser the transitions between adjacent output codes will be located LSB away from each center value As shown the risers are ideal and have no width Correct digital output codes will be provided for a range of analog input voltages that extend Functional Description continued 2 LSB from the ideal center values Each tread the range of analog input voltage that provides the same digital output code is therefore 1 LSB wide Figure 2 shows a worst case error plot for the ADCO0801 center valued inputs are guaranteed to produce the correct output codes and the adjacent risers are guaranteed to be no closer to the center value points than LSB In other words
119. ls have been renamed when compared to the standard A D Start and Output Enable labels addition these inputs are active low to allow easy interface to microprocessor control busses For non microprocessor based applications the CS input pin 1 can be grounded and the standard A D Start function is obtained by an active low pulse applied at the WR input pin 3 and the Output Enable function is caused by an active low pulse at the RD input pin 2 www national com ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Functional Description Continued 2 2 Analog Differential Voltage Inputs and Common Mode Rejection This A D has additional applications flexibility due to the analog differential voltage input The Vi input 7 can be used to automatically subtract a fixed voltage value from the input reading tare correction This is also useful in 4 mA 20 mA current loop conversion addition common mode noise can be reduced by use of the differen tial input The time interval between sampling V n and is 4 v2 clock periods The maximum error voltage due to this slight time difference between the input voltage samples is given by 4 5 AVe MAX Vp 2 E where AV is the error voltage due to sampling delay Vp is the peak value of the common mode voltage is the common mode frequency As an example to keep this error to 14 LSB 5 mV when operating with 60 Hz common mode frequency
120. mA ppm C 9o N 96 X Vcc mA nA mV mV www national com 9991 1171 LM555 Electrical Characteristics Notes 1 2 Continued 25 5V to 15V unless othewise specified Parameter Output Voltage Drop Low Output Voltage Drop High Rise Time of Output Fall Time of Output Conditions Vcc 15V 10mA lsink 50mA 100mA 200mA Voc 5V Isink 8MA SMA 200mA 15V lsource 100MA Voc 15V Voc 5 lsource Note 1 All voltages are measured with respect to the ground pin unless otherwise specified 12 75 2 75 Limits LM555C 12 5 13 3 3 9 100 0 35 7 Units Note 2 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur Operating Ratings indicate conditions for which the device is func tional but do not guarantee specific performance limits Electrical Characteristics state DC and AC electrical specifications under particular test conditions which guar antee specific performance limits This assumes that the device is within the Operating Ratings Specifications are not guaranteed for parameters where no limit is given however the typical value is a good indication of device performance Note 3 For operating at elevated temperatures the device must derated above 25 C based on a 150 C maximum junction temperature and a thermal
121. mation continued 50 DUTY CYCLE OSCILLATOR For a 50 duty cycle the resistors Ra and Rg may be con nected as in Figure 14 The time period for the output high is the same as previous t 0 693 Ra C For the output low it IS to Rg a Rg Ra R C Z RA Rg RA Thus frequency of oscillation is 1 f ty to www national com DS007851 18 FIGURE 14 50 Duty Cycle Oscillator Note that this circuit will not oscillate if Rg is greater than 1 2 Ra because the junction of R4 and cannot bring 2 down to 1 3 Vec and trigger the lower comparator ADDITIONAL INFORMATION Adequate power supply bypassing is necessary to protect associated circuitry Minimum recommended is 0 1uF in par allel with 1uF electrolytic Lower comparator storage time be as long 10us when pin 2 is driven fully to ground for triggering This limits the monostable pulse width to 10us minimum Delay time reset to output is 0 47us typical Minimum reset pulse width must be 0 5 typical Pin 7 current switches within 30ns of the output pin 3 volt age 9991 1171 Physical Dimensions inches millimeters unless otherwise noted 0 189 0 197 4 800 5 004 8 7 8 5 0 228 0 244 5 791 6 198 0 010 0 254 LEADNO 1 1 2 3 4 A 30 IDENT 0 150 0 157 3 810 3 988 0 010 0 020 45 1 DRE 0254 0 508 1 346 1 753 n ALL LEADS 0
122. mee a CT AAT AA of Basa O A ae A DS007851 23 9991 1171 LM555 Typical Performance Characteristics Continued Output Propagation Delay vs Output Propagation Delay vs Voltage Level of Trigger Pulse Voltage Level of Trigger Pulse 1200 1200 gt 1000 1000 gt gt lt 800 uJ e e 600 E E 5 5 Pl eec 10v asv Vec 10V 15 200 d 0 0 0 1 0 2 0 3 0 0 1 0 2 0 3 LOWEST VOLTAGE LEVEL OF TRIGGER PULSE X Vcc LOWEST VOLTAGE LEVEL OF TRIGGER PULSE X Vec DS007851 24 DS007851 25 Discharge Transistor Pin 7 Discharge Transistor Pin 7 Voltage vs Sink Current Voltage vs Sink Current 1000 1000 Saad n 2 EH 111111008 i a i 7411 gt 100 EIA p mn gt gt 2 10 EIN e E 10 e HH E E Es S DEBE us FERE AAA 0 01 0 1 1 0 10 100 0 01 0 1 1 0 10 100 mA PIN 7 mA PIN 7 DS007851 26 DS007851 27 www national com 6 Applications Information MONOSTABLE OPERATION In this mode of operation the timer functions as a one shot Figur
123. n for the ON resistance of the switches as they must conduct only the input bias current of the input amplifiers Output Port B is used as a successive approximation regis ter by the 8080 and the binary scaled resistors in series with each output bit create a D A converter During the zeroing subroutine the voltage at V increases or decreases as required to make the differential output voltage equal to zero This is accomplished by ensuring that the voltage at the output of A1 is approximately 2 5V so that a logic 1 5 on www national com 508090VW 08090V 2808090V 208090V 108090V ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Functional Description Continued any output of Port B will source current into node V thus raising the voltage at Vx and making the output differential more negative Conversely a logic 0 will pull current out of node Vx and decrease the voltage causing the differ ential output to become more positive For the resistor val ues shown Vx can move 12 mV with a resolution of 50 uV which will null the offset error term to 1 4 LSB of full scale for AVIN 2 5V gt AVIN 2 5V 2 62 5 FROM OUTPUT PORT C FIGURE 18 Note 26 R2 49 5 H1 Note 27 Switches are LMC13334 CMOS analog switches Note 28 The 9 resistors used in the auto zero section can be 5 tolerance R2 R R2 5 24k the ADC0801 It is important that the voltage
124. n of the PGA202 where other factors in the input stage begin to dominate APPLICATIONS In addition to general purpose applications the PGA202 203 are designed to handle two important and demanding classes of applications inputs with high source impedances and rapid scanning data acquisition systems requiring fast set tling time Because the user has access to output sense and output common pins current sources can also be constructed with a minimum of external components Some basic appli cation circuits are shown in Figures 6 through 12 Coupler FIGURE 6 Isolated Programmable Gain Instrumentation Amplifier Counter Gain Control FIGURE 8 AC Coupled Differential Amplifier for Frequencies Above 0 16Hz BURR BROWN PGA202 203 Gain Control FIGURE 9 Floating Source Programmable Gain Instrumen tation Amplifier FIGURE 11 Programmable Differential In Differential Out Amplifier Gain Control Gain Control FIGURE 10 Low Noise Differential Amplifier with Gains of 100 200 400 800 FIGURE 12 Programmable Current Source A a a 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FIGURE 13 Cascaded Amplifiers BURR BROWN PGA202 203 10
125. n su apoyo no hubiera concluido el proyecto Resumen El siguiente proyecto consiste en implementar un osciloscopio un amperimetro y un volt metro por medio del puerto USB de la computadora Como bien se sabe el osciloscopio es uno de los instrumentos m s utilizados en electr nica pero su precios es muy alto y es por ello que se desea implementar un osciloscopio con ayuda del computador utilizando el puerto USB esto con el fin de abaratar el costo de un osciloscopio para que sea m s accesible incluso a los mismos estudiantes de t cnico diplomado e ingenier a en electr nica el ctrica y cualquier rea en la que se pueda utilizar un osciloscopio Cabe mencionar que la tecnolog a de la computaci n ha avanzado a pasos agigantados abaratando los costos de las computadoras siendo m s r pidas y accesibles es por ello que se desea aprovechar aun m s las capacidades de la computadora por medio de este proyecto Adem s del osciloscopio se desea que el producto tambi n tenga la capacidad de medir corriente y tensi n para extender a n m s sus capacidades El sistema consistir en un aparato de puntas intercambiables que conecta al puerto USB de tal forma de que si el usuario desea utilizar el osciloscopio le conectar al aparato una extensi n que le permita utilizarlo como osciloscopio de igual forma si desea utilizar el aparato como volt metro solamente tendr que conectar la extensi n que le permita utilizarlo
126. nal R C Timing circuit control Port 0 Isink 0x30 0x37 Input sink current control for Port O pins There is one Isink register for each pin Address of the Isinkregister for pin O is located at 0x30 and the register address for pin 7 is located at 0x37 Port 1 Isink 0x38 0x3B W Input sink current control for Port 1 pins There is one Isink register for each pin Address of the Isink register for pin O is located at 0x38 and the register address for pin 3 is located at OX3B Status amp Control Processor status and control 5 3 Reset The USB Controller supports three types of resets All registers are restored to their default states during a reset The USB Device Address is set to O and all interrupts are disabled In addition the Program Stack Pointer PSP is set to 0x00 and the Data Stack Pointer DSP is set to 0x00 The user should set the DSP to location 0x70 to reserve 16 bytes of FIFO space The assembly instructions to do so are Mov A 70h Move 70 hex into Accumulator use 70 instead of 6F because the dsp is always decremented by 1 before data transfer in the PUSH instruction Swap dsp Move Accumulator value into dsp The three reset types are 1 Power On Reset POR 2 Watch Dog Reset WDR 3 USB Reset The occurrence of a reset is recorded in the Status and Control Register located at I O address OxFF Figure 5 3 Reading and writing this register are supported by the IORD and IOWR instructions Bits 1 2 and 7 are
127. nals a major system error is the input offset voltage of the amplifiers used for the preamp Figure 18 is a gain of 100 differential preamp whose offset voltage errors will be cancelled by a zeroing subroutine which is performed by the INS8080A microprocessor sys tem The total allowable input offset voltage error for this preamp is only 50 uV for 4 LSB error This would obviously require very precise amplifiers The expression for the differ ential output voltage of the preamp is 2R2 Vo Vin Vin Y SIGNAL GAIN 2R2 Vos Vos Vos IxRx 1 Rr VLLL NL DC ERROR TERM GAIN 33 where is the current through resistor Ry of the offset error terms be cancelled by making Xl4Ry2 Vos Voss Voss This is the principle of this auto zeroing scheme The INS8080A uses the 3 I O ports of INS8255 Progra mable Peripheral Interface to control the auto zeroing and input data from the ADCO801 as shown in Figure 19 The PPI is programmed for basic operation mode 0 with Port A being an input port and Ports B and C being output ports Two bits of Port C are used to alternately open or close the 2 switches at the input of the preamp Switch SW1 is closed to force the preamp s differential input to be zero during the zeroing subroutine and then opened and SW2 is then closed for conversion of the actual differential input signal Using 2 switches in this manner eliminates concer
128. nativas y s ntesis de una soluci n Como ya se mencion anteriormente lo que se requiere es implementar un sistema de bajo costo es por ello que se ha tomado la decisi n de que el costo para el osciloscopio no exceda los 50 de fabricaci n y de que el costo para las puntas removible de corriente y voltaje no exceda el de los 5 de fabricaci n por pieza y de igual forma para el dispositivo maestro que no deber exceder los 10 de fabricaci n es por ello que se evalu la utilizaci n de los componentes necesarios esperando que estos respondan a las necesidades requeridas Tambi n es por esto que se desea utilizar la resina para embalaje del circuito ya que el gal n de esta no excede los 3000 colones y la resina para elaborar los moldes tiene un costo aproximado de 18000 colones y no requiere de maquinaria especializada lo cual es mucho m s econ mico 17 solamente la punta de osciloscopio que por su tama o ser necesario utilizar moldes de pl stico inyectado cuyo costo esta por encima de los 400000 colones 4 4 Implementaci n de la soluci n Para lograr definir bien el problema y realizar una proyecci n certera de la posible soluci n es siempre necesaria una investigaci n exhaustiva del problema a resolver Para la implementaci n de la soluci n primeramente se busc toda la informaci n te rica necesaria para poder implementar el circuito para esto se hizo la investigaci n necesaria en Internet debido a que fue la f
129. network in use Figure 16 Small Signal Response of AD820 as Unity Follower Driving 350 pF Capacitive Load RI NOISE GAIN 1 Figure 17 Capacitive Load Tolerance vs Noise Gain REV D Figure 18 shows a possible configuration for extending capaci tance load drive capability for a unity gain follower With these component values the circuit will drive 5 000 pF with a 10 overshoot _ Figure 18 Extending Unity Gain Follower Capacitive Load Capability Beyond 350 pF OFFSET VOLTAGE ADJUSTMENT The AD820 s offset voltage is low so external offset voltage null ing is not usually required Figure 19 shows the recommended technique for AD820 s packaged in plastic DIPs Adjusting offset voltage in this manner will change the offset voltage temperature drift by 4 uV C for every millivolt of induced offset null pins are not functional for AD820s in the SO 8 R package Vs V 5 Figure 19 Offset Null APPLICATIONS Single Supply Half Wave and Full Wave Rectifiers An AD820 configured as a unity gain follower and operated with a single supply can be used as a simple half wave rectifier The AD820 s inputs maintain picoamp level input currents even when driven well below the minus supply The rectifier puts that behav ior to good use maintaining an input impedance of over 10 for input voltages from 1 volt from the positive sup
130. ng the first power up cycle On the high to low transition of the WR input the internal SAR latches and the shift register stages are reset As long as the CS input and WR input remain low the A D will remain in a reset state Conversion will start from 1 to 8 clock periods after at least one of these inputs makes a low to high transition www national com A functional diagram of the A D converter is shown in Figure 4 of the package pinouts are shown and the major logic control paths are drawn in heavier weight lines The converter is started by having CS and WR simulta neously low This sets the start flip flop F F and the result ing 1 level resets the 8 bit shift register resets the Interrupt INTR F F and inputs a 1 to the D flop F F1 which is at the input end of the 8 bit shift register Internal clock signals then transfer this 1 to the Q output of F F1 The AND gate G1 combines this 1 output with a clock signal to provide a reset signal to the start F F If the set signal is no longer present either WR or CS is a 1 the start F F is reset and the 8 bit shift register then can have the 1 clocked in which starts the conversion process the set signal were to still be present this reset pulse would have no effect both outputs of the start F F would momentarily be at a 1 level and the 8 bit shift register would continue to be held in the reset mode This logic therefore allows for
131. nowledge Interrupt Enable 7 Wake up IRQ Interrupt Priority Encoder Figure 5 16 Interrupt Controller Logic Block Diagram The Program Counter value as well as the Carry and Zero flags CF ZF are automatically stored onto the Program Stack by the CALL instruction as part of the interrupt acknowledge process The user firmware is responsible for insuring that the processor state is preserved and restored during an interrupt For example the PUSH A instruction should be used as the first command in the ISR to save the accumulator value and the POP A instruction should be used just before the RET instruction to restore the accumulator value The program counter CF and ZF are restored when the RET instruction is executed The Interrupt Vectors supported by the USB Controller are listed in Table 5 3 Interrupt Vector 0 Reset has the highest priority Interrupt Vector 7 has the lowest priority Because the JMP instruction is 2 bytes long the interrupt vectors occupy 2 bytes CY7C63000 CY7C63001 __ CY7C63100 CY7C63101 Ex PRELIMINARY CY7C63200 CY7C63201 Table 5 3 Interrupt Vector Assignments 0x02 128 us timer interrupt 5 8 1 Interrupt Latency Interrupt latency can be calculated from the following equation Interrupt Latency Number of clock cycles remaining in the current instruction 10 clock cycles for the CALL instruction 5 clock cycles for the JMP instruction For example if a 5 clock cycle instruction such as JC is
132. ns Information continued PULSE POSITION MODULATOR This application uses the timer connected for astable opera tion as in Figure 10 with a modulating signal again applied to the control voltage terminal The pulse position varies with the modulating signal since the threshold voltage and hence the time delay is varied Figure 11 shows the waveforms generated for a triangle wave modulation signal DS007851 14 FIGURE 10 Pulse Position Modulator DS007851 15 Voc 5V Top Trace Modulation Input 1V Div TIME 0 1 ms DIV Bottom Trace Output 2V Div Ra 3 9kQ 0 01uF FIGURE 11 Pulse Position Modulator LINEAR RAMP When the pullup resistor RA in the monostable circuit is re placed by a constant current source a linear ramp is gener ated Figure 12 shows a circuit configuration that will perform this function TRIGGER 2N4250 OR EQUIV R2 OUTPUTO DS007851 16 FIGURE 12 Figure 13 shows waveforms generated by the linear ramp The time interval is given by _ 2 8 R4 Ra Vee 0 6 0 6V DS007851 17 5V Top Trace Input 3V Div TIME 20us DIV Middle Trace Output 5V Div 47kQ 100 2 7 0 01 uF Bottom Trace Capacitor Voltage 1V Div FIGURE 13 Linear Ramp www national com 9991 1171 LM555 Applications Infor
133. nse to SETUP and OUT transactions on End Point 0 5 9 2 2 End Point O Transmit The USB End Point 0 TX Register located at I O address 0x10 controls data transmission from End Point 0 see Figure 5 23 This is a read write register All bits are cleared during reset RW T E 1 0 m Invalid m 3 a 2 1 EL 0 Respond to IN packets Figure 5 23 USB End Point 0 TX Configuration Register Address 0x10 Bits 0 to 3 indicate the numbers of data bytes to be transmitted during IN packet valid values 0 to 8 inclusive Bit 4 indicates that a received DATA packet error CRC PID or bitstuffing error occurred during a SETUP or OUT data phase Setting the Stall bit bit 5 will stall IN and OUT packets This bit is cleared whenever a SETUP packet is received by End Point O Bit 6 Data 1 0 must be set to either 0 or 1 to select the DATA packet s toggle state 0 for DATAO 1 for CY7C63000 CY7C63001 CY7C63100 CY7C63101 gt PRELIMINARY CY7C63200 CY7C63201 After the transmit data has been loaded into the FIFO bit 6 should be set according to the data toggle state and bit 7 set to 1 This enables the USB Controller to respond to an IN packet Bit 7 is cleared and an End Point 0 interrupt is generated by the SIE once the host acknowledges the data transmission Bit 7 is also cleared when a SETUP token is received The Interrupt Service Routine can check bit 7 to confirm that the data transfer w
134. ntas tendr n un valor monetario que depender de la funci n para la que fueron disefiadas y el dispositivo al que se conectar n ser siempre el mismo a este dispositivo le llamaremos dispositivo maestro y a los dispositivos que se le pueden conectar le llamaremos punta removible Todo esto se puede observar en la figura 1 2 1 donde se muestra la primera propuesta para el dise o del embalaje De igual manera se requiri hacer el software necesario que permita al usuario utilizar el dispositivo con la computadora b Figura 1 2 1 Dispositivo maestro y de puntas removibles Esto es s lo el principio de lo que realmente se podr a implementar m s adelante se tiene pensado hacer puntas removibles para medir velocidad temperatura luminosidad y otra serie de variables f sicas que puedan ser de inter s no s lo para el campo de la electr nica Para la soluci n de este proyecto se decidi utilizar el microcontrolador de la CYPRESS el cy7c63001 que incorpora el puerto USB esto debido a que ya tenia la experiencia de haber trabajado con este microcontrolador en proyectos pasados adem s de ser muy econ mico existe suficiente informaci n que permiti el desarrollo del proyecto sin mayor problema Para el dispositivo de puntas removibles se implementar con ayuda una serie de resistencias y amplificadores operacionales con un arreglo que depender del uso para el que sea dise ada la punta removible adem s de la util
135. o a 0 V to 5 V5 square wave input The input and output are superimposed The output polarity tracks the input polarity up to Vg no phase reversal The reduced bandwidth above a 4 V input causes the rounding of the output wave form For input voltages greater than Vs a resistor in series with the AD820 s plus input will prevent phase reversal at the expense of greater input voltage noise This is illustrated in Figure 14b Since the input stage uses n channel JFETs input current during normal operation is negative the current flows out from the input terminals If the input voltage is driven more positive than Vs 0 4 V the input current will reverse direction as internal device junctions become forward biased This is illustrated in TPC 4 L HL LE HUI Figure 14 a Response with 0 from 0 to b Vin 0 to 1 Vs 200 mV Vour 0 to Vs Rp 49 9 12 current limiting resistor should be used in series with the input of the AD820 if there is a possibility of the input voltage exceeding the positive supply by more than 300 mV or if an input voltage will be applied to the AD820 when 0 The amplifier will be damaged if left in that condition for more than 10 seconds 1 resistor allows the amplifier to withstand up to 10 volts of continuous overvoltage and increases the input voltage noise by a negligible amount
136. o anteriormente se seleccion este microcontrolador debido a su econom a 3 3 la unidad y 1 65 en cantidades mayores a las 100 unidades el 0804 de la Nacional semiconductors ya antes utilizado en la escuela de electr nica y junto a sus 8 bit de resoluci n convirti a este integrado en el m s apropiado ya que tambi n se encuentra para montaje de superficie y tambi n a su bajo costo 2 5 la unidad y 1 45 en cantidades mayores a las 100 unidades el cable USB tiene un costo de 1 5 el conector mini B USB el puerto USB que traen las c maras digitales tiene un costo de 1 y resistencias capacitor cristal de 6 MHz y placa para montaje tiene un costo de 0 9 con lo que el costo total m ximo de los materiales del dispositivo maestro es de 9 2 CONNECTOR USB X1 amp MHz Resonator 6 1 gt ADCOBSDA Figura 5 1 1 1 Circuito para el dispositivo maestro 20 Tabla 5 1 1 1 Costo de los materiales del dispositivo maestro adquirir mas de 100 CY7C63001 33 1 65 O ___2000804___________55 O al CABLE USB MINI B USB CRISTAL 6MHz 06 RESISTENCIAS TOTAL EA lO AO En la figura 5 1 1 se muestra el circuito del dispositivo maestro en este se muestra que el convertidor anal gico digital est con figurado para que corra libremente esto es que esta haciendo conversiones sin necesidad de que el micro le
137. ode If the voltage source applied to the V or pin exceeds the allowed operating range of Vc 5450 mV large input currents can flow through a parasitic diode to the pin If these currents can exceed the 1 mA max allowed spec an external diode 1N914 should be added to bypass this current to the Vec pin with the current bypassed with this diode the voltage at the pin can exceed the Voc voltage by the forward voltage of this diode 2 3 2 Input Bypass Capacitors Bypass capacitors at the inputs will average these charges and cause a DC current to flow through the output resis tances of the analog signal sources This charge pumping action is worse for continuous conversions with the Vin input voltage at full scale For continuous conversions with a 640 kHz clock frequency with the Vin input at this DC current is at a maximum of approximately 5 pA Therefore bypass capacitors should not be used at the analog inputs or the V amp gp 2 pin for high resistance sources gt 1 If input bypass capacitors are necessary for noise filtering and high source resistance is desirable to minimize capacitor size the detrimental effects of the voltage drop across this input resistance which is due to the average value of the input current can be eliminated with a full scale adjustment while the given source resistor and input bypass capacitor are both in place This is possible because the average value of the
138. of 1 converter are allowed For larger clock line loading a CMOS or low power TTL buffer or PNP input logic should be used to minimize the loading on the clock pin do not use a standard TTL buffer 2 7 Restart During a Conversion If the A D is restarted CS and WR go low and return high during a conversion the converter is reset and a new con version is started The output data latch is not updated if the conversion in process is not allowed to be completed there fore the data of the previous conversion remains in this latch The INTR output simply remains at the 1 level 2 8 Continuous Conversions For operation in the free running mode an initializing pulse should be used following power up to ensure circuit opera tion In this application the CS input is grounded and the WR input is tied to the INTR output This WR and INTR node should be momentarily forced to logic low following a power up cycle to guarantee operation 2 9 Driving the Data Bus This MOS A D like MOS microprocessors and memories will require a bus driver when the total capacitance of the data bus gets large Other circuitry which is tied to the data bus will add to the total capacitive loading even in TRI STATE high impedance mode Backplane bussing also greatly adds to the stray capacitance of the data bus There are some alternatives available to the designer to handle this problem Basically the capacitive loading of the data bu
139. of 3 0 V s Excellent DC Performance 800 Max Input Offset Voltage 1 pV C Typ Offset Voltage Drift 25 pA Max Input Bias Current Low Noise 13 nV VHz 10 kHz APPLICATIONS Battery Powered Precision Instrumentation Photodiode Preamps Active Filters 12 to 14 Bit Data Acquisition Systems Medical Instrumentation Low Power References and Regulators PRODUCT DESCRIPTION The AD820 is a precision low power FET input op amp that can operate from a single supply of 5 0 V to 36 V or dual sup plies of 2 5 V to 18 V It has true single supply capability with an input voltage range extending below the negative rail 50 m ot We 25 LITT ap 10 __ ke 0 2 5 10 T CURRENT Figure 1 Typical Distribution of Input Bias Current NUMBER OF UNITS REV D Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use norfor any infringements of patents or other rights ofthird parties that may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices FUNCTIONAL BLOCK DIAGRAM 8 Vs IN BE 6 Vout 5 NULL NC NO CONNECT V TOP VIEW E Not to Scale allowing the AD820 to accommodate input signals below ground in the single supply
140. og input signal that does not go to ground this new zero reference should be properly adjusted first A voltage that equals this desired zero reference plus 12 LSB where the LSB is cal culated for the desired analog span 1 LSB analog span www national com 22 256 is applied to pin 6 and the zero reference voltage at pin 7 should then be adjusted to just obtain the to 01 ex code transition The full scale adjustment should then be made with the proper Vin voltage applied by forcing a voltage to the Vin input which is given by Yun Vin fs adj Vmax 1 5 256 where Vuax high end of the analog input range and Vuin the low end the offset zero of the analog range Both are ground referenced The 2 voltage is then adjusted to provide code change from to FFyex This completes the adjustment procedure 2 6 Clocking Option The clock for the A D can be derived from the CPU clock or an external RC can be added to provide self clocking The CLK IN pin 4 makes use of a Schmitt trigger as shown in Figure 8 Functional Description continued DS005671 17 1 1 RC 210 FIGURE 8 Self Clocking the A D Heavy capacitive or DC loading of the clock R pin should be avoided as this will disturb normal converter operation Loads less than 50 pF such as driving up to 7 A D converter clock inputs from a single clock R pin
141. on el dispositivo Dispositivo a Interconexi n uU Fisico Capa de FUHCI H Funcion Dispositivo de l gico USB Depositi os USB Capa de Interfaz del bus USE busUSB Flujo real de las comunicaciones Flujo l gico delas comunicaciones Figura 3 1 2 Capas del sistema de comunicaciones USB La capa de funci n proporciona capacidades adicionales de host v a una adecuada capa de programa cliente Las capas de funci n y dispositivos USB tienen cada una de ellas una visi n de la comunicaci n l gica dentro de su nivel aunque la comunicaci n entre ellas se hace realmente por la capa de interfaz de bus USB 3 2 Descripci n del sistema Como se puede observar en la figura 3 2 1 se muestra el diagrama de bloques del dispositivo de punta removible que es por donde se introduce la se al anal gica para ser tratada antes de que esta entre al convertidor anal gico digital 11 ENTRADA ANALOGICA AMPLIFICADOR CONECTOR OPERACIONAL MACHO FIGURA 3 2 1 Dispositivo de punta removible En la figura 3 2 2 se muestra el diagrama de bloques del dispositivo maestro el cual toma la senal analogica proveniente del dispositivo de punta removible donde se introduce en el convertidor analogico digital para luego hacer pasar los datos binarios al microcontrolador que los tomara y los sacara por el puerto USB que este incorpora para que luego entren en la computadora donde
142. onnected to port USB of such form of that if the user wishes to use the oscilloscope he similarly connects to the apparatus an extension to him that allows him to use it like oscilloscope if wishes to use the apparatus as voltmeter will only have to connect the extension that allows him to use it like voltmeter and similarly to measure current In order to be able to make this project it was decided fundamentally to use a digital analogical converter and one of the microcontrollers of the CYPRESS that incorporates port USB as well as amplifying of instrumentation and integrated that provides negative tensions INDICE GENERAL MR Um O E 1 udo id 2 ro hal eo ERNEUT 4 1 1 Problema existente e implementaci n de su soluci n 4 1 2 Soluci n 4 Capitulo 2 Meta y 00 7 7 2 2 DON Cramer tetera 7 2 9 Objetivos espec ficos AES ETE 7 CARING M gt 9 3 1 Marco obe vere TU EU GA 9 3 2 Descripci n del sistema o proceso a 11 3 Descripci n de los principales principios f sicos y o electr nicos relacionados con la soluci n del pro
143. otal Unadjusted Error Note 8 Vaep 2 2 500 Vos LSB ADC0803 Total Adjusted Error Note 8 With Full Scale LSB PASA ADC0804 Total Unadjusted Error Note 8 Vaep 2 2 500 Voo LSB 805 Total Unadjusted Error Note8 2 Connection LSB Vner 2 Input Resistance Pin 9 ADC0801 02 03 05 2 5 8 0 Analog Input Voltage Range Note 4 Vis Or VI 6 9 045 Voot0 05 DC Common Mode Error Over Analog Input Voltage 11 16 11 LSB EUN Power Supply Sensitivity 5 10 Over 51 16 11 LSB Allowed and Vin Voltage Range Note 4 AC Electrical Characteristics The following specifications apply for 5 and Tmn lt Ta lt Tmax unless otherwise specified Symbol Parameter Conditions Mi Mex Unis To fou 640 KHz Note 6 108 ma us Clock Frequency 5 Note 5 100 640 1460 kHz wx CR Conversion Rate in Free Running INTR tied to WR with 8770 9708 conv s Mode CS 0 640 kHz mp ome tacc Access Time Delay from Falling C 2100 pF 135 200 ns Edge of RD to Output Data Valid tin ton TRI STATE Control Delay C 210 pF 210k 125 200 ns from Rising Edge of RD to See TRI STATE Test Hi Z State Circuits tw Ini Delay from Falling Edge 300 450 ns Cin Input Capacitance of Logic 5 75 pF AA www national com 508090VW 08090VW 208090V 208090V 108090V ADC0801 ADC0802 AD
144. ply to 20 volts below the negative supply full and half wave rectifier shown in Figure 20 operates as follows when is above ground is bootstrapped through the unity gain follower Al and the loop of amplifier A2 This forces the inputs of 2 to be equal thus no current flows through or R2 and the circuit output tracks the input When Vy is below ground the output of 1 is forced to ground The noninverting input of amplifier A2 sees the ground level output of A1 therefore A2 oper ates as a unity gain inverter The output at node C is then a full wave rectified version of the input Node B 15 a buffered half wave rectified version of the input Input voltages up to 18 volts can be rectified depending on the voltage supply used _13 10820 FULL WAVE RECTIFIED OUTPUT HALF WAVE RECTIFIED OUTPUT Low Power Three Pole Sallen Key Low Pass Filter The AD820 s high input impedance makes it a good selection for active filters High value resistors can be used to construct low frequency filters with capacitors much less than 1 uF The AD820 s picoamp level input currents contribute minimal dc errors Figure 22 shows an example a 10 Hz three pole Sallen Key Filter The high value used for minimizes interaction with signal source resistance Pole placement in this version of the filter minimizes the Q associated with the two pole section of the filter This eliminates any peaking of the nois
145. preferencia de superficie y tambi n hubo que utilizar un voltaje negativo para que la no se recorte en su parte negativa a la hora de pasar por los amplificadores operacionales Para encontrar los componentes que cumplieran las caracter sticas anteriores se utilizaron los manuales de la Texas Instrument Jamenco Digi Key y los de la Nacional Semiconductors Con respecto al microcontrolador a utilizar este tambi n es de montaje de superficie y al igual que el resto del circuito se alimenta con la energ a del puerto USB y contener un puerto USB para obtener un microcontrolador que se ajustara a estas necesidades se procedi a hacer una b squeda en Internet de integrados que pudieran ajustarse a las necesidades del proyecto as que se indag en empresas como Motorota Texas Instruments y Microchip pero la decisi n final se tomo a favor del cy7c63001 la empresa Cypres debido su econom a y a la cantidad de informaci n referente a la programaci n del microcontrolador Con respecto al software implementado para poder ver en la pantalla de la computadora la informaci n proveniente del sistema se utiliz el leguaje de programaci n Delphi 7 del cual existe mucha informaci n en la biblioteca del Instituto Tecnol gico as como en la U C R y en Internet a dem s de que el programa facilita su manejo debido a su semejanza con el lenguaje de programaci n Pascal como se menciono anterior mente 4 3 Evaluaci n de las alter
146. r otro lado muchos IDE como las memorias Flash tienen mayores facilidades para dise ar que Delphi pero no dan libertad para comunicarse con el sistema y la ejecuci n de estas aplicaciones no es para nada eficiente Esas son las razones por las cuales se decidi utilizar Delphi Object Pascal Junto al entorno Delphi se utiliz un paquete de componentes con c digo abierto llamado HIDKomponente que es una envoltura para las funciones de la biblioteca HID DLL de Windows lo que facilita el trabajo para la comunicaci n con el puerto USB siguiendo del est ndar HID Dispositivo de Interfaz Humana es b sicamente un est ndar que define un protocolo dise ado para comunicar el sistema operativo con dispositivos de control conectados por USB como ratones teclados y palancas de juego pero que tambi n permite muchas otras funciones Las ventajas de crear un dispositivo compatible con HID es que se usa el protocolo m s sencillo y la implementaci n generalmente es ofrecida tanto por el fabricante del microcontrolador como por el fabricante del sistema operativo Esto redujo much simo los recursos utilizados en la investigaci n y el desarrollo y minimiz los errores pues se est trabajando con un est ndar e implementaciones probadas ampliamente durante a os Windows reconoce monta y desmonta dispositivos HID autom ticamente sin requerir ninguna acci n del usuario y sin la necesidad de instalar software adicional As
147. rameter DC PERFORMANCE Initial Offset Max Offset over Temperature Offset Drift Input Bias Current at Tuax Input Offset Current at Tuax Open Loop Gain Tmn to Tmax Tmn to Tmax Tmn to Tmax NOISE HARMONIC PERFORMANCE Input Voltage Noise 0 1 Hz to 10 Hz f 10 Hz f 100 Hz f 1 kHz f 10 kHz Input Current Noise 0 1 Hz to 10 Hz f 1 kHz Harmonic Distortion f 10 kHz DYNAMIC PERFORMANCE Unity Gain Frequency Full Power Response Slew Rate Settling Time to 0 1 to 0 0196 INPUT CHARACTERISTICS Common Mode Voltage Range Tmn to Tmax CMRR Tmn to Tmax Input Impedance Differential Common Mode OUTPUT CHARACTERISTICS Output Saturation Voltage Vor VEE Tmn to Tmax Tmn to Tmax Vor Vxzg Tmn to Tmax Tmn to Tax Vor Vxzg Tmn to Tax Tmn to Tax Operating Output Current Tun to Tax Short Circuit Current Capacitive Load Drive POWER SUPPLY Quiescent Current Power Supply Rejection Tmn to Tmax REV D AD820 Max Unit AD820A AD820B Min Typ 5 4 Vo 24Vto 4V 100 10 1k0Q p p_ nV NHz nV VHz nV VHz nV VHz fA VHz dB MHz Vo 9 kHz Vo 20V to t4 5 V Vem 5 V to 2 10P0 5 10 2 8 100 5 10 2 8 Ismx 20 uA Isource 20 Ismx 2 mA Isource 2 mA 15 mA Isource 15 mA Tmn to Tmax 5 V to 15 V AD820 SPEC
148. rent Capacitive Load Drive POWER SUPPLY Quiescent Current Turn to Power Supply Rejection Vst 5Vto 15 V Tmn to Tmax 4 REV D 10820 NOTES l This is a functional specification Amplifier bandwidth decreases when the input common mode voltage is driven in the range Vg 1 V to Vs Common mode error voltage is typically less than 5 mV with the common mode voltage set at 1 volt below the positive supply is defined as the difference between the lowest possible output voltage V or and the minus voltage supply rail V gg is defined as the difference between the highest possible output voltage and the positive supply voltage Specifications subject to change without notice ABSOLUTE MAXIMUM RATINGS NOTES Supply Voltage io 18 V IStresses above those listed under Absolute Maximum Ratings may cause perma Internal Power Dissip ation nent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational Plastic DIP 1 6 W section of this specification 15 not implied Exposure to absolute maximum rating SOIC CR Em 1 0 W conditions for extended periods may affect device reliability Input Voltage Vs 0 2 V to 20 V Vs 8 Lead Plastic DIP Package 90 C W Output Short Circuit Duration
149. rent at IMAX Input Offset Current at IMAX Open Loop Gain Tmn to Tmax Tmn to Tmax Tmn to NOISE HARMONIC PERFORMANCE Input Voltage Noise 0 1 Hz to 10 Hz f 10 Hz f 100 Hz f 1 kHz f 10 kHz Input Current Noise 0 1 Hz to 10 Hz f 1 kHz Harmonic Distortion f 10 kHz DYNAMIC PERFORMANCE Unity Gain Frequency Full Power Response Slew Rate Settling Time to 0 1 to 0 01 INPUT CHARACTERISTICS Common Mode Voltage Range Tmn to Tmax CMRR Tmn to Tmax Input Impedance Differential Common Mode OUTPUT CHARACTERISTICS Output Saturation Voltage Vor Vzg Tmn to Tmax Tmn to Tmax Vor Vzg Tmn to Tmax Tmn to Tmax Tmn to Tmax Tmn to Tmax Operating Output Current Tmn to Tmax Short Circuit Current Capacitive Load Drive POWER SUPPLY Quiescent Current Power Supply Rejection Tmn to Tmax Vo 0Vto4V Vo 0 2 V to 4 V 100 10 1 10 to 2 5 V Vo 0 25 V to 4 75 V 4 5 Vo 0 2 4 5 V Vem 2 0Vto2V Ismx 20 20 lt 2 mA Isource 2 mA 15 Isource 15 mA Tmn to Tmax Vs 5 V to 15 V AD820A AD820B Min Typ Max Unit 0 2 0 2 72 80 66 1013 0 5 10 32 8 10 3 0 5 10 2 8 REV D SPEC 0 Vs 0 5 V OT 25 Ven 0 V 0 2 V unless otherwise noted Pa
150. reserved and must be written as zeros during a write During a read reserved bit positions should be ignored Bits 4 5 and 6 are used to record the occurrence of POR USB and WDR Reset respectively The firmware can interrogate these bits to determine the cause of a reset Bit 0 is the Run control clearing this bit will stop the microcontroller Once this bit is set to low only a reset can set this bit HIGH The microcontroller resumes execution from ROM address 0 00 after a reset unless the Suspend bit bit 3 of the Status and Control Register is set Setting the Suspend bit stops the clock oscillator and the interrupt timers as well as powering down the microcontroller The detection of any USB activity will terminate the suspend condition a A E Reserved Watch Dog USB Reset Power on Suspend Reserved Reserved Run Reset Reset Figure 5 3 Status and Control Register Address OxFF 5 3 1 Power On Reset POR Power On Reset POR occurs every time the power to the device is switched on Bit 4 of the Status and Control Register is set to record this event the register contents are set to 00011001 by the POR The USB Controller is placed in suspended mode at the end of POR to conserve power most device functions such as the clock oscillator the timers and the interrupt logic are turned off in the suspend mode Only a non idle USB Bus state will terminate the suspend mode and begin normal operations CY7
151. resistance of 106 C W DIP 170 C W 50 8 and 204 C W MSOP junction to ambient Note 4 Supply current when output high typically 1 mA less at 5V Note 5 Tested at Voc 5V and Vcc 15V Note 6 This will determine the maximum value of Ra for 15V operation The maximum total Rp is 20 0 Note 7 No protection against excessive pin 7 current is necessary providing the package dissipation rating will not be exceeded Note 8 Refer to RETS555X drawing of military LM555H and LM555J versions for specifications www national com Typical Performance Characteristics Minimuim Pulse Width Required for Triggering MINIMUM PULSE WIDTH us LOWEST VOLTAGE LEVEL OF TRIGGER PULSE X Vcc DS007851 4 High Output Voltage vs Output Source Current Vcc V 125 r Ld ISource mA DS007851 20 Low Output Voltage vs Output Sink Current Vour V p ANY Isink mA DS007851 22 Supply Current vs Supply Voltage SUPPLY CURRENT mA SUPPLY VOLTAGE V DS007851 19 Low Output Voltage vs Output Sink Current Vour V 01 ss cc 2 2724 22 So ZZ Patt 1 0 100 Isinx mA DS007851 21 Low Output Voltage vs Output Sink Current Vour V as
152. rga de otorgarle los recursos necesarios del sistema al dispositivo para su adecuado funcionamiento La computadora tambi n contiene el concentrador ra z el cual es quien se encarga de permitir que los datos y la energ a pasen a uno o dos conectores USB del PC y de all a los 127 perif ricos que puede soportar el PC Con respecto a los perif ricos tenemos dos clases los de baja velocidad y los de alta velocidad en los de baja velocidad se encuentran teclados ratones joysticks y otros dispositivos para juegos los cuales pueden trabajar a 1 5 Mbps con respecto a los dispositivos de alta velocidad tenemos Monitores impresoras scanner m dems y equipos de audio que necesitan velocidades m s altas por la cantidad de volumen de informaci n que requieren manejar estos dispositivos requieren de los 12Mbps En la figura 3 1 2 se muestra un diagrama de capas en el cual se puede observar como fluye la informaci n entre las diferentes capas a nivel real y a nivel l gico 10 El programa se ejecuta en el host corresponde a un dispositivo USB este se encuentra ya incorporado en el sistema operativo o los trae el dispositivo hay que recordar que la conexi n entre un host y un dispositivo requiere la interacci n entre las capas La capa de intertaz de bus USB proporciona la conexi n f sica entre el host y el dispositivo La capa de dispositivo USB es la que permite que el software del sistema USB realice operaciones gen ricas USB c
153. s a DAC and provides the error as an analog output voltage is shown in Figure 8 The 2 op amps can be eliminated if a lab DVM with a numerical subtraction feature is available to read the difference volt age directly The analog input voltage can be sup plied by a low frequency ramp generator and an X Y plotter can be used to provide analog error Y axis versus analog input X axis For operation with a microprocessor or a computer based test system it is more convenient to present the errors digitally This can be done with the circuit of Figure 11 where the output code transitions can be detected as the 10 bit DAC is incremented This provides LSB steps for the 8 bit A D under test If the results of this test are automatically plotted with the analog input on the X axis and the error in LSB s as the Y axis a useful transfer function of the A D under test results For acceptance testing the plot is not necessary and the testing speed can be increased by estab lishing internal limits on the allowed error for each code 4 0 MICROPROCESSOR INTERFACING To dicuss the interface with 8080A and 6800 microproces sors a common sample subroutine structure is used The microprocessor starts the A D reads and stores the results of 16 successive conversions then returns to the user s program The 16 data bytes are stored in 16 successive memory locations All Data and Addresses will be given in hexadecimal form Software and
154. s edge triggered with programmable polarity 2 pins Open drain with 2 pins Bidirectional USB data lines An external 7 5 resistor must be connected between the D pin and to select low speed USB operation 1 pin Open drain output with Schmitt trigger input The input is connected to a level sensitive HIGH interrupt CEXT may be connected to an external RC to generate a wake up from Suspend mode See Section 5 6 5 0 Functional Description The Cypress CY7C63000 1 CY7C63100 1 and CY7C63200 1 USB microcontrollers are optimized for human interface comput er peripherals such as a mouse joystick and gamepad Cypress USB microcontrollers conform to the low speed 1 5 Mbps requirements of the USB Specification version 1 0 Each micorcontroller is a self contained unit with a USB interface engine USB transceivers an 8 bit RISC microcontroller a clock oscillator timers and program memories It supports one USB device address and two end points The 6 MHz clock generated by the on chip oscillator is stepped up to 12 MHz to drive the microcontroller A RISC architecture with 35 instructions is chosen to provide the best balance between performance and product cost 5 1 Memory Organization The memory in the USB Controller is organized into user program memory in EPROM space and data memory in SRAM space 5 1 1 Program Memory Organization The 14 bit Program Counter PC is capable of addressing 16K bytes of program space
155. s in the case of the 8080A interface and it can be called from anywhere in the user s program In Figure 16 the ADCO801 series is interfaced to the M6800 microprocessor through the arbitrarily chosen Port B of the MC6820 or MC6821 Peripheral Interface Adapter PIA Here the CS pin of the A D is grounded since the PIA is ANALOG INPUTS Note 20 Numbers in parentheses refer to MC6800 CPU pin out already memory mapped in the M6800 system and no CS decoding is necessary Also notice that the A D output data lines are connected to the microprocessor bus under pro gram control through the PIA and therefore the A D RD pin can be grounded A sample interface program equivalent to the previous one is shown below Figure 16 The PIA Data and Control Registers of Port B are located at HEX addresses 8006 and 8007 respectively 5 0 GENERAL APPLICATIONS The following applications show some interesting uses for the A D The fact that one particular microprocessor is used is not meant to be restrictive Each of these application circuits would have its counterpart using any microprocessor that is desired 5 1 Multiple ADCO801 Series to MC6800 CPU Interface To transfer analog data from several channels to a single microprocessor system a multiple converter scheme pre sents several advantages over the conventional multiplexer single converter approach With the ADCO801 series the differential inputs allow individual span adjustmen
156. s located at I O address 0x01 The contents of both registers are set HIGH during a reset Refer to Figures 5 7 and 5 8 for the formats of the data registers In addition to supporting general input output functions each I O line can trigger an interrupt to the microcontroller Please refer to the interrupt section for more details Figure 5 8 Port 1 Data Register Address 0x01 Each GPIO line includes an internal 16 resistor This resistor provides both the pull up function and slew control Two factors govern the enabling and disabling of each resistor the state of its associated Port Pull up register bit and the state of the Data Register bit The control bits in the Port Pull up register are active LOW The output is HIGH when a 1 is written to the Data Register and the Port Pull up register is 0 Writing a 0 to the Data Register will disable the Pull up resistor and output a LOW regardless of the setting in the Port Pull up Register The output will go to a high Z state if the Data Register bit and the Port Pull up Register bit are both 1 Figure 5 9 illustrates the block diagram of one I O line The Port Isink Register is used to control the output current level and it is described later in this section Table 5 2 is the Output Control truth table CY7C63000 CY7C63001 CY7C63100 CY7C63101 v NN PRELIMINARY CY7C63200 CY7C63201 Vcc gt lt 16 Schmitt Port Data Trigger Register NA GPIO PA ET Pin Data Bus
157. s slows down the response time even though DC specifications are still met For systems operating with a relatively slow CPU clock frequency more time is available in which to establish proper logic levels on the bus and therefore higher capacitive loads can be driven see typical characteristics curves At higher CPU clock frequencies time can be extended for reads and or writes by inserting wait states 8080 or using clock extending circuits 6800 Finally if time is short and capacitive loading is high external bus drivers must be used These be TRI STATE buffers 23 low power Schottky such as the DM74LS240 series is rec ommended or special higher drive current products which are designed as bus drivers High current bipolar bus drivers with PNP inputs are recommended 2 10 Power Supplies Noise spikes on the supply line can cause conversion errors as the comparator will respond to this noise A low inductance tantalum filter capacitor should be used close to the converter Vcc pin and values of 1 uF or greater are recommended If an unregulated voltage is available in the system a separate LM340LAZ 5 0 TO 92 5V voltage regu lator for the converter and other analog circuitry will greatly reduce digital noise on the Vec supply 2 11 Wiring and Hook Up Precautions Standard digital wire wrap sockets are not satisfactory for breadboarding this A D converter Sockets on PC boards can be used and all log
158. source resistance and the use of an input bypass capacitor This error can be eliminated by doing a full scale adjustment of the A D adjust 2 for a proper full scale reading see section 2 5 2 on Full Scale Adjustment with the source re sistance and input bypass capacitor in place 2 4 Reference Voltage 2 4 1 Span Adjust For maximum applications flexibility these A Ds have been designed to accommodate 5 2 5 or an adjusted voltage reference This has been achieved in the design of the IC as shown in Figure 6 VREF U DIGITAL CIRCUITS ANALOG CIRCUITS DS005671 15 FIGURE 6 The Vrererence Design on the 21 Notice that the reference voltage for the IC is either gt of the voltage applied to the Vec supply or is equal to the voltage that is externally forced at the 2 pin This allows for a ratiometric voltage reference using the supply a 5 Voc reference voltage can be used for the supply or a voltage less than 2 5 can be applied to the 2 input for increased application flexibility The internal gain to the 2 input is 2 making the full scale differential input voltage twice the voltage at pin 9 An example of the use of an adjusted reference voltage is to accommodate a reduced span dynamic voltage range of the analog input voltage If the analog input voltage were to range from 0 5 to 3 5 Vpc instead of OV
159. spositivo que se conecte al puerto USB de una PC que se encargue de tomar datos anal gico y convertirlos en datos digitales para que luego sean transferido a la PC por el puerto USB Desarrollar los componentes puntas removibles que se conecten al dispositivo que va conectado a la computadora por el puerto USB dispositivo maestro Que los dispositivos sean de bajo consumo de energ a de tal forma que estos puedan se alimentados con el tensi n que proporciona el puerto USB Implementar dispositivos que sean utilizados para medir en forma independiente corriente tensi n y permita implementar un osciloscopio sin el puerto de la PC b Objetivos de programa Desarrollar un programa de interfaz gr fica en la computadora que permita obtener e interpretar los datos anal gicos que son introducidos por los dispositivos electr nicos de tal forma que se puedan observar mediciones de corriente y tensi n en la misma pantalla Desarrollar un programa de interfaz gr fica en la computadora que permita obtener e interpretar los datos anal gicos que son introducidos por los dispositivos electr nicos de tal forma que se pueda implementar un osciloscopio en la computadora e Objetivos de documentaci n e Desarrollar un manual de usuario por dispositivo desarrollado que facilite el uso del Programa y el circuito al usuario d Objetivos de implementaci n e Construir todos los circuitos como circuitos de soldadura de
160. ssign interrupt priority to different port pins and the Port Interrupt Enable Registers are not cleared during the interrupt acknowledge process When a GPIO interrupt is serviced the ISR must poll the ports to determine which pin caused the interrupt 5 8 3 USB Interrupt A USB End Point 0 interrupt is generated after the host has written data to End Point 0 or after the USB Controller has transmitted a packet from End Point 0 and receives an ACK from the host An OUT packet from the host which is NAKd by the USB Controller will not generate an interrupt This interrupt is masked by the USB EPO Interrupt Enable bit bit 3 of the Global Interrupt Enable Register A USB End Point 1 interrupt is generated after the USB Controller has transmitted a packet from End Point 1 and has received an ACK from the host This interrupt is masked by the USB EP1 Interrupt Enable bit bit 4 of the Global Interrupt Enable Register 5 8 4 Timer Interrupt There are two timer interrupts the 128 us interrupt and the 1 024 ms interrupt They are masked by bits 1 and 2 of the Global Interrupt Enable Register respectively The user should disable both timer interrupts before going into the suspend mode to avoid possible conflicts between servicing the interrupts first or the suspend request first 5 8 5 Wake up Interrupt A wake up interrupt is generated when the Cext pin is HIGH It is level sensitive and is not latched to the interrupt controller It can be masked by
161. system or to affect its accordance with instructions for use provided in the safety or effectiveness labeling can be reasonably expected to result in a significant injury to the user National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Asia Pacific Customer Japan Ltd Americas Fax 49 0 180 530 85 86 Response Group Tel 81 3 5639 7560 Email support nsc com Email europe support nsc com Tel 65 2544466 Fax 81 3 5639 7507 Deutsch Tel 49 0 69 9508 6208 Fax 65 2504466 English Tel 44 0 870 24 0 2171 Email ap support nsc com www national com Francais Tel 33 0 1 41 91 8790 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications National Semiconductor LM555 Timer General Description The LM555 is a highly stable device for generating accurate time delays or oscillation Additional terminals are provided for triggering or resetting if desired In the time delay mode of operation the time is precisely controlled by one external re sistor and capacitor For astable operation as an oscillator the free running frequency and duty cycle are accurately controlled with two external resistors and one capacitor The circuit may be triggered and reset on falling waveforms and the output circuit can source or sin
162. t tention to minimize stray capacitance is necessary to achieve specified performance High source resistance will interact with the input capacitance to reduce speed and overall bandwidth Also to maintain stability avoid capacitance from the output to the input or the offset adjust pins Applications with balanced source impedance will provide the best performance In some applications mismatched source impedances may be required If the impedance in the negative input exceeds that in the positive input stray capacitance from the output will create a net negative feed back and improve the stability of the circuit If however the impedance in the positive input is greater then the feedback due to stray capacitance will be positive and instability may result The degree of positive feedback will of course depend on the source impedance imbalance as well as the board layout and the operating gain The addition of a small bypass capacitor of about 5 to 5OpF directly across the input terminals of the PGIA will generally eliminate any instabil ity arising from these stray capacitances CMR errors due to the source imbalance will also be reduced by the addition of this capacitor The PGA202 and the PGA203 are designed for fast settling in response to changes in either the input voltage or the gain The bandwidth and the settling times are mostly determined by the output stage and are therefore independent of gain except at the highest gai
163. t for each channel Furthermore all analog input channels are sensed simultaneously which essentially divides the microproces sor s total system servicing time by the number of channels since all conversions occur simultaneously This scheme is shown in Figure 17 4 D R W 34 6 O 5V 8 pe 00 33 31 01 32 29 02 31 K 03 30 H 04 29 32 05 28 30 06 27 L 07 26 4 A12 22 34 O A13 23 N A14 24 M A15 25 33 1 2 0 8092 4 lt 5 VMA 5 F GND mi WXY 4142 43 DS005671 24 Note 21 Number or letters in brackets refer to standard M6800 system common bus code FIGURE 15 ADC0801 MC6800 CPU Interface www national com 508090VW 08090V 2808090V 208090V 108090V Functional Description continuea SAMPLE PROGRAM FOR Figure 15 ADC0801 MC6800 CPU INTERFACE ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 0010 DF 36 DATAIN STX TEMP2 Save contents of X 0012 CE 00 2C LDX 002 Upon IRQ 1ow CPU 0015 FF FF F8 STX FFF8 jumps to 002C 0018 B7 50 00 STAA 5000 Start ADCO801 0018 OE CLI 001C CONVRT WAI Wait for interrupt 001D DE 54 LDX 001F 8C 02 OF CPX 020 15 final data stored 0022 27 14 BEQ ENDP 0024 B7 50 00 STAA 5000 Restarts ADCO801 0027 08 INX 0028 DF 34 STX TEMP1 002A 20 FO BRA CONVRT 002C DE 34 INTRPT LDX 002 6 5000 LDAA 5000 Read data 0031 7 00 5 StoreitatX
164. taba 33 2 7 7 34 2 TS 35 INDICE DE FIGURAS Figura 1 2 1 Dispositivo maestro y de puntas removibles 3 Figura 3 1 1 Estructura de capas del bus USB 10 Figura 3 2 2 Capas del sistema de comunicaciones USB 11 Figura 3 2 1 Dispositivo de punta 12 Figura 3 2 2 Dispositivo 0 0 02 0 02 22 2 12 Figura 3 2 3 Ventana del 14 Figura 5 1 1 1 Circuito para el dispositivo maestro 20 Figura 5 1 1 2 Dise o de embalaje para el dispositivo maestro 22 Figura 5 1 2 1 Circuito para el dispositivo la punta removible de volt metro 22 Figura 5 1 2 2 Embalaje para la punta removible de volt metro 23 Figura 5 1 3 1 Circuito para el dispositivo la punta removible de AMP CHIME lO eo TE pa 24 Figura 5 1 4 1 Circuito para el dispositivo la punta removible GE OScllOSCODIO cs cii Pre aso ere E 25 Figura 5 1 4 2 Embalaje para la punta removible de OSCIOSCOD O Maret 26 Figura 5 1 5 1 Imagen de la ven
165. tamente igual que el hecho para la punta removible de volt metro que se observa en la figura 5 1 2 2 Tabla 5 1 3 3 Costo de los materiales de la punta removible de amperimetro Componentes AD820 Resistencias y Placa para montaje TOTAL 5 1 4 An lisis para el circuito del dispositivo punta removible de osciloscopio En la figura 5 1 4 1 se puede observar el circuito para la punta removible de osciloscopio el principal componente para este dispositivo fue el amplificador instrumental PGA202 de la Texas Istruments cuyo valor se encuentra por unidad en los 12 91 y mas de 100 unidades en 10 3 el problema con este dispositivo es que debe de trabajar con un voltaje negativo y el puerto USB no proporciona mas que un voltaje de 5 voltios positivos con lo que se tubo que agregar a la circuiter a el integrado de MAXIN el MAX1673 que tiene la capacidad de invertir el voltaje de entrada pero a este integrado se le necesita conectar una se al de reloj que sea superior en frecuencia a 1 KHz es por eso que se introduce al circuito el famoso integrado LM555 1 0 92 y mas de 100 unidades 0 4794 el cual en configuraci n astable puede proporcionar los pulsos y la frecuencia necesaria para el MAX1673 1 5 33 y mas de 100 2 36 con todo esto ya el PGA202 esta funcionando bien pero hay que eliminar los valores negativos de la se al de salida del PGA202 ya que hay que introducirlos en la entrada anal gica del dispositivo maestro ya que este
166. tana principal del programa 2f Figura 5 1 5 2 Ventana del bot n de 28 Figura 5 1 5 3 Ventana para el osciloscopio 20 Figura 5 1 5 4 Ventana para el volt metro 29 Figura 5 1 5 5 Ventana para el 29 Figura 6 1 Imagen que muestra la medici n de diferencia de potencial bajo iguales condiciones entre el programa O usa 30 Figura 6 2 Imagen que muestra la medici n de corriente bajo iguales condiciones entre el programa VUN MUME astas 31 Figura 6 3 Imagen que muestra una medici n hecha con el osciloscopio del laboratorio de 31 Figura 6 4 Imagen que muestra una medici n hecha con el osciloscopio del laboratorio de 32 NDICE DE TABLAS Tabla 5 1 1 1 Costo de los materiales del dispositivo maestro 21 Tabla 5 1 2 2 Costo los materiales de la punta removible de volt metro 23 Tabla 5 1 3 3 Costo de los materiales de la punta removible de amperimetro 24 Tabla 5 1 4 4 Costo de los materiales de la punta removible de osciloscopio 25 Tabla 6 Caracter sticas el ctricas de la punta de osciloscopio con y el d
167. teresis Voltage All ports and Cext 8 Output LOW Voltage Cext pin Vcc Min lo 2mA Output LOW Voltage Cext pin Vcc Min lo 8 0 Switching Characteristics Parameter _____ Wn wx Transition Fall Time 8 Notes 4 4 35V to 5 25 V 5 Measured as largest step size vs nominal according to measured full scale and zero programmed values 6 POR can occur only once per applied Vcc if Vcc drops below Vrst POR will not re occur must return to 0 0V before POR will be re applied a subsequent Voc ramp Low to High transition This parameter is guaranteed but not tested lsinkt nylsinko n for the same n range sink F lsink O for port 0 or 1 output CT OX 23 CY7C63000 CY7C63001 CY7C63100 CY7C63101 ES _ PRELIMINARY CY7C63200 CY7C63201 CLOCK Figure 8 2 USB Data Signal Timing 9 0 Ordering Information EPROM Number Operating 28 42 BOP OGM PDIP Commercial 7 6500986 46 12 20 Pin 00 Mi SOIT Commercial _ CY7C63001 PC B 2 o 20 Pin 300 Mil PDIP CY7C63001 SC B 12 20 Pin 300 Mil SOIC CY7C63001 WC B 2 20 Pin 300 Mil Windowed CerDIP Se _ NL ___ MS E 12 12 12 12 12 CY7C63100 SC B 16 24 Pin 300 Mil SOIC B 16 16 10 10 0 gt lt gt a CY7C63101 SC 24 Pin 300 Mil SOIC CY7C63101 WC 24 Pin 300 Mil
168. ters described in the sections below 5 9 1 USB Enumeration Process The USB Controller provides a USB Device Address Register at I O location 0x12 Reading and writing this register is achieved via the IORD and IOWR instructions The register contents are cleared during a reset setting the USB address of the USB Controller to 0 Figure 5 20 shows the format of the USB Address Register ADR6 ADR5 4 ADR2 ADR1 ADRO Figure 5 20 USB Device Address Register Address 0x12 Typical enumeration steps 1 The host computer sends a SETUP packet followed by a DATA packet to USB address O requesting the Device descriptor 2 The USB Controller decodes the request and retrieves its Device descriptor from the program memory space 3 The host computer performs a control read sequence and the USB Controller responds by sending the Device descriptor over the USB bus 4 After receiving the descriptor the host computer sends a SETUP packet followed by a DATA packet to address 0 assigning a new USB address to the device The USB Controller stores the new address in its USB Device Address Register after the no data control sequence completes The host sends a request for the Device descriptor using the new USB address The USB Controller decodes the request and retrieves the Device descriptor from the program memory The host performs a control read sequence and the USB Controller responds by sending its Device descriptor over the
169. the charge rate of the R C timing circuit The format of the Cext register is shown in Figure 5 13 Reading the register returns the value of the Cext pin During a reset the Cext is HIGH Figure 5 13 The Cext Register Address 0x22 5 7 XTALIN XTALOUT XTALIN and XTALOUT are the crystal oscillator pins A 6 MHz crystal or ceramic resonator should be connected to these pins The feedback capacitors and bias resistor are internal to the IC V XTALOUT fxtal XTALIN Y Y Figure 5 14 Clock Oscillator On chip Circuit CY7C63000 CY7C63001 pu CY7C63100 CY7C63101 o _ PRELIMINARY CY7C63200 CY7C63201 5 8 Interrupts Interrupts are generated by the General Purpose lines the Cext pin the internal timer and the USB engine All interrupts except Reset are maskable by the Global Interrupt Enable Register Access to this register is accomplished via IORD IOWR and IOWX instructions to address 0x20 Writing a 1 to a bit position enables the interrupt associated with that position During a reset the contents the Interrupt Enable Register are cleared disabling all interrupts Figure 5 15 illustrates the format of the Global Interrupt Enable Register s 8 mW mW RW RW Wake up GPIO Reserved USB USB EPO 1 024 ms Reserved Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Enable Enable Enable Enable Enable Enable Figure 5 15 Global Interrupt Enable Register Address 0x20 The interrupt contro
170. the response is a NAK This bit is cleared following a SETUP or OUT transaction 20 CY7C63000 CY7C63001 __ CY7C63100 CY7C63101 gt __ PRELIMINARY CY7C63200 CY7C63201 5 10 Instruction Set Summary Table 5 4 Instruction Set Map MNEMONIC operand opcode MNEMONIC operand opcode cycles mr ___ ___ m f da m CA jme oe fe x e m 7 AOC Rem f _ fe e WocADeem me pe gt eX w 1 jme m y fe 5 _ m 7 E CC _ 5 _ POPA me po 7 qp 2 der 5 AND A expr direct AND A X expr index ho al e m MOV expr A direct E MOV index neea CE 024 CO 4 r ANDA E S ____ ES ded 7 ROR Tema 3 IN __ me _ lt me _ me ASL WoVXep CC 6 4 MR MWovxiew wa o o we mag LL E p m 2 27 2 7 38 39
171. tre los circuitos integrados y tambi n el puerto USB Tambi n se tomo en cuenta la corriente de salida del puerto USB y el voltaje que este entrega a las cargas que se le conectan para de esta forma tener claro si es posible que exista una correcta alimentaci n de energ a por parte del puerto USB hacia los componentes electr nicos que se desean utilizar el puerto USB puede proporcionar una corriente no mayor a 500 mA y el dispositivo que mas consume corriente es el maestro conectado con la punta de osciloscopio cuyo valor es menor a los 200 mA Algo muy importante que fue tomado en cuenta son los qu micos a utilizar tanto para poder hacer los circuitos impresos as como el manejo de las resinas ya que estas deben de ser utilizadas con la medida exacta de componentes esto con el fin de evitar desperdicios que el producto no funcione como es debido o que se produzca un accidente Es por esto que se tomaron todas las precauciones necesarias al caso tales como usar gabachas anteojos de seguridad guantes y tener los conocimientos en qu mica necesarios para poder hacer las mezclas de la mejor forma adem s del tratamiento que hay que darle a los desperdicios para que no contaminen o que contaminen lo menos posible esto se logr depositando los residuos en ladrillos y sell ndolos con cemento para que no queden expuestos al medio ambiente 15 Capitulo 4 Procedimiento Metodol gico del problema 4 1 Reconocimiento y definici n del problema
172. trol is regulated by USB Status and Control Register located at I O address 0x13 as shown in Figure 5 25 This is a read write register All reserved bits must be written to zero All bits in the register are cleared during reset 3 2 m Hesume Figure 5 25 USB Status and Control Register Address 0x13 Bit O will be set by the SIE if any USB activity except idle D LOW D HIGH is detected The user program should check and clear this bit periodically to detect any loss of bus activity Writing a 0 to this bit clears it Writing a 1 does not change its value Bit 1 is used to force the on chip USB transmitter to the K state which will send a Resume signal to the host Bit 2 is a reserved bit that must be set 10 0 Bit 3 is used to automatically respond to the Status stage OUT of a control read transfer on End Point 0 A valid Status stage OUT contains a DATA1 packet with 0 bytes of data If the StatusOuts bit is set the USB engine will respond to a valid Status stage OUT with an ACK and any other OUT with a STALL The data is not written into the FIFO when this bit is set This bit is cleared when a SETUP token is received by End Point O Bit 4 is used to enable the receiving of End Point 0 OUT packets When this bit is set to 1 the data from an OUT transaction to be written into the End Point 0 FIFO and the USB engine responds with an ACK If this bit is 0 data will not be written to the and
173. uente de informaci n mas a mano y actualizada que se encontr Una vez que se obtuvo la informaci n deseada se procedi a hacer el estudio correspondiente Luego se procedi a hacer simulaci n en alguno de los programas para simulaci n de circuitos existentes para tratar de predecir de esta forma el comportamiento del circuito en la realidad Seleccionados todos los componentes a utilizar se mandaron a pedir a EE UU Cuando los componentes solicitados llegaron se procedi a hacer las mediciones correspondientes y a implementar los circuitos necesarios Con el prototipo funcionando se decidi mandar a traer los componentes de montaje de superficie para hacer los montajes correspondientes Para esta parte los circuitos no llegaron al pa s as que se continuo trabajando solamente con el prototipo sin haber hecho el montaje en placas procedi a implementar el software necesario para mostrar la informaci n en la computadora Ya con los circuitos y el programa realizados se procedi a hacer las mediciones y calibraciones necesarias tomando como base los volt metros amper metros y osciloscopios que se encuentran en los laboratorios de electr nica Por ltimo se procedi a realizar los manuales de usuarios necesarios y el informe final del proyecto A lo largo del proyecto han sido necesarias algunas modificaciones de las soluciones presentadas en el siguiente cap tulo esto dado que inicialmente los 18 dise
174. uestra una medici n hecha con el dispositivo de punta removible del osciloscopio Como se puede observar en la figura 6 3 y la figura 6 4 las mediciones de la onda son id nticas esto debido a que se utiliz el mismo circuito de prueba para ambos dispositivos de medici n Estas mediciones han demostrado que el dispositivo de adquisici n de datos implementado por USB es totalmente funcional satisfaciendo los objetivos esperados Tabla 6 Caracter sticas el ctricas de la punta de osciloscopio _ Voltaje de alimentaci n _ Corriente de entrada 90 pA 90 pA Impedancia de entrada 10 GO 10 GO Respuesta de frecuencia 32 Cap tulo 7 7 1 Conclusiones 1 2 La utilizaci n de integrados inversores de potencial reduce la circuiter a y proporciona la tensi n necesaria para los amplificadores de instrumentaci n Con los amplificadores de instrumentaci n se evita el uso de multiplexores anal gicos se economiza espacio y tiempo a la hora de construir el ciruito Con la ayuda de un integrado que trabaje con una fuente de tensi n positivo se puede lograr introducir un nivel de offset a una se al anal gica permitiendo que esta se al sea luego introducida a un ADC sin que su forma se vea alterada Con la ayuda de los microcontroladores se puede implementar la comunicaci n entre un dispositivo y la PC El puerto USB de la computadora permite introducir datos anal gicos en forma de Bits a la PC para que
175. ure of the life support device or system or to affect its safety or effectiveness National Semiconductor National Semiconductor Asia Pacific Customer Japan Ltd Response Group Tel 81 3 5639 7560 Tel 65 2544466 Fax 81 3 5639 7507 Fax 65 2504466 Email ap support nsc com National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications BURR BROWN O PGA202 203 Digitally Controlled Programmable Gain INSTRUMENTATION AMPLIFIER FEATURES O DIGITALLY PROGRAMMABLE GAINS DECADE MODEL PGA202 GAINS OF 1 10 100 1000 BINARY MODEL PGA203 GAINS OF 1 2 4 8 LOW BIAS CURRENT 50pA max O FAST SETTLING 215 to 0 01 LOW NON LINEARITY 0 012 max HIGH CMRR 80dB NEW TRANSCONDUCTANCE CIRCUITRY LOW COST DESCRIPTION The PGA202 is a monolithic instrumentation ampli fier with digitally controlled gains of 1 10 100 and 1000 The PGA203 provides gains of 1 2 4 and 8 Both have TTL or CMOS compatible inputs for easy microprocessor interface Both have FET inputs and a new transconductance circuitry that keeps the band width nearly constant with gain Gain and offsets are laser trimmed to allow use without any external com ponents Both amplifiers are available in ceramic or plastic packages The ceramic package is specified over the full
176. ves as the A D identifying word in 03 A D 3 the program DATA BUS al D gt gt gt gt NI 5 9 ow al gt gt gt DS005671 29 FIGURE 22 Multiple A Ds with Z 80 Type Microprocessor www national com 38 Functional Description continued INTERRUPT SERVICING SUBROUTINE LOC 0058 0059 003A 003B 003E 0040 0042 0044 0045 0046 0048 004B 004C 004D 004E 0051 0052 0055 0057 0059 005A 0058 005 0050 0060 0061 0062 0065 5 5 5 21 00 SE OE 01 0500 0800 47 DA 5500 C3 4500 ED 78 EE FF 77 2C 71 2C C35 51 00 1 Cl El C9 IEST NEXT LOAD DONE SOURCE STATEMENT PUSH HL PUSH BC PUSH AF LD HL 5 00 LD C OUT X00 A INA X00 LD LDA C CP X08 JPZ DONE LD B A JPC LOAD INC JP TEST INA C XOR FF LD HL A INCL LD HL C INCL JP NEXT POP AF POP BC POP HL RET COMMENT Save contents of all registers affected by this subroutine Assumed INT mode 1 earlier Set Initialize memory pointer where data will be stored Cregisterwillbe port ADDR of A D converters Load peripheral status word into 8 bit latch Load status word into accumulator Save the status word Test to see if the status of all A D s have been checked If so exit Subroutine
177. vs Time Offset vs Supply uV Month INPUT BIAS CURRENT Initial Bias Current at 25 C at 859 Initial Offset Current at 25 at 85 C COMMON MODE REJECTION RATIO INPUT NOISE Noise Voltage 0 1 to 10Hz Noise Density at 10kHz 9 OUTPUT NOISE Noise Voltage 0 1 to 10Hz Density at 1kHz 9 DYNAMIC RESPONSE Frequency Response G 1000 G 1000 Full Power Bandwidth lt 1000 G 1000 Slew Rate Settling Time 0 01 7 G 1000 1000 Overload Recovery Time 7 G 1000 1000 DIGITAL INPUTS Digital Common Range Input Low Threshold 9 Input Low Current Input High Voltage Input High Current POWER SUPPLY Rated Voltage Voltage Range Quiescent Current TEMPERATURE RANGE Specification Operating Storage On C gt eem N UJ UU UJ C C W Same as the PGA202 203AG NOTES 1 All specifications apply to both the PGA202 and the PGA203 Values given for a gain of 10 are the same for a gain of 8 and other values may be interpolated 2 Measured with a 10k load 3 The analog inputs are internally diode clamped 4 Adjustable to zero 5 Vwoise ati V VN input Vu ourrur Gainy 6 Threshold voltages are referenced to Digital Common 7 From input change or gain change
178. wide CS and WR signals and the converter will start after at least one of these signals returns high and the internal clocks again provide a reset signal for the start F F Functional Description continued 17 RESET SHIFT REGISTER 0 BUSY AND QUIESCENT STATE D DA INPUT PROTECTION FOR ALL LOGIC INPUTS INPUT TO INTERNAL CIRCUITS BV 30V START CONVERSION Vec IF RESET 0 g SAR 8 BIT VREF 2 O NOTE 2 0 8 A GND LE LATCH 1 0 508090VW 08090V 208090V 208090V 108090V 6 Y O D meme a Y OUTPUT LATCHES EIER MSB LSB 00000 11 12 13 14 15 16 17 1 INTR CONV COMPL DIGITAL OUTPUTS 1 TRI STATE CONTROL En Ld CS NOTE 1 gt 1 OUTPUT ENABLE RDO O RESET DS005671 13 Note 13 CS shown twice for clarity Note 14 SAR Successive Approximation Register FIGURE 4 Block Diagram After the 1 is clocked through the 8 bit shift register which completes the SAR search it appears as the input to the D type latch LATCH 1 As soon as this 1 is output from the shift register the AND gate G2 causes the new digital word to transfer to the TRI STATE output latches When LATCH 1 is subsequently enabled the Q output makes a high to low transition which causes the INTR F F to set An inverting buffer then supplies the INTR input signal Note that this SET control of the INT
179. x has ten GPIO Notice that each part has eight low current ports Port 0 with the remaining ports Port 1 being high current The twelve GPIO CY7C6300x is available in is a 20 pin PDIP PC 20 pin SOIC SC and a 20 pin Windowed CerDIP The sixteen GPIO CY7C6310x is available in a 24 pin SOIC SC and a 24 pin Windowed CerDIP SC The ten GPIO CY7C6320x is available in an 18 pin PDIP PC and an 18 pin Windowed CerDIP WC CY7C63000 CY7C63001 CY7C63100 CY7C63101 PRELIMINARY CY7C63200 CY7C63201 CYPRESS Logic Block Diagram 6 MHz RESONATOR 18 DIP Windowed CerDIP PO 0 LH 1 18 4 02 17 5 P0 2 03 16 P0 6 P0 3 04 15 7 P1005 14 P1 1 55 6 13 D XTALIN 9 10 J XTALO Pin Configurations Top View 20 pin 24 pin DIP SOIC SOIC Windowed CerDIP Windowed CerDIP PO 0 1 20 P0 4 1 12 19 0 5 2 0 20 3 18 P0 6 3 PO 3 4 17 P0 7 4 P1 0r15 16 1P1 1 5 P1 206 15 1 3 6 VSS U 7 14 J D 7 VPP 8 13 00 8 9 CEX UT XTALIN 10 11 XTALOUT 6311 1 CY7C63000 CY7C63001 CY7C63100 CY7C63101 gt __ PRELIMINARY CY7C63200 CY7C63201 3 0 Pin Definitions epin 1 Poom SooS 3 3 Port 1 bit 2 19 Port 1 bit 3 Peta SSS ma vO 7 ms vO e Pontes SSCS ms

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