「電子政府推奨暗号の実装」報告書 （PDFファイル 1.43MB
Contents
1. CLK1 RSTn 0 CLK2 EN 1 Drdy 1 Kin K Busy 1 EncDec 1 CLK7 Kvld 1 Busy 0 CLK8 Drdy 1 EncDec 1 Din CT Busy 1 CLK30 Busy 0 Dvld 1 Dout PT2. m s ms v v V V v V v V V VY V Y V 1 mds m s o Y v V v Y V v Y Y Y Y Y Y Y X 5 1 Hierocrypt 3 E AL 28 imdsr imdsr imdsr imdsr Eo V V V V v V v v Y Y Y V 3 imdsr imdsr imdsr imdsr V V V V Y v 7 3 v 1 X 5 2 Hierocrypt 3 29 1 1 TH T 1 24 Z5 p F T 1 1 1 T 1 2 1 25 23 z X 5 3 Hierocryot 3 X 5 4 Hirocrypt 3 5 5 128 ft Virtex 5 32 64
3. CLK1 RSTn 0 CLK2 Kin Key EN 1 Krdy 1 50 Busy 1 CLK19 Kvld 1 1 Busy 0 CLK20 lin 128 IV rrdy 1 Busy 1 CLK52 0 CLKS3 Rrdy 1 Busy 1 CLKS4 Rvld 1 Busy 0 64 RO Rout CLK55
4. 1 SASEBO GII FPGA 5 EXHO 128bit Al 64 256 IV R 256 IPA Windows PC Windows PC USB USB Windows PC ZN USB 4 4 USB Ctrl JFT2232D X PE e S S box 1 JTAG IEBPROM SPI ROM 4 o 11
5. 4 2 FTD2XX NETdl FTD2XX NET xml FTDI Future Technology Devices International http www ftdichip com Support SoftwareExamples CodeExamples CSharp htm USB pdf uu FPGA1 DISC2 lt gt lt Virtex 5 gt v Verilog HDL FPGA1 y 44 ucf bus iEY MULTIL S01 4 PANAMA y Y tbv
6. MS 0 uS ukl MS 1 uk3 MS 2 uk5 MS 3 uk6 uk7 46 17 384 39 6 18 32 one imkey 6 19 384 32 6 20 4 1 128 vh 14 1 792 SA SW 32 H8 ro rp 128 XOR 32 round 00 a0 al y 0150 bl 101c0 cl D 11 40 di one ekey 6 19 128 a0 al a2 bObl b2 cOclc2 40 41 d2 6 20 32 one 40 42 Hi
7. Busy 1 CLKS8 Busy 0 Dvld 1 Dout PT CLKS9 Drdy 1 EncDec 1 Din CT Busy 1 26 Hp Bev cessi ce ur ges n e ES Busy KL Dout PE ie sd K PK cse es X 4 11 27 5 Hierocrypt 3 128 Hierocrypt 3 5 1 EBd 5 2 BK 4 p 1 XS AK SPN MDS MDSy x Hierocryot 3 5 3
8. SASEBO GII 3 SRAM 39 2Mbits 24 Header IO Push SW Camellia CIPHERUNICORN A Hierocrypt 3 SC2000 MULTI S01 MUGI LUT Verilog HDL ISE WebPACK Version 12 4 SASEBO GII FPGA Viretex 5 SASEBO GII 24MHz CIPHERUNICORN A 24MHz FPGA Spartan 3 12MHz FPGA CIPHERUNICORN A 24MHz 1 1 DVD DISCI
9. Dvld Dout CT Busy 0 CLK1379 CLK 0 1 2 3 887 sss Tss 1890 T 891 1376 T1378 1377 Ti378 T1379 Day K NN S a k EncDec Busy Dot WA U AMAA WWW Dvld 5 6 CLK1 RSTn 0 CLK2 EN 1 Krdy 1 Busy 1 CLK888 Kvld 1 Busy 0 38 CLK890 CT Din EncDec 1 Drdy 1
10. 10 KA 3 2 F 4 3 1 kwi 64 lt lt lt 0 Initial kwas Ki lt lt lt 0 Round 1 lt lt lt 0 Round 2 K e4 lt lt lt 0 p Round3 kso lt lt lt 15 Round 4 KAG4 lt lt lt 15 Round 5 4 lt lt lt 15 oo Round 6 kecoa lt lt lt 15 FL kl lt lt lt 30 1 FL lt lt lt 30 Round 7 krea lt lt lt 45 Round 8 64 lt lt lt 45 F Round 9 lt lt lt 45 Round 10 io lt lt lt 60 Round 11 Ka lt lt lt 60 1 Round 12 2064 lt lt lt 60 Klsqga lt lt lt 7 FI klaqga 1 lt lt lt 77 na Round 13 kiza lt lt lt 94 Round 14 Kia oa lt lt lt 94 R 64 p Round 15 Kk1s 64 lt lt lt 94 Round 16 k16 64 lt lt lt 94 Round 17 Kk17 64 lt lt lt 111 raa Round 18 18 64 1 lt lt lt 111 na Kw3 64 lt lt lt 111 Final XOR lt lt lt 1 1 R 64 16
11. Feistel Network 2 p gt to Camellia 4 S box S1 S4 GF 2 Bd 3 3 S1 1 S2 1 S3 1 84 S box 8 Sl 4 8 S3 8 hi A 2 8 54 s 8 x gt y 51 X 3 3 Camellia S box 2 g x 1 GF 2 g x 2x 0 lt 10011 17 b b 1 0 0 0 0 0 1 0 ael b 0 0 1 0 1 0 01 p 5 19 9100 00 1 b 0 0 0 1 0009 vb olla b 1000 0 0 0 Illa b 00010 1 0 0 1 b 1 0 01 1 0 Afa 0 b 0 1 0 0 0 1 0 0llg 1 b 0 0 0 1
12. Busy 1 CLK32 Busy 0 Dvld 1 Dout PT HENA CLK33 Drdy 1 EncDec 1 Din CT Busy l CLK 0 1 2 3 15 1716 117 T18 T 19 T31 132 133 134 Dou rr o aa L n Cr D Cu ieu el X 622 42 7 MULTI S01 MULTI S01 PANAMA Bd 7 1 7 2 5 psi Rd PANAMA PANAMA reset push pull 3 reset PANAMA push
13. CLK CLK In Kin In 256 SEA JJ h 256 INI A Qin In 256 256 13 Lin In 32 32 Din In 64 64 Krdy Lrdy In In Kin Krdy 1 Kin Lrdy 1 T Lin 3 Tv
14. bif SPI ROM mcs lt Spartan 3 gt FPGA2 bit FPGA2 mcs CIPHERUNICORN A SASEBO GII 24MHz 12MHz FPGA2 12MHz bit FPGA2 12MHz mcs lt gt algorithm test cs lt Windows algorithm test exe txf algorithm test exe 23
15. Busy 0 CLK41 Lin Len Lrdy 1 CLK42 64 PT Din EncDec 0 Drdy 1 Busy 1 CLK46 Dvld 1 Busy 0 64 CT Dout CLK47 46 pn Drdy 5 1 i Busy 36 clock ME C ERES MA AAA is bl S RN 478 CLK1 RSTn 0 CLK2 Qin Q Kin Key
16. AddRoundKey InvMixColumns 2 2 ImvMixCol MixColumns 12 ShiftRows InvShiftRows InvMixCol SubBytes InvSubBytes Key LDecKreg 2 2 AES CLK1 RSTn 0 CLK2 Krdy 1 Kin 128bit CLK3 EncDec 0
17. R 1 2 DISC2 T DISCI lt gt lt gt CAD Qualtus ISE WebPACK Qualtus II Cyclone Stratix ISE WebPACK Spartan 3 Spartan 6 Virtex 5 Virtex 6 2 Hieroctypt 3 MULTI S01 spartan 3 pwr twr lt gt lt Virtex gt
18. 4 xy GEF 2 LE 11 2 1 AES ren 4 b 1 11 dd 0 b 11 00011 1 1 1 110001 lla lo 4 1 1 11000 0 1 Er 99 27 lo b lo111110 0 1 b 00 1 1 1 1 1 O a 1 b 000 1 1 1 1 Ifa 0 b 00 1 0 0 1 0 b 1 001001 0 261 b 0 100109 81 b b 10 1 b 1001010 0 a bJ 01001 0 1 Oja MixColumns 4x4 x 00 3 4 x 1 c x 031 0117 01 102 mvMixColumns x 081 0D1x 109 0E X 2 2 128 AES S box GF MixColumns InvMixColumns
19. ucf Virtex ucf FPGA1 v bus_iEV lt Spartan 3 gt CIPHERUNICORN A 12MHz chip sasebo gii ctrl 12MHz v 1 1 DISC 1 pdf AE zu m u Hf word pdf at H E sord pdf Word pdf Word pdf Word AES flow Qualtus flow report AES map Qualtus II analysis amp synthesis report lt gt Camellia flow Camell
20. 6 1 35 func B func 8877 v 7 4 0x33333333 0x55555555 CN x ng 9 NI Xr x gt ias poppe po papas 384 bit Reg k uk7 64 6 1 AES 5 I I I 2 B LR BLLR 3 RI RI 4 B L R BLR 5 RI 6 B LR BLR 7 RI 8 B LR BLLR 9 RI R I 10 B LR BLR 11 12 B L R BLR 13 RI RI 14 B I BI 36 465 6 8 14 R r mask sel T 0x33333333 0x55555555 i sel ek0 ek1 2 ek3 r mask 0x33333333 R func k 0x55555555 i sel ek0 ek1 ek2 ek3 X 6 6 R B func mask 0x33333333 R func k 0x55555555 i sel ek0 ek1 ek2 ek3 sel 6 7 R
21. 256 8 256 8 Q pull 1 32 K Q K Q X 71 MULTI SO1 7 2 MULTIL SO1 5 7 3 PANAMA a 32 x17 544 a 1 b 7 4 32 x8 LFSR 25 V E AJ 17 p 7 5 8word 17word Sword SO 9 SO 16 3 PANAMA
22. Busy 1 E CLK1377 Dvld 1 720 Dout PT Busy 0 CLK1379 CLK 0 1 2 s d hw w Din Q Drdy LET m Busy 886 ONT Dvld 34 MAMMA PT WWW 6 SC2000 6 1 6 2 128 SC2000 SC2000 Feistel SPN XOR 1 14 SPN B B 7 Feistel R 12 33 32 56
23. CLK3 gt BSY 1 CLK14 BSY 0 Kvld 1 Din 128bit CLK15 EncDec 1 BSY 1 Kout CLK16 25 10 CLK25 128bit BSY 0 7 2187 18 5 Dvld 1 1 14 CLK 0 1 2 3 1 1 712 113 114 1 15 22 124 125 26 Kin Key H EIL de Krdy r r T Din HH Drdy J EncDec BSY Kout eo Dout PT SE MEME NM r Saa X 2 4 AES 15 3 Camellia
24. 1 Kvld 1 45 X CN 7 7 7 E 7 8 7 9 CLK1 RSTn 0 CLK2 Qin Q Kin Key EN 1 Krdy 1 Busy 1 CLK39 Kvld 1 1
25. ek 0 ek 3 ek 4 51 ek 6 ek 7 0x55555555 0x55555555 ek 8 ek 9 ek 10 ek 11 ek 12 ek 13 ek 14 ek 15 5 0x33333333 0x33333333 ek 48 491 ek 50 ek 51 ek 52 ek 53 ek 54 ek 55 5 6 1 2000 ek 52 ek 53 ek 54 ek 55 ek 48 ek 49 ek 50 ek 51 8 0x33333333 0x33333333 ek 12 ek 13 ek 14 ek 15 ek 8 ek 9 ek 10 ek 11 0x55555555 0x55555555 ek 4 ek 5 ek 6 ek 7 ek 0 ek 1 ek 2 ek 3 e f g h B 6 2 SC2000 X 6 3 6 4 SC2000 1 B B R 2 1 14 14 IO 1 15 1 0128
26. 37 B func r mask 1 0x33333333 0x55555555 i sel gt ek0 ek1 ek2 ek3 sel 5 6 8 R BE I I 6 9 128 128 R 6 10 Feistel 128 64 F 64 14 R 32 32 32 32 k 32 kb 32 k 32 32 32 f 469 1 6 10 R F 6 11 64 32 S M L S 32 6 12 5 6 S box M d 6 13 M matrix
27. CLK31 EncDec 0 Drdy 1 PT Busy 1 Dout CLKS3 Busy 0 Dout CT Dvld 1 1 CLK54 EncDec 1 Drdy 1 1 Dvld 0 CLK76 Busy 0 Dout PT Dvld 1 19 CLK RSTn EN EncDec Kin 127 0 Krdy Din 127 0 Drdy Dout 127 0 Busy 20 4 CIPHERUNICORN A
28. Din PT Busy 1 CLK 0 1 2 3 1511716 117 19 T31 132 T33 134 Drdy USE COEUR EE OE D EncDec Dow 98 WW Dvld Ne iie Dawa em P Ie Py 1l 5621 41 CLK1 RSTn 0 CLK2 EN 1 Drdy 1 Kin K Busy 1 CLK17 Kvld 1 Busy 0 CLK18 Drdy 1 EncDec 1 Din CT
29. Rrdy 1 Busy 1 CLK56 Rvld 1 R2 CLK 0 1 2 17 F18 F19 T20 51 152 T53 T54 155 T56 157 T 58 LIT bend Ml LT Key PLI KP ires eod sw Lu Jf Lil Iin 4 ya Irdy m Ay ae li AI BSY Rout 285 51
30. Pill Drdy In Din EN 1 Drdy 1 Din EncDec In EncDec 0 EncDec 1 EN In EN 1 gt EN 1 Drdy Dout Out 64 Dvad 1 Busy Out Krdy Drdy Buy 1 Krdy Drdy Douf Dvld
31. Rrdy Im 1 1 Rout EN 1 EN Im 1 gt EN 0 Krdy Rrdy Rvld 1 Krdy Trdy Busy Out 1 Busy 1 Krdy Irdy Rout 1 FZR 1 Rvld 1 Kvld Out 1 1 Kvld 1 RSTn In 1 I In 256 Krdy In 1 Irdy In 1 128 8 5
32. 43 E 7 KAKI E e I5 22 6 E 6 1 ET Be S NN 140 D P P D P P Y Y P S OQ Q OQ Q O 5 7 5 p X 7 6 7 7 64 PANAMA 64 64 C C 1 Ex M P C 1 64 7 1 MULTI S01 IO RSTn In RSTn 0 G
33. SC2000 v SC2000 tb v FPGA1 SC2000 v lbus ifv lt 3 gt chip sasebo gii ctrl 12MHz v Spartan 3 12MHz R H 1 3 H TO MULTI SO1 4 HB MUGI IO 7 8 R 1 3 ax 13 VO RSTn 0 RSTn In 1 EN
34. 49 MT X 410 4 11 CLK1 RSTn 0 CLK2 Drdy 1 Kin K Busy 1 CLK41 Kvld 1 Busy 0 CLK42 Drdy 1 EncDec 0 PT Busy 1 CLKS58 Busy 0 Dvld 1 Dout CT CLKS
35. SUE BSY 1 CLK14 BSY 0 1 Kvld 1 Din 128bit CLK15 EncDec 0 BSY 1 Kout CLK16 23 BSY 0 Dvld 1 1 13 0 CLK25 128bit Dout Drdy EncDec BSY Kout Dout Dvld og I MI X 2 3 AES 2 4 CLK1 RSTn 0 CLK2 Krdy 1 128bit
36. 2 3 1 2128 K 5 Camellia7 F Y RADERA S x EY 22 6 Feistel 2 FL FL 128 128 XOR 128 64 Feistet F 64 XOR F 64 64 XOR 8 8 4 S1 S4 x2 S box 64 P 128 Lit O G H 2 128
37. EN 1 Krdy 1 Busy 1 CLK39 Kvld 1 1 Busy 0 CLK41 Lin Len Lrdy 1 CLK42 64 CT Din EncDec 0 Drdy 1 Busy 1 CLK46 Dvld 1 Busy 0 64 PT Dout CLK47 47 em doe S Toug EPS Ee unius Lin Be sies MM hl e Age c hee MM 0 mo NL Re V Busy 36 clock ME C ERES MAL T AAA is WS Ee
38. FPGA1_SC2000 summary html FPGA1 SC2000 map mrp ISE synthesis summary ISE synthesis report ISE mapping report ISE power analysis report ISE timing report lt 5 gt AES AES bit Virtex 5 bit stream file AES mcs Virtex 5 PROM file lt gt Camellia bit Virtex 5 bit stream file Virtex 5 PROM file lt gt CIPHERUNICORN A bit CIPHERUNICORN A mcs Virtex 5 bit stream file Virtex 5 PROM file Hierocrypt 3 gt Hierocrypt 3 bit Hierocrypt 3 mcs Virtex 5 bit stream file Virtex 5 PROM file lt MUGT gt MUGI bit Virtex 5 bit stream file MUGI mcs Virtex 5 PROM file lt MULTI S01 gt MULTI S01 bit MULTI S01 mcs Virtex 5 bit stream file Virtex 5 PROM file lt SC2000 gt SC2000 bit Virtex 5 bit stream file SC2000 mcs Virtex 5 PROM file lt Spartan 3 gt FPGA2 bit Spartan 3 bit stream file 24MHz FPGA2 mcs Spartan 3 PROM file 24MHz FPGA2 12MHz bit FPGA2 12MHz mcs Spartan 3 bit stream file 12MHz Spartan 3 PROM file 12MHz algorithm test cs algorithm test exe FTD2XX NET dll FTD2XX NET xml AES txt Camellia txt CIPHERUNICORN A txt Hierocrypt 3 txt MUGL txt PC 1 PC USB DLL USB
39. T K 8 1 MUGI IO RSTn 0 CLK CLK In 1 Kin In 256 256 Cv OD BIA WEZ IN 713 5 256 Kin Krdy 1 Kin Hin EN 1 Irdy 1 fn EN 1 Rrdy 1
40. 4 111286 k gt CIPHERUNICORN A 7 v H U RA OD 166tFeiste 4 2 F XOR 4 3 128 12 MT 16 MT 8 32 9 72 32 on the fly IK IK EE X 4 1 CIPHERUNICORN A Oxfe21464b 0x7e167289 SK 0 lt gt CO CL CO Cl HH SKa z 0 7 167289 Oxfe21464b 52 OxTe167289 Y CN A lt gt 32
41. gt Hierocrypt 3 summary html Hierocrypt 3 syr ISE synthesis summary ISE synthesis report lt gt FPGA1 Hierocrypt 3 summary html FPGA1 Hierocrypt 3 syr FPGA1 Hierocrypt 3 map mrp FPGA1 Hierocrypt 3 pwr FPGA1 Hierocrypt 3 twr ISE synthesis summary ISE synthesis report ISE mapping report ISE power analysis report ISE timing report MUGI lt gt MUGI summary html MUGI syn ISE synthesis summary ISE synthesis report lt gt FPGA1 FPGA1_MUGI summary html ISE synthesis summary ISE synthesis report FPGA1 ISE mapping report FPGA1 MUGI pwr ISE power analysis report MUGItwr ISE timing report lt MULTI S01 gt lt gt MULTI SO1 syr MULTI S01 summary html ISE synthesis summary ISE synthesis report lt gt FPGA1 MULTI SO1 summary html ISE synthesis summary SC2000 syr FPGA1 MULTI SO1 syr ISE synthesis report FPGA1 MULTI S01 map mrp ISE mapping report FPGA1 MULTI SO1 pwr ISE power analysis report FPGA1 MULTI SO1 twr ISE timing report lt SC2000 gt lt t gt SC2000 summary html ISE synthesis summary ISE synthesis report lt gt FPGAI_SC2000 syr FPGAI_SC2000 pwr FPGAI SC2000 twr
42. L 6 14 32 AND XOR 6 11 F 6 12 S 38 32 32 mask Z 2 mask 32 32 c d 4613 M 6 14 L 6 15 6 16 G B S box T T 959 dd 959 lt d ZEND lt Z lt lt S SS X 6 15 6 16 x 6 17 64 32 6 18 12 256 384 128 fuk0 ukl uk3 fuk4 uk5 uk6 uk7 MS 4ij 32
43. MixColumns 4 4 4 S box 4 10 4 rei rcio f 5 CU SERE E EC 0 ONE ShiftRows 4x4 ubBytes AddRoundKey XOR 128 ORERE ko DD 10 EO ZU FE koko reirei 3 ShiftRows AES O S box X 1 yE
44. 1 32 NL E 7 NL NL NL 0 LI 32 1 T T2 T Ti Ti To To A3 PLR 6 Oxfe21464b 5 4 2 CIPHERUNICORN A F 21 i1ZuvZGl2vvFER keyz 32 4 3 CIPHERUNICORN A X 4 4 4 6 CIPHERUNICORN A RL T4 16 128 1 22 F 16 VO 1 17 128 128 44 CIPHERUNICORN A Oxfe21464b 0x7e167289 Oxfe21464b 0x7e167289 Oxfe21464b 45 F 23 ksround round fka ska fkbskbik0 ik1 ik2 ik3 ik4 ik5 ik6 ik7 46 F 128 Feiste
45. ISE timing report lt 3 gt lt gt Hierocrypt 3 summary html Hierocrypt 3 syr ISE synthesis summary ISE synthesis report lt gt Hierocrypt 3 summary html Hierocrypt 3 syr ISE synthesis summary ISE synthesis report Hierocrypt 3 map mrp ISE mapping report lt MUGI gt lt gt MUGLsummary html ISE synthesis summary MUGI syn ISE synthesis report lt gt FPGA1 MUGI summary html FPGA1 FPGA1 MUGLmap mrp FPGA1 MUGI pwr FPGA1 MUGItwr ISE synthesis summary ISE synthesis report ISE mapping report ISE power analysis report ISE timing report lt MULTI S01 gt lt gt MULTI S01 summary html MULTI SO1 syr ISE synthesis summary ISE synthesis report lt gt FPGA1 MULTI SO1 summary html FPGA1 MULTI 801 5 ISE synthesis summary ISE synthesis report FPGA1 MULTI S01 map mrp ISE mapping report lt SC2000 gt lt gt SC2000 summary html ISE synthesis summary SC2000 syr ISE synthesis report lt gt SC2000 summary html SC2000 syr ISE synthesis summary ISE synthesis report SC2000 map mrp ISE mappi
46. flow report Qualtus II analysis amp synthesis report lt SC2000 gt SC2000 flow Qualtus flow report SC2000 map Qualtus II analysis amp synthesis report lt Spartan 3 gt lt AES gt lt gt AES summary html ISE synthesis summary AES syr ISE synthesis report lt gt AES summary html FPGA1 AES syr AES map mrp AES pwr AES twr ISE synthesis summary ISE synthesis report ISE mapping report ISE power analysis report ISE timing report lt Camellia gt lt gt Camellia summary html Camellia syr ISE synthesis summary ISE synthesis report lt gt FPGA1 Camellia summary html FPGA1 Camellia syr FPGA1 Camellia map mrp FPGA1 Camelha pwr FPGA1 Camellia twr ISE synthesis summary ISE synthesis report ISE mapping report ISE power analysis report ISE timing report lt gt lt gt CIPHERUNICORN A summary html CIPHERUNICORN A syr ISE synthesis summary ISE synthesis report lt gt CIPHERUNICORN A syr FPGAI CIPHERUNICORN A map mrp CIPHERUNICORN A pwr CIPHERUNICORN A twr FPGA1 CIPHERUNICORN A summary html ISE synthesis summary ISE synthesis report ISE mapping report ISE power analysis report
47. XML AES Camellia CIPHERUNICORN A Hierocrypt 3 MUGI MULTI SOI txt SC2000 txt MULTI S01 SC2000 1 2 DISC2 lt 5 gt AES AES ucf VO AES v AES tb v FPGA1 AES v lbus ifv lt gt Camellia ucf VO Camellia v Camellia tb v FPGA1 Camellia v lbus ifv lt gt CIPHERUNICORN A ucf CIPHERUNICORN A v CIPHERUNICORN A tb v FPGA1 CIPHERUNICORN A v Ibus if v lt Hierocryp
48. 0 0 1 ofla 1 b 0 1000001l1 al 0 e b 0010 0 01 lal 1 b 1 0 0 0 0 0 0 Ila l b 1 0 0 0 1 0 0 0llal 1 bJ 0 X 3 4 Camellia 1 FL FL key whitening 128 64 1 Key whitening FL FL 2 F 18 F TO 1 F 23 E 64 V64 64 Z B7 54 3 4 Camellia 5 15 X Key whitening XOR FL FL XOR FL FL 18 FL b FL X 3 5 3 6
49. 0 G AR T i Kin In 128 Din In 128 Krdy 1 EN 1 Krdy 1 Kin EN 1 Drdy 1 Din EncDec 0 Drdy T i EncDec 1 IDrdy 1 V EncDec In 1 EncDec 0 EncDec 1 EN 1 EN 0 EN In 1 Dvld 1 Dout Out 128 Dvld 1 Busy Out 1 Busy 1 Busy 1 Krdy
50. 1 Drdy 1 P i Dout 1 Dvld 1 Kvld 0 1 BHAM ATULCSELLZAZAMENRATUAC Kvld 1 1 Kvld 1 10 2 AES 2 1 x4 16 AddRoundKey 128 AES 128 ENDIL 4 SubBytes ShiftRows MixColumns Key Generator Co C 11 SubBytes S box 16 fB F 4 GF 2 InvSubBytes InvSiftRows
51. 2011 399 RU 24 12 Information technology Promotion Agency Japan Ip or RIMIS 1 m EEE E HH 11 Ga 16 GIPHERUNIGCORNsAS kG 21 Hieroerypt SR EE EE 28 SG 2000 MM 35 MUPTES01 2 2 43 yka 49 1 1 1 Y 107 E AES Camellia CIPHERUNICORN A 128 Hierocrypt 3 128 128 128 C vh 128 E 5 fi 2 CAD 128 128 128 SC2000 128 128 MULTI SO1 MUGI 64 128 IV 256 SASEBO GII FPGA Spartan 3A USB
52. 30 5 5 4 Hierocrypt 3 31 X 5 5 Hierocrypt 3 32 x 5 6 5 7 CLK1 RSTn 0 CLK2 EN 1 Krdy 1 Busy 1 CLK888 Kvld 1 Busy 0 CLK890 PT Din EncDec 0 Drdy 1 Bus 1 CLK1377
53. 49 X 6 21 6 22 CLK1 RSTn 0 CLK2 EN 1 Drdy 1 Kin K Busy 1 CLK17 Kvld 1 Busy 0 CLK18 Drdy 1 BEncDec 0 Din PT Busy 1 CLK32 Busy 0 Dvld 1 Dout CT CLK33 Drdy 1 EncDec 0
54. 9 Drdy 1 EncDec 0 PT Busy 1 25 Drdy EE EF gi T EN SE UN EncDec MB 5410 CLK1 RSTn 0 CLK2 EN 1 Drdy 1 Kin K Busy 1 CLK41 Busy 0 Kvld 1 CLK42 Drdy 1 EncDec 1 f amp HF THAD Din CT
55. ISE synthesis summary ISE synthesis report lt gt FPGA1 Hierocrypt 3 summary html FPGA1 Hierocrypt 3 syr FPGA1 Hierocrypt 3 map mrp FPGA1 Hierocrypt 3 pwr FPGA1 Hierocrypt 3 twr ISE synthesis summary ISE synthesis report ISE mapping report ISE power analysis report ISE timing report lt MUGD lt gt MUGIsummary html MUGLsyn ISE synthesis summary ISE synthesis report lt gt MUGI summary html MUGI pwr MUGI twr ISE synthesis summary ISE synthesis report ISE mapping report ISE power analysis report ISE timing report MULTI S01 gt gt MULTI S01 summary html MULTI SO1 syr ISE synthesis summary ISE synthesis report lt gt FPGA1 MULTI S01 summary html FPGA1_ MULTI SO1 syr FPGA1 MULTI 801 FPGA1 MULTI SO1 pwr FPGA1 MULTI SO1 twr ISE synthesis summary ISE synthesis report ISE mapping report ISE power analysis report ISE timing report lt SC2000 gt SC2000 summary html SC2000 syr ISE synthesis summary ISE synthesis report lt gt FPGA1_SC2000 summary html FPGA1_SC2000 syr FPGA1 SC2000 map
56. S Ead 479 48 8 MUGI x 8 1 MUGI 82 8 3 p 1 64 1 K I 481 MUGI 0 ao b b 9 b20 b b b b be9 bo0 b P bi b b bu bi9 be DD MD be p Dp b X 8 2 XA 483 p CN w N e pz g n har JE d d E d d d d d b 63 56 b 55 48 b 47 40 b 39 32 bi 31 24 bn 23 16 b 15 8 b 7 0 C CN en e NE 2 49 p F S box MixCloumns 8 4
57. ia map Qualtus II flow report Qualtus II analysis amp synthesis report lt gt CIPHERUNICORN CIPHERUNICORN A map Qualtus II flow report Qualtus II analysis amp synthesis report Hierocrypt 3 gt Hierocrypt 3 flow Hierocrypt 3 map Qualtus II flow report Qualtus II analysis amp synthesis report MUGI MUGI flow Qualtus II flow report MUGLmap Qualtus II analysis amp synthesis report lt MULTI S01 gt MULTI S01 flow MULTI S01 map Qualtus II flow report Qualtus II analysis amp synthesis report lt SC2000 gt SC2000 flow Qualtus flow report SC2000 map Qualtus II analysis amp synthesis report lt Stratix gt AES AES flow Qualtus II flow report AES map Qualtus II analysis amp synthesis report lt gt Camellia flow Camellia map Qualtus II flow report Qualtus II analysis amp synthesis report lt gt CIPHERUNICORN CIPHERUNICORN Qualtus flow report Qualtus II analysis amp synthesis report Hierocrypt 3 gt Hierocrypt 3 flow Hierocrypt 3 map Qualtus II flow report Qualtus II analysis amp synthesis report MUGI MUGI flow Qualtus II flow report MUGI map Qualtus II analysis amp synthesis report lt MULTI S01 gt MULTI S01 flow MULTI S01 map Qualtus
58. is report lt gt FPGA1 Hierocrypt 3 summary html FPGA1 Hierocrypt 3 syr FPGA1 Hierocrypt 3 map mrp FPGA1 Hierocrypt 3 pwr FPGA1 Hierocrypt 3 twr ISE synthesis summary ISE synthesis report ISE mapping report ISE power analysis report ISE timing report lt MUGI gt lt gt MUGI summary html ISE synthesis summary ISE synthesis report lt gt FPGA1 MUGI summary html FPGA1 FPGA1 MUGI map mrp FPGA1 MUGI pwr FPGA1_ MUGI twr ISE synthesis summary ISE synthesis report ISE mapping report ISE power analysis report ISE timing report lt MULTI S01 gt lt gt MULTI S01 summary html MULTI SO1 syr ISE synthesis summary ISE synthesis report lt gt FPGA1 MULTI SO1 summary html FPGAI MULTI SO1 syr ISE synthesis summary ISE synthesis report FPGA1 MULTI S01 map mrp ISE mapping report FPGA1 MULTI SO1 pwr ISE power analysis report FPGA1 MULTI SO1 twr ISE timing report lt SC2000 gt lt gt SC2000 summary html ISE synthesis summary SC2000 syr ISE synthesis report lt gt SC2000 summary html FPGA1_SC2000 syr ISE synthesis summary ISE synthesis report FPGA1 SC2000 ma
59. l 64 A3 4 7 XOR T0 T3 4 8 8 507 53 8 8 8 8 8 8 8 8 8 32 32 32 y y y 4 8 TO T1 T2 T3 24 1 4 9 MT 4 3 12 4 16 8 32 9 72 3 36 LO1 40 MT
60. mrp FPGA1_SC2000 pwr FPGA1_SC2000 twr ISE synthesis summary ISE synthesis report ISE mapping report ISE power analysis report ISE timing report lt 5 gt AES lt gt AES summary html ISE synthesis summary AES syr ISE synthesis report lt gt FPGA1_AES summary html ISE synthesis summary FPGA1 AES syr ISE synthesis report FPGA1 AES map mrp ISE mapping report FPGA1 AES pwr ISE power analysis report FPGA1 AES twr ISE timing report lt gt lt gt Camellia summary html ISE synthesis summary Camellia syr ISE synthesis report lt gt FPGA1 Camellia summary html FPGA1 Camellia syr ISE synthesis summary ISE synthesis report FPGA1 Camellia map mrp ISE mapping report FPGA1 Camellia pwr ISE power analysis report FPGA1 Camellia twr ISE timing report lt gt eu CIPHERUNICORN A summary html CIPHERUNICORN A syr ISE synthesis summary ISE synthesis report lt gt FPGA1_CIPHERUNICORN A summary html FPGA1 A syr ISE synthesis summary ISE synthesis report FPGA1 CIPHERUNICORN A map mrp ISE mapping report FPGA1 CIPHERUNICORN A pwr ISE power analysis report FPGA1 CIPHERUNICORN A twr ISE timing report lt 3 gt lt
61. ng report SC2000 pwr ISE power analysis report SC2000 twr ISE timing report Spartan 6 AES lt gt AES summary html ISE synthesis summary AES syr ISE synthesis report lt gt AES summary html ISE synthesis summary AES syr ISE synthesis report FPGA1 AES map mrp ISE mapping report FPGA1 AES pwr ISE power analysis report FPGA1 AES twr ISE timing report lt Camellia gt lt Camellia summary html Camellia syr ISE synthesis summary ISE synthesis report lt gt FPGA1 Camellia summary html FPGA1 Camellia syr FPGA1 Camellia map mrp FPGA1 Camellia pwr FPGA1 Camellia twr ISE synthesis summary ISE synthesis report ISE mapping report ISE power analysis report ISE timing report CIPHERUNICORN A lt gt CIPHERUNICORN A summary html CIPHERUNICORN A syr ISE synthesis summary ISE synthesis report lt gt FPGA1 CIPHERUNICORN A summary html FPGA1 CIPHERUNICORN FPGA1 CIPHERUNICORN A map mrp FPGA1 CIPHERUNICORN A pwr FPGA1 CIPHERUNICORN A twr ISE synthesis summary ISE synthesis report ISE mapping report ISE power analysis report ISE timing report lt Hierocrypt 3 gt lt gt Hierocrypt 3 summary html Hierocrypt 3 syr ISE synthesis summary ISE synthes
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