国立天文台 殿
Contents
1. 48VAC DC 48V 48V 12VAC DC 12V 12V FANALM FAN FAN FAN 06A032_FPGA 3 LED 4 3 2 13 LED DO 0 1 55555555555555 5 1 HAARAAARAARAAAARA 06A032_ FPGA 4 LED LED2. MAC bit UTC TVR FAN DISP DISP jm DISP FN DISP FN TVR
3. 06A032_FPGA 6 LCD 6 1 VDC 100F LOD Power ON Display System Initialize Firm Boot Up DLYALL CONFIG i FPGA Configulation LED TEST START TEST END 7SEG TEST START LED 7SEG TEST END SYSTEM FILE CHECK Apl mot xxxxxxxx Byte FPGA Configulation FPGA LCD 6 2 06A032_FPGA DISP DISP DISP
4. 3 3 1 3 2 LCD LED VDC 100F 06A032_FPGA 2 2 1 Y SW LED SW LED 13 7 LED LED 12 LED LCD
5. LCD 2 2 06A032 FPGA 2 2 1 48V 48V 5V 48V 5VDC DC 5V 5V 3 3VDC DC 3 3V 3 3V TMP 60 60C STS0 STS1 Ethernet Ethernet Ethernet STS2 Ethernet
6. 1 2 20 1 1 NO MORE OLD COMMAND FN bit jm CORMODE CROSS STATIONX 1234 567 CLKSEL X CORMODE CROSS INIT DATAFMT 512M 2b 1 NO MORE OLD COMMAND INIT 6 06A032_FPGA 3 2 bit 1 1 bit bit 1 X Y
7. DISP y DATAFMT 512M 2B 1 DISP DISP ST YYYYDDDHHMMSS ET YYYYDDDHHMMSS CORSTART SYC IP 255 255 255 255 PORT 60001 60000 SUBNET MASK 255 255 255 255 DISP GATEWAY 000 000 000 000 DISP MACADR 00 08 0C 00 00 99 DISP ELECS CORR UNIT Ver 1 0 DISP CLK 1PPS IP MAC 6 3 06A032 FPGA FN FN TVRSTRT SET 00000000 6 3 1 bit UTC TVR
8. CLK STATUS7 STATUS2 FAN STATUS27 CLK TMP FAN VLID OR 1PPS 1PPS QVALID STATUS27 VALID INVALID INVALID VALID VALID INVALID 10 100
9. Ethernet Ethernet STS3 2 2 3 3V 3 3VDC DC 3 3V 3 3V CLK CLK CLK CLK 2 2 3 1 8VDC DC 1 8V 1 8V 3 3VDC DC 3 3V 3 3V CLK CLK CLK 06A032_FPGA 2 2 4 DipSW SW 1 SW1 3 2 3 4 0ON ADS 1000 0FF 5
10. bit bit 31 3 3V 15 D C 30 1 8V 14 D C 29 Y VALID 13 D C 28 X VALID 12 D C 27 D C 11 NG 26 D C 10 ALM 25 Y CLK CD 5 0V ALN 17 3 3V NG 16 CLK ALM 1 24 X CLK 8 3 3V 23 Y FIFO 7 D C 22 X FIFO 6 D C 21 D C 5 F AN 20 D C 4 F AN 19 D C 3 NG 2 1 0 6 4 FAN TEMPO
11. bit 1 X bit Y bit X bit FN UTC jm X bit 11 013 2 10 036 3 X 00 036 3 01 013 3 11 013 2 10 036 3 Y Y bit 00 036 3 01 013 3 3 3 UTC VSI PDATA X Y FN TVR jm X 2006123123456 X Y 2006123123456 Y 9 4 TVR TVR TVR SET TVR X TVR TVR Y TVR X
12. 6 SW6 8 7 BIT1 lt 3 SW OFF 8 SW1 SW2 SW3 ON ON ON D C ON ON OFF D C ON OFF ON SDRAM ON OFF OFF RS SCIF OFF ON ON RS SCI OFF ON OFF TP OFF OFF ON FLSH OFF OFF OFF CF SW6 SW7 SW8 ON ON ON ON ON OFF DIPSW ON OFF ON SDRAM ON OFF OFF OFF OFF ON ON LCD ON OFF LED OFF OFF ON LED OFF OFF OFF CF 06A032_FPGA 2 3 MDI MDI MI ON so yO MUON Le POWER mv 12V FANALM SW
13. Ether 100BASE T 10BASE T LINK UNLINK LED nl EE I mE E gt LED 1 1 1 ml ml _ LED LED 06A032_FPGA 5 LCD LCD CLK 1PPS IP
14. TVR X Y TVR MSB LSB 1 TVR SET TVR TVR FN TVRSTRT SET TVR X TVR M MSB L LSB TVRSTOP X SET M 00000000L 00000000 SET TVRSTOP Y SET Y TVR lt M 00000000L 00000000 M MSB L LSB 06A032_ FPGA 6 3 5 32bit 8 16 jm STATUS 00000000 bit
15. FAN TEMP1 FAN TEMPO TEMP1
16. 06A032 FPGA FPGA VDC 100F 1 0 18 2006 3 30 06 A032 06A032_FPGA 06 03 30 06A032 FPGA 4 2 UTE 5 2 RN 5 a se edhe be ele a tT hat NR 5 2 2 1 6 2 2 2 6 2 2 3 6 2 2 4 RDipSW 2 7 2 3 8 3 LED pao Da a ad 9 4 10 5 BOD ASNSIOE ALL AYA AN AA Wa a dA TS 11 6 6D 12 12 0 13 1 14 Ti 14 15 98zeEG 2 EE 15 6 984 IVR EEEKANNNANNLNENNNREEEE 15 05895 Oo 16 he a ha er el ea en ye he 16 06A032_ FPGA 1 FPGA VDC 100F
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