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取扱説明書 - 株式会社エンベデッドテクノロジー

1. 1 MPC104 PCMCTIA PC 1 0 4 PCMC I A PC 1 0 4 4 0 2 PC 90 1mmxX 9 5 8 mmO PC104 SRAM ATA
2. 1 1 3 4 COCOM 5
3. S1 IO 8 SG2 1 ON 1 2 3 4 5 6 7 8 Fa ae ae pa eee ee ee le ee ea A8 A9 A10 A11 A12 A13 A14 A15 82 14 T 82 1 82 1 82 1 82 1 82 1 82 1 82 1 SW 0 1 S2 1 2 3 4 5 6 7 8 16E yb7h OFF REA VAF FASB Paar e S ER ore A5 A6 A7 xxxxh t7 xxh Ld SW 0 1 S3 PC IRQ 1 2 3 4 IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ 3 4 5 7 7 LED LED D1
4. 3 JEIDA4 2 PC CARD STANDARD TYPE I M 1 IR3 4 5 7 IO 3 2 8 1 6 PC 5V 3 3V 5V 8 0mA 90 1mmxX95 8mm 12V MPC104 PCMCIA 80mA ON 600mA 1000 F PC 12V 12V 4 laoso snxse BONAR DC D
5. 20 CPU 13 10 MPC104 PCMCIA PC IRQ MODEO0 1 IRQ IRQ3 4 5 7 MODEO 1 TRUE IDE m 10 u sec MODE0 0 TR MODE1 1 Se 10 u sec MODEO x IO MODE1 0 1 83 PC104 IRQ3 IRQ7 2 MODE0 1 I R Q 3 PWR 4 1I NTE I QR 5 1I NTE 1 S 3 I RQ MPC104 PCMCI
6. Alt Status register Device control register Drive Address register A0 A3 CPU CPU A3 0 0 7 A4 A25 1 8 1 8 pp 0 CE1 CE2 High OE CPU IORD High Low WE CPU 10WR High IORD High CPU IORD IOWR High CPU IOWR
7. 2 TZ ATA 70 l FS VPP 12V E n Fa 5V Z fik NT aL 0 l EE 100mS nD This SIV TWH D gt y 21 Q RDY CRES I O OET WH True IDE LET F 1 0 EOR RDY 0 2 1 0 MEOR RDY 0
8. BVD2 R VO True IDE CD1 2 R PWR WP R ON 1 RDY R 0 7 1 IO CPU 0 1 CPU True IDE CPU PIZ
9. bit5 VS1 bit6 VS2 bit7 RESET bit4 bit4 bit4 1 0 0 0 1 INPACK E AME SO als Bil OE OE 3 AIF o 10 9 PCMCIA
10. CD2 bit3 0 BVD1 bit4 bit4 bit4 BVD2 bit5 bit5 ay
11. 0 MODEO MODE1 0 1 17 18 19 T 578 0946 8 8 18 2F TELO06 6224 1137 FAX 06 6224 1138 http www emb tech co jp 20
12. 1 0 1 1 gan IMODE0 1 PCMCIA MODE1 0 MODE0 0 MODE1 0 MODEO0 1 MODE1 1 MODE0 0 MODE1 1 MODE0 1 12 IO True IDE ELE Fa 4 9 4 Offset Address 14H bit7 bit6 Bit5 bit4 Bit3 bit2 bit1 bit0 VS2 VS1 BVD2 BVD1 CD2 CD1 WP RDY Name R W Function VS1 2 R BVD1 R IO True IDE
13. 1O 0 1FH 0 14H CFT OCOH 1 O 0COH ODFH 9 1 Offset Address OH OFH bit7 bit6 bit5 bit4 Bit3 bit2 bit1 bit0 DATA Name R W Function DATA RW 16 4 16 1 3 9 2 1 Offset Address 10H bit7 bit6 bit5 bit4 Bit3 bit2 bit1 bitO CPU 2 Offset Address 11H bit7 bit6 bit5 bit4 Bit3 bit2 bit1 bit0 A15 A14 A13 A12 A11 A10 A9 A8 CPU 3 Of
14. FAL O D2 VPP D3 VCC 8 PCMCIA 1I O True IDE DO D7 CPU D8 D15 CE2 high REM Feature IDE ATA
15. REG 1 1 1 bit0 bit0 bit0 F 0 1 WAIT TOCHRDY 82 2 RDY bitO WP bit1 bit1 16 70 16 1 CD1 bit2 0
16. A W IRQ PCMCIA IRQ3 4 5 7 CPU IRQ IRQ3 4 5 7 CPU 1 83 PC104 TRQ3 IRQ7 14 2 PWR 3 1I NTE 1I QR 4 15 11 PC1 0 4 P 1 NO NO exp eoan o S05 e efe B07 Ao7 SD2 _ Bos Aos spi goglAoglspo BillAiilAEN gizlAnslsAje Bis ais aie _ ml ars sais mslArslsas san P A A K B20 1A20 ISA maz ror Aor saro 22 a22 saos _ B26 a26 saos B27 a27 saos SA03 16 REG MODEO MODE1 IO 0 0 0 FEV ESE 0 0 0 TRUE IDE 1 0 1 w REG MODEO MODE1 IO 0 1 0 1 0 0 TRUE IDE 1 0 1 REG 1
17. C OMANDADA AHK 5 AJAJAJA fee DO 3 211 O o lolo lo gt 0 D7 e Ds D4 lps b2 Di Do olo folo ID7 ID6 ps pa ps jp2 pi po ol 2 pr ID6 ps pa ps D2 pi bo ol foh li 3 p7 D6 ps pa ps jp2 pi po olo hifo 0 4 p7 ID6 ps pa ps jp2 pi po oloh 5 p7 ID6 ps pa ps jp2 pi po olh 6 D7 ID6 ps pa ps jp2 pi po PP Ll pt DS DS DA De D2 DD ol fofo 8 p7 ID6 ps pa ps jp2 pi po Sea ON A17 a16 ephir empe h op1 hop 1 lo f fo VS2 VS1 swz ew CD2 foi P RDY Fil lan i a a FA Da ae a es E ES A a Fi el re ee ee Of IIIITI WR DO D7 8 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W WR WR WR WR RD 6
18. MPC1O4 PCMCIA NII SS 6 7 LED Ke a 8 8 9 PCMCILA 10 11 PC1 OAR RIES OYTO SA NTO ON pp WWW WD 14 16 17 1 1 1 1 2 1 3 1 2
19. fset Address 12H bit7 bit6 bit5 bit4 Bit3 bit2 bit1 bit0 A23 A22 A21 A20 A19 A18 A17 A16 CPU Name R W Function A4 A25 W 4 16 REG W 1 0 11 VO True IDE 1 0 9 3 Offset Address 13H bit7 bit6 bit5 bit4 Bit3 bit2 bit1 bitO VPP PWR INTE CRES MODE1 MODEO CPU Name R W Function VPP PWR INTE W 1 100mS

取扱説明書 - 株式会社エンベデッドテクノロジー

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