Nios II Custom Instruction User Guide
Contents
1. Revisi n aos How to Contact Altera Typographic Conventions rin 2 4 Chapter 1 Nios Il Custom Instruction Overview do Ley Lo q 1 1 Custom Instruction Overview 1 2 Implementing Custom Instruction Hardware 1 2 Implementing Custom Instruction Software Custom Instruction Architectural Types Combinatorial Custom Instruction Architecture 1 5 Combinatorial Port Operation enis 1 6 Multi Cycle Custom Instruction Architecture 1 7 Multi Cycle Port Operation Extended Custom Instruction Architecture Extended Custom Instruction Port Operation Internal Register File Custom Instruction Architecture Internal Register File Custom Instruction Port Operation External Interface Custom Instruction Architecture sese Chapter 2 Software Interface TO Ue tI OE i a RS Custom Instr ction Examples tnihi iia Built In Functions and User Defined Macros Custom Instruction Assembly Software Interface Chapter Implementing a Nios II Custom Ins2. result result valid Altera Corporation May 2007 Multi Cycle Custom Instruction Architecture Multi cycle or sequential custom instructions consist of a logic block that requires two or more clock cycles to complete an operation Additional control ports are required for multi cycle custom instructions See Table 1 3 Figure 1 5 shows the multi cycle custom instruction block diagram Figure 1 5 Multi Cycle Custom Instruction Block Diagram Optional Interface dataa 31 0 datab 31 0 clk clk_en I J done reset start gt P result 31 0 Multi cycle custom instruction can complete in either a fixed or variable number of clock cycles Fixed length You specify the required number of clock cycles during system generation W Variable length The start and done ports are used in a handshaking scheme to determine when the custom instruction execution is complete Nios Il Processor v 7 1 1 7 Nios Il Custom Instruction User Guide Custom Instruction Architectural Types Table 1 3 lists multi cycle custom instruction ports Table 1 3 Multi Cycle Custom Instruction Ports Port Name Direction Required Application clk Input Yes System clock clk_en Input Yes Clock enable reset Input Yes Synchronous reset start Input No Commands custom instruction logic to start execution done Output No Custom instruction logic indicates to the processor tha
3. Prev Next gt Finish 2 If there is a message reporting Interface has no signals click Remove Interfaces With No Signals The message disappears Set the Component Group Name 1 Click Next to display the Component Wizard tab 2 Inthe Component Group text box type Custom Instructions as shown in Figure 3 5 3 6 Nios Il Processor v 7 1 Altera Corporation Nios Il Custom Instruction User Guide May 2007 Implementing a Nios II Custom Instruction Figure 3 5 Component Editor Component Wizard Tab Component Editor leading zero detector File Templates Introduction HDL Files Signals Interfaces Component Wizard b About Component Wizard Folder C ISOPC CustominstructionfniosII_cyclonell_2c35_es2fquartus project rtl Component Name leading zero detector Component Version 10 Component Group Custom Instructions Name Default Value Editable Type Tooltip Parameters Preview the Wizard Component leading zero detector is ok Gre we Con 3 Make sure the bottom pane of the dialog box displays the message Component lt design name gt is ok If it does not review the preceding steps Save the Custom Instruction 1 Click Finish A dialog box states You are about to save design name gt 1 0 to followed by the name of the directory containing the top level HDL file 2 Click Yes to finish importing the custom ins
4. For further information about external interface custom instructions see Custom Instruction Architectural Types on page 14 If your custom instruction hardware requires additional interfaces either to the Avalon MM system interconnect fabric or outside the SOPC Builder system you can specify these interfaces here Most custom instructions use some combination of standard custom instruction ports such as dataa datab and result and do not require any additional interfaces Also custom instructions can be published for later reuse in different projects 1 Click Next to display the Interfaces tab shown in Figure 3 4 on page 3 6 Altera Corporation Nios Il Processor v 7 1 3 5 May 2007 Nios Il Custom Instruction User Guide Implementing Custom Instruction Hardware in SOPC Builder Figure 3 4 Component Editor Interfaces Tab Component Editor leading_zero_detector File Templates Introduction HDL Files Signals Interfaces Component Wizard b About Interfaces nios custom instruction slave nios custom instruction slave 0 1 of 1 Name nios custom instruction slave O Type avalon slave v Nios Custom Instruction Slave Settings Initial Macro Mame instruction name The custom instruction will complete in one clock cycle The custom instruction uses 1 of 255 opcode extensions Add Interface Remove Interfaces With No Signals Component group is blank
5. 3 Inthe Module menu click Edit The Nios II configuration wizard appears Nios Il Processor v 7 1 3 1 Implementing Custom Instruction Hardware in SOPC Builder 4 Select the Custom Instructions page shown in Figure 3 1 Figure 3 1 Nios II Configuration Wizard Custom Instructions Page Nios II Processor cpu O x Nios II Processor Version 7 1 Co os II Caches and Memory Interfaces es Interrupt Vector Clock Cycles Opcode Extension Floating Point Hardware Endian Converter Bitswap 5 Click Import The SOPC Builder component editor appears displaying the Introduction tab 3 2 Nios Il Processor v 7 1 Altera Corporation Nios Il Custom Instruction User Guide May 2007 Implementing a Nios II Custom Instruction Altera Corporation May 2007 Figure 3 2 Component Editor Component Editor untitled File Templates Introduction HDL Fil Signals Interfaces Component Wizard p About HDL Files Top Level File makeis Set HDL File File Name Simulation Files Add Simulation File Remove Simulation File Top Level Module lo HDL Files 2 Component group is blank 5 untitled has no signals JE Your component is not based on HDL An instance of this component will export reversed direction signals to coni lt gt E Add the Top Level HDL File 1 2 Click Next to display the HDL Files
6. Example 2 4 Custom Instruction Macro Usage 1 define void udef_macrol float data 2 define UDEF_MACRO1_N 0x00 3 define UDEF MACROI builtin custom nf UDEF MACRO1 N A 4 define float udef macro2 void data 5 define UDEF MACRO2 0x01 6 define UDEF_MACRO2 builtin custom UDEF MACRO2 B T 8 int main void 9 10 float a 1 789 11 float b 0 0 12 float pt a amp a 13 14 UDEF_MACRO1 a 15 b UDEF_MACRO2 void pt a 16 return 0 17 On lines 2 through 6 the user defined macros are declared and mapped to the appropriate built in functions The macro UDEF_MACRO1 takes a float as an input parameter and does not return anything The macro UDEF_MACRO2 takes a pointer as an input parameter and returns a float Lines 14 and 15 show the use of the two user defined macros Custom The Nios II custom instructions are also accessible in assembly code This section describes the assembly interface Instruction Asse m b ly Custom instructions are R type instructions containing Software E A 6 bit opcode E Three 5 bit register index field interface ee5 bi egiste dex fields Three 1 bit fields for the readra readrb and writerc ports An 8 bit N field used for the custom instruction index opcode extension and optionally including a function select subfield Figure 2 1 on page 2 5 is a diagram of the custom instruction word 2 4
7. For details about writing software for Nios II custom instructions see Chapter 2 Software Interface Nios Il Processor v 7 1 3 9 Nios Il Custom Instruction User Guide Accessing the Custom Instruction from Software 3 10 Nios Il Processor v 7 1 Altera Corporation Nios Il Custom Instruction User Guide May 2007 Appendix A Custom i Instruction Templates Ove rvi ew This section provides VHDL and Verilog HDL custom instruction wrapper file templates that you can reference when writing custom instructions in VHDL and Verilog HDL a You can download the template files from the Altera web site at www altera com nios VHDL Tem p late Sample VHDL template file LIBRARY lt library name USE lt library name gt lt package name gt ALL ENTITY lt entity name gt IS PORT signal clk IN STD LOGIC CPU s master input clk required for multi cycle gt signal reset IN STD LOGIC CPU s master asynchronous reset required for multi cycle gt signal clk_en IN STD_LOGIC Clock qualifier lt required for multi cycle gt signal start IN STD_LOGIC True when this instr issues lt required for multi cycle gt signal done OUT STD LOGIC True when instr completes lt required for variable muli cycle gt signal dataa IN STD_LOGIC VECTOR 31 DOWNTO 0 operand A lt always required gt signal datab IN STD LOGIC VECTOR 31 DOWNTO 0 operand lt optional gt signal IN ST
8. Internal registers accessing custom instructions use readra readrb and writerc to determine if I O takes place between the Nios II processor s register file or an internal register file Additionally ports a b and c specify which internal registers to read from and or write to For example if readra is deasserted that is read from the internal register a provides an index to the internal register file For further details of Nios II custom instruction implementation refer to the Instruction Set Reference chapter of the Nios II Processor Reference Handbook Figure 1 8 shows a simple multiply accumulate custom logic block Figure 1 8 Multiply Accumulate Custom Logic Block dataa 31 0 __ _ gt datab 31 0 readrb Multiply gt Accumulate result 31 0 Altera Corporation May 2007 When readrb is deasserted the logic block multiplies dataa and datab and stores the results in the accumulate register The Nios II processor can read back those results Alternatively the processor can read the value in the accumulator as input to the multiplier by asserting readrb Nios Il Processor v 7 1 1 11 Nios Il Custom Instruction User Guide Custom Instruction Architectural Types Table 1 4 lists the internal register file custom instruction ports Use these optional ports only if the custom instruction functionality requires them Table 1 4 Internal Reg
9. dataa void dataa int datab float datab void datab int datab float datab void datab int datab float datab void datab Altera Corporation May 2007 Appendix C Porting First ANU S RYAN Generation Nios Custom Instructions to Nios Il Systems Overview Hardware Porting Considerations Software Porting Considerations Altera Corporation May 2007 Most first generation Nios custom instructions will port over to a Nios II system with minimal changes This chapter clarifies hardware and software considerations when porting first generation Nios custom instructions to your Nios II system Both combinatorial and multi cycle first generation Nios custom instructions will work with a Nios II system without any changes However because parameterized first generation Nios custom instructions allow a prefix to be passed to the custom instruction logic block parameterized first generation Nios custom instructions require a design change There is no strict definition for the use of prefixes in first generation Nios systems but in most cases the prefix controls the operation performed by the custom instruction However in a Nios II system the prefix option is supported directly by extended custom instructions Therefore any parameterized first generation Nios custom instruction that uses a prefix to control the operation executed by the custom instruction should be ported to a Nios II extended
10. function of the number of operations the custom logic block can perform Extended custom instructions occupy multiple custom instruction indices For example the custom instruction illustrated in Figure 1 7 on page 1 10 occupies 4 indices because n is two bits wide Therefore when this instruction is implemented in Nios II system it leaves 256 4 252 available indices For information about the custom instruction index see Custom Instruction Assembly Software Interface on page 2 4 Extended Custom Instruction Port Operation The n port behaves similarly to the dataa port The processor presents the n port on the rising edge of the clock when start is asserted and the n port remains stable throughout the execution of the custom instruction 1 10 Nios Il Processor v 7 1 Altera Corporation Nios Il Custom Instruction User Guide May 2007 Nios Il Custom Instruction Overview All other custom instruction port operations remain the same Internal Register File Custom Instruction Architecture The Nios II processor allows custom instruction logic to access its own internal register file for I O which provides you the flexibility to specify if the custom instruction reads its operands from the Nios II processor s register file or from the custom instruction s own internal register file In addition a custom instruction can write its results to the local register file rather than the Nios II processor s register file
11. 2007 Verilog HDL Template signal done OUT STD_LOGIC BEGIN Process Statement Concurrent Procedure Call Concurrent Signal Assignment Conditional Signal Assignment Selected Signal Assignment Component Instantiation Statement Generate Statement END a Ve ri log HDL Sample Verilog HDL template file Template Verilog Custom Instruction Template module lt module name gt clk CPU s master input clk lt required for multi cycle gt reset CPU s master asynchronous reset lt required for multi cycle gt clk en Clock qualifier lt required for multi cycle gt start True when this instr issues lt required for multi cycle gt done True when instr completes lt required for variable muli cycle gt dataa operand A lt always required gt datab operand B lt optional gt n N field selector lt required for extended gt a operand A selector lt used for Internal register file access gt b operand b selector lt used for Internal register file access gt E result destination selector lt used for Internal register file access gt readra register file index lt used for Internal register file access gt readrb register file index lt used for Internal register file access gt writerc register file index lt used for Internal register file access gt result result lt always required gt input clk input reset input clk_en input
12. asserted the processor ignores the value driven on the result port other custom instructions port operations remain the same External Interface Custom Instruction Architecture Figure 1 9 shows that the Nios II custom instructions allow you to add an interface to communicate with logic outside of the processor s data path At system generation any interfaces that are not recognized as custom instruction ports propagate out to the top level of the SOPC Builder module where external logic can access the interfaces Nios Il Processor v 7 1 Altera Corporation Nios Il Custom Instruction User Guide May 2007 Nios Il Custom Instruction Overview Because the custom instruction logic is able to access memory external to the processor it extends the capabilities of the custom instruction logic Figure 1 9 Custom Instructions Allow the Addition of an External Interface Optional Interface dataa 31 0 datab 31 0 clk clk_en done reset start m gt result 31 0 Figure 1 9 shows a multi cycle custom instruction that has an external memory interface Custom instruction logic can perform various tasks for example store intermediate results or read memory to control the custom instruction operation The optional external interface also provides a dedicated path for data to flow into or out of the processor For example custom instruction logic can feed data directly from the processor
13. custom instruction Refer to Extended Custom Instruction Architecture on page 1 9 Any other use of the prefix can be accomplished with one of the Nios II custom instruction architecture types Refer to Custom Instruction Architectural Types on page 1 4 All first generation Nios custom instructions will require a small change to application software Assuming no hardware changes i e not a parameterized first generation custom instruction software porting should be nothing more than a search and replace operation The first generation Nios and Nios II system macro definition nomenclature is different therefore first generation Nios macro calls should be replaced by the Nios II macros In the case of parameterized first generation custom instructions additional changes will be required depending on the implementation Refer to Chapter 2 Software Interface Nios Il Processor v 7 1 C 1 Software Porting Considerations C 2 Nios Il Processor v 7 1 Altera Corporation Nios Il Custom Instruction User Guide May 2007
14. dataa and datab ports are optional Include them only if the custom instruction functionality requires input operands If the custom instruction requires only a single input port use dataa Combinatorial Port Operation This section describes the combinatorial custom instruction hardware port operation Figure 1 4 shows the combinatorial custom instruction hardware port timing diagram In Figure 1 4 the processor presents the input data on the dataa and datab ports on the rising edge of the processor clock The processor reads the result porton the rising edge of the following processor clock The Nios II processor issues a combinatorial custom instruction speculatively that is it optimizes execution by issuing the instruction before knowing whether it is necessary and ignores the result if itis not required Therefore a combinatorial custom instruction must not have have side effects In particular a combinatorial custom instruction cannot have an external interface You can further optimize combinatorial custom instructions by implementing the extended custom instruction architecture Refer to Extended Custom Instruction Architecture on page 1 9 1 6 Nios Il Processor v 7 1 Altera Corporation Nios Il Custom Instruction User Guide May 2007 Nios Il Custom Instruction Overview Figure 1 4 Combinatorial Custom Instruction Port Timing Diagram TO 2 dataa dataa valid doa IN
15. int datab void builtin custom nif int n int dataa float datab void builtin custom nip int n int dataa void datab void builtin custom nfi int n float dataa int datab void builtin custom nff int n float dataa float datab void builtin custom nfp int n float dataa void datab void builtin custom npi int n void dataa int datab void builtin custom npf int n void dataa float datab void builtin custom npp int n void dataa void datab int builtin custom in int n int builtin custom ini int n int dataa int builtin custom inf int n float dataa int builtin custom inp int n void dataa int builtin custom inii int n int dataa int datab int builtin custom inif int n int dataa float datab int builtin custom inip int n int dataa void datab int builtin custom infi int n float dataa int datab int builtin custom inff int n float dataa float datab int builtin custom infp int n float dataa void datab int builtin custom inpi int n void dataa int datab int builtin custom inpf int n void dataa float datab int builtin custom inpp int n void dataa void datab Nios Il Processor v 7 1 Built in Functions Returning float loat loat loat loat loat loat loat loat loat loat loat loat loat Built in Functions Returning float Fh Fh Eh Fh Fh Fh Eh Fh Fh Fh Eh Fh Fh void void void void void void void void void void void vo
16. path Standard custom instruction ports plus user defined interface to external logic This section discusses the basic functionality and hardware interface of each custom instruction architecture type listed in Table 1 1 Combinatorial Custom Instruction Architecture Combinatorial custom instruction architecture consists of a logic block that is able to complete in a single clock cycle Figure 1 3 shows a block diagram of a combinatorial custom instruction architecture Figure 1 3 Combinatorial Custom Instruction Architecture dataa 31 0 9 datab 31 0 9 Combinatorial result 31 0 The Figure 1 3 combinatorial custom instruction diagram uses the dataa and datab ports as inputs and drives the results on the result port Because the logic is able to complete in a single clock cycle control ports are not needed Nios II Processor v 7 1 1 5 Nios Il Custom Instruction User Guide Custom Instruction Architectural Types Table 1 2 lists the combinatorial custom instruction ports Table 1 2 Combinatorial Custom Instruction Ports Port Name Direction Required Purpose dataa 31 0 Input No Input operand to custom instruction datab 31 0 Input No Input operand to custom instruction result 31 0 Output Yes Result from custom instruction The only required port for combinatorial custom instructions is the result port The
17. start input readra input readrb input writerc input 7 0 n input 4 0 a input 4 0 b input 4 0 input 31 0 dataa input 31 0 datab output 31 0 result output done Port Declaration Wire Declaration Integer Declaration Concurrent Assignment 2 2 lt Set Version Info Here gt Altera Corporation lt BOOK_TITLE variable gt May 2007 Always Construct endmodule Altera Corporation lt Set Version Info Here gt 2 3 May 2007 lt BOOK_TITLE variable gt Verilog HDL Template 2 4 lt Set Version Info Here gt Altera Corporation lt BOOK_TITLE variable gt May 2007 Appendix Custom Instruction Built In Functions Overview Built In Functions Returning void Built in Functions Returning int Altera Corporation May 2007 The Nios II gcc compiler is customized with built in functions to support custom instructions This section lists the built in functions For more information about gcc built in functions refer to www gnu org Nios custom instruction built in functions are of the following types Returning void Returning int Returning float Returning a pointer void builtin custom n int n void builtin custom ni int n int dataa void builtin custom nf int n float dataa void builtin custom np int n void dataa void builtin custom nii int n int dataa
18. tab shown in Figure 3 2 Click Set HDL File Browse to the directory containing the top level hardware definition language HDL file and select it Click Open The component editor shows the HDL file in the Top Level File list The Quartus II Analyzer checks the design for errors in the background The HDL file list blinks while analysis is taking place When analysis is complete a dialog box reports Info Quartus II Analysis amp Synthesis was successful Click OK Nios Il Processor v 7 1 3 3 Nios Il Custom Instruction User Guide Implementing Custom Instruction Hardware in SOPC Builder Import Simulation Files If you are running the system in ModelSim and you have additional simulation files import them by using the Add Simulation File button Figure 3 3 Component Editor Signals Tab Component Editor leading_zero_detector File Templates DER Introduction HDL Files Signals Interfaces Component Wizard b About Signals Name Interface Signal Type Blresutt avalon slave O export dataa avalon slave 0 v Y Direction put E Component group is blank avalon_slave_0 Slave must have clk signal to specify timing in cycles avalon slave 0 Slave must have a read or write interface or support interrupts lt Prev Next gt Finish Configure the Custom Instruction Ports 1 3 4 Click Next to display the Signals
19. tab shown in Figure 3 3 There are several ports signals listed For the first port carry out the following steps a Select the port b Inthe drop down box under Interface select New nios_custom_instruction slave The component editor creates a new interface nios_custom_instruction_slave_ lt n gt which appears in the drop down box Nios II Processor v 7 1 Nios Il Custom Instruction User Guide Altera Corporation May 2007 Implementing a Nios Custom Instruction The component editor names each Nios II custom instruction sequentially starting with n 0 c Inthe drop down box under Signal Type select the signal type corresponding to the port name For example if the custom instruction hardware presents the result on a port named output you set the type of output to result For further information about signal types see Custom Instruction Architectural Types on page 1 4 3 For each additional port carry out the following steps a Select the port b Inthe drop down box under Interface select nios_custom_instruction_slave_ lt n gt the Nios II custom instruction slave interface you created in step 2 c Inthe drop down box under Signal Type select the signal type corresponding to the port name Set Up Additional Interfaces Exported signal types are considered to be a part of the custom instruction s external interface This section describes how to set up custom interfaces
20. D LOGIC VECTOR 7 DOWNTO 0 N field selector lt required for extended gt signal IN STD LOGIC VECTOR 4 DOWNTO 0 operand A selector used for Internal register file access gt Signal b IN STD LOGIC VECTOR 4 DOWNTO 0 operand selector used for Internal register file access gt signal IN STD LOGIC result destination selector used for Internal register file access gt signal readra IN STD LOGIC register file index used for Internal register file access gt signal readrb IN STD LOGIC register file index used for Internal register file access gt signal writerc IN STD LOGIC register file index lt used for Internal register file access gt signal result OUT STD_LOGIC VECTOR 31 DOWNTO 0 result lt always required gt END entity name ARCHITECTURE a OF lt entity name IS signal clk IN STD LOGIC signal reset IN STD LOGIC signal clk en IN STD LOGIC signal start IN STD LOGIC signal readra IN STD LOGIC signal readrb IN STD LOGIC signal writerc IN STD LOGIC signal IN STD LOGIC VECTOR 7 DOWNTO 0 signal a IN STD LOGIC VECTOR 4 DOWNTO 0 signal b IN STD LOGIC VECTOR 4 DOWNTO 0 signal IN STD LOGIC VECTOR 4 DOWNTO 0 signal dataa IN STD LOGIC VECTOR 31 DOWNTO 0 signal datab IN STD LOGIC VECTOR 31 DOWNTO 0 signal result OUT STD LOGIC VECTOR 31 DOWNTO 0 Altera Corporation lt Set Version Info Here gt 2 1 May
21. Nios II Nios Il Custom Instruction User Guide ANU S RYA o 101 Innovation Drive San Jose CA 95134 408 544 7000 http www altera com Copyright 2007 Altera Corporation All rights reserved Altera The Programmable Solutions Company the stylized Altera logo specific device des ignations and all other words and logos that are identified as trademarks and or service marks are unless noted otherwise the trademarks and service marks of Altera Corporation in the U S and other countries All other product or service names are the property of their respective holders Al tera products are protected under numerous U S and foreign patents and pending applications maskwork rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the ap plication or use of any information product or service described herein except as expressly agreed to in writing by Altera NSAI Corporation Altera customers are advised to obtain the latest version of device specifications before relying on any published in formation and before placing orders for products or services Lip Printed on recycled paper UG N2CSTNST 1 4 LS EN ISO 9001 ii Altera Corporation NOTE YA Contents Pot this User GUIAA sc
22. Nios Il Processor v 7 1 Altera Corporation Nios Il Custom Instruction User Guide May 2007 Software Interface Figure 2 1 Custom Instruction Word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 76543210 uP OPCode Custom readra readrb writerc Instruction Fields A Register index of operand A B Register index of operand B C Register index of operand C N 8 bit number that selects instruction readra 1 if instruction uses rA 0 otherwise readrb 1 if instruction uses rB 0 otherwise writerc 1 if instruction provides result for rC O otherwise Bits 5 0 are the Nios II custom instruction opcode as specified in the Instruction Opcodes section in the Instruction Set Reference chapter of the Nios II Processor Reference Handbook This value appears in every custom instruction The N field bits 13 6 is the custom instruction index The custom instruction index distinguishes between different custom instructions allowing the Nios II processor to support up to 256 distinct custom instructions Depending on the type of custom instruction the N field represents one of the following E A unique custom instruction index for logic that implements a single custom function E An extended custom instruction index for logic that implements several custom functions Example 2 5 shows the assembly language syntax for the custom instruction Example 2 5 Custom Instruction Synt
23. ames dialog box titles checkbox options and dialog box options are shown in bold initial capital letters Example Save As dialog box bold type Italic Type with Initial Capital Letters Italic type External timing parameters directory names project names disk drive names filenames filename extensions and software utility names are shown in bold type Examples fmax qdesigns directory d drive chiptrip gdf file Document titles are shown in italic type with initial capital letters Example AN 75 High Speed Board Design Internal timing parameters and variables are shown in italic type Examples 1 Variable names are enclosed in angle brackets lt gt and shown in italic type Example lt file name gt lt project name gt pof file Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters Examples Delete key the Options menu Subheading Title References to sections within a document and titles of on line help topics are shown in quotation marks Example Typographic Conventions Courier type Signal and port names are shown in lowercase Courier type Examples data1 tdi input Active low signals are denoted by suffix e g resetn Anything that must be typed exactly as it appears is shown in Courier type For example c qdesigns tutorial chiptrip gdf Also sections of an actual file such as a Report File references to
24. ax custom xC XA xB Altera Corporation May 2007 In Example 2 5 N is the custom instruction index xC is the destination for the result 31 0 port xA is the dataa port and xB is the datab port To access the Nios II processor s register file replace x with To access a custom register file replace x with c Nios Il Processor v 7 1 2 5 Nios Il Custom Instruction User Guide Custom Instruction Assembly Software Interface Examples 2 6 and 2 7 show the syntax for two examples of custom instruction assembler calls Example 2 6 Custom Instruction Index 0 custom 0 6 r7 EB Example 2 6 executes a custom instruction with an index of 0 The contents of the Nios II processor registers r7 and r8 are used as input with the results stored in the Nios II processor register r6 Example 2 7 Custom Instruction Index 3 custom 3 cl r2 c4 Example 2 7 executes a custom instruction with an index of 3 The contents of the Nios II processor register r2 and custom register c4 are used as inputs The results are stored in the custom register c1 D For further information about the binary format of custom instructions refer to the Instruction Set Reference chapter of the Nios II Processor Reference Handbook 2 6 Nios Il Processor v 7 1 Altera Corporation Nios Il Custom Instruction User Guide May 2007 3 Implementing a Nios Il S RAYA Custom Instruction Introduction Implementi
25. ement several different operations Extended custom instructions use the N field to specify which operation the logic block performs The N field of the instruction word can be up to eight bits wide allowing a single custom logic block to implement up to 256 different operations Figure 1 7 is a block diagram of an extended custom instruction with bit swap byte swap and half word swap operations Nios Il Processor v 7 1 1 9 Nios Il Custom Instruction User Guide Custom Instruction Architectural Types Figure 1 7 Extended Custom Instruction with Swap Operations dataa 31 0 bit swap operation byte swap operation half word swap operation result 31 0 The custom instruction in Figure 1 7 on page 1 10 performs swap operations on data received at the dataa port It uses the two bit wide n port to select the output from a multiplexer determining which result is presented to the result port Input to the n port comes directly from the N field of the custom instruction word 5 This logic is just a simple example using multiplexer on the output You can implement function selection based on the N field in any way that is appropriate for your application Extended custom instructions can be combinatorial or multi cycle custom instructions To implement an extended custom instruction simply add port to your custom instruction logic The bit width of the n port is a
26. es what the hardware interface looks like Types Table 1 1 shows custom instruction architectural types application and the associated hardware ports Table 1 1 Custom Instruction Architectural Types Application and Hardware Ports Architectural Type Application Hardware Ports Combinatorial Single clock cycle custom logic dataa 31 0 blocks datab 31 0 e result 31 0 Multi cycle Multi clock cycle custom logic block e dataa 31 0 of fixed or variable durations datab 31 0 result 31 0 e clk e clk en eo start reset e done Extended Custom logic blocks that are e dataa 31 0 capable of performing multiple e datab 31 0 operations e result 31 522 0 e clk en O start reset e done e n 7 0 1 4 Nios Il Processor v 7 1 Altera Corporation Nios Il Custom Instruction User Guide May 2007 Nios Il Custom Instruction Overview Table 1 1 Custom Instruction Architectural Types Application and Hardware Ports Architectural Type Application Hardware Ports Internal Register File Custom logic blocks that access internal register files for input and or output dataa 31 0 datab 31 0 result 31 0 clk clk_en start reset done n 7 0 a 4 0 readra b 4 0 readrb c 4 0 writerc External Interface Altera Corporation May 2007 Custom logic blocks that interface to logic outside of the Nios Il processor s data
27. from Software Altera Corporation May 2007 The N port field indicates whether the custom instruction is an extended type In the case of an extended custom instruction this field indicates which bits in the n port serve as the function select Otherwise it displays a dash The Opcode Extension field displays the custom instruction index N field in the instruction word The value appears in both binary and decimal formats For further information about the N field see Custom Instruction Assembly Software Interface on page 2 4 4 Inthe Nios II configuration wizard click Finish to finish adding the custom instruction to the system and return to the SOPC Builder window Generate the SOPC Builder System and Compile in Quartus 11 Software After the custom instruction logic is added to the system you are ready for system generation and Quartus II compilation During system generation SOPC Builder connects the custom logic to the Nios II processor For detailed instructions on generating SOPC Builder systems refer to the Quartus II Handbook Volume 4 SOPC Builder or to the SOPC Builder Help system Adding a custom instruction to a Nios II processor results in a significant change to the SOPC Builder system The next time you run any related Nios II program in the Nios II IDE the IDE rebuilds the software project to accommodate the changes The IDE adds the macros for the custom instruction to the system h header file
28. id void Built in Functions Returning a Pointer B 2 o x builtin custom fn int builtin custom fni int n builtin custom fnf int n builtin custom fnp int builtin custom fnii int builtin custom fnif int builtin custom fnip int builtin custom fnfi int builtin custom fnff int builtin custom fnfp int builtin custom fnpi int builtin custom fnpf int builtin custom fnpp int builtin custom pn int n builtin custom pni int n builtin custom pnf int n builtin custom pnp int n builtin custom pnii int builtin custom pnif int builtin custom pnip int builtin custom pnfi int builtin custom pnff int builtin custom pnfp int builtin custom pnpi int builtin custom pnpf int builtin custom pnpp int Nios II Processor v 7 1 Nios Il Custom Instruction User Guide int dataa float dataa void dataa int dataa int dataa int dataa float dataa float dataa float dataa void dataa void dataa void dataa int datab float datab void datab int datab float datab void datab int datab float datab void datab int dataa float dataa void dataa int dataa int dataa int dataa float dataa float dataa float dataa void dataa void
29. in function names have the following format builtin_custom_ lt return type gt n lt parameter types gt Nios Il Processor v 7 1 Altera Corporation Nios Il Custom Instruction User Guide May 2007 Software Interface Table 2 1 shows 32 bit types supported by custom instructions as parameters and return types as well as the abbreviations used in the built in function name Table 2 1 32 Bit Types Support by Custom Instructions Type Built In Function Abbreviation int i float f void p Example 2 3 shows the prototype definitions for two built in functions Example 2 3 Built in Functions void builtin custom nf int float float builtin custom fnp int void dataa In Example 2 3 the_builtin custom nf function takes an int anda float as inputs and does not return a value In contrast the _builtin custom fnp function takes a pointer as an input and returns a float To support non integer input types define macros with mnemonic names that map to the specific built in function required for the application Refer to Appendix Custom Instruction Built In Functions for detailed information and a list of built in functions Example 2 4 shows user defined custom instruction macros used in an application Altera Corporation Nios Il Processor v 7 1 2 3 May 2007 Nios Il Custom Instruction User Guide Custom Instruction Assembly Software Interface
30. ister File Custom Instruction Ports Port Name Direction Required Application readra Input No If xeadra is high the Nios Il processor supplies dataa and datab If readra is low custom instruction logic reads the internal register file indexed by a readrb Input No If readrb is high the Nios Il processor supplies dataa and datab If readrb is low custom instruction logic reads the internal register file indexed by a writerc Input No Causes custom instruction to write result of to custom instruction internal register file Input Input No Custom instruction internal register file index No Custom instruction internal register file index Input No Custom instruction internal register file index 1 12 Internal Register File Custom Instruction Port Operation The readra readrb writerc and a b and c ports behave similarly to dataa When the start port is asserted the processor presents the readra readrb writerc a b and c ports on the rising edge of the processor clock the ports remain stable throughout the execution of the custom instructions To determine how to handle register file I O custom instruction logic reads the active high readra readrb and writerc ports The logic uses the a b and c ports as register file indexes When readra or readrb are not asserted the custom instruction logic ignores the corresponding a or b port When writerc is not
31. ket header processing and computation intensive applications The Nios II configuration wizard part of the Quartus II software s SOPC Builder provides a graphical user interface GUI used to add up to 256 custom instructions to the Nios II processor The custom instruction logic connects directly to the Nios II arithmetic logic unit ALU as shown in Figure 1 1 Figure 1 1 Custom Instruction Logic Connects to the Nios Il ALU Nios Il Embedded Processor Result Altera Corporation Nios Il Processor v 7 1 1 1 May 2007 Custom Instruction Overview Custom Instruction Overview 1 2 This chapter includes the following information E Description of the Nios II custom instruction feature Requirements for implementing a custom instruction in hardware and software Definition of custom instruction architectural types For information regarding the custom instruction software interface refer to Chapter 2 Software Interface For step by step instructions for implementing a custom instruction see Chapter 3 Implementing a Nios II Custom Instruction With Nios II custom instructions you can take full advantage of the flexibility of FPGAs to meet system performance requirements Custom instructions allow you to add custom functionality to the Nios II processor ALU Nios II custom instructions are custom logic blocks adjacent to the ALU in the processor s data path Custom instruc
32. ng Custom Instruction Hardware in SOPC Builder Altera Corporation May 2007 This chapter describes the process of implementing a Nios II custom instruction with the SOPC Builder component editor The component editor enables you to create new SOPC Builder components including Nios II custom instructions For detailed information about the SOPC Builder component editor refer to the Component Editor chapter of the Quartus II Handbook Volume 4 SOPC Builder Implementing a Nios custom instruction entails the following tasks Open the Component Editor on page 3 1 Add the Top Level HDL File on page 3 3 Import Simulation Files on page 3 4 Configure the Custom Instruction Ports on page 3 4 Set Up Additional Interfaces on page 3 5 Set the Component Group Name on page 3 6 Save the Custom Instruction on page 3 7 Generate the SOPC Builder System and Compile in Quartus II Software on page 3 9 The following sections detail the steps required to carry out these tasks This process imports the custom instruction into the design and adds it to the Nios II processor Open the Component Editor 1 Open the SOPC Builder system S For detailed information about opening and working with SOPC Builder systems refer to the Quartus II Handbook Volume 4 SOPC Builder or to the SOPC Builder Help system 2 Select the Nios II processor in the Altera SOPC Builder System Contents page
33. parts of files e g the AHDL keyword SUBDESIGN as well as logic function names 9 TRI are shown in Courier 1 2 3 and Numbered steps are used in a list of items when the sequence of the items is a b etc important such as the steps listed in a procedure Eos Bullets are used in a list of items when the sequence of the items is not important Y The checkmark indicates a procedure that consists of one step only Es The hand points to information that requires special attention A A caution calls attention to a condition or possible situation that can damage or CAUTION destroy the product or the user s work warning calls attention a condition or possible situation that can cause injury WARNING to the user The angled arrow indicates you should press the Enter key xr The feet direct you to more information on a particular topic 4 Altera Corporation 1 Nios Il Custom Instruction NOTE YA Overview Introduction With the Altera Nios II embedded processor you as the system designer can accelerate time critical software algorithms by adding custom instructions to the Nios II instruction set With custom instructions you can reduce a complex sequence of standard instructions to a single instruction implemented in hardware You can use this feature for a variety of applications for example to optimize software inner loops for digital signal processing DSP pac
34. result port on the same clock cycle that the done port is asserted 1 8 Nios Il Processor v 7 1 Altera Corporation Nios Il Custom Instruction User Guide May 2007 Nios Il Custom Instruction Overview The Nios II system clock feeds the custom logic block s c1k port and the Nios II system s master reset feeds the active high reset port The reset port is asserted only when the whole Nios II system is reset The custom logic block must treat the active high c1k en portas a conventional clock qualifier signal ignoring while c1k enis deasserted Any port in the custom logic block that is not recognized as a custom instruction port is considered to be an external interface You can further optimize multi cycle custom instructions by implementing the extended internal register file or by creating external interface custom instructions Refer to Extended Custom Instruction Architecture on page 1 9 Internal Register File Custom Instruction Architecture on page 1 11 or External Interface Custom Instruction Architecture on page 1 12 Figure 1 6 Multi Cycle Custom Instruction Timing Diagram clk clk_en start reset T1 T2 T3 T4 TS T6 dataal done FA result Altera Corporation May 2007 Extended Custom Instruction Architecture Extended custom instruction architecture allows a single custom logic block to impl
35. s register file to an external first in first out FIFO memory buffer bypassing the processor s data bus Altera Corporation Nios Il Processor v 7 1 1 13 May 2007 Nios Il Custom Instruction User Guide Custom Instruction Architectural Types 1 14 Nios Il Processor v 7 1 Altera Corporation Nios Il Custom Instruction User Guide May 2007 NOTE YA 2 Software Interface Introduction Custom Instruction Examples The Nios II custom instruction software interface abstracts logic implementation details from the application code During the build process the Nios II IDE generates macros that allow easy access from application code to custom instructions This chapter provides custom instruction software interface details including Custom Instruction Examples on page 2 1 Built In Functions and User Defined Macros on page 2 2 Custom Instruction Assembly Software Interface on page 2 4 Example 2 1 shows a portion of the system h header file that defines the macro for a bit swap custom instruction This bit swap example uses one 32 bit input and performs only one function Example 2 1 Bit Swap Macro Definition define ALT CI BSWAP N 0x00 define ALT CI BSWAP A builtin custom ini ALT CI BSWAP Altera Corporation May 2007 In Example 2 1 ALT CI BSWAP Nis defined to be 0x0 which is the custom instruction s index The ALT CI BSWAP A macro is mapped to a b
36. t execution is complete dataa 31 0 Input No Input operand to custom instruction datab 31 0 Input No Input operand to custom instruction result 31 0 Output No Result from custom instruction As indicated in Table 1 3 the clk clk en and reset ports are required for multi cycle custom instructions However the start done dataa datab and result ports are optional Implement them only if the custom instruction functionality specifically needs them Multi Cycle Port Operation The section provides operational details for the multi cycle custom instruction hardware port Figure 1 6 shows the multi cycle custom instruction timing diagram E The processor asserts the active high start port on the first clock cycle of execution when the custom instruction issues through the ALU At this time the dataa and datab ports have valid values and remain valid throughout the duration of the custom instruction execution Fixed or variable length custom instruction port operation e Fixed length The processor asserts start waits a specified number of clock cycles and then reads result For an n cycle operation the custom logic block must present valid data on the n 1 rising edge after the start port is asserted e Variable length The processor waits until the active high done port is asserted The processor reads the result port on the clock edge that done is asserted The custom logic block must present data on the
37. tions give you the ability to tailor the Nios II processor core to meet the needs of a particular application You have the ability to accelerate time critical software algorithms by converting them to custom hardware logic blocks Because it is easy to alter the design of the FPGA based Nios II processor custom instructions provide an easy way to experiment with hardware software tradeoffs at any point in the design process Implementing Custom Instruction Hardware Figure 1 2 is a hardware block diagram of a Nios II custom instruction Nios Il Processor v 7 1 Altera Corporation Nios Il Custom Instruction User Guide May 2007 Nios Il Custom Instruction Overview Altera Corporation May 2007 Figure 1 2 Hardware Block Diagram of a Nios Il Custom Instruction Optional interface to external memory FIFO or other logic dataa 31 0 9 datab 31 0 p Combinatorial Ep result 31 0 ck 0 Multi cycle P done start 7 0 9 Extended 4 0 9 readra b 4 0 9 Internal readrb Register File c 4 0 M9 9 writerc J The basic operation of Nios II custom instruction logic is to receive input on the dataa and or datab port and drive out the result on its result port You generate the custom instruction logic that produces the results The Nios II processor supports different architect
38. truction Intro aah 3 1 Implementing Custom Instruction Hardware in SOPC Builder 3 1 Open the Component Editor Add the Top Level HDL File Import Simulation Files Configure the Custom Instruction Ports sse nennen Set Up Additional Interfaces vinci titur ii eite reed 3 5 Set the Component Group Name ii 3 6 Save the Custom Instruction Generate the SOPC Builder System and Compile in Quartus II Software 3 9 Accessing the Custom Instruction from Software sssssssssseeeeneneteeeeee 3 9 Altera Corporation 1 Nios Il Custom Instruction User Guide Appendix A Custom Instruction Templates Overview VHDL Template Verilog HDL Template Appendix B Custom Instruction Built In Functions A Built In Functions Returning vold eee ee rete irre inca Functions Returning eret endete rette Built in Functions Returning float Built in Functions Returning a Pointer Appendix C Porting First Generation Nios Custom Instructions to Nios Il Systems aaa C JH C 1 Hardware Porting Considerations ertet ntis te etate rne C 1 Software Porting Considerations cinco iii ici C 1 2 Altera Corporation About this User G
39. truction and return to the Nios II configuration wizard 3 Select the new custom instruction and click Add to add it to the Nios II processor As shown in Figure 3 6 after you add the custom instruction to the processor the Name field lists the top level module name Altera Corporation Nios Il Processor v 7 1 3 7 May 2007 Nios Il Custom Instruction User Guide Implementing Custom Instruction Hardware in SOPC Builder Figure 3 6 Altera Nios II Configuration Wizard with Custom Instruction 18 Nios 11 Processor cpu 0 Nios II Processor Megetore Version 7 1 Core Nios II gt Interrupt Vector Name Clock Cycles Opcode Extension Floating Point Hardware leading zero det Combinatorial 00000000 0 leading zero detector Move Up The Clock Cycles field indicates the type of custom instruction combinatorial logic multi cycle extended internal register file or external interface If the custom instruction is a fixed length multi cycle custom instruction you must edit this field to specify the number of clocks You must determine this number based on knowledge of the custom instruction state machine In the case of a variable length multi cycle custom instruction the Clock Cycles field displays Variable 3 8 Nios Il Processor v 7 1 Altera Corporation Nios Il Custom Instruction User Guide May 2007 Implementing a Nios Custom Instruction Accessing the Custom Instruction
40. uide Revision Histo ry The table below displays the revision history for chapters in this User G uide Nios II Custom Instruction User Guide Revision History Chapter Date Version Changes Made 2 May 2007 1 4 Add title and core version number to page footers All May 2007 1 3 Minor corrections to terminology and usage 1 May 2007 1 3 Describe new component editor import flow 3 May 2007 1 3 Remove tutorial design All December 2004 1 2 Updates for the Nios Il version 1 1 release All September 2004 1 1 Updates for the Nios Il version 1 01 release All May 2004 1 0 First release of custom instruction user guide for the Nios II processor How to Contact For the most up to date information about Altera products refer to the Altera following table Information Type Contact 7 Technical support www altera com mysupport Technical training www altera com training custrain O altera com Product literature www altera com literature Altera literature services literature O altera com FTP site ftp altera com Note to table 1 You can also contact your local Altera sales office or sales representative Altera Corporation 3 How to Contact Altera Nios Il Custom Instruction User Guide Typographic Conventions This document uses the typographic conventions shown below Visual Cue Bold Type with Initial Capital Letters Meaning Command n
41. uilt in function that takes a single argument Example 2 2 illustrates a bit swap custom instruction used in application code Nios Il Processor v 7 1 2 1 Built In Functions and User Defined Macros Example 2 2 Bit Swap Instruction Usage include system h int a 0x12345678 al 2 3t 4 int main void 5 6 7 int a swap 0 8 9 a swap ALT CI BSWAP a 10 return 0 11 Built In Functions and User Defined Macros 2 2 In Example 2 2 the system h file is included to define the custom instruction macro definitions The example declares two integers a and a_swap Integer a is passed as input to the bit swap custom instruction with the results loaded into a swap Example 2 2 accommodates most applications using custom instructions The macros defined by the Nios II IDE only make use of C integer types Occasionally applications need to make use of input types other than integers and therefore need to pass expected return values other than integers 5 You can define custom macros for Nios II custom instructions that allow for other 32 bit input types to interface with custom instructions The Nios II processor uses gcc built in functions to map to custom instructions By using built in functions software can use non integer types with custom instructions There are 52 uniquely defined built in functions to accommodate the different combinations of the supported types Built
42. ural types of custom instructions Figure 1 2 lists the additional ports that accommodate different architectural types Only the ports used for the specific custom instruction implementation are required Figure 1 2 also shows an optional interface to external logic The interface to external logic allows you to include a custom interface to system resources outside of the Nios II processor data path Implementing Custom Instruction Software The Nios II custom instruction software interface is simple and abstracts the details of the custom instruction from the programmer For each custom instruction the Nios II integrated development environment IDE generates a macro in the system header file system h You can call the macro from C or C application code as a normal function call and Nios Il Processor v 7 1 1 3 Nios II Custom Instruction User Guide Custom Instruction Architectural Types you do not need to program assembly to access custom instructions Software can also invoke custom instructions in Nios II processor assembly language TTE For more information refer to Chapter 2 Software Interface Custo m There are different custom instruction architectures available to suit the application s requirements The architectures range from a simple single Instruction cycle combinatorial architecture to an extended variable length multi Architectural cycle custom instruction architecture The chosen architecture determin
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